From d8aee1c74a585f045228bace0739ab6abdeea57b Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Mon, 28 Mar 2022 20:15:54 -0400 Subject: å°†mb9x系列BSP并入fujitsu文件夹中 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/action.yml | 8 +- bsp/fujitsu/mb9x/mb9bf500r/CMSIS/SConscript | 19 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.c | 359 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.h | 1166 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmFunc.h | 912 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmInstr.h | 684 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/mb9bf506r.h | 9739 ++++++ bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_gcc.S | 350 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_iar.S | 359 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_rvds.S | 287 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.c | 111 + bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.h | 71 + bsp/fujitsu/mb9x/mb9bf500r/SConscript | 16 + bsp/fujitsu/mb9x/mb9bf500r/SConstruct | 37 + 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| 11 - bsp/mb9bf568r/applications/application.c | 52 - bsp/mb9bf568r/applications/startup.c | 87 - bsp/mb9bf568r/drivers/SConscript | 11 - bsp/mb9bf568r/drivers/board.c | 92 - bsp/mb9bf568r/drivers/board.h | 35 - bsp/mb9bf568r/drivers/led.c | 163 - bsp/mb9bf568r/drivers/mcu.h | 65 - bsp/mb9bf568r/drivers/serial.c | 355 - bsp/mb9bf568r/drivers/serial.h | 96 - bsp/mb9bf568r/project.uvopt | 172 - bsp/mb9bf568r/project.uvproj | 629 - bsp/mb9bf568r/rtconfig.h | 75 - bsp/mb9bf568r/rtconfig.py | 86 - bsp/mb9bf568r/rtthread-mb9bf568r.ld | 221 - bsp/mb9bf568r/rtthread-mb9bf568r.sct | 23 - bsp/mb9bf568r/template.uvopt | 172 - bsp/mb9bf568r/template.uvproj | 398 - .../CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf | Bin 24914 -> 0 bytes .../DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h | 29269 ------------------ .../DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h | 29338 ------------------- .../mb9bf61x/startup/arm/startup_mb9bf61x.S | 333 - .../mb9bf61x/startup/gcc/startup_mb9bf61x.c | 244 - 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@@ jobs: - {RTT_BSP: "loongson/ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "loongson/ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "loongson/ls2kdev", RTT_TOOL_CHAIN: "sourcery-mips"} - - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fujitsu/mb9x/mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fujitsu/mb9x/mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/SConscript b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/SConscript new file mode 100644 index 0000000000..165b344fe8 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +src = Glob('*.c') + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['start_gcc.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['start_rvds.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['start_iar.S'] + +CPPPATH = [GetCurrentDir()] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '') + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.c b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.c new file mode 100644 index 0000000000..f176c3acca --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.c @@ -0,0 +1,359 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.40 + * @date 18. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.h b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.h new file mode 100644 index 0000000000..e062e30606 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cm3.h @@ -0,0 +1,1166 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CM3_H__ +#define __CORE_CM3_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - not yet checked + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + +#include /* Include standard types */ + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + +/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; +#else + uint32_t _reserved0:16; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} APSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; +#else + uint32_t _reserved0:7; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} xPSR_Type; + +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */ + uint32_t _reserved0:29; + } b; + uint32_t w; +} CONTROL_Type; + +/*@}*/ /* end of group CMSIS_ARM_CORE */ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/* ########################## Core Instruction Access ######################### */ +#include "core_cmInstr.h" + +/* ########################### Core Function Access ########################### */ +#include "core_cmFunc.h" + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CORE_CM3_H__ */ + +/*lint -restore */ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmFunc.h b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..b9500f5510 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmFunc.h @@ -0,0 +1,912 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t mainStackPointer) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = mainStackPointer; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ + static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ + return(0); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, psp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" + "BX lr \n" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, msp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" + "BX lr \n" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result=0; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR control, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMFUNC_H__ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmInstr.h b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..e9bbde943d --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/core_cmInstr.h @@ -0,0 +1,684 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __nop + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +#define __WFI __wfi + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +#define __SEV __sev + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +#define __ISB() __isb(0xF) + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +#define __DSB() __dsb(0xF) + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +#define __REV __rev + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +#define __RBIT __rbit + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +#define __STREXB(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +#define __STREXH(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __no_operation + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +/* intrinsic void __ISB(void) (see intrinsics.h */ + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +/* intrinsic void __DSB(void) (see intrinsics.h */ + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +/* intrinsic void __DMB(void) (see intrinsics.h */ + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */ +static uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */ +static uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +static __INLINE void __NOP() { __ASM volatile ("nop"); } + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM volatile ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM volatile ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM volatile ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +static __INLINE void __ISB() { __ASM volatile ("isb"); } + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +static __INLINE void __DSB() { __ASM volatile ("dsb"); } + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +static __INLINE void __DMB() { __ASM volatile ("dmb"); } + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static __INLINE uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +static __INLINE int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static __INLINE uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static __INLINE uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +static __INLINE uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMINSTR_H__ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/mb9bf506r.h b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/mb9bf506r.h new file mode 100644 index 0000000000..68d3e8b362 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/mb9bf506r.h @@ -0,0 +1,9739 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9BF506R */ +/* Version V1.00 */ +/* Date 2011-01-21 */ +/* */ +/************************************************************************/ + +#ifndef _MB9BF506R_H_ +#define _MB9BF506R_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSVC_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + CAN0_IRQn = 32, /* CAN ch.0 */ + CAN1_IRQn = 33, /* CAN ch.1 */ + USBF_IRQn = 34, /* USB Function */ + USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ + /* Reserved = 36, */ + /* Reserved = 37, */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45, /* DMAC ch.7 */ + /* Reserved = 46, */ + /* Reserved = 47, */ +} IRQn_Type; + + +#include "core_cm3.h" +#include "system_mb9bf50x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + __IO uint32_t FASZR; + __IO uint32_t FRWTR; + __IO uint32_t FSTR; + uint8_t RESERVED0[4]; + __IO uint32_t FSYNDN; + uint8_t RESERVED1[236]; + __IO uint32_t CRTRMM; +}FM3_FIF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + __IO uint8_t SCM_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t SCM_STR; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + __IO uint16_t RST_STR; + uint8_t RESERVED2[2]; + __IO uint8_t BSC_PSR; + uint8_t RESERVED3[3]; + __IO uint8_t APBC0_PSR; + uint8_t RESERVED4[3]; + __IO uint8_t APBC1_PSR; + uint8_t RESERVED5[3]; + __IO uint8_t APBC2_PSR; + uint8_t RESERVED6[3]; + __IO uint8_t SWC_PSR; + uint8_t RESERVED7[7]; + __IO uint8_t TTC_PSR; + uint8_t RESERVED8[7]; + __IO uint8_t CSW_TMR; + uint8_t RESERVED9[3]; + __IO uint8_t PSW_TMR; + uint8_t RESERVED10[3]; + __IO uint8_t PLL_CTL1; + uint8_t RESERVED11[3]; + __IO uint8_t PLL_CTL2; + uint8_t RESERVED12[3]; + __IO uint16_t CSV_CTL; + uint8_t RESERVED13[2]; + __IO uint8_t CSV_STR; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + __IO uint8_t DBWDT_CTL; + uint8_t RESERVED18[11]; + __IO uint8_t INT_ENR; + uint8_t RESERVED19[3]; + __IO uint8_t INT_STR; + uint8_t RESERVED20[3]; + __IO uint8_t INT_CLR; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + __IO uint8_t WDG_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + __IO uint8_t WDG_RIS; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + __IO uint8_t WDOGCONTROL; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + __IO uint8_t WDOGRIS; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + __IO uint32_t TIMER1CONTROL; + __IO uint32_t TIMER1INTCLR; + __IO uint32_t TIMER1RIS; + __IO uint32_t TIMER1MIS; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + __IO uint32_t TIMER2CONTROL; + __IO uint32_t TIMER2INTCLR; + __IO uint32_t TIMER2RIS; + __IO uint32_t TIMER2MIS; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + __IO uint16_t TCSA0; + uint8_t RESERVED3[2]; + __IO uint16_t TCSB0; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + __IO uint16_t TCSA1; + uint8_t RESERVED7[2]; + __IO uint16_t TCSB1; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + __IO uint16_t TCSA2; + uint8_t RESERVED11[2]; + __IO uint16_t TCSB2; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + __IO uint8_t OCSA10; + __IO uint8_t OCSB10; + uint8_t RESERVED6[2]; + __IO uint8_t OCSA32; + __IO uint8_t OCSB32; + uint8_t RESERVED7[2]; + __IO uint8_t OCSA54; + __IO uint8_t OCSB54; + uint8_t RESERVED8[3]; + __IO uint8_t OCSC; + uint8_t RESERVED9[50]; + __IO uint8_t OCFS10; + __IO uint8_t OCFS32; + uint8_t RESERVED10[2]; + __IO uint8_t OCFS54; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + __IO uint16_t WFSA10; + uint8_t RESERVED4[2]; + __IO uint16_t WFSA32; + uint8_t RESERVED5[2]; + __IO uint16_t WFSA54; + uint8_t RESERVED6[2]; + __IO uint16_t WFIR; + uint8_t RESERVED7[2]; + __IO uint16_t NZCL; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + __IO uint8_t ICFS10; + __IO uint8_t ICFS32; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + __IO uint8_t ICSA10; + __IO uint8_t ICSB10; + uint8_t RESERVED6[2]; + __IO uint8_t ICSA32; + __IO uint8_t ICSB32; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + __IO uint8_t ACSB; + uint8_t RESERVED7[3]; + __IO uint16_t ACSA; + uint8_t RESERVED8[2]; + __IO uint16_t ATSA; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t TTCR0; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + __IO uint8_t TTCR1; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[203]; + __IO uint16_t TRG; + uint8_t RESERVED11[2]; + __IO uint16_t REVC; + uint8_t RESERVED12[250]; + __IO uint8_t PPGC1; + __IO uint8_t PPGC0; + uint8_t RESERVED13[2]; + __IO uint8_t PPGC3; + __IO uint8_t PPGC2; + uint8_t RESERVED14[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED15[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED18[2]; + __IO uint8_t GATEC0; + uint8_t RESERVED19[39]; + __IO uint8_t PPGC5; + __IO uint8_t PPGC4; + uint8_t RESERVED20[2]; + __IO uint8_t PPGC7; + __IO uint8_t PPGC6; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED25[2]; + __IO uint8_t GATEC4; + uint8_t RESERVED26[39]; + __IO uint8_t PPGC9; + __IO uint8_t PPGC8; + uint8_t RESERVED27[2]; + __IO uint8_t PPGC11; + __IO uint8_t PPGC10; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED32[2]; + __IO uint8_t GATEC8; + uint8_t RESERVED33[39]; + __IO uint8_t PPGC13; + __IO uint8_t PPGC12; + uint8_t RESERVED34[2]; + __IO uint8_t PPGC15; + __IO uint8_t PPGC14; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED39[2]; + __IO uint8_t GATEC12; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL0123; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL4567; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + __IO uint16_t BTSSSR; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t QICR; + struct { + __IO uint8_t QICRL; + __IO uint8_t QICRH; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t QCR; + struct { + __IO uint8_t QCRL; + __IO uint8_t QCRH; + }; + }; + uint8_t RESERVED6[2]; + __IO uint16_t QECR; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + __IO uint8_t ADSR; + __IO uint8_t ADCR; + uint8_t RESERVED0[6]; + __IO uint8_t SFNS; + __IO uint8_t SCCR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t SCFD; + struct { + __IO uint16_t SCFDL; + __IO uint16_t SCFDH; + }; + }; + union { + __IO uint16_t SCIS23; + struct { + __IO uint8_t SCIS2; + __IO uint8_t SCIS3; + }; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t SCIS01; + struct { + __IO uint8_t SCIS0; + __IO uint8_t SCIS1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t PFNS; + __IO uint8_t PCCR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t PCFD; + struct { + __IO uint16_t PCFDL; + __IO uint16_t PCFDH; + }; + }; + __IO uint8_t PCIS; + uint8_t RESERVED5[3]; + __IO uint8_t CMPCR; + uint8_t RESERVED6; + __IO uint16_t CMPD; + union { + __IO uint16_t ADSS23; + struct { + __IO uint8_t ADSS2; + __IO uint8_t ADSS3; + }; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t ADSS01; + struct { + __IO uint8_t ADSS0; + __IO uint8_t ADSS1; + }; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ADST01; + struct { + __IO uint8_t ADST1; + __IO uint8_t ADST0; + }; + }; + uint8_t RESERVED9[2]; + __IO uint8_t ADCT; + uint8_t RESERVED10[3]; + __IO uint8_t PRTSL; + __IO uint8_t SCTSL; + uint8_t RESERVED11[2]; + __IO uint8_t ADCEN; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + __IO uint8_t MCR_PSR; + uint8_t RESERVED0[3]; + __IO uint16_t MCR_FTRM; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + __IO uint16_t ENIR; + uint8_t RESERVED0[2]; + __IO uint16_t EIRR; + uint8_t RESERVED1[2]; + __IO uint16_t EICL; + uint8_t RESERVED2[2]; + __IO uint32_t ELVR; + uint8_t RESERVED3[4]; + __IO uint8_t NMIRR; + uint8_t RESERVED4[3]; + __IO uint8_t NMICL; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + __IO uint32_t DRQSEL; + uint8_t RESERVED0[12]; + __IO uint32_t EXC02MON; + __IO uint32_t IRQ00MON; + __IO uint32_t IRQ01MON; + __IO uint32_t IRQ02MON; + __IO uint32_t IRQ03MON; + __IO uint32_t IRQ04MON; + __IO uint32_t IRQ05MON; + __IO uint32_t IRQ06MON; + __IO uint32_t IRQ07MON; + __IO uint32_t IRQ08MON; + __IO uint32_t IRQ09MON; + __IO uint32_t IRQ10MON; + __IO uint32_t IRQ11MON; + __IO uint32_t IRQ12MON; + __IO uint32_t IRQ13MON; + __IO uint32_t IRQ14MON; + __IO uint32_t IRQ15MON; + __IO uint32_t IRQ16MON; + __IO uint32_t IRQ17MON; + __IO uint32_t IRQ18MON; + __IO uint32_t IRQ19MON; + __IO uint32_t IRQ20MON; + __IO uint32_t IRQ21MON; + __IO uint32_t IRQ22MON; + __IO uint32_t IRQ23MON; + __IO uint32_t IRQ24MON; + __IO uint32_t IRQ25MON; + __IO uint32_t IRQ26MON; + __IO uint32_t IRQ27MON; + __IO uint32_t IRQ28MON; + __IO uint32_t IRQ29MON; + __IO uint32_t IRQ30MON; + __IO uint32_t IRQ31MON; + __IO uint32_t IRQ32MON; + __IO uint32_t IRQ33MON; + __IO uint32_t IRQ34MON; + __IO uint32_t IRQ35MON; + __IO uint32_t IRQ36MON; + __IO uint32_t IRQ37MON; + __IO uint32_t IRQ38MON; + __IO uint32_t IRQ39MON; + __IO uint32_t IRQ40MON; + __IO uint32_t IRQ41MON; + __IO uint32_t IRQ42MON; + __IO uint32_t IRQ43MON; + __IO uint32_t IRQ44MON; + __IO uint32_t IRQ45MON; + __IO uint32_t IRQ46MON; + __IO uint32_t IRQ47MON; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + __IO uint32_t PFR0; + __IO uint32_t PFR1; + __IO uint32_t PFR2; + __IO uint32_t PFR3; + __IO uint32_t PFR4; + __IO uint32_t PFR5; + __IO uint32_t PFR6; + __IO uint32_t PFR7; + __IO uint32_t PFR8; + uint8_t RESERVED0[220]; + __IO uint32_t PCR0; + __IO uint32_t PCR1; + __IO uint32_t PCR2; + __IO uint32_t PCR3; + __IO uint32_t PCR4; + __IO uint32_t PCR5; + __IO uint32_t PCR6; + __IO uint32_t PCR7; + uint8_t RESERVED1[224]; + __IO uint32_t DDR0; + __IO uint32_t DDR1; + __IO uint32_t DDR2; + __IO uint32_t DDR3; + __IO uint32_t DDR4; + __IO uint32_t DDR5; + __IO uint32_t DDR6; + __IO uint32_t DDR7; + __IO uint32_t DDR8; + uint8_t RESERVED2[220]; + __IO uint32_t PDIR0; + __IO uint32_t PDIR1; + __IO uint32_t PDIR2; + __IO uint32_t PDIR3; + __IO uint32_t PDIR4; + __IO uint32_t PDIR5; + __IO uint32_t PDIR6; + __IO uint32_t PDIR7; + __IO uint32_t PDIR8; + uint8_t RESERVED3[220]; + __IO uint32_t PDOR0; + __IO uint32_t PDOR1; + __IO uint32_t PDOR2; + __IO uint32_t PDOR3; + __IO uint32_t PDOR4; + __IO uint32_t PDOR5; + __IO uint32_t PDOR6; + __IO uint32_t PDOR7; + __IO uint32_t PDOR8; + uint8_t RESERVED4[220]; + __IO uint32_t ADE; + uint8_t RESERVED5[124]; + __IO uint32_t SPSR; + uint8_t RESERVED6[124]; + __IO uint32_t EPFR00; + __IO uint32_t EPFR01; + __IO uint32_t EPFR02; + uint8_t RESERVED7[4]; + __IO uint32_t EPFR04; + __IO uint32_t EPFR05; + __IO uint32_t EPFR06; + __IO uint32_t EPFR07; + __IO uint32_t EPFR08; + __IO uint32_t EPFR09; + __IO uint32_t EPFR10; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + __IO uint8_t LVD_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t LVD_STR; + uint8_t RESERVED1[3]; + __IO uint8_t LVD_CLR; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + __IO uint8_t LVD_STR2; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USB clock registers */ +typedef struct +{ + __IO uint8_t UCCR; + uint8_t RESERVED0[3]; + __IO uint8_t UPCR1; + uint8_t RESERVED1[3]; + __IO uint8_t UPCR2; + uint8_t RESERVED2[3]; + __IO uint8_t UPCR3; + uint8_t RESERVED3[3]; + __IO uint8_t UPCR4; + uint8_t RESERVED4[3]; + __IO uint8_t UP_STR; + uint8_t RESERVED5[3]; + __IO uint8_t UPINT_ENR; + uint8_t RESERVED6[3]; + __IO uint8_t UPINT_CLR; + uint8_t RESERVED7[3]; + __IO uint8_t UPINT_STR; + uint8_t RESERVED8[15]; + __IO uint8_t USBEN; +}FM3_USBCLK_TypeDef; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CAN prescaler register */ +typedef struct +{ + __IO uint8_t CANPRE; +}FM3_CANPRE_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + __IO uint8_t CRCCR; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + __IO uint8_t WCRD; + __IO uint8_t WCRL; + __IO uint8_t WCCR; + uint8_t RESERVED0[13]; + __IO uint16_t CLK_SEL; + uint8_t RESERVED1[2]; + __IO uint8_t CLK_EN; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t MODE2; + __IO uint32_t MODE3; + __IO uint32_t MODE4; + __IO uint32_t MODE5; + __IO uint32_t MODE6; + __IO uint32_t MODE7; + __IO uint32_t TIM0; + __IO uint32_t TIM1; + __IO uint32_t TIM2; + __IO uint32_t TIM3; + __IO uint32_t TIM4; + __IO uint32_t TIM5; + __IO uint32_t TIM6; + __IO uint32_t TIM7; + __IO uint32_t AREA0; + __IO uint32_t AREA1; + __IO uint32_t AREA2; + __IO uint32_t AREA3; + __IO uint32_t AREA4; + __IO uint32_t AREA5; + __IO uint32_t AREA6; + __IO uint32_t AREA7; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + __IO uint16_t HCNT; + struct { + __IO uint8_t HCNT0; + __IO uint8_t HCNT1; + }; + }; + uint8_t RESERVED0[2]; + __IO uint8_t HIRQ; + __IO uint8_t HERR; + uint8_t RESERVED1[2]; + __IO uint8_t HSTATE; + __IO uint8_t HFCOMP; + uint8_t RESERVED2[2]; + union { + __IO uint16_t HRTIMER; + struct { + __IO uint8_t HRTIMER0; + __IO uint8_t HRTIMER1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t HRTIMER2; + __IO uint8_t HADR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t HEOF; + struct { + __IO uint8_t HEOF0; + __IO uint8_t HEOF1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t HFRAME; + struct { + __IO uint8_t HFRAME0; + __IO uint8_t HFRAME1; + }; + }; + uint8_t RESERVED6[2]; + __IO uint8_t HTOKEN; + uint8_t RESERVED7[3]; + __IO uint16_t UDCC; + uint8_t RESERVED8[2]; + __IO uint16_t EP0C; + uint8_t RESERVED9[2]; + __IO uint16_t EP1C; + uint8_t RESERVED10[2]; + __IO uint16_t EP2C; + uint8_t RESERVED11[2]; + __IO uint16_t EP3C; + uint8_t RESERVED12[2]; + __IO uint16_t EP4C; + uint8_t RESERVED13[2]; + __IO uint16_t EP5C; + uint8_t RESERVED14[2]; + __IO uint16_t TMSP; + uint8_t RESERVED15[2]; + __IO uint8_t UDCS; + __IO uint8_t UDCIE; + uint8_t RESERVED16[2]; + __IO uint16_t EP0IS; + uint8_t RESERVED17[2]; + __IO uint16_t EP0OS; + uint8_t RESERVED18[2]; + __IO uint16_t EP1S; + uint8_t RESERVED19[2]; + __IO uint16_t EP2S; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + __IO uint16_t EP4S; + uint8_t RESERVED22[2]; + __IO uint16_t EP5S; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + __IO uint32_t DMACR; + uint8_t RESERVED0[12]; + __IO uint32_t DMACA0; + __IO uint32_t DMACB0; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + __IO uint32_t DMACA1; + __IO uint32_t DMACB1; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + __IO uint32_t DMACA2; + __IO uint32_t DMACB2; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + __IO uint32_t DMACA3; + __IO uint32_t DMACB3; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + __IO uint32_t DMACA4; + __IO uint32_t DMACB4; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + __IO uint32_t DMACA5; + __IO uint32_t DMACB5; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + __IO uint32_t DMACA6; + __IO uint32_t DMACB6; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + __IO uint32_t DMACA7; + __IO uint32_t DMACB7; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN channel 0 registers */ +typedef struct +{ + __IO uint16_t CTRLR; + __IO uint16_t STATR; + __IO uint16_t ERRCNT; + __IO uint16_t BTR; + __IO uint16_t INTR; + __IO uint16_t TESTR; + __IO uint16_t BRPER; + uint8_t RESERVED0[2]; + __IO uint16_t IF1CREQ; + __IO uint16_t IF1CMSK; + union { + __IO uint32_t IF1MSK; + struct { + __IO uint16_t IF1MSK1; + __IO uint16_t IF1MSK2; + }; + }; + union { + __IO uint32_t IF1ARB; + struct { + __IO uint16_t IF1ARB1; + __IO uint16_t IF1ARB2; + }; + }; + __IO uint16_t IF1MCTR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + struct { + __IO uint16_t IF1DTA1_L; + __IO uint16_t IF1DTA2_L; + }; + }; + union { + __IO uint32_t IF1DTB_L; + struct { + __IO uint16_t IF1DTB1_L; + __IO uint16_t IF1DTB2_L; + }; + }; + uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + struct { + __IO uint16_t IF1DTA2_B; + __IO uint16_t IF1DTA1_B; + }; + }; + union { + __IO uint32_t IF1DTB_B; + struct { + __IO uint16_t IF1DTB2_B; + __IO uint16_t IF1DTB1_B; + }; + }; + uint8_t RESERVED3[8]; + __IO uint16_t IF2CREQ; + __IO uint16_t IF2CMSK; + union { + __IO uint32_t IF2MSK; + struct { + __IO uint16_t IF2MSK1; + __IO uint16_t IF2MSK2; + }; + }; + union { + __IO uint32_t IF2ARB; + struct { + __IO uint16_t IF2ARB1; + __IO uint16_t IF2ARB2; + }; + }; + __IO uint16_t IF2MCTR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + struct { + __IO uint16_t IF2DTA1_L; + __IO uint16_t IF2DTA2_L; + }; + }; + union { + __IO uint32_t IF2DTB_L; + struct { + __IO uint16_t IF2DTB1_L; + __IO uint16_t IF2DTB2_L; + }; + }; + uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + struct { + __IO uint16_t IF2DTA2_B; + __IO uint16_t IF2DTA1_B; + }; + }; + union { + __IO uint32_t IF2DTB_B; + struct { + __IO uint16_t IF2DTB2_B; + __IO uint16_t IF2DTB1_B; + }; + }; + uint8_t RESERVED6[24]; + union { + __IO uint32_t TREQR; + struct { + __IO uint16_t TREQR1; + __IO uint16_t TREQR2; + }; + }; + uint8_t RESERVED7[12]; + union { + __IO uint32_t NEWDT; + struct { + __IO uint16_t NEWDT1; + __IO uint16_t NEWDT2; + }; + }; + uint8_t RESERVED8[12]; + union { + __IO uint32_t INTPND; + struct { + __IO uint16_t INTPND1; + __IO uint16_t INTPND2; + }; + }; + uint8_t RESERVED9[12]; + union { + __IO uint32_t MSGVAL; + struct { + __IO uint16_t MSGVAL1; + __IO uint16_t MSGVAL2; + }; + }; +}FM3_CAN_TypeDef; + + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ +#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) +#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) +#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) +#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) +#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) +#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) +#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) +#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) +#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) +#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) +#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) +#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) +#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) +#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) +#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) +#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) +#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) +#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) +#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) +#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) +#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) +#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) +#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) +#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) +#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) +#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) +#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) +#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) +#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) +#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) +#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) +#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) +#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) +#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) +#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) +#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) +#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) +#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) +#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) +#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) +#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) +#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) +#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) +#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) +#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) +#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) +#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) +#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) +#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) +#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) +#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) +#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) +#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) +#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) +#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) +#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) +#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) +#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) +#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) +#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) +#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) +#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) +#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) +#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) +#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) +#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) +#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) +#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) +#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) +#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) +#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) +#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) +#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) +#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) +#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) +#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) +#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) +#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) +#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) +#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) +#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) +#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) +#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) +#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) +#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) +#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) +#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) +#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) +#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) +#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) +#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) +#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) +#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) +#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) +#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) +#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) +#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) +#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) +#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) +#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) +#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) +#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) +#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) +#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) +#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) +#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) +#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) +#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +/* CAN prescaler register */ +#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) +#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) +#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) +#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* CAN channel 0 registers */ +#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) +#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) +#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) +#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) +#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) +#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) +#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) +#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) +#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) +#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) +#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) +#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) +#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) +#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) +#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) +#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) +#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) +#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) +#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) +#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) +#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) +#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) +#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) +#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) +#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) +#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) +#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) +#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) +#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) +#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) +#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) +#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) +#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) +#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) +#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) +#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) +#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) +#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) +#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) +#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) +#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) +#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) +#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) +#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) +#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) +#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) +#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) +#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) +#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) +#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) +#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) +#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) +#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) +#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) +#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) +#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) +#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) +#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) +#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) +#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) +#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) +#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) +#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) +#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) +#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) +#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) +#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) +#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) +#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) +#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) +#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) +#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) +#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) +#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) +#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) +#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) +#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) +#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) +#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) +#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) +#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) +#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) +#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) +#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) +#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) +#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) +#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) +#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) +#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) +#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) +#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) +#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) +#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) +#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) +#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) +#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) +#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) +#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) +#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) +#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) +#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) +#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) +#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) +#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) +#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) +#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) +#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) +#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) +#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) +#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) +#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) +#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) +#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) +#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) +#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) + +/* CAN channel 1 registers */ +#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) +#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) +#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) +#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) +#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) +#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) +#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) +#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) +#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) +#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) +#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) +#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) +#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) +#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) +#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) +#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) +#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) +#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) +#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) +#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) +#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) +#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) +#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) +#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) +#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) +#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) +#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) +#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) +#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) +#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) +#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) +#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) +#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) +#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) +#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) +#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) +#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) +#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) +#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) +#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) +#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) +#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) +#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) +#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) +#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) +#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) +#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) +#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) +#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) +#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) +#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) +#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) +#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) +#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) +#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) +#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) +#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) +#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) +#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) +#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) +#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) +#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) +#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) +#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) +#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) +#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) +#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) +#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) +#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) +#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) +#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) +#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) +#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) +#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) +#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) +#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) +#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) +#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) +#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) +#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) +#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) +#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) +#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) +#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) +#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) +#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) +#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) +#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) +#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) +#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) +#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) +#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) +#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) +#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) +#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) +#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) +#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) +#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) +#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) +#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) +#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) +#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) +#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) +#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) +#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) +#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) +#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) +#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) +#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) +#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) +#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) +#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) +#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) +#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) +#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9BF506R_H_ */ + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_gcc.S b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_gcc.S new file mode 100644 index 0000000000..8789adb8f6 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_gcc.S @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-07-01 lgnq first version + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +// .equ Initial_spTop, 0x20000200 +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word CSV_IRQHandler + .word SWDT_IRQHandler + .word LVD_IRQHandler + .word WFG_IRQHandler + .word EXINT0_7_IRQHandler + .word EXINT8_15_IRQHandler + .word DTIM_QDU_IRQHandler + .word MFS0RX_IRQHandler + .word MFS0TX_IRQHandler + .word MFS1RX_IRQHandler + .word MFS1TX_IRQHandler + .word MFS2RX_IRQHandler + .word MFS2TX_IRQHandler + .word MFS3RX_IRQHandler + .word MFS3TX_IRQHandler + .word MFS4RX_IRQHandler + .word MFS4TX_IRQHandler + .word MFS5RX_IRQHandler + .word MFS5TX_IRQHandler + .word MFS6RX_IRQHandler + .word MFS6TX_IRQHandler + .word MFS7RX_IRQHandler + .word MFS7TX_IRQHandler + .word PPG_IRQHandler + .word OSC_PLL_WC_IRQHandler + .word ADC0_IRQHandler + .word ADC1_IRQHandler + .word ADC2_IRQHandler + .word FRTIM_IRQHandler + .word INCAP_IRQHandler + .word OUTCOMP_IRQHandler + .word BTIM_IRQHandler + .word CAN0_IRQHandler + .word CAN1_IRQHandler + .word USBF_IRQHandler + .word USBF_USBH_IRQHandler + .word RESERVED_1_IRQHandler + .word RESERVED_2_IRQHandler + .word DMAC0_IRQHandler + .word DMAC1_IRQHandler + .word DMAC2_IRQHandler + .word DMAC3_IRQHandler + .word DMAC4_IRQHandler + .word DMAC5_IRQHandler + .word DMAC6_IRQHandler + .word DMAC7_IRQHandler + .word RESERVED_3_IRQHandler + .word RESERVED_4_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak CSV_IRQHandler + .thumb_set CSV_IRQHandler,Default_Handler + + .weak SWDT_IRQHandler + .thumb_set SWDT_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak WFG_IRQHandler + .thumb_set WFG_IRQHandler,Default_Handler + + .weak EXINT0_7_IRQHandler + .thumb_set EXINT0_7_IRQHandler,Default_Handler + + .weak EXINT8_15_IRQHandler + .thumb_set EXINT8_15_IRQHandler,Default_Handler + + .weak DTIM_QDU_IRQHandler + .thumb_set DTIM_QDU_IRQHandler,Default_Handler + + .weak MFS0RX_IRQHandler + .thumb_set MFS0RX_IRQHandler,Default_Handler + + .weak MFS0TX_IRQHandler + .thumb_set MFS0TX_IRQHandler,Default_Handler + + .weak MFS1RX_IRQHandler + .thumb_set MFS1RX_IRQHandler,Default_Handler + + .weak MFS1TX_IRQHandler + .thumb_set MFS1TX_IRQHandler,Default_Handler + + .weak MFS2RX_IRQHandler + .thumb_set MFS2RX_IRQHandler,Default_Handler + + .weak MFS2TX_IRQHandler + .thumb_set MFS2TX_IRQHandler,Default_Handler + + .weak MFS3RX_IRQHandler + .thumb_set MFS3RX_IRQHandler,Default_Handler + + .weak MFS3TX_IRQHandler + .thumb_set MFS3TX_IRQHandler,Default_Handler + + .weak MFS4RX_IRQHandler + .thumb_set MFS4RX_IRQHandler,Default_Handler + + .weak MFS4TX_IRQHandler + .thumb_set MFS4TX_IRQHandler,Default_Handler + + .weak MFS5RX_IRQHandler + .thumb_set MFS5RX_IRQHandler,Default_Handler + + .weak MFS5TX_IRQHandler + .thumb_set MFS5TX_IRQHandler,Default_Handler + + .weak MFS6RX_IRQHandler + .thumb_set MFS6RX_IRQHandler,Default_Handler + + .weak MFS6TX_IRQHandler + .thumb_set MFS6TX_IRQHandler,Default_Handler + + .weak MFS7RX_IRQHandler + .thumb_set MFS7RX_IRQHandler,Default_Handler + + .weak MFS7TX_IRQHandler + .thumb_set MFS7TX_IRQHandler,Default_Handler + + .weak PPG_IRQHandler + .thumb_set PPG_IRQHandler,Default_Handler + + .weak OSC_PLL_WC_IRQHandler + .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler + + .weak ADC0_IRQHandler + .thumb_set ADC0_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak FRTIM_IRQHandler + .thumb_set FRTIM_IRQHandler,Default_Handler + + .weak INCAP_IRQHandler + .thumb_set INCAP_IRQHandler,Default_Handler + + .weak OUTCOMP_IRQHandler + .thumb_set OUTCOMP_IRQHandler,Default_Handler + + .weak BTIM_IRQHandler + .thumb_set BTIM_IRQHandler,Default_Handler + + .weak CAN0_IRQHandler + .thumb_set CAN0_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak USBF_IRQHandler + .thumb_set USBF_IRQHandler,Default_Handler + + .weak USBF_USBH_IRQHandler + .thumb_set USBF_USBH_IRQHandler,Default_Handler + + .weak RESERVED_1_IRQHandler + .thumb_set RESERVED_1_IRQHandler,Default_Handler + + .weak RESERVED_2_IRQHandler + .thumb_set RESERVED_2_IRQHandler,Default_Handler + + .weak DMAC0_IRQHandler + .thumb_set DMAC0_IRQHandler,Default_Handler + + .weak DMAC1_IRQHandler + .thumb_set DMAC1_IRQHandler,Default_Handler + + .weak DMAC2_IRQHandler + .thumb_set DMAC2_IRQHandler,Default_Handler + + .weak DMAC3_IRQHandler + .thumb_set DMAC3_IRQHandler,Default_Handler + + .weak DMAC4_IRQHandler + .thumb_set DMAC4_IRQHandler,Default_Handler + + .weak DMAC5_IRQHandler + .thumb_set DMAC5_IRQHandler,Default_Handler + + .weak DMAC6_IRQHandler + .thumb_set DMAC6_IRQHandler,Default_Handler + + .weak DMAC7_IRQHandler + .thumb_set DMAC7_IRQHandler,Default_Handler + + .weak RESERVED_3_IRQHandler + .thumb_set RESERVED_3_IRQHandler,Default_Handler + + .weak RESERVED_4_IRQHandler + .thumb_set RESERVED_4_IRQHandler,Default_Handler + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_iar.S b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_iar.S new file mode 100644 index 0000000000..e60f066822 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_iar.S @@ -0,0 +1,359 @@ +;/* +; * Copyright (c) 2006-2021, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; */ + +#include "rtconfig.h" + + MODULE ?cstartup + +;; ICODE is the same segment as cstartup. By placing __low_level_init +;; in the same segment, we make sure it can be reached with BL. */ + + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) + +#ifdef RT_USING_UART2 + IMPORT MFS2RX_IRQHandler +#endif + PUBLIC __low_level_init + + PUBWEAK SystemInit_ExtMemCtl + SECTION .text:CODE:REORDER(2) + THUMB +SystemInit_ExtMemCtl + BX LR + +__low_level_init: + ;; Initialize hardware. + LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller + MOV R11, LR + BLX R0 + LDR R1, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R1 + MOV R0,#1 + ;; Return with BX to be independent of mode of caller + BX R11 + + ;; Forward declaration of sections. + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD __iar_program_start + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD CSV_IRQHandler ; Clock Super Visor + DCD SWDT_IRQHandler ; Software Watchdog Timer + DCD LVD_IRQHandler ; Low Voltage Detector + DCD WFG_IRQHandler ; Wave Form Generator + DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 + DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 + DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 +#ifdef RT_USING_UART2 + DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 +#else + DCD NULL_IRQHandler ; MultiFunction Serial ch.2 +#endif + DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 + DCD PPG_IRQHandler ; PPG + DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; ADC0 + DCD ADC1_IRQHandler ; ADC1 + DCD ADC2_IRQHandler ; ADC2 + DCD FRTIM_IRQHandler ; Free-run Timer + DCD INCAP_IRQHandler ; Input Capture + DCD OUTCOMP_IRQHandler ; Output Compare + DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; CAN ch.0 + DCD CAN1_IRQHandler ; CAN ch.1 + DCD USBF_IRQHandler ; USB Function + DCD USBF_USBH_IRQHandler ; USB Function / USB HOST + DCD RESERVED_1_IRQHandler ; Reserved_1 + DCD RESERVED_2_IRQHandler ; Reserved_2 + DCD DMAC0_IRQHandler ; DMAC ch.0 + DCD DMAC1_IRQHandler ; DMAC ch.1 + DCD DMAC2_IRQHandler ; DMAC ch.2 + DCD DMAC3_IRQHandler ; DMAC ch.3 + DCD DMAC4_IRQHandler ; DMAC ch.4 + DCD DMAC5_IRQHandler ; DMAC ch.5 + DCD DMAC6_IRQHandler ; DMAC ch.6 + DCD DMAC7_IRQHandler ; DMAC ch.7 + DCD RESERVED_3_IRQHandler ; Reserved_3 + DCD RESERVED_4_IRQHandler ; Reserved_4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + PUBWEAK CSV_IRQHandler + SECTION .text:CODE:REORDER(1) +CSV_IRQHandler + B CSV_IRQHandler + PUBWEAK SWDT_IRQHandler + SECTION .text:CODE:REORDER(1) +SWDT_IRQHandler + B SWDT_IRQHandler + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + PUBWEAK WFG_IRQHandler + SECTION .text:CODE:REORDER(1) +WFG_IRQHandler + B WFG_IRQHandler + PUBWEAK EXINT0_7_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT0_7_IRQHandler + B EXINT0_7_IRQHandler + PUBWEAK EXINT8_15_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT8_15_IRQHandler + B EXINT8_15_IRQHandler + PUBWEAK DTIM_QDU_IRQHandler + SECTION .text:CODE:REORDER(1) +DTIM_QDU_IRQHandler + B DTIM_QDU_IRQHandler + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0RX_IRQHandler + B MFS0RX_IRQHandler + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0TX_IRQHandler + B MFS0TX_IRQHandler + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1RX_IRQHandler + B MFS1RX_IRQHandler + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1TX_IRQHandler + B MFS1TX_IRQHandler + PUBWEAK NULL_IRQHandler + SECTION .text:CODE:REORDER(1) +NULL_IRQHandler + B NULL_IRQHandler + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2TX_IRQHandler + B MFS2TX_IRQHandler + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3RX_IRQHandler + B MFS3RX_IRQHandler + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3TX_IRQHandler + B MFS3TX_IRQHandler + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4RX_IRQHandler + B MFS4RX_IRQHandler + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4TX_IRQHandler + B MFS4TX_IRQHandler + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5RX_IRQHandler + B MFS5RX_IRQHandler + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5TX_IRQHandler + B MFS5TX_IRQHandler + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6RX_IRQHandler + B MFS6RX_IRQHandler + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6TX_IRQHandler + B MFS6TX_IRQHandler + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7RX_IRQHandler + B MFS7RX_IRQHandler + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7TX_IRQHandler + B MFS7TX_IRQHandler + PUBWEAK PPG_IRQHandler + SECTION .text:CODE:REORDER(1) +PPG_IRQHandler + B PPG_IRQHandler + PUBWEAK OSC_PLL_WC_IRQHandler + SECTION .text:CODE:REORDER(1) +OSC_PLL_WC_IRQHandler + B OSC_PLL_WC_IRQHandler + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + PUBWEAK FRTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +FRTIM_IRQHandler + B FRTIM_IRQHandler + PUBWEAK INCAP_IRQHandler + SECTION .text:CODE:REORDER(1) +INCAP_IRQHandler + B INCAP_IRQHandler + PUBWEAK OUTCOMP_IRQHandler + SECTION .text:CODE:REORDER(1) +OUTCOMP_IRQHandler + B OUTCOMP_IRQHandler + PUBWEAK BTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +BTIM_IRQHandler + B BTIM_IRQHandler + PUBWEAK CAN0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN0_IRQHandler + B CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + PUBWEAK USBF_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_IRQHandler + B USBF_IRQHandler + PUBWEAK USBF_USBH_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_USBH_IRQHandler + B USBF_USBH_IRQHandler + PUBWEAK RESERVED_1_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_1_IRQHandler + B RESERVED_1_IRQHandler + PUBWEAK RESERVED_2_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_2_IRQHandler + B RESERVED_2_IRQHandler + PUBWEAK DMAC0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC0_IRQHandler + B DMAC0_IRQHandler + PUBWEAK DMAC1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC1_IRQHandler + B DMAC1_IRQHandler + PUBWEAK DMAC2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC2_IRQHandler + B DMAC2_IRQHandler + PUBWEAK DMAC3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC3_IRQHandler + B DMAC3_IRQHandler + PUBWEAK DMAC4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC4_IRQHandler + B DMAC4_IRQHandler + PUBWEAK DMAC5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC5_IRQHandler + B DMAC5_IRQHandler + PUBWEAK DMAC6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC6_IRQHandler + B DMAC6_IRQHandler + PUBWEAK DMAC7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC7_IRQHandler + B DMAC7_IRQHandler + PUBWEAK RESERVED_3_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_3_IRQHandler + B RESERVED_3_IRQHandler + PUBWEAK RESERVED_4_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_4_IRQHandler + B RESERVED_4_IRQHandler + + END diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_rvds.S b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_rvds.S new file mode 100644 index 0000000000..451f17aa0d --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/start_rvds.S @@ -0,0 +1,287 @@ +; /* +; * Copyright (c) 2006-2021, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2011-02-23 Bernard first implementation +; */ + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0. +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; 32: CAN ch.0 + DCD CAN1_IRQHandler ; 33: CAN ch.1 + DCD USBF_Handler ; 34: USB Function + DCD USB_Handler ; 35: USB Function / USB HOST + DCD DummyHandler ; 36: Reserved + DCD DummyHandler ; 37: Reserved + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD DummyHandler ; 46: Reserved + DCD DummyHandler ; 47: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R1, = __initial_sp ; restore original stack pointer + MSR MSP, R1 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT LVD_Handler [WEAK] + EXPORT MFT_WG_IRQHandler [WEAK] + EXPORT INT0_7_Handler [WEAK] + EXPORT INT8_15_Handler [WEAK] + EXPORT DT_Handler [WEAK] + EXPORT MFS0RX_IRQHandler [WEAK] + EXPORT MFS0TX_IRQHandler [WEAK] + EXPORT MFS1RX_IRQHandler [WEAK] + EXPORT MFS1TX_IRQHandler [WEAK] + EXPORT MFS2RX_IRQHandler [WEAK] + EXPORT MFS2TX_IRQHandler [WEAK] + EXPORT MFS3RX_IRQHandler [WEAK] + EXPORT MFS3TX_IRQHandler [WEAK] + EXPORT MFS4RX_IRQHandler [WEAK] + EXPORT MFS4TX_IRQHandler [WEAK] + EXPORT MFS5RX_IRQHandler [WEAK] + EXPORT MFS5TX_IRQHandler [WEAK] + EXPORT MFS6RX_IRQHandler [WEAK] + EXPORT MFS6TX_IRQHandler [WEAK] + EXPORT MFS7RX_IRQHandler [WEAK] + EXPORT MFS7TX_IRQHandler [WEAK] + EXPORT PPG_Handler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT MFT_FRT_IRQHandler [WEAK] + EXPORT MFT_IPC_IRQHandler [WEAK] + EXPORT MFT_OPC_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBF_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT DMAC0_Handler [WEAK] + EXPORT DMAC1_Handler [WEAK] + EXPORT DMAC2_Handler [WEAK] + EXPORT DMAC3_Handler [WEAK] + EXPORT DMAC4_Handler [WEAK] + EXPORT DMAC5_Handler [WEAK] + EXPORT DMAC6_Handler [WEAK] + EXPORT DMAC7_Handler [WEAK] + EXPORT DummyHandler [WEAK] + +CSV_Handler +SWDT_Handler +LVD_Handler +MFT_WG_IRQHandler +INT0_7_Handler +INT8_15_Handler +DT_Handler +MFS0RX_IRQHandler +MFS0TX_IRQHandler +MFS1RX_IRQHandler +MFS1TX_IRQHandler +MFS2RX_IRQHandler +MFS2TX_IRQHandler +MFS3RX_IRQHandler +MFS3TX_IRQHandler +MFS4RX_IRQHandler +MFS4TX_IRQHandler +MFS5RX_IRQHandler +MFS5TX_IRQHandler +MFS6RX_IRQHandler +MFS6TX_IRQHandler +MFS7RX_IRQHandler +MFS7TX_IRQHandler +PPG_Handler +TIM_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +MFT_FRT_IRQHandler +MFT_IPC_IRQHandler +MFT_OPC_IRQHandler +BT_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBF_Handler +USB_Handler +DMAC0_Handler +DMAC1_Handler +DMAC2_Handler +DMAC3_Handler +DMAC4_Handler +DMAC5_Handler +DMAC6_Handler +DMAC7_Handler +DummyHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + ENDIF + + END diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.c b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.c new file mode 100644 index 0000000000..12f9772e9f --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.c @@ -0,0 +1,111 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user’s obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intention and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.4) */ +/************************************************************************/ + +#include "mb9bf506r.h" + +/* + * 80MHz : Master Clock + */ +const uint32_t SystemFrequency = 80000000UL; + +uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */ +uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */ +uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */ +uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */ +uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */ + +/* + * Prototype of internal function + */ +static void ClockInit(void); +static void HwwdtDisable(void); + + +/* + * Setup the microcontroller system + */ +void SystemInit (void) +{ + HwwdtDisable(); /* Disable Hardware Watchdog */ + ClockInit(); /* Initialize Clock */ +} +/* + * Initialize Clock + */ +static void ClockInit(void) +{ + /*set Main clock stabilization + wait time to 2ms*/ + FM3_CRG->CSW_TMR = 0x79; + /*Enable Main Oscilator*/ + FM3_CRG->SCM_CTL |= 1<<1; + /*Wait stabilization end*/ + while(!(FM3_CRG->SCM_STR & 0x02)); + + /* sub CLK enable */ + //FM3_CRG->SCM_CTL |= 0x08; + //while(!(FM3_CRG->SCM_STR & 0x08)); + + /*Set PLL stabilization + wait time to 512uS*/ + FM3_CRG->PSW_TMR |= 2; + /*Set PLL to 80MHz*/ + FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/ + FM3_CRG->PLL_CTL2 = 19; /*N = 20*/ + /*Enable PLL*/ + FM3_CRG->SCM_CTL |= 0x10; + /*Set bus prescalers*/ + FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/ + FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/ + FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/ + FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/ + /*Wait PLL stabilizatoin end*/ + while(!(FM3_CRG->SCM_STR & 0x10)); + /*Select PLL for main clock*/ + FM3_CRG->SCM_CTL |= 2<<5; + /*Wait PLL to be connected*/ + while((FM3_CRG->SCM_STR & 0xe0) != 0x40); + +} +/* + * Stop HW Watchdog Timer + */ +static void HwwdtDisable(void) +{ + /* UnLock (except WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0x1ACCE551; + /* UnLock (WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0xE5331AAE; + /* Disable WDG */ + FM3_HWWDT->WDG_CTL = 0x00; +} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.h b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.h new file mode 100644 index 0000000000..2750d1efcb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/CMSIS/system_mb9bf50x.h @@ -0,0 +1,71 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ + +#ifndef _SYSTEM_MB9BF50X_H_ +#define _SYSTEM_MB9BF50X_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/SConscript b/bsp/fujitsu/mb9x/mb9bf500r/SConscript new file mode 100644 index 0000000000..2679fc6ce5 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'cpuusage.c'] +src_drv = ['adc.c', 'lcd.c', 'key.c'] + +if GetDepend('RT_USING_RTGUI'): + src_drv += ['info.c'] + +src = src_bsp + src_drv +CPPPATH = [GetCurrentDir()] +CPPDEFINES = [] +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf500r/SConstruct b/bsp/fujitsu/mb9x/mb9bf500r/SConstruct new file mode 100644 index 0000000000..67d8d9c3a5 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/SConstruct @@ -0,0 +1,37 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/CMSIS', duplicate=0) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/fujitsu/mb9x/mb9bf500r/adc.c b/bsp/fujitsu/mb9x/mb9bf500r/adc.c new file mode 100644 index 0000000000..2e431e90c9 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/adc.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq First version + */ + +#include +#include +#include "mb9bf506r.h" +#include "adc.h" +#include "led.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#include +#endif + +static struct rt_device adc; + +static rt_err_t rt_adc_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + /* I/O setting AN08 - P18 */ + FM3_GPIO->ADE |= 0x100; + FM3_GPIO->PFR1 = 0x100; + + /* A/DC setting */ + FM3_ADC0->SCIS1 = 0x01; + FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ + FM3_ADC0->ADST1 = 0x43; + FM3_ADC0->ADCT = 0x02; + FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ + FM3_ADC0->CMPCR = 0x00; /* disable comparator */ + + /* starting A/DC */ + FM3_ADC0->SCCR |= 0x01; /* A/DC start */ + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + return RT_EOK; +} + +static rt_err_t rt_adc_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_ADC_START: + FM3_ADC0->SCCR |= 0x1; + break; + + case RT_DEVICE_CTRL_ADC_RESULT: + while(FM3_ADC0->ADSR & 0x1) + ; + *((rt_uint16_t*)args) = FM3_ADC0->SCFD; + *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; + *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; + break; + } + return RT_EOK; +} + +extern struct rt_messagequeue mq; +extern rt_thread_t info_tid; +rt_uint16_t adc_value; +static void adc_thread_entry(void *parameter) +{ + rt_device_t device; + +#ifdef RT_USING_RTGUI + struct rtgui_event_command ecmd; + + RTGUI_EVENT_COMMAND_INIT(&ecmd); + ecmd.type = RTGUI_CMD_USER_INT; + ecmd.command_id = ADC_UPDATE; +#else + struct lcd_msg msg; +#endif + + device = rt_device_find("adc"); + + while(1) + { + rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); + rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); + pwm_update(adc_value/3); +#ifdef RT_USING_RTGUI + rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); +#else + msg.type = ADC_MSG; + msg.adc_value = adc_value; + rt_mq_send(&mq, &msg, sizeof(msg)); +#endif + rt_thread_delay(20); + } +} + +static rt_thread_t adc_thread; +void rt_hw_adc_init(void) +{ + adc.type = RT_Device_Class_Char; + adc.rx_indicate = RT_NULL; + adc.tx_complete = RT_NULL; + adc.init = rt_adc_init; + adc.open = RT_NULL; + adc.close = RT_NULL; + adc.read = RT_NULL; + adc.write = RT_NULL; + adc.control = rt_adc_control; + adc.user_data = RT_NULL; + + adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); + if(adc_thread != RT_NULL) + rt_thread_startup(adc_thread); + + /* register a character device */ + rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); +} + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/adc.h b/bsp/fujitsu/mb9x/mb9bf500r/adc.h new file mode 100644 index 0000000000..c8846b0beb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/adc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +/* Exported constants ---------------------------------------------------------*/ +/* Exported macro -------------------------------------------------------------*/ +#define ADC_MODE_SINGLE 0x00UL +#define ADC_MODE_SCAN 0x01UL +#define ADC_MODE_TAILGATE 0x02UL + +#define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ +#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ + +#define ADC_UPDATE 0 + +/* Exported functions --------------------------------------------------------- */ +void rt_hw_adc_init(void); + +#endif /*__ADC_H__ */ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/application.c b/bsp/fujitsu/mb9x/mb9bf500r/application.c new file mode 100644 index 0000000000..1cbd0c2d83 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/application.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard the first version + */ + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +#include +#include "board.h" +#include "led.h" +#include "key.h" +#include "adc.h" +#include "lcd.h" +#include "cpuusage.h" + +#ifdef RT_USING_RTGUI +#include +#include +extern void rtgui_startup(); +#endif + +struct rt_messagequeue mq; +static char msg_pool[2048]; + +void rt_init_thread_entry(void *parameter) +{ + rt_device_t lcd; + + rt_hw_led_init(); + rt_hw_key_init(); + rt_hw_adc_init(); + rt_hw_lcd_init(); + rt_hw_cpu_init(); + +#ifdef RT_USING_RTGUI + extern void rtgui_system_server_init(void); + + /* find lcd device */ + lcd = rt_device_find("lcd"); + + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); + + /* init rtgui system server */ + rtgui_system_server_init(); + + /* startup rtgui */ + rtgui_startup(); +#else + { + char buf[20] = {'\0'}; + struct lcd_msg msg; + rt_device_t device; + device = rt_device_find("lcd"); + rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); + x = 1; + y = 1; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); + x = 1; + y = 20; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); + x = 1; + y = 40; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); + + while(1) + { + if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) + { + switch(msg.type) + { + case ADC_MSG: + x = 40; + y = 1; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%04d", msg.adc_value); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case CPU_MSG: + x = 40; + y = 20; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case KEY_MSG: + x = 40; + y = 40; + rt_memset(buf, 0, sizeof(buf)); + switch(msg.key) + { + case KEY_DOWN: + rt_sprintf(buf, "DOWN KEY "); + break; + case KEY_UP: + rt_sprintf(buf, "UP KEY "); + break; + case KEY_RIGHT: + rt_sprintf(buf, "RIGHT KEY"); + break; + case KEY_LEFT: + rt_sprintf(buf, "LEFT KEY "); + break; + case KEY_ENTER: + rt_sprintf(buf, "ENTER KEY"); + break; + default: + rt_sprintf(buf, "NO KEY "); + break; + } + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + } + } + } + } +#endif +} + +int rt_application_init(void) +{ + rt_thread_t init_thread; + + rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); + + init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); + if(init_thread != RT_NULL) + rt_thread_startup(init_thread); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/board.c b/bsp/fujitsu/mb9x/mb9bf500r/board.c new file mode 100644 index 0000000000..f52a5fa3a8 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/board.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" +#include "core_cm3.h" + +extern const uint32_t SystemFrequency; + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** +* This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init() +{ + /* init systick */ + SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND); +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/board.h b/bsp/fujitsu/mb9x/mb9bf500r/board.h new file mode 100644 index 0000000000..2b419c759e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/board.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +//Internal SRAM memory size[Kbytes] <8-64> +//MB9BF500 : 32 +//MB9BF504 : 32 +//MB9BF505 : 48 +//MB9BF506 : 64 +#define FM3_SRAM_SIZE 32 +#define FM3_SRAM_END (0x1FFFC000 + FM3_SRAM_SIZE * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.c b/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.c new file mode 100644 index 0000000000..df8ba2c240 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include +#include "cpuusage.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#include +#endif + +#define CPU_USAGE_CALC_TICK 10 +#define CPU_USAGE_LOOP 100 + +static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; +static rt_uint32_t total_count = 0; + +static void cpu_usage_idle_hook() +{ + rt_tick_t tick; + rt_uint32_t count; + volatile rt_uint32_t loop; + + if (total_count == 0) + { + loop = 0; + + /* get total count */ + rt_enter_critical(); + tick = rt_tick_get(); + while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + total_count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } + rt_exit_critical(); + } + + count = 0; + loop = 0; + /* get CPU usage */ + tick = rt_tick_get(); + while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } + + /* calculate major and minor */ + if (count < total_count) + { + count = total_count - count; + cpu_usage_major = (count * 100) / total_count; + cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; + } + else + { + total_count = count; + + /* no CPU usage */ + cpu_usage_major = 0; + cpu_usage_minor = 0; + } +} + +void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor) +{ + RT_ASSERT(major != RT_NULL); + RT_ASSERT(minor != RT_NULL); + + *major = cpu_usage_major; + *minor = cpu_usage_minor; +} + +void cpu_usage_init() +{ + /* set idle thread hook */ + rt_thread_idle_sethook(cpu_usage_idle_hook); +} +extern struct rt_messagequeue mq; +extern rt_thread_t info_tid; +static void cpu_thread_entry(void *parameter) +{ +#ifdef RT_USING_RTGUI + struct rtgui_event_command ecmd; + + RTGUI_EVENT_COMMAND_INIT(&ecmd); + ecmd.type = RTGUI_CMD_USER_INT; + ecmd.command_id = CPU_UPDATE; +#else + struct lcd_msg msg; +#endif + + while (1) + { +#ifdef RT_USING_RTGUI + rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); +#else + msg.type = CPU_MSG; + msg.major = cpu_usage_major; + msg.minor = cpu_usage_minor; + rt_mq_send(&mq, &msg, sizeof(msg)); +#endif + rt_thread_delay(20); + } +} + +static rt_thread_t cpu_thread; +void rt_hw_cpu_init(void) +{ + cpu_usage_init(); + cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5); + if(cpu_thread != RT_NULL) + rt_thread_startup(cpu_thread); +} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.h b/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.h new file mode 100644 index 0000000000..6a53481f3f --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/cpuusage.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __CPUUSAGE_H__ +#define __CPUUSAGE_H__ + +#define CPU_UPDATE 1 + +void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor); +void rt_hw_cpu_init(void); + +#endif /*__ADC_H__ */ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.ewp b/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.ewp new file mode 100644 index 0000000000..d51d49cf6b --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.ewp @@ -0,0 +1,2027 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + CMSIS + + $PROJ_DIR$\CMSIS\core_cm3.c + + + $PROJ_DIR$\CMSIS\start_iar.S + + + $PROJ_DIR$\CMSIS\system_mb9bf50x.c + + + + FM3 + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\rtm.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + Rtgui + + $PROJ_DIR$\..\..\components\rtgui\widgets\about_view.c + + + $PROJ_DIR$\..\..\components\rtgui\common\asc12font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\asc16font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\blit.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\box.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\button.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\checkbox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\color.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\combobox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\container.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_buffer.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_client.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_hw.c + + + $PROJ_DIR$\..\..\components\rtgui\server\driver.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\filelist_view.c + + + $PROJ_DIR$\..\..\components\rtgui\common\filerw.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_freetype.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_hz_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_hz_file.c + + + $PROJ_DIR$\..\..\components\rtgui\common\framebuffer_driver.c + + + $PROJ_DIR$\..\..\components\rtgui\common\hz12font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\hz16font.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\iconbox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_container.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_hdc.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_jpg.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_png.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_xpm.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\label.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\list_view.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\listbox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\listctrl.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\menu.c + + + $PROJ_DIR$\..\..\components\rtgui\server\mouse.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\notebook.c + + + $PROJ_DIR$\..\..\components\rtgui\server\panel.c + + + $PROJ_DIR$\..\..\components\rtgui\common\pixel_driver.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\progressbar.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\radiobox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\region.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_object.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_system.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_theme.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_xml.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\scrollbar.c + + + $PROJ_DIR$\..\..\components\rtgui\server\server.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\slider.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\staticline.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\textbox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\textview.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\title.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\toplevel.c + + + $PROJ_DIR$\..\..\components\rtgui\server\topwin.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\view.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\widget.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\window.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\workbench.c + + + + Startup + + $PROJ_DIR$\adc.c + + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\cpuusage.c + + + $PROJ_DIR$\info.c + + + $PROJ_DIR$\key.c + + + $PROJ_DIR$\lcd.c + + + $PROJ_DIR$\led.c + + + $PROJ_DIR$\startup.c + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.eww b/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.eww new file mode 100644 index 0000000000..bdaf802ebd --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/fm3_easy_kit.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\fm3_easy_kit.ewp + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.ld b/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.ld new file mode 100644 index 0000000000..3d0151d23b --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.ld @@ -0,0 +1,133 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x0000C000 +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.sct b/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.sct new file mode 100644 index 0000000000..f1a09f4900 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/fm3_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/font.h b/bsp/fujitsu/mb9x/mb9bf500r/font.h new file mode 100644 index 0000000000..92253c59c3 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/font.h @@ -0,0 +1,970 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __FONT_H +#define __FONT_H + +/* Font definition */ +#define ________ 0x00 +#define _______X 0x01 +#define ______X_ 0x02 +#define ______XX 0x03 +#define _____X__ 0x04 +#define _____X_X 0x05 +#define _____XX_ 0x06 +#define _____XXX 0x07 +#define ____X___ 0x08 +#define ____X__X 0x09 +#define ____X_X_ 0x0a +#define ____X_XX 0x0b +#define ____XX__ 0x0c +#define ____XX_X 0x0d +#define ____XXX_ 0x0e +#define ____XXXX 0x0f +#define ___X____ 0x10 +#define ___X___X 0x11 +#define ___X__X_ 0x12 +#define ___X__XX 0x13 +#define ___X_X__ 0x14 +#define ___X_X_X 0x15 +#define ___X_XX_ 0x16 +#define ___X_XXX 0x17 +#define ___XX___ 0x18 +#define ___XX__X 0x19 +#define ___XX_X_ 0x1a +#define ___XX_XX 0x1b +#define ___XXX__ 0x1c +#define ___XXX_X 0x1d +#define ___XXXX_ 0x1e +#define ___XXXXX 0x1f +#define __X_____ 0x20 +#define __X____X 0x21 +#define __X___X_ 0x22 +#define __X___XX 0x23 +#define __X__X__ 0x24 +#define __X__X_X 0x25 +#define __X__XX_ 0x26 +#define __X__XXX 0x27 +#define __X_X___ 0x28 +#define __X_X__X 0x29 +#define __X_X_X_ 0x2a +#define __X_X_XX 0x2b +#define __X_XX__ 0x2c +#define __X_XX_X 0x2d +#define __X_XXX_ 0x2e +#define __X_XXXX 0x2f +#define __XX____ 0x30 +#define __XX___X 0x31 +#define __XX__X_ 0x32 +#define __XX__XX 0x33 +#define __XX_X__ 0x34 +#define __XX_X_X 0x35 +#define __XX_XX_ 0x36 +#define __XX_XXX 0x37 +#define __XXX___ 0x38 +#define __XXX__X 0x39 +#define __XXX_X_ 0x3a +#define __XXX_XX 0x3b +#define __XXXX__ 0x3c +#define __XXXX_X 0x3d +#define __XXXXX_ 0x3e +#define __XXXXXX 0x3f +#define _X______ 0x40 +#define _X_____X 0x41 +#define _X____X_ 0x42 +#define _X____XX 0x43 +#define _X___X__ 0x44 +#define _X___X_X 0x45 +#define _X___XX_ 0x46 +#define _X___XXX 0x47 +#define _X__X___ 0x48 +#define _X__X__X 0x49 +#define _X__X_X_ 0x4a +#define _X__X_XX 0x4b +#define _X__XX__ 0x4c +#define _X__XX_X 0x4d +#define _X__XXX_ 0x4e +#define _X__XXXX 0x4f +#define _X_X____ 0x50 +#define _X_X___X 0x51 +#define _X_X__X_ 0x52 +#define _X_X__XX 0x53 +#define _X_X_X__ 0x54 +#define _X_X_X_X 0x55 +#define _X_X_XX_ 0x56 +#define _X_X_XXX 0x57 +#define _X_XX___ 0x58 +#define _X_XX__X 0x59 +#define _X_XX_X_ 0x5a +#define _X_XX_XX 0x5b +#define _X_XXX__ 0x5c +#define _X_XXX_X 0x5d +#define _X_XXXX_ 0x5e +#define _X_XXXXX 0x5f +#define _XX_____ 0x60 +#define _XX____X 0x61 +#define _XX___X_ 0x62 +#define _XX___XX 0x63 +#define _XX__X__ 0x64 +#define _XX__X_X 0x65 +#define _XX__XX_ 0x66 +#define _XX__XXX 0x67 +#define _XX_X___ 0x68 +#define _XX_X__X 0x69 +#define _XX_X_X_ 0x6a +#define _XX_X_XX 0x6b +#define _XX_XX__ 0x6c +#define _XX_XX_X 0x6d +#define _XX_XXX_ 0x6e +#define _XX_XXXX 0x6f +#define _XXX____ 0x70 +#define _XXX___X 0x71 +#define _XXX__X_ 0x72 +#define _XXX__XX 0x73 +#define _XXX_X__ 0x74 +#define _XXX_X_X 0x75 +#define _XXX_XX_ 0x76 +#define _XXX_XXX 0x77 +#define _XXXX___ 0x78 +#define _XXXX__X 0x79 +#define _XXXX_X_ 0x7a +#define _XXXX_XX 0x7b +#define _XXXXX__ 0x7c +#define _XXXXX_X 0x7d +#define _XXXXXX_ 0x7e +#define _XXXXXXX 0x7f +#define X_______ 0x80 +#define X______X 0x81 +#define X_____X_ 0x82 +#define X_____XX 0x83 +#define X____X__ 0x84 +#define X____X_X 0x85 +#define X____XX_ 0x86 +#define X____XXX 0x87 +#define X___X___ 0x88 +#define X___X__X 0x89 +#define X___X_X_ 0x8a +#define X___X_XX 0x8b +#define X___XX__ 0x8c +#define X___XX_X 0x8d +#define X___XXX_ 0x8e +#define X___XXXX 0x8f +#define X__X____ 0x90 +#define X__X___X 0x91 +#define X__X__X_ 0x92 +#define X__X__XX 0x93 +#define X__X_X__ 0x94 +#define X__X_X_X 0x95 +#define X__X_XX_ 0x96 +#define X__X_XXX 0x97 +#define X__XX___ 0x98 +#define X__XX__X 0x99 +#define X__XX_X_ 0x9a +#define X__XX_XX 0x9b +#define X__XXX__ 0x9c +#define X__XXX_X 0x9d +#define X__XXXX_ 0x9e +#define X__XXXXX 0x9f +#define X_X_____ 0xa0 +#define X_X____X 0xa1 +#define X_X___X_ 0xa2 +#define X_X___XX 0xa3 +#define X_X__X__ 0xa4 +#define X_X__X_X 0xa5 +#define X_X__XX_ 0xa6 +#define X_X__XXX 0xa7 +#define X_X_X___ 0xa8 +#define X_X_X__X 0xa9 +#define X_X_X_X_ 0xaa +#define X_X_X_XX 0xab +#define X_X_XX__ 0xac +#define X_X_XX_X 0xad +#define X_X_XXX_ 0xae +#define X_X_XXXX 0xaf +#define X_XX____ 0xb0 +#define X_XX___X 0xb1 +#define X_XX__X_ 0xb2 +#define X_XX__XX 0xb3 +#define X_XX_X__ 0xb4 +#define X_XX_X_X 0xb5 +#define X_XX_XX_ 0xb6 +#define X_XX_XXX 0xb7 +#define X_XXX___ 0xb8 +#define X_XXX__X 0xb9 +#define X_XXX_X_ 0xba +#define X_XXX_XX 0xbb +#define X_XXXX__ 0xbc +#define X_XXXX_X 0xbd +#define X_XXXXX_ 0xbe +#define X_XXXXXX 0xbf +#define XX______ 0xc0 +#define XX_____X 0xc1 +#define XX____X_ 0xc2 +#define XX____XX 0xc3 +#define XX___X__ 0xc4 +#define XX___X_X 0xc5 +#define XX___XX_ 0xc6 +#define XX___XXX 0xc7 +#define XX__X___ 0xc8 +#define XX__X__X 0xc9 +#define XX__X_X_ 0xca +#define XX__X_XX 0xcb +#define XX__XX__ 0xcc +#define XX__XX_X 0xcd +#define XX__XXX_ 0xce +#define XX__XXXX 0xcf +#define XX_X____ 0xd0 +#define XX_X___X 0xd1 +#define XX_X__X_ 0xd2 +#define XX_X__XX 0xd3 +#define XX_X_X__ 0xd4 +#define XX_X_X_X 0xd5 +#define XX_X_XX_ 0xd6 +#define XX_X_XXX 0xd7 +#define XX_XX___ 0xd8 +#define XX_XX__X 0xd9 +#define XX_XX_X_ 0xda +#define XX_XX_XX 0xdb +#define XX_XXX__ 0xdc +#define XX_XXX_X 0xdd +#define XX_XXXX_ 0xde +#define XX_XXXXX 0xdf +#define XXX_____ 0xe0 +#define XXX____X 0xe1 +#define XXX___X_ 0xe2 +#define XXX___XX 0xe3 +#define XXX__X__ 0xe4 +#define XXX__X_X 0xe5 +#define XXX__XX_ 0xe6 +#define XXX__XXX 0xe7 +#define XXX_X___ 0xe8 +#define XXX_X__X 0xe9 +#define XXX_X_X_ 0xea +#define XXX_X_XX 0xeb +#define XXX_XX__ 0xec +#define XXX_XX_X 0xed +#define XXX_XXX_ 0xee +#define XXX_XXXX 0xef +#define XXXX____ 0xf0 +#define XXXX___X 0xf1 +#define XXXX__X_ 0xf2 +#define XXXX__XX 0xf3 +#define XXXX_X__ 0xf4 +#define XXXX_X_X 0xf5 +#define XXXX_XX_ 0xf6 +#define XXXX_XXX 0xf7 +#define XXXXX___ 0xf8 +#define XXXXX__X 0xf9 +#define XXXXX_X_ 0xfa +#define XXXXX_XX 0xfb +#define XXXXXX__ 0xfc +#define XXXXXX_X 0xfd +#define XXXXXXX_ 0xfe +#define XXXXXXXX 0xff + + + + +const unsigned char FONTTYPE8_8[][8] = { +/* blank */ + { + ________, + ________, + ________, + ________, + ________, + ________, + ________, + ________} + +/* 0 */ + ,{ + __XXX___, + _XX_XX__, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* 1 */ + ,{ + ___XX___, + __XXX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + _XXXXXX_, + ________} + +/* 2 */ + ,{ + _XXXXX__, + XX___XX_, + _____XX_, + ___XXX__, + __XX____, + _XX__XX_, + XXXXXXX_, + ________} + +/* 3 */ + ,{ + _XXXXX__, + XX___XX_, + _____XX_, + __XXXX__, + _____XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 4 */ + ,{ + ___XXX__, + __XXXX__, + _XX_XX__, + XX__XX__, + XXXXXXX_, + ____XX__, + ___XXXX_, + ________} + +/* 5 */ + ,{ + XXXXXXX_, + XX______, + XX______, + XXXXXX__, + _____XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 6 */ + ,{ + __XXX___, + _XX_____, + XX______, + XXXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 7 */ + ,{ + XXXXXXX_, + XX___XX_, + ____XX__, + ___XX___, + __XX____, + __XX____, + __XX____, + ________} + +/* 8 */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 9 */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXXX_, + _____XX_, + ____XX__, + _XXXX___, + ________} + +/* A */ + ,{ + __XXX___, + _XX_XX__, + XX___XX_, + XXXXXXX_, + XX___XX_, + XX___XX_, + XX___XX_, + ________} + +/* B */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX__XX_, + _XX__XX_, + XXXXXX__, + ________} + +/* C */ + ,{ + __XXXX__, + _XX__XX_, + XX______, + XX______, + XX______, + _XX__XX_, + __XXXX__, + ________} + +/* D */ + ,{ + XXXXX___, + _XX_XX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + _XX_XX__, + XXXXX___, + ________} + +/* E */ + ,{ + XXXXXXX_, + _XX___X_, + _XX_X___, + _XXXX___, + _XX_X___, + _XX___X_, + XXXXXXX_, + ________} + +/* F */ + ,{ + XXXXXXX_, + _XX___X_, + _XX_X___, + _XXXX___, + _XX_X___, + _XX_____, + XXXX____, + ________} + +/* G */ + ,{ + __XXXX__, + _XX__XX_, + XX______, + XX______, + XX__XXX_, + _XX__XX_, + __XXX_X_, + ________} + +/* H */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XXXXXXX_, + XX___XX_, + XX___XX_, + XX___XX_, + ________} + +/* I */ + ,{ + __XXXX__, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* J */ + ,{ + ___XXXX_, + ____XX__, + ____XX__, + ____XX__, + XX__XX__, + XX__XX__, + _XXXX___, + ________} + +/* K */ + ,{ + XXX__XX_, + _XX__XX_, + _XX_XX__, + _XXXX___, + _XX_XX__, + _XX__XX_, + XXX__XX_, + ________} + +/* L */ + ,{ + XXXX____, + _XX_____, + _XX_____, + _XX_____, + _XX___X_, + _XX__XX_, + XXXXXXX_, + ________} + +/* M */ + ,{ + XX___XX_, + XXX_XXX_, + XXXXXXX_, + XXXXXXX_, + XX_X_XX_, + XX___XX_, + XX___XX_, + ________} + +/* N */ + ,{ + XX___XX_, + XXX__XX_, + XXXX_XX_, + XX_XXXX_, + XX__XXX_, + XX___XX_, + XX___XX_, + ________} + +/* O */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* P */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* Q */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX__XXX_, + _XXXXX__, + ____XXX_} + +/* R */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_XX__, + _XX__XX_, + XXX__XX_, + ________} + +/* S */ + ,{ + __XXXX__, + _XX__XX_, + __XX____, + ___XX___, + ____XX__, + _XX__XX_, + __XXXX__, + ________} + +/* T */ + ,{ + _XXXXXX_, + _XXXXXX_, + _X_XX_X_, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* U */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* V */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* W */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX_X_XX_, + XX_X_XX_, + XXXXXXX_, + _XX_XX__, + ________} + +/* X */ + ,{ + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + _XX_XX__, + XX___XX_, + XX___XX_, + ________} + +/* Y */ + ,{ + _XX__XX_, + _XX__XX_, + _XX__XX_, + __XXXX__, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* Z */ + ,{ + XXXXXXX_, + XX___XX_, + X___XX__, + ___XX___, + __XX__X_, + _XX__XX_, + XXXXXXX_, + ________} + +/* a */ + ,{ + ________, + ________, + _XXXX___, + ____XX__, + _XXXXX__, + XX__XX__, + _XXX_XX_, + ________} + +/* b */ + ,{ + XXX_____, + _XX_____, + _XXXXX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + XX_XXX__, + ________} + +/* c */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XX______, + XX___XX_, + _XXXXX__, + ________} + +/* d */ + ,{ + ___XXX__, + ____XX__, + _XXXXX__, + XX__XX__, + XX__XX__, + XX__XX__, + _XXX_XX_, + ________} + +/* e */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XXXXXXX_, + XX______, + _XXXXX__, + ________} + +/* f */ + ,{ + __XXXX__, + _XX__XX_, + _XX_____, + XXXXX___, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* g */ + ,{ + ________, + ________, + _XXX_XX_, + XX__XX__, + XX__XX__, + _XXXXX__, + ____XX__, + XXXXX___} + +/* h */ + ,{ + XXX_____, + _XX_____, + _XX_XX__, + _XXX_XX_, + _XX__XX_, + _XX__XX_, + XXX__XX_, + ________} + +/* i */ + ,{ + ___XX___, + ________, + __XXX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* j */ + ,{ + _____XX_, + ________, + _____XX_, + _____XX_, + _____XX_, + _XX__XX_, + _XX__XX_, + __XXXX__} + +/* k */ + ,{ + XXX_____, + _XX_____, + _XX__XX_, + _XX_XX__, + _XXXX___, + _XX_XX__, + XXX__XX_, + ________} + +/* l */ + ,{ + __XXX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* m */ + ,{ + ________, + ________, + XXX_XX__, + XXXXXXX_, + XX_X_XX_, + XX_X_XX_, + XX_X_XX_, + ________} + +/* n */ + ,{ + ________, + ________, + XX_XXX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + _XX__XX_, + ________} + +/* o */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* p */ + ,{ + ________, + ________, + XX_XXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_____, + XXXX____} + +/* q */ + ,{ + ________, + ________, + _XXX_XX_, + XX__XX__, + XX__XX__, + _XXXXX__, + ____XX__, + ___XXXX_} + +/* r */ + ,{ + ________, + ________, + XX_XXX__, + _XXX_XX_, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* s */ + ,{ + ________, + ________, + _XXXXXX_, + XX______, + _XXXXX__, + _____XX_, + XXXXXX__, + ________} + +/* t */ + ,{ + __XX____, + __XX____, + XXXXXX__, + __XX____, + __XX____, + __XX_XX_, + ___XXX__, + ________} + +/* u */ + ,{ + ________, + ________, + XX__XX__, + XX__XX__, + XX__XX__, + XX__XX__, + _XXX_XX_, + ________} + +/* v */ + ,{ + ________, + ________, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* w */ + ,{ + ________, + ________, + XX___XX_, + XX_X_XX_, + XX_X_XX_, + XXXXXXX_, + _XX_XX__, + ________} + +/* x */ + ,{ + ________, + ________, + XX___XX_, + _XX_XX__, + __XXX___, + _XX_XX__, + XX___XX_, + ________} + +/* y */ + ,{ + ________, + ________, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXXX_, + _____XX_, + XXXXXX__} + +/* z */ + ,{ + ________, + ________, + _XXXXXX_, + _X__XX__, + ___XX___, + __XX__X_, + _XXXXXX_, + ________} + +}; + +#endif /* __FONT_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf500r/info.c b/bsp/fujitsu/mb9x/mb9bf500r/info.c new file mode 100644 index 0000000000..fcf514f1b0 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/info.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +#ifdef RT_USING_RTGUI +#include +#include +#include + +#include +#include + +#include "adc.h" +#include "cpuusage.h" + +extern rt_uint16_t adc_value; +static rt_uint8_t index = 0 ; +static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) +{ + if (event->type == RTGUI_EVENT_PAINT) + { + struct rtgui_dc* dc; + struct rtgui_rect rect; + + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rtgui_widget_get_rect(widget, &rect); + + rtgui_dc_fill_rect(dc, &rect); + rect.x2 -= 1; rect.y2 -= 1; + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); + rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); + + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); + rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); + + /* shrink border */ + rtgui_rect_inflate(&rect, -1); + + /* draw text */ + rtgui_widget_get_rect(widget, &rect); + rect.y1 += 25; + rtgui_dc_draw_text(dc, " FM3 Easy Kit Demo", &rect); + rect.y1 += 10; + rtgui_dc_draw_text(dc, " rt-thread / RTGUI", &rect); + rtgui_dc_end_drawing(dc, RT_TRUE); + + return RT_FALSE; + } + else if (event->type == RTGUI_EVENT_KBD) + { + struct rtgui_dc* dc; + struct rtgui_rect rect; + struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; + if (ekbd->type == RTGUI_KEYDOWN) + { + char key_str[16]; + switch (ekbd->key) + { + case RTGUIK_LEFT: + rt_sprintf(key_str, "%s", "L"); + break; + case RTGUIK_RIGHT: + rt_sprintf(key_str, "%s", "R"); + break; + case RTGUIK_DOWN: + rt_sprintf(key_str, "%s", "D"); + break; + case RTGUIK_UP: + rt_sprintf(key_str, "%s", "U"); + break; + default: + rt_sprintf(key_str, "%s", "S"); + break; + } + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rect.x1 = 118; + rect.y1 = 1; + rect.x2 = 127; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + rtgui_dc_draw_text(dc, key_str, &rect); + rtgui_dc_end_drawing(dc, RT_TRUE); + } + else if (ekbd->type == RTGUI_KEYUP) + { + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rect.x1 = 118; + rect.y1 = 1; + rect.x2 = 127; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + //rtgui_dc_draw_text(dc, key_str, &rect); + rtgui_dc_end_drawing(dc, RT_TRUE); + } + } + else if (event->type == RTGUI_EVENT_COMMAND) + { + char str[16]; + struct rtgui_dc* dc; + struct rtgui_rect rect; + struct rtgui_event_command* ecmd; + rt_uint8_t major,minor; + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + + ecmd = (struct rtgui_event_command*)event; + switch (ecmd->command_id) + { + case ADC_UPDATE: + rect.x1 = 1; + rect.y1 = 1; + rect.x2 = 117; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "ADC = %d mv", adc_value); + rtgui_dc_draw_text(dc, str, &rect); + break; + case CPU_UPDATE: + cpu_usage_get(&major, &minor); + rect.x1 = 1; + rect.y1 = 12; + rect.x2 = 127; + rect.y2 = 22; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "CPU : %d.%d%", major, minor); + rtgui_dc_draw_text(dc, str, &rect); + + rect.y1 = 23; + rect.y2 = 63; + index++; + if (index == 127) + { + index = 1; + rtgui_dc_fill_rect(dc, &rect); + } + if (major>40) + rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2); + else + rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2); + break; + } + rtgui_dc_end_drawing(dc, RT_TRUE); + } + + return rtgui_view_event_handler(widget, event); +} + +static void info_entry(void* parameter) +{ + rt_mq_t mq; + struct rtgui_view* view; + struct rtgui_workbench* workbench; + + mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); + rtgui_thread_register(rt_thread_self(), mq); + + workbench = rtgui_workbench_create("info", "workbench"); + if(workbench == RT_NULL) + return; + + view = rtgui_view_create("view"); + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; + RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black; + rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); + + rtgui_workbench_add_view(workbench, view); + /* this view can be focused */ + RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; + /* set widget focus */ + rtgui_widget_focus(RTGUI_WIDGET(view)); + + rtgui_view_show(view, RT_FALSE); + + rtgui_workbench_event_loop(workbench); + + rtgui_thread_deregister(rt_thread_self()); + rt_mq_delete(mq); +} + +rt_thread_t info_tid; +void info_init() +{ + info_tid = rt_thread_create("info", + info_entry, RT_NULL, + 2048, 25, 10); + + if (info_tid != RT_NULL) rt_thread_startup(info_tid); +} + +void rtgui_startup() +{ + rtgui_rect_t rect; + + rtgui_system_server_init(); + + /* register dock panel */ + rect.x1 = 0; + rect.y1 = 0; + rect.x2 = 128; + rect.y2 = 64; + rtgui_panel_register("info", &rect); + rtgui_panel_set_default_focused("info"); + + /*init info workbench */ + info_init(); +} + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/key.c b/bsp/fujitsu/mb9x/mb9bf500r/key.c new file mode 100644 index 0000000000..1886e72974 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/key.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include "key.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#endif + +static void key_io_init(void) +{ + /*Select CPIO function*/ + KEY_PFR &= ~KEY_MASK; + /*Set CPIO Pull-Up function*/ + KEY_PCR |= KEY_MASK; + /*Make button pins inputs*/ + KEY_DDR &= ~KEY_MASK; +} + +static void key_thread_entry(void *parameter) +{ +#ifdef RT_USING_RTGUI + rt_time_t next_delay; + rt_uint8_t i; + + struct rtgui_event_kbd kbd_event; + + key_io_init(); + + /* init keyboard event */ + RTGUI_EVENT_KBD_INIT(&kbd_event); + kbd_event.mod = RTGUI_KMOD_NONE; + kbd_event.unicode = 0; + + while (1) + { + next_delay = RT_TICK_PER_SECOND/10; + kbd_event.key = RTGUIK_UNKNOWN; + kbd_event.type = RTGUI_KEYDOWN; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + for(i=0; ; i++) + { + rt_thread_delay( next_delay ); + if (KEY_ENTER_GETVALUE() == 0) + { + if (i>=4) + { + /* HOME key */ + kbd_event.key = RTGUIK_HOME; + next_delay = RT_TICK_PER_SECOND/5; + break; + } + } + else + { + kbd_event.key = RTGUIK_RETURN; + break; + } + } + } + + if (KEY_DOWN_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_LEFT; + } + + if (kbd_event.key != RTGUIK_UNKNOWN) + { + /* post down event */ + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + else + { + kbd_event.type = RTGUI_KEYUP; + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + /* wait next key press */ + rt_thread_delay(next_delay); + } +#else + extern struct rt_messagequeue mq; + rt_time_t next_delay; + struct lcd_msg msg; + msg.type = KEY_MSG; + + key_io_init(); + + while (1) + { + msg.key = NO_KEY; + + next_delay = RT_TICK_PER_SECOND/10; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + msg.key = KEY_ENTER; + } + + if (KEY_DOWN_GETVALUE() == 0) + { + msg.key = KEY_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + msg.key = KEY_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + msg.key = KEY_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + msg.key = KEY_LEFT; + } + + rt_mq_send(&mq, &msg, sizeof(msg)); + + /* wait next key press */ + rt_thread_delay(next_delay); + } +#endif +} + +static rt_thread_t key_thread; +void rt_hw_key_init(void) +{ + key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); + if (key_thread != RT_NULL) + rt_thread_startup(key_thread); +} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/key.h b/bsp/fujitsu/mb9x/mb9bf500r/key.h new file mode 100644 index 0000000000..45c044c7c0 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/key.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-06 lgnq + */ +#ifndef __KEY_H__ +#define __KEY_H__ + +#include "mb9bf506r.h" + +#define KEY_DOWN (1<<0) +#define KEY_ENTER (1<<1) +#define KEY_LEFT (1<<2) +#define KEY_RIGHT (1<<3) +#define KEY_UP (1<<4) +#define NO_KEY (1<<5) + +#define KEY_MASK (KEY_DOWN | KEY_ENTER | KEY_LEFT | KEY_RIGHT | KEY_UP) +#define KEY_PFR (FM3_GPIO->PFR7) +#define KEY_PCR (FM3_GPIO->PCR7) +#define KEY_PDIR (FM3_GPIO->PDIR7) +#define KEY_DDR (FM3_GPIO->DDR7) + +#define RT_DEVICE_CTRL_KEY_SCAN 0 +#define RT_DEVICE_CTRL_KEY_STATUS 1 + +#define SET_BIT(byte, bit) ((byte) |= (1<<(bit))) +#define CLR_BIT(byte, bit) ((byte) &= ~(1<<(bit))) +#define TST_BIT(byte, bit) (((byte) & (1<<(bit)))?1:0) + +#define KEY_ENTER_GETVALUE() TST_BIT(KEY_PDIR, 1) +#define KEY_DOWN_GETVALUE() TST_BIT(KEY_PDIR, 0) +#define KEY_UP_GETVALUE() TST_BIT(KEY_PDIR, 4) +#define KEY_RIGHT_GETVALUE() TST_BIT(KEY_PDIR, 3) +#define KEY_LEFT_GETVALUE() TST_BIT(KEY_PDIR, 2) + +void rt_hw_key_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/lcd.c b/bsp/fujitsu/mb9x/mb9bf500r/lcd.c new file mode 100644 index 0000000000..8b61abf2e0 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/lcd.c @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-05 lgnq ZYMG12864C3 LCD driver + */ + +#include +#include "lcd.h" +#include "font.h" + +static struct rt_device_graphic_info _lcd_info; +static rt_uint8_t gui_disp_buf[GUI_LCM_YMAX/8][GUI_LCM_XMAX]; +const unsigned char BIT_MASK[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; +/* simple font: ' ', '0'~'9','a'~'z','A'~'Z' */ +extern const unsigned char FONTTYPE8_8[][8]; + +rt_uint32_t x; +rt_uint32_t y; + +void power_delay(void) +{ + rt_uint32_t i = 0x4ffff; + while(i--) + ; +} + +void delay(void) +{ + rt_uint8_t i = 0x8; + while(i--) + ; +} + +void reset_delay(void) +{ + rt_uint8_t i = 0xff; + while(i--) + ; +} + +void lcd_write_cmd(unsigned char command) +{ + rt_uint8_t i; + + LCD_PS_LOW(); + LCD_CS_LOW(); + LCD_CD_LOW(); + for (i=0; i<8; i++) + { + if (command & (0x80 >> i)) + LCD_DATA_HIGH(); + else + LCD_DATA_LOW(); + + LCD_CLK_LOW(); + delay(); + LCD_CLK_HIGH(); + delay(); + } + LCD_CS_HIGH(); +} + +void lcd_write_data(unsigned char data) +{ + rt_uint8_t i; + + LCD_PS_LOW(); + LCD_CS_LOW(); + LCD_CD_HIGH(); + for (i=0; i<8; i++) + { + if (data & (0x80 >> i)) + LCD_DATA_HIGH(); + else + LCD_DATA_LOW(); + + LCD_CLK_LOW(); + delay(); + LCD_CLK_HIGH(); + delay(); + } + LCD_CS_HIGH(); +} + +#ifdef RT_USING_RTGUI +#include +#include + +static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) +{ + rt_uint8_t i,j = GUI_LCM_XMAX; + rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; + + for (i=0; i> 4; + lcd_write_cmd(SET_PAGE_ADDR_0 | page); + lcd_write_cmd(SET_COLH_ADDR_0 | colh); + lcd_write_cmd(SET_COLL_ADDR_0 | coll); + lcd_write_data(gui_disp_buf[page][i]); + } +} + +const struct rtgui_graphic_driver_ops _lcd_ops = +{ + rt_hw_lcd_set_pixel, + rt_hw_lcd_get_pixel, + rt_hw_lcd_draw_hline, + rt_hw_lcd_draw_vline, + rt_hw_lcd_draw_raw_hline +}; +#endif + +void lcd_io_init() +{ + /* Release the analog input function*/ + FM3_GPIO->ADE =0x03; + /*Select CPIO function*/ + LCD_CS_PFR &= ~LCD_CS; + /*Make pin output*/ + LCD_CS_DDR |= LCD_CS; + /*Select CPIO function*/ + LCD_CD_PFR &= ~LCD_CD; + /*Make pin output*/ + LCD_CD_DDR |= LCD_CD; + /*Select CPIO function*/ + LCD_PS_PFR &= ~LCD_PS; + /*Make pin output*/ + LCD_PS_DDR |= LCD_PS; + /*Select CPIO function*/ + LCD_CLK_PFR &= ~LCD_CLK; + /*Make pin output*/ + LCD_CLK_DDR |= LCD_CLK; + /*Select CPIO function*/ + LCD_DATA_PFR &= ~LCD_DATA; + /*Make pin output*/ + LCD_DATA_DDR |= LCD_DATA; +} + +/* RT-Thread Device Interface */ +static rt_err_t rt_lcd_init (rt_device_t dev) +{ + lcd_io_init(); + + power_delay(); + lcd_write_cmd(DISPLAY_OFF); + reset_delay(); + // Resetting circuit + lcd_write_cmd(RESET_LCD); + reset_delay(); + // LCD bias setting + lcd_write_cmd(SET_LCD_BIAS_9); + reset_delay(); + // ADC selection: display from left to right + lcd_write_cmd(SET_ADC_NORMAL); + reset_delay(); + // Common output state selection: display from up to down + lcd_write_cmd(COM_SCAN_DIR_REVERSE); + reset_delay(); + + lcd_write_cmd(POWER_BOOSTER_ON); + power_delay(); // 50ms requried + lcd_write_cmd(POWER_REGULATOR_ON); + power_delay(); // 50ms + lcd_write_cmd(POWER_FOLLOWER_ON); + power_delay(); // 50ms + + // Setting the built-in resistance radio for regulation of the V0 voltage + // Electronic volume control + // Power control setting + lcd_write_cmd(SET_ELECVOL_REG|0x05); + delay(); + lcd_write_cmd(SET_ELECVOL_MODE); + delay(); + lcd_write_cmd(SET_ELECVOL_REG); + delay(); + // LCD_Clear(); + delay(); + lcd_write_cmd(SET_PAGE_ADDR_0); + delay(); + lcd_write_cmd(SET_COLH_ADDR_0); + delay(); + lcd_write_cmd(SET_COLL_ADDR_0); + delay(); + lcd_write_cmd(DISPLAY_ON); + delay(); + + lcd_write_cmd(DISPLAY_ALL_ON); + delay(); + lcd_write_cmd(DISPLAY_OFF); + delay(); + lcd_write_cmd(DISPLAY_ON); + delay(); + lcd_write_cmd(DISPLAY_ALL_NORMAL); + delay(); + + return RT_EOK; +} + +/******************************************************************************* +* Function Name : LCD_FillAll +* Description : Fill the whole LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_FillAll(unsigned char* buffer) +{ + unsigned char i,j = GUI_LCM_XMAX; + unsigned char* p = buffer; + + for (i=0; i> 4; + + lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. + lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr + lcd_write_cmd(SET_COLL_ADDR_0 | coll); + lcd_write_data(gui_disp_buf[page][x]); +} + +/**************************************************************************** +* Function Name : LCD_PutChar +* Description : output a char to screen + (the char only can be ' ','0'~'9','A'~'Z','a'~'z') +* Input : x X-coordinate + y Y-coordinate + ch character +* Output : None +* Return : 1 Success + 0 Fail +****************************************************************************/ +unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) +{ + unsigned char data; + unsigned char i, j; + + if( x >=(GUI_LCM_XMAX-8) ) return(0); + if( y >=(GUI_LCM_YMAX-8) ) return(0); + + if(ch == 0x20) + ch -= 0x20; + else if((ch >= 0x30)&&(ch <= 0x39)) + ch -= 0x2f; + else if((ch >= 0x41)&&(ch <= 0x5a)) + ch -= 0x36; + else if((ch >= 0x61)&&(ch <= 0x7a)) + ch -= 0x3C; + else + return(0); + + for(i = 0; i < 8; i++) + { + data = FONTTYPE8_8[ch][i]; + + for(j = 0; j < 8; j++) + { + if( (data&BIT_MASK[j]) == 0) + gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); + else + gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); + LCD_UpdatePoint(x, y); + x ++; + } + x -= 8; + y++; + } + + return(1); +} + +/**************************************************************************** +* Function Name : LCD_PutString +* Description : output string to screen +* Input : x X-coordinate + y Y-coordinate + str pointer to string +* Output : None +* Return : None +****************************************************************************/ +void LCD_PutString(unsigned long x, unsigned long y, char *str) +{ + while(1) + { + if( (*str)=='\0' ) break; + if( LCD_PutChar(x, y, *str++) == 0 ) break; + x += 6; + } +} + +static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { +#ifdef RT_USING_RTGUI + case RTGRAPHIC_CTRL_RECT_UPDATE: + rt_hw_lcd_update(args); + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; +#else + case RT_DEVICE_CTRL_LCD_DISPLAY_ON: + lcd_write_cmd(DISPLAY_ON); + break; + case RT_DEVICE_CTRL_LCD_DISPLAY_OFF: + lcd_write_cmd(DISPLAY_OFF); + break; + case RT_DEVICE_CTRL_LCD_PUT_STRING: + LCD_PutString(x, y, (char*)args); + break; + case RT_DEVICE_CTRL_LCD_CLEAR_SCR: + LCD_ClearSCR(); + break; +#endif + } + + return RT_EOK; +} + +void rt_hw_lcd_init(void) +{ + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = RT_NULL; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; +#ifdef RT_USING_RTGUI + lcd->user_data = (void*)&_lcd_ops; +#endif + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); +} diff --git a/bsp/fujitsu/mb9x/mb9bf500r/lcd.h b/bsp/fujitsu/mb9x/mb9bf500r/lcd.h new file mode 100644 index 0000000000..e0fa9efdc3 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/lcd.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-03-29 Yi.Qiu + * 2011-06-13 lgnq modified for FM3 easy kit + */ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include +#include "mb9bf506r.h" + +/********* LCD Hardward Interface ************* +LCD_CS PORT1.7 +LCD_CD PORT1.6 +LCD_WR PORT1.5 +LCD_RD PORT1.4 +LCD_SCK PORT1.3 +LCD_MOSI PORT1.2 +LCD_C86 PORT1.1 +LCD_PS PORT1.0 +LCD_DATA[0..7] PORT5.[0..7] +***********************************************/ +#define LCD_CS (1UL << 7) +#define LCD_CS_DDR (FM3_GPIO->DDR1) +#define LCD_CS_PFR (FM3_GPIO->PFR1) +#define LCD_CS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CD (1UL << 6) +#define LCD_CD_DDR (FM3_GPIO->DDR1) +#define LCD_CD_PFR (FM3_GPIO->PFR1) +#define LCD_CD_PDOR (FM3_GPIO->PDOR1) + +#define LCD_PS (1UL << 0) +#define LCD_PS_DDR (FM3_GPIO->DDR1) +#define LCD_PS_PFR (FM3_GPIO->PFR1) +#define LCD_PS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CLK (1UL << 6) +#define LCD_CLK_DDR (FM3_GPIO->DDR5) +#define LCD_CLK_PFR (FM3_GPIO->PFR5) +#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) + +#define LCD_DATA (1UL << 7) +#define LCD_DATA_DDR (FM3_GPIO->DDR5) +#define LCD_DATA_PFR (FM3_GPIO->PFR5) +#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) + +/* LCD driver for ZYMG12864C3 */ +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 + +// Driver the LCD with Parallel or serial interface and the command/data control pin is gpio +#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS +#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS + +#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD +#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD + +#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS +#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS + +#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK +#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK + +#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA +#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA + +// define the arrtibute of ZYMG12864(LCM) +#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 +#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 +#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) + +/* set LCD command */ +#define DISPLAY_ON 0xAF // A0,RD,WR:010 +#define DISPLAY_OFF 0xAE // A0,RD,WR:010 + +#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 +#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 +#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; +#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 + +#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 +#define STATUS_BUSY 0x80 +#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n +#define STATUS_DISPLAY_OFF 0x20 +#define STATUS_RESET 0x80 + +#define WRITE_DATA 0x-- // A0,RD,WR:110 +#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable + +#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 +#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 +#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 +#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color +#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 +#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 + +/************************************************************* +* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* ---------------|----------|----------|----------|--------- * +* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * +* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * +**************************************************************/ + +#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 +#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 + +#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating +#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. +#define RESET_LCD 0xE2 // A0,RD,WR:010 + + +/************************************************************************************** +* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* --------------|-------------|-------------|-------------|------------------------ * +* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * +* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * +***************************************************************************************/ + +#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 +#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 + +// 0 0 1 0 1 | Booster On | Regulator On | Follower On +#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 +#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 +#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 + +#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large + +#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command +#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. + +#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command +#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command +#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command + +#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command +#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command +#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command +#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command + +#define COMMAND_NOP 0xE3 // A0,RD,WR:010 +#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use + +#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 +#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 +#define RT_DEVICE_CTRL_LCD_GET_BPP 2 +#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 +#define RT_DEVICE_CTRL_LCD_POWER_ON 4 +#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 +#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 +#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 +#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 +#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 +#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 +#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 + +enum +{ + ADC_MSG, + KEY_MSG, + CPU_MSG, + MAX_MSG, +}; + +struct lcd_msg +{ + rt_uint8_t type; + rt_uint16_t adc_value; + rt_uint8_t key; + rt_uint16_t major; + rt_uint16_t minor; +}; + +extern rt_uint32_t x; +extern rt_uint32_t y; + +void rt_hw_lcd_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/led.c b/bsp/fujitsu/mb9x/mb9bf500r/led.c new file mode 100644 index 0000000000..ee28af7035 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/led.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include + +#include "mb9bf506r.h" +#include "led.h" + +void rt_hw_led_on(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + LED_PDOR &= ~LED1; + break; + case 2: + LED_PDOR &= ~LED2; + break; + case 3: + LED_PDOR &= ~LED3; + break; + default: + break; + } +} + +void rt_hw_led_off(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + LED_PDOR |= LED1; + break; + case 2: + LED_PDOR |= LED2; + break; + case 3: + LED_PDOR |= LED3; + break; + default: + break; + } +} + +void rt_hw_led_toggle(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + if (LED_PDOR&LED1) + LED_PDOR &= ~LED1; + else + LED_PDOR |= LED1; + break; + case 2: + if (LED_PDOR&LED2) + LED_PDOR &= ~LED2; + else + LED_PDOR |= LED2; + break; + case 3: + if (LED_PDOR&LED3) + LED_PDOR &= ~LED3; + else + LED_PDOR |= LED3; + break; + default: + break; + } +} + +static rt_err_t led_io_init(void) +{ + /*Select CPIO function*/ + LED_PFR &= ~LED_MASK; + /*Set Pin to turn off leds*/ + LED_PDOR |= LED_MASK; + /*Make led pins outputs*/ + LED_DDR |= LED_MASK; + + //LED3 is controled by PWM + FM3_GPIO->PFR3 = 0x1000; + FM3_GPIO->EPFR04 = 0x00080000; + FM3_BT2_PWM->TMCR = 0x0018; + FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ + FM3_BT2_PWM->STC = 0x00; + FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ + FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ + + FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ + return RT_EOK; +} + +void pwm_update(rt_uint16_t value) +{ + FM3_BT2_PWM->PDUT = value; +} + +static void led1_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(1); + rt_thread_delay(RT_TICK_PER_SECOND); + } +} + +static void led2_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(2); + rt_thread_delay(RT_TICK_PER_SECOND/2); + } +} + +static rt_thread_t led1_thread; +static rt_thread_t led2_thread; +void rt_hw_led_init(void) +{ + led_io_init(); + + led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); + if (led1_thread != RT_NULL) + rt_thread_startup(led1_thread); + + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); + if (led2_thread != RT_NULL) + rt_thread_startup(led2_thread); +} + + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/led.h b/bsp/fujitsu/mb9x/mb9bf500r/led.h new file mode 100644 index 0000000000..c4a433cb81 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/led.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include "mb9bf506r.h" + +#define LEDS_MAX_NUMBER 4 + +/*LEDs*/ +#define LED1 (1UL<<10) +#define LED2 (1UL<<11) +#define LED3 (1UL<<12) +#define LED_MASK (LED1 | LED2 | LED3) + +#define LED_PFR (FM3_GPIO->PFR3) +#define LED_DDR (FM3_GPIO->DDR3) +#define LED_PDOR (FM3_GPIO->PDOR3) + +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 + +void rt_hw_led_init(void); +void rt_hw_led_on(rt_uint8_t num); +void rt_hw_led_off(rt_uint8_t num); +void rt_hw_led_toggle(rt_uint8_t num); +void pwm_update(rt_uint16_t value); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/mb9bf500r.icf b/bsp/fujitsu/mb9x/mb9bf500r/mb9bf500r.icf new file mode 100644 index 0000000000..ff723823ce --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/mb9bf500r.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/fujitsu/mb9x/mb9bf500r/project.uvopt b/bsp/fujitsu/mb9x/mb9bf500r/project.uvopt new file mode 100644 index 0000000000..f4ebac8267 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/project.uvopt @@ -0,0 +1,559 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + RT-Thread FM3 + 0x4 + ARM-ADS + + 4000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\obj\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 7 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Startup + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 43 + 0 + 121 + 121 + 0 + .\application.c + application.c + + + 1 + 2 + 1 + 0 + 0 + 20 + 0 + 32 + 34 + 0 + .\board.c + board.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup.c + startup.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\adc.c + adc.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\cpuusage.c + cpuusage.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\key.c + key.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\lcd.c + lcd.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\led.c + led.c + + + 1 + 9 + 1 + 0 + 0 + 39 + 0 + 14 + 25 + 0 + .\info.c + info.c + + + + + FM3 + 0 + 0 + 0 + + 2 + 10 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + context_rvds.S + + + 2 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m3\cpuport.c + cpuport.c + + + + + CMSIS + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\core_cm3.c + core_cm3.c + + + 3 + 13 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\CMSIS\start_rvds.S + start_rvds.S + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\system_mb9bf50x.c + system_mb9bf50x.c + + + + + Kernel + 0 + 0 + 0 + + 4 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + + + 4 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\device.c + device.c + + + 4 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + + + 4 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + + + 4 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + + + 4 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + + + 4 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + + + 4 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + + + 4 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\object.c + object.c + + + 4 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + + + 4 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\slab.c + slab.c + + + 4 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf500r/project.uvproj new file mode 100644 index 0000000000..971e04f6e1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/project.uvproj @@ -0,0 +1,547 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread FM3 + 0x4 + ARM-ADS + + + MB9BF500R + Fujitsu Semiconductors + IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0003FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "STARTUP\FUJITSU\MB9BF50x\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BF50x_256 -FS00 -FL040000) + 5155 + MB9BF50x.h + + + + + + + + + + + 0 + + + + Fujitsu\MB9BF50x\ + Fujitsu\MB9BF50x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + rtthread-fm3 + 1 + 0 + 0 + 1 + 1 + .\obj\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + CMSIS;.;..\..\include;..\..\components\rtgui\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + + + + + + + + + + + Startup + + + application.c + 1 + .\application.c + + + board.c + 1 + .\board.c + + + startup.c + 1 + .\startup.c + + + adc.c + 1 + .\adc.c + + + cpuusage.c + 1 + .\cpuusage.c + + + key.c + 1 + .\key.c + + + lcd.c + 1 + .\lcd.c + + + led.c + 1 + .\led.c + + + info.c + 1 + .\info.c + + + + + FM3 + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + CMSIS + + + core_cm3.c + 1 + .\CMSIS\core_cm3.c + + + start_rvds.S + 2 + .\CMSIS\start_rvds.S + + + system_mb9bf50x.c + 1 + .\CMSIS\system_mb9bf50x.c + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + slab.c + 1 + ..\..\src\slab.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.h b/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.h new file mode 100644 index 0000000000..ac37ecb464 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.h @@ -0,0 +1,88 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +/* #define RT_DEBUG */ +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +/* RT_USING_UART */ +#define RT_USING_UART0 +#define RT_UART_RX_BUFFER_SIZE 64 + +/* SECTION: Console options */ +#define RT_TINY_SIZE +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: RTGUI support */ +/* using RTGUI support */ +/* #define RT_USING_RTGUI */ + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 16 +/* support 16 weight font */ +//#define RTGUI_USING_FONT16 +/* support 12 weight font */ +#define RTGUI_USING_FONT12 +/* support Chinese font */ +//#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +//#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +/* #define RTGUI_USING_HZ_FILE */ +/* use Chinese bitmap font */ +//#define RTGUI_USING_HZ_BMP +/* use small size in RTGUI */ +//#define RTGUI_USING_SMALL_SIZE +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +#define RTGUI_DEFAULT_FONT_SIZE 12 + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.py b/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.py new file mode 100644 index 0000000000..24ae26d0ab --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/rtconfig.py @@ -0,0 +1,124 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter fm3_rom.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + CFLAGS = '' + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' + + LFLAGS = ' --config mb9bf500r.icf' + LFLAGS += ' --semihosting' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/fujitsu/mb9x/mb9bf500r/startup.c b/bsp/fujitsu/mb9x/mb9bf500r/startup.c new file mode 100644 index 0000000000..1e7309ae3e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf500r/startup.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" +/** + * @addtogroup FM3 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init application */ + rt_application_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* init system setting */ + SystemInit(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/SConscript b/bsp/fujitsu/mb9x/mb9bf506r/SConscript new file mode 100644 index 0000000000..0992612410 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/SConscript @@ -0,0 +1,12 @@ +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/fujitsu/mb9x/mb9bf506r/SConstruct b/bsp/fujitsu/mb9x/mb9bf506r/SConstruct new file mode 100644 index 0000000000..97f374e663 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/SConstruct @@ -0,0 +1,35 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/fujitsu/mb9x/mb9bf506r/applications/SConscript b/bsp/fujitsu/mb9x/mb9bf506r/applications/SConscript new file mode 100644 index 0000000000..4ccb177207 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf506r/applications/application.c b/bsp/fujitsu/mb9x/mb9bf506r/applications/application.c new file mode 100644 index 0000000000..fdc42a9100 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/applications/application.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-24 Bernard the first version + */ + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +#include +#include "board.h" +#include "led.h" + +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:ELM filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +void rt_init_thread_entry(void *parameter) +{ + /* LED Initialization */ + rt_hw_led_init(); + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization RT-Thread Components */ + rt_components_init(); +#endif + + /* Filesystem Initialization */ +#ifdef RT_USING_DFS + /* mount nand fat partition 1 as root directory */ + if (dfs_mount("nand", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); +#endif +} + +int rt_application_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/applications/startup.c b/bsp/fujitsu/mb9x/mb9bf506r/applications/startup.c new file mode 100644 index 0000000000..ccb31d40b4 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/applications/startup.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* initialize board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + +#ifdef RT_USING_HEAP + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE +#if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS) + rt_hw_nand_init(); +#endif +#endif + + /* initialize application */ + rt_application_init(); + + /* initialize timer */ + rt_system_timer_init(); + + /* initialize timer thread */ + rt_system_timer_thread_init(); + + /* initialize idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/SConscript b/bsp/fujitsu/mb9x/mb9bf506r/drivers/SConscript new file mode 100644 index 0000000000..f4b66bd711 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/SConscript @@ -0,0 +1,16 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + SrcRemove(src, 'emac.c') +if GetDepend('RT_USING_DFS') == False: + SrcRemove(src, 'sd.c') + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.c b/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.c new file mode 100644 index 0000000000..d687bea929 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mcu.h" + +#include "fm3_uart.h" +#include "nand.h" + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init(void) +{ + /* init systick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + /* initialize nand flash device */ + rt_hw_nand_init(); +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.h b/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.h new file mode 100644 index 0000000000..d2f252990c --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/board.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +//Internal SRAM memory size[Kbytes] <8-64> +//MB9BF500 : 32 +//MB9BF504 : 32 +//MB9BF505 : 48 +//MB9BF506 : 64 +#define FM3_SRAM_SIZE 64 +#define FM3_SRAM_END (0x1FFF8000 + FM3_SRAM_SIZE * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.c b/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.c new file mode 100644 index 0000000000..ece042cca4 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.c @@ -0,0 +1,929 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-05-15 lgnq first version. + * 2012-05-28 heyuanjie87 change interfaces + */ + +#include +#include +#include "fm3_uart.h" + +#if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) +/* UART0 device driver structure */ +struct uart03_device uart0 = +{ + FM3_MFS0_UART, + MFS0RX_IRQn, + MFS0TX_IRQn, +}; +struct rt_serial_device serial0; + +void MFS0RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) +/* UART1 device driver structure */ +struct uart03_device uart1 = +{ + FM3_MFS1_UART, + MFS1RX_IRQn, + MFS1TX_IRQn, +}; +struct rt_serial_device serial1; + +void MFS1RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) +/* UART2 device driver structure */ +struct uart03_device uart2 = +{ + FM3_MFS2_UART, + MFS2RX_IRQn, + MFS2TX_IRQn, +}; +struct rt_serial_device serial2; + +void MFS2RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) +/* UART3 device driver structure */ +struct uart03_device uart3 = +{ + FM3_MFS3_UART, + MFS3RX_IRQn, + MFS3TX_IRQn, +}; +struct rt_serial_device serial3; + +void MFS3RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) +/* UART4 device driver structure */ +struct uart47_device uart4 = +{ + FM3_MFS4_UART, + MFS4RX_IRQn, + MFS4TX_IRQn, + FIFO_SIZE, +}; +struct rt_serial_device serial4; + +void MFS4RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) +/* UART5 device driver structure */ +struct uart47_device uart5 = +{ + FM3_MFS5_UART, + MFS5RX_IRQn, + MFS5TX_IRQn, + FIFO_SIZE, +}; +struct rt_serial_device serial5; + +void MFS5RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) +/* UART6 device driver structure */ +struct uart47_device uart6 = +{ + FM3_MFS6_UART, + MFS6RX_IRQn, + MFS6TX_IRQn, + FIFO_SIZE, +}; +struct rt_serial_device serial6; + +void MFS6RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) +/* UART7 device driver structure */ +struct uart47_device uart7 = +{ + FM3_MFS7_UART, + MFS7RX_IRQn, + MFS7TX_IRQn, + FIFO_SIZE, +}; +struct rt_serial_device serial7; + +void MFS7RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif + +void uart_pin_setup(void) +{ +#if defined(RT_USING_UART0_0) + /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ + FM3_GPIO->PFR2_f.P1 = 1; + FM3_GPIO->PFR2_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 1; + FM3_GPIO->EPFR07_f.SIN0S1 = 0; + FM3_GPIO->EPFR07_f.SOT0B0 = 1; + FM3_GPIO->EPFR07_f.SOT0B1 = 0; +#elif defined(RT_USING_UART0_1) + /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ + FM3_GPIO->PFR1_f.P4 = 1; + FM3_GPIO->PFR1_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 0; + FM3_GPIO->EPFR07_f.SIN0S1 = 1; + FM3_GPIO->EPFR07_f.SOT0B0 = 0; + FM3_GPIO->EPFR07_f.SOT0B1 = 1; +#endif + +#if defined(RT_USING_UART1_0) + /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ + FM3_GPIO->PFR5_f.P6 = 1; + FM3_GPIO->PFR5_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 1; + FM3_GPIO->EPFR07_f.SIN1S1 = 0; + FM3_GPIO->EPFR07_f.SOT1B0 = 1; + FM3_GPIO->EPFR07_f.SOT1B1 = 0; +#elif defined(RT_USING_UART1_1) + /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ + FM3_GPIO->PFR1_f.P1 = 1; + FM3_GPIO->PFR1_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 0; + FM3_GPIO->EPFR07_f.SIN1S1 = 1; + FM3_GPIO->EPFR07_f.SOT1B0 = 0; + FM3_GPIO->EPFR07_f.SOT1B1 = 1; +#endif + +#if defined(RT_USING_UART2_0) + /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ + FM3_GPIO->PFR7_f.P2 = 1; + FM3_GPIO->PFR7_f.P3 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 0; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 0; +#elif defined(RT_USING_UART2_1) + /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ + FM3_GPIO->PFR2_f.P4 = 1; + FM3_GPIO->PFR2_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 0; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 0; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; +#elif defined(RT_USING_UART2_2) + /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ + FM3_GPIO->PFR1_f.P7 = 1; + FM3_GPIO->PFR1_f.P8 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; +#endif + +#if defined(RT_USING_UART3_0) + /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ + FM3_GPIO->PFR6_f.P6 = 1; + FM3_GPIO->PFR6_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 0; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 0; +#elif defined(RT_USING_UART3_1) + /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ + FM3_GPIO->PFR5_f.P0 = 1; + FM3_GPIO->PFR5_f.P1 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 0; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 0; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; +#elif defined(RT_USING_UART3_2) + /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ + FM3_GPIO->PFR4_f.P8 = 1; + FM3_GPIO->PFR4_f.P9 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; +#endif + +#if defined(RT_USING_UART4_0) + /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ + FM3_GPIO->PFR0_f.PA = 1; + FM3_GPIO->PFR0_f.PB = 1; + FM3_GPIO->PFR0_f.PD = 1; + FM3_GPIO->PFR0_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 0; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 0; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 0; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 0; +#elif defined(RT_USING_UART4_1) + /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ + FM3_GPIO->PFR1_f.PA = 1; + FM3_GPIO->PFR1_f.PB = 1; + FM3_GPIO->PFR1_f.PD = 1; + FM3_GPIO->PFR1_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 0; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 0; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 0; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 0; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; +#elif defined(RT_USING_UART4_2) + /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ + FM3_GPIO->PFR0_f.P5 = 1; + FM3_GPIO->PFR0_f.P6 = 1; + FM3_GPIO->PFR0_f.P8 = 1; + FM3_GPIO->PFR0_f.P9 = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; +#endif + +#if defined(RT_USING_UART5_0) + /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ + FM3_GPIO->PFR6_f.P0 = 1; + FM3_GPIO->PFR6_f.P1 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 0; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 0; +#elif defined(RT_USING_UART5_1) + /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ + FM3_GPIO->PFR6_f.P3 = 1; + FM3_GPIO->PFR6_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 0; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 0; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; +#elif defined(RT_USING_UART5_2) + /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ + FM3_GPIO->PFR3_f.P6 = 1; + FM3_GPIO->PFR3_f.P7 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; +#endif + +#if defined(RT_USING_UART6_0) + /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ + FM3_GPIO->PFR5_f.P3 = 1; + FM3_GPIO->PFR5_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 1; + FM3_GPIO->EPFR08_f.SIN6S1 = 0; + FM3_GPIO->EPFR08_f.SOT6B0 = 1; + FM3_GPIO->EPFR08_f.SOT6B1 = 0; +#elif defined(RT_USING_UART6_1) + /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ + FM3_GPIO->PFR3_f.P2 = 1; + FM3_GPIO->PFR3_f.P3 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 0; + FM3_GPIO->EPFR08_f.SIN6S1 = 1; + FM3_GPIO->EPFR08_f.SOT6B0 = 0; + FM3_GPIO->EPFR08_f.SOT6B1 = 1; +#endif + +#if defined(RT_USING_UART7_0) + /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ + FM3_GPIO->PFR5_f.P9 = 1; + FM3_GPIO->PFR5_f.PA = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 1; + FM3_GPIO->EPFR08_f.SIN7S1 = 0; + FM3_GPIO->EPFR08_f.SOT7B0 = 1; + FM3_GPIO->EPFR08_f.SOT7B1 = 0; +#elif defined(RT_USING_UART7_1) + /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ + FM3_GPIO->PFR4_f.PD = 1; + FM3_GPIO->PFR4_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 0; + FM3_GPIO->EPFR08_f.SIN7S1 = 1; + FM3_GPIO->EPFR08_f.SOT7B0 = 0; + FM3_GPIO->EPFR08_f.SOT7B1 = 1; +#endif +} + +static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } + + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } + + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } + + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } + + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } + + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; +} + +static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct uart03_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); +} + +static int uart03_putc(struct rt_serial_device *serial, char c) +{ + struct uart03_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + /* while send buffer is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to send buffer */ + uart->uart_regs->TDR = c; + + return (1); +} + +static int uart03_getc(struct rt_serial_device *serial) +{ + struct uart03_device *uart; + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + /* receive buffer is full */ + if (uart->uart_regs->SSR & SSR_RDRF) + { + ch = uart->uart_regs->RDR & 0xff; + return (ch); + } + else + return (-1); +} + +static struct rt_uart_ops uart03_ops = +{ + uart03_configure, + uart03_control, + uart03_putc, + uart03_getc, +}; + +static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } + + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } + + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } + + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } + + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } + + /* configure fifo */ + /* Disable the Data Lost detection */ + uart->uart_regs->FCR1_f.FLSTE = 0; + /* Enable the received FIFO idle detection */ + uart->uart_regs->FCR1_f.FRIE = 1; + /* Requests for the transmit FIFO data */ + uart->uart_regs->FCR1_f.FDRQ = 1; + /* Disable the transmit FIFO interrupt */ + uart->uart_regs->FCR1_f.FTIE = 0; + /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ + uart->uart_regs->FCR1_f.FSEL = 0; + + /* Transfer data count */ + uart->uart_regs->FBYTE1 = 0; + /* Set the data count to generate a received interrupt */ + uart->uart_regs->FBYTE2 = uart->fifo_size; + + /* FIFO pointer Not reloaded */ + uart->uart_regs->FCR0_f.FLD = 0; + /* FIFO pointer Not saved */ + uart->uart_regs->FCR0_f.FSET = 0; + /* FIFO2 is reset */ + uart->uart_regs->FCR0_f.FCL2 = 1; + /* FIFO1 is reset */ + uart->uart_regs->FCR0_f.FCL1 = 1; + /* Enables the FIFO2 operation */ + uart->uart_regs->FCR0_f.FE2 = 1; + /* Enables the FIFO1 operation */ + uart->uart_regs->FCR0_f.FE1 = 1; + + /* enable receive and send */ + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; +} + +static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct uart47_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); +} + +static int uart47_putc(struct rt_serial_device *serial, char c) +{ + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + /* while send fifo is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to fifo */ + uart->uart_regs->TDR = c; + + return (1); +} + +static int uart47_getc(struct rt_serial_device *serial) +{ + int ch; + struct uart47_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + /* receive is disabled */ + if (!(uart->uart_regs->SCR & SCR_RXE)) + return (-1); + /* receive fifo is not full */ + if ((uart->uart_regs->SSR & SSR_RDRF) == 0) + return (-1); + /* read char */ + ch = uart->uart_regs->RDR & 0xff; + + return (ch); +} + +static struct rt_uart_ops uart47_ops = +{ + uart47_configure, + uart47_control, + uart47_putc, + uart47_getc, +}; + +void rt_hw_serial_init(void) +{ + struct serial_configure config; + + uart_pin_setup(); + +#if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial0.ops = &uart03_ops; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); +#endif + +#if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial1.ops = &uart03_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); +#endif + +#if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial2.ops = &uart03_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); +#endif + +#if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial3.ops = &uart03_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart3); +#endif + +#if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial4.ops = &uart47_ops; + serial4.config = config; + + /* register UART4 device */ + rt_hw_serial_register(&serial4, + "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart4); +#endif + +#if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial5.ops = &uart47_ops; + serial5.config = config; + + /* register UART5 device */ + rt_hw_serial_register(&serial5, + "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart5); +#endif + +#if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial6.ops = &uart47_ops; + serial6.config = config; + + /* register UART6 device */ + rt_hw_serial_register(&serial6, + "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); +#endif + +#if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + serial7.ops = &uart47_ops; + serial7.config = config; + + /* register UART7 device */ + rt_hw_serial_register(&serial7, + "uart7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart7); +#endif +} diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.h b/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.h new file mode 100644 index 0000000000..824592c850 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/fm3_uart.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#ifndef __FM3_UART_H__ +#define __FM3_UART_H__ + +#include +#include "mb9bf506r.h" + +#define SMR_SOE 0x01U +#define SMR_BDS 0x04U +#define SMR_SBL 0x08U +#define SMR_WUCR 0x10U +#define SMR_MD_UART 0x00U +#define SMR_MD_UART_MP 0x20U +#define SMR_MD_SIO 0x40U +#define SMR_MD_LIN 0x60U +#define SMR_MD_I2C 0x80U + +#define SCR_TXE 0x01U +#define SCR_RXE 0x02U +#define SCR_TBIE 0x04U +#define SCR_TIE 0x08U +#define SCR_RIE 0x10U +#define SCR_UPGL 0x80U + +#define SSR_TBI 0x01U +#define SSR_TDRE 0x02U +#define SSR_RDRF 0x04U +#define SSR_ORE 0x08U +#define SSR_FRE 0x10U +#define SSR_PE 0x20U +#define SSR_REC 0x80U + +#define ESCR_P 0x08U +#define ESCR_PEN 0x10U +#define ESCR_INV 0x20U +#define ESCR_ESBL 0x40U +#define ESCR_FLWEN 0x80U +#define ESCR_DATABITS_8 0x00U +#define ESCR_DATABITS_5 0x01U +#define ESCR_DATABITS_6 0x02U +#define ESCR_DATABITS_7 0x03U +#define ESCR_DATABITS_9 0x04U + +#define FIFO_SIZE 16 + +/* + * Enable/DISABLE Interrupt Controller + */ +/* deviation from MISRA-C:2004 Rule 19.7 */ +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct uart03_device +{ + FM3_MFS03_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; +}; + +struct uart47_device +{ + FM3_MFS47_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + rt_uint8_t fifo_size; +}; + +void rt_hw_serial_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.c b/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.c new file mode 100644 index 0000000000..3f6a11fcfe --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include + +#include "mb9bf506r.h" +#include "led.h" + +void rt_hw_led_on(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + USER_LED_PDOR &= ~USER_LED1; + break; + case 2: + USER_LED_PDOR &= ~USER_LED2; + break; + case 3: + USER_LED_PDOR &= ~USER_LED3; + break; + default: + break; + } +} + +void rt_hw_led_off(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + USER_LED_PDOR |= USER_LED1; + break; + case 2: + USER_LED_PDOR |= USER_LED2; + break; + case 3: + USER_LED_PDOR |= USER_LED3; + break; + default: + break; + } +} + +void rt_hw_led_toggle(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + if (USER_LED_PDOR&USER_LED1) + USER_LED_PDOR &= ~USER_LED1; + else + USER_LED_PDOR |= USER_LED1; + break; + case 2: + if (USER_LED_PDOR&USER_LED2) + USER_LED_PDOR &= ~USER_LED2; + else + USER_LED_PDOR |= USER_LED2; + break; + case 3: + if (USER_LED_PDOR&USER_LED3) + USER_LED_PDOR &= ~USER_LED3; + else + USER_LED_PDOR |= USER_LED3; + break; + default: + break; + } +} + +void led_init(void) +{ + /*Select CPIO function*/ + USER_LED_PFR &= ~USER_LED_MASK; + /* disable analog input */ + FM3_GPIO->ADE &= ~USER_LED_MASK; + /*Set CPIO Pull-Up function*/ + USER_LED_PCR |= USER_LED_MASK; + /*Make led pins outputs*/ + USER_LED_DDR |= USER_LED_MASK; + USER_LED_PDOR |= USER_LED_MASK; +} + +void pwm_update(rt_uint16_t value) +{ + FM3_BT2_PWM->PDUT = value; +} + +static void led1_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(1); + rt_thread_delay(RT_TICK_PER_SECOND); + } +} + +static void led2_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(2); + rt_thread_delay(RT_TICK_PER_SECOND/2); + } +} + +static rt_thread_t led1_thread; +static rt_thread_t led2_thread; +void rt_hw_led_init(void) +{ + led_init(); + + led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); + if (led1_thread != RT_NULL) + rt_thread_startup(led1_thread); + + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); + if (led2_thread != RT_NULL) + rt_thread_startup(led2_thread); +} + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.h b/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.h new file mode 100644 index 0000000000..bcbfaf9b62 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/led.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include "mb9bf506r.h" + +#define LEDS_MAX_NUMBER 4 + +/* LED */ +#define USER_LED1 (1UL<<0x9) +#define USER_LED2 (1UL<<0xa) +#define USER_LED3 (1UL<<0xb) + +#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) +#define USER_LED_PFR FM3_GPIO->PFR1 +#define USER_LED_PCR FM3_GPIO->PCR1 +#define USER_LED_PDOR FM3_GPIO->PDOR1 +#define USER_LED_DDR FM3_GPIO->DDR1 + +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 + +void rt_hw_led_init(void); +void rt_hw_led_on(rt_uint8_t num); +void rt_hw_led_off(rt_uint8_t num); +void rt_hw_led_toggle(rt_uint8_t num); +void pwm_update(rt_uint16_t value); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.c b/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.c new file mode 100644 index 0000000000..1c03120d14 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.c @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-25 Bernard first version + */ + +#include "nand.h" +#include "mb9bf506r.h" + +/* + * NandFlash driver for SamSung K9F5608 + * 32M x 8bit + */ +#define PAGE_SIZE 512 +#define PAGE_PER_BLOCK 32 +#define BLOCK_NUM 2048 + +/* device driver debug trace */ +/* #define NAND_DEBUG */ +#ifdef NAND_DEBUG +#define trace_log rt_kprintf +#else +#define trace_log(...) +#endif + +/* + * OOB, + * when block has been erased, OOB is 0xff. + * when block has been written, OOB is 0x00. + */ +struct rt_device_nand +{ + struct rt_device parent; /* which is inherited from rt_device */ + + rt_uint16_t block_num; /* total block number in device */ + rt_uint16_t page_per_block; /* pages in one block */ + rt_uint16_t page_size; /* page size */ + + /* this buffer which used as to save data before erase block */ + rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; +}; +static struct rt_device_nand _nand; + +/* Flash operation definition */ +#define NF_CMD(cmd) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_CMD_OFFSET) = (unsigned char)(cmd);} +#define NF_ADDR(addr) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ADDR_OFFSET)= (unsigned char)(addr);} +#define NF_RDDATA() (*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)) +#define NF_WRDATA(data) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)= (unsigned char)(data);} +#define NF_CLR_ALE() {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ALE_OFFSET) = (unsigned char)0;} + +/* Flash Control IO definition */ +#define NF_OE_H() {IO_NF_PDOR |= NF_EN;} +#define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} + +#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} +#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} + +static unsigned char NF_ReadStatus(void); +static void Wait(unsigned int cnt); +static void NF_Reset(void); + +static void Wait(unsigned int cnt) +{ + while(cnt--); +} + +static void NF_Reset(void) +{ + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_RESET); + NF_OE_H(); + + Wait(10000); /* wait for Trst */ +} + +static unsigned char NF_ReadStatus(void) +{ + unsigned int timeout=0; + NF_DATA_OUT(); + NF_CMD(NAND_CMD_STATUS); + NF_DATA_IN(); + + while(!(NF_RDDATA() & 0x40)) + { + timeout++; + if(timeout == 0x00080000) + return FLASH_NG; + } + if(NF_RDDATA() & 0x01)return FLASH_NG; + + return FLASH_OK; +} + +/* + * @ Funciton: NF_Init + * Parameter: None + * Return: None + */ +static void NF_Init(void) +{ + FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ + FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ + |1<<6 /* ALE, CLE, WEX, REX enable */ + |1<<0); /* D0-D7 enable */ + FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ + FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ + + IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); + IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); + IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ + + /*Reset NAND*/ + NF_Reset(); +} + +static void NF_UnInit(void) +{ + FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ + FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ + |1<<6 /* disable ALE, CLE, WEX, REX enable */ + |1<<0); /* disable D0-D7 enable */ + FM3_EXBUS->MODE7 &= ~(1<<4); + IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); + IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); + IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ +} + +/* + * @ Funciton: NF_ReadPage + * Parameter: block (max: 2048) + * page (max:32) + * buffer: pointer to data buffer + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, + unsigned char *oob) +{ + unsigned int blockPage,i; + + NF_Init(); + blockPage=(block<<5)+page; /* 1 block=32 page */ + NF_OE_L(); + NF_DATA_OUT(); + if (buffer != RT_NULL) + { + volatile unsigned char ch; + + NF_CMD(NAND_CMD_READ0); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for(i=0;i<512;i++) /* read 512 bytes data */ + buffer[i] = NF_RDDATA(); + for(i=0;i<16;i++) /* read 16 bytes oob */ + if (oob != RT_NULL) + oob[i] = NF_RDDATA(); + else + ch = NF_RDDATA(); + } + else + { + NF_CMD(NAND_CMD_READOOB); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for (i=0; i<16; i++) /* read 16 bytes oob */ + oob[i] = NF_RDDATA(); + } + + NF_OE_H(); + NF_UnInit(); + return 0; +} + +/* + * @ Funciton: NF_EraseBlock + * Parameter: block (max: 2048) + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_EraseBlock(unsigned int block) +{ + rt_uint32_t blockPage; + + trace_log("Erase block %d: ", block); + + NF_Init(); + blockPage = (block << 5); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_ERASE1); /* send erase command */ + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage >> 8) & 0xff); + NF_CMD(NAND_CMD_ERASE2); /* start erase */ + + if(NF_ReadStatus()) + { + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + trace_log("Failed\n"); + rt_kprintf("erase block failed\n"); + + return FLASH_NG; + } + + NF_OE_H(); + NF_UnInit(); + + trace_log("OK\n"); + + return FLASH_OK; +} + +/* + * @ Funciton: NF_WritePage + * Parameter: block (max: 2048) + * page (max:32) + * buffer: pointer to data buffer + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) +{ + unsigned int blockPage,i; + unsigned char se[16] = {0}; + unsigned char data; + + blockPage = (block<<5)+page; + NF_Init(); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(0x00); /* set programming area */ + NF_CMD(NAND_CMD_SEQIN); /* send write command */ + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); + NF_CLR_ALE(); + + for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ + for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ + + NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ + + if(NF_ReadStatus()) + { + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + + trace_log("write failed\n"); + return FLASH_NG; + } + + /* verify the write data */ + NF_DATA_OUT(); + NF_CMD(NAND_CMD_READ0); /* send read command */ + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + for(i=0; i<512; i++) + { + data=NF_RDDATA(); /* verify 1-512 byte */ + if(data != buffer[i]) + { + trace_log("block %d, page %d\n", block , page); + trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); + + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + return FLASH_NG; + } + } + + for(i=0; i<16; i++) + { + data=NF_RDDATA(); /* verify 16 byte dummy data */ + if(data != se[i]) + { + trace_log("block %d, page %d\n", block , page); + trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + return FLASH_NG; + } + } + + NF_OE_H(); + NF_UnInit(); + return FLASH_OK; +} + +/* + * @ Funciton: NF_ReadID + * Parameter: id: pointer to device ID + * Return: None + */ +void NF_ReadID(unsigned char *id) +{ + unsigned char maker_code; + NF_Init(); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_READID); + NF_ADDR(0x00); + NF_CLR_ALE(); + Wait(10); + NF_DATA_IN(); + maker_code = NF_RDDATA(); + maker_code = maker_code; + *id = NF_RDDATA(); + NF_OE_H(); + NF_UnInit(); +} + +static rt_err_t rt_nand_init (rt_device_t dev) +{ + /* empty implementation */ + return RT_EOK; +} + +static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) +{ + /* empty implementation */ + return RT_EOK; +} + +static rt_err_t rt_nand_close(rt_device_t dev) +{ + /* empty implementation */ + return RT_EOK; +} + +/* nand device read */ +static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_ubase_t block; /* block of position */ + rt_ubase_t page, index; /* page in block of position */ + rt_uint8_t *page_ptr, oob[16]; + struct rt_device_nand *nand; + + /* get nand device */ + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand read: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + /* set page buffer pointer */ + page_ptr = (rt_uint8_t*) buffer; + for (index = 0; index < size; index ++) + { + NF_ReadPage(block, page + index, page_ptr, oob); + page_ptr += nand->page_size; + + if (page + index > nand->page_per_block) + { + block += 1; + page = 0; + } + } + + /* return read size (count of block) */ + return size; +} + +/* + * write pages by erase block first + * @param nand the nand device driver + * @param block the block of page + * @param page the page + * @param buffer the data buffer to be written + * @param pages the number of pages to be written + */ +static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, + rt_ubase_t block, rt_ubase_t page, + const rt_uint8_t *buffer, rt_ubase_t pages) +{ + rt_ubase_t index; + rt_uint32_t page_status; + rt_uint8_t *page_ptr, oob[16]; + + /* set page status */ + page_status = 0; + + /* read each page in block */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + NF_ReadPage(block, index, page_ptr, oob); + if (!oob[0]) + page_status |= (1 << index); + page_ptr += nand->page_size; + } + + /* erase block */ + NF_EraseBlock(block); + + page_ptr = &(nand->block_buffer[page * nand->page_size]); + /* merge buffer to page buffer */ + for (index = 0; index < pages; index ++) + { + rt_memcpy(page_ptr, buffer, nand->page_size); + + /* set page status */ + page_status |= (1 << (page + index)); + + /* move to next page */ + page_ptr += nand->page_size; + buffer += nand->page_size; + } + + /* write to flash */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + if (page_status & (1 << index)) + NF_WritePage(block, index, page_ptr); + + /* move to next page */ + page_ptr += nand->page_size; + } + + return 0; +} + +/* nand device write */ +static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_ubase_t block, page; + rt_uint8_t oob[16]; + struct rt_device_nand *nand; + + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand write: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + if (size == 1) + { + /* write one page */ + + /* read oob to get page status */ + NF_ReadPage(block, page, RT_NULL, oob); + if (oob[0]) + NF_WritePage(block, page, buffer); + else + /* erase block and then write page */ + rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); + } + else if (size > 1) + { + rt_ubase_t index; + rt_ubase_t need_erase_block; + const rt_uint8_t *page_ptr; + rt_ubase_t chunk_pages, pages; + + pages = size; + page_ptr = (const rt_uint8_t*) buffer; + do + { + need_erase_block = 0; + /* calculate pages in current chunk */ + if (pages > nand->page_per_block - page) + chunk_pages = nand->page_per_block - page; + else + chunk_pages = pages; + + /* get page status in current block */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_ReadPage(block, index, RT_NULL, oob); + if (!oob[0]) + { + /* this page has data, need erase this block firstly */ + need_erase_block = 1; + break; + } + } + + if (need_erase_block) + { + /* erase block and then write it */ + rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); + page_ptr += chunk_pages * nand->page_size; + } + else + { + /* write pages directly */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_WritePage(block, index, page_ptr); + page_ptr += nand->page_size; + } + } + + pages -= chunk_pages; + page = 0; block ++; /* move to next block */ + } + while (pages); + } + + return size; +} + +static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args) +{ + struct rt_device_nand *nand; + + nand = (struct rt_device_nand*) dev; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; + + geometry->bytes_per_sector = nand->page_size; + geometry->block_size = nand->page_size * nand->page_per_block; + geometry->sector_count = nand->block_num * nand->page_per_block; + } + break; + } + + return RT_EOK; +} + +void rt_hw_nand_init(void) +{ + /* initialize nand flash structure */ + _nand.block_num = BLOCK_NUM; + _nand.page_per_block = PAGE_PER_BLOCK; + _nand.page_size = PAGE_SIZE; + + rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); + + _nand.parent.type = RT_Device_Class_MTD; + _nand.parent.rx_indicate = RT_NULL; + _nand.parent.tx_complete = RT_NULL; + _nand.parent.init = rt_nand_init; + _nand.parent.open = rt_nand_open; + _nand.parent.close = rt_nand_close; + _nand.parent.read = rt_nand_read; + _nand.parent.write = rt_nand_write; + _nand.parent.control = rt_nand_control; + + /* register a MTD device */ + rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); +} + +#ifdef NAND_DEBUG +#include +unsigned char nand_buffer[512]; +unsigned char nand_oob[16]; + +void dump_mem(unsigned char* buffer, int length) +{ + int i; + + if (length > 64) length = 64; + for (i = 0; i < length; i ++) + { + rt_kprintf("%02x ", *buffer++); + if (((i+1) % 16) == 0) + rt_kprintf("\n"); + } + rt_kprintf("\n"); +} + +void nand_read(int block, int page) +{ + rt_kprintf("read block %d, page %d\n", block, page); + + NF_ReadPage(block, page, nand_buffer, nand_oob); + rt_kprintf("page data:\n"); + dump_mem(nand_buffer, 512); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); + +void nand_write(int block, int page) +{ + int i; + for (i = 0; i < 512; i ++) + nand_buffer[i] = i; + + NF_WritePage(block, page, nand_buffer); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); + +void nand_erase(int block) +{ + NF_EraseBlock(block); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); + +void nand_readoob(int block, int page) +{ + rt_kprintf("read oob on block %d, page %d\n", block, page); + + NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); + +void nand_erase_chip(void) +{ + int i; + unsigned char id; + + NF_ReadID(&id); + rt_kprintf("id: %02x\n", id); + + for (i = 0; i < 2048; i ++) + { + NF_EraseBlock(i); + } +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.h b/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.h new file mode 100644 index 0000000000..d00909ddce --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/drivers/nand.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-25 Bernard first version + */ + +#ifndef __NAND_H__ +#define __NAND_H__ + +#include + +#define IO_NF_PFR FM3_GPIO->PFR3 +#define IO_NF_DDR FM3_GPIO->DDR3 +#define IO_NF_PDOR FM3_GPIO->PDOR3 + +#define NF_EN 0x0008 +#define NF_DATA_DIR 0x0004 + +#define EXT_BUS_BASE_ADDR 0x60000000 +#define EXT_CS7_OFFSET 0x0E000000 +#define EXT_CS7_SIZE 0x02000000 + +#define NF_FLASH_BASE_ADDR (EXT_BUS_BASE_ADDR+EXT_CS7_OFFSET) + +#define NF_ALE_OFFSET 0x00003000 +#define NF_ADDR_OFFSET 0x00002000 +#define NF_CMD_OFFSET 0x00001000 +#define NF_DATA_OFFSET 0x00000000 + +/* NAND command */ +#define NAND_CMD_READ0 0x00 +#define NAND_CMD_READ1 0x01 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_READID1 0x91 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +#define FLASH_OK 0 +#define FLASH_NG 1 + +/* nand flash device initialization */ +void rt_hw_nand_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h new file mode 100644 index 0000000000..1b7029a755 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h @@ -0,0 +1,209 @@ +/************************************************** + * + * This file shall be included in appropriate CMSIS header + * files, to provide required functions and intrinsics when + * building with the IAR C/C++ Compiler for ARM (iccarm). + * + * Copyright 2011 IAR Systems. All rights reserved. + * + * $Revision: 50409 $ + * + **************************************************/ + +#ifndef __CMSIS_IAR_H__ +#define __CMSIS_IAR_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#include + +#if (__CORE__ == __ARM6M__) + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz + #define __SSAT __cmsis_iar_ssat +#endif + +#pragma diag_suppress=Pe940 +#pragma diag_suppress=Pe177 + +#define __enable_irq __enable_interrupt +#define __disable_irq __disable_interrupt +#define __NOP __no_operation + +#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ + +#if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */ + +static uint32_t __get_APSR(void) +{ + __ASM("mrs r0, apsr"); +} + +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); /* assembler does not know "xpsr" */ +} + +#endif /* __VER__ < 6010002 */ + +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + +static uint32_t __get_PSR(void) +{ + __ASM("mrs r0, psr"); +} + +static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + +static __INLINE void __WFI(void) +{ + __ASM ("wfi"); +} + +static __INLINE void __WFE(void) +{ + __ASM ("wfe"); +} + +static __INLINE void __SEV(void) +{ + __ASM ("sev"); +} + +static uint32_t __REV16(uint32_t value) +{ + __ASM("rev16 r0, r0"); +} + +#else /* __VER__ < 6020000 */ + +static uint32_t __get_xPSR(void) +{ + return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */ +} + +#endif /* __VER__ < 6020000 */ + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + +#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ + +static __INLINE void __enable_fault_irq(void) +{ + __ASM ("cpsie f"); +} + +static __INLINE void __disable_fault_irq(void) +{ + __ASM ("cpsid f"); +} + +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + +static uint8_t __LDREXB(volatile uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + +static uint16_t __LDREXH(volatile uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + +static uint32_t __LDREXW(volatile uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + +static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + +static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + +static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + +static __INLINE void __CLREX(void) +{ + __ASM ("clrex"); +} + +#else /* __VER__ >= 6020000 --------------------- */ + +#define __LDREXW __LDREX +#define __STREXW __STREX +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#endif /* __VER__ < 6020000 */ + +#endif /* (__CORTEX_M >= 0x03) */ + +#if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + +#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ + +static uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */ + __ASM("vmrs r0, fpscr"); +#else + return(0); +#endif +} + +static void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */ + __ASM("vmsr fpscr, r0"); +#endif +} + +#endif /* __VER__ < 6020000 */ + +#endif /* (__CORTEX_M == 0x04) */ + +static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); +} + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_IAR_H__ */ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cm3.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..0173893fbd --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1612 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..3c932e0d6e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..597e64df04 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h new file mode 100644 index 0000000000..df507ee456 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h @@ -0,0 +1,17483 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9BF506R */ +/* Version V1.03 */ +/* Date 2011-05-16 */ +/* */ +/************************************************************************/ + +#ifndef _MB9BF506R_H_ +#define _MB9BF506R_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + CAN0_IRQn = 32, /* CAN ch.0 */ + CAN1_IRQn = 33, /* CAN ch.1 */ + USBF_IRQn = 34, /* USB Function */ + USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ + /* Reserved = 36 */ + /* Reserved = 37 */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45 /* DMAC ch.7 */ + /* Reserved = 46 */ + /* Reserved = 47 */ +} IRQn_Type; + + +#include "core_cm3.h" +#include "system_mb9bf50x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Peripheral register bit fields + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash_IF_MODULE register bit fields */ +typedef struct stc_flash_if_faszr_field +{ + __IO uint32_t ASZ0 : 1; + __IO uint32_t ASZ1 : 1; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + __IO uint32_t RWT0 : 1; + __IO uint32_t RWT1 : 1; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY : 1; + __IO uint32_t HNG : 1; + __IO uint32_t EER : 1; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + __IO uint32_t TRMM0 : 1; + __IO uint32_t TRMM1 : 1; + __IO uint32_t TRMM2 : 1; + __IO uint32_t TRMM3 : 1; + __IO uint32_t TRMM4 : 1; + __IO uint32_t TRMM5 : 1; + __IO uint32_t TRMM6 : 1; + __IO uint32_t TRMM7 : 1; + __IO uint32_t TRMM8 : 1; + __IO uint32_t TRMM9 : 1; +} stc_flash_if_crtrmm_field_t; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock_Reset_MODULE register bit fields */ +typedef struct stc_crg_scm_ctl_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MOSCE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SOSCE : 1; + __IO uint8_t PLLE : 1; + __IO uint8_t RCS0 : 1; + __IO uint8_t RCS1 : 1; + __IO uint8_t RCS2 : 1; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MORDY : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SORDY : 1; + __IO uint8_t PLRDY : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t RCM2 : 1; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint16_t PONR : 1; + __IO uint16_t INITX : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SWDT : 1; + __IO uint16_t HWDT : 1; + __IO uint16_t CSVR : 1; + __IO uint16_t FCSR : 1; + __IO uint16_t SRST : 1; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + __IO uint8_t BSR0 : 1; + __IO uint8_t BSR1 : 1; + __IO uint8_t BSR2 : 1; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + __IO uint8_t APBC00 : 1; + __IO uint8_t APBC01 : 1; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + __IO uint8_t APBC10 : 1; + __IO uint8_t APBC11 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC1RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC1EN : 1; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + __IO uint8_t APBC20 : 1; + __IO uint8_t APBC21 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC2RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC2EN : 1; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + __IO uint8_t SWDS0 : 1; + __IO uint8_t SWDS1 : 1; + uint8_t RESERVED1 : 5; + __IO uint8_t TESTB : 1; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + __IO uint8_t TTC : 1; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + __IO uint8_t MOWT0 : 1; + __IO uint8_t MOWT1 : 1; + __IO uint8_t MOWT2 : 1; + __IO uint8_t MOWT3 : 1; + __IO uint8_t SOWT0 : 1; + __IO uint8_t SOWT1 : 1; + __IO uint8_t SOWT2 : 1; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + __IO uint8_t POWT0 : 1; + __IO uint8_t POWT1 : 1; + __IO uint8_t POWT2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t PINC : 1; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + __IO uint8_t PLLM0 : 1; + __IO uint8_t PLLM1 : 1; + __IO uint8_t PLLM2 : 1; + __IO uint8_t PLLM3 : 1; + __IO uint8_t PLLK0 : 1; + __IO uint8_t PLLK1 : 1; + __IO uint8_t PLLK2 : 1; + __IO uint8_t PLLK3 : 1; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + __IO uint8_t PLLN0 : 1; + __IO uint8_t PLLN1 : 1; + __IO uint8_t PLLN2 : 1; + __IO uint8_t PLLN3 : 1; + __IO uint8_t PLLN4 : 1; + __IO uint8_t PLLN5 : 1; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + __IO uint16_t MCSVE : 1; + __IO uint16_t SCSVE : 1; + uint16_t RESERVED1 : 6; + __IO uint16_t FCSDE : 1; + __IO uint16_t FCSRE : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t FCD0 : 1; + __IO uint16_t FCD1 : 1; + __IO uint16_t FCD2 : 1; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint8_t MCMF : 1; + __IO uint8_t SCMF : 1; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + uint8_t RESERVED1 : 5; + __IO uint8_t DPSWBE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t DPHWBE : 1; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint8_t MCSE : 1; + __IO uint8_t SCSE : 1; + __IO uint8_t PCSE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSE : 1; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint8_t MCSI : 1; + __IO uint8_t SCSI : 1; + __IO uint8_t PCSI : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSI : 1; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint8_t MCSC : 1; + __IO uint8_t SCSC : 1; + __IO uint8_t PCSC : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSC : 1; +} stc_crg_int_clr_field_t; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* HWWDT_MODULE register bit fields */ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint8_t RIS : 1; +} stc_hwwdt_wdg_ris_field_t; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* SWWDT_MODULE register bit fields */ +typedef struct stc_swwdt_wdogcontrol_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint8_t RIS : 1; +} stc_swwdt_wdogris_field_t; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* DTIM_MODULE register bit fields */ +typedef struct stc_dtim_timer1control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer1control_field_t; + +typedef struct stc_dtim_timer1ris_field +{ + __IO uint32_t TIMERXRIS : 1; +} stc_dtim_timer1ris_field_t; + +typedef struct stc_dtim_timer1mis_field +{ + __IO uint32_t TIMERXRIS : 1; +} stc_dtim_timer1mis_field_t; + +typedef struct stc_dtim_timer2control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer2control_field_t; + +typedef struct stc_dtim_timer2ris_field +{ + __IO uint32_t TIMERXRIS : 1; +} stc_dtim_timer2ris_field_t; + +typedef struct stc_dtim_timer2mis_field +{ + __IO uint32_t TIMERXRIS : 1; +} stc_dtim_timer2mis_field_t; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* MFT_FRT_MODULE register bit fields */ +typedef struct stc_mft_frt_tcsa0_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsb0_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb0_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsb1_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb1_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsb2_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb2_field_t; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* MFT_OCU_MODULE register bit fields */ +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST2 : 1; + __IO uint8_t CST3 : 1; + __IO uint8_t BDIS2 : 1; + __IO uint8_t BDIS3 : 1; + __IO uint8_t IOE2 : 1; + __IO uint8_t IOE3 : 1; + __IO uint8_t IOP2 : 1; + __IO uint8_t IOP3 : 1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD2 : 1; + __IO uint8_t OTD3 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS2 : 1; + __IO uint8_t BTS3 : 1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST4 : 1; + __IO uint8_t CST5 : 1; + __IO uint8_t BDIS4 : 1; + __IO uint8_t BDIS5 : 1; + __IO uint8_t IOE4 : 1; + __IO uint8_t IOE5 : 1; + __IO uint8_t IOP4 : 1; + __IO uint8_t IOP5 : 1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD4 : 1; + __IO uint8_t OTD5 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS4 : 1; + __IO uint8_t BTS5 : 1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 : 1; + __IO uint8_t MOD1 : 1; + __IO uint8_t MOD2 : 1; + __IO uint8_t MOD3 : 1; + __IO uint8_t MOD4 : 1; + __IO uint8_t MOD5 : 1; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + __IO uint8_t FSO20 : 1; + __IO uint8_t FSO21 : 1; + __IO uint8_t FSO22 : 1; + __IO uint8_t FSO23 : 1; + __IO uint8_t FSO30 : 1; + __IO uint8_t FSO31 : 1; + __IO uint8_t FSO32 : 1; + __IO uint8_t FSO33 : 1; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + __IO uint8_t FSO40 : 1; + __IO uint8_t FSO41 : 1; + __IO uint8_t FSO42 : 1; + __IO uint8_t FSO43 : 1; + __IO uint8_t FSO50 : 1; + __IO uint8_t FSO51 : 1; + __IO uint8_t FSO52 : 1; + __IO uint8_t FSO53 : 1; +} stc_mft_ocu_ocfs54_field_t; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* MFT_WFG_MODULE register bit fields */ +typedef struct stc_mft_wfg_wfsa10_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIF : 1; + __IO uint16_t DTIC : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t TMIF10 : 1; + __IO uint16_t TMIC10 : 1; + __IO uint16_t TMIE10 : 1; + __IO uint16_t TMIS10 : 1; + __IO uint16_t TMIF32 : 1; + __IO uint16_t TMIC32 : 1; + __IO uint16_t TMIE32 : 1; + __IO uint16_t TMIS32 : 1; + __IO uint16_t TMIF54 : 1; + __IO uint16_t TMIC54 : 1; + __IO uint16_t TMIE54 : 1; + __IO uint16_t TMIS54 : 1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + __IO uint16_t DTIE : 1; + __IO uint16_t NWS0 : 1; + __IO uint16_t NWS1 : 1; + __IO uint16_t NWS2 : 1; + __IO uint16_t SDTI : 1; +} stc_mft_wfg_nzcl_field_t; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* MFT_ICU_MODULE register bit fields */ +typedef struct stc_mft_icu_icfs10_field +{ + __IO uint8_t FSI00 : 1; + __IO uint8_t FSI01 : 1; + __IO uint8_t FSI02 : 1; + __IO uint8_t FSI03 : 1; + __IO uint8_t FSI10 : 1; + __IO uint8_t FSI11 : 1; + __IO uint8_t FSI12 : 1; + __IO uint8_t FSI13 : 1; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + __IO uint8_t FSI20 : 1; + __IO uint8_t FSI21 : 1; + __IO uint8_t FSI22 : 1; + __IO uint8_t FSI23 : 1; + __IO uint8_t FSI30 : 1; + __IO uint8_t FSI31 : 1; + __IO uint8_t FSI32 : 1; + __IO uint8_t FSI33 : 1; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + __IO uint8_t EG00 : 1; + __IO uint8_t EG01 : 1; + __IO uint8_t EG10 : 1; + __IO uint8_t EG11 : 1; + __IO uint8_t ICE0 : 1; + __IO uint8_t ICE1 : 1; + __IO uint8_t ICP0 : 1; + __IO uint8_t ICP1 : 1; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 : 1; + __IO uint8_t IEI1 : 1; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + __IO uint8_t EG20 : 1; + __IO uint8_t EG21 : 1; + __IO uint8_t EG30 : 1; + __IO uint8_t EG31 : 1; + __IO uint8_t ICE2 : 1; + __IO uint8_t ICE3 : 1; + __IO uint8_t ICP2 : 1; + __IO uint8_t ICP3 : 1; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI2 : 1; + __IO uint8_t IEI3 : 1; +} stc_mft_icu_icsb32_field_t; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* MFT_ADCMP_MODULE register bit fields */ +typedef struct stc_mft_adcmp_acsb_field +{ + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t BDIS2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; + __IO uint8_t BTS2 : 1; +} stc_mft_adcmp_acsb_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + __IO uint16_t CE00 : 1; + __IO uint16_t CE01 : 1; + __IO uint16_t CE10 : 1; + __IO uint16_t CE11 : 1; + __IO uint16_t CE20 : 1; + __IO uint16_t CE21 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SEL00 : 1; + __IO uint16_t SEL01 : 1; + __IO uint16_t SEL10 : 1; + __IO uint16_t SEL11 : 1; + __IO uint16_t SEL20 : 1; + __IO uint16_t SEL21 : 1; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_atsa_field +{ + __IO uint16_t AD0S0 : 1; + __IO uint16_t AD0S1 : 1; + __IO uint16_t AD1S0 : 1; + __IO uint16_t AD1S1 : 1; + __IO uint16_t AD2S0 : 1; + __IO uint16_t AD2S1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t AD0P0 : 1; + __IO uint16_t AD0P1 : 1; + __IO uint16_t AD1P0 : 1; + __IO uint16_t AD1P1 : 1; + __IO uint16_t AD2P0 : 1; + __IO uint16_t AD2P1 : 1; +} stc_mft_adcmp_atsa_field_t; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* MFT_PPG_MODULE register bit fields */ +typedef struct stc_mft_ppg_ttcr0_field +{ + __IO uint8_t STR0 : 1; + __IO uint8_t MONI0 : 1; + __IO uint8_t CS00 : 1; + __IO uint8_t CS01 : 1; + __IO uint8_t TRG0O : 1; + __IO uint8_t TRG2O : 1; + __IO uint8_t TRG4O : 1; + __IO uint8_t TRG6O : 1; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + __IO uint8_t STR1 : 1; + __IO uint8_t MONI1 : 1; + __IO uint8_t CS10 : 1; + __IO uint8_t CS11 : 1; + __IO uint8_t TRG1O : 1; + __IO uint8_t TRG3O : 1; + __IO uint8_t TRG5O : 1; + __IO uint8_t TRG7O : 1; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_trg_field +{ + __IO uint16_t PEN00 : 1; + __IO uint16_t PEN01 : 1; + __IO uint16_t PEN02 : 1; + __IO uint16_t PEN03 : 1; + __IO uint16_t PEN04 : 1; + __IO uint16_t PEN05 : 1; + __IO uint16_t PEN06 : 1; + __IO uint16_t PEN07 : 1; + __IO uint16_t PEN08 : 1; + __IO uint16_t PEN09 : 1; + __IO uint16_t PEN10 : 1; + __IO uint16_t PEN11 : 1; + __IO uint16_t PEN12 : 1; + __IO uint16_t PEN13 : 1; + __IO uint16_t PEN14 : 1; + __IO uint16_t PEN15 : 1; +} stc_mft_ppg_trg_field_t; + +typedef struct stc_mft_ppg_revc_field +{ + __IO uint16_t REV00 : 1; + __IO uint16_t REV01 : 1; + __IO uint16_t REV02 : 1; + __IO uint16_t REV03 : 1; + __IO uint16_t REV04 : 1; + __IO uint16_t REV05 : 1; + __IO uint16_t REV06 : 1; + __IO uint16_t REV07 : 1; + __IO uint16_t REV08 : 1; + __IO uint16_t REV09 : 1; + __IO uint16_t REV10 : 1; + __IO uint16_t REV11 : 1; + __IO uint16_t REV12 : 1; + __IO uint16_t REV13 : 1; + __IO uint16_t REV14 : 1; + __IO uint16_t REV15 : 1; +} stc_mft_ppg_revc_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 : 1; + __IO uint8_t STRG0 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE2 : 1; + __IO uint8_t STRG2 : 1; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 : 1; + __IO uint8_t STRG4 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE6 : 1; + __IO uint8_t STRG6 : 1; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 : 1; + __IO uint8_t STRG8 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE10 : 1; + __IO uint8_t STRG10 : 1; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 : 1; + __IO uint8_t STRG12 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE14 : 1; + __IO uint8_t STRG14 : 1; +} stc_mft_ppg_gatec12_field_t; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* BT_PPG_MODULE register bit fields */ +typedef struct stc_bt_ppg_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_ppg_tmcr2_field_t; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* BT_PWM_MODULE register bit fields */ +typedef struct stc_bt_pwm_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR : 1; + __IO uint8_t DTIR : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t UDIE : 1; + __IO uint8_t DTIE : 1; + __IO uint8_t TGIE : 1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwm_tmcr2_field_t; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* BT_RT_MODULE register bit fields */ +typedef struct stc_bt_rt_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_rt_tmcr2_field_t; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* BT_PWC_MODULE register bit fields */ +typedef struct stc_bt_pwc_tmcr_field +{ + uint16_t RESERVED1 : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t EGS2 : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t EDIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t OVIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t EDIE : 1; + __IO uint8_t ERR : 1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwc_tmcr2_field_t; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* BTIOSEL03_MODULE register bit fields */ +typedef struct stc_btiosel03_btsel0123_field +{ + __IO uint8_t SEL01_0 : 1; + __IO uint8_t SEL01_1 : 1; + __IO uint8_t SEL01_2 : 1; + __IO uint8_t SEL01_3 : 1; + __IO uint8_t SEL23_0 : 1; + __IO uint8_t SEL23_1 : 1; + __IO uint8_t SEL23_2 : 1; + __IO uint8_t SEL23_3 : 1; +} stc_btiosel03_btsel0123_field_t; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* BTIOSEL47_MODULE register bit fields */ +typedef struct stc_btiosel47_btsel4567_field +{ + __IO uint8_t SEL45_0 : 1; + __IO uint8_t SEL45_1 : 1; + __IO uint8_t SEL45_2 : 1; + __IO uint8_t SEL45_3 : 1; + __IO uint8_t SEL67_0 : 1; + __IO uint8_t SEL67_1 : 1; + __IO uint8_t SEL67_2 : 1; + __IO uint8_t SEL67_3 : 1; +} stc_btiosel47_btsel4567_field_t; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* SBSSR_MODULE register bit fields */ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSR0 : 1; + __IO uint16_t SSR1 : 1; + __IO uint16_t SSR2 : 1; + __IO uint16_t SSR3 : 1; + __IO uint16_t SSR4 : 1; + __IO uint16_t SSR5 : 1; + __IO uint16_t SSR6 : 1; + __IO uint16_t SSR7 : 1; + __IO uint16_t SSR8 : 1; + __IO uint16_t SSR9 : 1; + __IO uint16_t SSR10 : 1; + __IO uint16_t SSR11 : 1; + __IO uint16_t SSR12 : 1; + __IO uint16_t SSR13 : 1; + __IO uint16_t SSR14 : 1; + __IO uint16_t SSR15 : 1; +} stc_sbssr_btsssr_field_t; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* QPRC_MODULE register bit fields */ +typedef struct stc_qprc_qicr_field +{ + __IO uint16_t QPCMIE : 1; + __IO uint16_t QPCMF : 1; + __IO uint16_t QPRCMIE : 1; + __IO uint16_t QPRCMF : 1; + __IO uint16_t OUZIE : 1; + __IO uint16_t UFDF : 1; + __IO uint16_t OFDF : 1; + __IO uint16_t ZIIF : 1; + __IO uint16_t CDCIE : 1; + __IO uint16_t CDCF : 1; + __IO uint16_t DIRPC : 1; + __IO uint16_t DIROU : 1; + __IO uint16_t QPCNRCMIE : 1; + __IO uint16_t QPCNRCMF : 1; +} stc_qprc_qicr_field_t; + +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE : 1; + __IO uint8_t QPCMF : 1; + __IO uint8_t QPRCMIE : 1; + __IO uint8_t QPRCMF : 1; + __IO uint8_t OUZIE : 1; + __IO uint8_t UFDF : 1; + __IO uint8_t OFDF : 1; + __IO uint8_t ZIIF : 1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE : 1; + __IO uint8_t CDCF : 1; + __IO uint8_t DIRPC : 1; + __IO uint8_t DIROU : 1; + __IO uint8_t QPCNRCMIE : 1; + __IO uint8_t QPCNRCMF : 1; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + __IO uint16_t PCM0 : 1; + __IO uint16_t PCM1 : 1; + __IO uint16_t RCM0 : 1; + __IO uint16_t RCM1 : 1; + __IO uint16_t PSTP : 1; + __IO uint16_t CGSC : 1; + __IO uint16_t RSEL : 1; + __IO uint16_t SWAP : 1; + __IO uint16_t PCRM0 : 1; + __IO uint16_t PCRM1 : 1; + __IO uint16_t AES0 : 1; + __IO uint16_t AES1 : 1; + __IO uint16_t BES0 : 1; + __IO uint16_t BES1 : 1; + __IO uint16_t CGE0 : 1; + __IO uint16_t CGE1 : 1; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qcrl_field +{ + __IO uint8_t PCM0 : 1; + __IO uint8_t PCM1 : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t PSTP : 1; + __IO uint8_t CGSC : 1; + __IO uint8_t RSEL : 1; + __IO uint8_t SWAP : 1; +} stc_qprc_qcrl_field_t; + +typedef struct stc_qprc_qcrh_field +{ + __IO uint8_t PCRM0 : 1; + __IO uint8_t PCRM1 : 1; + __IO uint8_t AES0 : 1; + __IO uint8_t AES1 : 1; + __IO uint8_t BES0 : 1; + __IO uint8_t BES1 : 1; + __IO uint8_t CGE0 : 1; + __IO uint8_t CGE1 : 1; +} stc_qprc_qcrh_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD : 1; + __IO uint16_t ORNGF : 1; + __IO uint16_t ORNGIE : 1; +} stc_qprc_qecr_field_t; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* ADC12_MODULE register bit fields */ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS : 1; + __IO uint8_t PCS : 1; + __IO uint8_t PCNS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t FDAS : 1; + __IO uint8_t ADSTP : 1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE : 1; + __IO uint8_t CMPIE : 1; + __IO uint8_t PCIE : 1; + __IO uint8_t SCIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t CMPIF : 1; + __IO uint8_t PCIF : 1; + __IO uint8_t SCIF : 1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + __IO uint8_t SFS0 : 1; + __IO uint8_t SFS1 : 1; + __IO uint8_t SFS2 : 1; + __IO uint8_t SFS3 : 1; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR : 1; + __IO uint8_t SHEN : 1; + __IO uint8_t RPT : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t SFCLR : 1; + __IO uint8_t SOVR : 1; + __IO uint8_t SFUL : 1; + __IO uint8_t SEMP : 1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_field +{ + __IO uint32_t SC0 : 1; + __IO uint32_t SC1 : 1; + __IO uint32_t SC2 : 1; + __IO uint32_t SC3 : 1; + __IO uint32_t SC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; + __IO uint32_t SD3 : 1; + __IO uint32_t SD4 : 1; + __IO uint32_t SD5 : 1; + __IO uint32_t SD6 : 1; + __IO uint32_t SD7 : 1; + __IO uint32_t SD8 : 1; + __IO uint32_t SD9 : 1; + __IO uint32_t SD10 : 1; + __IO uint32_t SD11 : 1; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scfdl_field +{ + __IO uint16_t SC0 : 1; + __IO uint16_t SC1 : 1; + __IO uint16_t SC2 : 1; + __IO uint16_t SC3 : 1; + __IO uint16_t SC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t INVL : 1; +} stc_adc_scfdl_field_t; + +typedef struct stc_adc_scfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t SD0 : 1; + __IO uint16_t SD1 : 1; + __IO uint16_t SD2 : 1; + __IO uint16_t SD3 : 1; + __IO uint16_t SD4 : 1; + __IO uint16_t SD5 : 1; + __IO uint16_t SD6 : 1; + __IO uint16_t SD7 : 1; + __IO uint16_t SD8 : 1; + __IO uint16_t SD9 : 1; + __IO uint16_t SD10 : 1; + __IO uint16_t SD11 : 1; +} stc_adc_scfdh_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 : 1; + __IO uint16_t AN17 : 1; + __IO uint16_t AN18 : 1; + __IO uint16_t AN19 : 1; + __IO uint16_t AN20 : 1; + __IO uint16_t AN21 : 1; + __IO uint16_t AN22 : 1; + __IO uint16_t AN23 : 1; + __IO uint16_t AN24 : 1; + __IO uint16_t AN25 : 1; + __IO uint16_t AN26 : 1; + __IO uint16_t AN27 : 1; + __IO uint16_t AN28 : 1; + __IO uint16_t AN29 : 1; + __IO uint16_t AN30 : 1; + __IO uint16_t AN31 : 1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis2_field +{ + __IO uint8_t AN16 : 1; + __IO uint8_t AN17 : 1; + __IO uint8_t AN18 : 1; + __IO uint8_t AN19 : 1; + __IO uint8_t AN20 : 1; + __IO uint8_t AN21 : 1; + __IO uint8_t AN22 : 1; + __IO uint8_t AN23 : 1; +} stc_adc_scis2_field_t; + +typedef struct stc_adc_scis3_field +{ + __IO uint8_t AN24 : 1; + __IO uint8_t AN25 : 1; + __IO uint8_t AN26 : 1; + __IO uint8_t AN27 : 1; + __IO uint8_t AN28 : 1; + __IO uint8_t AN29 : 1; + __IO uint8_t AN30 : 1; + __IO uint8_t AN31 : 1; +} stc_adc_scis3_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 : 1; + __IO uint16_t AN1 : 1; + __IO uint16_t AN2 : 1; + __IO uint16_t AN3 : 1; + __IO uint16_t AN4 : 1; + __IO uint16_t AN5 : 1; + __IO uint16_t AN6 : 1; + __IO uint16_t AN7 : 1; + __IO uint16_t AN8 : 1; + __IO uint16_t AN9 : 1; + __IO uint16_t AN10 : 1; + __IO uint16_t AN11 : 1; + __IO uint16_t AN12 : 1; + __IO uint16_t AN13 : 1; + __IO uint16_t AN14 : 1; + __IO uint16_t AN15 : 1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_scis0_field +{ + __IO uint8_t AN0 : 1; + __IO uint8_t AN1 : 1; + __IO uint8_t AN2 : 1; + __IO uint8_t AN3 : 1; + __IO uint8_t AN4 : 1; + __IO uint8_t AN5 : 1; + __IO uint8_t AN6 : 1; + __IO uint8_t AN7 : 1; +} stc_adc_scis0_field_t; + +typedef struct stc_adc_scis1_field +{ + __IO uint8_t AN8 : 1; + __IO uint8_t AN9 : 1; + __IO uint8_t AN10 : 1; + __IO uint8_t AN11 : 1; + __IO uint8_t AN12 : 1; + __IO uint8_t AN13 : 1; + __IO uint8_t AN14 : 1; + __IO uint8_t AN15 : 1; +} stc_adc_scis1_field_t; + +typedef struct stc_adc_pfns_field +{ + __IO uint8_t PFS0 : 1; + __IO uint8_t PFS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t TEST0 : 1; + __IO uint8_t TEST1 : 1; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR : 1; + __IO uint8_t PHEN : 1; + __IO uint8_t PEEN : 1; + __IO uint8_t ESCE : 1; + __IO uint8_t PFCLR : 1; + __IO uint8_t POVR : 1; + __IO uint8_t PFUL : 1; + __IO uint8_t PEMP : 1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_field +{ + __IO uint32_t PC0 : 1; + __IO uint32_t PC1 : 1; + __IO uint32_t PC2 : 1; + __IO uint32_t PC3 : 1; + __IO uint32_t PC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t PD0 : 1; + __IO uint32_t PD1 : 1; + __IO uint32_t PD2 : 1; + __IO uint32_t PD3 : 1; + __IO uint32_t PD4 : 1; + __IO uint32_t PD5 : 1; + __IO uint32_t PD6 : 1; + __IO uint32_t PD7 : 1; + __IO uint32_t PD8 : 1; + __IO uint32_t PD9 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcfdl_field +{ + __IO uint16_t PC0 : 1; + __IO uint16_t PC1 : 1; + __IO uint16_t PC2 : 1; + __IO uint16_t PC3 : 1; + __IO uint16_t PC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + __IO uint16_t RS2 : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t INVL : 1; +} stc_adc_pcfdl_field_t; + +typedef struct stc_adc_pcfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t PD0 : 1; + __IO uint16_t PD1 : 1; + __IO uint16_t PD2 : 1; + __IO uint16_t PD3 : 1; + __IO uint16_t PD4 : 1; + __IO uint16_t PD5 : 1; + __IO uint16_t PD6 : 1; + __IO uint16_t PD7 : 1; + __IO uint16_t PD8 : 1; + __IO uint16_t PD9 : 1; + __IO uint16_t PD10 : 1; + __IO uint16_t PD11 : 1; +} stc_adc_pcfdh_field_t; + +typedef struct stc_adc_pcis_field +{ + __IO uint8_t P1A0 : 1; + __IO uint8_t P1A1 : 1; + __IO uint8_t P1A2 : 1; + __IO uint8_t P2A0 : 1; + __IO uint8_t P2A1 : 1; + __IO uint8_t P2A2 : 1; + __IO uint8_t P2A3 : 1; + __IO uint8_t P2A4 : 1; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + __IO uint8_t CCH0 : 1; + __IO uint8_t CCH1 : 1; + __IO uint8_t CCH2 : 1; + __IO uint8_t CCH3 : 1; + __IO uint8_t CCH4 : 1; + __IO uint8_t CMD0 : 1; + __IO uint8_t CMD1 : 1; + __IO uint8_t CMPEN : 1; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + uint16_t RESERVED1 : 6; + __IO uint16_t CMAD2 : 1; + __IO uint16_t CMAD3 : 1; + __IO uint16_t CMAD4 : 1; + __IO uint16_t CMAD5 : 1; + __IO uint16_t CMAD6 : 1; + __IO uint16_t CMAD7 : 1; + __IO uint16_t CMAD8 : 1; + __IO uint16_t CMAD9 : 1; + __IO uint16_t CMAD10 : 1; + __IO uint16_t CMAD11 : 1; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 : 1; + __IO uint16_t TS17 : 1; + __IO uint16_t TS18 : 1; + __IO uint16_t TS19 : 1; + __IO uint16_t TS20 : 1; + __IO uint16_t TS21 : 1; + __IO uint16_t TS22 : 1; + __IO uint16_t TS23 : 1; + __IO uint16_t TS24 : 1; + __IO uint16_t TS25 : 1; + __IO uint16_t TS26 : 1; + __IO uint16_t TS27 : 1; + __IO uint16_t TS28 : 1; + __IO uint16_t TS29 : 1; + __IO uint16_t TS30 : 1; + __IO uint16_t TS31 : 1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss2_field +{ + __IO uint8_t TS16 : 1; + __IO uint8_t TS17 : 1; + __IO uint8_t TS18 : 1; + __IO uint8_t TS19 : 1; + __IO uint8_t TS20 : 1; + __IO uint8_t TS21 : 1; + __IO uint8_t TS22 : 1; + __IO uint8_t TS23 : 1; +} stc_adc_adss2_field_t; + +typedef struct stc_adc_adss3_field +{ + __IO uint8_t TS24 : 1; + __IO uint8_t TS25 : 1; + __IO uint8_t TS26 : 1; + __IO uint8_t TS27 : 1; + __IO uint8_t TS28 : 1; + __IO uint8_t TS29 : 1; + __IO uint8_t TS30 : 1; + __IO uint8_t TS31 : 1; +} stc_adc_adss3_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 : 1; + __IO uint16_t TS1 : 1; + __IO uint16_t TS2 : 1; + __IO uint16_t TS3 : 1; + __IO uint16_t TS4 : 1; + __IO uint16_t TS5 : 1; + __IO uint16_t TS6 : 1; + __IO uint16_t TS7 : 1; + __IO uint16_t TS8 : 1; + __IO uint16_t TS9 : 1; + __IO uint16_t TS10 : 1; + __IO uint16_t TS11 : 1; + __IO uint16_t TS12 : 1; + __IO uint16_t TS13 : 1; + __IO uint16_t TS14 : 1; + __IO uint16_t TS15 : 1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adss0_field +{ + __IO uint8_t TS0 : 1; + __IO uint8_t TS1 : 1; + __IO uint8_t TS2 : 1; + __IO uint8_t TS3 : 1; + __IO uint8_t TS4 : 1; + __IO uint8_t TS5 : 1; + __IO uint8_t TS6 : 1; + __IO uint8_t TS7 : 1; +} stc_adc_adss0_field_t; + +typedef struct stc_adc_adss1_field +{ + __IO uint8_t TS8 : 1; + __IO uint8_t TS9 : 1; + __IO uint8_t TS10 : 1; + __IO uint8_t TS11 : 1; + __IO uint8_t TS12 : 1; + __IO uint8_t TS13 : 1; + __IO uint8_t TS14 : 1; + __IO uint8_t TS15 : 1; +} stc_adc_adss1_field_t; + +typedef struct stc_adc_adst01_field +{ + __IO uint16_t ST10 : 1; + __IO uint16_t ST11 : 1; + __IO uint16_t ST12 : 1; + __IO uint16_t ST13 : 1; + __IO uint16_t ST14 : 1; + __IO uint16_t STX10 : 1; + __IO uint16_t STX11 : 1; + __IO uint16_t STX12 : 1; + __IO uint16_t ST00 : 1; + __IO uint16_t ST01 : 1; + __IO uint16_t ST02 : 1; + __IO uint16_t ST03 : 1; + __IO uint16_t ST04 : 1; + __IO uint16_t STX00 : 1; + __IO uint16_t STX01 : 1; + __IO uint16_t STX02 : 1; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adst1_field +{ + __IO uint8_t ST10 : 1; + __IO uint8_t ST11 : 1; + __IO uint8_t ST12 : 1; + __IO uint8_t ST13 : 1; + __IO uint8_t ST14 : 1; + __IO uint8_t STX10 : 1; + __IO uint8_t STX11 : 1; + __IO uint8_t STX12 : 1; +} stc_adc_adst1_field_t; + +typedef struct stc_adc_adst0_field +{ + __IO uint8_t ST00 : 1; + __IO uint8_t ST01 : 1; + __IO uint8_t ST02 : 1; + __IO uint8_t ST03 : 1; + __IO uint8_t ST04 : 1; + __IO uint8_t STX00 : 1; + __IO uint8_t STX01 : 1; + __IO uint8_t STX02 : 1; +} stc_adc_adst0_field_t; + +typedef struct stc_adc_adct_field +{ + __IO uint8_t CT0 : 1; + __IO uint8_t CT1 : 1; + __IO uint8_t CT2 : 1; + __IO uint8_t CT3 : 1; + __IO uint8_t CT4 : 1; + __IO uint8_t CT5 : 1; + __IO uint8_t CT6 : 1; + __IO uint8_t CT7 : 1; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + __IO uint8_t PRTSL0 : 1; + __IO uint8_t PRTSL1 : 1; + __IO uint8_t PRTSL2 : 1; + __IO uint8_t PRTSL3 : 1; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + __IO uint8_t SCTSL0 : 1; + __IO uint8_t SCTSL1 : 1; + __IO uint8_t SCTSL2 : 1; + __IO uint8_t SCTSL3 : 1; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + __IO uint8_t ENBL : 1; + __IO uint8_t READY : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CYCLSL0 : 1; + __IO uint8_t CYCLSL1 : 1; +} stc_adc_adcen_field_t; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CRTRIM_MODULE register bit fields */ +typedef struct stc_crtrim_mcr_psr_field +{ + __IO uint8_t CSR0 : 1; + __IO uint8_t CSR1 : 1; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + __IO uint16_t TRD0 : 1; + __IO uint16_t TRD1 : 1; + __IO uint16_t TRD2 : 1; + __IO uint16_t TRD3 : 1; + __IO uint16_t TRD4 : 1; + __IO uint16_t TRD5 : 1; + __IO uint16_t TRD6 : 1; + __IO uint16_t TRD7 : 1; + __IO uint16_t TRD8 : 1; + __IO uint16_t TRD9 : 1; +} stc_crtrim_mcr_ftrm_field_t; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* EXTI_MODULE register bit fields */ +typedef struct stc_exti_enir_field +{ + __IO uint16_t EN0 : 1; + __IO uint16_t EN1 : 1; + __IO uint16_t EN2 : 1; + __IO uint16_t EN3 : 1; + __IO uint16_t EN4 : 1; + __IO uint16_t EN5 : 1; + __IO uint16_t EN6 : 1; + __IO uint16_t EN7 : 1; + __IO uint16_t EN8 : 1; + __IO uint16_t EN9 : 1; + __IO uint16_t EN10 : 1; + __IO uint16_t EN11 : 1; + __IO uint16_t EN12 : 1; + __IO uint16_t EN13 : 1; + __IO uint16_t EN14 : 1; + __IO uint16_t EN15 : 1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint16_t ER0 : 1; + __IO uint16_t ER1 : 1; + __IO uint16_t ER2 : 1; + __IO uint16_t ER3 : 1; + __IO uint16_t ER4 : 1; + __IO uint16_t ER5 : 1; + __IO uint16_t ER6 : 1; + __IO uint16_t ER7 : 1; + __IO uint16_t ER8 : 1; + __IO uint16_t ER9 : 1; + __IO uint16_t ER10 : 1; + __IO uint16_t ER11 : 1; + __IO uint16_t ER12 : 1; + __IO uint16_t ER13 : 1; + __IO uint16_t ER14 : 1; + __IO uint16_t ER15 : 1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint16_t ECL0 : 1; + __IO uint16_t ECL1 : 1; + __IO uint16_t ECL2 : 1; + __IO uint16_t ECL3 : 1; + __IO uint16_t ECL4 : 1; + __IO uint16_t ECL5 : 1; + __IO uint16_t ECL6 : 1; + __IO uint16_t ECL7 : 1; + __IO uint16_t ECL8 : 1; + __IO uint16_t ECL9 : 1; + __IO uint16_t ECL10 : 1; + __IO uint16_t ECL11 : 1; + __IO uint16_t ECL12 : 1; + __IO uint16_t ECL13 : 1; + __IO uint16_t ECL14 : 1; + __IO uint16_t ECL15 : 1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 : 1; + __IO uint32_t LB0 : 1; + __IO uint32_t LA1 : 1; + __IO uint32_t LB1 : 1; + __IO uint32_t LA2 : 1; + __IO uint32_t LB2 : 1; + __IO uint32_t LA3 : 1; + __IO uint32_t LB3 : 1; + __IO uint32_t LA4 : 1; + __IO uint32_t LB4 : 1; + __IO uint32_t LA5 : 1; + __IO uint32_t LB5 : 1; + __IO uint32_t LA6 : 1; + __IO uint32_t LB6 : 1; + __IO uint32_t LA7 : 1; + __IO uint32_t LB7 : 1; + __IO uint32_t LA8 : 1; + __IO uint32_t LB8 : 1; + __IO uint32_t LA9 : 1; + __IO uint32_t LB9 : 1; + __IO uint32_t LA10 : 1; + __IO uint32_t LB10 : 1; + __IO uint32_t LA11 : 1; + __IO uint32_t LB11 : 1; + __IO uint32_t LA12 : 1; + __IO uint32_t LB12 : 1; + __IO uint32_t LA13 : 1; + __IO uint32_t LB13 : 1; + __IO uint32_t LA14 : 1; + __IO uint32_t LB14 : 1; + __IO uint32_t LA15 : 1; + __IO uint32_t LB15 : 1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint8_t NR0 : 1; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint8_t NCL0 : 1; +} stc_exti_nmicl_field_t; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* INTREQ_MODULE register bit fields */ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t DRQSEL0 : 1; + __IO uint32_t DRQSEL1 : 1; + __IO uint32_t DRQSEL2 : 1; + __IO uint32_t DRQSEL3 : 1; + __IO uint32_t DRQSEL4 : 1; + __IO uint32_t DRQSEL5 : 1; + __IO uint32_t DRQSEL6 : 1; + __IO uint32_t DRQSEL7 : 1; + __IO uint32_t DRQSEL8 : 1; + __IO uint32_t DRQSEL9 : 1; + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; + __IO uint32_t DRQSEL15 : 1; + __IO uint32_t DRQSEL16 : 1; + __IO uint32_t DRQSEL17 : 1; + __IO uint32_t DRQSEL18 : 1; + __IO uint32_t DRQSEL19 : 1; + __IO uint32_t DRQSEL20 : 1; + __IO uint32_t DRQSEL21 : 1; + __IO uint32_t DRQSEL22 : 1; + __IO uint32_t DRQSEL23 : 1; + __IO uint32_t DRQSEL24 : 1; + __IO uint32_t DRQSEL25 : 1; + __IO uint32_t DRQSEL26 : 1; + __IO uint32_t DRQSEL27 : 1; + __IO uint32_t DRQSEL28 : 1; + __IO uint32_t DRQSEL29 : 1; + __IO uint32_t DRQSEL30 : 1; + __IO uint32_t DRQSEL31 : 1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI : 1; + __IO uint32_t HWINT : 1; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq00mon_field +{ + __IO uint32_t FCSINT : 1; +} stc_intreq_irq00mon_field_t; + +typedef struct stc_intreq_irq01mon_field +{ + __IO uint32_t SWWDTINT : 1; +} stc_intreq_irq01mon_field_t; + +typedef struct stc_intreq_irq02mon_field +{ + __IO uint32_t LVDINT : 1; +} stc_intreq_irq02mon_field_t; + +typedef struct stc_intreq_irq03mon_field +{ + __IO uint32_t WAVE0INT0 : 1; + __IO uint32_t WAVE0INT1 : 1; + __IO uint32_t WAVE0INT2 : 1; + __IO uint32_t WAVE0INT3 : 1; + __IO uint32_t WAVE1INT0 : 1; + __IO uint32_t WAVE1INT1 : 1; + __IO uint32_t WAVE1INT2 : 1; + __IO uint32_t WAVE1INT3 : 1; +} stc_intreq_irq03mon_field_t; + +typedef struct stc_intreq_irq04mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; +} stc_intreq_irq04mon_field_t; + +typedef struct stc_intreq_irq05mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; +} stc_intreq_irq05mon_field_t; + +typedef struct stc_intreq_irq06mon_field +{ + __IO uint32_t TIMINT0 : 1; + __IO uint32_t TIMINT1 : 1; + __IO uint32_t QUD0INT0 : 1; + __IO uint32_t QUD0INT1 : 1; + __IO uint32_t QUD0INT2 : 1; + __IO uint32_t QUD0INT3 : 1; + __IO uint32_t QUD0INT4 : 1; + __IO uint32_t QUD0INT5 : 1; + __IO uint32_t QUD1INT0 : 1; + __IO uint32_t QUD1INT1 : 1; + __IO uint32_t QUD1INT2 : 1; + __IO uint32_t QUD1INT3 : 1; + __IO uint32_t QUD1INT4 : 1; + __IO uint32_t QUD1INT5 : 1; +} stc_intreq_irq06mon_field_t; + +typedef struct stc_intreq_irq07mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq07mon_field_t; + +typedef struct stc_intreq_irq08mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq08mon_field_t; + +typedef struct stc_intreq_irq09mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq09mon_field_t; + +typedef struct stc_intreq_irq10mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq10mon_field_t; + +typedef struct stc_intreq_irq11mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq11mon_field_t; + +typedef struct stc_intreq_irq12mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq12mon_field_t; + +typedef struct stc_intreq_irq13mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq13mon_field_t; + +typedef struct stc_intreq_irq14mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq14mon_field_t; + +typedef struct stc_intreq_irq15mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq15mon_field_t; + +typedef struct stc_intreq_irq16mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq16mon_field_t; + +typedef struct stc_intreq_irq17mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq17mon_field_t; + +typedef struct stc_intreq_irq18mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq18mon_field_t; + +typedef struct stc_intreq_irq19mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq19mon_field_t; + +typedef struct stc_intreq_irq20mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq20mon_field_t; + +typedef struct stc_intreq_irq21mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq21mon_field_t; + +typedef struct stc_intreq_irq22mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq22mon_field_t; + +typedef struct stc_intreq_irq23mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; + __IO uint32_t PPGINT3 : 1; + __IO uint32_t PPGINT4 : 1; + __IO uint32_t PPGINT5 : 1; +} stc_intreq_irq23mon_field_t; + +typedef struct stc_intreq_irq24mon_field +{ + __IO uint32_t MOSCINT : 1; + __IO uint32_t SOSCINT : 1; + __IO uint32_t MPLLINT : 1; + __IO uint32_t UPLLINT : 1; + __IO uint32_t WCINT : 1; +} stc_intreq_irq24mon_field_t; + +typedef struct stc_intreq_irq25mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq25mon_field_t; + +typedef struct stc_intreq_irq26mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq26mon_field_t; + +typedef struct stc_intreq_irq27mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq27mon_field_t; + +typedef struct stc_intreq_irq28mon_field +{ + __IO uint32_t FRT0INT0 : 1; + __IO uint32_t FRT0INT1 : 1; + __IO uint32_t FRT0INT2 : 1; + __IO uint32_t FRT0INT3 : 1; + __IO uint32_t FRT0INT4 : 1; + __IO uint32_t FRT0INT5 : 1; + __IO uint32_t FRT1INT0 : 1; + __IO uint32_t FRT1INT1 : 1; + __IO uint32_t FRT1INT2 : 1; + __IO uint32_t FRT1INT3 : 1; + __IO uint32_t FRT1INT4 : 1; + __IO uint32_t FRT1INT5 : 1; +} stc_intreq_irq28mon_field_t; + +typedef struct stc_intreq_irq29mon_field +{ + __IO uint32_t ICU0INT0 : 1; + __IO uint32_t ICU0INT1 : 1; + __IO uint32_t ICU0INT2 : 1; + __IO uint32_t ICU0INT3 : 1; + __IO uint32_t ICU1INT0 : 1; + __IO uint32_t ICU1INT1 : 1; + __IO uint32_t ICU1INT2 : 1; + __IO uint32_t ICU1INT3 : 1; +} stc_intreq_irq29mon_field_t; + +typedef struct stc_intreq_irq30mon_field +{ + __IO uint32_t OCU0INT0 : 1; + __IO uint32_t OCU0INT1 : 1; + __IO uint32_t OCU0INT2 : 1; + __IO uint32_t OCU0INT3 : 1; + __IO uint32_t OCU0INT4 : 1; + __IO uint32_t OCU0INT5 : 1; + __IO uint32_t OCU1INT0 : 1; + __IO uint32_t OCU1INT1 : 1; + __IO uint32_t OCU1INT2 : 1; + __IO uint32_t OCU1INT3 : 1; + __IO uint32_t OCU1INT4 : 1; + __IO uint32_t OCU1INT5 : 1; +} stc_intreq_irq30mon_field_t; + +typedef struct stc_intreq_irq31mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; + __IO uint32_t BTINT8 : 1; + __IO uint32_t BTINT9 : 1; + __IO uint32_t BTINT10 : 1; + __IO uint32_t BTINT11 : 1; + __IO uint32_t BTINT12 : 1; + __IO uint32_t BTINT13 : 1; + __IO uint32_t BTINT14 : 1; + __IO uint32_t BTINT15 : 1; +} stc_intreq_irq31mon_field_t; + +typedef struct stc_intreq_irq32mon_field +{ + __IO uint32_t CANINT : 1; +} stc_intreq_irq32mon_field_t; + +typedef struct stc_intreq_irq33mon_field +{ + __IO uint32_t CANINT : 1; +} stc_intreq_irq33mon_field_t; + +typedef struct stc_intreq_irq34mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; +} stc_intreq_irq34mon_field_t; + +typedef struct stc_intreq_irq35mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; + __IO uint32_t USB0INT5 : 1; +} stc_intreq_irq35mon_field_t; + +typedef struct stc_intreq_irq38mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq38mon_field_t; + +typedef struct stc_intreq_irq39mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq39mon_field_t; + +typedef struct stc_intreq_irq40mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq40mon_field_t; + +typedef struct stc_intreq_irq41mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq41mon_field_t; + +typedef struct stc_intreq_irq42mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq42mon_field_t; + +typedef struct stc_intreq_irq43mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq43mon_field_t; + +typedef struct stc_intreq_irq44mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq44mon_field_t; + +typedef struct stc_intreq_irq45mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq45mon_field_t; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* GPIO_MODULE register bit fields */ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pfr5_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; +} stc_gpio_pfr8_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pcr5_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_ddr5_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pdir5_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pdor5_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN0 : 1; + __IO uint32_t AN1 : 1; + __IO uint32_t AN2 : 1; + __IO uint32_t AN3 : 1; + __IO uint32_t AN4 : 1; + __IO uint32_t AN5 : 1; + __IO uint32_t AN6 : 1; + __IO uint32_t AN7 : 1; + __IO uint32_t AN8 : 1; + __IO uint32_t AN9 : 1; + __IO uint32_t ANA : 1; + __IO uint32_t ANB : 1; + __IO uint32_t ANC : 1; + __IO uint32_t AND : 1; + __IO uint32_t ANE : 1; + __IO uint32_t ANF : 1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + __IO uint32_t SUBXC : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t USB0C : 1; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + __IO uint32_t NMIS : 1; + __IO uint32_t CROUTE : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t USB0PE : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t JTAGEN0B : 1; + __IO uint32_t JTAGEN1S : 1; + uint32_t RESERVED3 : 6; + __IO uint32_t TRC0E : 1; + __IO uint32_t TRC1E : 1; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + __IO uint32_t RTO00E0 : 1; + __IO uint32_t RTO00E1 : 1; + __IO uint32_t RTO01E0 : 1; + __IO uint32_t RTO01E1 : 1; + __IO uint32_t RTO02E0 : 1; + __IO uint32_t RTO02E1 : 1; + __IO uint32_t RTO03E0 : 1; + __IO uint32_t RTO03E1 : 1; + __IO uint32_t RTO04E0 : 1; + __IO uint32_t RTO04E1 : 1; + __IO uint32_t RTO05E0 : 1; + __IO uint32_t RTO05E1 : 1; + __IO uint32_t DTTI0C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI0S0 : 1; + __IO uint32_t DTTI0S1 : 1; + __IO uint32_t FRCK0S0 : 1; + __IO uint32_t FRCK0S1 : 1; + __IO uint32_t IC00S0 : 1; + __IO uint32_t IC00S1 : 1; + __IO uint32_t IC00S2 : 1; + __IO uint32_t IC01S0 : 1; + __IO uint32_t IC01S1 : 1; + __IO uint32_t IC01S2 : 1; + __IO uint32_t IC02S0 : 1; + __IO uint32_t IC02S1 : 1; + __IO uint32_t IC02S2 : 1; + __IO uint32_t IC03S0 : 1; + __IO uint32_t IC03S1 : 1; + __IO uint32_t IC03S2 : 1; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + __IO uint32_t RTO10E0 : 1; + __IO uint32_t RTO10E1 : 1; + __IO uint32_t RTO11E0 : 1; + __IO uint32_t RTO11E1 : 1; + __IO uint32_t RTO12E0 : 1; + __IO uint32_t RTO12E1 : 1; + __IO uint32_t RTO13E0 : 1; + __IO uint32_t RTO13E1 : 1; + __IO uint32_t RTO14E0 : 1; + __IO uint32_t RTO14E1 : 1; + __IO uint32_t RTO15E0 : 1; + __IO uint32_t RTO15E1 : 1; + __IO uint32_t DTTI1C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI1S0 : 1; + __IO uint32_t DTTI1S1 : 1; + __IO uint32_t FRCK1S0 : 1; + __IO uint32_t FRCK1S1 : 1; + __IO uint32_t IC10S0 : 1; + __IO uint32_t IC10S1 : 1; + __IO uint32_t IC10S2 : 1; + __IO uint32_t IC11S0 : 1; + __IO uint32_t IC11S1 : 1; + __IO uint32_t IC11S2 : 1; + __IO uint32_t IC12S0 : 1; + __IO uint32_t IC12S1 : 1; + __IO uint32_t IC12S2 : 1; + __IO uint32_t IC13S0 : 1; + __IO uint32_t IC13S1 : 1; + __IO uint32_t IC13S2 : 1; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr04_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA0E0 : 1; + __IO uint32_t TIOA0E1 : 1; + __IO uint32_t TIOB0S0 : 1; + __IO uint32_t TIOB0S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA1S0 : 1; + __IO uint32_t TIOA1S1 : 1; + __IO uint32_t TIOA1E0 : 1; + __IO uint32_t TIOA1E1 : 1; + __IO uint32_t TIOB1S0 : 1; + __IO uint32_t TIOB1S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA2E0 : 1; + __IO uint32_t TIOA2E1 : 1; + __IO uint32_t TIOB2S0 : 1; + __IO uint32_t TIOB2S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA3S0 : 1; + __IO uint32_t TIOA3S1 : 1; + __IO uint32_t TIOA3E0 : 1; + __IO uint32_t TIOA3E1 : 1; + __IO uint32_t TIOB3S0 : 1; + __IO uint32_t TIOB3S1 : 1; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA4E0 : 1; + __IO uint32_t TIOA4E1 : 1; + __IO uint32_t TIOB4S0 : 1; + __IO uint32_t TIOB4S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA5S0 : 1; + __IO uint32_t TIOA5S1 : 1; + __IO uint32_t TIOA5E0 : 1; + __IO uint32_t TIOA5E1 : 1; + __IO uint32_t TIOB5S0 : 1; + __IO uint32_t TIOB5S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA6E0 : 1; + __IO uint32_t TIOA6E1 : 1; + __IO uint32_t TIOB6S0 : 1; + __IO uint32_t TIOB6S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA7S0 : 1; + __IO uint32_t TIOA7S1 : 1; + __IO uint32_t TIOA7E0 : 1; + __IO uint32_t TIOA7E1 : 1; + __IO uint32_t TIOB7S0 : 1; + __IO uint32_t TIOB7S1 : 1; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + __IO uint32_t EINT00S0 : 1; + __IO uint32_t EINT00S1 : 1; + __IO uint32_t EINT01S0 : 1; + __IO uint32_t EINT01S1 : 1; + __IO uint32_t EINT02S0 : 1; + __IO uint32_t EINT02S1 : 1; + __IO uint32_t EINT03S0 : 1; + __IO uint32_t EINT03S1 : 1; + __IO uint32_t EINT04S0 : 1; + __IO uint32_t EINT04S1 : 1; + __IO uint32_t EINT05S0 : 1; + __IO uint32_t EINT05S1 : 1; + __IO uint32_t EINT06S0 : 1; + __IO uint32_t EINT06S1 : 1; + __IO uint32_t EINT07S0 : 1; + __IO uint32_t EINT07S1 : 1; + __IO uint32_t EINT08S0 : 1; + __IO uint32_t EINT08S1 : 1; + __IO uint32_t EINT09S0 : 1; + __IO uint32_t EINT09S1 : 1; + __IO uint32_t EINT10S0 : 1; + __IO uint32_t EINT10S1 : 1; + __IO uint32_t EINT11S0 : 1; + __IO uint32_t EINT11S1 : 1; + __IO uint32_t EINT12S0 : 1; + __IO uint32_t EINT12S1 : 1; + __IO uint32_t EINT13S0 : 1; + __IO uint32_t EINT13S1 : 1; + __IO uint32_t EINT14S0 : 1; + __IO uint32_t EINT14S1 : 1; + __IO uint32_t EINT15S0 : 1; + __IO uint32_t EINT15S1 : 1; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + uint32_t RESERVED1 : 4; + __IO uint32_t SIN0S0 : 1; + __IO uint32_t SIN0S1 : 1; + __IO uint32_t SOT0B0 : 1; + __IO uint32_t SOT0B1 : 1; + __IO uint32_t SCK0B0 : 1; + __IO uint32_t SCK0B1 : 1; + __IO uint32_t SIN1S0 : 1; + __IO uint32_t SIN1S1 : 1; + __IO uint32_t SOT1B0 : 1; + __IO uint32_t SOT1B1 : 1; + __IO uint32_t SCK1B0 : 1; + __IO uint32_t SCK1B1 : 1; + __IO uint32_t SIN2S0 : 1; + __IO uint32_t SIN2S1 : 1; + __IO uint32_t SOT2B0 : 1; + __IO uint32_t SOT2B1 : 1; + __IO uint32_t SCK2B0 : 1; + __IO uint32_t SCK2B1 : 1; + __IO uint32_t SIN3S0 : 1; + __IO uint32_t SIN3S1 : 1; + __IO uint32_t SOT3B0 : 1; + __IO uint32_t SOT3B1 : 1; + __IO uint32_t SCK3B0 : 1; + __IO uint32_t SCK3B1 : 1; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + __IO uint32_t RTS4E0 : 1; + __IO uint32_t RTS4E1 : 1; + __IO uint32_t CTS4S0 : 1; + __IO uint32_t CTS4S1 : 1; + __IO uint32_t SIN4S0 : 1; + __IO uint32_t SIN4S1 : 1; + __IO uint32_t SOT4B0 : 1; + __IO uint32_t SOT4B1 : 1; + __IO uint32_t SCK4B0 : 1; + __IO uint32_t SCK4B1 : 1; + __IO uint32_t SIN5S0 : 1; + __IO uint32_t SIN5S1 : 1; + __IO uint32_t SOT5B0 : 1; + __IO uint32_t SOT5B1 : 1; + __IO uint32_t SCK5B0 : 1; + __IO uint32_t SCK5B1 : 1; + __IO uint32_t SIN6S0 : 1; + __IO uint32_t SIN6S1 : 1; + __IO uint32_t SOT6B0 : 1; + __IO uint32_t SOT6B1 : 1; + __IO uint32_t SCK6B0 : 1; + __IO uint32_t SCK6B1 : 1; + __IO uint32_t SIN7S0 : 1; + __IO uint32_t SIN7S1 : 1; + __IO uint32_t SOT7B0 : 1; + __IO uint32_t SOT7B1 : 1; + __IO uint32_t SCK7B0 : 1; + __IO uint32_t SCK7B1 : 1; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + __IO uint32_t QAIN0S0 : 1; + __IO uint32_t QAIN0S1 : 1; + __IO uint32_t QBIN0S0 : 1; + __IO uint32_t QBIN0S1 : 1; + __IO uint32_t QZIN0S0 : 1; + __IO uint32_t QZIN0S1 : 1; + __IO uint32_t QAIN1S0 : 1; + __IO uint32_t QAIN1S1 : 1; + __IO uint32_t QBIN1S0 : 1; + __IO uint32_t QBIN1S1 : 1; + __IO uint32_t QZIN1S0 : 1; + __IO uint32_t QZIN1S1 : 1; + __IO uint32_t ADTRG0S0 : 1; + __IO uint32_t ADTRG0S1 : 1; + __IO uint32_t ADTRG0S2 : 1; + __IO uint32_t ADTRG0S3 : 1; + __IO uint32_t ADTRG1S0 : 1; + __IO uint32_t ADTRG1S1 : 1; + __IO uint32_t ADTRG1S2 : 1; + __IO uint32_t ADTRG1S3 : 1; + __IO uint32_t ADTRG2S0 : 1; + __IO uint32_t ADTRG2S1 : 1; + __IO uint32_t ADTRG2S2 : 1; + __IO uint32_t ADTRG2S3 : 1; + __IO uint32_t CRX0S0 : 1; + __IO uint32_t CRX0S1 : 1; + __IO uint32_t CTX0E0 : 1; + __IO uint32_t CTX0E1 : 1; + __IO uint32_t CRX1S0 : 1; + __IO uint32_t CRX1S1 : 1; + __IO uint32_t CTX1E0 : 1; + __IO uint32_t CTX1E1 : 1; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB : 1; + __IO uint32_t UEDTHB : 1; + __IO uint32_t TESTB : 1; + __IO uint32_t UEWEXE : 1; + __IO uint32_t UEDQME : 1; + __IO uint32_t UEOEXE : 1; + __IO uint32_t UEFLSE : 1; + __IO uint32_t UECS1E : 1; + __IO uint32_t UECS2E : 1; + __IO uint32_t UECS3E : 1; + __IO uint32_t UECS4E : 1; + __IO uint32_t UECS5E : 1; + __IO uint32_t UECS6E : 1; + __IO uint32_t UECS7E : 1; + __IO uint32_t UEAOOE : 1; + __IO uint32_t UEA08E : 1; + __IO uint32_t UEA09E : 1; + __IO uint32_t UEA10E : 1; + __IO uint32_t UEA11E : 1; + __IO uint32_t UEA12E : 1; + __IO uint32_t UEA13E : 1; + __IO uint32_t UEA14E : 1; + __IO uint32_t UEA15E : 1; + __IO uint32_t UEA16E : 1; + __IO uint32_t UEA17E : 1; + __IO uint32_t UEA18E : 1; + __IO uint32_t UEA19E : 1; + __IO uint32_t UEA20E : 1; + __IO uint32_t UEA21E : 1; + __IO uint32_t UEA22E : 1; + __IO uint32_t UEA23E : 1; + __IO uint32_t UEA24E : 1; +} stc_gpio_epfr10_field_t; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* LVD_MODULE register bit fields */ +typedef struct stc_lvd_lvd_ctl_field +{ + uint8_t RESERVED1 : 2; + __IO uint8_t SVHI0 : 1; + __IO uint8_t SVHI1 : 1; + __IO uint8_t SVHI2 : 1; + __IO uint8_t SVHI3 : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t LVDIE : 1; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIR : 1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDCL : 1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIRDY : 1; +} stc_lvd_lvd_str2_field_t; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USBCLK register bit fields */ +typedef struct stc_usbclk_uccr_field +{ + __IO uint8_t UCEN : 1; + __IO uint8_t UCSEL : 1; +} stc_usbclk_uccr_field_t; + +typedef struct stc_usbclk_upcr1_field +{ + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; +} stc_usbclk_upcr1_field_t; + +typedef struct stc_usbclk_upcr2_field +{ + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; +} stc_usbclk_upcr2_field_t; + +typedef struct stc_usbclk_upcr3_field +{ + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; +} stc_usbclk_upcr3_field_t; + +typedef struct stc_usbclk_upcr4_field +{ + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; +} stc_usbclk_upcr4_field_t; + +typedef struct stc_usbclk_up_str_field +{ + __IO uint8_t UPRDY : 1; +} stc_usbclk_up_str_field_t; + +typedef struct stc_usbclk_upint_enr_field +{ + __IO uint8_t UPCSE : 1; +} stc_usbclk_upint_enr_field_t; + +typedef struct stc_usbclk_upint_clr_field +{ + __IO uint8_t UPCSC : 1; +} stc_usbclk_upint_clr_field_t; + +typedef struct stc_usbclk_upint_str_field +{ + __IO uint8_t UPCSI : 1; +} stc_usbclk_upint_str_field_t; + +typedef struct stc_usbclk_usben_field +{ + __IO uint8_t USBEN : 1; +} stc_usbclk_usben_field_t; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CANPRE_MODULE register bit fields */ +typedef struct stc_canpre_canpre_field +{ + __IO uint8_t CANPRE0 : 1; + __IO uint8_t CANPRE1 : 1; + __IO uint8_t CANPRE2 : 1; + __IO uint8_t CANPRE3 : 1; +} stc_canpre_canpre_field_t; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* MFS03_UART_MODULE register bit fields */ +typedef struct stc_mfs03_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_uart_smr_field_t; + +typedef struct stc_mfs03_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs03_uart_scr_field_t; + +typedef struct stc_mfs03_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs03_uart_escr_field_t; + +typedef struct stc_mfs03_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_uart_ssr_field_t; + +typedef struct stc_mfs03_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_rdr_field_t; + +typedef struct stc_mfs03_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_tdr_field_t; + +typedef struct stc_mfs03_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_uart_bgr_field_t; + +typedef struct stc_mfs03_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_uart_bgr1_field_t; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* MFS03_CSIO_MODULE register bit fields */ +typedef struct stc_mfs03_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_csio_smr_field_t; + +typedef struct stc_mfs03_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_csio_scr_field_t; + +typedef struct stc_mfs03_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs03_csio_escr_field_t; + +typedef struct stc_mfs03_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs03_csio_ssr_field_t; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* MFS03_LIN_MODULE register bit fields */ +typedef struct stc_mfs03_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_lin_smr_field_t; + +typedef struct stc_mfs03_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_lin_scr_field_t; + +typedef struct stc_mfs03_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs03_lin_escr_field_t; + +typedef struct stc_mfs03_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_lin_ssr_field_t; + +typedef struct stc_mfs03_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_lin_bgr_field_t; + +typedef struct stc_mfs03_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_lin_bgr1_field_t; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* MFS03_I2C_MODULE register bit fields */ +typedef struct stc_mfs03_i2c_smr_field +{ + __IO uint8_t ITST0 : 1; + __IO uint8_t ITST1 : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_i2c_smr_field_t; + +typedef struct stc_mfs03_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs03_i2c_ibcr_field_t; + +typedef struct stc_mfs03_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs03_i2c_ibsr_field_t; + +typedef struct stc_mfs03_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs03_i2c_ssr_field_t; + +typedef struct stc_mfs03_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs03_i2c_isba_field_t; + +typedef struct stc_mfs03_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs03_i2c_ismk_field_t; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* MFS47_UART_MODULE register bit fields */ +typedef struct stc_mfs47_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_uart_smr_field_t; + +typedef struct stc_mfs47_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs47_uart_scr_field_t; + +typedef struct stc_mfs47_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs47_uart_escr_field_t; + +typedef struct stc_mfs47_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_uart_ssr_field_t; + +typedef struct stc_mfs47_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_rdr_field_t; + +typedef struct stc_mfs47_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_tdr_field_t; + +typedef struct stc_mfs47_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_uart_bgr_field_t; + +typedef struct stc_mfs47_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_uart_bgr1_field_t; + +typedef struct stc_mfs47_uart_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_uart_fcr_field_t; + +typedef struct stc_mfs47_uart_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_uart_fcr0_field_t; + +typedef struct stc_mfs47_uart_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_uart_fcr1_field_t; + +typedef struct stc_mfs47_uart_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_uart_fbyte_field_t; + +typedef struct stc_mfs47_uart_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_uart_fbyte1_field_t; + +typedef struct stc_mfs47_uart_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_uart_fbyte2_field_t; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* MFS47_CSIO_MODULE register bit fields */ +typedef struct stc_mfs47_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_csio_smr_field_t; + +typedef struct stc_mfs47_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_csio_scr_field_t; + +typedef struct stc_mfs47_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs47_csio_escr_field_t; + +typedef struct stc_mfs47_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs47_csio_ssr_field_t; + +typedef struct stc_mfs47_csio_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_csio_fcr_field_t; + +typedef struct stc_mfs47_csio_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_csio_fcr0_field_t; + +typedef struct stc_mfs47_csio_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_csio_fcr1_field_t; + +typedef struct stc_mfs47_csio_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_csio_fbyte_field_t; + +typedef struct stc_mfs47_csio_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_csio_fbyte1_field_t; + +typedef struct stc_mfs47_csio_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_csio_fbyte2_field_t; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* MFS47_LIN_MODULE register bit fields */ +typedef struct stc_mfs47_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_lin_smr_field_t; + +typedef struct stc_mfs47_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_lin_scr_field_t; + +typedef struct stc_mfs47_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs47_lin_escr_field_t; + +typedef struct stc_mfs47_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_lin_ssr_field_t; + +typedef struct stc_mfs47_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_lin_bgr_field_t; + +typedef struct stc_mfs47_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_lin_bgr1_field_t; + +typedef struct stc_mfs47_lin_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_lin_fcr_field_t; + +typedef struct stc_mfs47_lin_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_lin_fcr0_field_t; + +typedef struct stc_mfs47_lin_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_lin_fcr1_field_t; + +typedef struct stc_mfs47_lin_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_lin_fbyte_field_t; + +typedef struct stc_mfs47_lin_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_lin_fbyte1_field_t; + +typedef struct stc_mfs47_lin_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_lin_fbyte2_field_t; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* MFS47_I2C_MODULE register bit fields */ +typedef struct stc_mfs47_i2c_smr_field +{ + __IO uint8_t ITST0 : 1; + __IO uint8_t ITST1 : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_i2c_smr_field_t; + +typedef struct stc_mfs47_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs47_i2c_ibcr_field_t; + +typedef struct stc_mfs47_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs47_i2c_ibsr_field_t; + +typedef struct stc_mfs47_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs47_i2c_ssr_field_t; + +typedef struct stc_mfs47_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs47_i2c_isba_field_t; + +typedef struct stc_mfs47_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs47_i2c_ismk_field_t; + +typedef struct stc_mfs47_i2c_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_i2c_fcr_field_t; + +typedef struct stc_mfs47_i2c_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_i2c_fcr0_field_t; + +typedef struct stc_mfs47_i2c_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_i2c_fcr1_field_t; + +typedef struct stc_mfs47_i2c_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_i2c_fbyte_field_t; + +typedef struct stc_mfs47_i2c_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_i2c_fbyte1_field_t; + +typedef struct stc_mfs47_i2c_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_i2c_fbyte2_field_t; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC_MODULE register bit fields */ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT : 1; + __IO uint8_t CRC32 : 1; + __IO uint8_t LTLEND : 1; + __IO uint8_t LSBFST : 1; + __IO uint8_t CRCLTE : 1; + __IO uint8_t CRCLSF : 1; + __IO uint8_t FXOR : 1; +} stc_crc_crccr_field_t; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* WC_MODULE register bit fields */ +typedef struct stc_wc_wcrd_field +{ + __IO uint8_t CTR0 : 1; + __IO uint8_t CTR1 : 1; + __IO uint8_t CTR2 : 1; + __IO uint8_t CTR3 : 1; + __IO uint8_t CTR4 : 1; + __IO uint8_t CTR5 : 1; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + __IO uint8_t RLC0 : 1; + __IO uint8_t RLC1 : 1; + __IO uint8_t RLC2 : 1; + __IO uint8_t RLC3 : 1; + __IO uint8_t RLC4 : 1; + __IO uint8_t RLC5 : 1; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + __IO uint8_t WCIF : 1; + __IO uint8_t WCIE : 1; + __IO uint8_t CS0 : 1; + __IO uint8_t CS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t WCOP : 1; + __IO uint8_t WCEN : 1; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + __IO uint16_t SEL_IN : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t SEL_OUT : 1; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN : 1; + __IO uint8_t CLK_EN_R : 1; +} stc_wc_clk_en_field_t; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* EXBUS_MODULE register bit fields */ +typedef struct stc_exbus_mode0_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode0_field_t; + +typedef struct stc_exbus_mode1_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode1_field_t; + +typedef struct stc_exbus_mode2_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode2_field_t; + +typedef struct stc_exbus_mode3_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode3_field_t; + +typedef struct stc_exbus_mode4_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode4_field_t; + +typedef struct stc_exbus_mode5_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode5_field_t; + +typedef struct stc_exbus_mode6_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode6_field_t; + +typedef struct stc_exbus_mode7_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t TEST : 1; +} stc_exbus_mode7_field_t; + +typedef struct stc_exbus_tim0_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim0_field_t; + +typedef struct stc_exbus_tim1_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim1_field_t; + +typedef struct stc_exbus_tim2_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim2_field_t; + +typedef struct stc_exbus_tim3_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim3_field_t; + +typedef struct stc_exbus_tim4_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim4_field_t; + +typedef struct stc_exbus_tim5_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim5_field_t; + +typedef struct stc_exbus_tim6_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim6_field_t; + +typedef struct stc_exbus_tim7_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim7_field_t; + +typedef struct stc_exbus_area0_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area0_field_t; + +typedef struct stc_exbus_area1_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area1_field_t; + +typedef struct stc_exbus_area2_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area2_field_t; + +typedef struct stc_exbus_area3_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area3_field_t; + +typedef struct stc_exbus_area4_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area4_field_t; + +typedef struct stc_exbus_area5_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area5_field_t; + +typedef struct stc_exbus_area6_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area6_field_t; + +typedef struct stc_exbus_area7_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area7_field_t; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB_MODULE register bit fields */ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST : 1; + __IO uint16_t URST : 1; + __IO uint16_t SOFIRE : 1; + __IO uint16_t DIRE : 1; + __IO uint16_t CNNIRE : 1; + __IO uint16_t CMPIRE : 1; + __IO uint16_t URIRE : 1; + __IO uint16_t RWKIRE : 1; + __IO uint16_t RETRY : 1; + __IO uint16_t CANCEL : 1; + __IO uint16_t SOFSTEP : 1; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hcnt0_field +{ + __IO uint8_t HOST : 1; + __IO uint8_t URST : 1; + __IO uint8_t SOFIRE : 1; + __IO uint8_t DIRE : 1; + __IO uint8_t CNNIRE : 1; + __IO uint8_t CMPIRE : 1; + __IO uint8_t URIRE : 1; + __IO uint8_t RWKIRE : 1; +} stc_usb_hcnt0_field_t; + +typedef struct stc_usb_hcnt1_field +{ + __IO uint8_t RETRY : 1; + __IO uint8_t CANCEL : 1; + __IO uint8_t SOFSTEP : 1; +} stc_usb_hcnt1_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ : 1; + __IO uint8_t DIRQ : 1; + __IO uint8_t CNNIRQ : 1; + __IO uint8_t CMPIRQ : 1; + __IO uint8_t URIRQ : 1; + __IO uint8_t RWKIRQ : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TCAN : 1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + __IO uint8_t HS0 : 1; + __IO uint8_t HS1 : 1; + __IO uint8_t STUFF : 1; + __IO uint8_t TGERR : 1; + __IO uint8_t CRC : 1; + __IO uint8_t TOUT : 1; + __IO uint8_t RERR : 1; + __IO uint8_t LSTOF : 1; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT : 1; + __IO uint8_t TMODE : 1; + __IO uint8_t SUSP : 1; + __IO uint8_t SOFBUSY : 1; + __IO uint8_t CLKSEL : 1; + __IO uint8_t ALIVE : 1; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + __IO uint8_t FRAMECOMP0 : 1; + __IO uint8_t FRAMECOMP1 : 1; + __IO uint8_t FRAMECOMP2 : 1; + __IO uint8_t FRAMECOMP3 : 1; + __IO uint8_t FRAMECOMP4 : 1; + __IO uint8_t FRAMECOMP5 : 1; + __IO uint8_t FRAMECOMP6 : 1; + __IO uint8_t FRAMECOMP7 : 1; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + __IO uint16_t RTIMER0 : 1; + __IO uint16_t RTIMER1 : 1; + __IO uint16_t RTIMER2 : 1; + __IO uint16_t RTIMER3 : 1; + __IO uint16_t RTIMER4 : 1; + __IO uint16_t RTIMER5 : 1; + __IO uint16_t RTIMER6 : 1; + __IO uint16_t RTIMER7 : 1; + __IO uint16_t RTIMER8 : 1; + __IO uint16_t RTIMER9 : 1; + __IO uint16_t RTIMER10 : 1; + __IO uint16_t RTIMER11 : 1; + __IO uint16_t RTIMER12 : 1; + __IO uint16_t RTIMER13 : 1; + __IO uint16_t RTIMER14 : 1; + __IO uint16_t RTIMER15 : 1; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer0_field +{ + __IO uint8_t RTIMER00 : 1; + __IO uint8_t RTIMER01 : 1; + __IO uint8_t RTIMER02 : 1; + __IO uint8_t RTIMER03 : 1; + __IO uint8_t RTIMER04 : 1; + __IO uint8_t RTIMER05 : 1; + __IO uint8_t RTIMER06 : 1; + __IO uint8_t RTIMER07 : 1; +} stc_usb_hrtimer0_field_t; + +typedef struct stc_usb_hrtimer1_field +{ + __IO uint8_t RTIMER10 : 1; + __IO uint8_t RTIMER11 : 1; + __IO uint8_t RTIMER12 : 1; + __IO uint8_t RTIMER13 : 1; + __IO uint8_t RTIMER14 : 1; + __IO uint8_t RTIMER15 : 1; + __IO uint8_t RTIMER16 : 1; + __IO uint8_t RTIMER17 : 1; +} stc_usb_hrtimer1_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + __IO uint8_t RTIMER20 : 1; + __IO uint8_t RTIMER21 : 1; + __IO uint8_t RTIMER22 : 1; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + __IO uint8_t ADDRESS0 : 1; + __IO uint8_t ADDRESS1 : 1; + __IO uint8_t ADDRESS2 : 1; + __IO uint8_t ADDRESS3 : 1; + __IO uint8_t ADDRESS4 : 1; + __IO uint8_t ADDRESS5 : 1; + __IO uint8_t ADDRESS6 : 1; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + __IO uint16_t EOF0 : 1; + __IO uint16_t EOF1 : 1; + __IO uint16_t EOF2 : 1; + __IO uint16_t EOF3 : 1; + __IO uint16_t EOF4 : 1; + __IO uint16_t EOF5 : 1; + __IO uint16_t EOF6 : 1; + __IO uint16_t EOF7 : 1; + __IO uint16_t EOF8 : 1; + __IO uint16_t EOF9 : 1; + __IO uint16_t EOF10 : 1; + __IO uint16_t EOF11 : 1; + __IO uint16_t EOF12 : 1; + __IO uint16_t EOF13 : 1; + __IO uint16_t EOF14 : 1; + __IO uint16_t EOF15 : 1; +} stc_usb_heof_field_t; + +typedef struct stc_usb_heof0_field +{ + __IO uint8_t EOF00 : 1; + __IO uint8_t EOF01 : 1; + __IO uint8_t EOF02 : 1; + __IO uint8_t EOF03 : 1; + __IO uint8_t EOF04 : 1; + __IO uint8_t EOF05 : 1; + __IO uint8_t EOF06 : 1; + __IO uint8_t EOF07 : 1; +} stc_usb_heof0_field_t; + +typedef struct stc_usb_heof1_field +{ + __IO uint8_t EOF10 : 1; + __IO uint8_t EOF11 : 1; + __IO uint8_t EOF12 : 1; + __IO uint8_t EOF13 : 1; + __IO uint8_t EOF14 : 1; + __IO uint8_t EOF15 : 1; +} stc_usb_heof1_field_t; + +typedef struct stc_usb_hframe_field +{ + __IO uint16_t FRAME0 : 1; + __IO uint16_t FRAME1 : 1; + __IO uint16_t FRAME2 : 1; + __IO uint16_t FRAME3 : 1; + __IO uint16_t FRAME4 : 1; + __IO uint16_t FRAME5 : 1; + __IO uint16_t FRAME6 : 1; + __IO uint16_t FRAME7 : 1; + __IO uint16_t FRAME8 : 1; + __IO uint16_t FRAME9 : 1; + __IO uint16_t FRAME10 : 1; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_hframe0_field +{ + __IO uint8_t FRAME00 : 1; + __IO uint8_t FRAME01 : 1; + __IO uint8_t FRAME02 : 1; + __IO uint8_t FRAME03 : 1; + __IO uint8_t FRAME04 : 1; + __IO uint8_t FRAME05 : 1; + __IO uint8_t FRAME06 : 1; + __IO uint8_t FRAME07 : 1; +} stc_usb_hframe0_field_t; + +typedef struct stc_usb_hframe1_field +{ + __IO uint8_t FRAME10 : 1; + __IO uint8_t FRAME11 : 1; + __IO uint8_t FRAME12 : 1; + __IO uint8_t FRAME13 : 1; +} stc_usb_hframe1_field_t; + +typedef struct stc_usb_htoken_field +{ + __IO uint8_t ENDPT0 : 1; + __IO uint8_t ENDPT1 : 1; + __IO uint8_t ENDPT2 : 1; + __IO uint8_t ENDPT3 : 1; + __IO uint8_t TKNEN0 : 1; + __IO uint8_t TKNEN1 : 1; + __IO uint8_t TKNEN2 : 1; + __IO uint8_t TGGL : 1; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC : 1; + __IO uint16_t RFBK : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t STALCLREN : 1; + __IO uint16_t USTP : 1; + __IO uint16_t HCONX : 1; + __IO uint16_t RESUM : 1; + __IO uint16_t RST : 1; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + __IO uint16_t PKS00 : 1; + __IO uint16_t PKS01 : 1; + __IO uint16_t PKS02 : 1; + __IO uint16_t PKS03 : 1; + __IO uint16_t PKS04 : 1; + __IO uint16_t PKS05 : 1; + __IO uint16_t PKS06 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + __IO uint16_t PKS10 : 1; + __IO uint16_t PKS11 : 1; + __IO uint16_t PKS12 : 1; + __IO uint16_t PKS13 : 1; + __IO uint16_t PKS14 : 1; + __IO uint16_t PKS15 : 1; + __IO uint16_t PKS16 : 1; + __IO uint16_t PKS17 : 1; + __IO uint16_t PKS18 : 1; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + __IO uint16_t PKS20 : 1; + __IO uint16_t PKS21 : 1; + __IO uint16_t PKS22 : 1; + __IO uint16_t PKS23 : 1; + __IO uint16_t PKS24 : 1; + __IO uint16_t PKS25 : 1; + __IO uint16_t PKS26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + __IO uint16_t PKS30 : 1; + __IO uint16_t PKS31 : 1; + __IO uint16_t PKS32 : 1; + __IO uint16_t PKS33 : 1; + __IO uint16_t PKS34 : 1; + __IO uint16_t PKS35 : 1; + __IO uint16_t PKS36 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + __IO uint16_t PKS40 : 1; + __IO uint16_t PKS41 : 1; + __IO uint16_t PKS42 : 1; + __IO uint16_t PKS43 : 1; + __IO uint16_t PKS44 : 1; + __IO uint16_t PKS45 : 1; + __IO uint16_t PKS46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + __IO uint16_t PKS50 : 1; + __IO uint16_t PKS51 : 1; + __IO uint16_t PKS52 : 1; + __IO uint16_t PKS53 : 1; + __IO uint16_t PKS54 : 1; + __IO uint16_t PKS55 : 1; + __IO uint16_t PKS56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + __IO uint16_t TMSP0 : 1; + __IO uint16_t TMSP1 : 1; + __IO uint16_t TMSP2 : 1; + __IO uint16_t TMSP3 : 1; + __IO uint16_t TMSP4 : 1; + __IO uint16_t TMSP5 : 1; + __IO uint16_t TMSP6 : 1; + __IO uint16_t TMSP7 : 1; + __IO uint16_t TMSP8 : 1; + __IO uint16_t TMSP9 : 1; + __IO uint16_t TMSP10 : 1; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF : 1; + __IO uint8_t SETP : 1; + __IO uint8_t WKUP : 1; + __IO uint8_t BRST : 1; + __IO uint8_t SOF : 1; + __IO uint8_t SUSP : 1; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE : 1; + __IO uint8_t CONFN : 1; + __IO uint8_t WKUPIE : 1; + __IO uint8_t BRSTIE : 1; + __IO uint8_t SOFIE : 1; + __IO uint8_t SUSPIE : 1; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + uint16_t RESERVED1 : 10; + __IO uint16_t DRQI : 1; + uint16_t RESERVED2 : 3; + __IO uint16_t DRQIIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + __IO uint16_t SIZE0 : 1; + __IO uint16_t SIZE1 : 1; + __IO uint16_t SIZE2 : 1; + __IO uint16_t SIZE3 : 1; + __IO uint16_t SIZE4 : 1; + __IO uint16_t SIZE5 : 1; + __IO uint16_t SIZE6 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQO : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQOIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + __IO uint16_t SIZE10 : 1; + __IO uint16_t SIZE11 : 1; + __IO uint16_t SIZE12 : 1; + __IO uint16_t SIZE13 : 1; + __IO uint16_t SIZE14 : 1; + __IO uint16_t SIZE15 : 1; + __IO uint16_t SIZE16 : 1; + __IO uint16_t SIZE17 : 1; + __IO uint16_t SIZE18 : 1; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + __IO uint16_t SIZE20 : 1; + __IO uint16_t SIZE21 : 1; + __IO uint16_t SIZE22 : 1; + __IO uint16_t SIZE23 : 1; + __IO uint16_t SIZE24 : 1; + __IO uint16_t SIZE25 : 1; + __IO uint16_t SIZE26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep4s_field +{ + __IO uint16_t SIZE40 : 1; + __IO uint16_t SIZE41 : 1; + __IO uint16_t SIZE42 : 1; + __IO uint16_t SIZE43 : 1; + __IO uint16_t SIZE44 : 1; + __IO uint16_t SIZE45 : 1; + __IO uint16_t SIZE46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + __IO uint16_t SIZE50 : 1; + __IO uint16_t SIZE51 : 1; + __IO uint16_t SIZE52 : 1; + __IO uint16_t SIZE53 : 1; + __IO uint16_t SIZE54 : 1; + __IO uint16_t SIZE55 : 1; + __IO uint16_t SIZE56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep5s_field_t; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMAC_MODULE register bit fields */ +typedef struct stc_dmac_dmacr_field +{ + uint32_t RESERVED1 : 24; + __IO uint32_t DH0 : 1; + __IO uint32_t DH1 : 1; + __IO uint32_t DH2 : 1; + __IO uint32_t DH3 : 1; + __IO uint32_t PR : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t DS : 1; + __IO uint32_t DE : 1; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb7_field_t; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN_MODULE register bit fields */ +typedef struct stc_can_ctrlr_field +{ + __IO uint16_t INIT : 1; + __IO uint16_t IE : 1; + __IO uint16_t SIE : 1; + __IO uint16_t EIE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t DAR : 1; + __IO uint16_t CCE : 1; + __IO uint16_t TEST : 1; +} stc_can_ctrlr_field_t; + +typedef struct stc_can_statr_field +{ + __IO uint16_t LEC0 : 1; + __IO uint16_t LEC1 : 1; + __IO uint16_t LEC2 : 1; + __IO uint16_t TXOK : 1; + __IO uint16_t RXOK : 1; + __IO uint16_t EPASS : 1; + __IO uint16_t EWARM : 1; + __IO uint16_t BOFF : 1; +} stc_can_statr_field_t; + +typedef struct stc_can_errcnt_field +{ + __IO uint16_t TEC0 : 1; + __IO uint16_t TEC1 : 1; + __IO uint16_t TEC2 : 1; + __IO uint16_t TEC3 : 1; + __IO uint16_t TEC4 : 1; + __IO uint16_t TEC5 : 1; + __IO uint16_t TEC6 : 1; + __IO uint16_t TEC7 : 1; + __IO uint16_t REC0 : 1; + __IO uint16_t REC1 : 1; + __IO uint16_t REC2 : 1; + __IO uint16_t REC3 : 1; + __IO uint16_t REC4 : 1; + __IO uint16_t REC5 : 1; + __IO uint16_t REC6 : 1; + __IO uint16_t RP : 1; +} stc_can_errcnt_field_t; + +typedef struct stc_can_btr_field +{ + __IO uint16_t BRP0 : 1; + __IO uint16_t BRP1 : 1; + __IO uint16_t BRP2 : 1; + __IO uint16_t BRP3 : 1; + __IO uint16_t BRP4 : 1; + __IO uint16_t BRP5 : 1; + __IO uint16_t SJW0 : 1; + __IO uint16_t SJW1 : 1; + __IO uint16_t TSEG10 : 1; + __IO uint16_t TSEG11 : 1; + __IO uint16_t TSEG12 : 1; + __IO uint16_t TSEG13 : 1; + __IO uint16_t TSEG20 : 1; + __IO uint16_t TSEG21 : 1; + __IO uint16_t TSEG22 : 1; +} stc_can_btr_field_t; + +typedef struct stc_can_intr_field +{ + __IO uint16_t INTID0 : 1; + __IO uint16_t INTID1 : 1; + __IO uint16_t INTID2 : 1; + __IO uint16_t INTID3 : 1; + __IO uint16_t INTID4 : 1; + __IO uint16_t INTID5 : 1; + __IO uint16_t INTID6 : 1; + __IO uint16_t INTID7 : 1; + __IO uint16_t INTID8 : 1; + __IO uint16_t INTID9 : 1; + __IO uint16_t INTID10 : 1; + __IO uint16_t INTID11 : 1; + __IO uint16_t INTID12 : 1; + __IO uint16_t INTID13 : 1; + __IO uint16_t INTID14 : 1; + __IO uint16_t INTID15 : 1; +} stc_can_intr_field_t; + +typedef struct stc_can_testr_field +{ + uint16_t RESERVED1 : 2; + __IO uint16_t BASIC : 1; + __IO uint16_t SILENT : 1; + __IO uint16_t LBACK : 1; + __IO uint16_t TX0 : 1; + __IO uint16_t TX1 : 1; + __IO uint16_t RX : 1; +} stc_can_testr_field_t; + +typedef struct stc_can_brper_field +{ + __IO uint16_t BRPE0 : 1; + __IO uint16_t BRPE1 : 1; + __IO uint16_t BRPE2 : 1; + __IO uint16_t BRPE3 : 1; +} stc_can_brper_field_t; + +typedef struct stc_can_if1creq_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t BUSY : 1; +} stc_can_if1creq_field_t; + +typedef struct stc_can_if1cmsk_field +{ + __IO uint16_t DATAB : 1; + __IO uint16_t DATAA : 1; + __IO uint16_t NEWDAT : 1; + __IO uint16_t CIP : 1; + __IO uint16_t CONTROL : 1; + __IO uint16_t ARB : 1; + __IO uint16_t MASK : 1; + __IO uint16_t WRRD : 1; +} stc_can_if1cmsk_field_t; + +typedef struct stc_can_if1msk_field +{ + uint32_t RESERVED1 : 30; + __IO uint32_t MDIR : 1; + __IO uint32_t MXTD : 1; +} stc_can_if1msk_field_t; + +typedef struct stc_can_if1msk2_field +{ + uint16_t RESERVED1 : 14; + __IO uint16_t MDIR : 1; + __IO uint16_t MXTD : 1; +} stc_can_if1msk2_field_t; + +typedef struct stc_can_if1arb_field +{ + uint32_t RESERVED1 : 29; + __IO uint32_t DIR : 1; + __IO uint32_t XTD : 1; + __IO uint32_t MSGVAL : 1; +} stc_can_if1arb_field_t; + +typedef struct stc_can_if1arb2_field +{ + uint16_t RESERVED1 : 13; + __IO uint16_t DIR : 1; + __IO uint16_t XTD : 1; + __IO uint16_t MSGVAL : 1; +} stc_can_if1arb2_field_t; + +typedef struct stc_can_if1mctr_field +{ + __IO uint16_t DLC0 : 1; + __IO uint16_t DLC1 : 1; + __IO uint16_t DLC2 : 1; + __IO uint16_t DLC3 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t EOB : 1; + __IO uint16_t TXRQST : 1; + __IO uint16_t RMTEN : 1; + __IO uint16_t RXIE : 1; + __IO uint16_t TXIE : 1; + __IO uint16_t UMASK : 1; + __IO uint16_t INTPND : 1; + __IO uint16_t MSGLST : 1; + __IO uint16_t NEWDAT : 1; +} stc_can_if1mctr_field_t; + +typedef struct stc_can_if2creq_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t BUSY : 1; +} stc_can_if2creq_field_t; + +typedef struct stc_can_if2cmsk_field +{ + __IO uint16_t DATAB : 1; + __IO uint16_t DATAA : 1; + __IO uint16_t NEWDAT : 1; + __IO uint16_t CIP : 1; + __IO uint16_t CONTROL : 1; + __IO uint16_t ARB : 1; + __IO uint16_t MASK : 1; + __IO uint16_t WRRD : 1; +} stc_can_if2cmsk_field_t; + +typedef struct stc_can_if2msk_field +{ + uint32_t RESERVED1 : 30; + __IO uint32_t MDIR : 1; + __IO uint32_t MXTD : 1; +} stc_can_if2msk_field_t; + +typedef struct stc_can_if2msk2_field +{ + uint16_t RESERVED1 : 14; + __IO uint16_t MDIR : 1; + __IO uint16_t MXTD : 1; +} stc_can_if2msk2_field_t; + +typedef struct stc_can_if2arb2_field +{ + uint16_t RESERVED1 : 13; + __IO uint16_t DIR : 1; + __IO uint16_t XTD : 1; + __IO uint16_t MSGVAL : 1; +} stc_can_if2arb2_field_t; + +typedef struct stc_can_if2mctr_field +{ + __IO uint16_t DLC0 : 1; + __IO uint16_t DLC1 : 1; + __IO uint16_t DLC2 : 1; + __IO uint16_t DLC3 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t EOB : 1; + __IO uint16_t TXRQST : 1; + __IO uint16_t RMTEN : 1; + __IO uint16_t RXIE : 1; + __IO uint16_t TXIE : 1; + __IO uint16_t UMASK : 1; + __IO uint16_t INTPND : 1; + __IO uint16_t MSGLST : 1; + __IO uint16_t NEWDAT : 1; +} stc_can_if2mctr_field_t; + +typedef struct stc_can_treqr_field +{ + __IO uint32_t TXRQST1 : 1; + __IO uint32_t TXRQST2 : 1; + __IO uint32_t TXRQST3 : 1; + __IO uint32_t TXRQST4 : 1; + __IO uint32_t TXRQST5 : 1; + __IO uint32_t TXRQST6 : 1; + __IO uint32_t TXRQST7 : 1; + __IO uint32_t TXRQST8 : 1; + __IO uint32_t TXRQST9 : 1; + __IO uint32_t TXRQST10 : 1; + __IO uint32_t TXRQST11 : 1; + __IO uint32_t TXRQST12 : 1; + __IO uint32_t TXRQST13 : 1; + __IO uint32_t TXRQST14 : 1; + __IO uint32_t TXRQST15 : 1; + __IO uint32_t TXRQST16 : 1; + __IO uint32_t TXRQST17 : 1; + __IO uint32_t TXRQST18 : 1; + __IO uint32_t TXRQST19 : 1; + __IO uint32_t TXRQST20 : 1; + __IO uint32_t TXRQST21 : 1; + __IO uint32_t TXRQST22 : 1; + __IO uint32_t TXRQST23 : 1; + __IO uint32_t TXRQST24 : 1; + __IO uint32_t TXRQST25 : 1; + __IO uint32_t TXRQST26 : 1; + __IO uint32_t TXRQST27 : 1; + __IO uint32_t TXRQST28 : 1; + __IO uint32_t TXRQST29 : 1; + __IO uint32_t TXRQST30 : 1; + __IO uint32_t TXRQST31 : 1; + __IO uint32_t TXRQST32 : 1; +} stc_can_treqr_field_t; + +typedef struct stc_can_treqr1_field +{ + __IO uint16_t TXRQST1 : 1; + __IO uint16_t TXRQST2 : 1; + __IO uint16_t TXRQST3 : 1; + __IO uint16_t TXRQST4 : 1; + __IO uint16_t TXRQST5 : 1; + __IO uint16_t TXRQST6 : 1; + __IO uint16_t TXRQST7 : 1; + __IO uint16_t TXRQST8 : 1; + __IO uint16_t TXRQST9 : 1; + __IO uint16_t TXRQST10 : 1; + __IO uint16_t TXRQST11 : 1; + __IO uint16_t TXRQST12 : 1; + __IO uint16_t TXRQST13 : 1; + __IO uint16_t TXRQST14 : 1; + __IO uint16_t TXRQST15 : 1; + __IO uint16_t TXRQST16 : 1; +} stc_can_treqr1_field_t; + +typedef struct stc_can_treqr2_field +{ + __IO uint16_t TXRQST17 : 1; + __IO uint16_t TXRQST18 : 1; + __IO uint16_t TXRQST19 : 1; + __IO uint16_t TXRQST20 : 1; + __IO uint16_t TXRQST21 : 1; + __IO uint16_t TXRQST22 : 1; + __IO uint16_t TXRQST23 : 1; + __IO uint16_t TXRQST24 : 1; + __IO uint16_t TXRQST25 : 1; + __IO uint16_t TXRQST26 : 1; + __IO uint16_t TXRQST27 : 1; + __IO uint16_t TXRQST28 : 1; + __IO uint16_t TXRQST29 : 1; + __IO uint16_t TXRQST30 : 1; + __IO uint16_t TXRQST31 : 1; + __IO uint16_t TXRQST32 : 1; +} stc_can_treqr2_field_t; + +typedef struct stc_can_newdt_field +{ + __IO uint32_t NEWDAT1 : 1; + __IO uint32_t NEWDAT2 : 1; + __IO uint32_t NEWDAT3 : 1; + __IO uint32_t NEWDAT4 : 1; + __IO uint32_t NEWDAT5 : 1; + __IO uint32_t NEWDAT6 : 1; + __IO uint32_t NEWDAT7 : 1; + __IO uint32_t NEWDAT8 : 1; + __IO uint32_t NEWDAT9 : 1; + __IO uint32_t NEWDAT10 : 1; + __IO uint32_t NEWDAT11 : 1; + __IO uint32_t NEWDAT12 : 1; + __IO uint32_t NEWDAT13 : 1; + __IO uint32_t NEWDAT14 : 1; + __IO uint32_t NEWDAT15 : 1; + __IO uint32_t NEWDAT16 : 1; + __IO uint32_t NEWDAT17 : 1; + __IO uint32_t NEWDAT18 : 1; + __IO uint32_t NEWDAT19 : 1; + __IO uint32_t NEWDAT20 : 1; + __IO uint32_t NEWDAT21 : 1; + __IO uint32_t NEWDAT22 : 1; + __IO uint32_t NEWDAT23 : 1; + __IO uint32_t NEWDAT24 : 1; + __IO uint32_t NEWDAT25 : 1; + __IO uint32_t NEWDAT26 : 1; + __IO uint32_t NEWDAT27 : 1; + __IO uint32_t NEWDAT28 : 1; + __IO uint32_t NEWDAT29 : 1; + __IO uint32_t NEWDAT30 : 1; + __IO uint32_t NEWDAT31 : 1; + __IO uint32_t NEWDAT32 : 1; +} stc_can_newdt_field_t; + +typedef struct stc_can_newdt1_field +{ + __IO uint16_t NEWDAT1 : 1; + __IO uint16_t NEWDAT2 : 1; + __IO uint16_t NEWDAT3 : 1; + __IO uint16_t NEWDAT4 : 1; + __IO uint16_t NEWDAT5 : 1; + __IO uint16_t NEWDAT6 : 1; + __IO uint16_t NEWDAT7 : 1; + __IO uint16_t NEWDAT8 : 1; + __IO uint16_t NEWDAT9 : 1; + __IO uint16_t NEWDAT10 : 1; + __IO uint16_t NEWDAT11 : 1; + __IO uint16_t NEWDAT12 : 1; + __IO uint16_t NEWDAT13 : 1; + __IO uint16_t NEWDAT14 : 1; + __IO uint16_t NEWDAT15 : 1; + __IO uint16_t NEWDAT16 : 1; +} stc_can_newdt1_field_t; + +typedef struct stc_can_intpnd_field +{ + __IO uint32_t INTPND1 : 1; + __IO uint32_t INTPND2 : 1; + __IO uint32_t INTPND3 : 1; + __IO uint32_t INTPND4 : 1; + __IO uint32_t INTPND5 : 1; + __IO uint32_t INTPND6 : 1; + __IO uint32_t INTPND7 : 1; + __IO uint32_t INTPND8 : 1; + __IO uint32_t INTPND9 : 1; + __IO uint32_t INTPND10 : 1; + __IO uint32_t INTPND11 : 1; + __IO uint32_t INTPND12 : 1; + __IO uint32_t INTPND13 : 1; + __IO uint32_t INTPND14 : 1; + __IO uint32_t INTPND15 : 1; + __IO uint32_t INTPND16 : 1; + __IO uint32_t INTPND17 : 1; + __IO uint32_t INTPND18 : 1; + __IO uint32_t INTPND19 : 1; + __IO uint32_t INTPND20 : 1; + __IO uint32_t INTPND21 : 1; + __IO uint32_t INTPND22 : 1; + __IO uint32_t INTPND23 : 1; + __IO uint32_t INTPND24 : 1; + __IO uint32_t INTPND25 : 1; + __IO uint32_t INTPND26 : 1; + __IO uint32_t INTPND27 : 1; + __IO uint32_t INTPND28 : 1; + __IO uint32_t INTPND29 : 1; + __IO uint32_t INTPND30 : 1; + __IO uint32_t INTPND31 : 1; + __IO uint32_t INTPND32 : 1; +} stc_can_intpnd_field_t; + +typedef struct stc_can_intpnd1_field +{ + __IO uint16_t INTPND1 : 1; + __IO uint16_t INTPND2 : 1; + __IO uint16_t INTPND3 : 1; + __IO uint16_t INTPND4 : 1; + __IO uint16_t INTPND5 : 1; + __IO uint16_t INTPND6 : 1; + __IO uint16_t INTPND7 : 1; + __IO uint16_t INTPND8 : 1; + __IO uint16_t INTPND9 : 1; + __IO uint16_t INTPND10 : 1; + __IO uint16_t INTPND11 : 1; + __IO uint16_t INTPND12 : 1; + __IO uint16_t INTPND13 : 1; + __IO uint16_t INTPND14 : 1; + __IO uint16_t INTPND15 : 1; + __IO uint16_t INTPND16 : 1; +} stc_can_intpnd1_field_t; + +typedef struct stc_can_intpnd2_field +{ + __IO uint16_t INTPND17 : 1; + __IO uint16_t INTPND18 : 1; + __IO uint16_t INTPND19 : 1; + __IO uint16_t INTPND20 : 1; + __IO uint16_t INTPND21 : 1; + __IO uint16_t INTPND22 : 1; + __IO uint16_t INTPND23 : 1; + __IO uint16_t INTPND24 : 1; + __IO uint16_t INTPND25 : 1; + __IO uint16_t INTPND26 : 1; + __IO uint16_t INTPND27 : 1; + __IO uint16_t INTPND28 : 1; + __IO uint16_t INTPND29 : 1; + __IO uint16_t INTPND30 : 1; + __IO uint16_t INTPND31 : 1; + __IO uint16_t INTPND32 : 1; +} stc_can_intpnd2_field_t; + +typedef struct stc_can_msgval_field +{ + __IO uint32_t MSGVAL1 : 1; + __IO uint32_t MSGVAL2 : 1; + __IO uint32_t MSGVAL3 : 1; + __IO uint32_t MSGVAL4 : 1; + __IO uint32_t MSGVAL5 : 1; + __IO uint32_t MSGVAL6 : 1; + __IO uint32_t MSGVAL7 : 1; + __IO uint32_t MSGVAL8 : 1; + __IO uint32_t MSGVAL9 : 1; + __IO uint32_t MSGVAL10 : 1; + __IO uint32_t MSGVAL11 : 1; + __IO uint32_t MSGVAL12 : 1; + __IO uint32_t MSGVAL13 : 1; + __IO uint32_t MSGVAL14 : 1; + __IO uint32_t MSGVAL15 : 1; + __IO uint32_t MSGVAL16 : 1; + __IO uint32_t MSGVAL17 : 1; + __IO uint32_t MSGVAL18 : 1; + __IO uint32_t MSGVAL19 : 1; + __IO uint32_t MSGVAL20 : 1; + __IO uint32_t MSGVAL21 : 1; + __IO uint32_t MSGVAL22 : 1; + __IO uint32_t MSGVAL23 : 1; + __IO uint32_t MSGVAL24 : 1; + __IO uint32_t MSGVAL25 : 1; + __IO uint32_t MSGVAL26 : 1; + __IO uint32_t MSGVAL27 : 1; + __IO uint32_t MSGVAL28 : 1; + __IO uint32_t MSGVAL29 : 1; + __IO uint32_t MSGVAL30 : 1; + __IO uint32_t MSGVAL31 : 1; + __IO uint32_t MSGVAL32 : 1; +} stc_can_msgval_field_t; + +typedef struct stc_can_msgval1_field +{ + __IO uint16_t MSGVAL1 : 1; + __IO uint16_t MSGVAL2 : 1; + __IO uint16_t MSGVAL3 : 1; + __IO uint16_t MSGVAL4 : 1; + __IO uint16_t MSGVAL5 : 1; + __IO uint16_t MSGVAL6 : 1; + __IO uint16_t MSGVAL7 : 1; + __IO uint16_t MSGVAL8 : 1; + __IO uint16_t MSGVAL9 : 1; + __IO uint16_t MSGVAL10 : 1; + __IO uint16_t MSGVAL11 : 1; + __IO uint16_t MSGVAL12 : 1; + __IO uint16_t MSGVAL13 : 1; + __IO uint16_t MSGVAL14 : 1; + __IO uint16_t MSGVAL15 : 1; + __IO uint16_t MSGVAL16 : 1; +} stc_can_msgval1_field_t; + +typedef struct stc_can_msgval2_field +{ + __IO uint16_t MSGVAL17 : 1; + __IO uint16_t MSGVAL18 : 1; + __IO uint16_t MSGVAL19 : 1; + __IO uint16_t MSGVAL20 : 1; + __IO uint16_t MSGVAL21 : 1; + __IO uint16_t MSGVAL22 : 1; + __IO uint16_t MSGVAL23 : 1; + __IO uint16_t MSGVAL24 : 1; + __IO uint16_t MSGVAL25 : 1; + __IO uint16_t MSGVAL26 : 1; + __IO uint16_t MSGVAL27 : 1; + __IO uint16_t MSGVAL28 : 1; + __IO uint16_t MSGVAL29 : 1; + __IO uint16_t MSGVAL30 : 1; + __IO uint16_t MSGVAL31 : 1; + __IO uint16_t MSGVAL32 : 1; +} stc_can_msgval2_field_t; + + +/****************************************************************************** + * Peripheral register structures + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + }; + uint8_t RESERVED0[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + }; + uint8_t RESERVED1[236]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + }; +}FM3_FLASH_IF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + union { + __IO uint8_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + }; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + union { + __IO uint16_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + }; + uint8_t RESERVED7[7]; + union { + __IO uint8_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + }; + uint8_t RESERVED8[7]; + union { + __IO uint8_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint16_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint8_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + }; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + union { + __IO uint8_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + }; + uint8_t RESERVED18[11]; + union { + __IO uint8_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + }; + uint8_t RESERVED19[3]; + union { + __IO uint8_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + }; + uint8_t RESERVED20[3]; + union { + __IO uint8_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + }; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + union { + __IO uint8_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + }; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + }; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + union { + __IO uint8_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + union { + __IO uint8_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + }; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + union { + __IO uint32_t TIMER1CONTROL; + stc_dtim_timer1control_field_t TIMER1CONTROL_f; + }; + __IO uint32_t TIMER1INTCLR; + union { + __IO uint32_t TIMER1RIS; + stc_dtim_timer1ris_field_t TIMER1RIS_f; + }; + union { + __IO uint32_t TIMER1MIS; + stc_dtim_timer1mis_field_t TIMER1MIS_f; + }; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + union { + __IO uint32_t TIMER2CONTROL; + stc_dtim_timer2control_field_t TIMER2CONTROL_f; + }; + __IO uint32_t TIMER2INTCLR; + union { + __IO uint32_t TIMER2RIS; + stc_dtim_timer2ris_field_t TIMER2RIS_f; + }; + union { + __IO uint32_t TIMER2MIS; + stc_dtim_timer2mis_field_t TIMER2MIS_f; + }; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t TCSB0; + stc_mft_frt_tcsb0_field_t TCSB0_f; + }; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t TCSB1; + stc_mft_frt_tcsb1_field_t TCSB1_f; + }; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t TCSB2; + stc_mft_frt_tcsb2_field_t TCSB2_f; + }; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + uint8_t RESERVED9[50]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + }; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ACSB; + stc_mft_adcmp_acsb_field_t ACSB_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ATSA; + stc_mft_adcmp_atsa_field_t ATSA_f; + }; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[203]; + union { + __IO uint16_t TRG; + stc_mft_ppg_trg_field_t TRG_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t REVC; + stc_mft_ppg_revc_field_t REVC_f; + }; + uint8_t RESERVED12[250]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED15[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED18[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + uint8_t RESERVED19[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + uint8_t RESERVED20[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + uint8_t RESERVED26[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + uint8_t RESERVED27[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED32[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + uint8_t RESERVED33[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + uint8_t RESERVED34[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED39[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + }; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t QICR; + stc_qprc_qicr_field_t QICR_f; + }; + struct { + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + }; + struct { + union { + __IO uint8_t QCRL; + stc_qprc_qcrl_field_t QCRL_f; + }; + union { + __IO uint8_t QCRH; + stc_qprc_qcrh_field_t QCRH_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + }; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + }; + struct { + union { + __IO uint16_t SCFDL; + stc_adc_scfdl_field_t SCFDL_f; + }; + union { + __IO uint16_t SCFDH; + stc_adc_scfdh_field_t SCFDH_f; + }; + }; + }; + union { + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + }; + struct { + union { + __IO uint8_t SCIS2; + stc_adc_scis2_field_t SCIS2_f; + }; + union { + __IO uint8_t SCIS3; + stc_adc_scis3_field_t SCIS3_f; + }; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + }; + struct { + union { + __IO uint8_t SCIS0; + stc_adc_scis0_field_t SCIS0_f; + }; + union { + __IO uint8_t SCIS1; + stc_adc_scis1_field_t SCIS1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + }; + struct { + union { + __IO uint16_t PCFDL; + stc_adc_pcfdl_field_t PCFDL_f; + }; + union { + __IO uint16_t PCFDH; + stc_adc_pcfdh_field_t PCFDH_f; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + uint8_t RESERVED6; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + }; + union { + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + }; + struct { + union { + __IO uint8_t ADSS2; + stc_adc_adss2_field_t ADSS2_f; + }; + union { + __IO uint8_t ADSS3; + stc_adc_adss3_field_t ADSS3_f; + }; + }; + }; + uint8_t RESERVED7[2]; + union { + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + }; + struct { + union { + __IO uint8_t ADSS0; + stc_adc_adss0_field_t ADSS0_f; + }; + union { + __IO uint8_t ADSS1; + stc_adc_adss1_field_t ADSS1_f; + }; + }; + }; + uint8_t RESERVED8[2]; + union { + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + }; + struct { + union { + __IO uint8_t ADST1; + stc_adc_adst1_field_t ADST1_f; + }; + union { + __IO uint8_t ADST0; + stc_adc_adst0_field_t ADST0_f; + }; + }; + }; + uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint8_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + }; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint16_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + }; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + union { + __IO uint16_t ENIR; + stc_exti_enir_field_t ENIR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint16_t EIRR; + stc_exti_eirr_field_t EIRR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t EICL; + stc_exti_eicl_field_t EICL_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + }; + uint8_t RESERVED3[4]; + union { + __IO uint8_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + }; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + }; + union { + __IO uint32_t IRQ00MON; + stc_intreq_irq00mon_field_t IRQ00MON_f; + }; + union { + __IO uint32_t IRQ01MON; + stc_intreq_irq01mon_field_t IRQ01MON_f; + }; + union { + __IO uint32_t IRQ02MON; + stc_intreq_irq02mon_field_t IRQ02MON_f; + }; + union { + __IO uint32_t IRQ03MON; + stc_intreq_irq03mon_field_t IRQ03MON_f; + }; + union { + __IO uint32_t IRQ04MON; + stc_intreq_irq04mon_field_t IRQ04MON_f; + }; + union { + __IO uint32_t IRQ05MON; + stc_intreq_irq05mon_field_t IRQ05MON_f; + }; + union { + __IO uint32_t IRQ06MON; + stc_intreq_irq06mon_field_t IRQ06MON_f; + }; + union { + __IO uint32_t IRQ07MON; + stc_intreq_irq07mon_field_t IRQ07MON_f; + }; + union { + __IO uint32_t IRQ08MON; + stc_intreq_irq08mon_field_t IRQ08MON_f; + }; + union { + __IO uint32_t IRQ09MON; + stc_intreq_irq09mon_field_t IRQ09MON_f; + }; + union { + __IO uint32_t IRQ10MON; + stc_intreq_irq10mon_field_t IRQ10MON_f; + }; + union { + __IO uint32_t IRQ11MON; + stc_intreq_irq11mon_field_t IRQ11MON_f; + }; + union { + __IO uint32_t IRQ12MON; + stc_intreq_irq12mon_field_t IRQ12MON_f; + }; + union { + __IO uint32_t IRQ13MON; + stc_intreq_irq13mon_field_t IRQ13MON_f; + }; + union { + __IO uint32_t IRQ14MON; + stc_intreq_irq14mon_field_t IRQ14MON_f; + }; + union { + __IO uint32_t IRQ15MON; + stc_intreq_irq15mon_field_t IRQ15MON_f; + }; + union { + __IO uint32_t IRQ16MON; + stc_intreq_irq16mon_field_t IRQ16MON_f; + }; + union { + __IO uint32_t IRQ17MON; + stc_intreq_irq17mon_field_t IRQ17MON_f; + }; + union { + __IO uint32_t IRQ18MON; + stc_intreq_irq18mon_field_t IRQ18MON_f; + }; + union { + __IO uint32_t IRQ19MON; + stc_intreq_irq19mon_field_t IRQ19MON_f; + }; + union { + __IO uint32_t IRQ20MON; + stc_intreq_irq20mon_field_t IRQ20MON_f; + }; + union { + __IO uint32_t IRQ21MON; + stc_intreq_irq21mon_field_t IRQ21MON_f; + }; + union { + __IO uint32_t IRQ22MON; + stc_intreq_irq22mon_field_t IRQ22MON_f; + }; + union { + __IO uint32_t IRQ23MON; + stc_intreq_irq23mon_field_t IRQ23MON_f; + }; + union { + __IO uint32_t IRQ24MON; + stc_intreq_irq24mon_field_t IRQ24MON_f; + }; + union { + __IO uint32_t IRQ25MON; + stc_intreq_irq25mon_field_t IRQ25MON_f; + }; + union { + __IO uint32_t IRQ26MON; + stc_intreq_irq26mon_field_t IRQ26MON_f; + }; + union { + __IO uint32_t IRQ27MON; + stc_intreq_irq27mon_field_t IRQ27MON_f; + }; + union { + __IO uint32_t IRQ28MON; + stc_intreq_irq28mon_field_t IRQ28MON_f; + }; + union { + __IO uint32_t IRQ29MON; + stc_intreq_irq29mon_field_t IRQ29MON_f; + }; + union { + __IO uint32_t IRQ30MON; + stc_intreq_irq30mon_field_t IRQ30MON_f; + }; + union { + __IO uint32_t IRQ31MON; + stc_intreq_irq31mon_field_t IRQ31MON_f; + }; + union { + __IO uint32_t IRQ32MON; + stc_intreq_irq32mon_field_t IRQ32MON_f; + }; + union { + __IO uint32_t IRQ33MON; + stc_intreq_irq33mon_field_t IRQ33MON_f; + }; + union { + __IO uint32_t IRQ34MON; + stc_intreq_irq34mon_field_t IRQ34MON_f; + }; + union { + __IO uint32_t IRQ35MON; + stc_intreq_irq35mon_field_t IRQ35MON_f; + }; + __IO uint32_t IRQ36MON; + __IO uint32_t IRQ37MON; + union { + __IO uint32_t IRQ38MON; + stc_intreq_irq38mon_field_t IRQ38MON_f; + }; + union { + __IO uint32_t IRQ39MON; + stc_intreq_irq39mon_field_t IRQ39MON_f; + }; + union { + __IO uint32_t IRQ40MON; + stc_intreq_irq40mon_field_t IRQ40MON_f; + }; + union { + __IO uint32_t IRQ41MON; + stc_intreq_irq41mon_field_t IRQ41MON_f; + }; + union { + __IO uint32_t IRQ42MON; + stc_intreq_irq42mon_field_t IRQ42MON_f; + }; + union { + __IO uint32_t IRQ43MON; + stc_intreq_irq43mon_field_t IRQ43MON_f; + }; + union { + __IO uint32_t IRQ44MON; + stc_intreq_irq44mon_field_t IRQ44MON_f; + }; + union { + __IO uint32_t IRQ45MON; + stc_intreq_irq45mon_field_t IRQ45MON_f; + }; + __IO uint32_t IRQ46MON; + __IO uint32_t IRQ47MON; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + }; + union { + __IO uint32_t PFR5; + stc_gpio_pfr5_field_t PFR5_f; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + }; + uint8_t RESERVED0[220]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + }; + union { + __IO uint32_t PCR5; + stc_gpio_pcr5_field_t PCR5_f; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + }; + uint8_t RESERVED1[224]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + }; + union { + __IO uint32_t DDR5; + stc_gpio_ddr5_field_t DDR5_f; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + }; + uint8_t RESERVED2[220]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + }; + union { + __IO uint32_t PDIR5; + stc_gpio_pdir5_field_t PDIR5_f; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + }; + uint8_t RESERVED3[220]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + }; + union { + __IO uint32_t PDOR5; + stc_gpio_pdor5_field_t PDOR5_f; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + }; + uint8_t RESERVED4[220]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + }; + uint8_t RESERVED5[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + }; + uint8_t RESERVED6[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + }; + uint8_t RESERVED7[4]; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + }; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USB clock registers */ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbclk_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclk_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclk_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclk_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclk_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclk_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclk_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclk_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclk_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[15]; + union { + __IO uint8_t USBEN; + stc_usbclk_usben_field_t USBEN_f; + }; +}FM3_USBCLK_TypeDef; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CAN prescaler register */ +typedef struct +{ + union { + __IO uint8_t CANPRE; + stc_canpre_canpre_field_t CANPRE_f; + }; +}FM3_CANPRE_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs03_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs03_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_uart_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_lin_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs03_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs03_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs03_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs03_i2c_ismk_field_t ISMK_f; + }; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs47_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs47_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_uart_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_uart_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_uart_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_uart_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_uart_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_uart_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_uart_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_csio_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_csio_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_csio_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_csio_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_csio_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_csio_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_lin_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_lin_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_lin_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_lin_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_lin_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_lin_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_lin_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs47_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs47_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs47_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs47_i2c_ismk_field_t ISMK_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_i2c_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_i2c_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_i2c_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_i2c_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode0_field_t MODE0_f; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode1_field_t MODE1_f; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode2_field_t MODE2_f; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode3_field_t MODE3_f; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode4_field_t MODE4_f; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode5_field_t MODE5_f; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode6_field_t MODE6_f; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode7_field_t MODE7_f; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim0_field_t TIM0_f; + }; + union { + __IO uint32_t TIM1; + stc_exbus_tim1_field_t TIM1_f; + }; + union { + __IO uint32_t TIM2; + stc_exbus_tim2_field_t TIM2_f; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim3_field_t TIM3_f; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim4_field_t TIM4_f; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim5_field_t TIM5_f; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim6_field_t TIM6_f; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim7_field_t TIM7_f; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area0_field_t AREA0_f; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area1_field_t AREA1_f; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area2_field_t AREA2_f; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area3_field_t AREA3_f; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area4_field_t AREA4_f; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area5_field_t AREA5_f; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area6_field_t AREA6_f; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area7_field_t AREA7_f; + }; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + }; + struct { + union { + __IO uint8_t HCNT0; + stc_usb_hcnt0_field_t HCNT0_f; + }; + union { + __IO uint8_t HCNT1; + stc_usb_hcnt1_field_t HCNT1_f; + }; + }; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + }; + struct { + union { + __IO uint8_t HRTIMER0; + stc_usb_hrtimer0_field_t HRTIMER0_f; + }; + union { + __IO uint8_t HRTIMER1; + stc_usb_hrtimer1_field_t HRTIMER1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + }; + struct { + union { + __IO uint8_t HEOF0; + stc_usb_heof0_field_t HEOF0_f; + }; + union { + __IO uint8_t HEOF1; + stc_usb_heof1_field_t HEOF1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + }; + struct { + union { + __IO uint8_t HFRAME0; + stc_usb_hframe0_field_t HFRAME0_f; + }; + union { + __IO uint8_t HFRAME1; + stc_usb_hframe1_field_t HFRAME1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + }; + uint8_t RESERVED19[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + }; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + }; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + }; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + }; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + }; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + }; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + }; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + }; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + }; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN channel 0 registers */ +typedef struct +{ + union { + __IO uint16_t CTRLR; + stc_can_ctrlr_field_t CTRLR_f; + }; + union { + __IO uint16_t STATR; + stc_can_statr_field_t STATR_f; + }; + union { + __IO uint16_t ERRCNT; + stc_can_errcnt_field_t ERRCNT_f; + }; + union { + __IO uint16_t BTR; + stc_can_btr_field_t BTR_f; + }; + union { + __IO uint16_t INTR; + stc_can_intr_field_t INTR_f; + }; + union { + __IO uint16_t TESTR; + stc_can_testr_field_t TESTR_f; + }; + union { + __IO uint16_t BRPER; + stc_can_brper_field_t BRPER_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint16_t IF1CREQ; + stc_can_if1creq_field_t IF1CREQ_f; + }; + union { + __IO uint16_t IF1CMSK; + stc_can_if1cmsk_field_t IF1CMSK_f; + }; + union { + union { + __IO uint32_t IF1MSK; + stc_can_if1msk_field_t IF1MSK_f; + }; + struct { + __IO uint16_t IF1MSK1; + union { + __IO uint16_t IF1MSK2; + stc_can_if1msk2_field_t IF1MSK2_f; + }; + }; + }; + union { + union { + __IO uint32_t IF1ARB; + stc_can_if1arb_field_t IF1ARB_f; + }; + struct { + __IO uint16_t IF1ARB1; + union { + __IO uint16_t IF1ARB2; + stc_can_if1arb2_field_t IF1ARB2_f; + }; + }; + }; + union { + __IO uint16_t IF1MCTR; + stc_can_if1mctr_field_t IF1MCTR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + struct { + __IO uint16_t IF1DTA1_L; + __IO uint16_t IF1DTA2_L; + }; + }; + union { + __IO uint32_t IF1DTB_L; + struct { + __IO uint16_t IF1DTB1_L; + __IO uint16_t IF1DTB2_L; + }; + }; + uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + struct { + __IO uint16_t IF1DTA2_B; + __IO uint16_t IF1DTA1_B; + }; + }; + union { + __IO uint32_t IF1DTB_B; + struct { + __IO uint16_t IF1DTB2_B; + __IO uint16_t IF1DTB1_B; + }; + }; + uint8_t RESERVED3[8]; + union { + __IO uint16_t IF2CREQ; + stc_can_if2creq_field_t IF2CREQ_f; + }; + union { + __IO uint16_t IF2CMSK; + stc_can_if2cmsk_field_t IF2CMSK_f; + }; + union { + union { + __IO uint32_t IF2MSK; + stc_can_if2msk_field_t IF2MSK_f; + }; + struct { + __IO uint16_t IF2MSK1; + union { + __IO uint16_t IF2MSK2; + stc_can_if2msk2_field_t IF2MSK2_f; + }; + }; + }; + union { + __IO uint32_t IF2ARB; + struct { + __IO uint16_t IF2ARB1; + union { + __IO uint16_t IF2ARB2; + stc_can_if2arb2_field_t IF2ARB2_f; + }; + }; + }; + union { + __IO uint16_t IF2MCTR; + stc_can_if2mctr_field_t IF2MCTR_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + struct { + __IO uint16_t IF2DTA1_L; + __IO uint16_t IF2DTA2_L; + }; + }; + union { + __IO uint32_t IF2DTB_L; + struct { + __IO uint16_t IF2DTB1_L; + __IO uint16_t IF2DTB2_L; + }; + }; + uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + struct { + __IO uint16_t IF2DTA2_B; + __IO uint16_t IF2DTA1_B; + }; + }; + union { + __IO uint32_t IF2DTB_B; + struct { + __IO uint16_t IF2DTB2_B; + __IO uint16_t IF2DTB1_B; + }; + }; + uint8_t RESERVED6[24]; + union { + union { + __IO uint32_t TREQR; + stc_can_treqr_field_t TREQR_f; + }; + struct { + union { + __IO uint16_t TREQR1; + stc_can_treqr1_field_t TREQR1_f; + }; + union { + __IO uint16_t TREQR2; + stc_can_treqr2_field_t TREQR2_f; + }; + }; + }; + uint8_t RESERVED7[12]; + union { + union { + __IO uint32_t NEWDT; + stc_can_newdt_field_t NEWDT_f; + }; + struct { + union { + __IO uint16_t NEWDT1; + stc_can_newdt1_field_t NEWDT1_f; + }; + __IO uint16_t NEWDT2; + }; + }; + uint8_t RESERVED8[12]; + union { + union { + __IO uint32_t INTPND; + stc_can_intpnd_field_t INTPND_f; + }; + struct { + union { + __IO uint16_t INTPND1; + stc_can_intpnd1_field_t INTPND1_f; + }; + union { + __IO uint16_t INTPND2; + stc_can_intpnd2_field_t INTPND2_f; + }; + }; + }; + uint8_t RESERVED9[12]; + union { + union { + __IO uint32_t MSGVAL; + stc_can_msgval_field_t MSGVAL_f; + }; + struct { + union { + __IO uint16_t MSGVAL1; + stc_can_msgval1_field_t MSGVAL1_f; + }; + union { + __IO uint16_t MSGVAL2; + stc_can_msgval2_field_t MSGVAL2_f; + }; + }; + }; +}FM3_CAN_TypeDef; + + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ +#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) +#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) +#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) +#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) +#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) +#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) +#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) +#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) +#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) +#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) +#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) +#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) +#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) +#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) +#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) +#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) +#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) +#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) +#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) +#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) +#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) +#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) +#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) +#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) +#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) +#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) +#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) +#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) +#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) +#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) +#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) +#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) +#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) +#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) +#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) +#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) +#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) +#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) +#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) +#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) +#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) +#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) +#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) +#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) +#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) +#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) +#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) +#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) +#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) +#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) +#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) +#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) +#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) +#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) +#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) +#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) +#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) +#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) +#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) +#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) +#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) +#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) +#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) +#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) +#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) +#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) +#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) +#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) +#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) +#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) +#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) +#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) +#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) +#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) +#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) +#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) +#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) +#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) +#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) +#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) +#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) +#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) +#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) +#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) +#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) +#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) +#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) +#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) +#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) +#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) +#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) +#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) +#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) +#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) +#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) +#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) +#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) +#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) +#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) +#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) +#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) +#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) +#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) +#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) +#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) +#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) +#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) +#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) +#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) +#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) +#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) +#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) +#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) +#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) +#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) +#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) +#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) +#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) +#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) +#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) +#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) +#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) +#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) +#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) +#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) +#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +/* CAN prescaler register */ +#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) +#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) +#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) +#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* CAN channel 0 registers */ +#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) +#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) +#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) +#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) +#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) +#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) +#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) +#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) +#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) +#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) +#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) +#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) +#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) +#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) +#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) +#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) +#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) +#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) +#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) +#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) +#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) +#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) +#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) +#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) +#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) +#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) +#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) +#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) +#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) +#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) +#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) +#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) +#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) +#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) +#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) +#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) +#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) +#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) +#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) +#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) +#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) +#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) +#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) +#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) +#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) +#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) +#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) +#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) +#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) +#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) +#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) +#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) +#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) +#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) +#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) +#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) +#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) +#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) +#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) +#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) +#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) +#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) +#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) +#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) +#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) +#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) +#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) +#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) +#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) +#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) +#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) +#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) +#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) +#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) +#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) +#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) +#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) +#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) +#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) +#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) +#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) +#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) +#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) +#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) +#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) +#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) +#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) +#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) +#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) +#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) +#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) +#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) +#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) +#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) +#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) +#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) +#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) +#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) +#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) +#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) +#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) +#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) +#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) +#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) +#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) +#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) +#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) +#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) +#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) +#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) +#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) +#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) +#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) +#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) +#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) + +/* CAN channel 1 registers */ +#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) +#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) +#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) +#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) +#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) +#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) +#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) +#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) +#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) +#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) +#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) +#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) +#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) +#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) +#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) +#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) +#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) +#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) +#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) +#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) +#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) +#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) +#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) +#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) +#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) +#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) +#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) +#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) +#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) +#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) +#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) +#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) +#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) +#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) +#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) +#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) +#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) +#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) +#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) +#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) +#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) +#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) +#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) +#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) +#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) +#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) +#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) +#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) +#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) +#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) +#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) +#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) +#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) +#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) +#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) +#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) +#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) +#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) +#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) +#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) +#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) +#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) +#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) +#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) +#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) +#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) +#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) +#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) +#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) +#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) +#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) +#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) +#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) +#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) +#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) +#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) +#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) +#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) +#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) +#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) +#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) +#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) +#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) +#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) +#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) +#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) +#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) +#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) +#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) +#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) +#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) +#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) +#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) +#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) +#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) +#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) +#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) +#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) +#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) +#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) +#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) +#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) +#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) +#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) +#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) +#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) +#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) +#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) +#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) +#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) +#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) +#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) +#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) +#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) +#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9BF506R_H_ */ + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h new file mode 100644 index 0000000000..4e5eff2db3 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h @@ -0,0 +1,62 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/** + ****************************************************************************** + ** \file mcu.h + ** + ** Header File for device dependent includes + ** + ** History: + ** 2011-05-19 V1.00 MWi first version + ** + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief MCU header file include + ** + ******************************************************************************/ +#ifndef _MB9BF506R_H_ + #include "mb9bf506r.h" +#endif + +/** + ****************************************************************************** + ** \brief MCU system start-up header file include + ** + ******************************************************************************/ +#ifndef _SYSTEM_MB9BF50X_H_ + #include "system_mb9bf50x.h" +#endif + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h new file mode 100644 index 0000000000..947349e2af --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h @@ -0,0 +1,679 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/** \file system_mb9bf50x.h + ** + ** Headerfile for FM3 system parameters + ** + ** User clock definitions can be done for the following clock settings: + ** - CLOCK_SETUP : Execute the clock settings form the settings below in + ** SystemInit() + ** - __CLKMO : External clock frequency for main oscillion + ** - __CLKSO : External clock frequency for sub oscillion + ** - SCM_CTL : System Clock Mode Control Register + ** - BSC_PSR : Base Clock Prescaler Register + ** - APBC0_PSR : APB0 Prescaler Register + ** - APBC1_PSR : APB1 Prescaler Register + ** - APBC2_PSR : APB2 Prescaler Register + ** - SWC_PSR : Software Watchdog Clock Prescaler Register + ** - TTC_PSR : Trace Clock Prescaler Register + ** - CSW_TMR : Clock Stabilization Wait Time Register + ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register + ** - PLL_CTL1 : PLL Control Register 1 + ** - PLL_CTL2 : PLL Control Register 2 + ** + ** The register settings are check for correct values of reserved bits. + ** Otherwise a preprocessor error is output and stops the build process. + ** Furthermore the 'master clock' is retrieved from the register settings + ** and the system clock (HCLK) is calculated from the Base Clock Prescaler + ** Register (BSC_PSR). This value is used for the global CMSIS variable + ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is + ** is checked. Note that not all possible wrong setting are checked! The + ** user has to take care to fulfill the settings stated in the according + ** device's data sheet! + ** + ** User definition for Hardware Watchdog: + ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit() + ** + ** User definition for CR Trimming: + ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit() + ** + ** History: + ** 2011-05-16 V1.0 MWi original version + ** 2011-12-20 V1.1 EH corresponded to C++ + *****************************************************************************/ + +#ifndef _SYSTEM_MB9BF50X_H_ +#define _SYSTEM_MB9BF50X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup Enable + ** (USER SETTING) + ** + ** - 0 = No clock setup done by system_mb9xfxxx.c + ** - 1 = Clock setup done by system_mb9xfxxx.c + ******************************************************************************/ +#define CLOCK_SETUP 1 // <<< Define clock setup here + +/** + ****************************************************************************** + ** \brief External Main Clock Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal + +/** + ****************************************************************************** + ** \brief External Sub Clock Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal + +/** + ****************************************************************************** + ** \brief System Clock Mode Control Register value definition + ** (USER SETTING) + ** + ** SCM_CTL + ** + ** Bit#7-5 : RCS[2:0] + ** - 0 = Internal high-speed CR oscillation (default) + ** - 1 = Main oscillation clock + ** - 2 = PLL oscillation clock + ** - 3 = (not allowed) + ** - 4 = Internal low-speed CR oscillation + ** - 5 = Sub clock oscillation + ** - 6 = (not allowed) + ** - 7 = (not allowed) + ** + ** Bit#4 : PLLE + ** - 0 = Disable PLL (default) + ** - 1 = Enable PLL + ** + ** Bit#3 : SOSCE + ** - 0 = Disable sub oscillation (default) + ** - 1 = Enable sub oscillation + ** + ** Bit#2 : (reserved) + ** + ** Bit#1 : MOSCE + ** - 0 = Disable main oscillation (default) + ** - 1 = Enable main oscillation + ** + ** Bit#0 : (reserved) + ******************************************************************************/ +#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here + +/** + ****************************************************************************** + ** \brief Base Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** BSC_PSR + ** + ** Bit#7-3 : (reserved) + ** + ** Bit#2-0 : BSR[2:0] + ** - 0 = HCLK = Master Clock + ** - 1 = HCLK = Master Clock / 2 + ** - 2 = HCLK = Master Clock / 3 + ** - 3 = HCLK = Master Clock / 4 + ** - 4 = HCLK = Master Clock / 6 + ** - 5 = HCLK = Master Clock / 8 + ** - 6 = HCLK = Master Clock / 16 + ** - 7 = (reserved) + ******************************************************************************/ +#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here + +/** + ****************************************************************************** + ** \brief APB0 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC0_PSR + ** + ** Bit#7-2 : (reserved) + ** + ** Bit#1-0 : BSR[2:0] + ** - 0 = PCLK0 = HCLK + ** - 1 = PCLK0 = HCLK / 2 + ** - 2 = PCLK0 = HCLK / 4 + ** - 3 = PCLK0 = HCLK / 8 + ******************************************************************************/ +#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here + +/** + ****************************************************************************** + ** \brief APB1 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC1_PSR + ** + ** Bit#7 : APBC1EN + ** - 0 = Disable PCLK1 output + ** - 1 = Enables PCLK1 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC1RST + ** - 0 = APB1 bus reset, inactive (default) + ** - 1 = APB1 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC1[2:0] + ** - 0 = PCLK1 = HCLK + ** - 1 = PCLK1 = HCLK / 2 + ** - 2 = PCLK1 = HCLK / 4 + ** - 3 = PCLK1 = HCLK / 8 + ******************************************************************************/ +#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here + +/** + ****************************************************************************** + ** \brief APB2 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC2_PSR + ** + ** Bit#7 : APBC2EN + ** - 0 = Disable PCLK2 output + ** - 1 = Enables PCLK2 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC2RST + ** - 0 = APB2 bus reset, inactive (default) + ** - 1 = APB2 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC2[1:0] + ** - 0 = PCLK2 = HCLK + ** - 1 = PCLK2 = HCLK / 2 + ** - 2 = PCLK2 = HCLK / 4 + ** - 3 = PCLK2 = HCLK / 8 + ******************************************************************************/ +#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here + +/** + ****************************************************************************** + ** \brief Software Watchdog Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** SWC_PSR + ** + ** Bit#7 : TESTB + ** - 0 = (not allowed) + ** - 1 = (always write "1" to this bit) + ** + ** Bit#6-2 : (reserved) + ** + ** Bit#1-0 : SWDS[2:0] + ** - 0 = SWDGOGCLK = PCLK0 + ** - 1 = SWDGOGCLK = PCLK0 / 2 + ** - 2 = SWDGOGCLK = PCLK0 / 4 + ** - 3 = SWDGOGCLK = PCLK0 / 8 + ******************************************************************************/ +#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here + +/** + ****************************************************************************** + ** \brief Trace Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** TTC_PSR + ** + ** Bit#7-1 : (reserved) + ** + ** Bit#0 : TTC + ** - 0 = TPIUCLK = HCLK + ** - 1 = TPIUCLK = HCLK / 2 + ******************************************************************************/ +#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here + +/** + ****************************************************************************** + ** \brief Clock Stabilization Wait Time Register value definition + ** (USER SETTING) + ** + ** CSW_TMR + ** + ** Bit#7 : (reserved) + ** + ** Bit#6-4 : SOWT[2:0] + ** - 0 = ~10.3 ms (default) + ** - 1 = ~20.5 ms + ** - 2 = ~41 ms + ** - 3 = ~82 ms + ** - 4 = ~164 ms + ** - 5 = ~327 ms + ** - 6 = ~655 ms + ** - 7 = ~1.31 s + ** + ** Bit#3-0 : MOWT[3:0] + ** - 0 = ~500 ns (default) + ** - 1 = ~8 us + ** - 2 = ~16 us + ** - 3 = ~32 us + ** - 4 = ~64 us + ** - 5 = ~128 us + ** - 6 = ~256 us + ** - 7 = ~512 us + ** - 8 = ~1.0 ms + ** - 9 = ~2.0 ms + ** - 10 = ~4.0 ms + ** - 11 = ~8.0 ms + ** - 12 = ~33.0 ms + ** - 13 = ~131 ms + ** - 14 = ~524 ms + ** - 15 = ~2.0 s + ******************************************************************************/ +#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Clock Stabilization Wait Time Setup Register value definition + ** (USER SETTING) + ** + ** PSW_TMR + ** + ** Bit#7-5 : (reserved) + ** + ** Bit#4 : PINC + ** - 0 = Selects CLKMO (main oscillation) (default) + ** - 1 = (setting diabled) + ** + ** Bit#3 : (reserved) + ** + ** Bit#2-0 : POWT[2:0] + ** - 0 = ~128 us (default) + ** - 1 = ~256 us + ** - 2 = ~512 us + ** - 3 = ~1.02 ms + ** - 4 = ~2.05 ms + ** - 5 = ~4.10 ms + ** - 6 = ~8.20 ms + ** - 7 = ~16.40 ms + ******************************************************************************/ +#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Control Register 1 value definition + ** (USER SETTING) + ** + ** PLL_CTL1 + ** + ** Bit#7-4 : PLLK[3:0] + ** - 0 = Division(PLLK) = 1/1 (default) + ** - 1 = Division(PLLK) = 1/2 + ** - 2 = Division(PLLK) = 1/3 + ** - . . . + ** - 15 = Division(PLLK) = 1/16 + ** + ** Bit#3-0 : PLLM[3:0] + ** - 0 = Division(PLLM) = 1/1 (default) + ** - 1 = Division(PLLM) = 1/2 + ** - 2 = Division(PLLM) = 1/3 + ** - . . . + ** - 15 = Division(PLLM) = 1/16 + ******************************************************************************/ +#define PLL_CTL1_Val 0x00000000 // <<< Define PLL_CTL1 here + +/** + ****************************************************************************** + ** \brief PLL Control Register 2 value definition + ** (USER SETTING) + ** + ** PLL_CTL2 + ** + ** Bit#7-6 : (reserved) + ** + ** Bit#5-0 : PLLN[5:0] + ** - 0 = Division(PLLN) = 1/1 (default) + ** - 1 = Division(PLLN) = 1/2 + ** - 2 = Division(PLLN) = 1/3 + ** - . . . + ** - 63 = Division(PLLN) = 1/64 + ******************************************************************************/ +#define PLL_CTL2_Val 0x00000013 // <<< Define PLL_CTL2 here + +/** + ****************************************************************************** + ** \brief Hardware Watchdog disable definition + ** (USER SETTING) + ** + ** - 0 = Hardware Watchdog enable + ** - 1 = Hardware Watchdog disable + ******************************************************************************/ +#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here + +/** + ****************************************************************************** + ** \brief Trimming CR + ** (USER SETTING) + ** + ** - 0 = CR is not trimmed at startup + ** - 1 = CR is trimmed at startup + ******************************************************************************/ +#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here + + +/******************************************************************************/ +/* */ +/* END OF USER SETTINGS HERE */ +/* ========================= */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Device dependent System Clock absolute maximum ranges */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMIN ( 4000000UL) + +/** + ****************************************************************************** + ** \brief Maximum Main Clock frequency using external clock + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMAX ( 48000000UL) + +/** + ****************************************************************************** + ** \brief Any case minimum Sub Clock frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMIN ( 32000UL) + +/** + ****************************************************************************** + ** \brief Maximum Sub Clock frequency using external clock + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMAX ( 100000UL) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL input frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMIN ( 4000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL input frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMAX ( 30000000UL) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL oscillation frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMIN ( 60000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL oscillation frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMAX (120000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum System Clock frequency (HCLK) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __HCLKMAX ( 80000000UL) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking range (clock settings) + ******************************************************************************/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking bits with mask (clock settings) + ******************************************************************************/ +#define CHECK_RSVD(val, mask) (val & mask) + + +/******************************************************************************/ +/* Check register settings */ +/******************************************************************************/ +#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA)) + #error "SCM_CTL: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10) + #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" +#endif + +#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F)) + #error "CSW_TMR: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */ + #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007)) + #error "PSW_TMR: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF)) + #error "PLL_CTL1: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F)) + #error "PLL_CTL2: Invalid values of reserved bits!" + #endif +#endif + +#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007)) + #error "BSC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003)) + #error "APBC0_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083)) + #error "APBC1_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083)) + #error "APBC2_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003)) + #error "SWC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001)) + #error "TTC_PSR: Invalid values of reserved bits!" +#endif + +/******************************************************************************/ +/* Define clocks with checking settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Calculate PLL K factor from settings + ******************************************************************************/ +#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL N factor from settings + ******************************************************************************/ +#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL M factor from settings + ******************************************************************************/ +#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL output frequency from settings + ******************************************************************************/ +#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) + +/******************************************************************************/ +/* Determine core clock frequency according to settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Define Master Clock from settings + ******************************************************************************/ +#if (((SCM_CTL_Val >> 5) & 0x07) == 0) + #define __MASTERCLK (__CLKHC) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 1) + #define __MASTERCLK (__CLKMO) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 2) + #define __MASTERCLK (__PLLCLK) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 4) + #define __MASTERCLK (__CLKLC) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 5) + #define __MASTERCLK (__CLKSO) +#else + #define __MASTERCLK (0UL) +#endif + +/** + ****************************************************************************** + ** \brief Define System Clock Frequency (Core Clock) from settings + ******************************************************************************/ +#if ((BSC_PSR_Val & 0x07) == 0) + #define __HCLK (__MASTERCLK / 1) +#elif ((BSC_PSR_Val & 0x07) == 1) + #define __HCLK (__MASTERCLK / 2) +#elif ((BSC_PSR_Val & 0x07) == 2) + #define __HCLK (__MASTERCLK / 3) +#elif ((BSC_PSR_Val & 0x07) == 3) + #define __HCLK (__MASTERCLK / 4) +#elif ((BSC_PSR_Val & 0x07) == 4) + #define __HCLK (__MASTERCLK / 6) +#elif ((BSC_PSR_Val & 0x07) == 5) + #define __HCLK (__MASTERCLK / 8) +#elif ((BSC_PSR_Val & 0x07) == 6) + #define __HCLK (__MASTERCLK /16) +#else + #define __HCLK (0UL) +#endif + +/******************************************************************************/ +/* HCLK range check */ +/******************************************************************************/ +#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0) + #error "Main Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0) + #error "Sub Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0) + #error "PLL input frequency out of range!" +#endif + +#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0) + #error "PLL oscillation frequency out of range!" +#endif + +#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0) + #error "System Clock (HCLK) out of range!" +#endif + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +extern void SystemInit (void); // Initialize the system + +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S new file mode 100644 index 0000000000..3d163aa6dd --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S @@ -0,0 +1,327 @@ +;/************************************************************************/ +;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +;/* */ +;/* The following software deliverable is intended for and must only be */ +;/* used for reference and in an evaluation laboratory environment. */ +;/* It is provided on an as-is basis without charge and is subject to */ +;/* alterations. */ +;/* It is the user's obligation to fully test the software in its */ +;/* environment and to ensure proper functionality, qualification and */ +;/* compliance with component specifications. */ +;/* */ +;/* In the event the software deliverable includes the use of open */ +;/* source components, the provisions of the governing open source */ +;/* license agreement shall apply with respect to such software */ +;/* deliverable. */ +;/* FSEU does not warrant that the deliverables do not infringe any */ +;/* third party intellectual property right (IPR). In the event that */ +;/* the deliverables infringe a third party IPR it is the sole */ +;/* responsibility of the customer to obtain necessary licenses to */ +;/* continue the usage of the deliverable. */ +;/* */ +;/* To the maximum extent permitted by applicable law FSEU disclaims all */ +;/* warranties, whether express or implied, in particular, but not */ +;/* limited to, warranties of merchantability and fitness for a */ +;/* particular purpose for which the deliverable is not designated. */ +;/* */ +;/* To the maximum extent permitted by applicable law, FSEU's liability */ +;/* is restricted to intentional misconduct and gross negligence. */ +;/* FSEU is not liable for consequential damages. */ +;/* */ +;/* (V1.5) */ +;/************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.02 */ +;/* Date 2011-01-12 */ +;/* Target-mcu MB9B5xx */ +;/************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; 32: CAN ch.0 + DCD CAN1_IRQHandler ; 33: CAN ch.1 + DCD USBF_Handler ; 34: USB Function + DCD USB_Handler ; 35: USB Function / USB HOST + DCD DummyHandler ; 36: Reserved + DCD DummyHandler ; 37: Reserved + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD DummyHandler ; 46: Reserved + DCD DummyHandler ; 47: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT LVD_Handler [WEAK] + EXPORT MFT_WG_IRQHandler [WEAK] + EXPORT INT0_7_Handler [WEAK] + EXPORT INT8_15_Handler [WEAK] + EXPORT DT_Handler [WEAK] + EXPORT MFS0RX_IRQHandler [WEAK] + EXPORT MFS0TX_IRQHandler [WEAK] + EXPORT MFS1RX_IRQHandler [WEAK] + EXPORT MFS1TX_IRQHandler [WEAK] + EXPORT MFS2RX_IRQHandler [WEAK] + EXPORT MFS2TX_IRQHandler [WEAK] + EXPORT MFS3RX_IRQHandler [WEAK] + EXPORT MFS3TX_IRQHandler [WEAK] + EXPORT MFS4RX_IRQHandler [WEAK] + EXPORT MFS4TX_IRQHandler [WEAK] + EXPORT MFS5RX_IRQHandler [WEAK] + EXPORT MFS5TX_IRQHandler [WEAK] + EXPORT MFS6RX_IRQHandler [WEAK] + EXPORT MFS6TX_IRQHandler [WEAK] + EXPORT MFS7RX_IRQHandler [WEAK] + EXPORT MFS7TX_IRQHandler [WEAK] + EXPORT PPG_Handler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT MFT_FRT_IRQHandler [WEAK] + EXPORT MFT_IPC_IRQHandler [WEAK] + EXPORT MFT_OPC_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBF_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT DMAC0_Handler [WEAK] + EXPORT DMAC1_Handler [WEAK] + EXPORT DMAC2_Handler [WEAK] + EXPORT DMAC3_Handler [WEAK] + EXPORT DMAC4_Handler [WEAK] + EXPORT DMAC5_Handler [WEAK] + EXPORT DMAC6_Handler [WEAK] + EXPORT DMAC7_Handler [WEAK] + EXPORT DummyHandler [WEAK] + +CSV_Handler +SWDT_Handler +LVD_Handler +MFT_WG_IRQHandler +INT0_7_Handler +INT8_15_Handler +DT_Handler +MFS0RX_IRQHandler +MFS0TX_IRQHandler +MFS1RX_IRQHandler +MFS1TX_IRQHandler +MFS2RX_IRQHandler +MFS2TX_IRQHandler +MFS3RX_IRQHandler +MFS3TX_IRQHandler +MFS4RX_IRQHandler +MFS4TX_IRQHandler +MFS5RX_IRQHandler +MFS5TX_IRQHandler +MFS6RX_IRQHandler +MFS6TX_IRQHandler +MFS7RX_IRQHandler +MFS7TX_IRQHandler +PPG_Handler +TIM_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +MFT_FRT_IRQHandler +MFT_IPC_IRQHandler +MFT_OPC_IRQHandler +BT_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBF_Handler +USB_Handler +DMAC0_Handler +DMAC1_Handler +DMAC2_Handler +DMAC3_Handler +DMAC4_Handler +DMAC5_Handler +DMAC6_Handler +DMAC7_Handler +DummyHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S new file mode 100644 index 0000000000..72981f1edb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S @@ -0,0 +1,290 @@ +/**************************************************************************//** + * @file startup_.s + * @brief CMSIS Cortex-M# Core Device Startup File for + * Device + * @version V3.01 + * @date 06. March 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000100 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ +/* ToDo: Add here the vectors for the device specific external interrupts handler */ + .long CSV_Handler /* 0: Clock Super Visor */ + .long SWDT_Handler /* 1: Software Watchdog Timer */ + .long LVD_Handler /* 2: Low Voltage Detector */ + .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + .long DT_Handler /* 6: Dual Timer / Quad Decoder */ + .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + .long PPG_Handler /* 23: PPG */ + .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + .long ADC0_IRQHandler /* 25: ADC0 */ + .long ADC1_IRQHandler /* 26: ADC1 */ + .long ADC2_IRQHandler /* 27: ADC2 */ + .long MFT_FRT_IRQHandler /* 28: Free-run Timer */ + .long MFT_IPC_IRQHandler /* 29: Input Capture */ + .long MFT_OPC_IRQHandler /* 30: Output Compare */ + .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + .long CAN0_IRQHandler /* 32: CAN ch.0 */ + .long CAN1_IRQHandler /* 33: CAN ch.1 */ + .long USBF_Handler /* 34: USB Function */ + .long USB_Handler /* 35: USB Function / USB HOST */ + .long RESERVED_1_IRQHandler /* 36: Reserved */ + .long RESERVED_2_IRQHandler /* 37: Reserved */ + .long DMAC0_Handler /* 38: DMAC ch.0 */ + .long DMAC1_Handler /* 39: DMAC ch.1 */ + .long DMAC2_Handler /* 40: DMAC ch.2 */ + .long DMAC3_Handler /* 41: DMAC ch.3 */ + .long DMAC4_Handler /* 42: DMAC ch.4 */ + .long DMAC5_Handler /* 43: DMAC ch.5 */ + .long DMAC6_Handler /* 44: DMAC ch.6 */ + .long DMAC7_Handler /* 45: DMAC ch.7 */ + .long RESERVED_3_IRQHandler /* 46: Reserved */ + .long RESERVED_4_IRQHandler /* 47: Reserved */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .globl _start + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: +_start: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + +/* ToDo: Add here the export definition for the device specific external interrupts handler */ +/* ToDo: Add here the names for the device specific external interrupts handler */ + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CSV_Handler /* 0: Clock Super Visor */ + IRQ SWDT_Handler /* 1: Software Watchdog Timer */ + IRQ LVD_Handler /* 2: Low Voltage Detector */ + IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */ + IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + IRQ PPG_Handler /* 23: PPG */ + IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + IRQ ADC0_IRQHandler /* 25: ADC0 */ + IRQ ADC1_IRQHandler /* 26: ADC1 */ + IRQ ADC2_IRQHandler /* 27: ADC2 */ + IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */ + IRQ MFT_IPC_IRQHandler /* 29: Input Capture */ + IRQ MFT_OPC_IRQHandler /* 30: Output Compare */ + IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + IRQ CAN0_IRQHandler /* 32: CAN ch.0 */ + IRQ CAN1_IRQHandler /* 33: CAN ch.1 */ + IRQ USBF_Handler /* 34: USB Function */ + IRQ USB_Handler /* 35: USB Function / USB HOST */ + IRQ RESERVED_1_IRQHandler /* 36: Reserved */ + IRQ RESERVED_2_IRQHandler /* 37: Reserved */ + IRQ DMAC0_Handler /* 38: DMAC ch.0 */ + IRQ DMAC1_Handler /* 39: DMAC ch.1 */ + IRQ DMAC2_Handler /* 40: DMAC ch.2 */ + IRQ DMAC3_Handler /* 41: DMAC ch.3 */ + IRQ DMAC4_Handler /* 42: DMAC ch.4 */ + IRQ DMAC5_Handler /* 43: DMAC ch.5 */ + IRQ DMAC6_Handler /* 44: DMAC ch.6 */ + IRQ DMAC7_Handler /* 45: DMAC ch.7 */ + IRQ RESERVED_3_IRQHandler /* 46: Reserved */ + IRQ RESERVED_4_IRQHandler /* 47: Reserved */ + + .end diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S new file mode 100644 index 0000000000..9ac63778f5 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S @@ -0,0 +1,402 @@ +;/************************************************************************/ +;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +;/* */ +;/* The following software deliverable is intended for and must only be */ +;/* used for reference and in an evaluation laboratory environment. */ +;/* It is provided on an as-is basis without charge and is subject to */ +;/* alterations. */ +;/* It is the user's obligation to fully test the software in its */ +;/* environment and to ensure proper functionality, qualification and */ +;/* compliance with component specifications. */ +;/* */ +;/* In the event the software deliverable includes the use of open */ +;/* source components, the provisions of the governing open source */ +;/* license agreement shall apply with respect to such software */ +;/* deliverable. */ +;/* FSEU does not warrant that the deliverables do not infringe any */ +;/* third party intellectual property right (IPR). In the event that */ +;/* the deliverables infringe a third party IPR it is the sole */ +;/* responsibility of the customer to obtain necessary licenses to */ +;/* continue the usage of the deliverable. */ +;/* */ +;/* To the maximum extent permitted by applicable law FSEU disclaims all */ +;/* warranties, whether express or implied, in particular, but not */ +;/* limited to, warranties of merchantability and fitness for a */ +;/* particular purpose for which the deliverable is not designated. */ +;/* */ +;/* To the maximum extent permitted by applicable law, FSEU's liability */ +;/* is restricted to intentional misconduct and gross negligence. */ +;/* FSEU is not liable for consequential damages. */ +;/* */ +;/* (V1.5) */ +;/************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.02 */ +;/* Date 2011-01-05 */ +;/* Target-mcu MB9B5xx */ +;/************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD MemManage_Handler ; MPU Fault + DCD BusFault_Handler ; Bus Fault + DCD UsageFault_Handler ; Usage Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD DebugMon_Handler ; Debug Monitor + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; 32: CAN ch.0 + DCD CAN1_IRQHandler ; 33: CAN ch.1 + DCD USBF_Handler ; 34: USB Function + DCD USB_Handler ; 35: USB Function / USB HOST + DCD DummyHandler ; 36: Reserved + DCD DummyHandler ; 37: Reserved + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD DummyHandler ; 46: Reserved + DCD DummyHandler ; 47: Reserved + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + + PUBWEAK CSV_Handler + SECTION .text:CODE:REORDER(1) +CSV_Handler + B CSV_Handler + + PUBWEAK SWDT_Handler + SECTION .text:CODE:REORDER(1) +SWDT_Handler + B SWDT_Handler + + PUBWEAK LVD_Handler + SECTION .text:CODE:REORDER(1) +LVD_Handler + B LVD_Handler + + PUBWEAK MFT_WG_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_WG_IRQHandler + B MFT_WG_IRQHandler + + PUBWEAK INT0_7_Handler + SECTION .text:CODE:REORDER(1) +INT0_7_Handler + B INT0_7_Handler + + PUBWEAK INT8_15_Handler + SECTION .text:CODE:REORDER(1) +INT8_15_Handler + B INT8_15_Handler + + PUBWEAK DT_Handler + SECTION .text:CODE:REORDER(1) +DT_Handler + B DT_Handler + + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0RX_IRQHandler + B MFS0RX_IRQHandler + + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0TX_IRQHandler + B MFS0TX_IRQHandler + + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1RX_IRQHandler + B MFS1RX_IRQHandler + + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1TX_IRQHandler + B MFS1TX_IRQHandler + + PUBWEAK MFS2RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2RX_IRQHandler + B MFS2RX_IRQHandler + + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2TX_IRQHandler + B MFS2TX_IRQHandler + + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3RX_IRQHandler + B MFS3RX_IRQHandler + + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3TX_IRQHandler + B MFS3TX_IRQHandler + + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4RX_IRQHandler + B MFS4RX_IRQHandler + + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4TX_IRQHandler + B MFS4TX_IRQHandler + + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5RX_IRQHandler + B MFS5RX_IRQHandler + + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5TX_IRQHandler + B MFS5TX_IRQHandler + + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6RX_IRQHandler + B MFS6RX_IRQHandler + + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6TX_IRQHandler + B MFS6TX_IRQHandler + + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7RX_IRQHandler + B MFS7RX_IRQHandler + + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7TX_IRQHandler + B MFS7TX_IRQHandler + + PUBWEAK PPG_Handler + SECTION .text:CODE:REORDER(1) +PPG_Handler + B PPG_Handler + + PUBWEAK TIM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM_IRQHandler + B TIM_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK MFT_FRT_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_FRT_IRQHandler + B MFT_FRT_IRQHandler + + PUBWEAK MFT_IPC_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_IPC_IRQHandler + B MFT_IPC_IRQHandler + + PUBWEAK MFT_OPC_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_OPC_IRQHandler + B MFT_OPC_IRQHandler + + PUBWEAK BT_IRQHandler + SECTION .text:CODE:REORDER(1) +BT_IRQHandler + B BT_IRQHandler + + PUBWEAK CAN0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN0_IRQHandler + B CAN0_IRQHandler + + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + + PUBWEAK USBF_Handler + SECTION .text:CODE:REORDER(1) +USBF_Handler + B USBF_Handler + + PUBWEAK USB_Handler + SECTION .text:CODE:REORDER(1) +USB_Handler + B USB_Handler + + PUBWEAK DMAC0_Handler + SECTION .text:CODE:REORDER(1) +DMAC0_Handler + B DMAC0_Handler + + + PUBWEAK DMAC1_Handler + SECTION .text:CODE:REORDER(1) +DMAC1_Handler + B DMAC1_Handler + + PUBWEAK DMAC2_Handler + SECTION .text:CODE:REORDER(1) +DMAC2_Handler + B DMAC2_Handler + + PUBWEAK DMAC3_Handler + SECTION .text:CODE:REORDER(1) +DMAC3_Handler + B DMAC3_Handler + + PUBWEAK DMAC4_Handler + SECTION .text:CODE:REORDER(1) +DMAC4_Handler + B DMAC4_Handler + + PUBWEAK DMAC5_Handler + SECTION .text:CODE:REORDER(1) +DMAC5_Handler + B DMAC5_Handler + + PUBWEAK DMAC6_Handler + SECTION .text:CODE:REORDER(1) +DMAC6_Handler + B DMAC6_Handler + + PUBWEAK DMAC7_Handler + SECTION .text:CODE:REORDER(1) +DMAC7_Handler + B DMAC7_Handler + + PUBWEAK DummyHandler + SECTION .text:CODE:REORDER(1) +DummyHandler + B DummyHandler + + END diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c new file mode 100644 index 0000000000..6ccf1ff957 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c @@ -0,0 +1,202 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ + +#include "mcu.h" + +/** \file system_mb9bf50x.c + ** + ** FM3 system initialization functions + ** All adjustments can be done in belonging header file. + ** + ** History: + ** 2011-05-16 V1.0 MWi original version + ******************************************************************************/ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = __HCLK; + +/** + ****************************************************************************** + ** \brief Update the System Core Clock with current core Clock retrieved from + ** cpu registers. + ** \param none + ** \return none + ******************************************************************************/ +void SystemCoreClockUpdate (void) { + uint32_t masterClk; + uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance + + switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) { + case 0: /* internal High-speed Cr osc. */ + masterClk = __CLKHC; + break; + + case 1: /* external main osc. */ + masterClk = __CLKMO; + break; + + case 2: /* PLL clock */ + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violation: + // "Unordered accesses to a volatile location" + u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1)); + masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1)); + break; + + case 4: /* internal Low-speed CR osc. */ + masterClk = __CLKLC; + break; + + case 5: /* external Sub osc. */ + masterClk = __CLKSO; + break; + + default: + masterClk = 0Ul; + break; + } + + switch (FM3_CRG->BSC_PSR & 0x07) { + case 0: + SystemCoreClock = masterClk; + break; + + case 1: + SystemCoreClock = masterClk / 2; + break; + + case 2: + SystemCoreClock = masterClk / 3; + break; + + case 3: + SystemCoreClock = masterClk / 4; + break; + + case 4: + SystemCoreClock = masterClk / 6; + break; + + case 5: + SystemCoreClock = masterClk /8; + break; + + case 6: + SystemCoreClock = masterClk /16; + break; + + default: + SystemCoreClock = 0Ul; + break; + } + +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit (void) { + + static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance + +#if (HWWD_DISABLE) /* HW Watchdog Disable */ + FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */ + FM3_HWWDT->WDG_LCK = 0xE5331AAE; + FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */ +#endif + +#if (CLOCK_SETUP) /* Clock Setup */ + FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */ + FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */ + FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */ + FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */ + FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */ + FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */ + + FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */ + + if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */ + while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */ + } + + if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ + while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ + } + + FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */ + FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */ + FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */ + + if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */ + while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */ + } + + FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */ + + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violations: + // "Unordered reads and writes to or from same location" and + // "Unordered accesses to a volatile location" + do + { + u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0); + }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead); +#endif // (CLOCK_SETUP) + +#if (CR_TRIM_SETUP) + /* CR Trimming Data */ + if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) ) + { + /* UnLock (MCR_FTRM) */ + FM3_CRTRIM->MCR_RLR = 0x1ACCE554; + /* Set MCR_FTRM */ + FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM; + /* Lock (MCR_FTRM) */ + FM3_CRTRIM->MCR_RLR = 0x00000000; + } +#endif // (CR_TRIM_SETUP) +} + + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/libraries/SConscript b/bsp/fujitsu/mb9x/mb9bf506r/libraries/SConscript new file mode 100644 index 0000000000..a0fa5ca72d --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/libraries/SConscript @@ -0,0 +1,23 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +src = ['Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c'] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += ['Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S'] + +CPPPATH = [cwd + '/Device/FUJISTU/MB9BF50x/Include'] + +CPPPATH += [cwd + '/CMSIS/Include'] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.ewp b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp new file mode 100644 index 0000000000..a258e109b6 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp @@ -0,0 +1,1945 @@ + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\application.c + + + $PROJ_DIR$\applications\startup.c + + + + CMSIS + + $PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c + + + $PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\IAR\startup_mb9bf50x.S + + + + Compiler + + $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c + + + + CPU + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + + Drivers + + $PROJ_DIR$\drivers\fm3_uart.c + + + $PROJ_DIR$\drivers\led.c + + + $PROJ_DIR$\drivers\nand.c + + + $PROJ_DIR$\drivers\board.c + + + + Finsh + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + + Kernel + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\timer.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + + POSIX + + + utestcases + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.eww b/bsp/fujitsu/mb9x/mb9bf506r/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj new file mode 100644 index 0000000000..8eaab29744 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj @@ -0,0 +1,697 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread-fm3 + 0x4 + ARM-ADS + + + MB9BF506R + Fujitsu Semiconductors + IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFF8000-0x1FFFFFFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000) + 5216 + MB9BF506R.h + + + + + + + + + + SFD\Fujitsu\MB9B500\MB9BF506R.SFR + 0 + + + + Fujitsu\MB9B500\ + Fujitsu\MB9B500\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-stm32 + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x1fff8000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;libraries\Device\FUJISTU\MB9BF50x\Include;libraries\CMSIS\Include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + Applications + + + application.c + 1 + applications\application.c + + + + + startup.c + 1 + applications\startup.c + + + + + CMSIS + + + startup_mb9bf50x.S + 2 + libraries\Device\FUJISTU\MB9BF50x\Source\ARM\startup_mb9bf50x.S + + + + + system_mb9bf50x.c + 1 + libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + DeviceDrivers + + + ringbuffer.c + 1 + ..\..\components\drivers\ipc\ringbuffer.c + + + + + completion.c + 1 + ..\..\components\drivers\ipc\completion.c + + + + + ringblk_buf.c + 1 + ..\..\components\drivers\ipc\ringblk_buf.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\ipc\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\ipc\pipe.c + + + + + workqueue.c + 1 + ..\..\components\drivers\ipc\workqueue.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\ipc\waitqueue.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + Drivers + + + led.c + 1 + drivers\led.c + + + + + board.c + 1 + drivers\board.c + + + + + nand.c + 1 + drivers\nand.c + + + + + fm3_uart.c + 1 + drivers\fm3_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + Kernel + + + components.c + 1 + ..\..\src\components.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + memheap.c + 1 + ..\..\src\memheap.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + clock.c + 1 + ..\..\src\clock.c + + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.h b/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.h new file mode 100644 index 0000000000..b7b675ab20 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.h @@ -0,0 +1,179 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// + +// +#define RT_NAME_MAX 8 +// +#define RT_ALIGN_SIZE 8 +// +// 8 +// 32 +// 256 +// +#define RT_THREAD_PRIORITY_MAX 32 +// +#define RT_TICK_PER_SECOND 100 +//
+// #define RT_DEBUG +// +// #define RT_THREAD_DEBUG +// +#define RT_USING_OVERFLOW_CHECK +//
+ +// +#define RT_USING_HOOK +//
+// #define RT_USING_TIMER_SOFT +// +#define RT_TIMER_THREAD_PRIO 8 +// +#define RT_TIMER_THREAD_STACK_SIZE 512 +// +#define RT_TIMER_TICK_PER_SECOND 10 +//
+ +//
+// +#define RT_USING_SEMAPHORE +// +#define RT_USING_MUTEX +// +#define RT_USING_EVENT +// +#define RT_USING_MAILBOX +// +#define RT_USING_MESSAGEQUEUE +//
+ +//
+// +#define RT_USING_MEMPOOL +// +#define RT_USING_MEMHEAP +// +#define RT_USING_HEAP +// +#define RT_USING_SMALL_MEM +// +// #define RT_USING_SLAB +//
+ +//
+#define RT_USING_DEVICE +// +#define RT_USING_DEVICE_IPC +// +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +// +#define RT_USING_UART0_0 +// +// #define RT_USING_UART0_1 +// +// #define RT_USING_UART1_0 +// +// #define RT_USING_UART1_1 +// +// #define RT_USING_UART2_0 +// +// #define RT_USING_UART2_1 +// +// #define RT_USING_UART2_2 +// +// #define RT_USING_UART3_0 +// +// #define RT_USING_UART3_1 +// +// #define RT_USING_UART3_2 +// +// #define RT_USING_UART4_0 +// +// #define RT_USING_UART4_1 +// +#define RT_USING_UART4_2 +// +// #define RT_USING_UART5_0 +// +// #define RT_USING_UART5_1 +// +// #define RT_USING_UART5_2 +// +// #define RT_USING_UART6_0 +// +// #define RT_USING_UART6_1 +// +#define RT_USING_UART7_0 +// +// #define RT_USING_UART7_1 +// +#define RT_UART_RX_BUFFER_SIZE 64 +//
+ +//
+#define RT_USING_CONSOLE +// +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart0" +//
+ +// +#define RT_USING_COMPONENTS_INIT +//
+#define RT_USING_FINSH +// +#define FINSH_USING_SYMTAB +// +#define FINSH_USING_DESCRIPTION +// +#define FINSH_THREAD_STACK_SIZE 4096 +//
+ +//
+// +// #define RT_USING_NEWLIB +// +// #define RT_USING_PTHREADS +//
+ +//
+// #define RT_USING_DFS +// +// #define DFS_USING_WORKDIR +// +#define DFS_FILESYSTEMS_MAX 2 +// +#define DFS_FD_MAX 4 +// +#define RT_USING_DFS_ELMFAT +// +// 1 +// 2 +// +#define RT_DFS_ELM_USE_LFN 1 +// +#define RT_DFS_ELM_MAX_LFN 64 +// +// #define RT_USING_DFS_YAFFS2 +// +// #define RT_USING_DFS_UFFS +// +// #define RT_USING_DFS_DEVFS +// +// #define RT_USING_DFS_NFS +// +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +//
+ +// +// #define RT_USING_CMSIS_OS +// +// #define RT_USING_BSP_CMSIS + +// + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.py b/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.py new file mode 100644 index 0000000000..d8b525f291 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtconfig.py @@ -0,0 +1,121 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='iar' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-mb9bf506.ld -nostartfiles' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter rtthread-mb9bf506.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + CFLAGS = '' + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' + + LFLAGS = ' --config rtthread-mb9bf506.icf' + LFLAGS += ' --semihosting' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf new file mode 100644 index 0000000000..66b859d099 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.ld b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.ld new file mode 100644 index 0000000000..644c891306 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.ld @@ -0,0 +1,221 @@ +/* Linker script to configure memory regions + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512k */ + ram (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 0x00010000 /* 32k */ +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + + .heap : + { + *(.heap) + } >ram + + __bss_end = .; + + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.sct b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.sct new file mode 100644 index 0000000000..6a8744246a --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/rtthread-mb9bf506.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/template.ewp b/bsp/fujitsu/mb9x/mb9bf506r/template.ewp new file mode 100644 index 0000000000..40100eb5cb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/template.ewp @@ -0,0 +1,1739 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf506r/template.uvproj b/bsp/fujitsu/mb9x/mb9bf506r/template.uvproj new file mode 100644 index 0000000000..137c045dea --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf506r/template.uvproj @@ -0,0 +1,388 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-fm3 + 0x4 + ARM-ADS + + + MB9BF506R + Fujitsu Semiconductors + IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFF8000-0x1FFFFFFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000) + 5216 + MB9BF506R.h + + + + + + + + + + SFD\Fujitsu\MB9B500\MB9BF506R.SFR + 0 + + + + Fujitsu\MB9B500\ + Fujitsu\MB9B500\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-stm32 + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x1fff8000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s new file mode 100644 index 0000000000..416a56f41d --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s @@ -0,0 +1,584 @@ +;******************************************************************************* +; Copyright (C) 2013 Spansion LLC. All Rights Reserved. +; +; This software is owned and published by: +; Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with Spansion +; components. This software is licensed by Spansion to be adapted only +; for use in systems utilizing Spansion components. Spansion shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. Spansion is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +; + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in +; pdl.h (section "IRQ name definition for all type MCUs" + + DCD CSV_IRQHandler + DCD SWDT_IRQHandler + DCD LVD_IRQHandler + DCD IRQ003SEL_IRQHandler + DCD IRQ004SEL_IRQHandler + DCD IRQ005SEL_IRQHandler + DCD IRQ006SEL_IRQHandler + DCD IRQ007SEL_IRQHandler + DCD IRQ008SEL_IRQHandler + DCD IRQ009SEL_IRQHandler + DCD IRQ010SEL_IRQHandler + DCD EXINT0_IRQHandler + DCD EXINT1_IRQHandler + DCD EXINT2_IRQHandler + DCD EXINT3_IRQHandler + DCD EXINT4_IRQHandler + DCD EXINT5_IRQHandler + DCD EXINT6_IRQHandler + DCD EXINT7_IRQHandler + DCD QPRC0_IRQHandler + DCD QPRC1_IRQHandler + DCD WFG0_DTIF0_IRQHandler + DCD WFG1_DTIF1_IRQHandler + DCD WFG2_DTIF2_IRQHandler + DCD FRT0_PEAK_IRQHandler + DCD FRT0_ZERO_IRQHandler + DCD ICU0_IRQHandler + DCD OCU0_IRQHandler + DCD FRT1_PEAK_IRQHandler + DCD FRT1_ZERO_IRQHandler + DCD ICU1_IRQHandler + DCD OCU1_IRQHandler + DCD FRT2_PEAK_IRQHandler + DCD FRT2_ZERO_IRQHandler + DCD ICU2_IRQHandler + DCD OCU2_IRQHandler + DCD PPG00_02_04_IRQHandler + DCD PPG08_10_12_IRQHandler + DCD PPG16_18_20_IRQHandler + DCD BT0_IRQHandler + DCD BT1_IRQHandler + DCD BT2_IRQHandler + DCD BT3_IRQHandler + DCD BT4_IRQHandler + DCD BT5_IRQHandler + DCD BT6_IRQHandler + DCD BT7_IRQHandler + DCD DT1_2_IRAHandler + DCD WC_IRQHandler + DCD EXTBUS_ERR_Handler + DCD RTC_IRQHandler + DCD EXTINT8_IRQHandler + DCD EXTINT9_IRQHandler + DCD EXTINT10_IRQHandler + DCD EXTINT11_IRQHandler + DCD EXTINT12_IRQHandler + DCD EXTINT13_IRQHandler + DCD EXTINT14_IRQHandler + DCD EXTINT15_IRQHandler + DCD TIM_IRQHandler + DCD MFS0_RX_IRQHandler + DCD MFS0_TX_IRQHandler + DCD MFS1_RX_IRQHandler + DCD MFS1_TX_IRQHandler + DCD MFS2_RX_IRQHandler + DCD MFS2_TX_IRQHandler + DCD MFS3_RX_IRQHandler + DCD MFS3_TX_IRQHandler + DCD MFS4_RX_IRQHandler + DCD MFS4_TX_IRQHandler + DCD MFS5_RX_IRQHandler + DCD MFS5_TX_IRQHandler + DCD MFS6_RX_IRQHandler + DCD MFS6_TX_IRQHandler + DCD MFS7_RX_IRQHandler + DCD MFS7_TX_IRQHandler + DCD ADC0_IRQHandler + DCD ADC1_IRQHandler + DCD USB0_IRQHandler + DCD USB0_HOST_IRQHandler + DCD CAN0_IRQHandler + DCD CAN1_IRQHandler + DCD ETHER0_IRQHandler + DCD DMAC0_IRQHandler + DCD DMAC1_IRQHandler + DCD DMAC2_IRQHandler + DCD DMAC3_IRQHandler + DCD DMAC4_IRQHandler + DCD DMAC5_IRQHandler + DCD DMAC6_IRQHandler + DCD DMAC7_IRQHandler + DCD DSTC_IRQHandler + DCD EXINT16_17_18_19_IRQHandler + DCD EXINT20_21_22_23_IRQHandler + DCD EXINT24_25_26_27_IRQHandler + DCD EXINT28_29_30_31_IRQHandler + DCD QPRC2_IRQHandler + DCD QPRC3_IRQHandler + DCD BT8_IRQHandler + DCD BT9_IRQHandler + DCD BT10_IRQHandler + DCD BT11_IRQHandler + DCD BT12_15_IRQHandler + DCD MFS8_RX_IRQHandler + DCD MFS8_TX_IRQHandler + DCD MFS9_RX_IRQHandler + DCD MFS9_TX_IRQHandler + DCD MFS10_RX_IRQHandler + DCD MFS10_TX_IRQHandler + DCD MFS11_RX_IRQHandler + DCD MFS11_TX_IRQHandler + DCD ADC2_IRQHandler + DCD Dummy + DCD USB1_IRQHandler + DCD USB1_HOST_IRQHandler + DCD Dummy + DCD Dummy + DCD Dummy + DCD SD_IRQHandler + DCD FLASHIF_IRQHandler + DCD MFS12_RX_IRQHandler + DCD MFS12_TX_IRQHandler + DCD MFS13_RX_IRQHandler + DCD MFS13_TX_IRQHandler + DCD MFS14_RX_IRQHandler + DCD MFS14_TX_IRQHandler + DCD MFS15_RX_IRQHandler + DCD MFS15_TX_IRQHandler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR.W R0, =0xE000ED88 ; CPACR is located at address 0xE000ED88 + LDR R1, [R0] ; Read CPACR + ORR R1, R1, #(0xF << 20) ; Set bits 20-23 to enable CP10 and CP11 coprocessors + STR R1, [R0] ; Write back the modified value to the CPACR + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_IRQHandler [WEAK] + EXPORT SWDT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT IRQ003SEL_IRQHandler [WEAK] + EXPORT IRQ004SEL_IRQHandler [WEAK] + EXPORT IRQ005SEL_IRQHandler [WEAK] + EXPORT IRQ006SEL_IRQHandler [WEAK] + EXPORT IRQ007SEL_IRQHandler [WEAK] + EXPORT IRQ008SEL_IRQHandler [WEAK] + EXPORT IRQ009SEL_IRQHandler [WEAK] + EXPORT IRQ010SEL_IRQHandler [WEAK] + EXPORT EXINT0_IRQHandler [WEAK] + EXPORT EXINT1_IRQHandler [WEAK] + EXPORT EXINT2_IRQHandler [WEAK] + EXPORT EXINT3_IRQHandler [WEAK] + EXPORT EXINT4_IRQHandler [WEAK] + EXPORT EXINT5_IRQHandler [WEAK] + EXPORT EXINT6_IRQHandler [WEAK] + EXPORT EXINT7_IRQHandler [WEAK] + EXPORT QPRC0_IRQHandler [WEAK] + EXPORT QPRC1_IRQHandler [WEAK] + EXPORT WFG0_DTIF0_IRQHandler [WEAK] + EXPORT WFG1_DTIF1_IRQHandler [WEAK] + EXPORT WFG2_DTIF2_IRQHandler [WEAK] + EXPORT FRT0_PEAK_IRQHandler [WEAK] + EXPORT FRT0_ZERO_IRQHandler [WEAK] + EXPORT ICU0_IRQHandler [WEAK] + EXPORT OCU0_IRQHandler [WEAK] + EXPORT FRT1_PEAK_IRQHandler [WEAK] + EXPORT FRT1_ZERO_IRQHandler [WEAK] + EXPORT ICU1_IRQHandler [WEAK] + EXPORT OCU1_IRQHandler [WEAK] + EXPORT FRT2_PEAK_IRQHandler [WEAK] + EXPORT FRT2_ZERO_IRQHandler [WEAK] + EXPORT ICU2_IRQHandler [WEAK] + EXPORT OCU2_IRQHandler [WEAK] + EXPORT PPG00_02_04_IRQHandler [WEAK] + EXPORT PPG08_10_12_IRQHandler [WEAK] + EXPORT PPG16_18_20_IRQHandler [WEAK] + EXPORT BT0_IRQHandler [WEAK] + EXPORT BT1_IRQHandler [WEAK] + EXPORT BT2_IRQHandler [WEAK] + EXPORT BT3_IRQHandler [WEAK] + EXPORT BT4_IRQHandler [WEAK] + EXPORT BT5_IRQHandler [WEAK] + EXPORT BT6_IRQHandler [WEAK] + EXPORT BT7_IRQHandler [WEAK] + EXPORT DT1_2_IRAHandler [WEAK] + EXPORT WC_IRQHandler [WEAK] + EXPORT EXTBUS_ERR_Handler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EXTINT8_IRQHandler [WEAK] + EXPORT EXTINT9_IRQHandler [WEAK] + EXPORT EXTINT10_IRQHandler [WEAK] + EXPORT EXTINT11_IRQHandler [WEAK] + EXPORT EXTINT12_IRQHandler [WEAK] + EXPORT EXTINT13_IRQHandler [WEAK] + EXPORT EXTINT14_IRQHandler [WEAK] + EXPORT EXTINT15_IRQHandler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT MFS0_RX_IRQHandler [WEAK] + EXPORT MFS0_TX_IRQHandler [WEAK] + EXPORT MFS1_RX_IRQHandler [WEAK] + EXPORT MFS1_TX_IRQHandler [WEAK] + EXPORT MFS2_RX_IRQHandler [WEAK] + EXPORT MFS2_TX_IRQHandler [WEAK] + EXPORT MFS3_RX_IRQHandler [WEAK] + EXPORT MFS3_TX_IRQHandler [WEAK] + EXPORT MFS4_RX_IRQHandler [WEAK] + EXPORT MFS4_TX_IRQHandler [WEAK] + EXPORT MFS5_RX_IRQHandler [WEAK] + EXPORT MFS5_TX_IRQHandler [WEAK] + EXPORT MFS6_RX_IRQHandler [WEAK] + EXPORT MFS6_TX_IRQHandler [WEAK] + EXPORT MFS7_RX_IRQHandler [WEAK] + EXPORT MFS7_TX_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USB0_HOST_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT ETHER0_IRQHandler [WEAK] + EXPORT DMAC0_IRQHandler [WEAK] + EXPORT DMAC1_IRQHandler [WEAK] + EXPORT DMAC2_IRQHandler [WEAK] + EXPORT DMAC3_IRQHandler [WEAK] + EXPORT DMAC4_IRQHandler [WEAK] + EXPORT DMAC5_IRQHandler [WEAK] + EXPORT DMAC6_IRQHandler [WEAK] + EXPORT DMAC7_IRQHandler [WEAK] + EXPORT DSTC_IRQHandler [WEAK] + EXPORT EXINT16_17_18_19_IRQHandler [WEAK] + EXPORT EXINT20_21_22_23_IRQHandler [WEAK] + EXPORT EXINT24_25_26_27_IRQHandler [WEAK] + EXPORT EXINT28_29_30_31_IRQHandler [WEAK] + EXPORT QPRC2_IRQHandler [WEAK] + EXPORT QPRC3_IRQHandler [WEAK] + EXPORT BT8_IRQHandler [WEAK] + EXPORT BT9_IRQHandler [WEAK] + EXPORT BT10_IRQHandler [WEAK] + EXPORT BT11_IRQHandler [WEAK] + EXPORT BT12_15_IRQHandler [WEAK] + EXPORT MFS8_RX_IRQHandler [WEAK] + EXPORT MFS8_TX_IRQHandler [WEAK] + EXPORT MFS9_RX_IRQHandler [WEAK] + EXPORT MFS9_TX_IRQHandler [WEAK] + EXPORT MFS10_RX_IRQHandler [WEAK] + EXPORT MFS10_TX_IRQHandler [WEAK] + EXPORT MFS11_RX_IRQHandler [WEAK] + EXPORT MFS11_TX_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT USB1_IRQHandler [WEAK] + EXPORT USB1_HOST_IRQHandler [WEAK] + EXPORT SD_IRQHandler [WEAK] + EXPORT FLASHIF_IRQHandler [WEAK] + EXPORT MFS12_RX_IRQHandler [WEAK] + EXPORT MFS12_TX_IRQHandler [WEAK] + EXPORT MFS13_RX_IRQHandler [WEAK] + EXPORT MFS13_TX_IRQHandler [WEAK] + EXPORT MFS14_RX_IRQHandler [WEAK] + EXPORT MFS14_TX_IRQHandler [WEAK] + EXPORT MFS15_RX_IRQHandler [WEAK] + EXPORT MFS15_TX_IRQHandler [WEAK] + EXPORT Dummy [WEAK] + + + +CSV_IRQHandler +SWDT_IRQHandler +LVD_IRQHandler +IRQ003SEL_IRQHandler +IRQ004SEL_IRQHandler +IRQ005SEL_IRQHandler +IRQ006SEL_IRQHandler +IRQ007SEL_IRQHandler +IRQ008SEL_IRQHandler +IRQ009SEL_IRQHandler +IRQ010SEL_IRQHandler +EXINT0_IRQHandler +EXINT1_IRQHandler +EXINT2_IRQHandler +EXINT3_IRQHandler +EXINT4_IRQHandler +EXINT5_IRQHandler +EXINT6_IRQHandler +EXINT7_IRQHandler +QPRC0_IRQHandler +QPRC1_IRQHandler +WFG0_DTIF0_IRQHandler +WFG1_DTIF1_IRQHandler +WFG2_DTIF2_IRQHandler +FRT0_PEAK_IRQHandler +FRT0_ZERO_IRQHandler +ICU0_IRQHandler +OCU0_IRQHandler +FRT1_PEAK_IRQHandler +FRT1_ZERO_IRQHandler +ICU1_IRQHandler +OCU1_IRQHandler +FRT2_PEAK_IRQHandler +FRT2_ZERO_IRQHandler +ICU2_IRQHandler +OCU2_IRQHandler +PPG00_02_04_IRQHandler +PPG08_10_12_IRQHandler +PPG16_18_20_IRQHandler +BT0_IRQHandler +BT1_IRQHandler +BT2_IRQHandler +BT3_IRQHandler +BT4_IRQHandler +BT5_IRQHandler +BT6_IRQHandler +BT7_IRQHandler +DT1_2_IRAHandler +WC_IRQHandler +EXTBUS_ERR_Handler +RTC_IRQHandler +EXTINT8_IRQHandler +EXTINT9_IRQHandler +EXTINT10_IRQHandler +EXTINT11_IRQHandler +EXTINT12_IRQHandler +EXTINT13_IRQHandler +EXTINT14_IRQHandler +EXTINT15_IRQHandler +TIM_IRQHandler +MFS0_RX_IRQHandler +MFS0_TX_IRQHandler +MFS1_RX_IRQHandler +MFS1_TX_IRQHandler +MFS2_RX_IRQHandler +MFS2_TX_IRQHandler +MFS3_RX_IRQHandler +MFS3_TX_IRQHandler +MFS4_RX_IRQHandler +MFS4_TX_IRQHandler +MFS5_RX_IRQHandler +MFS5_TX_IRQHandler +MFS6_RX_IRQHandler +MFS6_TX_IRQHandler +MFS7_RX_IRQHandler +MFS7_TX_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +USB0_IRQHandler +USB0_HOST_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +ETHER0_IRQHandler +DMAC0_IRQHandler +DMAC1_IRQHandler +DMAC2_IRQHandler +DMAC3_IRQHandler +DMAC4_IRQHandler +DMAC5_IRQHandler +DMAC6_IRQHandler +DMAC7_IRQHandler +DSTC_IRQHandler +EXINT16_17_18_19_IRQHandler +EXINT20_21_22_23_IRQHandler +EXINT24_25_26_27_IRQHandler +EXINT28_29_30_31_IRQHandler +QPRC2_IRQHandler +QPRC3_IRQHandler +BT8_IRQHandler +BT9_IRQHandler +BT10_IRQHandler +BT11_IRQHandler +BT12_15_IRQHandler +MFS8_RX_IRQHandler +MFS8_TX_IRQHandler +MFS9_RX_IRQHandler +MFS9_TX_IRQHandler +MFS10_RX_IRQHandler +MFS10_TX_IRQHandler +MFS11_RX_IRQHandler +MFS11_TX_IRQHandler +ADC2_IRQHandler +USB1_IRQHandler +USB1_HOST_IRQHandler +SD_IRQHandler +FLASHIF_IRQHandler +MFS12_RX_IRQHandler +MFS12_TX_IRQHandler +MFS13_RX_IRQHandler +MFS13_TX_IRQHandler +MFS14_RX_IRQHandler +MFS14_TX_IRQHandler +MFS15_RX_IRQHandler +MFS15_TX_IRQHandler +Dummy + + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/base_types.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/base_types.h new file mode 100644 index 0000000000..7b2fa72b5c --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/base_types.h @@ -0,0 +1,160 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/*****************************************************************************/ +/** \file base_types.h + ** + ** Additional base type definitions to stddef.h and stdint.h + ** + ** History: + ** - 2013-03-21 1.0 MWi First version. + ** + *****************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include "stdint.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0) +#endif + +/** Returns the minimum value out of two values */ +#define MIN( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAX( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define DIM( X ) (sizeof(X) / sizeof(X[0])) + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCCI character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0, ///< No error + Error = 1, ///< Non-specific error code + ErrorAddressAlignment = 2, ///< Address alignment does not match + ErrorAccessRights = 3, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4, ///< Provided parameter is not valid + ErrorOperationInProgress = 5, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6, ///< Operation not allowed in current mode + ErrorUninitialized = 7, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10, ///< A requested final state is not reached + OperationInProgress = 11 ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + PDLLow = 0, ///< Low level '0' + PDLHigh = 1 ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + PdlClr = 0, ///< Flag clr '0' + PdlSet = 1 ///< Flag set '1' +} en_stat_flag_t, en_int_flag_t; + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S new file mode 100644 index 0000000000..72981f1edb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S @@ -0,0 +1,290 @@ +/**************************************************************************//** + * @file startup_.s + * @brief CMSIS Cortex-M# Core Device Startup File for + * Device + * @version V3.01 + * @date 06. March 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000100 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ +/* ToDo: Add here the vectors for the device specific external interrupts handler */ + .long CSV_Handler /* 0: Clock Super Visor */ + .long SWDT_Handler /* 1: Software Watchdog Timer */ + .long LVD_Handler /* 2: Low Voltage Detector */ + .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + .long DT_Handler /* 6: Dual Timer / Quad Decoder */ + .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + .long PPG_Handler /* 23: PPG */ + .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + .long ADC0_IRQHandler /* 25: ADC0 */ + .long ADC1_IRQHandler /* 26: ADC1 */ + .long ADC2_IRQHandler /* 27: ADC2 */ + .long MFT_FRT_IRQHandler /* 28: Free-run Timer */ + .long MFT_IPC_IRQHandler /* 29: Input Capture */ + .long MFT_OPC_IRQHandler /* 30: Output Compare */ + .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + .long CAN0_IRQHandler /* 32: CAN ch.0 */ + .long CAN1_IRQHandler /* 33: CAN ch.1 */ + .long USBF_Handler /* 34: USB Function */ + .long USB_Handler /* 35: USB Function / USB HOST */ + .long RESERVED_1_IRQHandler /* 36: Reserved */ + .long RESERVED_2_IRQHandler /* 37: Reserved */ + .long DMAC0_Handler /* 38: DMAC ch.0 */ + .long DMAC1_Handler /* 39: DMAC ch.1 */ + .long DMAC2_Handler /* 40: DMAC ch.2 */ + .long DMAC3_Handler /* 41: DMAC ch.3 */ + .long DMAC4_Handler /* 42: DMAC ch.4 */ + .long DMAC5_Handler /* 43: DMAC ch.5 */ + .long DMAC6_Handler /* 44: DMAC ch.6 */ + .long DMAC7_Handler /* 45: DMAC ch.7 */ + .long RESERVED_3_IRQHandler /* 46: Reserved */ + .long RESERVED_4_IRQHandler /* 47: Reserved */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .globl _start + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: +_start: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + +/* ToDo: Add here the export definition for the device specific external interrupts handler */ +/* ToDo: Add here the names for the device specific external interrupts handler */ + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CSV_Handler /* 0: Clock Super Visor */ + IRQ SWDT_Handler /* 1: Software Watchdog Timer */ + IRQ LVD_Handler /* 2: Low Voltage Detector */ + IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */ + IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + IRQ PPG_Handler /* 23: PPG */ + IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + IRQ ADC0_IRQHandler /* 25: ADC0 */ + IRQ ADC1_IRQHandler /* 26: ADC1 */ + IRQ ADC2_IRQHandler /* 27: ADC2 */ + IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */ + IRQ MFT_IPC_IRQHandler /* 29: Input Capture */ + IRQ MFT_OPC_IRQHandler /* 30: Output Compare */ + IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + IRQ CAN0_IRQHandler /* 32: CAN ch.0 */ + IRQ CAN1_IRQHandler /* 33: CAN ch.1 */ + IRQ USBF_Handler /* 34: USB Function */ + IRQ USB_Handler /* 35: USB Function / USB HOST */ + IRQ RESERVED_1_IRQHandler /* 36: Reserved */ + IRQ RESERVED_2_IRQHandler /* 37: Reserved */ + IRQ DMAC0_Handler /* 38: DMAC ch.0 */ + IRQ DMAC1_Handler /* 39: DMAC ch.1 */ + IRQ DMAC2_Handler /* 40: DMAC ch.2 */ + IRQ DMAC3_Handler /* 41: DMAC ch.3 */ + IRQ DMAC4_Handler /* 42: DMAC ch.4 */ + IRQ DMAC5_Handler /* 43: DMAC ch.5 */ + IRQ DMAC6_Handler /* 44: DMAC ch.6 */ + IRQ DMAC7_Handler /* 45: DMAC ch.7 */ + IRQ RESERVED_3_IRQHandler /* 46: Reserved */ + IRQ RESERVED_4_IRQHandler /* 47: Reserved */ + + .end diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h new file mode 100644 index 0000000000..317f63644c --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h @@ -0,0 +1,28433 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file mb9b560r.h + ** + ** Unfified Header File for FM4 PDL + ** + ** History: + ** - 2013-01-21 0.0.1 MWi First version + ** - 2013-02-06 0.0.2 MWi All FM3_ prexifes changed to FM4_; New defines + ** for MFS8-15 added; FM4_MFS_NFC_BASE added + ** - 2013-06-28 0.0.3 EH Modified bitband address of RTC + ** - 2013-08-08 0.0.4 EH Modified UESMCE bit of EPFR20 register to UESMCEE + ** Modified DESP bit of MONERS register to EDESP in DSTC + ** Modified DQID bit of MONERS register to ECH in DSTC + ** Modified HS bit of MONERS register to EHS in DSTC + ** Modified DREQEMSK register to DQMSK in DSTC + ** Added DQMSKCLK register in DSTC + ** Added AN16-AN31 bits to ADE register in GPIO + ** Modified FERRAD bit of FERRAD register to ERRAD + ** Modified DAC register composition + ** - 2013-08-21 0.0.5 EH Added IRQSEL_MODULE definition + ** - 2013-09-10 0.0.6 EH Modified structure of FM4_EXBUS_TypeDef + ** + ******************************************************************************/ + +#ifndef _MB9B560R_H_ +#define _MB9B560R_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ + +#include "mcu.h" + +/** + ****************************************************************************** + ** \brief Interrupt number definition for all type MCUs + ******************************************************************************/ +#if (PDL_MCU_INT_TYPE == PDL_INT_TYPE_A) +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Supervisor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detection */ + IRQ003SEL_IRQn = 3, /* Interrupt Selection IRQ003SEL */ + IRQ004SEL_IRQn = 4, /* Interrupt Selection IRQ004SEL */ + IRQ005SEL_IRQn = 5, /* Interrupt Selection IRQ005SEL */ + IRQ006SEL_IRQn = 6, /* Interrupt Selection IRQ006SEL */ + IRQ007SEL_IRQn = 7, /* Interrupt Selection IRQ007SEL */ + IRQ008SEL_IRQn = 8, /* Interrupt Selection IRQ008SEL */ + IRQ009SEL_IRQn = 9, /* Interrupt Selection IRQ009SEL */ + IRQ010SEL_IRQn = 10, /* Interrupt Selection IRQ010SEL */ + EXINT0_IRQn = 11, /* External Interrupt Ch. 0 */ + EXINT1_IRQn = 12, /* External Interrupt Ch. 1 */ + EXINT2_IRQn = 13, /* External Interrupt Ch. 2 */ + EXINT3_IRQn = 14, /* External Interrupt Ch. 3 */ + EXINT4_IRQn = 15, /* External Interrupt Ch. 4 */ + EXINT5_IRQn = 16, /* External Interrupt Ch. 5 */ + EXINT6_IRQn = 17, /* External Interrupt Ch. 6 */ + EXINT7_IRQn = 18, /* External Interrupt Ch. 7 */ + QPRC0_IRQn = 19, /* Quad Decoder and Revolution Counter Ch. 0 */ + QPRC1_IRQn = 20, /* Quad Decoder and Revolution Counter Ch. 1 */ + WFG0_DTIF0_IRQn = 21, /* MFT0 Wave Form Generator / DTIF */ + WFG1_DTIF1_IRQn = 22, /* MFT1 Wave Form Generator / DTIF */ + WFG2_DTIF2_IRQn = 23, /* MFT2 Wave Form Generator / DTIF */ + FRT0_PEAK_IRQn = 24, /* MFT0 Free Running Timer Peak Detection */ + FRT0_ZERO_IRQn = 25, /* MFT0 Free Running Timer Zero Detection */ + ICU0_IRQn = 26, /* MFT0 Input Capture Unit */ + OCU0_IRQn = 27, /* MFT0 Output Compare Unit */ + FRT1_PEAK_IRQn = 28, /* MFT1 Free Running Timer Peak Detection */ + FRT1_ZERO_IRQn = 29, /* MFT1 Free Running Timer Zero Detection */ + ICU1_IRQn = 30, /* MFT1 Input Capture Unit */ + OCU1_IRQn = 31, /* MFT1 Output Compare Unit */ + FRT2_PEAK_IRQn = 32, /* MFT2 Free Running Timer Peak Detection */ + FRT2_ZERO_IRQn = 33, /* MFT2 Free Running Timer Zero Detection */ + ICU2_IRQn = 34, /* MFT2 Input Capture Unit */ + OCU2_IRQn = 35, /* MFT2 Output Compare Unit */ + PPG00_02_04_IRQn = 36, /* Programmable Pulse Generator Ch. 0, 2, 4 */ + PPG08_10_12_IRQn = 37, /* Programmable Pulse Generator Ch. 8, 10, 12 */ + PPG16_18_20_IRQn = 38, /* Programmable Pulse Generator Ch. 16, 18, 20 */ + BT0_IRQn = 39, /* Base Timer Ch. 0 */ + BT1_IRQn = 40, /* Base Timer Ch. 1 */ + BT2_IRQn = 41, /* Base Timer Ch. 2 */ + BT3_IRQn = 42, /* Base Timer Ch. 3 */ + BT4_IRQn = 43, /* Base Timer Ch. 4 */ + BT5_IRQn = 44, /* Base Timer Ch. 5 */ + BT6_IRQn = 45, /* Base Timer Ch. 6 */ + BT7_IRQn = 46, /* Base Timer Ch. 7 */ + DT1_2_IRQn = 47, /* Dual Timmer Ch. 1, 2 */ + WC_IRQn = 48, /* Watch Counter */ + EXTBUS_ERR_IRQn = 49, /* External Bus Error */ + RTC_IRQn = 50, /* Realtime Clock */ + EXINT8_IRQn = 51, /* External Interrupt Ch. 8 */ + EXINT9_IRQn = 52, /* External Interrupt Ch. 9 */ + EXINT10_IRQn = 53, /* External Interrupt Ch. 10 */ + EXINT11_IRQn = 54, /* External Interrupt Ch. 11 */ + EXINT12_IRQn = 55, /* External Interrupt Ch. 12 */ + EXINT13_IRQn = 56, /* External Interrupt Ch. 13 */ + EXINT14_IRQn = 57, /* External Interrupt Ch. 14 */ + EXINT15_IRQn = 58, /* External Interrupt Ch. 15 */ + TIM_IRQn = 59, /* Clock/PLL Timer */ + MFS0_RX_IRQn = 60, /* Multifunction Serial I/F Reception Ch. 0 */ + MFS0_TX_IRQn = 61, /* Multifunction Serial I/F Transmission Ch. 0 */ + MFS1_RX_IRQn = 62, /* Multifunction Serial I/F Reception Ch. 1 */ + MFS1_TX_IRQn = 63, /* Multifunction Serial I/F Transmission Ch. 1 */ + MFS2_RX_IRQn = 64, /* Multifunction Serial I/F Reception Ch. 2 */ + MFS2_TX_IRQn = 65, /* Multifunction Serial I/F Transmission Ch. 2 */ + MFS3_RX_IRQn = 66, /* Multifunction Serial I/F Reception Ch. 3 */ + MFS3_TX_IRQn = 67, /* Multifunction Serial I/F Transmission Ch. 3 */ + MFS4_RX_IRQn = 68, /* Multifunction Serial I/F Reception Ch. 4 */ + MFS4_TX_IRQn = 69, /* Multifunction Serial I/F Transmission Ch. 4 */ + MFS5_RX_IRQn = 70, /* Multifunction Serial I/F Reception Ch. 5 */ + MFS5_TX_IRQn = 71, /* Multifunction Serial I/F Transmission Ch. 5 */ + MFS6_RX_IRQn = 72, /* Multifunction Serial I/F Reception Ch. 6 */ + MFS6_TX_IRQn = 73, /* Multifunction Serial I/F Transmission Ch. 6 */ + MFS7_RX_IRQn = 74, /* Multifunction Serial I/F Reception Ch. 7 */ + MFS7_TX_IRQn = 75, /* Multifunction Serial I/F Transmission Ch. 7 */ + ADC0_IRQn = 76, /* Analog Digital Converter Unit 0 */ + ADC1_IRQn = 77, /* Analog Digital Converter Unit 1 */ + USB0_IRQn = 78, /* USB0 Function */ + USB0_HOST_IRQn = 79, /* USB0 Function and Host */ + CAN0_IRQn = 80, /* CAN I/F Ch. 0 */ + CAN1_IRQn = 81, /* CAN I/F Ch. 1 */ + ETHER0_IRQn = 82, /* Ethernet */ + DMAC0_IRQn = 83, /* Direct Memory Access Controller Ch. 0 */ + DMAC1_IRQn = 84, /* Direct Memory Access Controller Ch. 1 */ + DMAC2_IRQn = 85, /* Direct Memory Access Controller Ch. 2 */ + DMAC3_IRQn = 86, /* Direct Memory Access Controller Ch. 3 */ + DMAC4_IRQn = 87, /* Direct Memory Access Controller Ch. 4 */ + DMAC5_IRQn = 88, /* Direct Memory Access Controller Ch. 5 */ + DMAC6_IRQn = 89, /* Direct Memory Access Controller Ch. 6 */ + DMAC7_IRQn = 90, /* Direct Memory Access Controller Ch. 7 */ + DSTC_IRQn = 91, /* DSTC SW Transfer */ + EXINT16_17_18_19_IRQn = 92, /* External Interrupt Ch. 16 - 19 */ + EXINT20_21_22_23_IRQn = 93, /* External Interrupt Ch. 20 - 23 */ + EXINT24_25_26_27_IRQn = 94, /* External Interrupt Ch. 24 - 27 */ + EXINT28_29_30_31_IRQn = 95, /* External Interrupt Ch. 28 - 31 */ + QPRC2_IRQn = 96, /* Quad Decoder and Revolution Counter Ch. 2 */ + QPRC3_IRQn = 97, /* Quad Decoder and Revolution Counter Ch. 3 */ + BT8_IRQn = 98, /* Base Timer Ch. 8 */ + BT9_IRQn = 99, /* Base Timer Ch. 9 */ + BT10_IRQn = 100, /* Base Timer Ch. 10 */ + BT11_IRQn = 101, /* Base Timer Ch. 11 */ + BT12_IRQn = 102, /* Base Timer Ch. 12 */ + MFS8_RX_IRQn = 103, /* Multifunction Serial I/F Reception Ch. 8 */ + MFS8_TX_IRQn = 104, /* Multifunction Serial I/F Transmission Ch. 8 */ + MFS9_RX_IRQn = 105, /* Multifunction Serial I/F Reception Ch. 9 */ + MFS9_TX_IRQn = 106, /* Multifunction Serial I/F Transmission Ch. 9 */ + MFS10_RX_IRQn = 107, /* Multifunction Serial I/F Reception Ch. 10 */ + MFS10_TX_IRQn = 108, /* Multifunction Serial I/F Transmission Ch. 10 */ + MFS11_RX_IRQn = 109, /* Multifunction Serial I/F Reception Ch. 11 */ + MFS11_TX_IRQn = 110, /* Multifunction Serial I/F Transmission Ch. 11 */ + ADC2_IRQn = 111, /* Analog Digital Converter Unit 2 */ + USB1_IRQn = 113, /* USB1 Function */ + USB1_HOST_IRQn = 114, /* USB1 Function and Host */ + SD_IRQn = 118, /* SD Card I/F */ + FLASH_IRQn = 119 /* Flash */ +} IRQn_Type; + +#elif (PDL_MCU_INT_TYPE == PDL_INT_TYPE_C) +typedef enum IRQn +{ + NMI_IRQn = -14, /* A<- */ + HardFault_IRQn = -13, /* A<- */ + MemManage_IRQn = -12, /* A<- */ + BusFault_IRQn = -11, /* A<- */ + UsageFault_IRQn = -10, /* A<- */ + SVC_IRQn = -5, /* A<- */ + DebugMonitor_IRQn = -4, /* A<- */ + PendSV_IRQn = -2, /* A<- */ + SysTick_IRQn = -1, /* A<- */ + + CSV_IRQn = 0, /* A<- */ + SWDT_IRQn = 1, /* A<- */ + LVD_IRQn = 2, /* A<- */ + WFG_IRQn = 3, /* A<- */ + EXINT0_7_IRQn = 4, /* A<- */ + EXINT8_31_IRQn = 5, /* A<- */ + MFS0_8_RX_IRQn = 6, /* A<- */ + MFS0_8_TX_IRQn = 7, /* A<- */ + MFS1_9_RX_IRQn = 8, /* A<- */ + MFS1_9_TX_IRQn = 9, /* A<- */ + MFS2_10_RX_IRQn = 10,/* A<- */ + MFS2_10_TX_IRQn = 11,/* A<- */ + MFS3_11_RX_IRQn = 12, /* A<- */ + MFS3_11_TX_IRQn = 13, /* A<- */ + MFS4_12_RX_IRQn = 14, /* A<- */ + MFS4_12_TX_IRQn = 15, /* A<- */ + MFS5_13_RX_IRQn = 16, /* A<- */ + MFS5_13_TX_IRQn = 17, /* A<- */ + MFS6_14_RX_IRQn = 18, /* A<- */ + MFS6_14_TX_IRQn = 19, /* A<- */ + MFS7_15_RX_IRQn = 20, /* A<- */ + MFS7_15_TX_IRQn = 21, /* A<- */ + PPG_IRQn = 22, /* A<- */ + OSC_PLL_WC_RTC_IRQn = 23, /* A<- */ + ADC0_IRQn = 24, /* A<- */ + FRTIM_IRQn = 25, /* A<- */ + INCAP_IRQn = 26, /* A<- */ + OUTCOMP_IRQn = 27, /* A<- */ + BTIM0_7_IRQn = 28, /* A<- */ + ADC2_LCD_IRQn = 29, /* A<- */ + USB1F_HDMICEC0_IRQn = 30, /* A<- */ + USB1F_USB1H_HDMICEC1_IRQn = 31, /* A<- */ +} IRQn_Type; +#else + #error Interrupt Type not found! +#endif // PDL_INT_TYPE + +#include "core_cm4.h" +#include "system_mb9bf56xr.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * INTREQ_MODULE Bit fields and registers depending on device type + ******************************************************************************/ +#if (PDL_MCU_INT_TYPE == PDL_INT_TYPE_A) + +/* Interrupt request read registers */ +typedef struct +{ + __IO uint32_t DRQSEL; + uint8_t RESERVED0[12]; + __IO uint32_t EXC02MON; + __IO uint32_t IRQ00MON; + __IO uint32_t IRQ01MON; + __IO uint32_t IRQ02MON; + __IO uint32_t IRQ03MON; + __IO uint32_t IRQ04MON; + __IO uint32_t IRQ05MON; + __IO uint32_t IRQ06MON; + __IO uint32_t IRQ07MON; + __IO uint32_t IRQ08MON; + __IO uint32_t IRQ09MON; + __IO uint32_t IRQ10MON; + __IO uint32_t IRQ11MON; + __IO uint32_t IRQ12MON; + __IO uint32_t IRQ13MON; + __IO uint32_t IRQ14MON; + __IO uint32_t IRQ15MON; + __IO uint32_t IRQ16MON; + __IO uint32_t IRQ17MON; + __IO uint32_t IRQ18MON; + __IO uint32_t IRQ19MON; + __IO uint32_t IRQ20MON; + __IO uint32_t IRQ21MON; + __IO uint32_t IRQ22MON; + __IO uint32_t IRQ23MON; + __IO uint32_t IRQ24MON; + __IO uint32_t IRQ25MON; + __IO uint32_t IRQ26MON; + __IO uint32_t IRQ27MON; + __IO uint32_t IRQ28MON; + __IO uint32_t IRQ29MON; + __IO uint32_t IRQ30MON; + __IO uint32_t IRQ31MON; + __IO uint32_t IRQ32MON; + __IO uint32_t IRQ33MON; + __IO uint32_t IRQ34MON; + __IO uint32_t IRQ35MON; + __IO uint32_t IRQ36MON; + __IO uint32_t IRQ37MON; + __IO uint32_t IRQ38MON; + __IO uint32_t IRQ39MON; + __IO uint32_t IRQ40MON; + __IO uint32_t IRQ41MON; + __IO uint32_t IRQ42MON; + __IO uint32_t IRQ43MON; + __IO uint32_t IRQ44MON; + __IO uint32_t IRQ45MON; + __IO uint32_t IRQ46MON; + __IO uint32_t IRQ47MON; +}PDL_INTREQ_TypeDef; + +#define PDL_INTREQ_BASE (PDL_PERIPH_BASE + 0x31000UL) // Interrupt request read registers +#define PDL_INTREQ ((PDL_INTREQ_TypeDef *)PDL_INTREQ_BASE) + +#elif (PDL_MCU_INT_TYPE == PDL_INT_TYPE_C) + +/* Interrupt request read registers */ +typedef struct +{ + uint8_t RESERVED0[16]; + __IO uint32_t EXC02MON; + __IO uint32_t IRQ00MON; + __IO uint32_t IRQ01MON; + __IO uint32_t IRQ02MON; + __IO uint32_t IRQ03MON; + __IO uint32_t IRQ04MON; + __IO uint32_t IRQ05MON; + __IO uint32_t IRQ06MON; + __IO uint32_t IRQ07MON; + __IO uint32_t IRQ08MON; + __IO uint32_t IRQ09MON; + __IO uint32_t IRQ10MON; + __IO uint32_t IRQ11MON; + __IO uint32_t IRQ12MON; + __IO uint32_t IRQ13MON; + __IO uint32_t IRQ14MON; + __IO uint32_t IRQ15MON; + __IO uint32_t IRQ16MON; + __IO uint32_t IRQ17MON; + __IO uint32_t IRQ18MON; + __IO uint32_t IRQ19MON; + __IO uint32_t IRQ20MON; + __IO uint32_t IRQ21MON; + __IO uint32_t IRQ22MON; + __IO uint32_t IRQ23MON; + __IO uint32_t IRQ24MON; + __IO uint32_t IRQ25MON; + __IO uint32_t IRQ26MON; + __IO uint32_t IRQ27MON; + __IO uint32_t IRQ28MON; + __IO uint32_t IRQ29MON; + __IO uint32_t IRQ30MON; + __IO uint32_t IRQ31MON; +}PDL_INTREQ_TypeDef; + +#define PDL_INTREQ_BASE (PDL_PERIPH_BASE + 0x31000UL) // Interrupt request read registers +#define FPDL_INTREQ ((PDL_INTREQ_TypeDef *)PDL_INTREQ_BASE) + +#endif // PDL_INT_TYPE + + +/****************************************************************************** + * Peripheral register bit fields + ******************************************************************************/ + +/****************************************************************************** + * WorkFlash_IF_MODULE + ******************************************************************************/ +/* WorkFlash_IF_MODULE register bit fields */ +typedef struct stc_workflash_if_wfaszr_field +{ + __IO uint32_t ASZ : 1; +} stc_workflash_if_wfaszr_field_t; + +typedef struct stc_workflash_if_wfrwtr_field +{ + __IO uint32_t RWT : 3; +} stc_workflash_if_wfrwtr_field_t; + +typedef struct stc_workflash_if_wfstr_field +{ + __IO uint32_t RDY : 1; + __IO uint32_t HNG : 1; +} stc_workflash_if_wfstr_field_t; + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash_IF_MODULE register bit fields */ +typedef struct stc_flash_if_faszr_field +{ + __IO uint32_t ASZ : 2; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + __IO uint32_t RWT : 2; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY : 1; + __IO uint32_t HNG : 1; + __IO uint32_t ERR : 1; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + __IO uint32_t SD : 3; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_fbfcr_field +{ + __IO uint32_t BE : 1; + __IO uint32_t BS : 1; +} stc_flash_if_fbfcr_field_t; + +typedef struct stc_flash_if_ficr_field +{ + __IO uint32_t RDYIE : 1; + __IO uint32_t HANGIE : 1; + __IO uint32_t ERRIE : 1; +} stc_flash_if_ficr_field_t; + +typedef struct stc_flash_if_fisr_field +{ + __IO uint32_t RDYIF : 1; + __IO uint32_t HANGIF : 1; + __IO uint32_t ERRIF : 1; +} stc_flash_if_fisr_field_t; + +typedef struct stc_flash_if_ficlr_field +{ + __IO uint32_t RDYIC : 1; + __IO uint32_t HANGIC : 1; + __IO uint32_t ERRIC : 1; +} stc_flash_if_ficlr_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + __IO uint32_t TRMM :10; + uint32_t RESERVED10 : 6; + __IO uint32_t TTRMM : 5; +} stc_flash_if_crtrmm_field_t; + +/****************************************************************************** + * UNIQUE_ID_MODULE + ******************************************************************************/ +/* UNIQUE_ID_MODULE register bit fields */ +typedef struct stc_unique_id_uidr0_field +{ + uint32_t RESERVED0 : 4; + __IO uint32_t UID :28; +} stc_unique_id_uidr0_field_t; + +typedef struct stc_unique_id_uidr1_field +{ + __IO uint32_t UID :13; +} stc_unique_id_uidr1_field_t; + +/****************************************************************************** + * ECC_CAPTURE_MODULE + ******************************************************************************/ +/* ECC_CAPTURE_MODULE register bit fields */ +typedef struct stc_ecc_capture_ferrad_field +{ + __IO uint32_t ERRAD :23; +} stc_ecc_capture_ferrad_field_t; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock_Reset_MODULE register bit fields */ +typedef struct stc_crg_scm_ctl_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MOSCE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SOSCE : 1; + __IO uint8_t PLLE : 1; + __IO uint8_t RCS : 3; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MORDY : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SORDY : 1; + __IO uint8_t PLRDY : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t RCM2 : 1; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint16_t PONR : 1; + __IO uint16_t INITX : 1; + __IO uint16_t LVDH : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SWDT : 1; + __IO uint16_t HWDT : 1; + __IO uint16_t CSVR : 1; + __IO uint16_t FCSR : 1; + __IO uint16_t SRST : 1; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + __IO uint8_t BSR0 : 1; + __IO uint8_t BSR1 : 1; + __IO uint8_t BSR2 : 1; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + __IO uint8_t APBC00 : 1; + __IO uint8_t APBC01 : 1; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + __IO uint8_t APBC10 : 1; + __IO uint8_t APBC11 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC1RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC1EN : 1; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + __IO uint8_t APBC20 : 1; + __IO uint8_t APBC21 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC2RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC2EN : 1; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + __IO uint8_t SWDS0 : 1; + __IO uint8_t SWDS1 : 1; + uint8_t RESERVED1 : 5; + __IO uint8_t TESTB : 1; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + __IO uint8_t TTC : 2; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + __IO uint8_t MOWT0 : 1; + __IO uint8_t MOWT1 : 1; + __IO uint8_t MOWT2 : 1; + __IO uint8_t MOWT3 : 1; + __IO uint8_t SOWT0 : 1; + __IO uint8_t SOWT1 : 1; + __IO uint8_t SOWT2 : 1; + __IO uint8_t SOWT3 : 1; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + __IO uint8_t POWT0 : 1; + __IO uint8_t POWT1 : 1; + __IO uint8_t POWT2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t PINC : 1; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + __IO uint8_t PLLM0 : 1; + __IO uint8_t PLLM1 : 1; + __IO uint8_t PLLM2 : 1; + __IO uint8_t PLLM3 : 1; + __IO uint8_t PLLK0 : 1; + __IO uint8_t PLLK1 : 1; + __IO uint8_t PLLK2 : 1; + __IO uint8_t PLLK3 : 1; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + __IO uint8_t PLLN0 : 1; + __IO uint8_t PLLN1 : 1; + __IO uint8_t PLLN2 : 1; + __IO uint8_t PLLN3 : 1; + __IO uint8_t PLLN4 : 1; + __IO uint8_t PLLN5 : 1; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + __IO uint16_t MCSVE : 1; + __IO uint16_t SCSVE : 1; + uint16_t RESERVED1 : 6; + __IO uint16_t FCSDE : 1; + __IO uint16_t FCSRE : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t FCD0 : 1; + __IO uint16_t FCD1 : 1; + __IO uint16_t FCD2 : 1; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint8_t MCMF : 1; + __IO uint8_t SCMF : 1; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + uint8_t RESERVED1 : 5; + __IO uint8_t DPSWBE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t DPHWBE : 1; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint8_t MCSE : 1; + __IO uint8_t SCSE : 1; + __IO uint8_t PCSE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSE : 1; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint8_t MCSI : 1; + __IO uint8_t SCSI : 1; + __IO uint8_t PCSI : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSI : 1; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint8_t MCSC : 1; + __IO uint8_t SCSC : 1; + __IO uint8_t PCSC : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSC : 1; +} stc_crg_int_clr_field_t; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* HWWDT_MODULE register bit fields */ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint8_t RIS : 1; +} stc_hwwdt_wdg_ris_field_t; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* SWWDT_MODULE register bit fields */ +typedef struct stc_swwdt_wdogcontrol_field +{ + union { + struct { + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; + __IO uint8_t TWD : 2; + __IO uint8_t SPM : 1; + uint8_t RESERVED1 : 3; + }; + struct { + uint8_t RESERVED2 : 2; + __IO uint8_t TWD0 : 1; + __IO uint8_t TWD1 : 1; + uint8_t RESERVED3 : 4; + }; + }; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint8_t RIS : 1; + uint8_t RESERVED1 : 7; +} stc_swwdt_wdogris_field_t; + +typedef struct stc_swwdt_wdogspmc_field +{ + __IO uint8_t TGR : 1; + uint8_t RESERVED1 : 7; +} stc_swwdt_wdogspmc_field_t; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* DTIM_MODULE register bit fields */ +typedef struct stc_dtim_timerXcontrol_field +{ + union { + struct { + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE : 2; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; + uint32_t RESERVED2 : 24; + }; + struct { + uint32_t RESERVED3 : 2; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED4 : 28; + }; + }; +} stc_dtim_timerXcontrol_field_t; + +typedef struct stc_dtim_timerXris_field +{ + __IO uint32_t TIMERXRIS : 1; + uint32_t RESERVED1 : 31; +} stc_dtim_timerXris_field_t; + +typedef struct stc_dtim_timerXmis_field +{ + __IO uint32_t TIMERXMIS : 1; + uint32_t RESERVED1 : 31; +} stc_dtim_timerXmis_field_t; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* MFT_FRT_MODULE register bit fields */ +typedef struct stc_mft_frt_tcsa0_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsc0_field +{ + __IO uint16_t MSZI : 4; + __IO uint16_t MSPI : 4; + __IO uint16_t MSZC : 4; + __IO uint16_t MSPC : 4; +} stc_mft_frt_tcsc0_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsc1_field +{ + __IO uint16_t MSZI : 4; + __IO uint16_t MSPI : 4; + __IO uint16_t MSZC : 4; + __IO uint16_t MSPC : 4; +} stc_mft_frt_tcsc1_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsc2_field +{ + __IO uint16_t MSZI : 4; + __IO uint16_t MSPI : 4; + __IO uint16_t MSZC : 4; + __IO uint16_t MSPC : 4; +} stc_mft_frt_tcsc2_field_t; + +typedef struct stc_mft_frt_tcal_field +{ + __IO uint32_t STOP00 : 1; + __IO uint32_t STOP01 : 1; + __IO uint32_t STOP02 : 1; + __IO uint32_t STOP10 : 1; + __IO uint32_t STOP11 : 1; + __IO uint32_t STOP12 : 1; + __IO uint32_t STOP20 : 1; + __IO uint32_t STOP21 : 1; + __IO uint32_t STOP22 : 1; + __IO uint32_t RESERVED1 : 7; + __IO uint32_t SCLR00 : 1; + __IO uint32_t SCLR01 : 1; + __IO uint32_t SCLR02 : 1; + __IO uint32_t SCLR10 : 1; + __IO uint32_t SCLR11 : 1; + __IO uint32_t SCLR12 : 1; + __IO uint32_t SCLR20 : 1; + __IO uint32_t SCLR21 : 1; + __IO uint32_t SCLR22 : 1; + __IO uint32_t RESERVED2 : 7; +} stc_mft_frt_tcal_field_t; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* MFT_OCU_MODULE register bit fields */ +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t RESERVED1 : 2; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t FM4 : 1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t RESERVED1 : 2; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t FM4 : 1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t RESERVED1 : 2; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t FM4 : 1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 : 1; + __IO uint8_t MOD1 : 1; + __IO uint8_t MOD2 : 1; + __IO uint8_t MOD3 : 1; + __IO uint8_t MOD4 : 1; + __IO uint8_t MOD5 : 1; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs54_field_t; + +typedef struct stc_mft_ocu_ocsd10_field +{ + __IO uint8_t OCCP0BUFE : 2; + __IO uint8_t OCCP1BUFE : 2; + __IO uint8_t OCSE0BUFE : 2; + __IO uint8_t OCSE1BUFE : 2; +} stc_mft_ocu_ocsd10_field_t; + +typedef struct stc_mft_ocu_ocsd32_field +{ + __IO uint8_t OCCP2BUFE : 2; + __IO uint8_t OCCP3BUFE : 2; + __IO uint8_t OCSE2BUFE : 2; + __IO uint8_t OCSE3BUFE : 2; +} stc_mft_ocu_ocsd32_field_t; + +typedef struct stc_mft_ocu_ocsd54_field +{ + __IO uint8_t OCCP4BUFE : 2; + __IO uint8_t OCCP5BUFE : 2; + __IO uint8_t OCSE4BUFE : 2; + __IO uint8_t OCSE5BUFE : 2; +} stc_mft_ocu_ocsd54_field_t; + +typedef struct stc_mft_ocu_ocse0_field +{ + __IO uint16_t OCSE : 16; +} stc_mft_ocu_ocse0_field_t; + +typedef struct stc_mft_ocu_ocse1_field +{ + __IO uint32_t OCSE : 32; +} stc_mft_ocu_ocse1_field_t; + +typedef struct stc_mft_ocu_ocse2_field +{ + __IO uint16_t OCSE : 16; +} stc_mft_ocu_ocse2_field_t; + +typedef struct stc_mft_ocu_ocse3_field +{ + __IO uint32_t OCSE : 32; +} stc_mft_ocu_ocse3_field_t; + +typedef struct stc_mft_ocu_ocse4_field +{ + __IO uint16_t OCSE : 16; +} stc_mft_ocu_ocse4_field_t; + +typedef struct stc_mft_ocu_ocse5_field +{ + __IO uint32_t OCSE : 32; +} stc_mft_ocu_ocse5_field_t; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* MFT_WFG_MODULE register bit fields */ +typedef struct stc_mft_wfg_wfsa10_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 2; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 2; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 2; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIFA : 1; + __IO uint16_t DTICA : 1; + __IO uint16_t DTIFB : 1; + __IO uint16_t DTICB : 1; + __IO uint16_t TMIF10 : 1; + __IO uint16_t TMIC10 : 1; + __IO uint16_t TMIE10 : 1; + __IO uint16_t TMIS10 : 1; + __IO uint16_t TMIF32 : 1; + __IO uint16_t TMIC32 : 1; + __IO uint16_t TMIE32 : 1; + __IO uint16_t TMIS32 : 1; + __IO uint16_t TMIF54 : 1; + __IO uint16_t TMIC54 : 1; + __IO uint16_t TMIE54 : 1; + __IO uint16_t TMIS54 : 1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + __IO uint16_t DTIEA : 1; + __IO uint16_t NWS0 : 1; + __IO uint16_t NWS1 : 1; + __IO uint16_t NWS2 : 1; + __IO uint16_t SDTI : 1; + __IO uint16_t DTIEB : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t DIMA : 1; + __IO uint16_t DIMB : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t WIM10 : 1; + __IO uint16_t WIM32 : 1; + __IO uint16_t WIM54 : 1; + uint16_t RESERVED3 : 1; +} stc_mft_wfg_nzcl_field_t; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* MFT_ICU_MODULE register bit fields */ +typedef struct stc_mft_icu_icfs10_field +{ + __IO uint8_t FSI00 : 1; + __IO uint8_t FSI01 : 1; + __IO uint8_t FSI02 : 1; + __IO uint8_t FSI03 : 1; + __IO uint8_t FSI10 : 1; + __IO uint8_t FSI11 : 1; + __IO uint8_t FSI12 : 1; + __IO uint8_t FSI13 : 1; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + __IO uint8_t FSI00 : 1; + __IO uint8_t FSI01 : 1; + __IO uint8_t FSI02 : 1; + __IO uint8_t FSI03 : 1; + __IO uint8_t FSI10 : 1; + __IO uint8_t FSI11 : 1; + __IO uint8_t FSI12 : 1; + __IO uint8_t FSI13 : 1; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + __IO uint8_t EG00 : 1; + __IO uint8_t EG01 : 1; + __IO uint8_t EG10 : 1; + __IO uint8_t EG11 : 1; + __IO uint8_t ICE0 : 1; + __IO uint8_t ICE1 : 1; + __IO uint8_t ICP0 : 1; + __IO uint8_t ICP1 : 1; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 : 1; + __IO uint8_t IEI1 : 1; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + __IO uint8_t EG00 : 1; + __IO uint8_t EG01 : 1; + __IO uint8_t EG10 : 1; + __IO uint8_t EG11 : 1; + __IO uint8_t ICE0 : 1; + __IO uint8_t ICE1 : 1; + __IO uint8_t ICP0 : 1; + __IO uint8_t ICP1 : 1; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI0 : 1; + __IO uint8_t IEI1 : 1; +} stc_mft_icu_icsb32_field_t; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* MFT_ADCMP_MODULE register bit fields */ +typedef struct stc_mft_adcmp_acfs10_field +{ + __IO uint8_t FSA0 : 4; + __IO uint8_t FSA1 : 4; +} stc_mft_adcmp_acfs10_field_t; + +typedef struct stc_mft_adcmp_acfs32_field +{ + __IO uint8_t FSA2 : 4; + __IO uint8_t FSA3 : 4; +} stc_mft_adcmp_acfs32_field_t; + +typedef struct stc_mft_adcmp_acfs54_field +{ + __IO uint8_t FSA4 : 4; + __IO uint8_t FSA5 : 4; +} stc_mft_adcmp_acfs54_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + __IO uint16_t CE10 : 2; + __IO uint16_t CE32 : 2; + __IO uint16_t CE54 : 2; + uint16_t RESERVED1 : 2; + __IO uint16_t SEL10 : 2; + __IO uint16_t SEL32 : 2; + __IO uint16_t SEL54 : 2; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_acsc_field +{ + __IO uint8_t BUFE : 2; + __IO uint8_t ADSEL : 3; + uint8_t RESERVED1 : 3; +} stc_mft_adcmp_acsc_field_t; + +typedef struct stc_mft_adcmp_acsd_field +{ + __IO uint8_t AMOD : 1; + __IO uint8_t OCUS : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t DE : 1; + __IO uint8_t PE : 1; + __IO uint8_t UE : 1; + __IO uint8_t ZE : 1; +} stc_mft_adcmp_acsd_field_t; + +/****************************************************************************** + * DAC MODULE + ******************************************************************************/ +typedef struct stc_dacr_field +{ + __IO uint8_t DAE : 1; + __IO uint8_t DRDY : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t DAC10 : 1; + __IO uint8_t DDAS : 1; + __IO uint8_t RESERVED2 : 2; +} stc_dacr_field_t; + +typedef struct stc_dadr_field +{ + __IO uint16_t DA : 12; + __IO uint16_t RESERVED : 4; +} stc_dadr_field_t; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* MFT_PPG_MODULE register bit fields */ +typedef struct stc_mft_ppg_ttcr0_field +{ + __IO uint8_t STR0 : 1; + __IO uint8_t MONI0 : 1; + __IO uint8_t CS00 : 1; + __IO uint8_t CS01 : 1; + __IO uint8_t TRG0O : 1; + __IO uint8_t TRG2O : 1; + __IO uint8_t TRG4O : 1; + __IO uint8_t TRG6O : 1; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + __IO uint8_t STR1 : 1; + __IO uint8_t MONI1 : 1; + __IO uint8_t CS10 : 1; + __IO uint8_t CS11 : 1; + __IO uint8_t TRG1O : 1; + __IO uint8_t TRG3O : 1; + __IO uint8_t TRG5O : 1; + __IO uint8_t TRG7O : 1; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_ttcr2_field +{ + __IO uint8_t STR2 : 1; + __IO uint8_t MONI2 : 1; + __IO uint8_t CS20 : 1; + __IO uint8_t CS21 : 1; + __IO uint8_t TRG16O : 1; + __IO uint8_t TRG18O : 1; + __IO uint8_t TRG20O : 1; + __IO uint8_t TRG22O : 1; +} stc_mft_ppg_ttcr2_field_t; + +typedef struct stc_mft_ppg_trg_field +{ + __IO uint16_t PEN00 : 1; + __IO uint16_t PEN01 : 1; + __IO uint16_t PEN02 : 1; + __IO uint16_t PEN03 : 1; + __IO uint16_t PEN04 : 1; + __IO uint16_t PEN05 : 1; + __IO uint16_t PEN06 : 1; + __IO uint16_t PEN07 : 1; + __IO uint16_t PEN08 : 1; + __IO uint16_t PEN09 : 1; + __IO uint16_t PEN10 : 1; + __IO uint16_t PEN11 : 1; + __IO uint16_t PEN12 : 1; + __IO uint16_t PEN13 : 1; + __IO uint16_t PEN14 : 1; + __IO uint16_t PEN15 : 1; +} stc_mft_ppg_trg0_field_t; + +typedef struct stc_mft_ppg_trg1_field +{ + __IO uint16_t PEN16 : 1; + __IO uint16_t PEN17 : 1; + __IO uint16_t PEN18 : 1; + __IO uint16_t PEN19 : 1; + __IO uint16_t PEN20 : 1; + __IO uint16_t PEN21 : 1; + __IO uint16_t PEN22 : 1; + __IO uint16_t PEN23 : 1; +} stc_mft_ppg_trg1_field_t; + +typedef struct stc_mft_ppg_revc_field +{ + __IO uint16_t REV00 : 1; + __IO uint16_t REV01 : 1; + __IO uint16_t REV02 : 1; + __IO uint16_t REV03 : 1; + __IO uint16_t REV04 : 1; + __IO uint16_t REV05 : 1; + __IO uint16_t REV06 : 1; + __IO uint16_t REV07 : 1; + __IO uint16_t REV08 : 1; + __IO uint16_t REV09 : 1; + __IO uint16_t REV10 : 1; + __IO uint16_t REV11 : 1; + __IO uint16_t REV12 : 1; + __IO uint16_t REV13 : 1; + __IO uint16_t REV14 : 1; + __IO uint16_t REV15 : 1; +} stc_mft_ppg_revc0_field_t; + +typedef struct stc_mft_ppg_revc1_field +{ + __IO uint16_t REV16 : 1; + __IO uint16_t REV17 : 1; + __IO uint16_t REV18 : 1; + __IO uint16_t REV19 : 1; + __IO uint16_t REV20 : 1; + __IO uint16_t REV21 : 1; + __IO uint16_t REV22 : 1; + __IO uint16_t REV23 : 1; +} stc_mft_ppg_revc1_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 : 1; + __IO uint8_t STRG0 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE2 : 1; + __IO uint8_t STRG2 : 1; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 : 1; + __IO uint8_t STRG4 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE6 : 1; + __IO uint8_t STRG6 : 1; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 : 1; + __IO uint8_t STRG8 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE10 : 1; + __IO uint8_t STRG10 : 1; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 : 1; + __IO uint8_t STRG12 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE14 : 1; + __IO uint8_t STRG14 : 1; +} stc_mft_ppg_gatec12_field_t; + +typedef struct stc_mft_ppg_ppgc17_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc17_field_t; + +typedef struct stc_mft_ppg_ppgc16_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc16_field_t; + +typedef struct stc_mft_ppg_ppgc19_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc19_field_t; + +typedef struct stc_mft_ppg_ppgc18_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc18_field_t; + +typedef struct stc_mft_ppg_gatec16_field +{ + __IO uint8_t EDGE16 : 1; + __IO uint8_t STRG16 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE18 : 1; + __IO uint8_t STRG18 : 1; +} stc_mft_ppg_gatec16_field_t; + +typedef struct stc_mft_ppg_ppgc21_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc21_field_t; + +typedef struct stc_mft_ppg_ppgc20_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc20_field_t; + +typedef struct stc_mft_ppg_ppgc23_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc23_field_t; + +typedef struct stc_mft_ppg_ppgc22_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc22_field_t; + +typedef struct stc_mft_ppg_gatec20_field +{ + __IO uint8_t EDGE20 : 1; + __IO uint8_t STRG20 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE22 : 1; + __IO uint8_t STRG22 : 1; +} stc_mft_ppg_gatec20_field_t; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* BT_PPG_MODULE register bit fields */ +typedef struct stc_bt_ppg_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_ppg_tmcr2_field_t; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* BT_PWM_MODULE register bit fields */ +typedef struct stc_bt_pwm_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR : 1; + __IO uint8_t DTIR : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t UDIE : 1; + __IO uint8_t DTIE : 1; + __IO uint8_t TGIE : 1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwm_tmcr2_field_t; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* BT_RT_MODULE register bit fields */ +typedef struct stc_bt_rt_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 : 1; + __IO uint8_t RESERVED1 : 6; + __IO uint8_t GATE : 1; +} stc_bt_rt_tmcr2_field_t; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* BT_PWC_MODULE register bit fields */ +typedef struct stc_bt_pwc_tmcr_field +{ + uint16_t RESERVED1 : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t EGS2 : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t EDIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t OVIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t EDIE : 1; + __IO uint8_t ERR : 1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwc_tmcr2_field_t; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* BTIOSEL03_MODULE register bit fields */ +typedef struct stc_btiosel03_btsel0123_field +{ + __IO uint8_t SEL01_0 : 1; + __IO uint8_t SEL01_1 : 1; + __IO uint8_t SEL01_2 : 1; + __IO uint8_t SEL01_3 : 1; + __IO uint8_t SEL23_0 : 1; + __IO uint8_t SEL23_1 : 1; + __IO uint8_t SEL23_2 : 1; + __IO uint8_t SEL23_3 : 1; +} stc_btiosel03_btsel0123_field_t; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* BTIOSEL47_MODULE register bit fields */ +typedef struct stc_btiosel47_btsel4567_field +{ + __IO uint8_t SEL45_0 : 1; + __IO uint8_t SEL45_1 : 1; + __IO uint8_t SEL45_2 : 1; + __IO uint8_t SEL45_3 : 1; + __IO uint8_t SEL67_0 : 1; + __IO uint8_t SEL67_1 : 1; + __IO uint8_t SEL67_2 : 1; + __IO uint8_t SEL67_3 : 1; +} stc_btiosel47_btsel4567_field_t; + +/****************************************************************************** + * BTIOSEL811_MODULE + ******************************************************************************/ +/* BTIOSEL811_MODULE register bit fields */ +typedef struct stc_btiosel8b_btsel89ab_field +{ + __IO uint8_t SEL89_0 : 1; + __IO uint8_t SEL89_1 : 1; + __IO uint8_t SEL89_2 : 1; + __IO uint8_t SEL89_3 : 1; + __IO uint8_t SELAB_0 : 1; + __IO uint8_t SELAB_1 : 1; + __IO uint8_t SELAB_2 : 1; + __IO uint8_t SELAB_3 : 1; +} stc_btiosel8b_btsel89ab_field_t; + +/****************************************************************************** + * BTIOSEL1215_MODULE + ******************************************************************************/ +/* BTIOSEL1215_MODULE register bit fields */ +typedef struct stc_btioselcf_btselcdef_field +{ + __IO uint8_t SELCD_0 : 1; + __IO uint8_t SELCD_1 : 1; + __IO uint8_t SELCD_2 : 1; + __IO uint8_t SELCD_3 : 1; + __IO uint8_t SELEF_0 : 1; + __IO uint8_t SELEF_1 : 1; + __IO uint8_t SELEF_2 : 1; + __IO uint8_t SELEF_3 : 1; +} stc_btioselcf_btselcdef_field_t; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* SBSSR_MODULE register bit fields */ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSR0 : 1; + __IO uint16_t SSR1 : 1; + __IO uint16_t SSR2 : 1; + __IO uint16_t SSR3 : 1; + __IO uint16_t SSR4 : 1; + __IO uint16_t SSR5 : 1; + __IO uint16_t SSR6 : 1; + __IO uint16_t SSR7 : 1; + __IO uint16_t SSR8 : 1; + __IO uint16_t SSR9 : 1; + __IO uint16_t SSR10 : 1; + __IO uint16_t SSR11 : 1; + __IO uint16_t SSR12 : 1; + __IO uint16_t SSR13 : 1; + __IO uint16_t SSR14 : 1; + __IO uint16_t SSR15 : 1; +} stc_sbssr_btsssr_field_t; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* QPRC_MODULE register bit fields */ +typedef struct stc_qprc_qicr_field +{ + __IO uint16_t QPCMIE : 1; + __IO uint16_t QPCMF : 1; + __IO uint16_t QPRCMIE : 1; + __IO uint16_t QPRCMF : 1; + __IO uint16_t OUZIE : 1; + __IO uint16_t UFDF : 1; + __IO uint16_t OFDF : 1; + __IO uint16_t ZIIF : 1; + __IO uint16_t CDCIE : 1; + __IO uint16_t CDCF : 1; + __IO uint16_t DIRPC : 1; + __IO uint16_t DIROU : 1; + __IO uint16_t QPCNRCMIE : 1; + __IO uint16_t QPCNRCMF : 1; +} stc_qprc_qicr_field_t; + +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE : 1; + __IO uint8_t QPCMF : 1; + __IO uint8_t QPRCMIE : 1; + __IO uint8_t QPRCMF : 1; + __IO uint8_t OUZIE : 1; + __IO uint8_t UFDF : 1; + __IO uint8_t OFDF : 1; + __IO uint8_t ZIIF : 1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE : 1; + __IO uint8_t CDCF : 1; + __IO uint8_t DIRPC : 1; + __IO uint8_t DIROU : 1; + __IO uint8_t QPCNRCMIE : 1; + __IO uint8_t QPCNRCMF : 1; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + __IO uint16_t PCM0 : 1; + __IO uint16_t PCM1 : 1; + __IO uint16_t RCM0 : 1; + __IO uint16_t RCM1 : 1; + __IO uint16_t PSTP : 1; + __IO uint16_t CGSC : 1; + __IO uint16_t RSEL : 1; + __IO uint16_t SWAP : 1; + __IO uint16_t PCRM0 : 1; + __IO uint16_t PCRM1 : 1; + __IO uint16_t AES0 : 1; + __IO uint16_t AES1 : 1; + __IO uint16_t BES0 : 1; + __IO uint16_t BES1 : 1; + __IO uint16_t CGE0 : 1; + __IO uint16_t CGE1 : 1; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qcrl_field +{ + __IO uint8_t PCM0 : 1; + __IO uint8_t PCM1 : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t PSTP : 1; + __IO uint8_t CGSC : 1; + __IO uint8_t RSEL : 1; + __IO uint8_t SWAP : 1; +} stc_qprc_qcrl_field_t; + +typedef struct stc_qprc_qcrh_field +{ + __IO uint8_t PCRM0 : 1; + __IO uint8_t PCRM1 : 1; + __IO uint8_t AES0 : 1; + __IO uint8_t AES1 : 1; + __IO uint8_t BES0 : 1; + __IO uint8_t BES1 : 1; + __IO uint8_t CGE0 : 1; + __IO uint8_t CGE1 : 1; +} stc_qprc_qcrh_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD : 1; + __IO uint16_t ORNGF : 1; + __IO uint16_t ORNGIE : 1; +} stc_qprc_qecr_field_t; + +/****************************************************************************** + * QPRC_NF_MODULE + ******************************************************************************/ +/* QPRC_NF_MODULE register bit fields */ +typedef struct stc_qprc_nf_nfctla_field +{ + __IO uint8_t AINNWS : 3; + uint8_t RESERVED1 : 1; + __IO uint8_t AINLV : 1; + __IO uint8_t AINMD : 1; +} stc_qprc_nf_nfctla_field_t; + +typedef struct stc_qprc_nf_nfctlb_field +{ + __IO uint8_t BINNWS : 3; + uint8_t RESERVED1 : 1; + __IO uint8_t BINLV : 1; + __IO uint8_t BINMD : 1; +} stc_qprc_nf_nfctlb_field_t; + +typedef struct stc_qprc_nf_nfrctlz_field +{ + __IO uint8_t ZINNWS : 3; + uint8_t RESERVED1 : 1; + __IO uint8_t ZINLV : 1; + __IO uint8_t ZINMD : 1; +} stc_qprc_nf_nfrctlz_field_t; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* ADC12_MODULE register bit fields */ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS : 1; + __IO uint8_t PCS : 1; + __IO uint8_t PCNS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t FDAS : 1; + __IO uint8_t ADSTP : 1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE : 1; + __IO uint8_t CMPIE : 1; + __IO uint8_t PCIE : 1; + __IO uint8_t SCIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t CMPIF : 1; + __IO uint8_t PCIF : 1; + __IO uint8_t SCIF : 1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + __IO uint8_t SFS0 : 1; + __IO uint8_t SFS1 : 1; + __IO uint8_t SFS2 : 1; + __IO uint8_t SFS3 : 1; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR : 1; + __IO uint8_t SHEN : 1; + __IO uint8_t RPT : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t SFCLR : 1; + __IO uint8_t SOVR : 1; + __IO uint8_t SFUL : 1; + __IO uint8_t SEMP : 1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_field +{ + __IO uint32_t SC0 : 1; + __IO uint32_t SC1 : 1; + __IO uint32_t SC2 : 1; + __IO uint32_t SC3 : 1; + __IO uint32_t SC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; + __IO uint32_t SD3 : 1; + __IO uint32_t SD4 : 1; + __IO uint32_t SD5 : 1; + __IO uint32_t SD6 : 1; + __IO uint32_t SD7 : 1; + __IO uint32_t SD8 : 1; + __IO uint32_t SD9 : 1; + __IO uint32_t SD10 : 1; + __IO uint32_t SD11 : 1; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scfdl_field +{ + __IO uint16_t SC0 : 1; + __IO uint16_t SC1 : 1; + __IO uint16_t SC2 : 1; + __IO uint16_t SC3 : 1; + __IO uint16_t SC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t INVL : 1; +} stc_adc_scfdl_field_t; + +typedef struct stc_adc_scfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t SD0 : 1; + __IO uint16_t SD1 : 1; + __IO uint16_t SD2 : 1; + __IO uint16_t SD3 : 1; + __IO uint16_t SD4 : 1; + __IO uint16_t SD5 : 1; + __IO uint16_t SD6 : 1; + __IO uint16_t SD7 : 1; + __IO uint16_t SD8 : 1; + __IO uint16_t SD9 : 1; + __IO uint16_t SD10 : 1; + __IO uint16_t SD11 : 1; +} stc_adc_scfdh_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 : 1; + __IO uint16_t AN17 : 1; + __IO uint16_t AN18 : 1; + __IO uint16_t AN19 : 1; + __IO uint16_t AN20 : 1; + __IO uint16_t AN21 : 1; + __IO uint16_t AN22 : 1; + __IO uint16_t AN23 : 1; + __IO uint16_t AN24 : 1; + __IO uint16_t AN25 : 1; + __IO uint16_t AN26 : 1; + __IO uint16_t AN27 : 1; + __IO uint16_t AN28 : 1; + __IO uint16_t AN29 : 1; + __IO uint16_t AN30 : 1; + __IO uint16_t AN31 : 1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis2_field +{ + __IO uint8_t AN16 : 1; + __IO uint8_t AN17 : 1; + __IO uint8_t AN18 : 1; + __IO uint8_t AN19 : 1; + __IO uint8_t AN20 : 1; + __IO uint8_t AN21 : 1; + __IO uint8_t AN22 : 1; + __IO uint8_t AN23 : 1; +} stc_adc_scis2_field_t; + +typedef struct stc_adc_scis3_field +{ + __IO uint8_t AN24 : 1; + __IO uint8_t AN25 : 1; + __IO uint8_t AN26 : 1; + __IO uint8_t AN27 : 1; + __IO uint8_t AN28 : 1; + __IO uint8_t AN29 : 1; + __IO uint8_t AN30 : 1; + __IO uint8_t AN31 : 1; +} stc_adc_scis3_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 : 1; + __IO uint16_t AN1 : 1; + __IO uint16_t AN2 : 1; + __IO uint16_t AN3 : 1; + __IO uint16_t AN4 : 1; + __IO uint16_t AN5 : 1; + __IO uint16_t AN6 : 1; + __IO uint16_t AN7 : 1; + __IO uint16_t AN8 : 1; + __IO uint16_t AN9 : 1; + __IO uint16_t AN10 : 1; + __IO uint16_t AN11 : 1; + __IO uint16_t AN12 : 1; + __IO uint16_t AN13 : 1; + __IO uint16_t AN14 : 1; + __IO uint16_t AN15 : 1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_scis0_field +{ + __IO uint8_t AN0 : 1; + __IO uint8_t AN1 : 1; + __IO uint8_t AN2 : 1; + __IO uint8_t AN3 : 1; + __IO uint8_t AN4 : 1; + __IO uint8_t AN5 : 1; + __IO uint8_t AN6 : 1; + __IO uint8_t AN7 : 1; +} stc_adc_scis0_field_t; + +typedef struct stc_adc_scis1_field +{ + __IO uint8_t AN8 : 1; + __IO uint8_t AN9 : 1; + __IO uint8_t AN10 : 1; + __IO uint8_t AN11 : 1; + __IO uint8_t AN12 : 1; + __IO uint8_t AN13 : 1; + __IO uint8_t AN14 : 1; + __IO uint8_t AN15 : 1; +} stc_adc_scis1_field_t; + +typedef struct stc_adc_pfns_field +{ + __IO uint8_t PFS : 2; + uint8_t RESERVED1 : 2; + __IO uint8_t TEST0 : 1; + __IO uint8_t TEST1 : 1; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR : 1; + __IO uint8_t PHEN : 1; + __IO uint8_t PEEN : 1; + __IO uint8_t ESCE : 1; + __IO uint8_t PFCLR : 1; + __IO uint8_t POVR : 1; + __IO uint8_t PFUL : 1; + __IO uint8_t PEMP : 1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_field +{ + __IO uint32_t PC0 : 1; + __IO uint32_t PC1 : 1; + __IO uint32_t PC2 : 1; + __IO uint32_t PC3 : 1; + __IO uint32_t PC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t PD0 : 1; + __IO uint32_t PD1 : 1; + __IO uint32_t PD2 : 1; + __IO uint32_t PD3 : 1; + __IO uint32_t PD4 : 1; + __IO uint32_t PD5 : 1; + __IO uint32_t PD6 : 1; + __IO uint32_t PD7 : 1; + __IO uint32_t PD8 : 1; + __IO uint32_t PD9 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcfdl_field +{ + __IO uint16_t PC0 : 1; + __IO uint16_t PC1 : 1; + __IO uint16_t PC2 : 1; + __IO uint16_t PC3 : 1; + __IO uint16_t PC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + __IO uint16_t RS2 : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t INVL : 1; +} stc_adc_pcfdl_field_t; + +typedef struct stc_adc_pcfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t PD0 : 1; + __IO uint16_t PD1 : 1; + __IO uint16_t PD2 : 1; + __IO uint16_t PD3 : 1; + __IO uint16_t PD4 : 1; + __IO uint16_t PD5 : 1; + __IO uint16_t PD6 : 1; + __IO uint16_t PD7 : 1; + __IO uint16_t PD8 : 1; + __IO uint16_t PD9 : 1; + __IO uint16_t PD10 : 1; + __IO uint16_t PD11 : 1; +} stc_adc_pcfdh_field_t; + +typedef struct stc_adc_pcis_field +{ + __IO uint8_t P1A : 3; + __IO uint8_t P2A : 5; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + __IO uint8_t CCH : 5; + __IO uint8_t CMD0 : 1; + __IO uint8_t CMD1 : 1; + __IO uint8_t CMPEN : 1; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + uint16_t RESERVED1 : 6; + __IO uint16_t CMAD2 : 1; + __IO uint16_t CMAD3 : 1; + __IO uint16_t CMAD4 : 1; + __IO uint16_t CMAD5 : 1; + __IO uint16_t CMAD6 : 1; + __IO uint16_t CMAD7 : 1; + __IO uint16_t CMAD8 : 1; + __IO uint16_t CMAD9 : 1; + __IO uint16_t CMAD10 : 1; + __IO uint16_t CMAD11 : 1; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 : 1; + __IO uint16_t TS17 : 1; + __IO uint16_t TS18 : 1; + __IO uint16_t TS19 : 1; + __IO uint16_t TS20 : 1; + __IO uint16_t TS21 : 1; + __IO uint16_t TS22 : 1; + __IO uint16_t TS23 : 1; + __IO uint16_t TS24 : 1; + __IO uint16_t TS25 : 1; + __IO uint16_t TS26 : 1; + __IO uint16_t TS27 : 1; + __IO uint16_t TS28 : 1; + __IO uint16_t TS29 : 1; + __IO uint16_t TS30 : 1; + __IO uint16_t TS31 : 1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss2_field +{ + __IO uint8_t TS16 : 1; + __IO uint8_t TS17 : 1; + __IO uint8_t TS18 : 1; + __IO uint8_t TS19 : 1; + __IO uint8_t TS20 : 1; + __IO uint8_t TS21 : 1; + __IO uint8_t TS22 : 1; + __IO uint8_t TS23 : 1; +} stc_adc_adss2_field_t; + +typedef struct stc_adc_adss3_field +{ + __IO uint8_t TS24 : 1; + __IO uint8_t TS25 : 1; + __IO uint8_t TS26 : 1; + __IO uint8_t TS27 : 1; + __IO uint8_t TS28 : 1; + __IO uint8_t TS29 : 1; + __IO uint8_t TS30 : 1; + __IO uint8_t TS31 : 1; +} stc_adc_adss3_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 : 1; + __IO uint16_t TS1 : 1; + __IO uint16_t TS2 : 1; + __IO uint16_t TS3 : 1; + __IO uint16_t TS4 : 1; + __IO uint16_t TS5 : 1; + __IO uint16_t TS6 : 1; + __IO uint16_t TS7 : 1; + __IO uint16_t TS8 : 1; + __IO uint16_t TS9 : 1; + __IO uint16_t TS10 : 1; + __IO uint16_t TS11 : 1; + __IO uint16_t TS12 : 1; + __IO uint16_t TS13 : 1; + __IO uint16_t TS14 : 1; + __IO uint16_t TS15 : 1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adss0_field +{ + __IO uint8_t TS0 : 1; + __IO uint8_t TS1 : 1; + __IO uint8_t TS2 : 1; + __IO uint8_t TS3 : 1; + __IO uint8_t TS4 : 1; + __IO uint8_t TS5 : 1; + __IO uint8_t TS6 : 1; + __IO uint8_t TS7 : 1; +} stc_adc_adss0_field_t; + +typedef struct stc_adc_adss1_field +{ + __IO uint8_t TS8 : 1; + __IO uint8_t TS9 : 1; + __IO uint8_t TS10 : 1; + __IO uint8_t TS11 : 1; + __IO uint8_t TS12 : 1; + __IO uint8_t TS13 : 1; + __IO uint8_t TS14 : 1; + __IO uint8_t TS15 : 1; +} stc_adc_adss1_field_t; + +typedef struct stc_adc_adst01_field +{ + __IO uint16_t ST10 : 1; + __IO uint16_t ST11 : 1; + __IO uint16_t ST12 : 1; + __IO uint16_t ST13 : 1; + __IO uint16_t ST14 : 1; + __IO uint16_t STX10 : 1; + __IO uint16_t STX11 : 1; + __IO uint16_t STX12 : 1; + __IO uint16_t ST00 : 1; + __IO uint16_t ST01 : 1; + __IO uint16_t ST02 : 1; + __IO uint16_t ST03 : 1; + __IO uint16_t ST04 : 1; + __IO uint16_t STX00 : 1; + __IO uint16_t STX01 : 1; + __IO uint16_t STX02 : 1; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adst1_field +{ + __IO uint8_t ST1 : 5; + __IO uint8_t STX1 : 3; +} stc_adc_adst1_field_t; + +typedef struct stc_adc_adst0_field +{ + __IO uint8_t ST0 : 5; + __IO uint8_t STX0 : 3; +} stc_adc_adst0_field_t; + +typedef struct stc_adc_adct_field +{ + __IO uint8_t CT0 : 1; + __IO uint8_t CT1 : 1; + __IO uint8_t CT2 : 1; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + __IO uint8_t PRTSL0 : 1; + __IO uint8_t PRTSL1 : 1; + __IO uint8_t PRTSL2 : 1; + __IO uint8_t PRTSL3 : 1; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + __IO uint8_t SCTSL0 : 1; + __IO uint8_t SCTSL1 : 1; + __IO uint8_t SCTSL2 : 1; + __IO uint8_t SCTSL3 : 1; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + __IO uint16_t ENBL : 1; + __IO uint16_t READY : 1; + __IO uint16_t RESERVED : 6; + __IO uint16_t ENBLTIME : 8; +} stc_adc_adcen_field_t; + +typedef struct stc_adc_wcmpdh_field +{ + uint16_t RESERVED : 6; + __IO uint16_t CMHD : 10; +} stc_adc_wcmpdh_field_t; + +typedef struct stc_adc_wcmpcr_field +{ + uint8_t RESERVED : 2; + __IO uint8_t RCOE : 1; + __IO uint8_t RCOIE : 1; + __IO uint8_t RCOIRRS : 1; + __IO uint8_t RCOCD : 3; +} stc_adc_wcmpcr_field_t; + +typedef struct stc_adc_wcmpdl_field +{ + uint16_t RESERVED : 6; + __IO uint16_t CMLD : 10; +} stc_adc_wcmpdl_field_t; + +typedef struct stc_adc_wcmpsr_field +{ + __IO uint8_t WCCH : 5; + __IO uint8_t WCMD : 1; + __IO uint8_t RESERVED : 2; +} stc_adc_wcmpsr_field_t; + +typedef struct stc_adc_wcmrcot_field +{ + __IO uint32_t RCOOF : 1; + uint32_t RESERVED : 31; +} stc_adc_wcmrcot_field_t; + +typedef struct stc_adc_wcmrcif_field +{ + __IO uint32_t RCINT : 1; + uint32_t RESERVED : 31; +} stc_adc_wcmrcif_field_t; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CRTRIM_MODULE register bit fields */ +typedef struct stc_crtrim_mcr_psr_field +{ + __IO uint8_t CSR : 3; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + __IO uint16_t TRD :10; +} stc_crtrim_mcr_ftrm_field_t; + +typedef struct stc_crtrim_mcr_ttrm_field +{ + __IO uint8_t TRT : 5; +} stc_crtrim_mcr_ttrm_field_t; + +typedef struct stc_crtrim_mcr_rlr_field +{ + __IO uint32_t TRMLCK :32; +} stc_crtrim_mcr_rlr_field_t; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* EXTI_MODULE register bit fields */ +typedef struct stc_exti_enir_field +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; + __IO uint32_t EN16 : 1; + __IO uint32_t EN17 : 1; + __IO uint32_t EN18 : 1; + __IO uint32_t EN19 : 1; + __IO uint32_t EN20 : 1; + __IO uint32_t EN21 : 1; + __IO uint32_t EN22 : 1; + __IO uint32_t EN23 : 1; + __IO uint32_t EN24 : 1; + __IO uint32_t EN25 : 1; + __IO uint32_t EN26 : 1; + __IO uint32_t EN27 : 1; + __IO uint32_t EN28 : 1; + __IO uint32_t EN29 : 1; + __IO uint32_t EN30 : 1; + __IO uint32_t EN31 : 1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint32_t ER0 : 1; + __IO uint32_t ER1 : 1; + __IO uint32_t ER2 : 1; + __IO uint32_t ER3 : 1; + __IO uint32_t ER4 : 1; + __IO uint32_t ER5 : 1; + __IO uint32_t ER6 : 1; + __IO uint32_t ER7 : 1; + __IO uint32_t ER8 : 1; + __IO uint32_t ER9 : 1; + __IO uint32_t ER10 : 1; + __IO uint32_t ER11 : 1; + __IO uint32_t ER12 : 1; + __IO uint32_t ER13 : 1; + __IO uint32_t ER14 : 1; + __IO uint32_t ER15 : 1; + __IO uint32_t ER16 : 1; + __IO uint32_t ER17 : 1; + __IO uint32_t ER18 : 1; + __IO uint32_t ER19 : 1; + __IO uint32_t ER20 : 1; + __IO uint32_t ER21 : 1; + __IO uint32_t ER22 : 1; + __IO uint32_t ER23 : 1; + __IO uint32_t ER24 : 1; + __IO uint32_t ER25 : 1; + __IO uint32_t ER26 : 1; + __IO uint32_t ER27 : 1; + __IO uint32_t ER28 : 1; + __IO uint32_t ER29 : 1; + __IO uint32_t ER30 : 1; + __IO uint32_t ER31 : 1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint32_t ECL0 : 1; + __IO uint32_t ECL1 : 1; + __IO uint32_t ECL2 : 1; + __IO uint32_t ECL3 : 1; + __IO uint32_t ECL4 : 1; + __IO uint32_t ECL5 : 1; + __IO uint32_t ECL6 : 1; + __IO uint32_t ECL7 : 1; + __IO uint32_t ECL8 : 1; + __IO uint32_t ECL9 : 1; + __IO uint32_t ECL10 : 1; + __IO uint32_t ECL11 : 1; + __IO uint32_t ECL12 : 1; + __IO uint32_t ECL13 : 1; + __IO uint32_t ECL14 : 1; + __IO uint32_t ECL15 : 1; + __IO uint32_t ECL16 : 1; + __IO uint32_t ECL17 : 1; + __IO uint32_t ECL18 : 1; + __IO uint32_t ECL19 : 1; + __IO uint32_t ECL20 : 1; + __IO uint32_t ECL21 : 1; + __IO uint32_t ECL22 : 1; + __IO uint32_t ECL23 : 1; + __IO uint32_t ECL24 : 1; + __IO uint32_t ECL25 : 1; + __IO uint32_t ECL26 : 1; + __IO uint32_t ECL27 : 1; + __IO uint32_t ECL28 : 1; + __IO uint32_t ECL29 : 1; + __IO uint32_t ECL30 : 1; + __IO uint32_t ECL31 : 1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 : 1; + __IO uint32_t LB0 : 1; + __IO uint32_t LA1 : 1; + __IO uint32_t LB1 : 1; + __IO uint32_t LA2 : 1; + __IO uint32_t LB2 : 1; + __IO uint32_t LA3 : 1; + __IO uint32_t LB3 : 1; + __IO uint32_t LA4 : 1; + __IO uint32_t LB4 : 1; + __IO uint32_t LA5 : 1; + __IO uint32_t LB5 : 1; + __IO uint32_t LA6 : 1; + __IO uint32_t LB6 : 1; + __IO uint32_t LA7 : 1; + __IO uint32_t LB7 : 1; + __IO uint32_t LA8 : 1; + __IO uint32_t LB8 : 1; + __IO uint32_t LA9 : 1; + __IO uint32_t LB9 : 1; + __IO uint32_t LA10 : 1; + __IO uint32_t LB10 : 1; + __IO uint32_t LA11 : 1; + __IO uint32_t LB11 : 1; + __IO uint32_t LA12 : 1; + __IO uint32_t LB12 : 1; + __IO uint32_t LA13 : 1; + __IO uint32_t LB13 : 1; + __IO uint32_t LA14 : 1; + __IO uint32_t LB14 : 1; + __IO uint32_t LA15 : 1; + __IO uint32_t LB15 : 1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_elvr1_field +{ + __IO uint32_t LA16 : 1; + __IO uint32_t LB16 : 1; + __IO uint32_t LA17 : 1; + __IO uint32_t LB17 : 1; + __IO uint32_t LA18 : 1; + __IO uint32_t LB18 : 1; + __IO uint32_t LA19 : 1; + __IO uint32_t LB19 : 1; + __IO uint32_t LA20 : 1; + __IO uint32_t LB20 : 1; + __IO uint32_t LA21 : 1; + __IO uint32_t LB21 : 1; + __IO uint32_t LA22 : 1; + __IO uint32_t LB22 : 1; + __IO uint32_t LA23 : 1; + __IO uint32_t LB23 : 1; + __IO uint32_t LA24 : 1; + __IO uint32_t LB24 : 1; + __IO uint32_t LA25 : 1; + __IO uint32_t LB25 : 1; + __IO uint32_t LA26 : 1; + __IO uint32_t LB26 : 1; + __IO uint32_t LA27 : 1; + __IO uint32_t LB27 : 1; + __IO uint32_t LA28 : 1; + __IO uint32_t LB28 : 1; + __IO uint32_t LA29 : 1; + __IO uint32_t LB29 : 1; + __IO uint32_t LA30 : 1; + __IO uint32_t LB30 : 1; + __IO uint32_t LA31 : 1; + __IO uint32_t LB31 : 1; +} stc_exti_elvr1_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint8_t NR : 1; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint8_t NCL : 1; +} stc_exti_nmicl_field_t; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* INTREQ_MODULE register bit fields */ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t DRQSEL0 : 1; + __IO uint32_t DRQSEL1 : 1; + __IO uint32_t DRQSEL2 : 1; + __IO uint32_t DRQSEL3 : 1; + __IO uint32_t DRQSEL4 : 1; + __IO uint32_t DRQSEL5 : 1; + __IO uint32_t DRQSEL6 : 1; + __IO uint32_t DRQSEL7 : 1; + __IO uint32_t DRQSEL8 : 1; + __IO uint32_t DRQSEL9 : 1; + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; + __IO uint32_t DRQSEL15 : 1; + __IO uint32_t DRQSEL16 : 1; + __IO uint32_t DRQSEL17 : 1; + __IO uint32_t DRQSEL18 : 1; + __IO uint32_t DRQSEL19 : 1; + __IO uint32_t DRQSEL20 : 1; + __IO uint32_t DRQSEL21 : 1; + __IO uint32_t DRQSEL22 : 1; + __IO uint32_t DRQSEL23 : 1; + __IO uint32_t DRQSEL24 : 1; + __IO uint32_t DRQSEL25 : 1; + __IO uint32_t DRQSEL26 : 1; + __IO uint32_t DRQSEL27 : 1; + __IO uint32_t DRQSEL28 : 1; + __IO uint32_t DRQSEL29 : 1; + __IO uint32_t DRQSEL30 : 1; + __IO uint32_t DRQSEL31 : 1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_oddpks_field +{ + __IO uint8_t ODDPKS0 : 1; + __IO uint8_t ODDPKS1 : 1; + __IO uint8_t ODDPKS2 : 1; + __IO uint8_t ODDPKS3 : 1; + __IO uint8_t ODDPKS4 : 1; +} stc_intreq_oddpks_field_t; + +typedef struct stc_intreq_irq003sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq003sel_field_t; + +typedef struct stc_intreq_irq004sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq004sel_field_t; + +typedef struct stc_intreq_irq005sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq005sel_field_t; + +typedef struct stc_intreq_irq006sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq006sel_field_t; + +typedef struct stc_intreq_irq007sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq007sel_field_t; + +typedef struct stc_intreq_irq008sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq008sel_field_t; + +typedef struct stc_intreq_irq009sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq009sel_field_t; + +typedef struct stc_intreq_irq010sel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t SELBIT : 8; +} stc_intreq_irq010sel_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI : 1; + __IO uint32_t HWINT : 1; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq000mon_field +{ + __IO uint32_t FCSINT : 1; +} stc_intreq_irq000mon_field_t; + +typedef struct stc_intreq_irq001mon_field +{ + __IO uint32_t SWWDTINT : 1; +} stc_intreq_irq001mon_field_t; + +typedef struct stc_intreq_irq002mon_field +{ + __IO uint32_t LVDINT : 1; +} stc_intreq_irq002mon_field_t; + +typedef struct stc_intreq_irq003mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq003mon_field_t; + +typedef struct stc_intreq_irq004mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq004mon_field_t; + +typedef struct stc_intreq_irq005mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq005mon_field_t; + +typedef struct stc_intreq_irq006mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq006mon_field_t; + +typedef struct stc_intreq_irq007mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq007mon_field_t; + +typedef struct stc_intreq_irq008mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq008mon_field_t; + +typedef struct stc_intreq_irq009mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq009mon_field_t; + +typedef struct stc_intreq_irq010mon_field +{ + __IO uint32_t IRQBIT0 : 1; + __IO uint32_t IRQBIT1 : 1; + __IO uint32_t IRQBIT2 : 1; + __IO uint32_t IRQBIT3 : 1; + __IO uint32_t IRQBIT4 : 1; + __IO uint32_t IRQBIT5 : 1; + __IO uint32_t IRQBIT6 : 1; + __IO uint32_t IRQBIT7 : 1; +} stc_intreq_irq010mon_field_t; + +typedef struct stc_intreq_irq011mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq011mon_field_t; + +typedef struct stc_intreq_irq012mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq012mon_field_t; + +typedef struct stc_intreq_irq013mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq013mon_field_t; + +typedef struct stc_intreq_irq014mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq014mon_field_t; + +typedef struct stc_intreq_irq015mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq015mon_field_t; + +typedef struct stc_intreq_irq016mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq016mon_field_t; + +typedef struct stc_intreq_irq017mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq017mon_field_t; + +typedef struct stc_intreq_irq018mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq018mon_field_t; + +typedef struct stc_intreq_irq019mon_field +{ + __IO uint32_t QUDINT0 : 1; + __IO uint32_t QUDINT1 : 1; + __IO uint32_t QUDINT2 : 1; + __IO uint32_t QUDINT3 : 1; + __IO uint32_t QUDINT4 : 1; + __IO uint32_t QUDINT5 : 1; +} stc_intreq_irq019mon_field_t; + +typedef struct stc_intreq_irq020mon_field +{ + __IO uint32_t QUDINT0 : 1; + __IO uint32_t QUDINT1 : 1; + __IO uint32_t QUDINT2 : 1; + __IO uint32_t QUDINT3 : 1; + __IO uint32_t QUDINT4 : 1; + __IO uint32_t QUDINT5 : 1; +} stc_intreq_irq020mon_field_t; + +typedef struct stc_intreq_irq021mon_field +{ + __IO uint32_t WAVEINT0 : 1; + __IO uint32_t WAVEINT1 : 1; + __IO uint32_t WAVEINT2 : 1; + __IO uint32_t WAVEINT3 : 1; +} stc_intreq_irq021mon_field_t; + +typedef struct stc_intreq_irq022mon_field +{ + __IO uint32_t WAVEINT0 : 1; + __IO uint32_t WAVEINT1 : 1; + __IO uint32_t WAVEINT2 : 1; + __IO uint32_t WAVEINT3 : 1; +} stc_intreq_irq022mon_field_t; + +typedef struct stc_intreq_irq023mon_field +{ + __IO uint32_t WAVEINT0 : 1; + __IO uint32_t WAVEINT1 : 1; + __IO uint32_t WAVEINT2 : 1; + __IO uint32_t WAVEINT3 : 1; +} stc_intreq_irq023mon_field_t; + +typedef struct stc_intreq_irq024mon_field +{ + __IO uint32_t FRT_PEAK_INT0: 1; + __IO uint32_t FRT_PEAK_INT1: 1; + __IO uint32_t FRT_PEAK_INT2: 1; +} stc_intreq_irq024mon_field_t; + +typedef struct stc_intreq_irq025mon_field +{ + __IO uint32_t FRT_ZERO_INT0: 1; + __IO uint32_t FRT_ZERO_INT1: 1; + __IO uint32_t FRT_ZERO_INT2: 1; +} stc_intreq_irq025mon_field_t; + +typedef struct stc_intreq_irq026mon_field +{ + __IO uint32_t ICUINT0 : 1; + __IO uint32_t ICUINT1 : 1; + __IO uint32_t ICUINT2 : 1; + __IO uint32_t ICUINT3 : 1; +} stc_intreq_irq026mon_field_t; + +typedef struct stc_intreq_irq027mon_field +{ + __IO uint32_t OCUINT0 : 1; + __IO uint32_t OCUINT1 : 1; + __IO uint32_t OCUINT2 : 1; + __IO uint32_t OCUINT3 : 1; + __IO uint32_t OCUINT4 : 1; + __IO uint32_t OCUINT5 : 1; +} stc_intreq_irq027mon_field_t; + +typedef struct stc_intreq_irq028mon_field +{ + __IO uint32_t FRT_PEAK_INT0: 1; + __IO uint32_t FRT_PEAK_INT1: 1; + __IO uint32_t FRT_PEAK_INT2: 1; +} stc_intreq_irq028mon_field_t; + +typedef struct stc_intreq_irq029mon_field +{ + __IO uint32_t FRT_ZERO_INT0: 1; + __IO uint32_t FRT_ZERO_INT1: 1; + __IO uint32_t FRT_ZERO_INT2: 1; +} stc_intreq_irq029mon_field_t; + +typedef struct stc_intreq_irq030mon_field +{ + __IO uint32_t ICUINT0 : 1; + __IO uint32_t ICUINT1 : 1; + __IO uint32_t ICUINT2 : 1; + __IO uint32_t ICUINT3 : 1; +} stc_intreq_irq030mon_field_t; + +typedef struct stc_intreq_irq031mon_field +{ + __IO uint32_t OCUINT0 : 1; + __IO uint32_t OCUINT1 : 1; + __IO uint32_t OCUINT2 : 1; + __IO uint32_t OCUINT3 : 1; + __IO uint32_t OCUINT4 : 1; + __IO uint32_t OCUINT5 : 1; +} stc_intreq_irq031mon_field_t; + +typedef struct stc_intreq_irq032mon_field +{ + __IO uint32_t FRT_PEAK_INT0: 1; + __IO uint32_t FRT_PEAK_INT1: 1; + __IO uint32_t FRT_PEAK_INT2: 1; +} stc_intreq_irq032mon_field_t; + +typedef struct stc_intreq_irq033mon_field +{ + __IO uint32_t FRT_ZERO_INT0: 1; + __IO uint32_t FRT_ZERO_INT1: 1; + __IO uint32_t FRT_ZERO_INT2: 1; +} stc_intreq_irq033mon_field_t; + +typedef struct stc_intreq_irq034mon_field +{ + __IO uint32_t ICUINT0 : 1; + __IO uint32_t ICUINT1 : 1; + __IO uint32_t ICUINT2 : 1; + __IO uint32_t ICUINT3 : 1; +} stc_intreq_irq034mon_field_t; + +typedef struct stc_intreq_irq035mon_field +{ + __IO uint32_t OCUINT0 : 1; + __IO uint32_t OCUINT1 : 1; + __IO uint32_t OCUINT2 : 1; + __IO uint32_t OCUINT3 : 1; + __IO uint32_t OCUINT4 : 1; + __IO uint32_t OCUINT5 : 1; +} stc_intreq_irq035mon_field_t; + +typedef struct stc_intreq_irq036mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; +} stc_intreq_irq036mon_field_t; + +typedef struct stc_intreq_irq037mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; +} stc_intreq_irq037mon_field_t; + +typedef struct stc_intreq_irq038mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; +} stc_intreq_irq038mon_field_t; + +typedef struct stc_intreq_irq039mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq039mon_field_t; + +typedef struct stc_intreq_irq040mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq040mon_field_t; + +typedef struct stc_intreq_irq041mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq041mon_field_t; + +typedef struct stc_intreq_irq042mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq042mon_field_t; + +typedef struct stc_intreq_irq043mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq043mon_field_t; + +typedef struct stc_intreq_irq044mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq044mon_field_t; + +typedef struct stc_intreq_irq045mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq045mon_field_t; + +typedef struct stc_intreq_irq046mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq046mon_field_t; + +typedef struct stc_intreq_irq047mon_field +{ + __IO uint32_t TIMINT1 : 1; + __IO uint32_t TIMINT2 : 1; +} stc_intreq_irq047mon_field_t; + +typedef struct stc_intreq_irq048mon_field +{ + __IO uint32_t WCINT : 1; +} stc_intreq_irq048mon_field_t; + +typedef struct stc_intreq_irq049mon_field +{ + __IO uint32_t BMEMCS : 1; +} stc_intreq_irq049mon_field_t; + +typedef struct stc_intreq_irq050mon_field +{ + __IO uint32_t RTCINT : 1; +} stc_intreq_irq050mon_field_t; + +typedef struct stc_intreq_irq051mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq051mon_field_t; + +typedef struct stc_intreq_irq052mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq052mon_field_t; + +typedef struct stc_intreq_irq053mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq053mon_field_t; + +typedef struct stc_intreq_irq054mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq054mon_field_t; + +typedef struct stc_intreq_irq055mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq055mon_field_t; + +typedef struct stc_intreq_irq056mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq056mon_field_t; + +typedef struct stc_intreq_irq057mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq057mon_field_t; + +typedef struct stc_intreq_irq058mon_field +{ + __IO uint32_t EXTINT : 1; +} stc_intreq_irq058mon_field_t; + +typedef struct stc_intreq_irq059mon_field +{ + __IO uint32_t MOSCINT : 1; + __IO uint32_t SOSCINT : 1; + __IO uint32_t MPLLINT : 1; + __IO uint32_t UPLLINT : 1; +} stc_intreq_irq059mon_field_t; + +typedef struct stc_intreq_irq060mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq060mon_field_t; + +typedef struct stc_intreq_irq061mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq061mon_field_t; + +typedef struct stc_intreq_irq062mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq062mon_field_t; + +typedef struct stc_intreq_irq063mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq063mon_field_t; + +typedef struct stc_intreq_irq064mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq064mon_field_t; + +typedef struct stc_intreq_irq065mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq065mon_field_t; + +typedef struct stc_intreq_irq066mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq066mon_field_t; + +typedef struct stc_intreq_irq067mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq067mon_field_t; + +typedef struct stc_intreq_irq068mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq068mon_field_t; + +typedef struct stc_intreq_irq069mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq069mon_field_t; + +typedef struct stc_intreq_irq070mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq070mon_field_t; + +typedef struct stc_intreq_irq071mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq071mon_field_t; + +typedef struct stc_intreq_irq072mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq072mon_field_t; + +typedef struct stc_intreq_irq073mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq073mon_field_t; + +typedef struct stc_intreq_irq074mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq074mon_field_t; + +typedef struct stc_intreq_irq075mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq075mon_field_t; + +typedef struct stc_intreq_irq076mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; + __IO uint32_t ADCINT4 : 1; +} stc_intreq_irq076mon_field_t; + +typedef struct stc_intreq_irq077mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; + __IO uint32_t ADCINT4 : 1; +} stc_intreq_irq077mon_field_t; + +typedef struct stc_intreq_irq078mon_field +{ + __IO uint32_t USB_DRQ_INT0: 1; + __IO uint32_t USB_DRQ_INT1: 1; + __IO uint32_t USB_DRQ_INT2: 1; + __IO uint32_t USB_DRQ_INT3: 1; + __IO uint32_t USB_DRQ_INT4: 1; +} stc_intreq_irq078mon_field_t; + +typedef struct stc_intreq_irq079mon_field +{ + __IO uint32_t USB_INT0 : 1; + __IO uint32_t USB_INT1 : 1; + __IO uint32_t USB_INT2 : 1; + __IO uint32_t USB_INT3 : 1; + __IO uint32_t USB_INT4 : 1; + __IO uint32_t USB_INT5 : 1; +} stc_intreq_irq079mon_field_t; + +typedef struct stc_intreq_irq080mon_field +{ + __IO uint32_t CANINT : 1; +} stc_intreq_irq080mon_field_t; + +typedef struct stc_intreq_irq081mon_field +{ + __IO uint32_t CANINT : 1; +} stc_intreq_irq081mon_field_t; + +typedef struct stc_intreq_irq082mon_field +{ + __IO uint32_t MACSBD : 1; + __IO uint32_t MACPMT : 1; + __IO uint32_t MACLPI : 1; +} stc_intreq_irq082mon_field_t; + +typedef struct stc_intreq_irq083mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq083mon_field_t; + +typedef struct stc_intreq_irq084mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq084mon_field_t; + +typedef struct stc_intreq_irq085mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq085mon_field_t; + +typedef struct stc_intreq_irq086mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq086mon_field_t; + +typedef struct stc_intreq_irq087mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq087mon_field_t; + +typedef struct stc_intreq_irq088mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq088mon_field_t; + +typedef struct stc_intreq_irq089mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq089mon_field_t; + +typedef struct stc_intreq_irq090mon_field +{ + __IO uint32_t DMACINT : 1; +} stc_intreq_irq090mon_field_t; + +typedef struct stc_intreq_irq091mon_field +{ + __IO uint32_t DSTCINT0 : 1; + __IO uint32_t DSTCINT1 : 1; +} stc_intreq_irq091mon_field_t; + +typedef struct stc_intreq_irq092mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; +} stc_intreq_irq092mon_field_t; + +typedef struct stc_intreq_irq093mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; +} stc_intreq_irq093mon_field_t; + +typedef struct stc_intreq_irq094mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; +} stc_intreq_irq094mon_field_t; + +typedef struct stc_intreq_irq095mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; +} stc_intreq_irq095mon_field_t; + +typedef struct stc_intreq_irq096mon_field +{ + __IO uint32_t QUDINT0 : 1; + __IO uint32_t QUDINT1 : 1; + __IO uint32_t QUDINT2 : 1; + __IO uint32_t QUDINT3 : 1; + __IO uint32_t QUDINT4 : 1; + __IO uint32_t QUDINT5 : 1; +} stc_intreq_irq096mon_field_t; + +typedef struct stc_intreq_irq097mon_field +{ + __IO uint32_t QUDINT0 : 1; + __IO uint32_t QUDINT1 : 1; + __IO uint32_t QUDINT2 : 1; + __IO uint32_t QUDINT3 : 1; + __IO uint32_t QUDINT4 : 1; + __IO uint32_t QUDINT5 : 1; +} stc_intreq_irq097mon_field_t; + +typedef struct stc_intreq_irq098mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq098mon_field_t; + +typedef struct stc_intreq_irq099mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq099mon_field_t; + +typedef struct stc_intreq_irq100mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq100mon_field_t; + +typedef struct stc_intreq_irq101mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; +} stc_intreq_irq101mon_field_t; + +typedef struct stc_intreq_irq102mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; +} stc_intreq_irq102mon_field_t; + +typedef struct stc_intreq_irq103mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq103mon_field_t; + +typedef struct stc_intreq_irq104mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq104mon_field_t; + +typedef struct stc_intreq_irq105mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq105mon_field_t; + +typedef struct stc_intreq_irq106mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq106mon_field_t; + +typedef struct stc_intreq_irq107mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq107mon_field_t; + +typedef struct stc_intreq_irq108mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq108mon_field_t; + +typedef struct stc_intreq_irq109mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq109mon_field_t; + +typedef struct stc_intreq_irq110mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq110mon_field_t; + +typedef struct stc_intreq_irq111mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; + __IO uint32_t ADCINT4 : 1; +} stc_intreq_irq111mon_field_t; + +typedef struct stc_intreq_irq113mon_field +{ + __IO uint32_t USB_DRQ_INT0: 1; + __IO uint32_t USB_DRQ_INT1: 1; + __IO uint32_t USB_DRQ_INT2: 1; + __IO uint32_t USB_DRQ_INT3: 1; + __IO uint32_t USB_DRQ_INT4: 1; +} stc_intreq_irq113mon_field_t; + +typedef struct stc_intreq_irq114mon_field +{ + __IO uint32_t USB_INT0 : 1; + __IO uint32_t USB_INT1 : 1; + __IO uint32_t USB_INT2 : 1; + __IO uint32_t USB_INT3 : 1; + __IO uint32_t USB_INT4 : 1; + __IO uint32_t USB_INT5 : 1; +} stc_intreq_irq114mon_field_t; + +typedef struct stc_intreq_irq118mon_field +{ + __IO uint32_t SDINT0 : 1; + __IO uint32_t SDINT1 : 1; +} stc_intreq_irq118mon_field_t; + +typedef struct stc_intreq_irq119mon_field +{ + __IO uint32_t FLINT : 1; +} stc_intreq_irq119mon_field_t; + +typedef struct stc_intreq_irq120mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq120mon_field_t; + +typedef struct stc_intreq_irq121mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq121mon_field_t; + +typedef struct stc_intreq_irq122mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq122mon_field_t; + +typedef struct stc_intreq_irq123mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq123mon_field_t; + +typedef struct stc_intreq_irq124mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq124mon_field_t; + +typedef struct stc_intreq_irq125mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq125mon_field_t; + +typedef struct stc_intreq_irq126mon_field +{ + __IO uint32_t MFSRINT : 1; +} stc_intreq_irq126mon_field_t; + +typedef struct stc_intreq_irq127mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq127mon_field_t; + +/****************************************************************************** + * IRQSEL_MODULE +******************************************************************************/ +typedef struct stc_irqsel_field +{ + __IO uint32_t SELIRQ : 8; + uint32_t RESERVED0 : 8; + __IO uint32_t SELBIT : 8; + uint32_t RESERVED1 : 8; +} stc_irqsel_field_t; + +/****************************************************************************** + * DSTC_MODULE + ******************************************************************************/ +/* DSTC_MODULE register bit fields */ +typedef struct stc_dstc_hwdesp_field +{ + __IO uint32_t CHANNEL : 8; + uint32_t RESERVED1 : 8; + __IO uint32_t HWDESP : 14; + uint32_t RESERVED2 : 2; +} stc_dstc_hwdesp_field_t; + +typedef struct stc_dstc_cfg_field +{ + __IO uint8_t SWINTE : 1; + __IO uint8_t ERINTE : 1; + __IO uint8_t RBDIS : 1; + __IO uint8_t ESTE : 1; + __IO uint8_t SWPR : 3; + uint8_t RESERVED : 1; +} stc_dstc_cfg_field_t; + +typedef struct stc_dstc_swtr_field +{ + __IO uint16_t SWDESP : 14; + __IO uint16_t SWREQ : 1; + __IO uint16_t SWST : 1; +} stc_dstc_swtr_field_t; + +typedef struct stc_dstc_moners_field +{ + __IO uint32_t EST : 3; + __IO uint32_t DER : 1; + __IO uint32_t ESTOP : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t EHS : 1; + __IO uint32_t RESERVED2 : 1; + __IO uint32_t ECH : 8; + __IO uint32_t EDESP : 14; + uint32_t RESERVED3 : 2; +} stc_dstc_moners_field_t; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* GPIO_MODULE register bit fields */ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_pfr5_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_pfr8_field_t; + +typedef struct stc_gpio_pfre_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_pfre_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_pcr5_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_pcr8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_pcr8_field_t; + +typedef struct stc_gpio_pcre_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_pcre_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; + __IO uint32_t P0F : 1; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_ddr5_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_ddre_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_ddre_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; + __IO uint32_t P0F : 1; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_pdir5_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdire_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_pdire_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; + __IO uint32_t P0F : 1; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_pdor5_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_pdore_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_pdore_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN00 : 1; + __IO uint32_t AN01 : 1; + __IO uint32_t AN02 : 1; + __IO uint32_t AN03 : 1; + __IO uint32_t AN04 : 1; + __IO uint32_t AN05 : 1; + __IO uint32_t AN06 : 1; + __IO uint32_t AN07 : 1; + __IO uint32_t AN08 : 1; + __IO uint32_t AN09 : 1; + __IO uint32_t AN10 : 1; + __IO uint32_t AN11 : 1; + __IO uint32_t AN12 : 1; + __IO uint32_t AN13 : 1; + __IO uint32_t AN14 : 1; + __IO uint32_t AN15 : 1; + __IO uint32_t AN16 : 1; + __IO uint32_t AN17 : 1; + __IO uint32_t AN18 : 1; + __IO uint32_t AN19 : 1; + __IO uint32_t AN20 : 1; + __IO uint32_t AN21 : 1; + __IO uint32_t AN22 : 1; + __IO uint32_t AN23 : 1; + __IO uint32_t AN24 : 1; + __IO uint32_t AN25 : 1; + __IO uint32_t AN26 : 1; + __IO uint32_t AN27 : 1; + __IO uint32_t AN28 : 1; + __IO uint32_t AN29 : 1; + __IO uint32_t AN30 : 1; + __IO uint32_t AN31 : 1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + uint32_t RESERVED0 : 2; + __IO uint32_t MAINXC : 2; + __IO uint32_t USB0C : 1; + __IO uint32_t USB1C : 1; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + __IO uint32_t NMIS : 1; + __IO uint32_t CROUTE : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t RTCCOE : 2; + __IO uint32_t SUBOUTE : 2; + uint32_t RESERVED8 : 1; + __IO uint32_t USBP0E : 1; + uint32_t RESERVED10 : 3; + __IO uint32_t USBP1E : 1; + uint32_t RESERVED14 : 2; + __IO uint32_t JTAGEN0B : 1; + __IO uint32_t JTAGEN1S : 1; + uint32_t RESERVED18 : 6; + __IO uint32_t TRC0E : 1; + __IO uint32_t TRC1E : 1; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + __IO uint32_t RTO00E : 2; + __IO uint32_t RTO01E : 2; + __IO uint32_t RTO02E : 2; + __IO uint32_t RTO03E : 2; + __IO uint32_t RTO04E : 2; + __IO uint32_t RTO05E : 2; + __IO uint32_t DTTI0C : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t DTTI0S : 2; + __IO uint32_t FRCK0S : 2; + __IO uint32_t IC00S : 3; + __IO uint32_t IC01S : 3; + __IO uint32_t IC02S : 3; + __IO uint32_t IC03S : 3; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + __IO uint32_t RTO10E : 2; + __IO uint32_t RTO11E : 2; + __IO uint32_t RTO12E : 2; + __IO uint32_t RTO13E : 2; + __IO uint32_t RTO14E : 2; + __IO uint32_t RTO15E : 2; + __IO uint32_t DTTI1C : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t DTTI1S : 2; + __IO uint32_t FRCK1S : 2; + __IO uint32_t IC10S : 3; + __IO uint32_t IC11S : 3; + __IO uint32_t IC12S : 3; + __IO uint32_t IC13S : 3; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr03_field +{ + __IO uint32_t RTO20E : 2; + __IO uint32_t RTO21E : 2; + __IO uint32_t RTO22E : 2; + __IO uint32_t RTO23E : 2; + __IO uint32_t RTO24E : 2; + __IO uint32_t RTO25E : 2; + __IO uint32_t DTTI2C : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t DTTI2S : 2; + __IO uint32_t FRCK2S : 2; + __IO uint32_t IC20S : 3; + __IO uint32_t IC21S : 3; + __IO uint32_t IC22S : 3; + __IO uint32_t IC23S : 3; +} stc_gpio_epfr03_field_t; + +typedef struct stc_gpio_epfr04_field +{ + uint32_t RESERVED0 : 2; + __IO uint32_t TIOA0E : 2; + __IO uint32_t TIOB0S : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t TIOA1S : 2; + __IO uint32_t TIOA1E : 2; + __IO uint32_t TIOB1S : 2; + uint32_t RESERVED14 : 4; + __IO uint32_t TIOA2E : 2; + __IO uint32_t TIOB2S : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t TIOA3S : 2; + __IO uint32_t TIOA3E : 2; + __IO uint32_t TIOB3S : 2; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + uint32_t RESERVED0 : 2; + __IO uint32_t TIOA4E : 2; + __IO uint32_t TIOB4S : 2; + uint32_t RESERVED6 : 2; + __IO uint32_t TIOA5S : 2; + __IO uint32_t TIOA5E : 2; + __IO uint32_t TIOB5S : 2; + uint32_t RESERVED14 : 4; + __IO uint32_t TIOA6E : 2; + __IO uint32_t TIOB6S : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t TIOA7S : 2; + __IO uint32_t TIOA7E : 2; + __IO uint32_t TIOB7S : 2; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + __IO uint32_t EINT00S : 2; + __IO uint32_t EINT01S : 2; + __IO uint32_t EINT02S : 2; + __IO uint32_t EINT03S : 2; + __IO uint32_t EINT04S : 2; + __IO uint32_t EINT05S : 2; + __IO uint32_t EINT06S : 2; + __IO uint32_t EINT07S : 2; + __IO uint32_t EINT08S : 2; + __IO uint32_t EINT09S : 2; + __IO uint32_t EINT10S : 2; + __IO uint32_t EINT11S : 2; + __IO uint32_t EINT12S : 2; + __IO uint32_t EINT13S : 2; + __IO uint32_t EINT14S : 2; + __IO uint32_t EINT15S : 2; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + uint32_t RESERVED0 : 4; + __IO uint32_t SIN0S : 2; + __IO uint32_t SOT0B : 2; + __IO uint32_t SCK0B : 2; + __IO uint32_t SIN1S : 2; + __IO uint32_t SOT1B : 2; + __IO uint32_t SCK1B : 2; + __IO uint32_t SIN2S : 2; + __IO uint32_t SOT2B : 2; + __IO uint32_t SCK2B : 2; + __IO uint32_t SIN3S : 2; + __IO uint32_t SOT3B : 2; + __IO uint32_t SCK3B : 2; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + __IO uint32_t RTS4E : 2; + __IO uint32_t CTS4S : 2; + __IO uint32_t SIN4S : 2; + __IO uint32_t SOT4B : 2; + __IO uint32_t SCK4B : 2; + __IO uint32_t SIN5S : 2; + __IO uint32_t SOT5B : 2; + __IO uint32_t SCK5B : 2; + __IO uint32_t SIN6S : 2; + __IO uint32_t SOT6B : 2; + __IO uint32_t SCK6B : 2; + __IO uint32_t SIN7S : 2; + __IO uint32_t SOT7B : 2; + __IO uint32_t SCK7B : 2; + __IO uint32_t RTS5E : 2; + __IO uint32_t CTS5S : 2; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + __IO uint32_t QAIN0S : 2; + __IO uint32_t QBIN0S : 2; + __IO uint32_t QZIN0S : 2; + __IO uint32_t QAIN1S : 2; + __IO uint32_t QBIN1S : 2; + __IO uint32_t QZIN1S : 2; + __IO uint32_t ADTRG0S : 4; + __IO uint32_t ADTRG1S : 4; + __IO uint32_t ADTRG2S : 4; + __IO uint32_t CRX0S : 2; + __IO uint32_t CTX0E : 2; + __IO uint32_t CRX1S : 2; + __IO uint32_t CTX1E : 2; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB : 1; + __IO uint32_t UEDTHB : 1; + __IO uint32_t UECLKE : 1; + __IO uint32_t UEWEXE : 1; + __IO uint32_t UEDQME : 1; + __IO uint32_t UEOEXE : 1; + __IO uint32_t UEFLSE : 1; + __IO uint32_t UECS1E : 1; + __IO uint32_t UECS2E : 1; + __IO uint32_t UECS3E : 1; + __IO uint32_t UECS4E : 1; + __IO uint32_t UECS5E : 1; + __IO uint32_t UECS6E : 1; + __IO uint32_t UECS7E : 1; + __IO uint32_t UEAOOE : 1; + __IO uint32_t UEA08E : 1; + __IO uint32_t UEA09E : 1; + __IO uint32_t UEA10E : 1; + __IO uint32_t UEA11E : 1; + __IO uint32_t UEA12E : 1; + __IO uint32_t UEA13E : 1; + __IO uint32_t UEA14E : 1; + __IO uint32_t UEA15E : 1; + __IO uint32_t UEA16E : 1; + __IO uint32_t UEA17E : 1; + __IO uint32_t UEA18E : 1; + __IO uint32_t UEA19E : 1; + __IO uint32_t UEA20E : 1; + __IO uint32_t UEA21E : 1; + __IO uint32_t UEA22E : 1; + __IO uint32_t UEA23E : 1; + __IO uint32_t UEA24E : 1; +} stc_gpio_epfr10_field_t; + +typedef struct stc_gpio_epfr11_field +{ + __IO uint32_t UEALEE : 1; + __IO uint32_t UECS0E : 1; + __IO uint32_t UEA01E : 1; + __IO uint32_t UEA02E : 1; + __IO uint32_t UEA03E : 1; + __IO uint32_t UEA04E : 1; + __IO uint32_t UEA05E : 1; + __IO uint32_t UEA06E : 1; + __IO uint32_t UEA07E : 1; + __IO uint32_t UED00B : 1; + __IO uint32_t UED01B : 1; + __IO uint32_t UED02B : 1; + __IO uint32_t UED03B : 1; + __IO uint32_t UED04B : 1; + __IO uint32_t UED05B : 1; + __IO uint32_t UED06B : 1; + __IO uint32_t UED07B : 1; + __IO uint32_t UED08B : 1; + __IO uint32_t UED09B : 1; + __IO uint32_t UED10B : 1; + __IO uint32_t UED11B : 1; + __IO uint32_t UED12B : 1; + __IO uint32_t UED13B : 1; + __IO uint32_t UED14B : 1; + __IO uint32_t UED15B : 1; + __IO uint32_t UERLC : 1; +} stc_gpio_epfr11_field_t; + +typedef struct stc_gpio_epfr12_field +{ + uint32_t RESERVED0 : 2; + __IO uint32_t TIOA8E : 2; + __IO uint32_t TIOB8S : 2; + uint32_t RESERVED6 : 2; + __IO uint32_t TIOA9S : 2; + __IO uint32_t TIOA9E : 2; + __IO uint32_t TIOB9S : 2; + uint32_t RESERVED14 : 4; + __IO uint32_t TIOA10E : 2; + __IO uint32_t TIOB10S : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t TIOA11S : 2; + __IO uint32_t TIOA11E : 2; + __IO uint32_t TIOB11S : 2; +} stc_gpio_epfr12_field_t; + +typedef struct stc_gpio_epfr13_field +{ + uint32_t RESERVED0 : 2; + __IO uint32_t TIOA12E : 2; + __IO uint32_t TIOB12S : 2; + uint32_t RESERVED6 : 2; + __IO uint32_t TIOA13S : 2; + __IO uint32_t TIOA13E : 2; + __IO uint32_t TIOB13S : 2; + uint32_t RESERVED14 : 4; + __IO uint32_t TIOA14E : 2; + __IO uint32_t TIOB14S : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t TIOA15S : 2; + __IO uint32_t TIOA15E : 2; + __IO uint32_t TIOB15S : 2; +} stc_gpio_epfr13_field_t; + +typedef struct stc_gpio_epfr14_field +{ + __IO uint32_t QAIN2S : 2; + __IO uint32_t QBIN2S : 2; + __IO uint32_t QZIN2S : 2; + uint32_t RESERVED6 :12; + __IO uint32_t E_TD0E : 1; + __IO uint32_t E_TD1E : 1; + __IO uint32_t E_TE0E : 1; + __IO uint32_t E_TE1E : 1; + __IO uint32_t E_MC0E : 1; + __IO uint32_t E_MC1B : 1; + __IO uint32_t E_MD0B : 1; + __IO uint32_t E_MD1B : 1; + __IO uint32_t E_CKE : 1; + __IO uint32_t E_PSE : 1; + __IO uint32_t E_SPLC : 2; +} stc_gpio_epfr14_field_t; + +typedef struct stc_gpio_epfr15_field +{ + __IO uint32_t EINT16S : 2; + __IO uint32_t EINT17S : 2; + __IO uint32_t EINT18S : 2; + __IO uint32_t EINT19S : 2; + __IO uint32_t EINT20S : 2; + __IO uint32_t EINT21S : 2; + __IO uint32_t EINT22S : 2; + __IO uint32_t EINT23S : 2; + __IO uint32_t EINT24S : 2; + __IO uint32_t EINT25S : 2; + __IO uint32_t EINT26S : 2; + __IO uint32_t EINT27S : 2; + __IO uint32_t EINT28S : 2; + __IO uint32_t EINT29S : 2; + __IO uint32_t EINT30S : 2; + __IO uint32_t EINT31S : 2; +} stc_gpio_epfr15_field_t; + +typedef struct stc_gpio_epfr16_field +{ + __IO uint32_t SCS6B : 2; + __IO uint32_t SCS7B : 2; + __IO uint32_t SIN8S : 2; + __IO uint32_t SOT8B : 2; + __IO uint32_t SCK8B : 2; + __IO uint32_t SIN9S : 2; + __IO uint32_t SOT9B : 2; + __IO uint32_t SCK9B : 2; + __IO uint32_t SIN10S : 2; + __IO uint32_t SOT10B : 2; + __IO uint32_t SCK10B : 2; + __IO uint32_t SIN11S : 2; + __IO uint32_t SOT11B : 2; + __IO uint32_t SCK11B : 2; + __IO uint32_t SFMPAC : 1; + __IO uint32_t SFMPBC : 1; +} stc_gpio_epfr16_field_t; + +typedef struct stc_gpio_epfr17_field +{ + uint32_t RESERVED0 : 4; + __IO uint32_t SIN12S : 2; + __IO uint32_t SOT12B : 2; + __IO uint32_t SCK12B : 2; + __IO uint32_t SIN13S : 2; + __IO uint32_t SOT13B : 2; + __IO uint32_t SCK13B : 2; + __IO uint32_t SIN14S : 2; + __IO uint32_t SOT14B : 2; + __IO uint32_t SCK14B : 2; + __IO uint32_t SIN15S : 2; + __IO uint32_t SOT15B : 2; + __IO uint32_t SCK15B : 2; +} stc_gpio_epfr17_field_t; + +typedef struct stc_gpio_epfr18_field +{ + uint32_t RESERVED0 : 4; + __IO uint32_t QAIN3S : 2; + __IO uint32_t QBIN3S : 2; + __IO uint32_t QZIN3S : 2; + uint32_t RESERVED10 : 4; + __IO uint32_t SDCLKE : 2; + __IO uint32_t SDCMDB : 2; + __IO uint32_t SDDATA0B : 2; + __IO uint32_t SDDATA1B : 2; + __IO uint32_t SDDATA2B : 2; + __IO uint32_t SDDATA3B : 2; + __IO uint32_t SDCDS : 2; + __IO uint32_t SDWPS : 2; +} stc_gpio_epfr18_field_t; + +typedef struct stc_gpio_epfr20_field +{ + __IO uint32_t UESMCEE : 1; + __IO uint32_t UESMCKE : 1; + __IO uint32_t UERASE : 1; + __IO uint32_t UECASE : 1; + __IO uint32_t UEDWEXE : 1; + __IO uint32_t UECSXE : 1; + __IO uint32_t UEDQM2E : 1; + __IO uint32_t UEDQM3E : 1; + __IO uint32_t UEDTHHB : 1; + __IO uint32_t UED16B : 1; + __IO uint32_t UED17B : 1; + __IO uint32_t UED18B : 1; + __IO uint32_t UED19B : 1; + __IO uint32_t UED20B : 1; + __IO uint32_t UED21B : 1; + __IO uint32_t UED22B : 1; + __IO uint32_t UED23B : 1; + __IO uint32_t UED24B : 1; + __IO uint32_t UED25B : 1; + __IO uint32_t UED26B : 1; + __IO uint32_t UED27B : 1; + __IO uint32_t UED28B : 1; + __IO uint32_t UED29B : 1; + __IO uint32_t UED30B : 1; + __IO uint32_t UED31B : 1; +} stc_gpio_epfr20_field_t; + +typedef struct stc_gpio_pzr0_field +{ + __IO uint32_t P00 : 1; + __IO uint32_t P01 : 1; + __IO uint32_t P02 : 1; + __IO uint32_t P03 : 1; + __IO uint32_t P04 : 1; + __IO uint32_t P05 : 1; + __IO uint32_t P06 : 1; + __IO uint32_t P07 : 1; + __IO uint32_t P08 : 1; + __IO uint32_t P09 : 1; + __IO uint32_t P0A : 1; + __IO uint32_t P0B : 1; + __IO uint32_t P0C : 1; + __IO uint32_t P0D : 1; + __IO uint32_t P0E : 1; + __IO uint32_t P0F : 1; +} stc_gpio_pzr0_field_t; + +typedef struct stc_gpio_pzr1_field +{ + __IO uint32_t P10 : 1; + __IO uint32_t P11 : 1; + __IO uint32_t P12 : 1; + __IO uint32_t P13 : 1; + __IO uint32_t P14 : 1; + __IO uint32_t P15 : 1; + __IO uint32_t P16 : 1; + __IO uint32_t P17 : 1; + __IO uint32_t P18 : 1; + __IO uint32_t P19 : 1; + __IO uint32_t P1A : 1; + __IO uint32_t P1B : 1; + __IO uint32_t P1C : 1; + __IO uint32_t P1D : 1; + __IO uint32_t P1E : 1; + __IO uint32_t P1F : 1; +} stc_gpio_pzr1_field_t; + +typedef struct stc_gpio_pzr2_field +{ + __IO uint32_t P20 : 1; + __IO uint32_t P21 : 1; + __IO uint32_t P22 : 1; + __IO uint32_t P23 : 1; + __IO uint32_t P24 : 1; + __IO uint32_t P25 : 1; + __IO uint32_t P26 : 1; + __IO uint32_t P27 : 1; +} stc_gpio_pzr2_field_t; + +typedef struct stc_gpio_pzr3_field +{ + __IO uint32_t P30 : 1; + __IO uint32_t P31 : 1; + __IO uint32_t P32 : 1; + __IO uint32_t P33 : 1; + __IO uint32_t P34 : 1; + __IO uint32_t P35 : 1; + __IO uint32_t P36 : 1; + __IO uint32_t P37 : 1; + __IO uint32_t P38 : 1; + __IO uint32_t P39 : 1; + __IO uint32_t P3A : 1; + __IO uint32_t P3B : 1; + __IO uint32_t P3C : 1; + __IO uint32_t P3D : 1; + __IO uint32_t P3E : 1; + __IO uint32_t P3F : 1; +} stc_gpio_pzr3_field_t; + +typedef struct stc_gpio_pzr4_field +{ + __IO uint32_t P40 : 1; + __IO uint32_t P41 : 1; + __IO uint32_t P42 : 1; + __IO uint32_t P43 : 1; + __IO uint32_t P44 : 1; + __IO uint32_t P45 : 1; + __IO uint32_t P46 : 1; + __IO uint32_t P47 : 1; + __IO uint32_t P48 : 1; + __IO uint32_t P49 : 1; + __IO uint32_t P4A : 1; + __IO uint32_t P4B : 1; + __IO uint32_t P4C : 1; + __IO uint32_t P4D : 1; + __IO uint32_t P4E : 1; +} stc_gpio_pzr4_field_t; + +typedef struct stc_gpio_pzr5_field +{ + __IO uint32_t P50 : 1; + __IO uint32_t P51 : 1; + __IO uint32_t P52 : 1; + __IO uint32_t P53 : 1; + __IO uint32_t P54 : 1; + __IO uint32_t P55 : 1; + __IO uint32_t P56 : 1; + __IO uint32_t P57 : 1; + __IO uint32_t P58 : 1; + __IO uint32_t P59 : 1; + __IO uint32_t P5A : 1; + __IO uint32_t P5B : 1; +} stc_gpio_pzr5_field_t; + +typedef struct stc_gpio_pzr6_field +{ + __IO uint32_t P60 : 1; + __IO uint32_t P61 : 1; + __IO uint32_t P62 : 1; + __IO uint32_t P63 : 1; + __IO uint32_t P64 : 1; + __IO uint32_t P65 : 1; + __IO uint32_t P66 : 1; + __IO uint32_t P67 : 1; + __IO uint32_t P68 : 1; +} stc_gpio_pzr6_field_t; + +typedef struct stc_gpio_pzr7_field +{ + __IO uint32_t P70 : 1; + __IO uint32_t P71 : 1; + __IO uint32_t P72 : 1; + __IO uint32_t P73 : 1; + __IO uint32_t P74 : 1; +} stc_gpio_pzr7_field_t; + +typedef struct stc_gpio_pzr8_field +{ + __IO uint32_t P80 : 1; + __IO uint32_t P81 : 1; +} stc_gpio_pzr8_field_t; + +typedef struct stc_gpio_pzre_field +{ + __IO uint32_t PE0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t PE2 : 1; + __IO uint32_t PE3 : 1; +} stc_gpio_pzre_field_t; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* LVD_MODULE register bit fields */ +typedef struct stc_lvd_lvd_ctl_field +{ + union { + struct { + uint8_t RESERVED1 : 2; + __IO uint8_t SVHI : 4; + uint8_t RESERVED2 : 1; + __IO uint8_t LVDIE : 1; + }; + struct { + uint8_t RESERVED3 : 2; + __IO uint8_t SVHI0 : 1; + __IO uint8_t SVHI1 : 1; + __IO uint8_t SVHI2 : 1; + __IO uint8_t SVHI3 : 1; + uint8_t RESERVED4 : 2; + }; + }; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIR : 1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDCL : 1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + uint8_t RESERVED1 : 6; + __IO uint8_t LVDRRDY : 1; + __IO uint8_t LVDIRDY : 1; +} stc_lvd_lvd_str2_field_t; + +/****************************************************************************** + * DS_MODULE + ******************************************************************************/ +/* DS_MODULE register bit fields */ +typedef struct stc_ds_rck_ctl_field +{ + __IO uint8_t RTCCKE : 1; +} stc_ds_rck_ctl_field_t; + +typedef struct stc_ds_pmd_ctl_field +{ + __IO uint8_t RTCE : 1; +} stc_ds_pmd_ctl_field_t; + +typedef struct stc_ds_wrfsr_field +{ + __IO uint8_t WINITX : 1; + __IO uint8_t WLVDH : 1; +} stc_ds_wrfsr_field_t; + +typedef struct stc_ds_wifsr_field +{ + __IO uint16_t WRTCI : 1; + __IO uint16_t WLVDI : 1; + __IO uint16_t WUI0 : 1; + __IO uint16_t WUI1 : 1; + __IO uint16_t WUI2 : 1; + __IO uint16_t WUI3 : 1; + __IO uint16_t WUI4 : 1; + __IO uint16_t WUI5 : 1; +} stc_ds_wifsr_field_t; + +typedef struct stc_ds_wier_field +{ + __IO uint16_t WRTCE : 1; + __IO uint16_t WLVDE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t WUI1E : 1; + __IO uint16_t WUI2E : 1; + __IO uint16_t WUI3E : 1; + __IO uint16_t WUI4E : 1; + __IO uint16_t WUI5E : 1; +} stc_ds_wier_field_t; + +typedef struct stc_ds_wilvr_field +{ + __IO uint8_t WUI1LV : 1; + __IO uint8_t WUI2LV : 1; + __IO uint8_t WUI3LV : 1; + __IO uint8_t WUI4LV : 1; + __IO uint8_t WUI5LV : 1; +} stc_ds_wilvr_field_t; + +typedef struct stc_ds_dsramr_field +{ + __IO uint8_t SRAMR : 2; +} stc_ds_dsramr_field_t; + +/****************************************************************************** + * USB Ethernet CLK + ******************************************************************************/ +/* USB ETHERNET CLK register bit fields */ +typedef struct stc_usbethernetclk_uccr_field +{ + __IO uint8_t UCEN0 : 1; + __IO uint8_t UCSEL0 : 1; + __IO uint8_t UCSEL1 : 1; + __IO uint8_t UCEN1 : 1; + __IO uint8_t ECEN : 1; + __IO uint8_t ECSEL0 : 1; + __IO uint8_t ECSEL1 : 1; +} stc_usbethernetclk_uccr_field_t; + +typedef struct stc_usbethernetclk_upcr1_field +{ + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; +} stc_usbethernetclk_upcr1_field_t; + +typedef struct stc_usbethernetclk_upcr2_field +{ + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; +} stc_usbethernetclk_upcr2_field_t; + +typedef struct stc_usbethernetclk_upcr3_field +{ + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; +} stc_usbethernetclk_upcr3_field_t; + +typedef struct stc_usbethernetclk_upcr4_field +{ + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; +} stc_usbethernetclk_upcr4_field_t; + +typedef struct stc_usbethernetclk_up_str_field +{ + __IO uint8_t UPRDY : 1; +} stc_usbethernetclk_up_str_field_t; + +typedef struct stc_usbethernetclk_upint_enr_field +{ + __IO uint8_t UPCSE : 1; +} stc_usbethernetclk_upint_enr_field_t; + +typedef struct stc_usbethernetclk_upint_clr_field +{ + __IO uint8_t UPCSC : 1; +} stc_usbethernetclk_upint_clr_field_t; + +typedef struct stc_usbethernetclk_upint_str_field +{ + __IO uint8_t UPCSI : 1; +} stc_usbethernetclk_upint_str_field_t; + +typedef struct stc_usbethernetclk_upcr5_field +{ + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; +} stc_usbethernetclk_upcr5_field_t; + +typedef struct stc_usbethernetclk_upcr6_field +{ + __IO uint8_t UBSR0 : 1; + __IO uint8_t UBSR1 : 1; + __IO uint8_t UBSR2 : 1; + __IO uint8_t UBSR3 : 1; +} stc_usbethernetclk_upcr6_field_t; + +typedef struct stc_usbethernetclk_upcr7_field +{ + __IO uint8_t EPLLEN : 1; +} stc_usbethernetclk_upcr7_field_t; + +typedef struct stc_usbethernetclk_usben0_field +{ + __IO uint8_t USBEN0 : 1; +} stc_usbethernetclk_usben0_field_t; + +typedef struct stc_usbethernetclk_usben1_field +{ + __IO uint8_t USBEN1 : 1; +} stc_usbethernetclk_usben1_field_t; + + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USBCLK register bit fields */ +typedef struct stc_usbclk_uccr_field +{ + __IO uint8_t UCEN : 1; + __IO uint8_t UCSEL : 1; +} stc_usbclk_uccr_field_t; + +typedef struct stc_usbclk_upcr1_field +{ + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; +} stc_usbclk_upcr1_field_t; + +typedef struct stc_usbclk_upcr2_field +{ + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; +} stc_usbclk_upcr2_field_t; + +typedef struct stc_usbclk_upcr3_field +{ + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; +} stc_usbclk_upcr3_field_t; + +typedef struct stc_usbclk_upcr4_field +{ + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; +} stc_usbclk_upcr4_field_t; + +typedef struct stc_usbclk_up_str_field +{ + __IO uint8_t UPRDY : 1; +} stc_usbclk_up_str_field_t; + +typedef struct stc_usbclk_upint_enr_field +{ + __IO uint8_t UPCSE : 1; +} stc_usbclk_upint_enr_field_t; + +typedef struct stc_usbclk_upint_clr_field +{ + __IO uint8_t UPCSC : 1; +} stc_usbclk_upint_clr_field_t; + +typedef struct stc_usbclk_upint_str_field +{ + __IO uint8_t UPCSI : 1; +} stc_usbclk_upint_str_field_t; + +typedef struct stc_usbclk_usben_field +{ + __IO uint8_t USBEN : 1; +} stc_usbclk_usben_field_t; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CANPRE_MODULE register bit fields */ +typedef struct stc_canpre_canpre_field +{ + __IO uint8_t CANPRE0 : 1; + __IO uint8_t CANPRE1 : 1; + __IO uint8_t CANPRE2 : 1; + __IO uint8_t CANPRE3 : 1; +} stc_canpre_canpre_field_t; + +/****************************************************************************** + * MFS_MODULE(COMMON) + ******************************************************************************/ +/* MFS_MODULE(COMMON) register bit fields */ +typedef struct stc_mfs_smr_field +{ + union { + struct { + __IO uint8_t SOE : 1; /* for UART/CSIO/LIN */ + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; /* for UART/CSIO */ + __IO uint8_t SBL : 1; /* for UART/LIN */ + __IO uint8_t WUCR : 1; /* for UART/LIN */ + __IO uint8_t MD : 3; /* for UART/CSIO/LIN/I2C */ + }; + struct { + uint8_t RESERVED2 : 1; + __IO uint8_t SCKE : 1; /* for CSIO */ + uint8_t RESERVED3 : 1; + __IO uint8_t SCINV : 1; /* for CSIO */ + uint8_t RESERVED4 : 4; + }; + struct { + uint8_t RESERVED5 : 2; + __IO uint8_t TIE : 1; /* for I2C */ + __IO uint8_t RIE : 1; /* for I2C */ + uint8_t RESERVED6 : 4; + }; + }; +} stc_mfs_smr_field_t; + +typedef struct stc_mfs_scr_field +{ + union { + struct { + __IO uint8_t TXE : 1; /* for UART/CSIO/LIN */ + __IO uint8_t RXE : 1; /* for UART/CSIO/LIN */ + __IO uint8_t TBIE : 1; /* for UART/CSIO/LIN */ + __IO uint8_t TIE : 1; /* for UART/CSIO/LIN */ + __IO uint8_t RIE : 1; /* for UART/CSIO/LIN */ + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; /* for UART/CSIO/LIN */ + }; + struct { + uint8_t RESERVED2 : 5; + __IO uint8_t SPI : 1; /* for CSIO */ + __IO uint8_t MS : 1; /* for CSIO/LIN */ + uint8_t RESERVED3 : 1; + }; + struct { + uint8_t RESERVED4 : 5; + __IO uint8_t LBR : 1; /* for LIN */ + uint8_t RESERVED5 : 2; + }; + }; +} stc_mfs_scr_field_t; + +typedef struct stc_mfs_escr_field +{ + union { + struct { + __IO uint8_t L : 3; /* for UART/CSIO */ + __IO uint8_t P : 1; /* for UART */ + __IO uint8_t PEN : 1; /* for UART */ + __IO uint8_t INV : 1; /* for UART */ + __IO uint8_t ESBL : 1; /* for UART/LIN */ + __IO uint8_t FLWEN : 1; /* for UART */ + }; + struct { + __IO uint8_t L0 : 1; /* for UART/CSIO */ + __IO uint8_t L1 : 1; /* for UART/CSIO */ + __IO uint8_t L2 : 1; /* for UART/CSIO */ + __IO uint8_t WT : 2; /* for CSIO */ + uint8_t RESERVED2 : 1; + __IO uint8_t L3 : 1; /* for CSIO */ + __IO uint8_t SOP : 1; /* for CSIO */ + }; + struct { + uint8_t RESERVED3 : 3; + __IO uint8_t WT0 : 1; /* for CSIO */ + __IO uint8_t WT1 : 1; /* for CSIO */ + uint8_t RESERVED4 : 3; + }; + struct { + __IO uint8_t DEL : 2; /* for LIN */ + __IO uint8_t LBL : 2; /* for LIN */ + __IO uint8_t LBIE : 1; /* for LIN */ + uint8_t RESERVED5 : 3; + }; + struct { + __IO uint8_t DEL0 : 1; /* for LIN */ + __IO uint8_t DEL1 : 1; /* for LIN */ + __IO uint8_t LBL0 : 1; /* for LIN */ + __IO uint8_t LBL1 : 1; /* for LIN */ + uint8_t RESERVED6 : 4; + }; + }; +} stc_mfs_escr_field_t; + +typedef struct stc_mfs_ssr_field +{ + union { + struct { + __IO uint8_t TBI : 1; /* for UART/CSIO/LIN/I2C */ + __IO uint8_t TDRE : 1; /* for UART/CSIO/LIN/I2C */ + __IO uint8_t RDRF : 1; /* for UART/CSIO/LIN/I2C */ + __IO uint8_t ORE : 1; /* for UART/CSIO/LIN/I2C */ + __IO uint8_t FRE : 1; /* for UART/LIN */ + __IO uint8_t PE : 1; /* for UART */ + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; /* for UART/CSIO/LIN/I2C */ + }; + struct { + uint8_t RESERVED2 : 4; + __IO uint8_t AWC : 1; /* for CSIO */ + uint8_t RESERVED3 : 3; + }; + struct { + uint8_t RESERVED4 : 5; + __IO uint8_t LBD : 1; /* for LIN */ + uint8_t RESERVED5 : 2; + }; + struct { + uint8_t RESERVED6 : 4; + __IO uint8_t TBIE : 1; /* for I2C */ + __IO uint8_t DMA : 1; /* for I2C */ + __IO uint8_t TSET : 1; /* for I2C */ + uint8_t RESERVED7 : 1; + }; + }; +} stc_mfs_ssr_field_t; + +typedef struct stc_mfs_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs_bgr_field_t; + +typedef struct stc_mfs_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs_bgr1_field_t; + +typedef struct stc_mfs_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs_fcr_field_t; + +typedef struct stc_mfs_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; + uint8_t RESERVED1 : 1; +} stc_mfs_fcr0_field_t; + +typedef struct stc_mfs_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs_fcr1_field_t; + +typedef struct stc_mfs_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs_fbyte_field_t; + +typedef struct stc_mfs_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs_fbyte1_field_t; + +typedef struct stc_mfs_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs_fbyte2_field_t; + +/****************************************************************************** + * MFS_MODULE(UART) + ******************************************************************************/ +/* MFS_MODULE(UART) register bit fields */ +typedef struct stc_mfs_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; + uint16_t RESERVED2 : 7; +} stc_mfs_uart_rdr_field_t; + +typedef struct stc_mfs_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; + uint16_t RESERVED2 : 7; +} stc_mfs_uart_tdr_field_t; + +/****************************************************************************** + * MFS_MODULE(CSIO) + ******************************************************************************/ +/* MFS_MODULE(CSIO) register bit fields */ +typedef struct stc_mfs_csio_scstr10_field +{ + __IO uint16_t CSHD0 : 1; + __IO uint16_t CSHD1 : 1; + __IO uint16_t CSHD2 : 1; + __IO uint16_t CSHD3 : 1; + __IO uint16_t CSHD4 : 1; + __IO uint16_t CSHD5 : 1; + __IO uint16_t CSHD6 : 1; + __IO uint16_t CSHD7 : 1; + __IO uint16_t CSSU0 : 1; + __IO uint16_t CSSU1 : 1; + __IO uint16_t CSSU2 : 1; + __IO uint16_t CSSU3 : 1; + __IO uint16_t CSSU4 : 1; + __IO uint16_t CSSU5 : 1; + __IO uint16_t CSSU6 : 1; + __IO uint16_t CSSU7 : 1; +} stc_mfs_csio_scstr10_field_t; + +typedef struct stc_mfs_csio_scstr0_field +{ + __IO uint8_t CSHD0 : 1; + __IO uint8_t CSHD1 : 1; + __IO uint8_t CSHD2 : 1; + __IO uint8_t CSHD3 : 1; + __IO uint8_t CSHD4 : 1; + __IO uint8_t CSHD5 : 1; + __IO uint8_t CSHD6 : 1; + __IO uint8_t CSHD7 : 1; +} stc_mfs_csio_scstr0_field_t; + +typedef struct stc_mfs_csio_scstr1_field +{ + __IO uint8_t CSSU0 : 1; + __IO uint8_t CSSU1 : 1; + __IO uint8_t CSSU2 : 1; + __IO uint8_t CSSU3 : 1; + __IO uint8_t CSSU4 : 1; + __IO uint8_t CSSU5 : 1; + __IO uint8_t CSSU6 : 1; + __IO uint8_t CSSU7 : 1; +} stc_mfs_csio_scstr1_field_t; + +typedef struct stc_mfs_csio_scstr32_field +{ + __IO uint16_t CSDS0 : 1; + __IO uint16_t CSDS1 : 1; + __IO uint16_t CSDS2 : 1; + __IO uint16_t CSDS3 : 1; + __IO uint16_t CSDS4 : 1; + __IO uint16_t CSDS5 : 1; + __IO uint16_t CSDS6 : 1; + __IO uint16_t CSDS7 : 1; + __IO uint16_t CSDS8 : 1; + __IO uint16_t CSDS9 : 1; + __IO uint16_t CSDS10 : 1; + __IO uint16_t CSDS11 : 1; + __IO uint16_t CSDS12 : 1; + __IO uint16_t CSDS13 : 1; + __IO uint16_t CSDS14 : 1; + __IO uint16_t CSDS15 : 1; +} stc_mfs_csio_scstr32_field_t; + +typedef struct stc_mfs_csio_scstr2_field +{ + __IO uint8_t CSDS0 : 1; + __IO uint8_t CSDS1 : 1; + __IO uint8_t CSDS2 : 1; + __IO uint8_t CSDS3 : 1; + __IO uint8_t CSDS4 : 1; + __IO uint8_t CSDS5 : 1; + __IO uint8_t CSDS6 : 1; + __IO uint8_t CSDS7 : 1; +} stc_mfs_csio_scstr2_field_t; + +typedef struct stc_mfs_csio_scstr3_field +{ + __IO uint8_t CSDS8 : 1; + __IO uint8_t CSDS9 : 1; + __IO uint8_t CSDS10 : 1; + __IO uint8_t CSDS11 : 1; + __IO uint8_t CSDS12 : 1; + __IO uint8_t CSDS13 : 1; + __IO uint8_t CSDS14 : 1; + __IO uint8_t CSDS15 : 1; +} stc_mfs_csio_scstr3_field_t; + +typedef struct stc_mfs_csio_sacsr_field +{ + __IO uint16_t TMRE : 1; + __IO uint16_t TDIV : 4; + uint16_t RESERVED1 : 1; + __IO uint16_t TSYNE : 1; + __IO uint16_t TINTE : 1; + __IO uint16_t TINT : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t CSE : 1; + __IO uint16_t CSEIE : 1; + __IO uint16_t TBEEN : 1; + uint16_t RESERVED3 : 2; +} stc_mfs_csio_sacsr_field_t; + +typedef struct stc_mfs_csio_sacsr0_field +{ + __IO uint8_t TMRE : 1; + __IO uint8_t TDIV : 4; + uint8_t RESERVED1 : 1; + __IO uint8_t TSYNE : 1; + __IO uint8_t TINTE : 1; +} stc_mfs_csio_sacsr0_field_t; + +typedef struct stc_mfs_csio_sacsr1_field +{ + __IO uint8_t TINT : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CSE : 1; + __IO uint8_t CSEIE : 1; + __IO uint8_t TBEEN : 1; + uint8_t RESERVED2 : 2; +} stc_mfs_csio_sacsr1_field_t; + +typedef struct stc_mfs_csio_stmr_field +{ + __IO uint16_t TM0 : 1; + __IO uint16_t TM1 : 1; + __IO uint16_t TM2 : 1; + __IO uint16_t TM3 : 1; + __IO uint16_t TM4 : 1; + __IO uint16_t TM5 : 1; + __IO uint16_t TM6 : 1; + __IO uint16_t TM7 : 1; + __IO uint16_t TM8 : 1; + __IO uint16_t TM9 : 1; + __IO uint16_t TM10 : 1; + __IO uint16_t TM11 : 1; + __IO uint16_t TM12 : 1; + __IO uint16_t TM13 : 1; + __IO uint16_t TM14 : 1; + __IO uint16_t TM15 : 1; +} stc_mfs_csio_stmr_field_t; + +typedef struct stc_mfs_csio_stmr0_field +{ + __IO uint8_t TM0 : 1; + __IO uint8_t TM1 : 1; + __IO uint8_t TM2 : 1; + __IO uint8_t TM3 : 1; + __IO uint8_t TM4 : 1; + __IO uint8_t TM5 : 1; + __IO uint8_t TM6 : 1; + __IO uint8_t TM7 : 1; +} stc_mfs_csio_stmr0_field_t; + +typedef struct stc_mfs_csio_stmr1_field +{ + __IO uint8_t TM8 : 1; + __IO uint8_t TM9 : 1; + __IO uint8_t TM10 : 1; + __IO uint8_t TM11 : 1; + __IO uint8_t TM12 : 1; + __IO uint8_t TM13 : 1; + __IO uint8_t TM14 : 1; + __IO uint8_t TM15 : 1; +} stc_mfs_csio_stmr1_field_t; + +typedef struct stc_mfs_csio_stmcr_field +{ + __IO uint16_t TC0 : 1; + __IO uint16_t TC1 : 1; + __IO uint16_t TC2 : 1; + __IO uint16_t TC3 : 1; + __IO uint16_t TC4 : 1; + __IO uint16_t TC5 : 1; + __IO uint16_t TC6 : 1; + __IO uint16_t TC7 : 1; + __IO uint16_t TC8 : 1; + __IO uint16_t TC9 : 1; + __IO uint16_t TC10 : 1; + __IO uint16_t TC11 : 1; + __IO uint16_t TC12 : 1; + __IO uint16_t TC13 : 1; + __IO uint16_t TC14 : 1; + __IO uint16_t TC15 : 1; +} stc_mfs_csio_stmcr_field_t; + +typedef struct stc_mfs_csio_stmcr0_field +{ + __IO uint8_t TC0 : 1; + __IO uint8_t TC1 : 1; + __IO uint8_t TC2 : 1; + __IO uint8_t TC3 : 1; + __IO uint8_t TC4 : 1; + __IO uint8_t TC5 : 1; + __IO uint8_t TC6 : 1; + __IO uint8_t TC7 : 1; +} stc_mfs_csio_stmcr0_field_t; + +typedef struct stc_mfs_csio_stmcr1_field +{ + __IO uint8_t TC8 : 1; + __IO uint8_t TC9 : 1; + __IO uint8_t TC10 : 1; + __IO uint8_t TC11 : 1; + __IO uint8_t TC12 : 1; + __IO uint8_t TC13 : 1; + __IO uint8_t TC14 : 1; + __IO uint8_t TC15 : 1; +} stc_mfs_csio_stmcr1_field_t; + +typedef struct stc_mfs_csio_scscr_field +{ + __IO uint16_t CSOE : 1; + __IO uint16_t CSEN0 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t CSLVL : 1; + __IO uint16_t CDIV : 3; + __IO uint16_t SCAM : 1; + uint16_t RESERVED2 : 6; +} stc_mfs_csio_scscr_field_t; + +/****************************************************************************** + * MFS_MODULE(I2C) + ******************************************************************************/ +/* MFS_MODULE(I2C) register bit fields */ +typedef struct stc_mfs_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t ACT_SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs_i2c_ibcr_field_t; + +typedef struct stc_mfs_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs_i2c_ibsr_field_t; + +typedef struct stc_mfs_i2c_isba_field +{ + union { + struct { + __IO uint8_t SA : 7; + __IO uint8_t SAEN : 1; + }; + struct { + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + uint8_t RESERVED1 : 1; + }; + }; +} stc_mfs_i2c_isba_field_t; + +typedef struct stc_mfs_i2c_ismk_field +{ + union { + struct { + __IO uint8_t SM : 7; + __IO uint8_t EN : 1; + }; + struct { + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + uint8_t RESERVED1 : 1; + }; + }; +} stc_mfs_i2c_ismk_field_t; + +typedef struct stc_mfs_i2c_nfcr_field +{ + __IO uint8_t NFT : 5; + uint8_t RESERVED1 : 3; +} stc_mfs_i2c_nfcr_field_t; + +typedef struct stc_mfs_i2c_eibcr_field +{ + __IO uint8_t BEC : 1; + __IO uint8_t SOCE : 1; + __IO uint8_t SCLC : 1; + __IO uint8_t SDAC : 1; + __IO uint8_t SCLS : 1; + __IO uint8_t SDAS : 1; + uint8_t RESERVED1 : 2; +} stc_mfs_i2c_eibcr_field_t; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC_MODULE register bit fields */ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT : 1; + __IO uint8_t CRC32 : 1; + __IO uint8_t LTLEND : 1; + __IO uint8_t LSBFST : 1; + __IO uint8_t CRCLTE : 1; + __IO uint8_t CRCLSF : 1; + __IO uint8_t FXOR : 1; +} stc_crc_crccr_field_t; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* WC_MODULE register bit fields */ +typedef struct stc_wc_wcrd_field +{ + __IO uint8_t CTR0 : 1; + __IO uint8_t CTR1 : 1; + __IO uint8_t CTR2 : 1; + __IO uint8_t CTR3 : 1; + __IO uint8_t CTR4 : 1; + __IO uint8_t CTR5 : 1; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + __IO uint8_t RLC0 : 1; + __IO uint8_t RLC1 : 1; + __IO uint8_t RLC2 : 1; + __IO uint8_t RLC3 : 1; + __IO uint8_t RLC4 : 1; + __IO uint8_t RLC5 : 1; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + __IO uint8_t WCIF : 1; + __IO uint8_t WCIE : 1; + __IO uint8_t CS0 : 1; + __IO uint8_t CS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t WCOP : 1; + __IO uint8_t WCEN : 1; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + __IO uint16_t SEL_IN : 2; + uint16_t RESERVED1 : 6; + __IO uint16_t SEL_OUT : 3; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN : 1; + __IO uint8_t CLK_EN_R : 1; +} stc_wc_clk_en_field_t; + +/****************************************************************************** + * RTC_MODULE + ******************************************************************************/ +/* RTC_MODULE register bit fields */ +/* RTC CNT */ +typedef struct stc_rtc_wtcr10_field +{ + __IO uint8_t ST : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t RUN : 1; + __IO uint8_t SRST : 1; + __IO uint8_t SCST : 1; + __IO uint8_t SCRST : 1; + __IO uint8_t BUSY : 1; + __IO uint8_t TRANS : 1; +} stc_rtc_wtcr10_field_t; + +typedef struct stc_rtc_wtcr11_field +{ + __IO uint8_t MIEN : 1; + __IO uint8_t HEN : 1; + __IO uint8_t DEN : 1; + __IO uint8_t MOEN : 1; + __IO uint8_t YEN : 1; + uint8_t RESERVED1 : 3; +} stc_rtc_wtcr11_field_t; + +typedef struct stc_rtc_wtcr12_field +{ + __IO uint8_t INTSSI : 1; + __IO uint8_t INTSI : 1; + __IO uint8_t INTMI : 1; + __IO uint8_t INTHI : 1; + __IO uint8_t INTTMI : 1; + __IO uint8_t INTALI : 1; + __IO uint8_t INTERI : 1; + __IO uint8_t INTCRI : 1; +} stc_rtc_wtcr12_field_t; + +typedef struct stc_rtc_wtcr13_field +{ + __IO uint8_t INTSSIE : 1; + __IO uint8_t INTSIE : 1; + __IO uint8_t INTMIE : 1; + __IO uint8_t INTHIE : 1; + __IO uint8_t INTTMIE : 1; + __IO uint8_t INTALIE : 1; + __IO uint8_t INTERIE : 1; + __IO uint8_t INTCRIE : 1; +} stc_rtc_wtcr13_field_t; + +typedef struct stc_rtc_wtcr20_field +{ + __IO uint8_t CREAD : 1; + __IO uint8_t CWRITE : 1; + __IO uint8_t BREAD : 1; + __IO uint8_t BWRITE : 1; + __IO uint8_t PREAD : 1; + __IO uint8_t PWRITE : 1; + uint8_t RESERVED1 : 2; +} stc_rtc_wtcr20_field_t; + +typedef struct stc_rtc_wtcr21_field +{ + __IO uint8_t TMST : 1; + __IO uint8_t TMEN : 1; + __IO uint8_t TMRUN : 1; + uint8_t RESERVED1 : 5; +} stc_rtc_wtcr21_field_t; + +typedef struct stc_rtc_wtsr_field +{ + union { + struct { + __IO uint8_t S : 4; + __IO uint8_t TS : 3; + uint8_t RESERVED1 : 1; + }; + struct { + __IO uint8_t S0 : 1; + __IO uint8_t S1 : 1; + __IO uint8_t S2 : 1; + __IO uint8_t S3 : 1; + __IO uint8_t TS0 : 1; + __IO uint8_t TS1 : 1; + __IO uint8_t TS2 : 1; + uint8_t RESERVED2 : 1; + }; + }; +} stc_rtc_wtsr_field_t; + +typedef struct stc_rtc_wtmir_field +{ + union { + struct { + __IO uint8_t MI : 4; + __IO uint8_t TMI : 3; + uint8_t RESERVED1 : 1; + }; + struct { + __IO uint8_t MI0 : 1; + __IO uint8_t MI1 : 1; + __IO uint8_t MI2 : 1; + __IO uint8_t MI3 : 1; + __IO uint8_t TMI0 : 1; + __IO uint8_t TMI1 : 1; + __IO uint8_t TMI2 : 1; + uint8_t RESERVED2 : 1; + }; + }; +} stc_rtc_wtmir_field_t; + +typedef struct stc_rtc_wthr_field +{ + union { + struct { + __IO uint8_t H : 4; + __IO uint8_t TH : 2; + uint8_t RESERVED1 : 2; + }; + struct { + __IO uint8_t H0 : 1; + __IO uint8_t H1 : 1; + __IO uint8_t H2 : 1; + __IO uint8_t H3 : 1; + __IO uint8_t TH0 : 1; + __IO uint8_t TH1 : 1; + uint8_t RESERVED2 : 2; + }; + }; +} stc_rtc_wthr_field_t; + +typedef struct stc_rtc_wtdr_field +{ + union { + struct { + __IO uint8_t D : 4; + __IO uint8_t TD : 2; + uint8_t RESERVED1 : 2; + }; + struct { + __IO uint8_t D0 : 1; + __IO uint8_t D1 : 1; + __IO uint8_t D2 : 1; + __IO uint8_t D3 : 1; + __IO uint8_t TD0 : 1; + __IO uint8_t TD1 : 1; + uint8_t RESERVED2 : 2; + }; + }; +} stc_rtc_wtdr_field_t; + +typedef struct stc_rtc_wtdw_field +{ + union { + struct { + __IO uint8_t DW : 3; + uint8_t RESERVED1 : 5; + }; + struct { + __IO uint8_t DW0 : 1; + __IO uint8_t DW1 : 1; + __IO uint8_t DW2 : 1; + uint8_t RESERVED2 : 5; + }; + }; +} stc_rtc_wtdw_field_t; + +typedef struct stc_rtc_wtmor_field +{ + union { + struct { + __IO uint8_t MO : 4; + __IO uint8_t TMO : 1; + uint8_t RESERVED1 : 3; + }; + struct { + __IO uint8_t MO0 : 1; + __IO uint8_t MO1 : 1; + __IO uint8_t MO2 : 1; + __IO uint8_t MO3 : 1; + uint8_t RESERVED2 : 4; + }; + }; +} stc_rtc_wtmor_field_t; + +typedef struct stc_rtc_wtyr_field +{ + union { + struct { + __IO uint8_t Y : 4; + __IO uint8_t TY : 4; + }; + struct { + __IO uint8_t Y0 : 1; + __IO uint8_t Y1 : 1; + __IO uint8_t Y2 : 1; + __IO uint8_t Y3 : 1; + __IO uint8_t TY0 : 1; + __IO uint8_t TY1 : 1; + __IO uint8_t TY2 : 1; + __IO uint8_t TY3 : 1; + }; + }; +} stc_rtc_wtyr_field_t; + +typedef struct stc_rtc_almir_field +{ + union { + struct { + __IO uint8_t AMI : 4; + __IO uint8_t TAMI : 3; + uint8_t RESERVED1 : 1; + }; + struct { + __IO uint8_t AMI0 : 1; + __IO uint8_t AMI1 : 1; + __IO uint8_t AMI2 : 1; + __IO uint8_t AMI3 : 1; + __IO uint8_t TAMI0 : 1; + __IO uint8_t TAMI1 : 1; + __IO uint8_t TAMI2 : 1; + uint8_t RESERVED2 : 1; + }; + }; +} stc_rtc_almir_field_t; + +typedef struct stc_rtc_alhr_field +{ + union { + struct { + __IO uint8_t AH : 4; + __IO uint8_t TAH : 2; + uint8_t RESERVED1 : 2; + }; + struct { + __IO uint8_t AH0 : 1; + __IO uint8_t AH1 : 1; + __IO uint8_t AH2 : 1; + __IO uint8_t AH3 : 1; + __IO uint8_t TAH0 : 1; + __IO uint8_t TAH1 : 1; + uint8_t RESERVED2 : 2; + }; + }; +} stc_rtc_alhr_field_t; + +typedef struct stc_rtc_aldr_field +{ + union { + struct { + __IO uint8_t AD : 4; + __IO uint8_t TAD : 2; + uint8_t RESERVED1 : 2; + }; + struct { + __IO uint8_t AD0 : 1; + __IO uint8_t AD1 : 1; + __IO uint8_t AD2 : 1; + __IO uint8_t AD3 : 1; + __IO uint8_t TAD0 : 1; + __IO uint8_t TAD1 : 1; + uint8_t RESERVED2 : 2; + }; + }; +} stc_rtc_aldr_field_t; + +typedef struct stc_rtc_almor_field +{ + union { + struct { + __IO uint8_t AMO : 4; + __IO uint8_t TAMO : 1; + uint8_t RESERVED1 : 3; + }; + struct { + __IO uint8_t AMO0 : 1; + __IO uint8_t AMO1 : 1; + __IO uint8_t AMO2 : 1; + __IO uint8_t AMO3 : 1; + uint8_t RESERVED2 : 4; + }; + }; +} stc_rtc_almor_field_t; + +typedef struct stc_rtc_alyr_field +{ + union { + struct { + __IO uint8_t AY : 4; + __IO uint8_t TAY : 4; + }; + struct { + __IO uint8_t AY0 : 1; + __IO uint8_t AY1 : 1; + __IO uint8_t AY2 : 1; + __IO uint8_t AY3 : 1; + __IO uint8_t TAY0 : 1; + __IO uint8_t TAY1 : 1; + __IO uint8_t TAY2 : 1; + __IO uint8_t TAY3 : 1; + }; + }; +} stc_rtc_alyr_field_t; + +typedef struct stc_rtc_wttr0_field +{ + __IO uint8_t TM0 : 1; + __IO uint8_t TM1 : 1; + __IO uint8_t TM2 : 1; + __IO uint8_t TM3 : 1; + __IO uint8_t TM4 : 1; + __IO uint8_t TM5 : 1; + __IO uint8_t TM6 : 1; + __IO uint8_t TM7 : 1; +} stc_rtc_wttr0_field_t; + +typedef struct stc_rtc_wttr1_field +{ + __IO uint8_t TM8 : 1; + __IO uint8_t TM9 : 1; + __IO uint8_t TM10 : 1; + __IO uint8_t TM11 : 1; + __IO uint8_t TM12 : 1; + __IO uint8_t TM13 : 1; + __IO uint8_t TM14 : 1; + __IO uint8_t TM15 : 1; +} stc_rtc_wttr1_field_t; + +typedef struct stc_rtc_wttr2_field +{ + __IO uint8_t TM16 : 1; + __IO uint8_t TM17 : 1; + uint8_t RESERVED1 : 6; +} stc_rtc_wttr2_field_t; + +/* RTC CLK */ +typedef struct stc_rtc_wtcal1_field +{ + union { + struct { + __IO uint8_t WTCAL1 : 2; + uint8_t RESERVED1 : 6; + }; + struct { + __IO uint8_t WTCAL10 : 1; + __IO uint8_t WTCAL11 : 1; + uint8_t RESERVED2 : 6; + }; + }; +} stc_rtc_wtcal1_field_t; + +typedef struct stc_rtc_wtcalen_field +{ + __IO uint8_t WTCALEN : 1; + uint8_t RESERVED1 : 7; +} stc_rtc_wtcalen_field_t; + +typedef struct stc_rtc_wtdiv_field +{ + union { + struct { + __IO uint8_t WTDIV : 4; + uint8_t RESERVED1 : 4; + }; + struct { + __IO uint8_t WTDIV0 : 1; + __IO uint8_t WTDIV1 : 1; + __IO uint8_t WTDIV2 : 1; + __IO uint8_t WTDIV3 : 1; + uint8_t RESERVED2 : 4; + }; + }; +} stc_rtc_wtdiv_field_t; + +typedef struct stc_rtc_wtdiven_field +{ + __IO uint8_t WTDIVEN : 1; + __IO uint8_t WTDIVRDY : 1; + uint8_t RESERVED1 : 6; +} stc_rtc_wtdiven_field_t; + +typedef struct stc_rtc_wtcalprd_field +{ + union { + struct { + __IO uint8_t WTCALPRD : 6; + uint8_t RESERVED1 : 2; + }; + struct { + __IO uint8_t WTCALPRD0 : 1; + __IO uint8_t WTCALPRD1 : 1; + __IO uint8_t WTCALPRD2 : 1; + __IO uint8_t WTCALPRD3 : 1; + __IO uint8_t WTCALPRD4 : 1; + __IO uint8_t WTCALPRD5 : 1; + uint8_t RESERVED2 : 2; + }; + }; +} stc_rtc_wtcalprd_field_t; + +typedef struct stc_rtc_wtcosel_field +{ + __IO uint8_t WTCOSEL : 1; + __IO uint8_t WTDIVRDY : 7; +} stc_rtc_wtcosel_field_t; + +/* VBVat Domain */ +typedef struct stc_rtc_vb_clkdiv_field +{ + __IO uint8_t DIV : 8; +} stc_rtc_vb_clkdiv_field_t; + +typedef struct stc_rtc_wtosccnt_field +{ + __IO uint8_t SOSCEX : 1; + __IO uint8_t SOSCNTL : 1; +} stc_rtc_wtosccnt_field_t; + +typedef struct stc_rtc_boost_field +{ + __IO uint8_t BOOST : 2; +} stc_rtc_boost_field_t; + +typedef struct stc_rtc_ewkup_field +{ + __IO uint8_t WUP0 : 1; +} stc_rtc_ewkup_field_t; + +typedef struct stc_rtc_vdet_field +{ + uint8_t RESERVED0 : 7; + __IO uint8_t PON : 1; +} stc_rtc_vdet_field_t; + +typedef struct stc_rtc_hibrst_field +{ + __IO uint8_t HIBRST : 1; +} stc_rtc_hibrst_field_t; + +typedef struct stc_rtc_vbpfr_field +{ + __IO uint8_t VPFR0 : 1; + __IO uint8_t VPFR1 : 1; + __IO uint8_t VPFR2 : 1; + __IO uint8_t VPFR3 : 1; + __IO uint8_t SPSR0 : 1; + __IO uint8_t SPSR1 : 1; +} stc_rtc_vbpfr_field_t; + +typedef struct stc_rtc_vbpcr_field +{ + __IO uint8_t VPCR0 : 1; + __IO uint8_t VPCR1 : 1; + __IO uint8_t VPCR2 : 1; + __IO uint8_t VPCR3 : 1; +} stc_rtc_vbpcr_field_t; + +typedef struct stc_rtc_vbddr_field +{ + __IO uint8_t VDDR0 : 1; + __IO uint8_t VDDR1 : 1; + __IO uint8_t VDDR2 : 1; + __IO uint8_t VDDR3 : 1; +} stc_rtc_vbddr_field_t; + +typedef struct stc_rtc_vbdir_field +{ + __IO uint8_t VDIR0 : 1; + __IO uint8_t VDIR1 : 1; + __IO uint8_t VDIR2 : 1; + __IO uint8_t VDIR3 : 1; +} stc_rtc_vbdir_field_t; + +typedef struct stc_rtc_vbdor_field +{ + __IO uint8_t VDOR0 : 1; + __IO uint8_t VDOR1 : 1; + __IO uint8_t VDOR2 : 1; + __IO uint8_t VDOR3 : 1; +} stc_rtc_vbdor_field_t; + +typedef struct stc_rtc_vbpzr_field +{ + __IO uint8_t VPZR0 : 1; + __IO uint8_t VPZR1 : 1; +} stc_rtc_vbpzr_field_t; + +/****************************************************************************** + * LCR_MODULE + ******************************************************************************/ +/* LCR_MODULE register bit fields */ +typedef struct stc_lcr_lcr_prsld_field +{ + __IO uint8_t LCR_PRSLD : 6; +} stc_lcr_lcr_prsld_field_t; + +/****************************************************************************** + * CLK_GATING_MODULE + ******************************************************************************/ +/* CLK_GATING_MODULE register bit fields */ +typedef struct stc_clk_gating_cken0_field +{ + __IO uint32_t MFSCK0 : 1; + __IO uint32_t MFSCK1 : 1; + __IO uint32_t MFSCK2 : 1; + __IO uint32_t MFSCK3 : 1; + __IO uint32_t MFSCK4 : 1; + __IO uint32_t MFSCK5 : 1; + __IO uint32_t MFSCK6 : 1; + __IO uint32_t MFSCK7 : 1; + __IO uint32_t MFSCK8 : 1; + __IO uint32_t MFSCK9 : 1; + __IO uint32_t MFSCK10 : 1; + __IO uint32_t MFSCK11 : 1; + __IO uint32_t MFSCK12 : 1; + __IO uint32_t MFSCK13 : 1; + __IO uint32_t MFSCK14 : 1; + __IO uint32_t MFSCK15 : 1; + __IO uint32_t ADCCK0 : 1; + __IO uint32_t ADCCK1 : 1; + __IO uint32_t ADCCK2 : 1; + __IO uint32_t ADCCK3 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t DMACK : 1; + uint32_t RESERVED25 : 1; + __IO uint32_t EXBCK : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t GIOCK : 1; +} stc_clk_gating_cken0_field_t; + +typedef struct stc_clk_gating_mrst0_field +{ + __IO uint32_t MFSRST0 : 1; + __IO uint32_t MFSRST1 : 1; + __IO uint32_t MFSRST2 : 1; + __IO uint32_t MFSRST3 : 1; + __IO uint32_t MFSRST4 : 1; + __IO uint32_t MFSRST5 : 1; + __IO uint32_t MFSRST6 : 1; + __IO uint32_t MFSRST7 : 1; + __IO uint32_t MFSRST8 : 1; + __IO uint32_t MFSRST9 : 1; + __IO uint32_t MFSRST10 : 1; + __IO uint32_t MFSRST11 : 1; + __IO uint32_t MFSRST12 : 1; + __IO uint32_t MFSRST13 : 1; + __IO uint32_t MFSRST14 : 1; + __IO uint32_t MFSRST15 : 1; + __IO uint32_t ADCRST0 : 1; + __IO uint32_t ADCRST1 : 1; + __IO uint32_t ADCRST2 : 1; + __IO uint32_t ADCRST3 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t DMARST : 1; + uint32_t RESERVED25 : 1; + __IO uint32_t EXBRST : 1; +} stc_clk_gating_mrst0_field_t; + +typedef struct stc_clk_gating_cken1_field +{ + __IO uint32_t BTMCK0 : 1; + __IO uint32_t BTMCK1 : 1; + __IO uint32_t BTMCK2 : 1; + __IO uint32_t BTMCK3 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t MFTCK0 : 1; + __IO uint32_t MFTCK1 : 1; + __IO uint32_t MFTCK2 : 1; + __IO uint32_t MFTCK3 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t QDUCK0 : 1; + __IO uint32_t QDUCK1 : 1; + __IO uint32_t QDUCK2 : 1; + __IO uint32_t QDUCK3 : 1; +} stc_clk_gating_cken1_field_t; + +typedef struct stc_clk_gating_mrst1_field +{ + __IO uint32_t BTMRST0 : 1; + __IO uint32_t BTMRST1 : 1; + __IO uint32_t BTMRST2 : 1; + __IO uint32_t BTMRST3 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t MFTRST0 : 1; + __IO uint32_t MFTRST1 : 1; + __IO uint32_t MFTRST2 : 1; + __IO uint32_t MFTRST3 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t QDURST0 : 1; + __IO uint32_t QDURST1 : 1; + __IO uint32_t QDURST2 : 1; + __IO uint32_t QDURST3 : 1; +} stc_clk_gating_mrst1_field_t; + +typedef struct stc_clk_gating_cken2_field +{ + __IO uint32_t USBCK0 : 1; + __IO uint32_t USBCK1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CANCK0 : 1; + __IO uint32_t CANCK1 : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SDCCK : 1; +} stc_clk_gating_cken2_field_t; + +typedef struct stc_clk_gating_mrst2_field +{ + __IO uint32_t USBRST0 : 1; + __IO uint32_t USBRST1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CANRST0 : 1; + __IO uint32_t CANRST1 : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SDCRST : 1; +} stc_clk_gating_mrst2_field_t; + + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* EXBUS_MODULE register bit fields */ +typedef struct stc_exbus_mode_field +{ + __IO uint32_t WDTH : 2; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; + uint32_t RESERVED : 18; +} stc_exbus_mode_field_t; + +typedef struct stc_exbus_tim_field +{ + __IO uint32_t RACC : 4; + __IO uint32_t RADC : 4; + __IO uint32_t FRADC : 4; + __IO uint32_t RIDLC : 4; + __IO uint32_t WACC : 4; + __IO uint32_t WADC : 4; + __IO uint32_t WWEC : 4; + __IO uint32_t WIDLC : 4; +} stc_exbus_tim_field_t; + +typedef struct stc_exbus_area_field +{ + __IO uint32_t ADDR : 8; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK : 7; + uint32_t RESERVED2 : 9; +} stc_exbus_area_field_t; + +typedef struct stc_exbus_atim_field +{ + __IO uint32_t ALC : 4; + __IO uint32_t ALES : 4; + __IO uint32_t ALEW : 4; + uint32_t RESERVED : 20; +} stc_exbus_atim_field_t; + +typedef struct stc_exbus_sdmode_field +{ + __IO uint32_t SDON : 1; + __IO uint32_t PDON : 1; + __IO uint32_t ROFF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CASEL : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t RASEL : 4; + __IO uint32_t BASEL : 4; + __IO uint32_t MSDCLK : 1; + uint32_t RESERVED3 : 15; +} stc_exbus_sdmode_field_t; + +typedef struct stc_exbus_reftim_field +{ + __IO uint32_t REFC : 16; + __IO uint32_t NREF : 8; + __IO uint32_t PREF : 1; + uint32_t RESERVED : 7; +} stc_exbus_reftim_field_t; + +typedef struct stc_exbus_pwrdwn_field +{ + __IO uint32_t PDC : 16; + uint32_t RESERVED : 16; +} stc_exbus_pwrdwn_field_t; + +typedef struct stc_exbus_sdtim_field +{ + __IO uint32_t CL : 2; + uint32_t RESERVED1 : 2; + __IO uint32_t TRC : 4; + __IO uint32_t TRP : 4; + __IO uint32_t TRCD : 4; + __IO uint32_t TRAS : 4; + __IO uint32_t TREFC : 4; + __IO uint32_t TDPL : 2; + uint32_t RESERVED2 : 6; +} stc_exbus_sdtim_field_t; + +typedef struct stc_exbus_sdcmd_field +{ + __IO uint32_t SDAD : 16; + __IO uint32_t SDWE : 1; + __IO uint32_t SDCAS : 1; + __IO uint32_t SDRAS : 1; + __IO uint32_t SDCS : 1; + __IO uint32_t SDCKE : 1; + uint32_t RESERVED2 : 10; + __IO uint32_t PEND : 1; +} stc_exbus_sdcmd_field_t; + +typedef struct stc_exbus_memcerr_field +{ + __IO uint32_t SFER : 1; + __IO uint32_t SDER : 1; + __IO uint32_t SFION : 1; + __IO uint32_t SDION : 1; + uint32_t RESERVED : 28; +} stc_exbus_memcerr_field_t; + +typedef struct stc_exbus_dclkr_field +{ + __IO uint32_t MDIV : 4; + __IO uint32_t MCLKON : 1; + uint32_t RESERVED : 27; +} stc_exbus_dclkr_field_t; + +typedef struct stc_exbus_est_field +{ + __IO uint32_t WERR : 1; + uint32_t RESERVED : 31; +} stc_exbus_est_field_t; + +typedef struct stc_exbus_wead_field +{ + __IO uint32_t ADDR : 32; +} stc_exbus_wead_field_t; + +typedef struct stc_exbus_esclr_field +{ + __IO uint32_t WERRCLR : 1; + uint32_t RESERVED : 31; +} stc_exbus_esclr_field_t; + +typedef struct stc_exbus_amode_field +{ + __IO uint32_t WAEN : 1; + uint32_t RESERVED : 31; +} stc_exbus_amode_field_t; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB_MODULE register bit fields */ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST : 1; + __IO uint16_t URST : 1; + __IO uint16_t SOFIRE : 1; + __IO uint16_t DIRE : 1; + __IO uint16_t CNNIRE : 1; + __IO uint16_t CMPIRE : 1; + __IO uint16_t URIRE : 1; + __IO uint16_t RWKIRE : 1; + __IO uint16_t RETRY : 1; + __IO uint16_t CANCEL : 1; + __IO uint16_t SOFSTEP : 1; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hcnt0_field +{ + __IO uint8_t HOST : 1; + __IO uint8_t URST : 1; + __IO uint8_t SOFIRE : 1; + __IO uint8_t DIRE : 1; + __IO uint8_t CNNIRE : 1; + __IO uint8_t CMPIRE : 1; + __IO uint8_t URIRE : 1; + __IO uint8_t RWKIRE : 1; +} stc_usb_hcnt0_field_t; + +typedef struct stc_usb_hcnt1_field +{ + __IO uint8_t RETRY : 1; + __IO uint8_t CANCEL : 1; + __IO uint8_t SOFSTEP : 1; +} stc_usb_hcnt1_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ : 1; + __IO uint8_t DIRQ : 1; + __IO uint8_t CNNIRQ : 1; + __IO uint8_t CMPIRQ : 1; + __IO uint8_t URIRQ : 1; + __IO uint8_t RWKIRQ : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TCAN : 1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + __IO uint8_t HS0 : 1; + __IO uint8_t HS1 : 1; + __IO uint8_t STUFF : 1; + __IO uint8_t TGERR : 1; + __IO uint8_t CRC : 1; + __IO uint8_t TOUT : 1; + __IO uint8_t RERR : 1; + __IO uint8_t LSTOF : 1; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT : 1; + __IO uint8_t TMODE : 1; + __IO uint8_t SUSP : 1; + __IO uint8_t SOFBUSY : 1; + __IO uint8_t CLKSEL : 1; + __IO uint8_t ALIVE : 1; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + __IO uint8_t FRAMECOMP0 : 1; + __IO uint8_t FRAMECOMP1 : 1; + __IO uint8_t FRAMECOMP2 : 1; + __IO uint8_t FRAMECOMP3 : 1; + __IO uint8_t FRAMECOMP4 : 1; + __IO uint8_t FRAMECOMP5 : 1; + __IO uint8_t FRAMECOMP6 : 1; + __IO uint8_t FRAMECOMP7 : 1; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + __IO uint16_t RTIMER0 : 1; + __IO uint16_t RTIMER1 : 1; + __IO uint16_t RTIMER2 : 1; + __IO uint16_t RTIMER3 : 1; + __IO uint16_t RTIMER4 : 1; + __IO uint16_t RTIMER5 : 1; + __IO uint16_t RTIMER6 : 1; + __IO uint16_t RTIMER7 : 1; + __IO uint16_t RTIMER8 : 1; + __IO uint16_t RTIMER9 : 1; + __IO uint16_t RTIMER10 : 1; + __IO uint16_t RTIMER11 : 1; + __IO uint16_t RTIMER12 : 1; + __IO uint16_t RTIMER13 : 1; + __IO uint16_t RTIMER14 : 1; + __IO uint16_t RTIMER15 : 1; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer0_field +{ + __IO uint8_t RTIMER00 : 1; + __IO uint8_t RTIMER01 : 1; + __IO uint8_t RTIMER02 : 1; + __IO uint8_t RTIMER03 : 1; + __IO uint8_t RTIMER04 : 1; + __IO uint8_t RTIMER05 : 1; + __IO uint8_t RTIMER06 : 1; + __IO uint8_t RTIMER07 : 1; +} stc_usb_hrtimer0_field_t; + +typedef struct stc_usb_hrtimer1_field +{ + __IO uint8_t RTIMER10 : 1; + __IO uint8_t RTIMER11 : 1; + __IO uint8_t RTIMER12 : 1; + __IO uint8_t RTIMER13 : 1; + __IO uint8_t RTIMER14 : 1; + __IO uint8_t RTIMER15 : 1; + __IO uint8_t RTIMER16 : 1; + __IO uint8_t RTIMER17 : 1; +} stc_usb_hrtimer1_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + __IO uint8_t RTIMER20 : 1; + __IO uint8_t RTIMER21 : 1; + __IO uint8_t RTIMER22 : 1; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + __IO uint8_t ADDRESS0 : 1; + __IO uint8_t ADDRESS1 : 1; + __IO uint8_t ADDRESS2 : 1; + __IO uint8_t ADDRESS3 : 1; + __IO uint8_t ADDRESS4 : 1; + __IO uint8_t ADDRESS5 : 1; + __IO uint8_t ADDRESS6 : 1; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + __IO uint16_t EOF0 : 1; + __IO uint16_t EOF1 : 1; + __IO uint16_t EOF2 : 1; + __IO uint16_t EOF3 : 1; + __IO uint16_t EOF4 : 1; + __IO uint16_t EOF5 : 1; + __IO uint16_t EOF6 : 1; + __IO uint16_t EOF7 : 1; + __IO uint16_t EOF8 : 1; + __IO uint16_t EOF9 : 1; + __IO uint16_t EOF10 : 1; + __IO uint16_t EOF11 : 1; + __IO uint16_t EOF12 : 1; + __IO uint16_t EOF13 : 1; + __IO uint16_t EOF14 : 1; + __IO uint16_t EOF15 : 1; +} stc_usb_heof_field_t; + +typedef struct stc_usb_heof0_field +{ + __IO uint8_t EOF00 : 1; + __IO uint8_t EOF01 : 1; + __IO uint8_t EOF02 : 1; + __IO uint8_t EOF03 : 1; + __IO uint8_t EOF04 : 1; + __IO uint8_t EOF05 : 1; + __IO uint8_t EOF06 : 1; + __IO uint8_t EOF07 : 1; +} stc_usb_heof0_field_t; + +typedef struct stc_usb_heof1_field +{ + __IO uint8_t EOF10 : 1; + __IO uint8_t EOF11 : 1; + __IO uint8_t EOF12 : 1; + __IO uint8_t EOF13 : 1; + __IO uint8_t EOF14 : 1; + __IO uint8_t EOF15 : 1; +} stc_usb_heof1_field_t; + +typedef struct stc_usb_hframe_field +{ + __IO uint16_t FRAME0 : 1; + __IO uint16_t FRAME1 : 1; + __IO uint16_t FRAME2 : 1; + __IO uint16_t FRAME3 : 1; + __IO uint16_t FRAME4 : 1; + __IO uint16_t FRAME5 : 1; + __IO uint16_t FRAME6 : 1; + __IO uint16_t FRAME7 : 1; + __IO uint16_t FRAME8 : 1; + __IO uint16_t FRAME9 : 1; + __IO uint16_t FRAME10 : 1; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_hframe0_field +{ + __IO uint8_t FRAME00 : 1; + __IO uint8_t FRAME01 : 1; + __IO uint8_t FRAME02 : 1; + __IO uint8_t FRAME03 : 1; + __IO uint8_t FRAME04 : 1; + __IO uint8_t FRAME05 : 1; + __IO uint8_t FRAME06 : 1; + __IO uint8_t FRAME07 : 1; +} stc_usb_hframe0_field_t; + +typedef struct stc_usb_hframe1_field +{ + __IO uint8_t FRAME10 : 1; + __IO uint8_t FRAME11 : 1; + __IO uint8_t FRAME12 : 1; + __IO uint8_t FRAME13 : 1; +} stc_usb_hframe1_field_t; + +typedef struct stc_usb_htoken_field +{ + __IO uint8_t ENDPT0 : 1; + __IO uint8_t ENDPT1 : 1; + __IO uint8_t ENDPT2 : 1; + __IO uint8_t ENDPT3 : 1; + __IO uint8_t TKNEN0 : 1; + __IO uint8_t TKNEN1 : 1; + __IO uint8_t TKNEN2 : 1; + __IO uint8_t TGGL : 1; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC : 1; + __IO uint16_t RFBK : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t STALCLREN : 1; + __IO uint16_t USTP : 1; + __IO uint16_t HCONX : 1; + __IO uint16_t RESUM : 1; + __IO uint16_t RST : 1; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + __IO uint16_t PKS00 : 1; + __IO uint16_t PKS01 : 1; + __IO uint16_t PKS02 : 1; + __IO uint16_t PKS03 : 1; + __IO uint16_t PKS04 : 1; + __IO uint16_t PKS05 : 1; + __IO uint16_t PKS06 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + __IO uint16_t PKS10 : 1; + __IO uint16_t PKS11 : 1; + __IO uint16_t PKS12 : 1; + __IO uint16_t PKS13 : 1; + __IO uint16_t PKS14 : 1; + __IO uint16_t PKS15 : 1; + __IO uint16_t PKS16 : 1; + __IO uint16_t PKS17 : 1; + __IO uint16_t PKS18 : 1; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + __IO uint16_t PKS20 : 1; + __IO uint16_t PKS21 : 1; + __IO uint16_t PKS22 : 1; + __IO uint16_t PKS23 : 1; + __IO uint16_t PKS24 : 1; + __IO uint16_t PKS25 : 1; + __IO uint16_t PKS26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + __IO uint16_t PKS30 : 1; + __IO uint16_t PKS31 : 1; + __IO uint16_t PKS32 : 1; + __IO uint16_t PKS33 : 1; + __IO uint16_t PKS34 : 1; + __IO uint16_t PKS35 : 1; + __IO uint16_t PKS36 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + __IO uint16_t PKS40 : 1; + __IO uint16_t PKS41 : 1; + __IO uint16_t PKS42 : 1; + __IO uint16_t PKS43 : 1; + __IO uint16_t PKS44 : 1; + __IO uint16_t PKS45 : 1; + __IO uint16_t PKS46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + __IO uint16_t PKS50 : 1; + __IO uint16_t PKS51 : 1; + __IO uint16_t PKS52 : 1; + __IO uint16_t PKS53 : 1; + __IO uint16_t PKS54 : 1; + __IO uint16_t PKS55 : 1; + __IO uint16_t PKS56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + __IO uint16_t TMSP0 : 1; + __IO uint16_t TMSP1 : 1; + __IO uint16_t TMSP2 : 1; + __IO uint16_t TMSP3 : 1; + __IO uint16_t TMSP4 : 1; + __IO uint16_t TMSP5 : 1; + __IO uint16_t TMSP6 : 1; + __IO uint16_t TMSP7 : 1; + __IO uint16_t TMSP8 : 1; + __IO uint16_t TMSP9 : 1; + __IO uint16_t TMSP10 : 1; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF : 1; + __IO uint8_t SETP : 1; + __IO uint8_t WKUP : 1; + __IO uint8_t BRST : 1; + __IO uint8_t SOF : 1; + __IO uint8_t SUSP : 1; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE : 1; + __IO uint8_t CONFN : 1; + __IO uint8_t WKUPIE : 1; + __IO uint8_t BRSTIE : 1; + __IO uint8_t SOFIE : 1; + __IO uint8_t SUSPIE : 1; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + uint16_t RESERVED1 : 10; + __IO uint16_t DRQI : 1; + uint16_t RESERVED2 : 3; + __IO uint16_t DRQIIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + __IO uint16_t SIZE0 : 1; + __IO uint16_t SIZE1 : 1; + __IO uint16_t SIZE2 : 1; + __IO uint16_t SIZE3 : 1; + __IO uint16_t SIZE4 : 1; + __IO uint16_t SIZE5 : 1; + __IO uint16_t SIZE6 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQO : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQOIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + __IO uint16_t SIZE10 : 1; + __IO uint16_t SIZE11 : 1; + __IO uint16_t SIZE12 : 1; + __IO uint16_t SIZE13 : 1; + __IO uint16_t SIZE14 : 1; + __IO uint16_t SIZE15 : 1; + __IO uint16_t SIZE16 : 1; + __IO uint16_t SIZE17 : 1; + __IO uint16_t SIZE18 : 1; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + __IO uint16_t SIZE20 : 1; + __IO uint16_t SIZE21 : 1; + __IO uint16_t SIZE22 : 1; + __IO uint16_t SIZE23 : 1; + __IO uint16_t SIZE24 : 1; + __IO uint16_t SIZE25 : 1; + __IO uint16_t SIZE26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep4s_field +{ + __IO uint16_t SIZE40 : 1; + __IO uint16_t SIZE41 : 1; + __IO uint16_t SIZE42 : 1; + __IO uint16_t SIZE43 : 1; + __IO uint16_t SIZE44 : 1; + __IO uint16_t SIZE45 : 1; + __IO uint16_t SIZE46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + __IO uint16_t SIZE50 : 1; + __IO uint16_t SIZE51 : 1; + __IO uint16_t SIZE52 : 1; + __IO uint16_t SIZE53 : 1; + __IO uint16_t SIZE54 : 1; + __IO uint16_t SIZE55 : 1; + __IO uint16_t SIZE56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep5s_field_t; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMAC_MODULE register bit fields */ +typedef struct stc_dmac_dmacr_field +{ + uint32_t RESERVED1 : 24; + __IO uint32_t DH0 : 1; + __IO uint32_t DH1 : 1; + __IO uint32_t DH2 : 1; + __IO uint32_t DH3 : 1; + __IO uint32_t PR : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t DS : 1; + __IO uint32_t DE : 1; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + __IO uint32_t TC : 16; + __IO uint32_t BC : 4; + uint32_t RESERVED1 : 3; + __IO uint32_t IS : 6; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS : 3; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW : 2; + __IO uint32_t MS : 2; +} stc_dmac_dmacb7_field_t; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN_MODULE register bit fields */ +typedef struct stc_can_ctrlr_field +{ + __IO uint16_t INIT : 1; + __IO uint16_t IE : 1; + __IO uint16_t SIE : 1; + __IO uint16_t EIE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t DAR : 1; + __IO uint16_t CCE : 1; + __IO uint16_t TEST : 1; +} stc_can_ctrlr_field_t; + +typedef struct stc_can_statr_field +{ + __IO uint16_t LEC : 3; + __IO uint16_t TXOK : 1; + __IO uint16_t RXOK : 1; + __IO uint16_t EPASS : 1; + __IO uint16_t EWARN : 1; + __IO uint16_t BOFF : 1; +} stc_can_statr_field_t; + +typedef struct stc_can_errcnt_field +{ + __IO uint16_t TEC0 : 1; + __IO uint16_t TEC1 : 1; + __IO uint16_t TEC2 : 1; + __IO uint16_t TEC3 : 1; + __IO uint16_t TEC4 : 1; + __IO uint16_t TEC5 : 1; + __IO uint16_t TEC6 : 1; + __IO uint16_t TEC7 : 1; + __IO uint16_t REC0 : 1; + __IO uint16_t REC1 : 1; + __IO uint16_t REC2 : 1; + __IO uint16_t REC3 : 1; + __IO uint16_t REC4 : 1; + __IO uint16_t REC5 : 1; + __IO uint16_t REC6 : 1; + __IO uint16_t RP : 1; +} stc_can_errcnt_field_t; + +typedef struct stc_can_btr_field +{ + __IO uint16_t BRP : 6; + __IO uint16_t SJW : 2; + __IO uint16_t TSEG1 : 4; + __IO uint16_t TSEG2 : 3; +} stc_can_btr_field_t; + +typedef struct stc_can_intr_field +{ + __IO uint16_t INTID0 : 1; + __IO uint16_t INTID1 : 1; + __IO uint16_t INTID2 : 1; + __IO uint16_t INTID3 : 1; + __IO uint16_t INTID4 : 1; + __IO uint16_t INTID5 : 1; + __IO uint16_t INTID6 : 1; + __IO uint16_t INTID7 : 1; + __IO uint16_t INTID8 : 1; + __IO uint16_t INTID9 : 1; + __IO uint16_t INTID10 : 1; + __IO uint16_t INTID11 : 1; + __IO uint16_t INTID12 : 1; + __IO uint16_t INTID13 : 1; + __IO uint16_t INTID14 : 1; + __IO uint16_t INTID15 : 1; +} stc_can_intr_field_t; + +typedef struct stc_can_testr_field +{ + uint16_t RESERVED1 : 2; + __IO uint16_t BASIC : 1; + __IO uint16_t SILENT : 1; + __IO uint16_t LBACK : 1; + __IO uint16_t TX0 : 1; + __IO uint16_t TX1 : 1; + __IO uint16_t RX : 1; +} stc_can_testr_field_t; + +typedef struct stc_can_brper_field +{ + __IO uint16_t BRPE0 : 1; + __IO uint16_t BRPE1 : 1; + __IO uint16_t BRPE2 : 1; + __IO uint16_t BRPE3 : 1; +} stc_can_brper_field_t; + +typedef struct stc_can_if1creq_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t BUSY : 1; +} stc_can_if1creq_field_t; + +typedef struct stc_can_if1cmsk_field +{ + __IO uint16_t DATAB : 1; + __IO uint16_t DATAA : 1; + __IO uint16_t NEWDAT : 1; + __IO uint16_t CIP : 1; + __IO uint16_t CONTROL : 1; + __IO uint16_t ARB : 1; + __IO uint16_t MASK : 1; + __IO uint16_t WRRD : 1; +} stc_can_if1cmsk_field_t; + +typedef struct stc_can_if1msk_field +{ + __IO uint32_t MSK : 29; + uint32_t RESERVED1 : 1; + __IO uint32_t MDIR : 1; + __IO uint32_t MXTD : 1; +} stc_can_if1msk_field_t; + +typedef struct stc_can_if1msk2_field +{ + uint16_t RESERVED1 : 14; + __IO uint16_t MDIR : 1; + __IO uint16_t MXTD : 1; +} stc_can_if1msk2_field_t; + +typedef struct stc_can_if1arb_field +{ + __IO uint32_t ID : 29; + __IO uint32_t DIR : 1; + __IO uint32_t XTD : 1; + __IO uint32_t MSGVAL : 1; +} stc_can_if1arb_field_t; + +typedef struct stc_can_if1arb2_field +{ + uint16_t RESERVED1 : 13; + __IO uint16_t DIR : 1; + __IO uint16_t XTD : 1; + __IO uint16_t MSGVAL : 1; +} stc_can_if1arb2_field_t; + +typedef struct stc_can_if1mctr_field +{ + __IO uint16_t DLC : 4; + uint16_t RESERVED1 : 3; + __IO uint16_t EOB : 1; + __IO uint16_t TXRQST : 1; + __IO uint16_t RMTEN : 1; + __IO uint16_t RXIE : 1; + __IO uint16_t TXIE : 1; + __IO uint16_t UMASK : 1; + __IO uint16_t INTPND : 1; + __IO uint16_t MSGLST : 1; + __IO uint16_t NEWDAT : 1; +} stc_can_if1mctr_field_t; + +typedef struct stc_can_if2creq_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t BUSY : 1; +} stc_can_if2creq_field_t; + +typedef struct stc_can_if2cmsk_field +{ + __IO uint16_t DATAB : 1; + __IO uint16_t DATAA : 1; + __IO uint16_t NEWDAT : 1; + __IO uint16_t CIP : 1; + __IO uint16_t CONTROL : 1; + __IO uint16_t ARB : 1; + __IO uint16_t MASK : 1; + __IO uint16_t WRRD : 1; +} stc_can_if2cmsk_field_t; + +typedef struct stc_can_if2msk_field +{ + uint32_t RESERVED1 : 30; + __IO uint32_t MDIR : 1; + __IO uint32_t MXTD : 1; +} stc_can_if2msk_field_t; + +typedef struct stc_can_if2msk2_field +{ + uint16_t RESERVED1 : 14; + __IO uint16_t MDIR : 1; + __IO uint16_t MXTD : 1; +} stc_can_if2msk2_field_t; + +typedef struct stc_can_if2arb2_field +{ + uint16_t RESERVED1 : 13; + __IO uint16_t DIR : 1; + __IO uint16_t XTD : 1; + __IO uint16_t MSGVAL : 1; +} stc_can_if2arb2_field_t; + +typedef struct stc_can_if2mctr_field +{ + __IO uint16_t DLC : 4; + uint16_t RESERVED1 : 3; + __IO uint16_t EOB : 1; + __IO uint16_t TXRQST : 1; + __IO uint16_t RMTEN : 1; + __IO uint16_t RXIE : 1; + __IO uint16_t TXIE : 1; + __IO uint16_t UMASK : 1; + __IO uint16_t INTPND : 1; + __IO uint16_t MSGLST : 1; + __IO uint16_t NEWDAT : 1; +} stc_can_if2mctr_field_t; + +typedef struct stc_can_treqr_field +{ + __IO uint32_t TXRQST1 : 1; + __IO uint32_t TXRQST2 : 1; + __IO uint32_t TXRQST3 : 1; + __IO uint32_t TXRQST4 : 1; + __IO uint32_t TXRQST5 : 1; + __IO uint32_t TXRQST6 : 1; + __IO uint32_t TXRQST7 : 1; + __IO uint32_t TXRQST8 : 1; + __IO uint32_t TXRQST9 : 1; + __IO uint32_t TXRQST10 : 1; + __IO uint32_t TXRQST11 : 1; + __IO uint32_t TXRQST12 : 1; + __IO uint32_t TXRQST13 : 1; + __IO uint32_t TXRQST14 : 1; + __IO uint32_t TXRQST15 : 1; + __IO uint32_t TXRQST16 : 1; + __IO uint32_t TXRQST17 : 1; + __IO uint32_t TXRQST18 : 1; + __IO uint32_t TXRQST19 : 1; + __IO uint32_t TXRQST20 : 1; + __IO uint32_t TXRQST21 : 1; + __IO uint32_t TXRQST22 : 1; + __IO uint32_t TXRQST23 : 1; + __IO uint32_t TXRQST24 : 1; + __IO uint32_t TXRQST25 : 1; + __IO uint32_t TXRQST26 : 1; + __IO uint32_t TXRQST27 : 1; + __IO uint32_t TXRQST28 : 1; + __IO uint32_t TXRQST29 : 1; + __IO uint32_t TXRQST30 : 1; + __IO uint32_t TXRQST31 : 1; + __IO uint32_t TXRQST32 : 1; +} stc_can_treqr_field_t; + +typedef struct stc_can_treqr1_field +{ + __IO uint16_t TXRQST1 : 1; + __IO uint16_t TXRQST2 : 1; + __IO uint16_t TXRQST3 : 1; + __IO uint16_t TXRQST4 : 1; + __IO uint16_t TXRQST5 : 1; + __IO uint16_t TXRQST6 : 1; + __IO uint16_t TXRQST7 : 1; + __IO uint16_t TXRQST8 : 1; + __IO uint16_t TXRQST9 : 1; + __IO uint16_t TXRQST10 : 1; + __IO uint16_t TXRQST11 : 1; + __IO uint16_t TXRQST12 : 1; + __IO uint16_t TXRQST13 : 1; + __IO uint16_t TXRQST14 : 1; + __IO uint16_t TXRQST15 : 1; + __IO uint16_t TXRQST16 : 1; +} stc_can_treqr1_field_t; + +typedef struct stc_can_treqr2_field +{ + __IO uint16_t TXRQST17 : 1; + __IO uint16_t TXRQST18 : 1; + __IO uint16_t TXRQST19 : 1; + __IO uint16_t TXRQST20 : 1; + __IO uint16_t TXRQST21 : 1; + __IO uint16_t TXRQST22 : 1; + __IO uint16_t TXRQST23 : 1; + __IO uint16_t TXRQST24 : 1; + __IO uint16_t TXRQST25 : 1; + __IO uint16_t TXRQST26 : 1; + __IO uint16_t TXRQST27 : 1; + __IO uint16_t TXRQST28 : 1; + __IO uint16_t TXRQST29 : 1; + __IO uint16_t TXRQST30 : 1; + __IO uint16_t TXRQST31 : 1; + __IO uint16_t TXRQST32 : 1; +} stc_can_treqr2_field_t; + +typedef struct stc_can_newdt_field +{ + __IO uint32_t NEWDAT1 : 1; + __IO uint32_t NEWDAT2 : 1; + __IO uint32_t NEWDAT3 : 1; + __IO uint32_t NEWDAT4 : 1; + __IO uint32_t NEWDAT5 : 1; + __IO uint32_t NEWDAT6 : 1; + __IO uint32_t NEWDAT7 : 1; + __IO uint32_t NEWDAT8 : 1; + __IO uint32_t NEWDAT9 : 1; + __IO uint32_t NEWDAT10 : 1; + __IO uint32_t NEWDAT11 : 1; + __IO uint32_t NEWDAT12 : 1; + __IO uint32_t NEWDAT13 : 1; + __IO uint32_t NEWDAT14 : 1; + __IO uint32_t NEWDAT15 : 1; + __IO uint32_t NEWDAT16 : 1; + __IO uint32_t NEWDAT17 : 1; + __IO uint32_t NEWDAT18 : 1; + __IO uint32_t NEWDAT19 : 1; + __IO uint32_t NEWDAT20 : 1; + __IO uint32_t NEWDAT21 : 1; + __IO uint32_t NEWDAT22 : 1; + __IO uint32_t NEWDAT23 : 1; + __IO uint32_t NEWDAT24 : 1; + __IO uint32_t NEWDAT25 : 1; + __IO uint32_t NEWDAT26 : 1; + __IO uint32_t NEWDAT27 : 1; + __IO uint32_t NEWDAT28 : 1; + __IO uint32_t NEWDAT29 : 1; + __IO uint32_t NEWDAT30 : 1; + __IO uint32_t NEWDAT31 : 1; + __IO uint32_t NEWDAT32 : 1; +} stc_can_newdt_field_t; + +typedef struct stc_can_newdt1_field +{ + __IO uint16_t NEWDAT1 : 1; + __IO uint16_t NEWDAT2 : 1; + __IO uint16_t NEWDAT3 : 1; + __IO uint16_t NEWDAT4 : 1; + __IO uint16_t NEWDAT5 : 1; + __IO uint16_t NEWDAT6 : 1; + __IO uint16_t NEWDAT7 : 1; + __IO uint16_t NEWDAT8 : 1; + __IO uint16_t NEWDAT9 : 1; + __IO uint16_t NEWDAT10 : 1; + __IO uint16_t NEWDAT11 : 1; + __IO uint16_t NEWDAT12 : 1; + __IO uint16_t NEWDAT13 : 1; + __IO uint16_t NEWDAT14 : 1; + __IO uint16_t NEWDAT15 : 1; + __IO uint16_t NEWDAT16 : 1; +} stc_can_newdt1_field_t; + +typedef struct stc_can_intpnd_field +{ + __IO uint32_t INTPND1 : 1; + __IO uint32_t INTPND2 : 1; + __IO uint32_t INTPND3 : 1; + __IO uint32_t INTPND4 : 1; + __IO uint32_t INTPND5 : 1; + __IO uint32_t INTPND6 : 1; + __IO uint32_t INTPND7 : 1; + __IO uint32_t INTPND8 : 1; + __IO uint32_t INTPND9 : 1; + __IO uint32_t INTPND10 : 1; + __IO uint32_t INTPND11 : 1; + __IO uint32_t INTPND12 : 1; + __IO uint32_t INTPND13 : 1; + __IO uint32_t INTPND14 : 1; + __IO uint32_t INTPND15 : 1; + __IO uint32_t INTPND16 : 1; + __IO uint32_t INTPND17 : 1; + __IO uint32_t INTPND18 : 1; + __IO uint32_t INTPND19 : 1; + __IO uint32_t INTPND20 : 1; + __IO uint32_t INTPND21 : 1; + __IO uint32_t INTPND22 : 1; + __IO uint32_t INTPND23 : 1; + __IO uint32_t INTPND24 : 1; + __IO uint32_t INTPND25 : 1; + __IO uint32_t INTPND26 : 1; + __IO uint32_t INTPND27 : 1; + __IO uint32_t INTPND28 : 1; + __IO uint32_t INTPND29 : 1; + __IO uint32_t INTPND30 : 1; + __IO uint32_t INTPND31 : 1; + __IO uint32_t INTPND32 : 1; +} stc_can_intpnd_field_t; + +typedef struct stc_can_intpnd1_field +{ + __IO uint16_t INTPND1 : 1; + __IO uint16_t INTPND2 : 1; + __IO uint16_t INTPND3 : 1; + __IO uint16_t INTPND4 : 1; + __IO uint16_t INTPND5 : 1; + __IO uint16_t INTPND6 : 1; + __IO uint16_t INTPND7 : 1; + __IO uint16_t INTPND8 : 1; + __IO uint16_t INTPND9 : 1; + __IO uint16_t INTPND10 : 1; + __IO uint16_t INTPND11 : 1; + __IO uint16_t INTPND12 : 1; + __IO uint16_t INTPND13 : 1; + __IO uint16_t INTPND14 : 1; + __IO uint16_t INTPND15 : 1; + __IO uint16_t INTPND16 : 1; +} stc_can_intpnd1_field_t; + +typedef struct stc_can_intpnd2_field +{ + __IO uint16_t INTPND17 : 1; + __IO uint16_t INTPND18 : 1; + __IO uint16_t INTPND19 : 1; + __IO uint16_t INTPND20 : 1; + __IO uint16_t INTPND21 : 1; + __IO uint16_t INTPND22 : 1; + __IO uint16_t INTPND23 : 1; + __IO uint16_t INTPND24 : 1; + __IO uint16_t INTPND25 : 1; + __IO uint16_t INTPND26 : 1; + __IO uint16_t INTPND27 : 1; + __IO uint16_t INTPND28 : 1; + __IO uint16_t INTPND29 : 1; + __IO uint16_t INTPND30 : 1; + __IO uint16_t INTPND31 : 1; + __IO uint16_t INTPND32 : 1; +} stc_can_intpnd2_field_t; + +typedef struct stc_can_msgval_field +{ + __IO uint32_t MSGVAL1 : 1; + __IO uint32_t MSGVAL2 : 1; + __IO uint32_t MSGVAL3 : 1; + __IO uint32_t MSGVAL4 : 1; + __IO uint32_t MSGVAL5 : 1; + __IO uint32_t MSGVAL6 : 1; + __IO uint32_t MSGVAL7 : 1; + __IO uint32_t MSGVAL8 : 1; + __IO uint32_t MSGVAL9 : 1; + __IO uint32_t MSGVAL10 : 1; + __IO uint32_t MSGVAL11 : 1; + __IO uint32_t MSGVAL12 : 1; + __IO uint32_t MSGVAL13 : 1; + __IO uint32_t MSGVAL14 : 1; + __IO uint32_t MSGVAL15 : 1; + __IO uint32_t MSGVAL16 : 1; + __IO uint32_t MSGVAL17 : 1; + __IO uint32_t MSGVAL18 : 1; + __IO uint32_t MSGVAL19 : 1; + __IO uint32_t MSGVAL20 : 1; + __IO uint32_t MSGVAL21 : 1; + __IO uint32_t MSGVAL22 : 1; + __IO uint32_t MSGVAL23 : 1; + __IO uint32_t MSGVAL24 : 1; + __IO uint32_t MSGVAL25 : 1; + __IO uint32_t MSGVAL26 : 1; + __IO uint32_t MSGVAL27 : 1; + __IO uint32_t MSGVAL28 : 1; + __IO uint32_t MSGVAL29 : 1; + __IO uint32_t MSGVAL30 : 1; + __IO uint32_t MSGVAL31 : 1; + __IO uint32_t MSGVAL32 : 1; +} stc_can_msgval_field_t; + +typedef struct stc_can_msgval1_field +{ + __IO uint16_t MSGVAL1 : 1; + __IO uint16_t MSGVAL2 : 1; + __IO uint16_t MSGVAL3 : 1; + __IO uint16_t MSGVAL4 : 1; + __IO uint16_t MSGVAL5 : 1; + __IO uint16_t MSGVAL6 : 1; + __IO uint16_t MSGVAL7 : 1; + __IO uint16_t MSGVAL8 : 1; + __IO uint16_t MSGVAL9 : 1; + __IO uint16_t MSGVAL10 : 1; + __IO uint16_t MSGVAL11 : 1; + __IO uint16_t MSGVAL12 : 1; + __IO uint16_t MSGVAL13 : 1; + __IO uint16_t MSGVAL14 : 1; + __IO uint16_t MSGVAL15 : 1; + __IO uint16_t MSGVAL16 : 1; +} stc_can_msgval1_field_t; + +typedef struct stc_can_msgval2_field +{ + __IO uint16_t MSGVAL17 : 1; + __IO uint16_t MSGVAL18 : 1; + __IO uint16_t MSGVAL19 : 1; + __IO uint16_t MSGVAL20 : 1; + __IO uint16_t MSGVAL21 : 1; + __IO uint16_t MSGVAL22 : 1; + __IO uint16_t MSGVAL23 : 1; + __IO uint16_t MSGVAL24 : 1; + __IO uint16_t MSGVAL25 : 1; + __IO uint16_t MSGVAL26 : 1; + __IO uint16_t MSGVAL27 : 1; + __IO uint16_t MSGVAL28 : 1; + __IO uint16_t MSGVAL29 : 1; + __IO uint16_t MSGVAL30 : 1; + __IO uint16_t MSGVAL31 : 1; + __IO uint16_t MSGVAL32 : 1; +} stc_can_msgval2_field_t; + +/****************************************************************************** + * SDIF_MODULE + ******************************************************************************/ +/* SDIF_MODULE register bit fields */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/****************************************************************************** + * Peripheral register structures + ******************************************************************************/ + +/****************************************************************************** + * WorkFlash_IF_MODULE + ******************************************************************************/ +/* WorkFlash interface registers */ +typedef struct +{ + union { + __IO uint32_t WFASZR; + stc_workflash_if_wfaszr_field_t WFASZR_f; + }; + union { + __IO uint32_t WFRWTR; + stc_workflash_if_wfrwtr_field_t WFRWTR_f; + }; + union { + __IO uint32_t WFSTR; + stc_workflash_if_wfstr_field_t WFSTR_f; + }; +}FM4_WORKFLASH_IF_TypeDef; + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + }; + uint8_t RESERVED2[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + }; + union { + __IO uint32_t FBFCR; + stc_flash_if_fbfcr_field_t FBFCR_f; + }; + uint8_t RESERVED4[8]; + union { + __IO uint32_t FICR; + stc_flash_if_ficr_field_t FICR_f; + }; + union { + __IO uint32_t FISR; + stc_flash_if_fisr_field_t FISR_f; + }; + union { + __IO uint32_t FICLR; + stc_flash_if_ficlr_field_t FICLR_f; + }; + uint8_t RESERVED7[212]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + }; +}FM4_FLASH_IF_TypeDef; + +/****************************************************************************** + * UNIQUE_ID_MODULE + ******************************************************************************/ +/* Unique ID registers */ +typedef struct +{ + union { + __IO uint32_t UIDR0; + stc_unique_id_uidr0_field_t UIDR0_f; + }; + union { + __IO uint32_t UIDR1; + stc_unique_id_uidr1_field_t UIDR1_f; + }; +}FM4_UNIQUE_ID_TypeDef; + +/****************************************************************************** + * ECC_CAPTURE_MODULE + ******************************************************************************/ +/* ECC Capture address registers */ +typedef struct +{ + union { + __IO uint32_t FERRAD; + stc_ecc_capture_ferrad_field_t FERRAD_f; + }; +}FM4_ECC_CAPTURE_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + union { + __IO uint8_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + }; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + union { + __IO uint16_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + }; + uint8_t RESERVED7[7]; + union { + __IO uint8_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + }; + uint8_t RESERVED8[7]; + union { + __IO uint8_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint16_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint8_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + }; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + union { + __IO uint8_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + }; + uint8_t RESERVED18[11]; + union { + __IO uint8_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + }; + uint8_t RESERVED19[3]; + union { + __IO uint8_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + }; + uint8_t RESERVED20[3]; + union { + __IO uint8_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + }; +}FM4_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + union { + __IO uint8_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + }; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + }; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM4_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + union { + __IO uint8_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + union { + __IO uint8_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + }; + uint8_t RESERVED1[7]; + union { + __IO uint8_t WDOGSPMC; + stc_swwdt_wdogspmc_field_t WDOGSPMC_f; + }; + uint8_t RESERVED2[3047]; + __IO uint32_t WDOGLOCK; +}FM4_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMERXLOAD; + __IO uint32_t TIMERXVALUE; + union { + __IO uint32_t TIMERXCONTROL; + stc_dtim_timerXcontrol_field_t TIMERXCONTROL_f; + }; + __IO uint32_t TIMERXINTCLR; + union { + __IO uint32_t TIMERXRIS; + stc_dtim_timerXris_field_t TIMERXRIS_f; + }; + union { + __IO uint32_t TIMERXMIS; + stc_dtim_timerXmis_field_t TIMERXMIS_f; + }; + __IO uint32_t TIMERXBGLOAD; + uint8_t RESERVED0[4]; +}FM4_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[66]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + }; + union { + __IO uint16_t TCSC0; + stc_mft_frt_tcsc0_field_t TCSC0_f; + }; + uint8_t RESERVED2[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED3[2]; + __IO uint16_t TCDT1; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + }; + union { + __IO uint16_t TCSC1; + stc_mft_frt_tcsc1_field_t TCSC1_f; + }; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT2; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + }; + union { + __IO uint16_t TCSC2; + stc_mft_frt_tcsc2_field_t TCSC2_f; + }; + union { + __IO uint32_t TCAL; + stc_mft_frt_tcal_field_t TCAL_f; + }; +}FM4_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED5[2]; + __IO uint16_t OCCP5; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + union { + __IO uint8_t OCSD10; + stc_mft_ocu_ocsd10_field_t OCSD10_f; + }; + uint8_t RESERVED6; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + union { + __IO uint8_t OCSD32; + stc_mft_ocu_ocsd32_field_t OCSD32_f; + }; + uint8_t RESERVED7; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + union { + __IO uint8_t OCSD54; + stc_mft_ocu_ocsd54_field_t OCSD54_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t OCSE0; + stc_mft_ocu_ocse0_field_t OCSE0_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint32_t OCSE1; + stc_mft_ocu_ocse1_field_t OCSE1_f; + }; + union { + __IO uint16_t OCSE2; + stc_mft_ocu_ocse2_field_t OCSE2_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint32_t OCSE3; + stc_mft_ocu_ocse3_field_t OCSE3_f; + }; + union { + __IO uint16_t OCSE4; + stc_mft_ocu_ocse4_field_t OCSE4_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint32_t OCSE5; + stc_mft_ocu_ocse5_field_t OCSE5_f; + }; + uint8_t RESERVED13[40]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +}FM4_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[142]; + __IO uint16_t WFTF10; + __IO uint16_t WFTA10; + __IO uint16_t WFTB10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTF32; + __IO uint16_t WFTA32; + __IO uint16_t WFTB32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTF54; + __IO uint16_t WFTA54; + __IO uint16_t WFTB54; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + }; +}FM4_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[108]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + uint8_t RESERVED1[8]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +}FM4_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[112]; + union { + __IO uint8_t ACFS10; + stc_mft_adcmp_acfs10_field_t ACFS10_f; + }; + union { + __IO uint8_t ACFS32; + stc_mft_adcmp_acfs32_field_t ACFS32_f; + }; + union { + __IO uint8_t ACFS54; + stc_mft_adcmp_acfs54_field_t ACFS54_f; + }; + uint8_t RESERVED1[71]; + __IO uint16_t ACMP0; + uint8_t RESERVED2[2]; + __IO uint16_t ACMP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACMP2; + uint8_t RESERVED4[2]; + __IO uint16_t ACMP3; + uint8_t RESERVED5[2]; + __IO uint16_t ACMP4; + uint8_t RESERVED6[2]; + __IO uint16_t ACMP5; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint8_t ACSC0; + stc_mft_adcmp_acsc_field_t ACSC0_f; + }; + union { + __IO uint8_t ACSD0; + stc_mft_adcmp_acsd_field_t ACSD0_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint8_t ACSC1; + stc_mft_adcmp_acsc_field_t ACSC1_f; + }; + union { + __IO uint8_t ACSD1; + stc_mft_adcmp_acsd_field_t ACSD1_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint8_t ACSC2; + stc_mft_adcmp_acsc_field_t ACSC2_f; + }; + union { + __IO uint8_t ACSD2; + stc_mft_adcmp_acsd_field_t ACSD2_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint8_t ACSC3; + stc_mft_adcmp_acsc_field_t ACSC3_f; + }; + union { + __IO uint8_t ACSD3; + stc_mft_adcmp_acsd_field_t ACSD3_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint8_t ACSC4; + stc_mft_adcmp_acsc_field_t ACSC4_f; + }; + union { + __IO uint8_t ACSD4; + stc_mft_adcmp_acsd_field_t ACSD4_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint8_t ACSC5; + stc_mft_adcmp_acsc_field_t ACSC5_f; + }; + union { + __IO uint8_t ACSD5; + stc_mft_adcmp_acsd_field_t ACSD5_f; + }; + uint8_t RESERVED13[2]; +}FM4_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + uint8_t RESERVED1[2]; + __IO uint8_t TSTPR0; + uint8_t RESERVED3[4]; + __IO uint8_t COMP0; + uint8_t RESERVED4[2]; + __IO uint8_t COMP2; + uint8_t RESERVED5[4]; + __IO uint8_t COMP4; + uint8_t RESERVED6[2]; + __IO uint8_t COMP6; + uint8_t RESERVED7[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + uint8_t RESERVED8[2]; + __IO uint8_t TSTPR1; + uint8_t RESERVED9[4]; + __IO uint8_t COMP1; + uint8_t RESERVED10[2]; + __IO uint8_t COMP3; + uint8_t RESERVED11[4]; + __IO uint8_t COMP5; + uint8_t RESERVED12[2]; + __IO uint8_t COMP7; + uint8_t RESERVED13[12]; + union { + __IO uint8_t TTCR2; + stc_mft_ppg_ttcr2_field_t TTCR2_f; + }; + uint8_t RESERVED14[2]; + __IO uint8_t TSTPR2; + uint8_t RESERVED15[4]; + __IO uint8_t COMP8; + uint8_t RESERVED16[2]; + __IO uint8_t COMP10; + uint8_t RESERVED17[4]; + __IO uint8_t COMP12; + uint8_t RESERVED18[2]; + __IO uint8_t COMP14; + uint8_t RESERVED19[171]; + union { + __IO uint16_t TRG0; + stc_mft_ppg_trg0_field_t TRG0_f; + }; + uint8_t RESERVED20[2]; + union { + __IO uint16_t REVC0; + stc_mft_ppg_revc0_field_t REVC0_f; + }; + uint8_t RESERVED21[58]; + union { + __IO uint16_t TRG1; + stc_mft_ppg_trg1_field_t TRG1_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t REVC1; + stc_mft_ppg_revc1_field_t REVC1_f; + }; + uint8_t RESERVED23[186]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + uint8_t RESERVED24[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + uint8_t RESERVED30[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + uint8_t RESERVED31[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + uint8_t RESERVED32[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED33[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED34[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + uint8_t RESERVED37[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + uint8_t RESERVED38[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + uint8_t RESERVED39[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED40[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED41[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED42[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED43[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + uint8_t RESERVED44[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + uint8_t RESERVED45[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + uint8_t RESERVED46[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED47[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED48[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED49[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED50[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; + uint8_t RESERVED51[39]; + union { + __IO uint8_t PPGC17; + stc_mft_ppg_ppgc17_field_t PPGC17_f; + }; + union { + __IO uint8_t PPGC16; + stc_mft_ppg_ppgc16_field_t PPGC16_f; + }; + uint8_t RESERVED52[2]; + union { + __IO uint8_t PPGC19; + stc_mft_ppg_ppgc19_field_t PPGC19_f; + }; + union { + __IO uint8_t PPGC18; + stc_mft_ppg_ppgc18_field_t PPGC18_f; + }; + uint8_t RESERVED53[2]; + union { + __IO uint16_t PRL16; + struct { + __IO uint8_t PRLL16; + __IO uint8_t PRLH16; + }; + }; + uint8_t RESERVED54[2]; + union { + __IO uint16_t PRL17; + struct { + __IO uint8_t PRLL17; + __IO uint8_t PRLH17; + }; + }; + uint8_t RESERVED55[2]; + union { + __IO uint16_t PRL18; + struct { + __IO uint8_t PRLL18; + __IO uint8_t PRLH18; + }; + }; + uint8_t RESERVED56[2]; + union { + __IO uint16_t PRL19; + struct { + __IO uint8_t PRLL19; + __IO uint8_t PRLH19; + }; + }; + uint8_t RESERVED57[2]; + union { + __IO uint8_t GATEC16; + stc_mft_ppg_gatec16_field_t GATEC16_f; + }; + uint8_t RESERVED58[39]; + union { + __IO uint8_t PPGC21; + stc_mft_ppg_ppgc21_field_t PPGC21_f; + }; + union { + __IO uint8_t PPGC20; + stc_mft_ppg_ppgc20_field_t PPGC20_f; + }; + uint8_t RESERVED59[2]; + union { + __IO uint8_t PPGC23; + stc_mft_ppg_ppgc23_field_t PPGC23_f; + }; + union { + __IO uint8_t PPGC22; + stc_mft_ppg_ppgc22_field_t PPGC22_f; + }; + uint8_t RESERVED60[2]; + union { + __IO uint16_t PRL20; + struct { + __IO uint8_t PRLL20; + __IO uint8_t PRLH20; + }; + }; + uint8_t RESERVED61[2]; + union { + __IO uint16_t PRL21; + struct { + __IO uint8_t PRLL21; + __IO uint8_t PRLH21; + }; + }; + uint8_t RESERVED62[2]; + union { + __IO uint16_t PRL22; + struct { + __IO uint8_t PRLL22; + __IO uint8_t PRLH22; + }; + }; + uint8_t RESERVED63[2]; + union { + __IO uint16_t PRL23; + struct { + __IO uint8_t PRLL23; + __IO uint8_t PRLH23; + }; + }; + uint8_t RESERVED64[2]; + union { + __IO uint8_t GATEC20; + stc_mft_ppg_gatec20_field_t GATEC20_f; + }; + uint8_t RESERVED65[39]; + __IO uint8_t IGBTC; + uint8_t RESERVED66[39]; +}FM4_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +}FM4_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +}FM4_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +}FM4_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +}FM4_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +}FM4_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +}FM4_BTIOSEL47_TypeDef; + +/****************************************************************************** + * BTIOSEL8B_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 8 - channel 11 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL89AB; + stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; + }; +}FM4_BTIOSEL8B_TypeDef; + +/****************************************************************************** + * BTIOSELCF_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 12 - channel 15 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSELCDEF; + stc_btioselcf_btselcdef_field_t BTSELCDEF_f; + }; +}FM4_BTIOSELCF_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + }; +}FM4_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t QICR; + stc_qprc_qicr_field_t QICR_f; + }; + struct { + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + }; + struct { + union { + __IO uint8_t QCRL; + stc_qprc_qcrl_field_t QCRL_f; + }; + union { + __IO uint8_t QCRH; + stc_qprc_qcrh_field_t QCRH_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + }; +}FM4_QPRC_TypeDef; + +/****************************************************************************** + * QPRC_NF_MODULE + ******************************************************************************/ +/* Quad position and revolution counter noise filter registers */ +typedef struct +{ + union { + __IO uint8_t NFCTLA; + stc_qprc_nf_nfctla_field_t NFCTLA_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t NFCTLB; + stc_qprc_nf_nfctlb_field_t NFCTLB_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t NFRCTLZ; + stc_qprc_nf_nfrctlz_field_t NFRCTLZ_f; + }; + uint8_t RESERVED2[7]; +}FM4_QPRC_NF_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + }; + struct { + union { + __IO uint16_t SCFDL; + stc_adc_scfdl_field_t SCFDL_f; + }; + union { + __IO uint16_t SCFDH; + stc_adc_scfdh_field_t SCFDH_f; + }; + }; + }; + union { + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + }; + struct { + union { + __IO uint8_t SCIS2; + stc_adc_scis2_field_t SCIS2_f; + }; + union { + __IO uint8_t SCIS3; + stc_adc_scis3_field_t SCIS3_f; + }; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + }; + struct { + union { + __IO uint8_t SCIS0; + stc_adc_scis0_field_t SCIS0_f; + }; + union { + __IO uint8_t SCIS1; + stc_adc_scis1_field_t SCIS1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + }; + struct { + union { + __IO uint16_t PCFDL; + stc_adc_pcfdl_field_t PCFDL_f; + }; + union { + __IO uint16_t PCFDH; + stc_adc_pcfdh_field_t PCFDH_f; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + uint8_t RESERVED6; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + }; + union { + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + }; + struct { + union { + __IO uint8_t ADSS2; + stc_adc_adss2_field_t ADSS2_f; + }; + union { + __IO uint8_t ADSS3; + stc_adc_adss3_field_t ADSS3_f; + }; + }; + }; + uint8_t RESERVED7[2]; + union { + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + }; + struct { + union { + __IO uint8_t ADSS0; + stc_adc_adss0_field_t ADSS0_f; + }; + union { + __IO uint8_t ADSS1; + stc_adc_adss1_field_t ADSS1_f; + }; + }; + }; + uint8_t RESERVED8[2]; + union { + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + }; + struct { + union { + __IO uint8_t ADST1; + stc_adc_adst1_field_t ADST1_f; + }; + union { + __IO uint8_t ADST0; + stc_adc_adst0_field_t ADST0_f; + }; + }; + }; + uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + }; + uint8_t RESERVED12[2]; + uint32_t OFFESET; + union { + __IO uint8_t WCMRCOT; + stc_adc_wcmrcot_field_t WCMRCOT_f; + }; + uint8_t RESERVED13[3]; + union { + __IO uint8_t WCMRCIF; + stc_adc_wcmrcif_field_t WCMRCIF_f; + }; + uint8_t RESERVED14[3]; + union { + __IO uint8_t WCMPCR; + stc_adc_wcmpcr_field_t WCMPCR_f; + }; + union { + __IO uint8_t WCMPSR; + stc_adc_wcmpsr_field_t WCMPSR_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint16_t WCMPDL; + stc_adc_wcmpdl_field_t WCMPDL_f; + }; + union { + __IO uint16_t WCMPDH; + stc_adc_wcmpdh_field_t WCMPDH_f; + }; +}FM4_ADC_TypeDef; + +/****************************************************************************** + * DAC_MODULE + ******************************************************************************/ + +typedef struct +{ + union { + __IO uint8_t DACR; + stc_dacr_field_t DACR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint16_t DADR; + stc_dadr_field_t DADR_f; + }; +}FM4_DAC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint16_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t MCR_TTRM; + stc_crtrim_mcr_ttrm_field_t MCR_TTRM_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint32_t MCR_RLR; + stc_crtrim_mcr_rlr_field_t MCR_RLR_f; + }; +}FM4_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + union { + __IO uint32_t ENIR; + stc_exti_enir_field_t ENIR_f; + }; + union { + __IO uint32_t EIRR; + stc_exti_eirr_field_t EIRR_f; + }; + union { + __IO uint32_t EICL; + stc_exti_eicl_field_t EICL_f; + }; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + }; + union { + __IO uint32_t ELVR1; + stc_exti_elvr1_field_t ELVR1_f; + }; + union { + __IO uint8_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + }; +}FM4_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint8_t ODDPKS; + stc_intreq_oddpks_field_t ODDPKS_f; + }; + uint8_t RESERVED1[255]; + union { + __IO uint32_t IRQ003SEL; + stc_intreq_irq003sel_field_t IRQ003SEL_f; + }; + union { + __IO uint32_t IRQ004SEL; + stc_intreq_irq004sel_field_t IRQ004SEL_f; + }; + union { + __IO uint32_t IRQ005SEL; + stc_intreq_irq005sel_field_t IRQ005SEL_f; + }; + union { + __IO uint32_t IRQ006SEL; + stc_intreq_irq006sel_field_t IRQ006SEL_f; + }; + union { + __IO uint32_t IRQ007SEL; + stc_intreq_irq007sel_field_t IRQ007SEL_f; + }; + union { + __IO uint32_t IRQ008SEL; + stc_intreq_irq008sel_field_t IRQ008SEL_f; + }; + union { + __IO uint32_t IRQ009SEL; + stc_intreq_irq009sel_field_t IRQ009SEL_f; + }; + union { + __IO uint32_t IRQ010SEL; + stc_intreq_irq010sel_field_t IRQ010SEL_f; + }; + uint8_t RESERVED9[208]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + }; + union { + __IO uint32_t IRQ000MON; + stc_intreq_irq000mon_field_t IRQ000MON_f; + }; + union { + __IO uint32_t IRQ001MON; + stc_intreq_irq001mon_field_t IRQ001MON_f; + }; + union { + __IO uint32_t IRQ002MON; + stc_intreq_irq002mon_field_t IRQ002MON_f; + }; + union { + __IO uint32_t IRQ003MON; + stc_intreq_irq003mon_field_t IRQ003MON_f; + }; + union { + __IO uint32_t IRQ004MON; + stc_intreq_irq004mon_field_t IRQ004MON_f; + }; + union { + __IO uint32_t IRQ005MON; + stc_intreq_irq005mon_field_t IRQ005MON_f; + }; + union { + __IO uint32_t IRQ006MON; + stc_intreq_irq006mon_field_t IRQ006MON_f; + }; + union { + __IO uint32_t IRQ007MON; + stc_intreq_irq007mon_field_t IRQ007MON_f; + }; + union { + __IO uint32_t IRQ008MON; + stc_intreq_irq008mon_field_t IRQ008MON_f; + }; + union { + __IO uint32_t IRQ009MON; + stc_intreq_irq009mon_field_t IRQ009MON_f; + }; + union { + __IO uint32_t IRQ010MON; + stc_intreq_irq010mon_field_t IRQ010MON_f; + }; + union { + __IO uint32_t IRQ011MON; + stc_intreq_irq011mon_field_t IRQ011MON_f; + }; + union { + __IO uint32_t IRQ012MON; + stc_intreq_irq012mon_field_t IRQ012MON_f; + }; + union { + __IO uint32_t IRQ013MON; + stc_intreq_irq013mon_field_t IRQ013MON_f; + }; + union { + __IO uint32_t IRQ014MON; + stc_intreq_irq014mon_field_t IRQ014MON_f; + }; + union { + __IO uint32_t IRQ015MON; + stc_intreq_irq015mon_field_t IRQ015MON_f; + }; + union { + __IO uint32_t IRQ016MON; + stc_intreq_irq016mon_field_t IRQ016MON_f; + }; + union { + __IO uint32_t IRQ017MON; + stc_intreq_irq017mon_field_t IRQ017MON_f; + }; + union { + __IO uint32_t IRQ018MON; + stc_intreq_irq018mon_field_t IRQ018MON_f; + }; + union { + __IO uint32_t IRQ019MON; + stc_intreq_irq019mon_field_t IRQ019MON_f; + }; + union { + __IO uint32_t IRQ020MON; + stc_intreq_irq020mon_field_t IRQ020MON_f; + }; + union { + __IO uint32_t IRQ021MON; + stc_intreq_irq021mon_field_t IRQ021MON_f; + }; + union { + __IO uint32_t IRQ022MON; + stc_intreq_irq022mon_field_t IRQ022MON_f; + }; + union { + __IO uint32_t IRQ023MON; + stc_intreq_irq023mon_field_t IRQ023MON_f; + }; + union { + __IO uint32_t IRQ024MON; + stc_intreq_irq024mon_field_t IRQ024MON_f; + }; + union { + __IO uint32_t IRQ025MON; + stc_intreq_irq025mon_field_t IRQ025MON_f; + }; + union { + __IO uint32_t IRQ026MON; + stc_intreq_irq026mon_field_t IRQ026MON_f; + }; + union { + __IO uint32_t IRQ027MON; + stc_intreq_irq027mon_field_t IRQ027MON_f; + }; + union { + __IO uint32_t IRQ028MON; + stc_intreq_irq028mon_field_t IRQ028MON_f; + }; + union { + __IO uint32_t IRQ029MON; + stc_intreq_irq029mon_field_t IRQ029MON_f; + }; + union { + __IO uint32_t IRQ030MON; + stc_intreq_irq030mon_field_t IRQ030MON_f; + }; + union { + __IO uint32_t IRQ031MON; + stc_intreq_irq031mon_field_t IRQ031MON_f; + }; + union { + __IO uint32_t IRQ032MON; + stc_intreq_irq032mon_field_t IRQ032MON_f; + }; + union { + __IO uint32_t IRQ033MON; + stc_intreq_irq033mon_field_t IRQ033MON_f; + }; + union { + __IO uint32_t IRQ034MON; + stc_intreq_irq034mon_field_t IRQ034MON_f; + }; + union { + __IO uint32_t IRQ035MON; + stc_intreq_irq035mon_field_t IRQ035MON_f; + }; + union { + __IO uint32_t IRQ036MON; + stc_intreq_irq036mon_field_t IRQ036MON_f; + }; + union { + __IO uint32_t IRQ037MON; + stc_intreq_irq037mon_field_t IRQ037MON_f; + }; + union { + __IO uint32_t IRQ038MON; + stc_intreq_irq038mon_field_t IRQ038MON_f; + }; + union { + __IO uint32_t IRQ039MON; + stc_intreq_irq039mon_field_t IRQ039MON_f; + }; + union { + __IO uint32_t IRQ040MON; + stc_intreq_irq040mon_field_t IRQ040MON_f; + }; + union { + __IO uint32_t IRQ041MON; + stc_intreq_irq041mon_field_t IRQ041MON_f; + }; + union { + __IO uint32_t IRQ042MON; + stc_intreq_irq042mon_field_t IRQ042MON_f; + }; + union { + __IO uint32_t IRQ043MON; + stc_intreq_irq043mon_field_t IRQ043MON_f; + }; + union { + __IO uint32_t IRQ044MON; + stc_intreq_irq044mon_field_t IRQ044MON_f; + }; + union { + __IO uint32_t IRQ045MON; + stc_intreq_irq045mon_field_t IRQ045MON_f; + }; + union { + __IO uint32_t IRQ046MON; + stc_intreq_irq046mon_field_t IRQ046MON_f; + }; + union { + __IO uint32_t IRQ047MON; + stc_intreq_irq047mon_field_t IRQ047MON_f; + }; + union { + __IO uint32_t IRQ048MON; + stc_intreq_irq048mon_field_t IRQ048MON_f; + }; + union { + __IO uint32_t IRQ049MON; + stc_intreq_irq049mon_field_t IRQ049MON_f; + }; + union { + __IO uint32_t IRQ050MON; + stc_intreq_irq050mon_field_t IRQ050MON_f; + }; + union { + __IO uint32_t IRQ051MON; + stc_intreq_irq051mon_field_t IRQ051MON_f; + }; + union { + __IO uint32_t IRQ052MON; + stc_intreq_irq052mon_field_t IRQ052MON_f; + }; + union { + __IO uint32_t IRQ053MON; + stc_intreq_irq053mon_field_t IRQ053MON_f; + }; + union { + __IO uint32_t IRQ054MON; + stc_intreq_irq054mon_field_t IRQ054MON_f; + }; + union { + __IO uint32_t IRQ055MON; + stc_intreq_irq055mon_field_t IRQ055MON_f; + }; + union { + __IO uint32_t IRQ056MON; + stc_intreq_irq056mon_field_t IRQ056MON_f; + }; + union { + __IO uint32_t IRQ057MON; + stc_intreq_irq057mon_field_t IRQ057MON_f; + }; + union { + __IO uint32_t IRQ058MON; + stc_intreq_irq058mon_field_t IRQ058MON_f; + }; + union { + __IO uint32_t IRQ059MON; + stc_intreq_irq059mon_field_t IRQ059MON_f; + }; + union { + __IO uint32_t IRQ060MON; + stc_intreq_irq060mon_field_t IRQ060MON_f; + }; + union { + __IO uint32_t IRQ061MON; + stc_intreq_irq061mon_field_t IRQ061MON_f; + }; + union { + __IO uint32_t IRQ062MON; + stc_intreq_irq062mon_field_t IRQ062MON_f; + }; + union { + __IO uint32_t IRQ063MON; + stc_intreq_irq063mon_field_t IRQ063MON_f; + }; + union { + __IO uint32_t IRQ064MON; + stc_intreq_irq064mon_field_t IRQ064MON_f; + }; + union { + __IO uint32_t IRQ065MON; + stc_intreq_irq065mon_field_t IRQ065MON_f; + }; + union { + __IO uint32_t IRQ066MON; + stc_intreq_irq066mon_field_t IRQ066MON_f; + }; + union { + __IO uint32_t IRQ067MON; + stc_intreq_irq067mon_field_t IRQ067MON_f; + }; + union { + __IO uint32_t IRQ068MON; + stc_intreq_irq068mon_field_t IRQ068MON_f; + }; + union { + __IO uint32_t IRQ069MON; + stc_intreq_irq069mon_field_t IRQ069MON_f; + }; + union { + __IO uint32_t IRQ070MON; + stc_intreq_irq070mon_field_t IRQ070MON_f; + }; + union { + __IO uint32_t IRQ071MON; + stc_intreq_irq071mon_field_t IRQ071MON_f; + }; + union { + __IO uint32_t IRQ072MON; + stc_intreq_irq072mon_field_t IRQ072MON_f; + }; + union { + __IO uint32_t IRQ073MON; + stc_intreq_irq073mon_field_t IRQ073MON_f; + }; + union { + __IO uint32_t IRQ074MON; + stc_intreq_irq074mon_field_t IRQ074MON_f; + }; + union { + __IO uint32_t IRQ075MON; + stc_intreq_irq075mon_field_t IRQ075MON_f; + }; + union { + __IO uint32_t IRQ076MON; + stc_intreq_irq076mon_field_t IRQ076MON_f; + }; + union { + __IO uint32_t IRQ077MON; + stc_intreq_irq077mon_field_t IRQ077MON_f; + }; + union { + __IO uint32_t IRQ078MON; + stc_intreq_irq078mon_field_t IRQ078MON_f; + }; + union { + __IO uint32_t IRQ079MON; + stc_intreq_irq079mon_field_t IRQ079MON_f; + }; + union { + __IO uint32_t IRQ080MON; + stc_intreq_irq080mon_field_t IRQ080MON_f; + }; + union { + __IO uint32_t IRQ081MON; + stc_intreq_irq081mon_field_t IRQ081MON_f; + }; + union { + __IO uint32_t IRQ082MON; + stc_intreq_irq082mon_field_t IRQ082MON_f; + }; + union { + __IO uint32_t IRQ083MON; + stc_intreq_irq083mon_field_t IRQ083MON_f; + }; + union { + __IO uint32_t IRQ084MON; + stc_intreq_irq084mon_field_t IRQ084MON_f; + }; + union { + __IO uint32_t IRQ085MON; + stc_intreq_irq085mon_field_t IRQ085MON_f; + }; + union { + __IO uint32_t IRQ086MON; + stc_intreq_irq086mon_field_t IRQ086MON_f; + }; + union { + __IO uint32_t IRQ087MON; + stc_intreq_irq087mon_field_t IRQ087MON_f; + }; + union { + __IO uint32_t IRQ088MON; + stc_intreq_irq088mon_field_t IRQ088MON_f; + }; + union { + __IO uint32_t IRQ089MON; + stc_intreq_irq089mon_field_t IRQ089MON_f; + }; + union { + __IO uint32_t IRQ090MON; + stc_intreq_irq090mon_field_t IRQ090MON_f; + }; + union { + __IO uint32_t IRQ091MON; + stc_intreq_irq091mon_field_t IRQ091MON_f; + }; + union { + __IO uint32_t IRQ092MON; + stc_intreq_irq092mon_field_t IRQ092MON_f; + }; + union { + __IO uint32_t IRQ093MON; + stc_intreq_irq093mon_field_t IRQ093MON_f; + }; + union { + __IO uint32_t IRQ094MON; + stc_intreq_irq094mon_field_t IRQ094MON_f; + }; + union { + __IO uint32_t IRQ095MON; + stc_intreq_irq095mon_field_t IRQ095MON_f; + }; + union { + __IO uint32_t IRQ096MON; + stc_intreq_irq096mon_field_t IRQ096MON_f; + }; + union { + __IO uint32_t IRQ097MON; + stc_intreq_irq097mon_field_t IRQ097MON_f; + }; + union { + __IO uint32_t IRQ098MON; + stc_intreq_irq098mon_field_t IRQ098MON_f; + }; + union { + __IO uint32_t IRQ099MON; + stc_intreq_irq099mon_field_t IRQ099MON_f; + }; + union { + __IO uint32_t IRQ100MON; + stc_intreq_irq100mon_field_t IRQ100MON_f; + }; + union { + __IO uint32_t IRQ101MON; + stc_intreq_irq101mon_field_t IRQ101MON_f; + }; + union { + __IO uint32_t IRQ102MON; + stc_intreq_irq102mon_field_t IRQ102MON_f; + }; + union { + __IO uint32_t IRQ103MON; + stc_intreq_irq103mon_field_t IRQ103MON_f; + }; + union { + __IO uint32_t IRQ104MON; + stc_intreq_irq104mon_field_t IRQ104MON_f; + }; + union { + __IO uint32_t IRQ105MON; + stc_intreq_irq105mon_field_t IRQ105MON_f; + }; + union { + __IO uint32_t IRQ106MON; + stc_intreq_irq106mon_field_t IRQ106MON_f; + }; + union { + __IO uint32_t IRQ107MON; + stc_intreq_irq107mon_field_t IRQ107MON_f; + }; + union { + __IO uint32_t IRQ108MON; + stc_intreq_irq108mon_field_t IRQ108MON_f; + }; + union { + __IO uint32_t IRQ109MON; + stc_intreq_irq109mon_field_t IRQ109MON_f; + }; + union { + __IO uint32_t IRQ110MON; + stc_intreq_irq110mon_field_t IRQ110MON_f; + }; + union { + __IO uint32_t IRQ111MON; + stc_intreq_irq111mon_field_t IRQ111MON_f; + }; + __IO uint32_t IRQ112MON; + union { + __IO uint32_t IRQ113MON; + stc_intreq_irq113mon_field_t IRQ113MON_f; + }; + union { + __IO uint32_t IRQ114MON; + stc_intreq_irq114mon_field_t IRQ114MON_f; + }; + __IO uint32_t IRQ115MON; + __IO uint32_t IRQ116MON; + __IO uint32_t IRQ117MON; + union { + __IO uint32_t IRQ118MON; + stc_intreq_irq118mon_field_t IRQ118MON_f; + }; + union { + __IO uint32_t IRQ119MON; + stc_intreq_irq119mon_field_t IRQ119MON_f; + }; + union { + __IO uint32_t IRQ120MON; + stc_intreq_irq120mon_field_t IRQ120MON_f; + }; + union { + __IO uint32_t IRQ121MON; + stc_intreq_irq121mon_field_t IRQ121MON_f; + }; + union { + __IO uint32_t IRQ122MON; + stc_intreq_irq122mon_field_t IRQ122MON_f; + }; + union { + __IO uint32_t IRQ123MON; + stc_intreq_irq123mon_field_t IRQ123MON_f; + }; + union { + __IO uint32_t IRQ124MON; + stc_intreq_irq124mon_field_t IRQ124MON_f; + }; + union { + __IO uint32_t IRQ125MON; + stc_intreq_irq125mon_field_t IRQ125MON_f; + }; + union { + __IO uint32_t IRQ126MON; + stc_intreq_irq126mon_field_t IRQ126MON_f; + }; + union { + __IO uint32_t IRQ127MON; + stc_intreq_irq127mon_field_t IRQ127MON_f; + }; +}FM4_INTREQ_TypeDef; + +/****************************************************************************** + * IRQSEL_MODULE +******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t IRQ03SEL; + stc_irqsel_field_t IRQ03SEL_f; + }; + union { + __IO uint32_t IRQ04SEL; + stc_irqsel_field_t IRQ04SEL_f; + }; + union { + __IO uint32_t IRQ05SEL; + stc_irqsel_field_t IRQ05SEL_f; + }; + union { + __IO uint32_t IRQ06SEL; + stc_irqsel_field_t IRQ06SEL_f; + }; + union { + __IO uint32_t IRQ07SEL; + stc_irqsel_field_t IRQ07SEL_f; + }; + union { + __IO uint32_t IRQ08SEL; + stc_irqsel_field_t IRQ08SEL_f; + }; + union { + __IO uint32_t IRQ09SEL; + stc_irqsel_field_t IRQ09SEL_f; + }; + union { + __IO uint32_t IRQ10SEL; + stc_irqsel_field_t IRQ10SEL_f; + }; +} FM4_IRQSEL_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + }; + union { + __IO uint32_t PFR5; + stc_gpio_pfr5_field_t PFR5_f; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + }; + uint8_t RESERVED8[20]; + union { + __IO uint32_t PFRE; + stc_gpio_pfre_field_t PFRE_f; + }; + uint8_t RESERVED9[196]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + }; + union { + __IO uint32_t PCR5; + stc_gpio_pcr5_field_t PCR5_f; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + }; + union { + __IO uint32_t PCR8; + stc_gpio_pcr8_field_t PCR8_f; + }; + uint8_t RESERVED18[20]; + union { + __IO uint32_t PCRE; + stc_gpio_pcre_field_t PCRE_f; + }; + uint8_t RESERVED19[196]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + }; + union { + __IO uint32_t DDR5; + stc_gpio_ddr5_field_t DDR5_f; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + }; + uint8_t RESERVED28[20]; + union { + __IO uint32_t DDRE; + stc_gpio_ddre_field_t DDRE_f; + }; + uint8_t RESERVED29[196]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + }; + union { + __IO uint32_t PDIR5; + stc_gpio_pdir5_field_t PDIR5_f; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + }; + uint8_t RESERVED38[20]; + union { + __IO uint32_t PDIRE; + stc_gpio_pdire_field_t PDIRE_f; + }; + uint8_t RESERVED39[196]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + }; + union { + __IO uint32_t PDOR5; + stc_gpio_pdor5_field_t PDOR5_f; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + }; + uint8_t RESERVED48[20]; + union { + __IO uint32_t PDORE; + stc_gpio_pdore_field_t PDORE_f; + }; + uint8_t RESERVED49[196]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + }; + uint8_t RESERVED50[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + }; + uint8_t RESERVED51[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + }; + union { + __IO uint32_t EPFR03; + stc_gpio_epfr03_field_t EPFR03_f; + }; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + }; + union { + __IO uint32_t EPFR11; + stc_gpio_epfr11_field_t EPFR11_f; + }; + union { + __IO uint32_t EPFR12; + stc_gpio_epfr12_field_t EPFR12_f; + }; + union { + __IO uint32_t EPFR13; + stc_gpio_epfr13_field_t EPFR13_f; + }; + union { + __IO uint32_t EPFR14; + stc_gpio_epfr14_field_t EPFR14_f; + }; + union { + __IO uint32_t EPFR15; + stc_gpio_epfr15_field_t EPFR15_f; + }; + union { + __IO uint32_t EPFR16; + stc_gpio_epfr16_field_t EPFR16_f; + }; + union { + __IO uint32_t EPFR17; + stc_gpio_epfr17_field_t EPFR17_f; + }; + union { + __IO uint32_t EPFR18; + stc_gpio_epfr18_field_t EPFR18_f; + }; + __IO uint32_t EPFR19; + union { + __IO uint32_t EPFR20; + stc_gpio_epfr20_field_t EPFR20_f; + }; + uint8_t RESERVED72[172]; + union { + __IO uint32_t PZR0; + stc_gpio_pzr0_field_t PZR0_f; + }; + union { + __IO uint32_t PZR1; + stc_gpio_pzr1_field_t PZR1_f; + }; + union { + __IO uint32_t PZR2; + stc_gpio_pzr2_field_t PZR2_f; + }; + union { + __IO uint32_t PZR3; + stc_gpio_pzr3_field_t PZR3_f; + }; + union { + __IO uint32_t PZR4; + stc_gpio_pzr4_field_t PZR4_f; + }; + union { + __IO uint32_t PZR5; + stc_gpio_pzr5_field_t PZR5_f; + }; + union { + __IO uint32_t PZR6; + stc_gpio_pzr6_field_t PZR6_f; + }; + union { + __IO uint32_t PZR7; + stc_gpio_pzr7_field_t PZR7_f; + }; + union { + __IO uint32_t PZR8; + stc_gpio_pzr8_field_t PZR8_f; + }; + uint8_t RESERVED81[20]; + union { + __IO uint32_t PZRE; + stc_gpio_pzre_field_t PZRE_f; + }; +}FM4_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +}FM4_LVD_TypeDef; + +/****************************************************************************** + * DS_MODULE + ******************************************************************************/ +/* Deep standby mode registers */ +typedef struct +{ + uint8_t RESERVED10[4]; + union { + __IO uint8_t RCK_CTL; + stc_ds_rck_ctl_field_t RCK_CTL_f; + }; + uint8_t RESERVED0[1787]; + union { + __IO uint8_t PMD_CTL; + stc_ds_pmd_ctl_field_t PMD_CTL_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WRFSR; + stc_ds_wrfsr_field_t WRFSR_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint16_t WIFSR; + stc_ds_wifsr_field_t WIFSR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t WIER; + stc_ds_wier_field_t WIER_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint8_t WILVR; + stc_ds_wilvr_field_t WILVR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t DSRAMR; + stc_ds_dsramr_field_t DSRAMR_f; + }; + uint8_t RESERVED6[235]; + __IO uint8_t BUR01; + __IO uint8_t BUR02; + __IO uint8_t BUR03; + __IO uint8_t BUR04; + __IO uint8_t BUR05; + __IO uint8_t BUR06; + __IO uint8_t BUR07; + __IO uint8_t BUR08; + __IO uint8_t BUR09; + __IO uint8_t BUR10; + __IO uint8_t BUR11; + __IO uint8_t BUR12; + __IO uint8_t BUR13; + __IO uint8_t BUR14; + __IO uint8_t BUR15; + __IO uint8_t BUR16; +}FM4_DS_TypeDef; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USB clock registers */ +/* +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbclk_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclk_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclk_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclk_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclk_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclk_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclk_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclk_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclk_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[15]; + union { + __IO uint8_t USBEN; + stc_usbclk_usben_field_t USBEN_f; + }; +}FM4_USBCLK_TypeDef; +*/ + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CAN prescaler register */ +typedef struct +{ + union { + __IO uint8_t CANPRE; + stc_canpre_canpre_field_t CANPRE_f; + }; +}FM4_CANPRE_TypeDef; + +/****************************************************************************** + * USBETHERNETCLK + ******************************************************************************/ +/* USB Ethernet clock registers */ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbethernetclk_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbethernetclk_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbethernetclk_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbethernetclk_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbethernetclk_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbethernetclk_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbethernetclk_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbethernetclk_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t UPCR6; + stc_usbethernetclk_upcr6_field_t UPCR6_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t UPCR7; + stc_usbethernetclk_upcr7_field_t UPCR7_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t USBEN0; + stc_usbethernetclk_usben0_field_t USBEN0_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t USBEN1; + stc_usbethernetclk_usben1_field_t USBEN1_f; + }; +}FM4_USBETHERNETCLK_TypeDef; + +/****************************************************************************** + * MFS_MODULE + ******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_scr_field_t SCR_f; + __IO uint8_t IBCR; + stc_mfs_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs_escr_field_t ESCR_f; + __IO uint8_t IBSR; + stc_mfs_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint32_t RDR32; + __IO uint32_t TDR32; + struct { + union { + __IO uint16_t RDR; + stc_mfs_uart_rdr_field_t RDR_f; + }; + uint8_t RESERVED2[2]; + }; + struct { + union { + __IO uint16_t TDR; + stc_mfs_uart_tdr_field_t TDR_f; + }; + uint8_t RESERVED3[2]; + }; + }; + union { + union { + __IO uint16_t BGR; + stc_mfs_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint8_t ISBA; + stc_mfs_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs_i2c_ismk_field_t ISMK_f; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t FCR; + stc_mfs_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_fbyte2_field_t FBYTE2_f; + }; + }; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t SCSTR10; + stc_mfs_csio_scstr10_field_t SCSTR10_f; + struct { + union { + __IO uint8_t SCSTR0; + stc_mfs_csio_scstr0_field_t SCSTR0_f; + __IO uint8_t NFCR; + stc_mfs_i2c_nfcr_field_t NFCR_f; + }; + union { + __IO uint8_t SCSTR1; + stc_mfs_csio_scstr1_field_t SCSTR1_f; + __IO uint8_t EIBCR; + stc_mfs_i2c_eibcr_field_t EIBCR_f; + }; + }; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t SCSTR32; + stc_mfs_csio_scstr32_field_t SCSTR32_f; + struct { + union { + __IO uint8_t SCSTR2; + stc_mfs_csio_scstr2_field_t SCSTR2_f; + }; + union { + __IO uint8_t SCSTR3; + stc_mfs_csio_scstr3_field_t SCSTR3_f; + }; + }; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t SACSR; + stc_mfs_csio_sacsr_field_t SACSR_f; + struct { + union { + __IO uint8_t SACSR0; + stc_mfs_csio_sacsr0_field_t SACSR0_f; + }; + union { + __IO uint8_t SACSR1; + stc_mfs_csio_sacsr1_field_t SACSR1_f; + }; + }; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t STMR; + stc_mfs_csio_stmr_field_t STMR_f; + struct { + union { + __IO uint8_t STMR0; + stc_mfs_csio_stmr0_field_t STMR0_f; + }; + union { + __IO uint8_t STMR1; + stc_mfs_csio_stmr1_field_t STMR1_f; + }; + }; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t STMCR; + stc_mfs_csio_stmcr_field_t STMCR_f; + struct { + union { + __IO uint8_t STMCR0; + stc_mfs_csio_stmcr0_field_t STMCR0_f; + }; + union { + __IO uint8_t STMCR1; + stc_mfs_csio_stmcr1_field_t STMCR1_f; + }; + }; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t SCSCR; + stc_mfs_csio_scscr_field_t SCSCR_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t SCSFR; + struct { + __IO uint8_t SCSFR0; + __IO uint8_t SCSFR1; + }; + }; + uint8_t RESERVED14[2]; + __IO uint8_t SCSFR2; + uint8_t RESERVED15[3]; + union { + __IO uint16_t TBYTE10; + struct { + __IO uint8_t TBYTE0; + __IO uint8_t TBYTE1; + }; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t TBYTE32; + struct { + __IO uint8_t TBYTE2; + __IO uint8_t TBYTE3; + }; + }; +}FM4_MFS_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM4_CRC_TypeDef; + +/****************************************************************************** + * DSTC_MODULE + ******************************************************************************/ +/* DSTC registers */ +typedef struct +{ + __IO uint32_t DESTP; + union { + __IO uint32_t HWDESP; + stc_dstc_hwdesp_field_t HWDESP_f; + }; + __IO uint8_t CMD; + union { + __IO uint8_t CFG; + stc_dstc_cfg_field_t CFG_f; + }; + union { + __IO uint16_t SWTR; + stc_dstc_swtr_field_t SWTR_f; + }; + union { + __IO uint32_t MONERS; + stc_dstc_moners_field_t MONERS_f; + }; + __IO uint32_t DREQENB0; + __IO uint32_t DREQENB1; + __IO uint32_t DREQENB2; + __IO uint32_t DREQENB3; + __IO uint32_t DREQENB4; + __IO uint32_t DREQENB5; + __IO uint32_t DREQENB6; + __IO uint32_t DREQENB7; + __IO uint32_t HWINT0; + __IO uint32_t HWINT1; + __IO uint32_t HWINT2; + __IO uint32_t HWINT3; + __IO uint32_t HWINT4; + __IO uint32_t HWINT5; + __IO uint32_t HWINT6; + __IO uint32_t HWINT7; + __IO uint32_t HWINTCLR0; + __IO uint32_t HWINTCLR1; + __IO uint32_t HWINTCLR2; + __IO uint32_t HWINTCLR3; + __IO uint32_t HWINTCLR4; + __IO uint32_t HWINTCLR5; + __IO uint32_t HWINTCLR6; + __IO uint32_t HWINTCLR7; + __IO uint32_t DQMSK0; + __IO uint32_t DQMSK1; + __IO uint32_t DQMSK2; + __IO uint32_t DQMSK3; + __IO uint32_t DQMSK4; + __IO uint32_t DQMSK5; + __IO uint32_t DQMSK6; + __IO uint32_t DQMSK7; + __IO uint32_t DQMSKCLR0; + __IO uint32_t DQMSKCLR1; + __IO uint32_t DQMSKCLR2; + __IO uint32_t DQMSKCLR3; + __IO uint32_t DQMSKCLR4; + __IO uint32_t DQMSKCLR5; + __IO uint32_t DQMSKCLR6; + __IO uint32_t DQMSKCLR7; +}FM4_DSTC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +}FM4_WC_TypeDef; + +/****************************************************************************** + * RTC_MODULE + ******************************************************************************/ +/* Real time clock registers */ +typedef struct +{ + union { + __IO uint8_t WTCR10; + stc_rtc_wtcr10_field_t WTCR10_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WTCR11; + stc_rtc_wtcr11_field_t WTCR11_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t WTCR12; + stc_rtc_wtcr12_field_t WTCR12_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t WTCR13; + stc_rtc_wtcr13_field_t WTCR13_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t WTCR20; + stc_rtc_wtcr20_field_t WTCR20_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t WTCR21; + stc_rtc_wtcr21_field_t WTCR21_f; + }; + uint8_t RESERVED6[3]; + __IO uint8_t WTCR22; + uint8_t RESERVED7[3]; + union { + __IO uint8_t WTSR; + stc_rtc_wtsr_field_t WTSR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t WTMIR; + stc_rtc_wtmir_field_t WTMIR_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t WTHR; + stc_rtc_wthr_field_t WTHR_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t WTDR; + stc_rtc_wtdr_field_t WTDR_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t WTDW; + stc_rtc_wtdw_field_t WTDW_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t WTMOR; + stc_rtc_wtmor_field_t WTMOR_f; + }; + uint8_t RESERVED13[3]; + union { + __IO uint8_t WTYR; + stc_rtc_wtyr_field_t WTYR_f; + }; + uint8_t RESERVED14[3]; + union { + __IO uint8_t ALMIR; + stc_rtc_almir_field_t ALMIR_f; + }; + uint8_t RESERVED15[3]; + union { + __IO uint8_t ALHR; + stc_rtc_alhr_field_t ALHR_f; + }; + uint8_t RESERVED16[3]; + union { + __IO uint8_t ALDR; + stc_rtc_aldr_field_t ALDR_f; + }; + uint8_t RESERVED17[3]; + union { + __IO uint8_t ALMOR; + stc_rtc_almor_field_t ALMOR_f; + }; + uint8_t RESERVED18[3]; + union { + __IO uint8_t ALYR; + stc_rtc_alyr_field_t ALYR_f; + }; + uint8_t RESERVED19[3]; + union { + __IO uint8_t WTTR0; + stc_rtc_wttr0_field_t WTTR0_f; + }; + uint8_t RESERVED20[3]; + union { + __IO uint8_t WTTR1; + stc_rtc_wttr1_field_t WTTR1_f; + }; + uint8_t RESERVED21[3]; + union { + __IO uint8_t WTTR2; + stc_rtc_wttr2_field_t WTTR2_f; + }; + uint8_t RESERVED22[3]; + __IO uint8_t WTCAL0; + uint8_t RESERVED23[3]; + union { + __IO uint8_t WTCAL1; + stc_rtc_wtcal1_field_t WTCAL1_f; + }; + uint8_t RESERVED24[3]; + union { + __IO uint8_t WTCALEN; + stc_rtc_wtcalen_field_t WTCALEN_f; + }; + uint8_t RESERVED25[3]; + union { + __IO uint8_t WTDIV; + stc_rtc_wtdiv_field_t WTDIV_f; + }; + uint8_t RESERVED26[3]; + union { + __IO uint8_t WTDIVEN; + stc_rtc_wtdiven_field_t WTDIVEN_f; + }; + uint8_t RESERVED27[3]; + union { + __IO uint8_t WTCALPRD; + stc_rtc_wtcalprd_field_t WTCALPRD_f; + }; + uint8_t RESERVED28[3]; + union { + __IO uint8_t WTCOSEL; + stc_rtc_wtcosel_field_t WTCOSEL_f; + }; + uint8_t RESERVED29[3]; + union { + __IO uint8_t VB_CLKDIV; + stc_rtc_vb_clkdiv_field_t VB_CLKDIV_f; + }; + uint8_t RESERVED30[3]; + union { + __IO uint8_t WTOSCCNT; + stc_rtc_wtosccnt_field_t WTOSCCNT_f; + }; + uint8_t RESERVED31[3]; + __IO uint8_t CCS; + uint8_t RESERVED32[3]; + __IO uint8_t CCB; + uint8_t RESERVED33[3]; + /* Don't exist on peripheral manual */ + __IO uint8_t TRIM; + uint8_t RESERVED34[3]; + union { + __IO uint8_t BOOST; + stc_rtc_boost_field_t BOOST_f; + }; + uint8_t RESERVED35[3]; + union { + __IO uint8_t EWKUP; + stc_rtc_ewkup_field_t EWKUP_f; + }; + uint8_t RESERVED36[3]; + union { + __IO uint8_t VDET; + stc_rtc_vdet_field_t VDET_f; + }; + uint8_t RESERVED37[3]; + /* Don't exist on peripheral manual */ + __IO uint8_t FDET; + uint8_t RESERVED38[3]; + union { + __IO uint8_t HIBRST; + stc_rtc_hibrst_field_t HIBRST_f; + }; + uint8_t RESERVED39[3]; + union { + __IO uint8_t VBPFR; + stc_rtc_vbpfr_field_t VBPFR_f; + }; + uint8_t RESERVED40[3]; + union { + __IO uint8_t VBPCR; + stc_rtc_vbpcr_field_t VBPCR_f; + }; + uint8_t RESERVED41[3]; + union { + __IO uint8_t VBDDR; + stc_rtc_vbddr_field_t VBDDR_f; + }; + uint8_t RESERVED42[3]; + union { + __IO uint8_t VBDIR; + stc_rtc_vbdir_field_t VBDIR_f; + }; + uint8_t RESERVED43[3]; + union { + __IO uint8_t VBDOR; + stc_rtc_vbdor_field_t VBDOR_f; + }; + uint8_t RESERVED44[3]; + union { + __IO uint8_t VBPZR; + stc_rtc_vbpzr_field_t VBPZR_f; + }; + uint8_t RESERVED45[87]; + union { + __IO uint32_t BREG00_03; + struct { + __IO uint16_t BREG00_01; + __IO uint16_t BREG02_03; + }; + struct { + __IO uint8_t BREG00; + __IO uint8_t BREG01; + __IO uint8_t BREG02; + __IO uint8_t BREG03; + }; + }; + union { + __IO uint32_t BREG04_07; + struct { + __IO uint16_t BREG04_05; + __IO uint16_t BREG06_07; + }; + struct { + __IO uint8_t BREG04; + __IO uint8_t BREG05; + __IO uint8_t BREG06; + __IO uint8_t BREG07; + }; + }; + union { + __IO uint32_t BREG08_0B; + struct { + __IO uint16_t BREG08_09; + __IO uint16_t BREG0A_0B; + }; + struct { + __IO uint8_t BREG08; + __IO uint8_t BREG09; + __IO uint8_t BREG0A; + __IO uint8_t BREG0B; + }; + }; + union { + __IO uint32_t BREG0C_0F; + struct { + __IO uint16_t BREG0C_0D; + __IO uint16_t BREG0E_0F; + }; + struct { + __IO uint8_t BREG0C; + __IO uint8_t BREG0D; + __IO uint8_t BREG0E; + __IO uint8_t BREG0F; + }; + }; + union { + __IO uint32_t BREG10_13; + struct { + __IO uint16_t BREG10_11; + __IO uint16_t BREG12_13; + }; + struct { + __IO uint8_t BREG10; + __IO uint8_t BREG11; + __IO uint8_t BREG12; + __IO uint8_t BREG13; + }; + }; + union { + __IO uint32_t BREG14_17; + struct { + __IO uint16_t BREG14_15; + __IO uint16_t BREG16_17; + }; + struct { + __IO uint8_t BREG14; + __IO uint8_t BREG15; + __IO uint8_t BREG16; + __IO uint8_t BREG17; + }; + }; + union { + __IO uint32_t BREG18_1B; + struct { + __IO uint16_t BREG18_19; + __IO uint16_t BREG1A_1B; + }; + struct { + __IO uint8_t BREG18; + __IO uint8_t BREG19; + __IO uint8_t BREG1A; + __IO uint8_t BREG1B; + }; + }; + union { + __IO uint32_t BREG1C_1F; + struct { + __IO uint16_t BREG1C_1D; + __IO uint16_t BREG1E_1F; + }; + struct { + __IO uint8_t BREG1C; + __IO uint8_t BREG1D; + __IO uint8_t BREG1E; + __IO uint8_t BREG1F; + }; + }; + union { + __IO uint32_t BREG20_23; + struct { + __IO uint16_t BREG20_21; + __IO uint16_t BREG22_23; + }; + struct { + __IO uint8_t BREG20; + __IO uint8_t BREG21; + __IO uint8_t BREG22; + __IO uint8_t BREG23; + }; + }; + union { + __IO uint32_t BREG24_27; + struct { + __IO uint16_t BREG24_25; + __IO uint16_t BREG26_27; + }; + struct { + __IO uint8_t BREG24; + __IO uint8_t BREG25; + __IO uint8_t BREG26; + __IO uint8_t BREG27; + }; + }; + union { + __IO uint32_t BREG28_2B; + struct { + __IO uint16_t BREG28_29; + __IO uint16_t BREG2A_2B; + }; + struct { + __IO uint8_t BREG28; + __IO uint8_t BREG29; + __IO uint8_t BREG2A; + __IO uint8_t BREG2B; + }; + }; + union { + __IO uint32_t BREG2C_2F; + struct { + __IO uint16_t BREG2C_2D; + __IO uint16_t BREG2E_2F; + }; + struct { + __IO uint8_t BREG2C; + __IO uint8_t BREG2D; + __IO uint8_t BREG2E; + __IO uint8_t BREG2F; + }; + }; + union { + __IO uint32_t BREG30_33; + struct { + __IO uint16_t BREG30_31; + __IO uint16_t BREG32_33; + }; + struct { + __IO uint8_t BREG30; + __IO uint8_t BREG31; + __IO uint8_t BREG32; + __IO uint8_t BREG33; + }; + }; + union { + __IO uint32_t BREG34_37; + struct { + __IO uint16_t BREG34_35; + __IO uint16_t BREG36_37; + }; + struct { + __IO uint8_t BREG34; + __IO uint8_t BREG35; + __IO uint8_t BREG36; + __IO uint8_t BREG37; + }; + }; + union { + __IO uint32_t BREG38_3B; + struct { + __IO uint16_t BREG38_39; + __IO uint16_t BREG3A_3B; + }; + struct { + __IO uint8_t BREG38; + __IO uint8_t BREG39; + __IO uint8_t BREG3A; + __IO uint8_t BREG3B; + }; + }; + union { + __IO uint32_t BREG3C_3F; + struct { + __IO uint16_t BREG3C_3D; + __IO uint16_t BREG3E_3F; + }; + struct { + __IO uint8_t BREG3C; + __IO uint8_t BREG3D; + __IO uint8_t BREG3E; + __IO uint8_t BREG3F; + }; + }; + union { + __IO uint32_t BREG40_43; + struct { + __IO uint16_t BREG40_41; + __IO uint16_t BREG42_43; + }; + struct { + __IO uint8_t BREG40; + __IO uint8_t BREG41; + __IO uint8_t BREG42; + __IO uint8_t BREG43; + }; + }; + union { + __IO uint32_t BREG44_47; + struct { + __IO uint16_t BREG44_45; + __IO uint16_t BREG46_47; + }; + struct { + __IO uint8_t BREG44; + __IO uint8_t BREG45; + __IO uint8_t BREG46; + __IO uint8_t BREG47; + }; + }; + union { + __IO uint32_t BREG48_4B; + struct { + __IO uint16_t BREG48_49; + __IO uint16_t BREG4A_4B; + }; + struct { + __IO uint8_t BREG48; + __IO uint8_t BREG49; + __IO uint8_t BREG4A; + __IO uint8_t BREG4B; + }; + }; + union { + __IO uint32_t BREG4C_4F; + struct { + __IO uint16_t BREG4C_4D; + __IO uint16_t BREG4E_4F; + }; + struct { + __IO uint8_t BREG4C; + __IO uint8_t BREG4D; + __IO uint8_t BREG4E; + __IO uint8_t BREG4F; + }; + }; + union { + __IO uint32_t BREG50_53; + struct { + __IO uint16_t BREG50_51; + __IO uint16_t BREG52_53; + }; + struct { + __IO uint8_t BREG50; + __IO uint8_t BREG51; + __IO uint8_t BREG52; + __IO uint8_t BREG53; + }; + }; + union { + __IO uint32_t BREG54_57; + struct { + __IO uint16_t BREG54_55; + __IO uint16_t BREG56_57; + }; + struct { + __IO uint8_t BREG54; + __IO uint8_t BREG55; + __IO uint8_t BREG56; + __IO uint8_t BREG57; + }; + }; + union { + __IO uint32_t BREG58_5B; + struct { + __IO uint16_t BREG58_59; + __IO uint16_t BREG5A_5B; + }; + struct { + __IO uint8_t BREG58; + __IO uint8_t BREG59; + __IO uint8_t BREG5A; + __IO uint8_t BREG5B; + }; + }; + union { + __IO uint32_t BREG5C_5F; + struct { + __IO uint16_t BREG5C_5D; + __IO uint16_t BREG5E_5F; + }; + struct { + __IO uint8_t BREG5C; + __IO uint8_t BREG5D; + __IO uint8_t BREG5E; + __IO uint8_t BREG5F; + }; + }; + union { + __IO uint32_t BREG60_63; + struct { + __IO uint16_t BREG60_61; + __IO uint16_t BREG62_63; + }; + struct { + __IO uint8_t BREG60; + __IO uint8_t BREG61; + __IO uint8_t BREG62; + __IO uint8_t BREG63; + }; + }; + union { + __IO uint32_t BREG64_67; + struct { + __IO uint16_t BREG64_65; + __IO uint16_t BREG66_67; + }; + struct { + __IO uint8_t BREG64; + __IO uint8_t BREG65; + __IO uint8_t BREG66; + __IO uint8_t BREG67; + }; + }; + union { + __IO uint32_t BREG68_6B; + struct { + __IO uint16_t BREG68_69; + __IO uint16_t BREG6A_6B; + }; + struct { + __IO uint8_t BREG68; + __IO uint8_t BREG69; + __IO uint8_t BREG6A; + __IO uint8_t BREG6B; + }; + }; + union { + __IO uint32_t BREG6C_6F; + struct { + __IO uint16_t BREG6C_6D; + __IO uint16_t BREG6E_6F; + }; + struct { + __IO uint8_t BREG6C; + __IO uint8_t BREG6D; + __IO uint8_t BREG6E; + __IO uint8_t BREG6F; + }; + }; + union { + __IO uint32_t BREG70_73; + struct { + __IO uint16_t BREG70_71; + __IO uint16_t BREG72_73; + }; + struct { + __IO uint8_t BREG70; + __IO uint8_t BREG71; + __IO uint8_t BREG72; + __IO uint8_t BREG73; + }; + }; + union { + __IO uint32_t BREG74_77; + struct { + __IO uint16_t BREG74_75; + __IO uint16_t BREG76_77; + }; + struct { + __IO uint8_t BREG74; + __IO uint8_t BREG75; + __IO uint8_t BREG76; + __IO uint8_t BREG77; + }; + }; + union { + __IO uint32_t BREG78_7B; + struct { + __IO uint16_t BREG78_79; + __IO uint16_t BREG7A_7B; + }; + struct { + __IO uint8_t BREG78; + __IO uint8_t BREG79; + __IO uint8_t BREG7A; + __IO uint8_t BREG7B; + }; + }; + union { + __IO uint32_t BREG7C_7F; + struct { + __IO uint16_t BREG7C_7D; + __IO uint16_t BREG7E_7F; + }; + struct { + __IO uint8_t BREG7C; + __IO uint8_t BREG7D; + __IO uint8_t BREG7E; + __IO uint8_t BREG7F; + }; + }; +}FM4_RTC_TypeDef; + +/****************************************************************************** + * LCR_MODULE + ******************************************************************************/ +/* Low-speed CR prescaler registers */ +typedef struct +{ + union { + __IO uint8_t LCR_PRSLD; + stc_lcr_lcr_prsld_field_t LCR_PRSLD_f; + }; +}FM4_LCR_TypeDef; + +/****************************************************************************** + * CLK_GATING_MODULE + ******************************************************************************/ +/* CLK_GATING registers */ +typedef struct +{ + union { + __IO uint32_t CKEN0; + stc_clk_gating_cken0_field_t CKEN0_f; + }; + union { + __IO uint32_t MRST0; + stc_clk_gating_mrst0_field_t MRST0_f; + }; + uint8_t RESERVED1[8]; + union { + __IO uint32_t CKEN1; + stc_clk_gating_cken1_field_t CKEN1_f; + }; + union { + __IO uint32_t MRST1; + stc_clk_gating_mrst1_field_t MRST1_f; + }; + uint8_t RESERVED3[8]; + union { + __IO uint32_t CKEN2; + stc_clk_gating_cken2_field_t CKEN2_f; + }; + union { + __IO uint32_t MRST2; + stc_clk_gating_mrst2_field_t MRST2_f; + }; +}FM4_CLK_GATING_TypeDef; + +/****************************************************************************** + * PLL_CONTROL_MODULE + ******************************************************************************/ +/* PLL_CONTROL registers */ +typedef struct +{ + __IO uint32_t SSCTL1; + __IO uint32_t SSCTL2; +}FM4_PLL_CONTROL_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode_field_t MODE0_f; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode_field_t MODE1_f; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode_field_t MODE2_f; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode_field_t MODE3_f; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode_field_t MODE4_f; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode_field_t MODE5_f; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode_field_t MODE6_f; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode_field_t MODE7_f; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim_field_t TIM0_f; + }; + __IO uint32_t TIM1; + union { + __IO uint32_t TIM2; + stc_exbus_tim_field_t TIM2_f; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim_field_t TIM3_f; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim_field_t TIM4_f; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim_field_t TIM5_f; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim_field_t TIM6_f; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim_field_t TIM7_f; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area_field_t AREA0_f; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area_field_t AREA1_f; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area_field_t AREA2_f; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area_field_t AREA3_f; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area_field_t AREA4_f; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area_field_t AREA5_f; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area_field_t AREA6_f; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area_field_t AREA7_f; + }; + union { + __IO uint32_t ATIM0; + stc_exbus_atim_field_t ATIM0_f; + }; + union { + __IO uint32_t ATIM1; + stc_exbus_atim_field_t ATIM1_f; + }; + union { + __IO uint32_t ATIM2; + stc_exbus_atim_field_t ATIM2_f; + }; + union { + __IO uint32_t ATIM3; + stc_exbus_atim_field_t ATIM3_f; + }; + union { + __IO uint32_t ATIM4; + stc_exbus_atim_field_t ATIM4_f; + }; + union { + __IO uint32_t ATIM5; + stc_exbus_atim_field_t ATIM5_f; + }; + union { + __IO uint32_t ATIM6; + stc_exbus_atim_field_t ATIM6_f; + }; + union { + __IO uint32_t ATIM7; + stc_exbus_atim_field_t ATIM7_f; + }; + uint8_t RESERVED1[128]; + union { + __IO uint32_t SDMODE; + stc_exbus_sdmode_field_t SDMODE_f; + }; + union { + __IO uint32_t REFTIM; + stc_exbus_reftim_field_t REFTIM_f; + }; + union { + __IO uint32_t PWRDWN; + stc_exbus_pwrdwn_field_t PWRDWN_f; + }; + union { + __IO uint32_t SDTIM; + stc_exbus_sdtim_field_t SDTIM_f; + }; + union { + __IO uint32_t SDCMD; + stc_exbus_sdcmd_field_t SDCMD_f; + }; + uint8_t RESERVED2[236]; + union { + __IO uint32_t MEMCERR; + stc_exbus_memcerr_field_t MEMCERR_f; + }; + uint8_t RESERVED3[252]; + union { + __IO uint32_t DCLKR; + stc_exbus_dclkr_field_t DCLKR_f; + }; + union { + __IO uint32_t EST; + stc_exbus_est_field_t EST_f; + }; + union { + __IO uint32_t WEAD; + stc_exbus_wead_field_t WEAD_f; + }; + union { + __IO uint32_t ESCLR; + stc_exbus_esclr_field_t ESCLR_f; + }; + union { + __IO uint32_t AMODE; + stc_exbus_amode_field_t AMODE_f; + }; +}FM4_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + }; + struct { + union { + __IO uint8_t HCNT0; + stc_usb_hcnt0_field_t HCNT0_f; + }; + union { + __IO uint8_t HCNT1; + stc_usb_hcnt1_field_t HCNT1_f; + }; + }; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + }; + struct { + union { + __IO uint8_t HRTIMER0; + stc_usb_hrtimer0_field_t HRTIMER0_f; + }; + union { + __IO uint8_t HRTIMER1; + stc_usb_hrtimer1_field_t HRTIMER1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + }; + struct { + union { + __IO uint8_t HEOF0; + stc_usb_heof0_field_t HEOF0_f; + }; + union { + __IO uint8_t HEOF1; + stc_usb_heof1_field_t HEOF1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + }; + struct { + union { + __IO uint8_t HFRAME0; + stc_usb_hframe0_field_t HFRAME0_f; + }; + union { + __IO uint8_t HFRAME1; + stc_usb_hframe1_field_t HFRAME1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + }; + uint8_t RESERVED19[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + }; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM4_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + }; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + }; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + }; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + }; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + }; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + }; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + }; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + }; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM4_DMAC_TypeDef; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN channel 0 registers */ +typedef struct +{ + union { + __IO uint16_t CTRLR; + stc_can_ctrlr_field_t CTRLR_f; + }; + union { + __IO uint16_t STATR; + stc_can_statr_field_t STATR_f; + }; + union { + __IO uint16_t ERRCNT; + stc_can_errcnt_field_t ERRCNT_f; + }; + union { + __IO uint16_t BTR; + stc_can_btr_field_t BTR_f; + }; + union { + __IO uint16_t INTR; + stc_can_intr_field_t INTR_f; + }; + union { + __IO uint16_t TESTR; + stc_can_testr_field_t TESTR_f; + }; + union { + __IO uint16_t BRPER; + stc_can_brper_field_t BRPER_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint16_t IF1CREQ; + stc_can_if1creq_field_t IF1CREQ_f; + }; + union { + __IO uint16_t IF1CMSK; + stc_can_if1cmsk_field_t IF1CMSK_f; + }; + union { + union { + __IO uint32_t IF1MSK; + stc_can_if1msk_field_t IF1MSK_f; + }; + struct { + __IO uint16_t IF1MSK1; + union { + __IO uint16_t IF1MSK2; + stc_can_if1msk2_field_t IF1MSK2_f; + }; + }; + }; + union { + union { + __IO uint32_t IF1ARB; + stc_can_if1arb_field_t IF1ARB_f; + }; + struct { + __IO uint16_t IF1ARB1; + union { + __IO uint16_t IF1ARB2; + stc_can_if1arb2_field_t IF1ARB2_f; + }; + }; + }; + union { + __IO uint16_t IF1MCTR; + stc_can_if1mctr_field_t IF1MCTR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + struct { + __IO uint16_t IF1DTA1_L; + __IO uint16_t IF1DTA2_L; + }; + }; + union { + __IO uint32_t IF1DTB_L; + struct { + __IO uint16_t IF1DTB1_L; + __IO uint16_t IF1DTB2_L; + }; + }; + uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + struct { + __IO uint16_t IF1DTA2_B; + __IO uint16_t IF1DTA1_B; + }; + }; + union { + __IO uint32_t IF1DTB_B; + struct { + __IO uint16_t IF1DTB2_B; + __IO uint16_t IF1DTB1_B; + }; + }; + uint8_t RESERVED3[8]; + union { + __IO uint16_t IF2CREQ; + stc_can_if2creq_field_t IF2CREQ_f; + }; + union { + __IO uint16_t IF2CMSK; + stc_can_if2cmsk_field_t IF2CMSK_f; + }; + union { + union { + __IO uint32_t IF2MSK; + stc_can_if2msk_field_t IF2MSK_f; + }; + struct { + __IO uint16_t IF2MSK1; + union { + __IO uint16_t IF2MSK2; + stc_can_if2msk2_field_t IF2MSK2_f; + }; + }; + }; + union { + __IO uint32_t IF2ARB; + struct { + __IO uint16_t IF2ARB1; + union { + __IO uint16_t IF2ARB2; + stc_can_if2arb2_field_t IF2ARB2_f; + }; + }; + }; + union { + __IO uint16_t IF2MCTR; + stc_can_if2mctr_field_t IF2MCTR_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + struct { + __IO uint16_t IF2DTA1_L; + __IO uint16_t IF2DTA2_L; + }; + }; + union { + __IO uint32_t IF2DTB_L; + struct { + __IO uint16_t IF2DTB1_L; + __IO uint16_t IF2DTB2_L; + }; + }; + uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + struct { + __IO uint16_t IF2DTA2_B; + __IO uint16_t IF2DTA1_B; + }; + }; + union { + __IO uint32_t IF2DTB_B; + struct { + __IO uint16_t IF2DTB2_B; + __IO uint16_t IF2DTB1_B; + }; + }; + uint8_t RESERVED6[24]; + union { + union { + __IO uint32_t TREQR; + stc_can_treqr_field_t TREQR_f; + }; + struct { + union { + __IO uint16_t TREQR1; + stc_can_treqr1_field_t TREQR1_f; + }; + union { + __IO uint16_t TREQR2; + stc_can_treqr2_field_t TREQR2_f; + }; + }; + }; + uint8_t RESERVED7[12]; + union { + union { + __IO uint32_t NEWDT; + stc_can_newdt_field_t NEWDT_f; + }; + struct { + union { + __IO uint16_t NEWDT1; + stc_can_newdt1_field_t NEWDT1_f; + }; + __IO uint16_t NEWDT2; + }; + }; + uint8_t RESERVED8[12]; + union { + union { + __IO uint32_t INTPND; + stc_can_intpnd_field_t INTPND_f; + }; + struct { + union { + __IO uint16_t INTPND1; + stc_can_intpnd1_field_t INTPND1_f; + }; + union { + __IO uint16_t INTPND2; + stc_can_intpnd2_field_t INTPND2_f; + }; + }; + }; + uint8_t RESERVED9[12]; + union { + union { + __IO uint32_t MSGVAL; + stc_can_msgval_field_t MSGVAL_f; + }; + struct { + union { + __IO uint16_t MSGVAL1; + stc_can_msgval1_field_t MSGVAL1_f; + }; + union { + __IO uint16_t MSGVAL2; + stc_can_msgval2_field_t MSGVAL2_f; + }; + }; + }; +}FM4_CAN_TypeDef; + +/****************************************************************************** + * SDIF_MODULE + ******************************************************************************/ +/* SD interface registers */ + + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM4_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM4_WORKFLASH_BASE (0x200C0000UL) /* Work Flash Base */ +#define FM4_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM4_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM4_WORKFLASH_IF_BASE (FM4_WORKFLASH_BASE + 0x20000UL) /* Work Flash interface registers */ +#define FM4_FLASH_IF_BASE (FM4_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM4_UNIQUE_ID_BASE (FM4_PERIPH_BASE + 0x00200UL) /* Unique ID registers */ +#define FM4_ECC_CAPTURE_BASE (FM4_PERIPH_BASE + 0x00300UL) /* ECC Capture address registers */ +#define FM4_CRG_BASE (FM4_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM4_HWWDT_BASE (FM4_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM4_SWWDT_BASE (FM4_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM4_DTIM_BASE (FM4_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM4_MFT0_FRT_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM4_MFT0_OCU_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM4_MFT0_WFG_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM4_MFT0_ICU_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM4_MFT0_ADCMP_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM4_MFT1_FRT_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM4_MFT1_OCU_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM4_MFT1_WFG_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM4_MFT1_ICU_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM4_MFT1_ADCMP_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM4_MFT2_FRT_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Free Running Timer registers */ +#define FM4_MFT2_OCU_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ +#define FM4_MFT2_WFG_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define FM4_MFT2_ICU_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ +#define FM4_MFT2_ADCMP_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define FM4_MFT_PPG_BASE (FM4_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM4_BT0_PPG_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM4_BT0_PWM_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM4_BT0_RT_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM4_BT0_PWC_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM4_BT1_PPG_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM4_BT1_PWM_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM4_BT1_RT_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM4_BT1_PWC_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM4_BT2_PPG_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM4_BT2_PWM_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM4_BT2_RT_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM4_BT2_PWC_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM4_BT3_PPG_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM4_BT3_PWM_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM4_BT3_RT_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM4_BT3_PWC_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM4_BT4_PPG_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM4_BT4_PWM_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM4_BT4_RT_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM4_BT4_PWC_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM4_BT5_PPG_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM4_BT5_PWM_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM4_BT5_RT_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM4_BT5_PWC_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM4_BT6_PPG_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM4_BT6_PWM_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM4_BT6_RT_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM4_BT6_PWC_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM4_BT7_PPG_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM4_BT7_PWM_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM4_BT7_RT_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM4_BT7_PWC_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM4_BTIOSEL03_BASE (FM4_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM4_BTIOSEL47_BASE (FM4_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM4_BT8_PPG_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ +#define FM4_BT8_PWM_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ +#define FM4_BT8_RT_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ +#define FM4_BT8_PWC_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ +#define FM4_BT9_PPG_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ +#define FM4_BT9_PWM_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ +#define FM4_BT9_RT_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ +#define FM4_BT9_PWC_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ +#define FM4_BT10_PPG_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ +#define FM4_BT10_PWM_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ +#define FM4_BT10_RT_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ +#define FM4_BT10_PWC_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ +#define FM4_BT11_PPG_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ +#define FM4_BT11_PWM_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ +#define FM4_BT11_RT_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ +#define FM4_BT11_PWC_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ +#define FM4_BT12_PPG_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ +#define FM4_BT12_PWM_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ +#define FM4_BT12_RT_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ +#define FM4_BT12_PWC_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ +#define FM4_BT13_PPG_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ +#define FM4_BT13_PWM_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ +#define FM4_BT13_RT_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ +#define FM4_BT13_PWC_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ +#define FM4_BT14_PPG_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ +#define FM4_BT14_PWM_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ +#define FM4_BT14_RT_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ +#define FM4_BT14_PWC_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ +#define FM4_BT15_PPG_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ +#define FM4_BT15_PWM_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ +#define FM4_BT15_RT_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ +#define FM4_BT15_PWC_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ +#define FM4_BTIOSEL8B_BASE (FM4_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ +#define FM4_BTIOSELCF_BASE (FM4_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ +#define FM4_SBSSR_BASE (FM4_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM4_QPRC0_BASE (FM4_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM4_QPRC1_BASE (FM4_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM4_QPRC2_BASE (FM4_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ +#define FM4_QPRC3_BASE (FM4_PERIPH_BASE + 0x260C0UL) /* Quad position and revolution counter channel 3 registers */ +#define FM4_QPRC0_NF_BASE (FM4_PERIPH_BASE + 0x26100UL) /* Quad position and revolution counter channel 0 noise filter registers */ +#define FM4_QPRC1_NF_BASE (FM4_PERIPH_BASE + 0x26110UL) /* Quad position and revolution counter channel 0 noise filter registers */ +#define FM4_QPRC2_NF_BASE (FM4_PERIPH_BASE + 0x26120UL) /* Quad position and revolution counter channel 0 noise filter registers */ +#define FM4_QPRC3_NF_BASE (FM4_PERIPH_BASE + 0x26130UL) /* Quad position and revolution counter channel 0 noise filter registers */ +#define FM4_ADC0_BASE (FM4_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM4_ADC1_BASE (FM4_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM4_ADC2_BASE (FM4_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM4_DAC0_BASE (FM4_PERIPH_BASE + 0x33000UL) /* 12-bit DAC uint 0 registers */ +#define FM4_DAC1_BASE (FM4_PERIPH_BASE + 0x33008UL) /* 12-bit DAC uint 1 registers */ +#define FM4_CRTRIM_BASE (FM4_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM4_EXTI_BASE (FM4_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM4_INTREQ_BASE (FM4_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM4_IRQSEL_BASE (FM4_PERIPH_BASE + 0x31110UL) /* Interrupt Selector */ +#define FM4_GPIO_BASE (FM4_PERIPH_BASE + 0x6F000UL) /* General purpose I/O registers */ +#define FM4_LVD_BASE (FM4_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM4_DS_BASE (FM4_PERIPH_BASE + 0x35100UL) /* Deep standby mode registers */ +#define FM4_USBCLK_BASE (FM4_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM4_CANPRES_BASE (FM4_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ +#define FM4_MFS0_BASE (FM4_PERIPH_BASE + 0x38000UL) /* MFS channel 0 registers */ +#define FM4_MFS1_BASE (FM4_PERIPH_BASE + 0x38100UL) /* MFS channel 1 registers */ +#define FM4_MFS2_BASE (FM4_PERIPH_BASE + 0x38200UL) /* MFS channel 2 registers */ +#define FM4_MFS3_BASE (FM4_PERIPH_BASE + 0x38300UL) /* MFS channel 3 registers */ +#define FM4_MFS4_BASE (FM4_PERIPH_BASE + 0x38400UL) /* MFS channel 4 registers */ +#define FM4_MFS5_BASE (FM4_PERIPH_BASE + 0x38500UL) /* MFS channel 5 registers */ +#define FM4_MFS6_BASE (FM4_PERIPH_BASE + 0x38600UL) /* MFS channel 6 registers */ +#define FM4_MFS7_BASE (FM4_PERIPH_BASE + 0x38700UL) /* MFS channel 7 registers */ +#define FM4_MFS8_BASE (FM4_PERIPH_BASE + 0x38800UL) /* MFS channel 8 registers */ +#define FM4_MFS9_BASE (FM4_PERIPH_BASE + 0x38900UL) /* MFS channel 9 registers */ +#define FM4_MFS10_BASE (FM4_PERIPH_BASE + 0x38A00UL) /* MFS channel 10 registers */ +#define FM4_MFS11_BASE (FM4_PERIPH_BASE + 0x38B00UL) /* MFS channel 11 registers */ +#define FM4_MFS12_BASE (FM4_PERIPH_BASE + 0x38C00UL) /* MFS channel 12 registers */ +#define FM4_MFS13_BASE (FM4_PERIPH_BASE + 0x38D00UL) /* MFS channel 13 registers */ +#define FM4_MFS14_BASE (FM4_PERIPH_BASE + 0x38E00UL) /* MFS channel 14 registers */ +#define FM4_MFS15_BASE (FM4_PERIPH_BASE + 0x38F00UL) /* MFS channel 15 registers */ +#define FM4_MFS_NFC_BASE (FM4_PERIPH_BASE + 0x38FFFF0) /* JUST A RANDOM ADDRESS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ +#define FM4_CRC_BASE (FM4_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM4_WC_BASE (FM4_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM4_RTC_BASE (FM4_PERIPH_BASE + 0x3B100UL) /* RTC registers */ +#define FM4_LCR_BASE (FM4_PERIPH_BASE + 0x3C000UL) /* Low-speed CR prescaler registers */ +#define FM4_CLK_GATING_BASE (FM4_PERIPH_BASE + 0x3C100UL) /* Peripheral Clock Gating registers */ +#define FM4_PLL_CONTROL_BASE (FM4_PERIPH_BASE + 0x3C800UL) /* Main PLL Control registers */ +#define FM4_EXBUS_BASE (FM4_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM4_USB0_BASE (FM4_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM4_DMAC_BASE (FM4_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM4_DSTC_BASE (FM4_PERIPH_BASE + 0x61000UL) /* DSTC controller */ +#define FM4_CAN0_BASE (FM4_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ +#define FM4_CAN1_BASE (FM4_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ +#define FM4_SDIF_BASE (FM4_PERIPH_BASE + 0x6E000UL) /* SDIF registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM4_WORKFLASH_IF ((FM4_WORKFLASH_IF_TypeDef *)FM4_WORKFLASH_IF_BASE) +#define FM4_FLASH_IF ((FM4_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) +#define FM4_UNIQUE_ID ((FM4_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) +#define FM4_ECC_CAPTURE ((FM4_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) +#define FM4_CRG ((FM4_CRG_TypeDef *)FM4_CRG_BASE) +#define FM4_HWWDT ((FM4_HWWDT_TypeDef *)FM4_HWWDT_BASE) +#define FM4_SWWDT ((FM4_SWWDT_TypeDef *)FM4_SWWDT_BASE) +#define FM4_DTIM ((FM4_DTIM_TypeDef *)FM4_DTIM_BASE) +#define FM4_MFT0_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT0_FRT_BASE) +#define FM4_MFT0_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT0_OCU_BASE) +#define FM4_MFT0_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT0_WFG_BASE) +#define FM4_MFT0_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT0_ICU_BASE) +#define FM4_MFT0_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT0_ADCMP_BASE) +#define FM4_MFT1_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT1_FRT_BASE) +#define FM4_MFT1_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT1_OCU_BASE) +#define FM4_MFT1_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT1_WFG_BASE) +#define FM4_MFT1_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT1_ICU_BASE) +#define FM4_MFT1_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT1_ADCMP_BASE) +#define FM4_MFT2_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT2_FRT_BASE) +#define FM4_MFT2_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT2_OCU_BASE) +#define FM4_MFT2_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT2_WFG_BASE) +#define FM4_MFT2_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT2_ICU_BASE) +#define FM4_MFT2_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT2_ADCMP_BASE) +#define FM4_MFT_PPG ((FM4_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) +#define FM4_BT0_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT0_PPG_BASE) +#define FM4_BT0_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT0_PWM_BASE) +#define FM4_BT0_RT ((FM4_BT_RT_TypeDef *)FM4_BT0_RT_BASE) +#define FM4_BT0_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT0_PWC_BASE) +#define FM4_BT1_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT1_PPG_BASE) +#define FM4_BT1_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT1_PWM_BASE) +#define FM4_BT1_RT ((FM4_BT_RT_TypeDef *)FM4_BT1_RT_BASE) +#define FM4_BT1_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT1_PWC_BASE) +#define FM4_BT2_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT2_PPG_BASE) +#define FM4_BT2_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT2_PWM_BASE) +#define FM4_BT2_RT ((FM4_BT_RT_TypeDef *)FM4_BT2_RT_BASE) +#define FM4_BT2_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT2_PWC_BASE) +#define FM4_BT3_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT3_PPG_BASE) +#define FM4_BT3_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT3_PWM_BASE) +#define FM4_BT3_RT ((FM4_BT_RT_TypeDef *)FM4_BT3_RT_BASE) +#define FM4_BT3_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT3_PWC_BASE) +#define FM4_BT4_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT4_PPG_BASE) +#define FM4_BT4_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT4_PWM_BASE) +#define FM4_BT4_RT ((FM4_BT_RT_TypeDef *)FM4_BT4_RT_BASE) +#define FM4_BT4_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT4_PWC_BASE) +#define FM4_BT5_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT5_PPG_BASE) +#define FM4_BT5_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT5_PWM_BASE) +#define FM4_BT5_RT ((FM4_BT_RT_TypeDef *)FM4_BT5_RT_BASE) +#define FM4_BT5_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT5_PWC_BASE) +#define FM4_BT6_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT6_PPG_BASE) +#define FM4_BT6_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT6_PWM_BASE) +#define FM4_BT6_RT ((FM4_BT_RT_TypeDef *)FM4_BT6_RT_BASE) +#define FM4_BT6_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT6_PWC_BASE) +#define FM4_BT7_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT7_PPG_BASE) +#define FM4_BT7_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT7_PWM_BASE) +#define FM4_BT7_RT ((FM4_BT_RT_TypeDef *)FM4_BT7_RT_BASE) +#define FM4_BT7_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT7_PWC_BASE) +#define FM4_BTIOSEL03 ((FM4_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) +#define FM4_BTIOSEL47 ((FM4_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) +#define FM4_BT8_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT8_PPG_BASE) +#define FM4_BT8_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT8_PWM_BASE) +#define FM4_BT8_RT ((FM4_BT_RT_TypeDef *)FM4_BT8_RT_BASE) +#define FM4_BT8_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT8_PWC_BASE) +#define FM4_BT9_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT9_PPG_BASE) +#define FM4_BT9_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT9_PWM_BASE) +#define FM4_BT9_RT ((FM4_BT_RT_TypeDef *)FM4_BT9_RT_BASE) +#define FM4_BT9_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT9_PWC_BASE) +#define FM4_BT10_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT10_PPG_BASE) +#define FM4_BT10_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT10_PWM_BASE) +#define FM4_BT10_RT ((FM4_BT_RT_TypeDef *)FM4_BT10_RT_BASE) +#define FM4_BT10_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT10_PWC_BASE) +#define FM4_BT11_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT11_PPG_BASE) +#define FM4_BT11_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT11_PWM_BASE) +#define FM4_BT11_RT ((FM4_BT_RT_TypeDef *)FM4_BT11_RT_BASE) +#define FM4_BT11_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT11_PWC_BASE) +#define FM4_BT12_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT12_PPG_BASE) +#define FM4_BT12_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT12_PWM_BASE) +#define FM4_BT12_RT ((FM4_BT_RT_TypeDef *)FM4_BT12_RT_BASE) +#define FM4_BT12_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT12_PWC_BASE) +#define FM4_BT13_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT13_PPG_BASE) +#define FM4_BT13_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT13_PWM_BASE) +#define FM4_BT13_RT ((FM4_BT_RT_TypeDef *)FM4_BT13_RT_BASE) +#define FM4_BT13_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT13_PWC_BASE) +#define FM4_BT14_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT14_PPG_BASE) +#define FM4_BT14_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT14_PWM_BASE) +#define FM4_BT14_RT ((FM4_BT_RT_TypeDef *)FM4_BT14_RT_BASE) +#define FM4_BT14_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT14_PWC_BASE) +#define FM4_BT15_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT15_PPG_BASE) +#define FM4_BT15_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT15_PWM_BASE) +#define FM4_BT15_RT ((FM4_BT_RT_TypeDef *)FM4_BT15_RT_BASE) +#define FM4_BT15_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT15_PWC_BASE) +#define FM4_BTIOSEL8B ((FM4_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) +#define FM4_BTIOSELCF ((FM4_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) +#define FM4_SBSSR ((FM4_SBSSR_TypeDef *)FM4_SBSSR_BASE) +#define FM4_QPRC0 ((FM4_QPRC_TypeDef *)FM4_QPRC0_BASE) +#define FM4_QPRC1 ((FM4_QPRC_TypeDef *)FM4_QPRC1_BASE) +#define FM4_QPRC2 ((FM4_QPRC_TypeDef *)FM4_QPRC2_BASE) +#define FM4_QPRC3 ((FM4_QPRC_TypeDef *)FM4_QPRC3_BASE) +#define FM4_QPRC0_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) +#define FM4_QPRC1_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) +#define FM4_QPRC2_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) +#define FM4_QPRC3_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) +#define FM4_ADC0 ((FM4_ADC_TypeDef *)FM4_ADC0_BASE) +#define FM4_ADC1 ((FM4_ADC_TypeDef *)FM4_ADC1_BASE) +#define FM4_ADC2 ((FM4_ADC_TypeDef *)FM4_ADC2_BASE) +#define FM4_DAC0 ((FM4_DAC_TypeDef *)FM4_DAC0_BASE) +#define FM4_DAC1 ((FM4_DAC_TypeDef *)FM4_DAC1_BASE) +#define FM4_CRTRIM ((FM4_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) +#define FM4_EXTI ((FM4_EXTI_TypeDef *)FM4_EXTI_BASE) +#define FM4_INTREQ ((FM4_INTREQ_TypeDef *)FM4_INTREQ_BASE) +#define FM4_IRQSEL ((FM4_IRQSEL_TypeDef *)FM4_IRQSEL_BASE) +#define FM4_GPIO ((FM4_GPIO_TypeDef *)FM4_GPIO_BASE) +#define FM4_LVD ((FM4_LVD_TypeDef *)FM4_LVD_BASE) +#define FM4_DS ((FM4_DS_TypeDef *)FM4_DS_BASE) +#define FM4_USBCLK ((FM4_USBCLK_TypeDef *)FM4_USBCLK_BASE) +#define FM4_CANPRES ((FM4_CANPRE_TypeDef *)FM4_CANPRES_BASE) +#define FM4_MFS0 ((FM4_MFS_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS1 ((FM4_MFS_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS2 ((FM4_MFS_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS3 ((FM4_MFS_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS4 ((FM4_MFS_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS5 ((FM4_MFS_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS6 ((FM4_MFS_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS7 ((FM4_MFS_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS8 ((FM4_MFS_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS9 ((FM4_MFS_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS10 ((FM4_MFS_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS11 ((FM4_MFS_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS12 ((FM4_MFS_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS13 ((FM4_MFS_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS14 ((FM4_MFS_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS15 ((FM4_MFS_TypeDef *)FM4_MFS15_BASE) +#define FM4_CRC ((FM4_CRC_TypeDef *)FM4_CRC_BASE) +#define FM4_WC ((FM4_WC_TypeDef *)FM4_WC_BASE) +#define FM4_RTC ((FM4_RTC_TypeDef *)FM4_RTC_BASE) +#define FM4_LCR ((FM4_LCR_TypeDef *)FM4_LCR_BASE) +#define FM4_CLK_GATING ((FM4_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) +#define FM4_PLL_CONTROL ((FM4_PLL_CONTROL_TypeDef *)FM4_PLL_CONTROL_BASE) +#define FM4_EXBUS ((FM4_EXBUS_TypeDef *)FM4_EXBUS_BASE) +#define FM4_USB0 ((FM4_USB_TypeDef *)FM4_USB0_BASE) +#define FM4_DMAC ((FM4_DMAC_TypeDef *)FM4_DMAC_BASE) +#define FM4_DSTC ((FM4_DSTC_TypeDef *)FM4_DSTC_BASE) +#define FM4_CAN0 ((FM4_CAN_TypeDef *)FM4_CAN0_BASE) +#define FM4_CAN1 ((FM4_CAN_TypeDef *)FM4_CAN1_BASE) +#define FM4_SDIF ((FM4_SDIF_TypeDef *)FM4_SDIF_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Work Flash interface registers */ +#define bFM4_WORKFLASH_IF_WFASZR_ASZ *((volatile unsigned int*)(0x23C00000UL)) +#define bFM4_WORKFLASH_IF_WFRWTR_RWT0 *((volatile unsigned int*)(0x23C00080UL)) +#define bFM4_WORKFLASH_IF_WFRWTR_RWT1 *((volatile unsigned int*)(0x23C00084UL)) +#define bFM4_WORKFLASH_IF_WFRWTR_RWT2 *((volatile unsigned int*)(0x23C00088UL)) +#define bFM4_WORKFLASH_IF_WFSTR_RDY *((volatile unsigned int*)(0x23C00100UL)) +#define bFM4_WORKFLASH_IF_WFSTR_HNG *((volatile unsigned int*)(0x23C00104UL)) + +/* Flash interface registers */ +#define bFM4_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM4_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM4_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM4_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM4_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM4_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM4_FLASH_IF_FSTR_ERR *((volatile unsigned int*)(0x42000108UL)) +#define bFM4_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM4_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM4_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM4_FLASH_IF_FBFCR_BE *((volatile unsigned int*)(0x42000280UL)) +#define bFM4_FLASH_IF_FBFCR_BS *((volatile unsigned int*)(0x42000284UL)) +#define bFM4_FLASH_IF_FICR_RDYIE *((volatile unsigned int*)(0x42000400UL)) +#define bFM4_FLASH_IF_FICR_HANGIE *((volatile unsigned int*)(0x42000404UL)) +#define bFM4_FLASH_IF_FICR_ERRIE *((volatile unsigned int*)(0x42000408UL)) +#define bFM4_FLASH_IF_FISR_RDYIF *((volatile unsigned int*)(0x42000480UL)) +#define bFM4_FLASH_IF_FISR_HANGIF *((volatile unsigned int*)(0x42000484UL)) +#define bFM4_FLASH_IF_FISR_ERRIF *((volatile unsigned int*)(0x42000488UL)) +#define bFM4_FLASH_IF_FICLR_RDYIC *((volatile unsigned int*)(0x42000500UL)) +#define bFM4_FLASH_IF_FICLR_HANGIC *((volatile unsigned int*)(0x42000504UL)) +#define bFM4_FLASH_IF_FICLR_ERRIC *((volatile unsigned int*)(0x42000508UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM4_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) +#define bFM4_FLASH_IF_CRTRMM_TTRMM0 *((volatile unsigned int*)(0x42002040UL)) +#define bFM4_FLASH_IF_CRTRMM_TTRMM1 *((volatile unsigned int*)(0x42002044UL)) +#define bFM4_FLASH_IF_CRTRMM_TTRMM2 *((volatile unsigned int*)(0x42002048UL)) +#define bFM4_FLASH_IF_CRTRMM_TTRMM3 *((volatile unsigned int*)(0x4200204CUL)) +#define bFM4_FLASH_IF_CRTRMM_TTRMM4 *((volatile unsigned int*)(0x42002050UL)) + +/* Unique ID registers */ +#define bFM4_UNIQUE_ID_UIDR0_UID0 *((volatile unsigned int*)(0x42004010UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID1 *((volatile unsigned int*)(0x42004014UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID2 *((volatile unsigned int*)(0x42004018UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID3 *((volatile unsigned int*)(0x4200401CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID4 *((volatile unsigned int*)(0x42004020UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID5 *((volatile unsigned int*)(0x42004024UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID6 *((volatile unsigned int*)(0x42004028UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID7 *((volatile unsigned int*)(0x4200402CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID8 *((volatile unsigned int*)(0x42004030UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID9 *((volatile unsigned int*)(0x42004034UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID10 *((volatile unsigned int*)(0x42004038UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID11 *((volatile unsigned int*)(0x4200403CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID12 *((volatile unsigned int*)(0x42004040UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID13 *((volatile unsigned int*)(0x42004044UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID14 *((volatile unsigned int*)(0x42004048UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID15 *((volatile unsigned int*)(0x4200404CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID16 *((volatile unsigned int*)(0x42004050UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID17 *((volatile unsigned int*)(0x42004054UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID18 *((volatile unsigned int*)(0x42004058UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID19 *((volatile unsigned int*)(0x4200405CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID20 *((volatile unsigned int*)(0x42004060UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID21 *((volatile unsigned int*)(0x42004064UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID22 *((volatile unsigned int*)(0x42004068UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID23 *((volatile unsigned int*)(0x4200406CUL)) +#define bFM4_UNIQUE_ID_UIDR0_UID24 *((volatile unsigned int*)(0x42004070UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID25 *((volatile unsigned int*)(0x42004074UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID26 *((volatile unsigned int*)(0x42004078UL)) +#define bFM4_UNIQUE_ID_UIDR0_UID27 *((volatile unsigned int*)(0x4200407CUL)) +#define bFM4_UNIQUE_ID_UIDR1_UID28 *((volatile unsigned int*)(0x42004080UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID29 *((volatile unsigned int*)(0x42004084UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID30 *((volatile unsigned int*)(0x42004088UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID31 *((volatile unsigned int*)(0x4200408CUL)) +#define bFM4_UNIQUE_ID_UIDR1_UID32 *((volatile unsigned int*)(0x42004090UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID33 *((volatile unsigned int*)(0x42004094UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID34 *((volatile unsigned int*)(0x42004098UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID35 *((volatile unsigned int*)(0x4200409CUL)) +#define bFM4_UNIQUE_ID_UIDR1_UID36 *((volatile unsigned int*)(0x420040A0UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID37 *((volatile unsigned int*)(0x420040A4UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID38 *((volatile unsigned int*)(0x420040A8UL)) +#define bFM4_UNIQUE_ID_UIDR1_UID39 *((volatile unsigned int*)(0x420040ACUL)) +#define bFM4_UNIQUE_ID_UIDR1_UID40 *((volatile unsigned int*)(0x420040B0UL)) + +/* ECC_CAPTURE registers */ +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD0 *((volatile unsigned int*)(0x42006000UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD1 *((volatile unsigned int*)(0x42006004UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD2 *((volatile unsigned int*)(0x42006008UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD3 *((volatile unsigned int*)(0x4200600CUL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD4 *((volatile unsigned int*)(0x42006010UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD5 *((volatile unsigned int*)(0x42006014UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD6 *((volatile unsigned int*)(0x42006018UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD7 *((volatile unsigned int*)(0x4200601CUL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD8 *((volatile unsigned int*)(0x42006020UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD9 *((volatile unsigned int*)(0x42006024UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD10 *((volatile unsigned int*)(0x42006028UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD11 *((volatile unsigned int*)(0x4200602CUL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD12 *((volatile unsigned int*)(0x42006030UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD13 *((volatile unsigned int*)(0x42006034UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD14 *((volatile unsigned int*)(0x42006038UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD15 *((volatile unsigned int*)(0x4200603CUL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD16 *((volatile unsigned int*)(0x42006040UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD17 *((volatile unsigned int*)(0x42006044UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD18 *((volatile unsigned int*)(0x42006048UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD19 *((volatile unsigned int*)(0x4200604CUL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD20 *((volatile unsigned int*)(0x42006050UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD21 *((volatile unsigned int*)(0x42006054UL)) +#define bFM4_ECC_CAPTURE_FERRAD_ERRAD22 *((volatile unsigned int*)(0x42006058UL)) + +/* Clock and reset registers */ +#define bFM4_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM4_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM4_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM4_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM4_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM4_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM4_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM4_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM4_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM4_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM4_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM4_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM4_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM4_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM4_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM4_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM4_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM4_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM4_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM4_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM4_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM4_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM4_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM4_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM4_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM4_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM4_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM4_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM4_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM4_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM4_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM4_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM4_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM4_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM4_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM4_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) +#define bFM4_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) +#define bFM4_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM4_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM4_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM4_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM4_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM4_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM4_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM4_CRG_CSW_TMR_SOWT3 *((volatile unsigned int*)(0x4220061CUL)) +#define bFM4_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM4_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM4_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM4_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM4_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM4_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM4_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM4_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM4_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM4_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM4_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM4_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM4_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM4_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM4_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM4_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM4_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM4_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) +#define bFM4_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM4_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM4_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM4_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM4_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM4_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM4_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM4_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM4_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM4_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM4_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM4_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM4_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM4_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM4_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM4_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM4_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM4_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM4_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM4_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM4_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM4_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM4_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM4_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM4_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM4_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM4_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM4_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM4_SWWDT_WDOGCONTROL_TWD0 *((volatile unsigned int*)(0x42240108UL)) +#define bFM4_SWWDT_WDOGCONTROL_TWD1 *((volatile unsigned int*)(0x4224010CUL)) +#define bFM4_SWWDT_WDOGCONTROL_SPM *((volatile unsigned int*)(0x42240110UL)) +#define bFM4_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) +#define bFM4_SWWDT_WDOGSPMC_TGR *((volatile unsigned int*)(0x42240300UL)) + +/* Dual timer 1/2 registers */ +#define bFM4_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM4_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM4_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM4_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM4_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM4_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM4_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM4_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM4_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM4_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM4_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM4_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM4_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM4_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM4_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM4_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM4_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM4_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM4_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42402900UL)) +#define bFM4_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42402904UL)) +#define bFM4_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42402908UL)) +#define bFM4_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240290cUL)) +#define bFM4_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42402910UL)) +#define bFM4_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42402914UL)) +#define bFM4_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42402918UL)) +#define bFM4_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240291cUL)) +#define bFM4_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42402920UL)) +#define bFM4_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42402924UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42402934UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42402938UL)) +#define bFM4_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240293cUL)) +#define bFM4_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42402a80UL)) +#define bFM4_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42402a84UL)) +#define bFM4_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42402a88UL)) +#define bFM4_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42402a8cUL)) +#define bFM4_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42402a90UL)) +#define bFM4_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42402a94UL)) +#define bFM4_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42402a98UL)) +#define bFM4_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42402a9cUL)) +#define bFM4_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42402aa0UL)) +#define bFM4_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42402aa4UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42402ab4UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42402ab8UL)) +#define bFM4_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42402abcUL)) +#define bFM4_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42402c00UL)) +#define bFM4_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42402c04UL)) +#define bFM4_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42402c08UL)) +#define bFM4_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42402c0cUL)) +#define bFM4_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42402c10UL)) +#define bFM4_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42402c14UL)) +#define bFM4_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42402c18UL)) +#define bFM4_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42402c1cUL)) +#define bFM4_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42402c20UL)) +#define bFM4_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42402c24UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42402c34UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42402c38UL)) +#define bFM4_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42402c3cUL)) +#define bFM4_MFT0_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42402c80UL)) +#define bFM4_MFT0_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42402c84UL)) +#define bFM4_MFT0_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42402c88UL)) +#define bFM4_MFT0_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42402c8cUL)) +#define bFM4_MFT0_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42402c90UL)) +#define bFM4_MFT0_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42402c94UL)) +#define bFM4_MFT0_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42402c98UL)) +#define bFM4_MFT0_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42402c9cUL)) +#define bFM4_MFT0_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42402ca0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42402cc0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42402cc4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42402cc8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42402cccUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42402cd0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42402cd4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42402cd8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42402cdcUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42402ce0UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM4_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42402300UL)) +#define bFM4_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42402304UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42402310UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42402314UL)) +#define bFM4_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42402318UL)) +#define bFM4_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240231cUL)) +#define bFM4_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42402320UL)) +#define bFM4_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42402324UL)) +#define bFM4_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42402330UL)) +#define bFM4_MFT0_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4240233cUL)) +#define bFM4_MFT0_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42402380UL)) +#define bFM4_MFT0_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42402384UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42402390UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42402394UL)) +#define bFM4_MFT0_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42402398UL)) +#define bFM4_MFT0_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4240239cUL)) +#define bFM4_MFT0_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424023a0UL)) +#define bFM4_MFT0_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424023a4UL)) +#define bFM4_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424023b0UL)) +#define bFM4_MFT0_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424023bcUL)) +#define bFM4_MFT0_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42402400UL)) +#define bFM4_MFT0_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42402404UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42402410UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42402414UL)) +#define bFM4_MFT0_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42402418UL)) +#define bFM4_MFT0_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4240241cUL)) +#define bFM4_MFT0_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42402420UL)) +#define bFM4_MFT0_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42402424UL)) +#define bFM4_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42402430UL)) +#define bFM4_MFT0_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4240243cUL)) +#define bFM4_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424024a0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424024a4UL)) +#define bFM4_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424024a8UL)) +#define bFM4_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424024acUL)) +#define bFM4_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424024b0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424024b4UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42402d00UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42402d04UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42402d08UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42402d0cUL)) +#define bFM4_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42402d10UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42402d14UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42402d18UL)) +#define bFM4_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42402d1cUL)) +#define bFM4_MFT0_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42402d20UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42402d24UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42402d28UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42402d2cUL)) +#define bFM4_MFT0_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42402d30UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42402d34UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42402d38UL)) +#define bFM4_MFT0_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42402d3cUL)) +#define bFM4_MFT0_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42402d40UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42402d44UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42402d48UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42402d4cUL)) +#define bFM4_MFT0_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42402d50UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42402d54UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42402d58UL)) +#define bFM4_MFT0_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42402d5cUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM4_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42403480UL)) +#define bFM4_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42403484UL)) +#define bFM4_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42403488UL)) +#define bFM4_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42403498UL)) +#define bFM4_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240349cUL)) +#define bFM4_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424034a0UL)) +#define bFM4_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424034a4UL)) +#define bFM4_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424034a8UL)) +#define bFM4_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424034acUL)) +#define bFM4_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42403500UL)) +#define bFM4_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42403504UL)) +#define bFM4_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42403508UL)) +#define bFM4_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42403518UL)) +#define bFM4_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240351cUL)) +#define bFM4_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42403520UL)) +#define bFM4_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42403524UL)) +#define bFM4_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42403528UL)) +#define bFM4_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240352cUL)) +#define bFM4_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42403580UL)) +#define bFM4_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42403584UL)) +#define bFM4_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42403588UL)) +#define bFM4_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42403598UL)) +#define bFM4_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240359cUL)) +#define bFM4_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424035a0UL)) +#define bFM4_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424035a4UL)) +#define bFM4_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424035a8UL)) +#define bFM4_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424035acUL)) +#define bFM4_MFT0_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42403600UL)) +#define bFM4_MFT0_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42403604UL)) +#define bFM4_MFT0_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42403608UL)) +#define bFM4_MFT0_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4240360cUL)) +#define bFM4_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42403610UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42403614UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42403618UL)) +#define bFM4_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240361cUL)) +#define bFM4_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42403620UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42403624UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42403628UL)) +#define bFM4_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240362cUL)) +#define bFM4_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42403630UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42403634UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42403638UL)) +#define bFM4_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240363cUL)) +#define bFM4_MFT0_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42403680UL)) +#define bFM4_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42403684UL)) +#define bFM4_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42403688UL)) +#define bFM4_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240368cUL)) +#define bFM4_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42403690UL)) +#define bFM4_MFT0_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42403694UL)) +#define bFM4_MFT0_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424036a0UL)) +#define bFM4_MFT0_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424036a4UL)) +#define bFM4_MFT0_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424036b0UL)) +#define bFM4_MFT0_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424036b4UL)) +#define bFM4_MFT0_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424036b8UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM4_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42402d80UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42402d84UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42402d88UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42402d8cUL)) +#define bFM4_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42402d90UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42402d94UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42402d98UL)) +#define bFM4_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42402d9cUL)) +#define bFM4_MFT0_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42402da0UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42402da4UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42402da8UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42402dacUL)) +#define bFM4_MFT0_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42402db0UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42402db4UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42402db8UL)) +#define bFM4_MFT0_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42402dbcUL)) +#define bFM4_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42403080UL)) +#define bFM4_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42403084UL)) +#define bFM4_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42403088UL)) +#define bFM4_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4240308cUL)) +#define bFM4_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42403090UL)) +#define bFM4_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42403094UL)) +#define bFM4_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42403098UL)) +#define bFM4_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4240309cUL)) +#define bFM4_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424030a0UL)) +#define bFM4_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424030a4UL)) +#define bFM4_MFT0_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42403100UL)) +#define bFM4_MFT0_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42403104UL)) +#define bFM4_MFT0_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42403108UL)) +#define bFM4_MFT0_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4240310cUL)) +#define bFM4_MFT0_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42403110UL)) +#define bFM4_MFT0_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42403114UL)) +#define bFM4_MFT0_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42403118UL)) +#define bFM4_MFT0_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4240311cUL)) +#define bFM4_MFT0_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42403120UL)) +#define bFM4_MFT0_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42403124UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM4_MFT0_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42403aa0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42403aa4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42403ab0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42403ab4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42403ab8UL)) +#define bFM4_MFT0_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42403abcUL)) +#define bFM4_MFT0_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42403b20UL)) +#define bFM4_MFT0_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42403b24UL)) +#define bFM4_MFT0_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42403b30UL)) +#define bFM4_MFT0_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42403b34UL)) +#define bFM4_MFT0_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42403b38UL)) +#define bFM4_MFT0_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42403b3cUL)) +#define bFM4_MFT0_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42403ba0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42403ba4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42403bb0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42403bb4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42403bb8UL)) +#define bFM4_MFT0_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42403bbcUL)) +#define bFM4_MFT0_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42403c20UL)) +#define bFM4_MFT0_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42403c24UL)) +#define bFM4_MFT0_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42403c30UL)) +#define bFM4_MFT0_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42403c34UL)) +#define bFM4_MFT0_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42403c38UL)) +#define bFM4_MFT0_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42403c3cUL)) +#define bFM4_MFT0_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42403ca0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42403ca4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42403cb0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42403cb4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42403cb8UL)) +#define bFM4_MFT0_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42403cbcUL)) +#define bFM4_MFT0_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42403d20UL)) +#define bFM4_MFT0_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42403d24UL)) +#define bFM4_MFT0_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42403d30UL)) +#define bFM4_MFT0_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42403d34UL)) +#define bFM4_MFT0_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42403d38UL)) +#define bFM4_MFT0_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42403d3cUL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM4_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42422900UL)) +#define bFM4_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42422904UL)) +#define bFM4_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42422908UL)) +#define bFM4_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242290cUL)) +#define bFM4_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42422910UL)) +#define bFM4_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42422914UL)) +#define bFM4_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42422918UL)) +#define bFM4_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242291cUL)) +#define bFM4_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42422920UL)) +#define bFM4_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42422924UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42422934UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42422938UL)) +#define bFM4_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242293cUL)) +#define bFM4_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42422a80UL)) +#define bFM4_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42422a84UL)) +#define bFM4_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42422a88UL)) +#define bFM4_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42422a8cUL)) +#define bFM4_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42422a90UL)) +#define bFM4_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42422a94UL)) +#define bFM4_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42422a98UL)) +#define bFM4_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42422a9cUL)) +#define bFM4_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42422aa0UL)) +#define bFM4_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42422aa4UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42422ab4UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42422ab8UL)) +#define bFM4_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42422abcUL)) +#define bFM4_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42422c00UL)) +#define bFM4_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42422c04UL)) +#define bFM4_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42422c08UL)) +#define bFM4_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42422c0cUL)) +#define bFM4_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42422c10UL)) +#define bFM4_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42422c14UL)) +#define bFM4_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42422c18UL)) +#define bFM4_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42422c1cUL)) +#define bFM4_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42422c20UL)) +#define bFM4_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42422c24UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42422c34UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42422c38UL)) +#define bFM4_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42422c3cUL)) +#define bFM4_MFT1_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42422c80UL)) +#define bFM4_MFT1_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42422c84UL)) +#define bFM4_MFT1_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42422c88UL)) +#define bFM4_MFT1_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42422c8cUL)) +#define bFM4_MFT1_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42422c90UL)) +#define bFM4_MFT1_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42422c94UL)) +#define bFM4_MFT1_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42422c98UL)) +#define bFM4_MFT1_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42422c9cUL)) +#define bFM4_MFT1_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42422ca0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42422cc0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42422cc4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42422cc8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42422cccUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42422cd0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42422cd4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42422cd8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42422cdcUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42422ce0UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM4_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42422300UL)) +#define bFM4_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42422304UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42422310UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42422314UL)) +#define bFM4_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42422318UL)) +#define bFM4_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242231cUL)) +#define bFM4_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42422320UL)) +#define bFM4_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42422324UL)) +#define bFM4_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42422330UL)) +#define bFM4_MFT1_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4242233cUL)) +#define bFM4_MFT1_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42422380UL)) +#define bFM4_MFT1_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42422384UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42422390UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42422394UL)) +#define bFM4_MFT1_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42422398UL)) +#define bFM4_MFT1_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4242239cUL)) +#define bFM4_MFT1_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424223a0UL)) +#define bFM4_MFT1_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424223a4UL)) +#define bFM4_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424223b0UL)) +#define bFM4_MFT1_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424223bcUL)) +#define bFM4_MFT1_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42422400UL)) +#define bFM4_MFT1_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42422404UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42422410UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42422414UL)) +#define bFM4_MFT1_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42422418UL)) +#define bFM4_MFT1_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4242241cUL)) +#define bFM4_MFT1_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42422420UL)) +#define bFM4_MFT1_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42422424UL)) +#define bFM4_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42422430UL)) +#define bFM4_MFT1_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4242243cUL)) +#define bFM4_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424224a0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424224a4UL)) +#define bFM4_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424224a8UL)) +#define bFM4_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424224acUL)) +#define bFM4_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424224b0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424224b4UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42422d00UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42422d04UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42422d08UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42422d0cUL)) +#define bFM4_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42422d10UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42422d14UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42422d18UL)) +#define bFM4_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42422d1cUL)) +#define bFM4_MFT1_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42422d20UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42422d24UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42422d28UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42422d2cUL)) +#define bFM4_MFT1_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42422d30UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42422d34UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42422d38UL)) +#define bFM4_MFT1_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42422d3cUL)) +#define bFM4_MFT1_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42422d40UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42422d44UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42422d48UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42422d4cUL)) +#define bFM4_MFT1_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42422d50UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42422d54UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42422d58UL)) +#define bFM4_MFT1_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42422d5cUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM4_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42423480UL)) +#define bFM4_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42423484UL)) +#define bFM4_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42423488UL)) +#define bFM4_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42423498UL)) +#define bFM4_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242349cUL)) +#define bFM4_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424234a0UL)) +#define bFM4_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424234a4UL)) +#define bFM4_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424234a8UL)) +#define bFM4_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424234acUL)) +#define bFM4_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42423500UL)) +#define bFM4_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42423504UL)) +#define bFM4_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42423508UL)) +#define bFM4_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42423518UL)) +#define bFM4_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242351cUL)) +#define bFM4_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42423520UL)) +#define bFM4_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42423524UL)) +#define bFM4_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42423528UL)) +#define bFM4_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242352cUL)) +#define bFM4_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42423580UL)) +#define bFM4_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42423584UL)) +#define bFM4_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42423588UL)) +#define bFM4_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42423598UL)) +#define bFM4_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242359cUL)) +#define bFM4_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424235a0UL)) +#define bFM4_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424235a4UL)) +#define bFM4_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424235a8UL)) +#define bFM4_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424235acUL)) +#define bFM4_MFT1_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42423600UL)) +#define bFM4_MFT1_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42423604UL)) +#define bFM4_MFT1_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42423608UL)) +#define bFM4_MFT1_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4242360cUL)) +#define bFM4_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42423610UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42423614UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42423618UL)) +#define bFM4_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242361cUL)) +#define bFM4_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42423620UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42423624UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42423628UL)) +#define bFM4_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242362cUL)) +#define bFM4_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42423630UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42423634UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42423638UL)) +#define bFM4_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242363cUL)) +#define bFM4_MFT1_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42423680UL)) +#define bFM4_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42423684UL)) +#define bFM4_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42423688UL)) +#define bFM4_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242368cUL)) +#define bFM4_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42423690UL)) +#define bFM4_MFT1_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42423694UL)) +#define bFM4_MFT1_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424236a0UL)) +#define bFM4_MFT1_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424236a4UL)) +#define bFM4_MFT1_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424236b0UL)) +#define bFM4_MFT1_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424236b4UL)) +#define bFM4_MFT1_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424236b8UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM4_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42422d80UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42422d84UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42422d88UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42422d8cUL)) +#define bFM4_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42422d90UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42422d94UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42422d98UL)) +#define bFM4_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42422d9cUL)) +#define bFM4_MFT1_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42422da0UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42422da4UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42422da8UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42422dacUL)) +#define bFM4_MFT1_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42422db0UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42422db4UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42422db8UL)) +#define bFM4_MFT1_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42422dbcUL)) +#define bFM4_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42423080UL)) +#define bFM4_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42423084UL)) +#define bFM4_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42423088UL)) +#define bFM4_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4242308cUL)) +#define bFM4_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42423090UL)) +#define bFM4_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42423094UL)) +#define bFM4_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42423098UL)) +#define bFM4_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4242309cUL)) +#define bFM4_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424230a0UL)) +#define bFM4_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424230a4UL)) +#define bFM4_MFT1_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42423100UL)) +#define bFM4_MFT1_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42423104UL)) +#define bFM4_MFT1_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42423108UL)) +#define bFM4_MFT1_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4242310cUL)) +#define bFM4_MFT1_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42423110UL)) +#define bFM4_MFT1_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42423114UL)) +#define bFM4_MFT1_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42423118UL)) +#define bFM4_MFT1_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4242311cUL)) +#define bFM4_MFT1_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42423120UL)) +#define bFM4_MFT1_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42423124UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM4_MFT1_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42423aa0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42423aa4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42423ab0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42423ab4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42423ab8UL)) +#define bFM4_MFT1_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42423abcUL)) +#define bFM4_MFT1_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42423b20UL)) +#define bFM4_MFT1_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42423b24UL)) +#define bFM4_MFT1_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42423b30UL)) +#define bFM4_MFT1_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42423b34UL)) +#define bFM4_MFT1_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42423b38UL)) +#define bFM4_MFT1_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42423b3cUL)) +#define bFM4_MFT1_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42423ba0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42423ba4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42423bb0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42423bb4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42423bb8UL)) +#define bFM4_MFT1_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42423bbcUL)) +#define bFM4_MFT1_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42423c20UL)) +#define bFM4_MFT1_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42423c24UL)) +#define bFM4_MFT1_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42423c30UL)) +#define bFM4_MFT1_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42423c34UL)) +#define bFM4_MFT1_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42423c38UL)) +#define bFM4_MFT1_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42423c3cUL)) +#define bFM4_MFT1_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42423ca0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42423ca4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42423cb0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42423cb4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42423cb8UL)) +#define bFM4_MFT1_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42423cbcUL)) +#define bFM4_MFT1_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42423d20UL)) +#define bFM4_MFT1_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42423d24UL)) +#define bFM4_MFT1_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42423d30UL)) +#define bFM4_MFT1_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42423d34UL)) +#define bFM4_MFT1_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42423d38UL)) +#define bFM4_MFT1_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42423d3cUL)) + +/* Multifunction Timer unit 2 Free Running Timer registers */ +#define bFM4_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42442900UL)) +#define bFM4_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42442904UL)) +#define bFM4_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42442908UL)) +#define bFM4_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244290cUL)) +#define bFM4_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42442910UL)) +#define bFM4_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42442914UL)) +#define bFM4_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42442918UL)) +#define bFM4_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244291cUL)) +#define bFM4_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42442920UL)) +#define bFM4_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42442924UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42442934UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42442938UL)) +#define bFM4_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244293cUL)) +#define bFM4_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42442a80UL)) +#define bFM4_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42442a84UL)) +#define bFM4_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42442a88UL)) +#define bFM4_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42442a8cUL)) +#define bFM4_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42442a90UL)) +#define bFM4_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42442a94UL)) +#define bFM4_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42442a98UL)) +#define bFM4_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42442a9cUL)) +#define bFM4_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42442aa0UL)) +#define bFM4_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42442aa4UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42442ab4UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42442ab8UL)) +#define bFM4_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42442abcUL)) +#define bFM4_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42442c00UL)) +#define bFM4_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42442c04UL)) +#define bFM4_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42442c08UL)) +#define bFM4_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42442c0cUL)) +#define bFM4_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42442c10UL)) +#define bFM4_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42442c14UL)) +#define bFM4_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42442c18UL)) +#define bFM4_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42442c1cUL)) +#define bFM4_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42442c20UL)) +#define bFM4_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42442c24UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42442c34UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42442c38UL)) +#define bFM4_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42442c3cUL)) +#define bFM4_MFT2_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42442c80UL)) +#define bFM4_MFT2_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42442c84UL)) +#define bFM4_MFT2_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42442c88UL)) +#define bFM4_MFT2_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42442c8cUL)) +#define bFM4_MFT2_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42442c90UL)) +#define bFM4_MFT2_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42442c94UL)) +#define bFM4_MFT2_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42442c98UL)) +#define bFM4_MFT2_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42442c9cUL)) +#define bFM4_MFT2_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42442ca0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42442cc0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42442cc4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42442cc8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42442cccUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42442cd0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42442cd4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42442cd8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42442cdcUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42442ce0UL)) + +/* Multifunction Timer unit 2 Output Compare Unit registers */ +#define bFM4_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42442300UL)) +#define bFM4_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42442304UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42442310UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42442314UL)) +#define bFM4_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42442318UL)) +#define bFM4_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244231cUL)) +#define bFM4_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42442320UL)) +#define bFM4_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42442324UL)) +#define bFM4_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42442330UL)) +#define bFM4_MFT2_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4244233cUL)) +#define bFM4_MFT2_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42442380UL)) +#define bFM4_MFT2_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42442384UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42442390UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42442394UL)) +#define bFM4_MFT2_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42442398UL)) +#define bFM4_MFT2_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4244239cUL)) +#define bFM4_MFT2_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424423a0UL)) +#define bFM4_MFT2_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424423a4UL)) +#define bFM4_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424423b0UL)) +#define bFM4_MFT2_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424423bcUL)) +#define bFM4_MFT2_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42442400UL)) +#define bFM4_MFT2_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42442404UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42442410UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42442414UL)) +#define bFM4_MFT2_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42442418UL)) +#define bFM4_MFT2_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4244241cUL)) +#define bFM4_MFT2_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42442420UL)) +#define bFM4_MFT2_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42442424UL)) +#define bFM4_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42442430UL)) +#define bFM4_MFT2_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4244243cUL)) +#define bFM4_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424424a0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424424a4UL)) +#define bFM4_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424424a8UL)) +#define bFM4_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424424acUL)) +#define bFM4_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424424b0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424424b4UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42442d00UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42442d04UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42442d08UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42442d0cUL)) +#define bFM4_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42442d10UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42442d14UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42442d18UL)) +#define bFM4_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42442d1cUL)) +#define bFM4_MFT2_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42442d20UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42442d24UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42442d28UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42442d2cUL)) +#define bFM4_MFT2_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42442d30UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42442d34UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42442d38UL)) +#define bFM4_MFT2_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42442d3cUL)) +#define bFM4_MFT2_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42442d40UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42442d44UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42442d48UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42442d4cUL)) +#define bFM4_MFT2_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42442d50UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42442d54UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42442d58UL)) +#define bFM4_MFT2_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42442d5cUL)) + +/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define bFM4_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42443480UL)) +#define bFM4_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42443484UL)) +#define bFM4_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42443488UL)) +#define bFM4_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42443498UL)) +#define bFM4_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244349cUL)) +#define bFM4_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424434a0UL)) +#define bFM4_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424434a4UL)) +#define bFM4_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424434a8UL)) +#define bFM4_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424434acUL)) +#define bFM4_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42443500UL)) +#define bFM4_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42443504UL)) +#define bFM4_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42443508UL)) +#define bFM4_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42443518UL)) +#define bFM4_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244351cUL)) +#define bFM4_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42443520UL)) +#define bFM4_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42443524UL)) +#define bFM4_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42443528UL)) +#define bFM4_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244352cUL)) +#define bFM4_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42443580UL)) +#define bFM4_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42443584UL)) +#define bFM4_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42443588UL)) +#define bFM4_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42443598UL)) +#define bFM4_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244359cUL)) +#define bFM4_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424435a0UL)) +#define bFM4_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424435a4UL)) +#define bFM4_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424435a8UL)) +#define bFM4_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424435acUL)) +#define bFM4_MFT2_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42443600UL)) +#define bFM4_MFT2_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42443604UL)) +#define bFM4_MFT2_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42443608UL)) +#define bFM4_MFT2_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4244360cUL)) +#define bFM4_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42443610UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42443614UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42443618UL)) +#define bFM4_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244361cUL)) +#define bFM4_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42443620UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42443624UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42443628UL)) +#define bFM4_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244362cUL)) +#define bFM4_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42443630UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42443634UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42443638UL)) +#define bFM4_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244363cUL)) +#define bFM4_MFT2_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42443680UL)) +#define bFM4_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42443684UL)) +#define bFM4_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42443688UL)) +#define bFM4_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244368cUL)) +#define bFM4_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42443690UL)) +#define bFM4_MFT2_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42443694UL)) +#define bFM4_MFT2_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424436a0UL)) +#define bFM4_MFT2_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424436a4UL)) +#define bFM4_MFT2_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424436b0UL)) +#define bFM4_MFT2_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424436b4UL)) +#define bFM4_MFT2_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424436b8UL)) + +/* Multifunction Timer unit 2 Input Capture Unit registers */ +#define bFM4_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42442d80UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42442d84UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42442d88UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42442d8cUL)) +#define bFM4_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42442d90UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42442d94UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42442d98UL)) +#define bFM4_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42442d9cUL)) +#define bFM4_MFT2_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42442da0UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42442da4UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42442da8UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42442dacUL)) +#define bFM4_MFT2_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42442db0UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42442db4UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42442db8UL)) +#define bFM4_MFT2_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42442dbcUL)) +#define bFM4_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42443080UL)) +#define bFM4_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42443084UL)) +#define bFM4_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42443088UL)) +#define bFM4_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4244308cUL)) +#define bFM4_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42443090UL)) +#define bFM4_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42443094UL)) +#define bFM4_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42443098UL)) +#define bFM4_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4244309cUL)) +#define bFM4_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424430a0UL)) +#define bFM4_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424430a4UL)) +#define bFM4_MFT2_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42443100UL)) +#define bFM4_MFT2_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42443104UL)) +#define bFM4_MFT2_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42443108UL)) +#define bFM4_MFT2_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4244310cUL)) +#define bFM4_MFT2_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42443110UL)) +#define bFM4_MFT2_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42443114UL)) +#define bFM4_MFT2_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42443118UL)) +#define bFM4_MFT2_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4244311cUL)) +#define bFM4_MFT2_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42443120UL)) +#define bFM4_MFT2_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42443124UL)) + +/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define bFM4_MFT2_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42443aa0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42443aa4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42443ab0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42443ab4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42443ab8UL)) +#define bFM4_MFT2_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42443abcUL)) +#define bFM4_MFT2_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42443b20UL)) +#define bFM4_MFT2_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42443b24UL)) +#define bFM4_MFT2_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42443b30UL)) +#define bFM4_MFT2_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42443b34UL)) +#define bFM4_MFT2_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42443b38UL)) +#define bFM4_MFT2_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42443b3cUL)) +#define bFM4_MFT2_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42443ba0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42443ba4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42443bb0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42443bb4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42443bb8UL)) +#define bFM4_MFT2_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42443bbcUL)) +#define bFM4_MFT2_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42443c20UL)) +#define bFM4_MFT2_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42443c24UL)) +#define bFM4_MFT2_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42443c30UL)) +#define bFM4_MFT2_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42443c34UL)) +#define bFM4_MFT2_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42443c38UL)) +#define bFM4_MFT2_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42443c3cUL)) +#define bFM4_MFT2_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42443ca0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42443ca4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42443cb0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42443cb4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42443cb8UL)) +#define bFM4_MFT2_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42443cbcUL)) +#define bFM4_MFT2_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42443d20UL)) +#define bFM4_MFT2_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42443d24UL)) +#define bFM4_MFT2_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42443d30UL)) +#define bFM4_MFT2_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42443d34UL)) +#define bFM4_MFT2_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42443d38UL)) +#define bFM4_MFT2_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42443d3cUL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) +#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) +#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) +#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) +#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) +#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) +#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) +#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) +#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) +#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) +#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) +#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) +#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) +#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) +#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) +#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) +#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) +#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) +#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) +#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) +#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) +#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) +#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) +#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) +#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) +#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) +#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) +#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) +#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) +#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) +#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) +#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) +#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) +#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) +#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) +#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) +#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) +#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) +#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) +#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) +#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) +#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) +#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) +#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) +#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) +#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) +#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) +#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) +#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) +#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) +#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) +#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) +#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) +#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) +#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) +#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) +#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) +#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) +#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) +#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) +#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) +#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) +#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) +#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) +#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) +#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) +#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) +#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) +#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) +#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) +#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) +#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) +#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) +#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) +#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) +#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) +#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) +#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) +#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM4_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM4_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM4_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM4_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM4_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM4_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM4_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM4_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM4_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM4_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM4_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM4_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM4_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM4_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM4_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM4_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM4_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM4_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM4_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM4_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM4_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM4_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM4_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM4_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM4_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM4_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM4_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM4_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM4_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM4_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM4_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM4_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM4_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM4_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM4_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM4_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM4_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM4_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM4_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM4_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM4_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM4_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM4_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM4_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM4_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM4_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM4_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM4_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM4_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM4_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM4_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM4_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM4_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM4_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM4_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM4_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM4_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM4_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM4_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM4_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM4_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM4_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM4_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM4_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM4_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM4_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM4_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM4_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM4_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM4_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM4_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM4_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM4_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM4_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM4_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM4_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM4_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM4_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM4_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM4_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM4_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM4_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM4_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM4_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM4_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM4_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM4_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM4_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM4_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM4_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM4_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM4_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM4_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM4_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM4_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM4_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM4_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM4_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM4_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM4_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM4_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM4_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM4_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM4_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM4_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM4_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM4_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM4_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM4_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM4_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM4_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM4_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM4_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM4_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM4_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM4_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM4_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM4_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM4_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM4_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM4_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM4_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM4_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM4_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM4_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM4_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM4_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM4_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM4_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM4_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM4_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM4_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM4_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM4_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM4_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM4_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM4_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM4_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM4_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM4_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM4_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM4_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM4_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM4_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM4_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM4_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM4_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM4_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM4_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM4_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM4_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM4_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM4_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM4_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM4_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM4_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM4_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM4_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM4_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM4_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM4_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM4_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM4_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM4_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM4_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM4_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM4_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM4_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM4_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM4_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM4_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM4_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM4_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM4_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM4_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM4_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM4_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM4_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM4_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM4_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM4_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM4_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM4_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM4_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM4_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM4_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM4_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM4_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM4_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM4_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM4_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM4_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM4_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM4_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM4_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM4_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM4_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM4_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM4_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM4_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM4_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM4_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM4_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM4_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM4_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM4_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM4_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM4_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM4_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM4_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM4_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM4_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM4_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM4_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM4_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM4_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM4_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM4_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM4_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM4_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM4_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM4_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM4_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM4_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM4_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM4_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM4_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM4_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM4_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM4_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM4_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM4_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM4_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM4_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM4_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM4_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM4_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM4_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM4_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM4_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM4_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM4_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM4_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM4_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM4_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM4_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM4_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM4_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM4_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM4_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM4_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM4_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM4_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM4_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM4_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM4_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM4_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM4_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM4_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM4_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM4_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM4_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM4_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM4_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM4_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM4_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM4_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM4_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM4_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM4_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM4_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM4_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM4_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM4_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM4_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM4_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM4_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM4_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM4_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM4_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM4_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM4_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM4_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM4_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM4_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM4_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM4_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM4_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM4_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM4_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM4_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM4_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM4_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM4_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM4_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM4_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM4_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM4_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM4_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM4_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM4_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM4_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM4_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM4_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM4_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM4_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM4_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM4_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM4_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM4_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM4_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM4_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM4_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM4_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM4_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM4_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM4_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM4_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM4_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM4_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM4_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM4_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM4_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM4_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM4_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM4_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM4_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM4_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM4_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM4_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM4_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM4_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM4_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM4_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM4_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM4_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM4_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM4_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM4_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM4_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM4_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM4_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM4_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM4_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM4_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM4_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM4_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM4_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM4_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM4_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM4_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM4_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM4_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM4_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM4_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM4_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM4_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM4_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM4_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM4_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM4_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM4_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM4_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM4_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM4_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM4_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM4_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM4_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM4_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM4_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM4_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM4_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM4_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM4_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM4_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM4_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM4_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM4_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM4_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM4_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM4_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM4_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM4_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM4_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM4_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM4_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM4_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM4_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM4_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM4_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM4_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM4_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM4_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM4_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM4_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM4_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM4_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM4_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM4_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM4_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM4_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM4_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM4_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM4_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM4_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM4_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM4_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM4_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM4_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM4_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM4_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM4_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM4_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM4_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM4_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM4_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM4_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM4_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM4_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM4_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM4_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM4_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM4_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM4_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM4_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM4_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM4_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM4_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM4_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM4_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM4_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM4_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM4_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM4_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM4_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM4_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM4_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM4_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM4_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM4_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM4_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM4_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM4_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM4_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM4_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM4_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM4_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM4_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM4_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM4_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM4_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM4_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM4_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM4_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM4_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM4_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM4_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM4_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM4_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM4_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM4_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM4_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM4_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM4_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM4_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM4_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM4_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM4_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM4_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM4_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM4_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM4_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM4_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM4_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM4_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM4_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM4_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM4_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM4_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM4_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM4_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM4_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM4_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM4_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM4_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM4_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM4_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM4_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM4_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM4_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM4_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM4_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM4_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM4_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM4_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM4_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM4_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM4_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM4_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM4_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM4_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM4_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM4_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM4_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM4_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM4_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM4_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM4_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM4_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM4_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM4_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM4_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM4_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM4_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM4_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM4_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM4_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM4_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM4_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM4_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM4_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM4_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM4_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM4_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM4_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM4_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM4_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM4_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM4_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM4_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM4_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM4_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM4_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM4_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM4_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM4_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM4_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM4_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM4_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM4_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM4_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM4_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM4_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM4_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM4_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM4_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM4_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM4_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM4_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM4_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM4_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM4_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM4_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM4_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM4_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM4_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM4_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM4_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM4_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM4_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM4_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM4_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM4_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM4_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM4_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM4_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM4_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM4_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM4_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM4_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM4_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM4_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM4_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM4_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM4_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM4_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM4_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM4_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM4_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM4_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM4_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM4_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM4_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM4_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM4_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM4_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM4_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM4_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM4_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM4_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM4_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM4_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM4_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM4_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM4_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM4_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM4_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM4_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM4_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM4_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM4_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM4_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM4_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM4_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM4_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM4_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM4_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM4_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM4_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM4_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM4_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM4_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Base Timer 8 PPG registers */ +#define bFM4_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM4_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM4_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM4_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM4_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM4_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM4_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM4_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM4_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM4_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM4_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM4_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM4_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM4_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM4_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM4_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWM registers */ +#define bFM4_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM4_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM4_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM4_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM4_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM4_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM4_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM4_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM4_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM4_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM4_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM4_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM4_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) +#define bFM4_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM4_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM4_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) +#define bFM4_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM4_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 RT registers */ +#define bFM4_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM4_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM4_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM4_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM4_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM4_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM4_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM4_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM4_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM4_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM4_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM4_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM4_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM4_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM4_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWC registers */ +#define bFM4_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM4_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM4_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM4_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM4_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM4_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM4_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM4_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM4_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM4_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM4_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM4_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM4_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM4_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) +#define bFM4_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 9 PPG registers */ +#define bFM4_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM4_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM4_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM4_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM4_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM4_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM4_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM4_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM4_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM4_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM4_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM4_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM4_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM4_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM4_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM4_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWM registers */ +#define bFM4_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM4_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM4_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM4_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM4_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM4_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM4_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM4_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM4_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM4_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM4_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM4_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM4_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) +#define bFM4_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM4_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM4_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) +#define bFM4_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM4_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 RT registers */ +#define bFM4_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM4_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM4_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM4_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM4_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM4_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM4_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM4_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM4_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM4_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM4_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM4_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM4_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM4_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM4_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWC registers */ +#define bFM4_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM4_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM4_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM4_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM4_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM4_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM4_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM4_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM4_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM4_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM4_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM4_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM4_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM4_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) +#define bFM4_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 10 PPG registers */ +#define bFM4_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM4_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM4_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM4_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM4_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM4_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM4_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM4_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM4_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM4_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM4_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM4_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM4_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM4_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM4_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM4_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWM registers */ +#define bFM4_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM4_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM4_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM4_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM4_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM4_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM4_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM4_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM4_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM4_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM4_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM4_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM4_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) +#define bFM4_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM4_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM4_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) +#define bFM4_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM4_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 RT registers */ +#define bFM4_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM4_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM4_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM4_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM4_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM4_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM4_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM4_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM4_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM4_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM4_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM4_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM4_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM4_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM4_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWC registers */ +#define bFM4_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM4_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM4_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM4_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM4_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM4_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM4_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM4_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM4_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM4_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM4_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM4_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM4_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM4_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) +#define bFM4_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 11 PPG registers */ +#define bFM4_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM4_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM4_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM4_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM4_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM4_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM4_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM4_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM4_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM4_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM4_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM4_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM4_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM4_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM4_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM4_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWM registers */ +#define bFM4_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM4_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM4_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM4_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM4_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM4_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM4_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM4_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM4_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM4_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM4_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM4_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM4_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) +#define bFM4_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM4_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM4_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) +#define bFM4_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM4_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 RT registers */ +#define bFM4_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM4_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM4_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM4_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM4_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM4_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM4_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM4_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM4_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM4_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM4_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM4_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM4_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM4_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM4_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWC registers */ +#define bFM4_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM4_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM4_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM4_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM4_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM4_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM4_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM4_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM4_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM4_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM4_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM4_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM4_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM4_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) +#define bFM4_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 12 PPG registers */ +#define bFM4_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM4_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM4_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM4_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM4_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM4_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM4_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM4_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM4_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM4_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM4_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM4_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM4_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM4_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM4_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM4_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWM registers */ +#define bFM4_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM4_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM4_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM4_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM4_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM4_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM4_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM4_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM4_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM4_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM4_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM4_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM4_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) +#define bFM4_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM4_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM4_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) +#define bFM4_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM4_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 RT registers */ +#define bFM4_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM4_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM4_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM4_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM4_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM4_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM4_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM4_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM4_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM4_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM4_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM4_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM4_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM4_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM4_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWC registers */ +#define bFM4_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM4_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM4_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM4_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM4_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM4_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM4_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM4_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM4_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM4_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM4_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM4_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM4_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM4_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) +#define bFM4_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 13 PPG registers */ +#define bFM4_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM4_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM4_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM4_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM4_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM4_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM4_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM4_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM4_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM4_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM4_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM4_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM4_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM4_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM4_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM4_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWM registers */ +#define bFM4_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM4_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM4_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM4_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM4_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM4_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM4_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM4_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM4_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM4_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM4_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM4_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM4_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) +#define bFM4_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM4_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM4_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) +#define bFM4_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM4_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 RT registers */ +#define bFM4_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM4_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM4_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM4_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM4_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM4_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM4_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM4_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM4_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM4_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM4_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM4_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM4_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM4_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM4_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWC registers */ +#define bFM4_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM4_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM4_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM4_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM4_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM4_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM4_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM4_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM4_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM4_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM4_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM4_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM4_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM4_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) +#define bFM4_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 14 PPG registers */ +#define bFM4_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM4_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM4_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM4_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM4_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM4_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM4_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM4_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM4_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM4_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM4_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM4_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM4_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM4_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM4_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM4_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWM registers */ +#define bFM4_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM4_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM4_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM4_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM4_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM4_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM4_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM4_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM4_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM4_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM4_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM4_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM4_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) +#define bFM4_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM4_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM4_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) +#define bFM4_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM4_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 RT registers */ +#define bFM4_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM4_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM4_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM4_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM4_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM4_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM4_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM4_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM4_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM4_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM4_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM4_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM4_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM4_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM4_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWC registers */ +#define bFM4_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM4_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM4_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM4_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM4_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM4_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM4_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM4_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM4_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM4_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM4_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM4_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM4_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM4_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) +#define bFM4_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 15 PPG registers */ +#define bFM4_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM4_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM4_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM4_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM4_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM4_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM4_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM4_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM4_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM4_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM4_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM4_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM4_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM4_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM4_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM4_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWM registers */ +#define bFM4_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM4_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM4_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM4_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM4_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM4_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM4_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM4_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM4_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM4_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM4_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM4_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM4_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) +#define bFM4_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM4_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM4_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) +#define bFM4_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM4_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 RT registers */ +#define bFM4_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM4_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM4_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM4_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM4_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM4_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM4_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM4_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM4_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM4_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM4_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM4_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM4_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM4_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM4_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWC registers */ +#define bFM4_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM4_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM4_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM4_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM4_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM4_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM4_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM4_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM4_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM4_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM4_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM4_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM4_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM4_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) +#define bFM4_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer I/O selector channel 8 - channel 11 registers */ +#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) +#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) + +/* Base Timer I/O selector channel 12 - channel 15 registers */ +#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) +#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM4_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM4_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM4_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM4_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM4_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM4_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM4_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM4_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM4_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM4_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM4_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM4_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM4_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM4_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM4_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM4_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM4_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM4_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM4_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM4_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM4_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM4_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM4_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM4_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM4_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM4_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM4_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM4_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM4_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM4_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM4_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM4_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM4_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM4_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM4_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM4_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM4_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM4_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM4_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM4_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM4_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM4_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM4_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM4_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM4_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM4_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM4_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM4_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM4_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM4_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM4_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM4_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM4_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM4_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM4_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM4_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM4_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM4_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM4_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM4_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM4_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM4_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM4_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM4_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM4_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM4_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM4_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM4_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM4_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM4_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM4_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM4_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM4_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM4_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM4_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM4_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM4_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM4_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM4_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM4_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM4_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM4_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM4_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM4_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM4_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM4_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM4_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM4_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM4_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM4_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM4_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM4_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM4_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM4_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM4_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM4_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM4_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM4_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM4_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM4_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM4_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM4_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM4_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM4_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM4_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM4_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM4_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM4_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM4_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM4_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM4_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM4_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM4_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM4_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM4_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM4_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM4_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM4_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM4_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM4_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM4_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM4_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM4_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM4_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM4_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM4_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM4_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM4_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM4_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM4_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM4_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM4_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM4_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM4_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM4_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM4_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM4_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM4_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM4_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM4_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM4_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM4_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* Quad position and revolution counter channel 2 registers */ +#define bFM4_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM4_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM4_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM4_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM4_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM4_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM4_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM4_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM4_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM4_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM4_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM4_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM4_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM4_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM4_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM4_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM4_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM4_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM4_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM4_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM4_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM4_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM4_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM4_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM4_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM4_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM4_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM4_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM4_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM4_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM4_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM4_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM4_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM4_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM4_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM4_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM4_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM4_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM4_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM4_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM4_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM4_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM4_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM4_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM4_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM4_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM4_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM4_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM4_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM4_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM4_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM4_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM4_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM4_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM4_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM4_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM4_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM4_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM4_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM4_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM4_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) +#define bFM4_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) +#define bFM4_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) + +/* Quad position and revolution counter channel 3 registers */ +#define bFM4_QPRC3_QICR_QPCMIE *((volatile unsigned int*)(0x424c1a80UL)) +#define bFM4_QPRC3_QICR_QPCMF *((volatile unsigned int*)(0x424c1a84UL)) +#define bFM4_QPRC3_QICR_QPRCMIE *((volatile unsigned int*)(0x424c1a88UL)) +#define bFM4_QPRC3_QICR_QPRCMF *((volatile unsigned int*)(0x424c1a8cUL)) +#define bFM4_QPRC3_QICR_OUZIE *((volatile unsigned int*)(0x424c1a90UL)) +#define bFM4_QPRC3_QICR_UFDF *((volatile unsigned int*)(0x424c1a94UL)) +#define bFM4_QPRC3_QICR_OFDF *((volatile unsigned int*)(0x424c1a98UL)) +#define bFM4_QPRC3_QICR_ZIIF *((volatile unsigned int*)(0x424c1a9cUL)) +#define bFM4_QPRC3_QICR_CDCIE *((volatile unsigned int*)(0x424c1aa0UL)) +#define bFM4_QPRC3_QICR_CDCF *((volatile unsigned int*)(0x424c1aa4UL)) +#define bFM4_QPRC3_QICR_DIRPC *((volatile unsigned int*)(0x424c1aa8UL)) +#define bFM4_QPRC3_QICR_DIROU *((volatile unsigned int*)(0x424c1aacUL)) +#define bFM4_QPRC3_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424c1ab0UL)) +#define bFM4_QPRC3_QICR_QPCNRCMF *((volatile unsigned int*)(0x424c1ab4UL)) +#define bFM4_QPRC3_QCR_PCM0 *((volatile unsigned int*)(0x424c1b00UL)) +#define bFM4_QPRC3_QCR_PCM1 *((volatile unsigned int*)(0x424c1b04UL)) +#define bFM4_QPRC3_QCR_RCM0 *((volatile unsigned int*)(0x424c1b08UL)) +#define bFM4_QPRC3_QCR_RCM1 *((volatile unsigned int*)(0x424c1b0cUL)) +#define bFM4_QPRC3_QCR_PSTP *((volatile unsigned int*)(0x424c1b10UL)) +#define bFM4_QPRC3_QCR_CGSC *((volatile unsigned int*)(0x424c1b14UL)) +#define bFM4_QPRC3_QCR_RSEL *((volatile unsigned int*)(0x424c1b18UL)) +#define bFM4_QPRC3_QCR_SWAP *((volatile unsigned int*)(0x424c1b1cUL)) +#define bFM4_QPRC3_QCR_PCRM0 *((volatile unsigned int*)(0x424c1b20UL)) +#define bFM4_QPRC3_QCR_PCRM1 *((volatile unsigned int*)(0x424c1b24UL)) +#define bFM4_QPRC3_QCR_AES0 *((volatile unsigned int*)(0x424c1b28UL)) +#define bFM4_QPRC3_QCR_AES1 *((volatile unsigned int*)(0x424c1b2cUL)) +#define bFM4_QPRC3_QCR_BES0 *((volatile unsigned int*)(0x424c1b30UL)) +#define bFM4_QPRC3_QCR_BES1 *((volatile unsigned int*)(0x424c1b34UL)) +#define bFM4_QPRC3_QCR_CGE0 *((volatile unsigned int*)(0x424c1b38UL)) +#define bFM4_QPRC3_QCR_CGE1 *((volatile unsigned int*)(0x424c1b3cUL)) +#define bFM4_QPRC3_QECR_ORNGMD *((volatile unsigned int*)(0x424c1b80UL)) +#define bFM4_QPRC3_QECR_ORNGF *((volatile unsigned int*)(0x424c1b84UL)) +#define bFM4_QPRC3_QECR_ORNGIE *((volatile unsigned int*)(0x424c1b88UL)) + +/* QPRC NF channel 0 registers */ +#define bFM4_QPRC0_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2010UL)) +#define bFM4_QPRC0_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2014UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2090UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2094UL)) +#define bFM4_QPRC0_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2110UL)) +#define bFM4_QPRC0_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2114UL)) + +/* QPRC NF channel 1 registers */ +#define bFM4_QPRC1_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2210UL)) +#define bFM4_QPRC1_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2214UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2290UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2294UL)) +#define bFM4_QPRC1_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2310UL)) +#define bFM4_QPRC1_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2314UL)) + +/* QPRC NF channel 2 registers */ +#define bFM4_QPRC2_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2410UL)) +#define bFM4_QPRC2_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2414UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2490UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2494UL)) +#define bFM4_QPRC2_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2510UL)) +#define bFM4_QPRC2_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2514UL)) + +/* QPRC NF channel 3 registers */ +#define bFM4_QPRC3_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2610UL)) +#define bFM4_QPRC3_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2614UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2690UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2694UL)) +#define bFM4_QPRC3_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2710UL)) +#define bFM4_QPRC3_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2714UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM4_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM4_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM4_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM4_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM4_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM4_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM4_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM4_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM4_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM4_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM4_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM4_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM4_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM4_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM4_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM4_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM4_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM4_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM4_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM4_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM4_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM4_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM4_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM4_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM4_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM4_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM4_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM4_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM4_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM4_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM4_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM4_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM4_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM4_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM4_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM4_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM4_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM4_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM4_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM4_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM4_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM4_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM4_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM4_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM4_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM4_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM4_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM4_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM4_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM4_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM4_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM4_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM4_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM4_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM4_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM4_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM4_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM4_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM4_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM4_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM4_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM4_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM4_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM4_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM4_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM4_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM4_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM4_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM4_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM4_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM4_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM4_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM4_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM4_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM4_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM4_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM4_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM4_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM4_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM4_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM4_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM4_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM4_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM4_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM4_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM4_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM4_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM4_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM4_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM4_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM4_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM4_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM4_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM4_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM4_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM4_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM4_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM4_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM4_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM4_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM4_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM4_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM4_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM4_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM4_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM4_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM4_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM4_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM4_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM4_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM4_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM4_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM4_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM4_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM4_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM4_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM4_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM4_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM4_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM4_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM4_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM4_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM4_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM4_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM4_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM4_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM4_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM4_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM4_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM4_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM4_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM4_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM4_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM4_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM4_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM4_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM4_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM4_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM4_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM4_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM4_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM4_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM4_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM4_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM4_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM4_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM4_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM4_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM4_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM4_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM4_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM4_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM4_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM4_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM4_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM4_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM4_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM4_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM4_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM4_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM4_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM4_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM4_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM4_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM4_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM4_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM4_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM4_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM4_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM4_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM4_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM4_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM4_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM4_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM4_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM4_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM4_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM4_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM4_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM4_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM4_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM4_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM4_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM4_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM4_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM4_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM4_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM4_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM4_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM4_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM4_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM4_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM4_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM4_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM4_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM4_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM4_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM4_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM4_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM4_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM4_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM4_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM4_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM4_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM4_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM4_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM4_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM4_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM4_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM4_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM4_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM4_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM4_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM4_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM4_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM4_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM4_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM4_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM4_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM4_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM4_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM4_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM4_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM4_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM4_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM4_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM4_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM4_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM4_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM4_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM4_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM4_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM4_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM4_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM4_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM4_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM4_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM4_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM4_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM4_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM4_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM4_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM4_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM4_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM4_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM4_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM4_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM4_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM4_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM4_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM4_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM4_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM4_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM4_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM4_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM4_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM4_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM4_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM4_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM4_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM4_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM4_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM4_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM4_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM4_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM4_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM4_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM4_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM4_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM4_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM4_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM4_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM4_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM4_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM4_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM4_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM4_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM4_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM4_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM4_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM4_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM4_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM4_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM4_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM4_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM4_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM4_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM4_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM4_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM4_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM4_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM4_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM4_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM4_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM4_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM4_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM4_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM4_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM4_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM4_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM4_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM4_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM4_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM4_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM4_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM4_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM4_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM4_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM4_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM4_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM4_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM4_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM4_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM4_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM4_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM4_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM4_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM4_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM4_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM4_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM4_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM4_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM4_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM4_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM4_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM4_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM4_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM4_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM4_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM4_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM4_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM4_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM4_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM4_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM4_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM4_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM4_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM4_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM4_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM4_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM4_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM4_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM4_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM4_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM4_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM4_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM4_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM4_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM4_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM4_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM4_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM4_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM4_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM4_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM4_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM4_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM4_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM4_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM4_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM4_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM4_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM4_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM4_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM4_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM4_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM4_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM4_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM4_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM4_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM4_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM4_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM4_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM4_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM4_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM4_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM4_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM4_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM4_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM4_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM4_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM4_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM4_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM4_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM4_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM4_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM4_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM4_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM4_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM4_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM4_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM4_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM4_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM4_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM4_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM4_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM4_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM4_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM4_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM4_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM4_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM4_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM4_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM4_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM4_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM4_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM4_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM4_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM4_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM4_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM4_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM4_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM4_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM4_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM4_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM4_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM4_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM4_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM4_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM4_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM4_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM4_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM4_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM4_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM4_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM4_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM4_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM4_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM4_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM4_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM4_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM4_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM4_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM4_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM4_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM4_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM4_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM4_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM4_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM4_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM4_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM4_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM4_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM4_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM4_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM4_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM4_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM4_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM4_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM4_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM4_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM4_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM4_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM4_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM4_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM4_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM4_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM4_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM4_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM4_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM4_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM4_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM4_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM4_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM4_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM4_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM4_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM4_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM4_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM4_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM4_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM4_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM4_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM4_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM4_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM4_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM4_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM4_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM4_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM4_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM4_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM4_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM4_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM4_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM4_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM4_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM4_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM4_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM4_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM4_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM4_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM4_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM4_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM4_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM4_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM4_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM4_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM4_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM4_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM4_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM4_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM4_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM4_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM4_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM4_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM4_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM4_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM4_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM4_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM4_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM4_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM4_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM4_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM4_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM4_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM4_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM4_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM4_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM4_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM4_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM4_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM4_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM4_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM4_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM4_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM4_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM4_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM4_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM4_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM4_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM4_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM4_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM4_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM4_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM4_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM4_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM4_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM4_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM4_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM4_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM4_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM4_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM4_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM4_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM4_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM4_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM4_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM4_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM4_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM4_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM4_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM4_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM4_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM4_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM4_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM4_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM4_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM4_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM4_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM4_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM4_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM4_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM4_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM4_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM4_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM4_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM4_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM4_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM4_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM4_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM4_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM4_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM4_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM4_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM4_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM4_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM4_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM4_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM4_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM4_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM4_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM4_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM4_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM4_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM4_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM4_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM4_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM4_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM4_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM4_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM4_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM4_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM4_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM4_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM4_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM4_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM4_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM4_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM4_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM4_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM4_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM4_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM4_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM4_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM4_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM4_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM4_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM4_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM4_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM4_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM4_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM4_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM4_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM4_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM4_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM4_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM4_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM4_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM4_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM4_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM4_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM4_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM4_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM4_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM4_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM4_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM4_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM4_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM4_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM4_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM4_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM4_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM4_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM4_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM4_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM4_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM4_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM4_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM4_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM4_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM4_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM4_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM4_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM4_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM4_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM4_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM4_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM4_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM4_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM4_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM4_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM4_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM4_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM4_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM4_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM4_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM4_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM4_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM4_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM4_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM4_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM4_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM4_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM4_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM4_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM4_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM4_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM4_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM4_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM4_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM4_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM4_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM4_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM4_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM4_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM4_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM4_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM4_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM4_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM4_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM4_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM4_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM4_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM4_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM4_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM4_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM4_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM4_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM4_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM4_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM4_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM4_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM4_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM4_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM4_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM4_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM4_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM4_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM4_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM4_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM4_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM4_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM4_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM4_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM4_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM4_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM4_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM4_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM4_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM4_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM4_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM4_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM4_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM4_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM4_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM4_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM4_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM4_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM4_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM4_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM4_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM4_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM4_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM4_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM4_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM4_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM4_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM4_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM4_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM4_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM4_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM4_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM4_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM4_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM4_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM4_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM4_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM4_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM4_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM4_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM4_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM4_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM4_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM4_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM4_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM4_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM4_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM4_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM4_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM4_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM4_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM4_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM4_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM4_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM4_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM4_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM4_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM4_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM4_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM4_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM4_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM4_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM4_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM4_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM4_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM4_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM4_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM4_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM4_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM4_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM4_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM4_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM4_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM4_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM4_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM4_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM4_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM4_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM4_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM4_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM4_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM4_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM4_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM4_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM4_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM4_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM4_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM4_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM4_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM4_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM4_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM4_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM4_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM4_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM4_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM4_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM4_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM4_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM4_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM4_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM4_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM4_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM4_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM4_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM4_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM4_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM4_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM4_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM4_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM4_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM4_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM4_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM4_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM4_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM4_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM4_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM4_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM4_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM4_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM4_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM4_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM4_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM4_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM4_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM4_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM4_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM4_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM4_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM4_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM4_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM4_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM4_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM4_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM4_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM4_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM4_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM4_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM4_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM4_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM4_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM4_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM4_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM4_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM4_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM4_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM4_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM4_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM4_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM4_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM4_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM4_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM4_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM4_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM4_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM4_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM4_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM4_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM4_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM4_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM4_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM4_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM4_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM4_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM4_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM4_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM4_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM4_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM4_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM4_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM4_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM4_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM4_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM4_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM4_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM4_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM4_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM4_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM4_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM4_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM4_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM4_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM4_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM4_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM4_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM4_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM4_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM4_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM4_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM4_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM4_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM4_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM4_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM4_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM4_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM4_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM4_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM4_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM4_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM4_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM4_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM4_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM4_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM4_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM4_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM4_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM4_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM4_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM4_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM4_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM4_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM4_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM4_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM4_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM4_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM4_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM4_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM4_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM4_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM4_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM4_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM4_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM4_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM4_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM4_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM4_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM4_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM4_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM4_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM4_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM4_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM4_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM4_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM4_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM4_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM4_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM4_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM4_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM4_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM4_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM4_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM4_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM4_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM4_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM4_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM4_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM4_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM4_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM4_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM4_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) + +/* CR trimming registers */ +#define bFM4_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM4_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM4_CRTRIM_MCR_PSR_CSR2 *((volatile unsigned int*)(0x425C0008UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) +#define bFM4_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) +#define bFM4_CRTRIM_MCR_TTRM_TRT0 *((volatile unsigned int*)(0x425C0100UL)) +#define bFM4_CRTRIM_MCR_TTRM_TRT1 *((volatile unsigned int*)(0x425C0104UL)) +#define bFM4_CRTRIM_MCR_TTRM_TRT2 *((volatile unsigned int*)(0x425C0108UL)) +#define bFM4_CRTRIM_MCR_TTRM_TRT3 *((volatile unsigned int*)(0x425C010CUL)) +#define bFM4_CRTRIM_MCR_TTRM_TRT4 *((volatile unsigned int*)(0x425C0110UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK0 *((volatile unsigned int*)(0x425C0180UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK1 *((volatile unsigned int*)(0x425C0184UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK2 *((volatile unsigned int*)(0x425C0188UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK3 *((volatile unsigned int*)(0x425C018CUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK4 *((volatile unsigned int*)(0x425C0190UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK5 *((volatile unsigned int*)(0x425C0194UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK6 *((volatile unsigned int*)(0x425C0198UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK7 *((volatile unsigned int*)(0x425C019CUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK8 *((volatile unsigned int*)(0x425C01A0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK9 *((volatile unsigned int*)(0x425C01A4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK10 *((volatile unsigned int*)(0x425C01A8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK11 *((volatile unsigned int*)(0x425C01ACUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK12 *((volatile unsigned int*)(0x425C01B0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK13 *((volatile unsigned int*)(0x425C01B4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK14 *((volatile unsigned int*)(0x425C01B8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK15 *((volatile unsigned int*)(0x425C01BCUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK16 *((volatile unsigned int*)(0x425C01C0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK17 *((volatile unsigned int*)(0x425C01C4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK18 *((volatile unsigned int*)(0x425C01C8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK19 *((volatile unsigned int*)(0x425C01CCUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK20 *((volatile unsigned int*)(0x425C01D0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK21 *((volatile unsigned int*)(0x425C01D4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK22 *((volatile unsigned int*)(0x425C01D8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK23 *((volatile unsigned int*)(0x425C01DCUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK24 *((volatile unsigned int*)(0x425C01E0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK25 *((volatile unsigned int*)(0x425C01E4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK26 *((volatile unsigned int*)(0x425C01E8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK27 *((volatile unsigned int*)(0x425C01ECUL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK28 *((volatile unsigned int*)(0x425C01F0UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK29 *((volatile unsigned int*)(0x425C01F4UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK30 *((volatile unsigned int*)(0x425C01F8UL)) +#define bFM4_CRTRIM_MCR_RLR_TRMLCK31 *((volatile unsigned int*)(0x425C01FCUL)) + +/* External interrupt registers */ +#define bFM4_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM4_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM4_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM4_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM4_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM4_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM4_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM4_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM4_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM4_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM4_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM4_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM4_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM4_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM4_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM4_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM4_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) +#define bFM4_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) +#define bFM4_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) +#define bFM4_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) +#define bFM4_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) +#define bFM4_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) +#define bFM4_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) +#define bFM4_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) +#define bFM4_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) +#define bFM4_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) +#define bFM4_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) +#define bFM4_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) +#define bFM4_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) +#define bFM4_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) +#define bFM4_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) +#define bFM4_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) +#define bFM4_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM4_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM4_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM4_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM4_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM4_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM4_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM4_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM4_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM4_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM4_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM4_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM4_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM4_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM4_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM4_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM4_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) +#define bFM4_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) +#define bFM4_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) +#define bFM4_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) +#define bFM4_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) +#define bFM4_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) +#define bFM4_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) +#define bFM4_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) +#define bFM4_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) +#define bFM4_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) +#define bFM4_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) +#define bFM4_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) +#define bFM4_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) +#define bFM4_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) +#define bFM4_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) +#define bFM4_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) +#define bFM4_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM4_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM4_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM4_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM4_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM4_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM4_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM4_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM4_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM4_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM4_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM4_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM4_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM4_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM4_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM4_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM4_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) +#define bFM4_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) +#define bFM4_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) +#define bFM4_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) +#define bFM4_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) +#define bFM4_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) +#define bFM4_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) +#define bFM4_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) +#define bFM4_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) +#define bFM4_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) +#define bFM4_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) +#define bFM4_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) +#define bFM4_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) +#define bFM4_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) +#define bFM4_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) +#define bFM4_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) +#define bFM4_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM4_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM4_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM4_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM4_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM4_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM4_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM4_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM4_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM4_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM4_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM4_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM4_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM4_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM4_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM4_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM4_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM4_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM4_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM4_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM4_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM4_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM4_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM4_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM4_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM4_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM4_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM4_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM4_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM4_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM4_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM4_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM4_EXTI_ELVR1_LA16 *((volatile unsigned int*)(0x42600200UL)) +#define bFM4_EXTI_ELVR1_LB16 *((volatile unsigned int*)(0x42600204UL)) +#define bFM4_EXTI_ELVR1_LA17 *((volatile unsigned int*)(0x42600208UL)) +#define bFM4_EXTI_ELVR1_LB17 *((volatile unsigned int*)(0x4260020CUL)) +#define bFM4_EXTI_ELVR1_LA18 *((volatile unsigned int*)(0x42600210UL)) +#define bFM4_EXTI_ELVR1_LB18 *((volatile unsigned int*)(0x42600214UL)) +#define bFM4_EXTI_ELVR1_LA19 *((volatile unsigned int*)(0x42600218UL)) +#define bFM4_EXTI_ELVR1_LB19 *((volatile unsigned int*)(0x4260021CUL)) +#define bFM4_EXTI_ELVR1_LA20 *((volatile unsigned int*)(0x42600220UL)) +#define bFM4_EXTI_ELVR1_LB20 *((volatile unsigned int*)(0x42600224UL)) +#define bFM4_EXTI_ELVR1_LA21 *((volatile unsigned int*)(0x42600228UL)) +#define bFM4_EXTI_ELVR1_LB21 *((volatile unsigned int*)(0x4260022CUL)) +#define bFM4_EXTI_ELVR1_LA22 *((volatile unsigned int*)(0x42600230UL)) +#define bFM4_EXTI_ELVR1_LB22 *((volatile unsigned int*)(0x42600234UL)) +#define bFM4_EXTI_ELVR1_LA23 *((volatile unsigned int*)(0x42600238UL)) +#define bFM4_EXTI_ELVR1_LB23 *((volatile unsigned int*)(0x4260023CUL)) +#define bFM4_EXTI_ELVR1_LA24 *((volatile unsigned int*)(0x42600240UL)) +#define bFM4_EXTI_ELVR1_LB24 *((volatile unsigned int*)(0x42600244UL)) +#define bFM4_EXTI_ELVR1_LA25 *((volatile unsigned int*)(0x42600248UL)) +#define bFM4_EXTI_ELVR1_LB25 *((volatile unsigned int*)(0x4260024CUL)) +#define bFM4_EXTI_ELVR1_LA26 *((volatile unsigned int*)(0x42600250UL)) +#define bFM4_EXTI_ELVR1_LB26 *((volatile unsigned int*)(0x42600254UL)) +#define bFM4_EXTI_ELVR1_LA27 *((volatile unsigned int*)(0x42600258UL)) +#define bFM4_EXTI_ELVR1_LB27 *((volatile unsigned int*)(0x4260025CUL)) +#define bFM4_EXTI_ELVR1_LA28 *((volatile unsigned int*)(0x42600260UL)) +#define bFM4_EXTI_ELVR1_LB28 *((volatile unsigned int*)(0x42600264UL)) +#define bFM4_EXTI_ELVR1_LA29 *((volatile unsigned int*)(0x42600268UL)) +#define bFM4_EXTI_ELVR1_LB29 *((volatile unsigned int*)(0x4260026CUL)) +#define bFM4_EXTI_ELVR1_LA30 *((volatile unsigned int*)(0x42600270UL)) +#define bFM4_EXTI_ELVR1_LB30 *((volatile unsigned int*)(0x42600274UL)) +#define bFM4_EXTI_ELVR1_LA31 *((volatile unsigned int*)(0x42600278UL)) +#define bFM4_EXTI_ELVR1_LB31 *((volatile unsigned int*)(0x4260027CUL)) +#define bFM4_EXTI_NMIRR_NR *((volatile unsigned int*)(0x42600280UL)) +#define bFM4_EXTI_NMICL_NCL *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM4_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM4_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned int*)(0x42620200UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned int*)(0x42620204UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned int*)(0x42620208UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned int*)(0x4262020CUL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned int*)(0x42620210UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ0 *((volatile unsigned int*)(0x42622200UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ1 *((volatile unsigned int*)(0x42622204UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ2 *((volatile unsigned int*)(0x42622208UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ3 *((volatile unsigned int*)(0x4262220CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ4 *((volatile unsigned int*)(0x42622210UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ5 *((volatile unsigned int*)(0x42622214UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ6 *((volatile unsigned int*)(0x42622218UL)) +#define bFM4_INTREQ_IRQ003SEL_SELIRQ7 *((volatile unsigned int*)(0x4262221CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT0 *((volatile unsigned int*)(0x42622240UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT1 *((volatile unsigned int*)(0x42622244UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT2 *((volatile unsigned int*)(0x42622248UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT3 *((volatile unsigned int*)(0x4262224CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT4 *((volatile unsigned int*)(0x42622250UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT5 *((volatile unsigned int*)(0x42622254UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT6 *((volatile unsigned int*)(0x42622258UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT7 *((volatile unsigned int*)(0x4262225CUL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ0 *((volatile unsigned int*)(0x42622280UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ1 *((volatile unsigned int*)(0x42622284UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ2 *((volatile unsigned int*)(0x42622288UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ3 *((volatile unsigned int*)(0x4262228CUL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ4 *((volatile unsigned int*)(0x42622290UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ5 *((volatile unsigned int*)(0x42622294UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ6 *((volatile unsigned int*)(0x42622298UL)) +#define bFM4_INTREQ_IRQ004SEL_SELIRQ7 *((volatile unsigned int*)(0x4262229CUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT0 *((volatile unsigned int*)(0x426222C0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT1 *((volatile unsigned int*)(0x426222C4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT2 *((volatile unsigned int*)(0x426222C8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT3 *((volatile unsigned int*)(0x426222CCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT4 *((volatile unsigned int*)(0x426222D0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT5 *((volatile unsigned int*)(0x426222D4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT6 *((volatile unsigned int*)(0x426222D8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT7 *((volatile unsigned int*)(0x426222DCUL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ0 *((volatile unsigned int*)(0x42622300UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ1 *((volatile unsigned int*)(0x42622304UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ2 *((volatile unsigned int*)(0x42622308UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ3 *((volatile unsigned int*)(0x4262230CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ4 *((volatile unsigned int*)(0x42622310UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ5 *((volatile unsigned int*)(0x42622314UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ6 *((volatile unsigned int*)(0x42622318UL)) +#define bFM4_INTREQ_IRQ005SEL_SELIRQ7 *((volatile unsigned int*)(0x4262231CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT0 *((volatile unsigned int*)(0x42622340UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT1 *((volatile unsigned int*)(0x42622344UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT2 *((volatile unsigned int*)(0x42622348UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT3 *((volatile unsigned int*)(0x4262234CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT4 *((volatile unsigned int*)(0x42622350UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT5 *((volatile unsigned int*)(0x42622354UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT6 *((volatile unsigned int*)(0x42622358UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT7 *((volatile unsigned int*)(0x4262235CUL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ0 *((volatile unsigned int*)(0x42622380UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ1 *((volatile unsigned int*)(0x42622384UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ2 *((volatile unsigned int*)(0x42622388UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ3 *((volatile unsigned int*)(0x4262238CUL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ4 *((volatile unsigned int*)(0x42622390UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ5 *((volatile unsigned int*)(0x42622394UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ6 *((volatile unsigned int*)(0x42622398UL)) +#define bFM4_INTREQ_IRQ006SEL_SELIRQ7 *((volatile unsigned int*)(0x4262239CUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT0 *((volatile unsigned int*)(0x426223C0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT1 *((volatile unsigned int*)(0x426223C4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT2 *((volatile unsigned int*)(0x426223C8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT3 *((volatile unsigned int*)(0x426223CCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT4 *((volatile unsigned int*)(0x426223D0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT5 *((volatile unsigned int*)(0x426223D4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT6 *((volatile unsigned int*)(0x426223D8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT7 *((volatile unsigned int*)(0x426223DCUL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ0 *((volatile unsigned int*)(0x42622400UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ1 *((volatile unsigned int*)(0x42622404UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ2 *((volatile unsigned int*)(0x42622408UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ3 *((volatile unsigned int*)(0x4262240CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ4 *((volatile unsigned int*)(0x42622410UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ5 *((volatile unsigned int*)(0x42622414UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ6 *((volatile unsigned int*)(0x42622418UL)) +#define bFM4_INTREQ_IRQ007SEL_SELIRQ7 *((volatile unsigned int*)(0x4262241CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT0 *((volatile unsigned int*)(0x42622440UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT1 *((volatile unsigned int*)(0x42622444UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT2 *((volatile unsigned int*)(0x42622448UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT3 *((volatile unsigned int*)(0x4262244CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT4 *((volatile unsigned int*)(0x42622450UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT5 *((volatile unsigned int*)(0x42622454UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT6 *((volatile unsigned int*)(0x42622458UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT7 *((volatile unsigned int*)(0x4262245CUL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ0 *((volatile unsigned int*)(0x42622480UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ1 *((volatile unsigned int*)(0x42622484UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ2 *((volatile unsigned int*)(0x42622488UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ3 *((volatile unsigned int*)(0x4262248CUL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ4 *((volatile unsigned int*)(0x42622490UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ5 *((volatile unsigned int*)(0x42622494UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ6 *((volatile unsigned int*)(0x42622498UL)) +#define bFM4_INTREQ_IRQ008SEL_SELIRQ7 *((volatile unsigned int*)(0x4262249CUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT0 *((volatile unsigned int*)(0x426224C0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT1 *((volatile unsigned int*)(0x426224C4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT2 *((volatile unsigned int*)(0x426224C8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT3 *((volatile unsigned int*)(0x426224CCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT4 *((volatile unsigned int*)(0x426224D0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT5 *((volatile unsigned int*)(0x426224D4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT6 *((volatile unsigned int*)(0x426224D8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT7 *((volatile unsigned int*)(0x426224DCUL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ0 *((volatile unsigned int*)(0x42622500UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ1 *((volatile unsigned int*)(0x42622504UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ2 *((volatile unsigned int*)(0x42622508UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ3 *((volatile unsigned int*)(0x4262250CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ4 *((volatile unsigned int*)(0x42622510UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ5 *((volatile unsigned int*)(0x42622514UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ6 *((volatile unsigned int*)(0x42622518UL)) +#define bFM4_INTREQ_IRQ009SEL_SELIRQ7 *((volatile unsigned int*)(0x4262251CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT0 *((volatile unsigned int*)(0x42622540UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT1 *((volatile unsigned int*)(0x42622544UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT2 *((volatile unsigned int*)(0x42622548UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT3 *((volatile unsigned int*)(0x4262254CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT4 *((volatile unsigned int*)(0x42622550UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT5 *((volatile unsigned int*)(0x42622554UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT6 *((volatile unsigned int*)(0x42622558UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT7 *((volatile unsigned int*)(0x4262255CUL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ0 *((volatile unsigned int*)(0x42622580UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ1 *((volatile unsigned int*)(0x42622584UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ2 *((volatile unsigned int*)(0x42622588UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ3 *((volatile unsigned int*)(0x4262258CUL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ4 *((volatile unsigned int*)(0x42622590UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ5 *((volatile unsigned int*)(0x42622594UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ6 *((volatile unsigned int*)(0x42622598UL)) +#define bFM4_INTREQ_IRQ010SEL_SELIRQ7 *((volatile unsigned int*)(0x4262259CUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT0 *((volatile unsigned int*)(0x426225C0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT1 *((volatile unsigned int*)(0x426225C4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT2 *((volatile unsigned int*)(0x426225C8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT3 *((volatile unsigned int*)(0x426225CCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT4 *((volatile unsigned int*)(0x426225D0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT5 *((volatile unsigned int*)(0x426225D4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT6 *((volatile unsigned int*)(0x426225D8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT7 *((volatile unsigned int*)(0x426225DCUL)) +#define bFM4_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42624000UL)) +#define bFM4_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42624004UL)) +#define bFM4_INTREQ_IRQ000MON_FCSINT *((volatile unsigned int*)(0x42624080UL)) +#define bFM4_INTREQ_IRQ001MON_SWWDTINT *((volatile unsigned int*)(0x42624100UL)) +#define bFM4_INTREQ_IRQ002MON_LVDINT *((volatile unsigned int*)(0x42624180UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT0 *((volatile unsigned int*)(0x42624200UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT1 *((volatile unsigned int*)(0x42624204UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT2 *((volatile unsigned int*)(0x42624208UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT3 *((volatile unsigned int*)(0x4262420CUL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT4 *((volatile unsigned int*)(0x42624210UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT5 *((volatile unsigned int*)(0x42624214UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT6 *((volatile unsigned int*)(0x42624218UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT7 *((volatile unsigned int*)(0x4262421CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT0 *((volatile unsigned int*)(0x42624280UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT1 *((volatile unsigned int*)(0x42624284UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT2 *((volatile unsigned int*)(0x42624288UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT3 *((volatile unsigned int*)(0x4262428CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT4 *((volatile unsigned int*)(0x42624290UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT5 *((volatile unsigned int*)(0x42624294UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT6 *((volatile unsigned int*)(0x42624298UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT7 *((volatile unsigned int*)(0x4262429CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT0 *((volatile unsigned int*)(0x42624300UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT1 *((volatile unsigned int*)(0x42624304UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT2 *((volatile unsigned int*)(0x42624308UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT3 *((volatile unsigned int*)(0x4262430CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT4 *((volatile unsigned int*)(0x42624310UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT5 *((volatile unsigned int*)(0x42624314UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT6 *((volatile unsigned int*)(0x42624318UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT7 *((volatile unsigned int*)(0x4262431CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT0 *((volatile unsigned int*)(0x42624380UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT1 *((volatile unsigned int*)(0x42624384UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT2 *((volatile unsigned int*)(0x42624388UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT3 *((volatile unsigned int*)(0x4262438CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT4 *((volatile unsigned int*)(0x42624390UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT5 *((volatile unsigned int*)(0x42624394UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT6 *((volatile unsigned int*)(0x42624398UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT7 *((volatile unsigned int*)(0x4262439CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT0 *((volatile unsigned int*)(0x42624400UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT1 *((volatile unsigned int*)(0x42624404UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT2 *((volatile unsigned int*)(0x42624408UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT3 *((volatile unsigned int*)(0x4262440CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT4 *((volatile unsigned int*)(0x42624410UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT5 *((volatile unsigned int*)(0x42624414UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT6 *((volatile unsigned int*)(0x42624418UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT7 *((volatile unsigned int*)(0x4262441CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT0 *((volatile unsigned int*)(0x42624480UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT1 *((volatile unsigned int*)(0x42624484UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT2 *((volatile unsigned int*)(0x42624488UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT3 *((volatile unsigned int*)(0x4262448CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT4 *((volatile unsigned int*)(0x42624490UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT5 *((volatile unsigned int*)(0x42624494UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT6 *((volatile unsigned int*)(0x42624498UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT7 *((volatile unsigned int*)(0x4262449CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT0 *((volatile unsigned int*)(0x42624500UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT1 *((volatile unsigned int*)(0x42624504UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT2 *((volatile unsigned int*)(0x42624508UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT3 *((volatile unsigned int*)(0x4262450CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT4 *((volatile unsigned int*)(0x42624510UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT5 *((volatile unsigned int*)(0x42624514UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT6 *((volatile unsigned int*)(0x42624518UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT7 *((volatile unsigned int*)(0x4262451CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT0 *((volatile unsigned int*)(0x42624580UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT1 *((volatile unsigned int*)(0x42624584UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT2 *((volatile unsigned int*)(0x42624588UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT3 *((volatile unsigned int*)(0x4262458CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT4 *((volatile unsigned int*)(0x42624590UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT5 *((volatile unsigned int*)(0x42624594UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT6 *((volatile unsigned int*)(0x42624598UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT7 *((volatile unsigned int*)(0x4262459CUL)) +#define bFM4_INTREQ_IRQ011MON_EXTINT *((volatile unsigned int*)(0x42624600UL)) +#define bFM4_INTREQ_IRQ012MON_EXTINT *((volatile unsigned int*)(0x42624680UL)) +#define bFM4_INTREQ_IRQ013MON_EXTINT *((volatile unsigned int*)(0x42624700UL)) +#define bFM4_INTREQ_IRQ014MON_EXTINT *((volatile unsigned int*)(0x42624780UL)) +#define bFM4_INTREQ_IRQ015MON_EXTINT *((volatile unsigned int*)(0x42624800UL)) +#define bFM4_INTREQ_IRQ016MON_EXTINT *((volatile unsigned int*)(0x42624880UL)) +#define bFM4_INTREQ_IRQ017MON_EXTINT *((volatile unsigned int*)(0x42624900UL)) +#define bFM4_INTREQ_IRQ018MON_EXTINT *((volatile unsigned int*)(0x42624980UL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT0 *((volatile unsigned int*)(0x42624A00UL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT1 *((volatile unsigned int*)(0x42624A04UL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT2 *((volatile unsigned int*)(0x42624A08UL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT3 *((volatile unsigned int*)(0x42624A0CUL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT4 *((volatile unsigned int*)(0x42624A10UL)) +#define bFM4_INTREQ_IRQ019MON_QUDINT5 *((volatile unsigned int*)(0x42624A14UL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT0 *((volatile unsigned int*)(0x42624A80UL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT1 *((volatile unsigned int*)(0x42624A84UL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT2 *((volatile unsigned int*)(0x42624A88UL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT3 *((volatile unsigned int*)(0x42624A8CUL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT4 *((volatile unsigned int*)(0x42624A90UL)) +#define bFM4_INTREQ_IRQ020MON_QUDINT5 *((volatile unsigned int*)(0x42624A94UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT0 *((volatile unsigned int*)(0x42624B00UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT1 *((volatile unsigned int*)(0x42624B04UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT2 *((volatile unsigned int*)(0x42624B08UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT3 *((volatile unsigned int*)(0x42624B0CUL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT0 *((volatile unsigned int*)(0x42624B80UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT1 *((volatile unsigned int*)(0x42624B84UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT2 *((volatile unsigned int*)(0x42624B88UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT3 *((volatile unsigned int*)(0x42624B8CUL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT0 *((volatile unsigned int*)(0x42624C00UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT1 *((volatile unsigned int*)(0x42624C04UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT2 *((volatile unsigned int*)(0x42624C08UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT3 *((volatile unsigned int*)(0x42624C0CUL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42624C80UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42624C84UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42624C88UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42624D00UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42624D04UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42624D08UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT0 *((volatile unsigned int*)(0x42624D80UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT1 *((volatile unsigned int*)(0x42624D84UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT2 *((volatile unsigned int*)(0x42624D88UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT3 *((volatile unsigned int*)(0x42624D8CUL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT0 *((volatile unsigned int*)(0x42624E00UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT1 *((volatile unsigned int*)(0x42624E04UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT2 *((volatile unsigned int*)(0x42624E08UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT3 *((volatile unsigned int*)(0x42624E0CUL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT4 *((volatile unsigned int*)(0x42624E10UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT5 *((volatile unsigned int*)(0x42624E14UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42624E80UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42624E84UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42624E88UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42624F00UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42624F04UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42624F08UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT0 *((volatile unsigned int*)(0x42624F80UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT1 *((volatile unsigned int*)(0x42624F84UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT2 *((volatile unsigned int*)(0x42624F88UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT3 *((volatile unsigned int*)(0x42624F8CUL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT0 *((volatile unsigned int*)(0x42625000UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT1 *((volatile unsigned int*)(0x42625004UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT2 *((volatile unsigned int*)(0x42625008UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT3 *((volatile unsigned int*)(0x4262500CUL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT4 *((volatile unsigned int*)(0x42625010UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT5 *((volatile unsigned int*)(0x42625014UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42625080UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42625084UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42625088UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42625100UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42625104UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42625108UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT0 *((volatile unsigned int*)(0x42625180UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT1 *((volatile unsigned int*)(0x42625184UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT2 *((volatile unsigned int*)(0x42625188UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT3 *((volatile unsigned int*)(0x4262518CUL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT0 *((volatile unsigned int*)(0x42625200UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT1 *((volatile unsigned int*)(0x42625204UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT2 *((volatile unsigned int*)(0x42625208UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT3 *((volatile unsigned int*)(0x4262520CUL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT4 *((volatile unsigned int*)(0x42625210UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT5 *((volatile unsigned int*)(0x42625214UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT0 *((volatile unsigned int*)(0x42625280UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT1 *((volatile unsigned int*)(0x42625284UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT2 *((volatile unsigned int*)(0x42625288UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT0 *((volatile unsigned int*)(0x42625300UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT1 *((volatile unsigned int*)(0x42625304UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT2 *((volatile unsigned int*)(0x42625308UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT0 *((volatile unsigned int*)(0x42625380UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT1 *((volatile unsigned int*)(0x42625384UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT2 *((volatile unsigned int*)(0x42625388UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT0 *((volatile unsigned int*)(0x42625400UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT1 *((volatile unsigned int*)(0x42625404UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT0 *((volatile unsigned int*)(0x42625480UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT1 *((volatile unsigned int*)(0x42625484UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT0 *((volatile unsigned int*)(0x42625500UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT1 *((volatile unsigned int*)(0x42625504UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT0 *((volatile unsigned int*)(0x42625580UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT1 *((volatile unsigned int*)(0x42625584UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT0 *((volatile unsigned int*)(0x42625600UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT1 *((volatile unsigned int*)(0x42625604UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT0 *((volatile unsigned int*)(0x42625680UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT1 *((volatile unsigned int*)(0x42625684UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT0 *((volatile unsigned int*)(0x42625700UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT1 *((volatile unsigned int*)(0x42625704UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT0 *((volatile unsigned int*)(0x42625780UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT1 *((volatile unsigned int*)(0x42625784UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT1 *((volatile unsigned int*)(0x42625800UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT2 *((volatile unsigned int*)(0x42625804UL)) +#define bFM4_INTREQ_IRQ048MON_WCINT *((volatile unsigned int*)(0x42625880UL)) +#define bFM4_INTREQ_IRQ049MON_BMEMCS *((volatile unsigned int*)(0x42625900UL)) +#define bFM4_INTREQ_IRQ050MON_RTCINT *((volatile unsigned int*)(0x42625980UL)) +#define bFM4_INTREQ_IRQ051MON_EXTINT *((volatile unsigned int*)(0x42625A00UL)) +#define bFM4_INTREQ_IRQ052MON_EXTINT *((volatile unsigned int*)(0x42625A80UL)) +#define bFM4_INTREQ_IRQ053MON_EXTINT *((volatile unsigned int*)(0x42625B00UL)) +#define bFM4_INTREQ_IRQ054MON_EXTINT *((volatile unsigned int*)(0x42625B80UL)) +#define bFM4_INTREQ_IRQ055MON_EXTINT *((volatile unsigned int*)(0x42625C00UL)) +#define bFM4_INTREQ_IRQ056MON_EXTINT *((volatile unsigned int*)(0x42625C80UL)) +#define bFM4_INTREQ_IRQ057MON_EXTINT *((volatile unsigned int*)(0x42625D00UL)) +#define bFM4_INTREQ_IRQ058MON_EXTINT *((volatile unsigned int*)(0x42625D80UL)) +#define bFM4_INTREQ_IRQ059MON_MOSCINT *((volatile unsigned int*)(0x42625E00UL)) +#define bFM4_INTREQ_IRQ059MON_SOSCINT *((volatile unsigned int*)(0x42625E04UL)) +#define bFM4_INTREQ_IRQ059MON_MPLLINT *((volatile unsigned int*)(0x42625E08UL)) +#define bFM4_INTREQ_IRQ059MON_UPLLINT *((volatile unsigned int*)(0x42625E0CUL)) +#define bFM4_INTREQ_IRQ060MON_MFSRINT *((volatile unsigned int*)(0x42625E80UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT0 *((volatile unsigned int*)(0x42625F00UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT1 *((volatile unsigned int*)(0x42625F04UL)) +#define bFM4_INTREQ_IRQ062MON_MFSRINT *((volatile unsigned int*)(0x42625F80UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT0 *((volatile unsigned int*)(0x42626000UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT1 *((volatile unsigned int*)(0x42626004UL)) +#define bFM4_INTREQ_IRQ064MON_MFSRINT *((volatile unsigned int*)(0x42626080UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT0 *((volatile unsigned int*)(0x42626100UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT1 *((volatile unsigned int*)(0x42626104UL)) +#define bFM4_INTREQ_IRQ066MON_MFSRINT *((volatile unsigned int*)(0x42626180UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT0 *((volatile unsigned int*)(0x42626200UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT1 *((volatile unsigned int*)(0x42626204UL)) +#define bFM4_INTREQ_IRQ068MON_MFSRINT *((volatile unsigned int*)(0x42626280UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT0 *((volatile unsigned int*)(0x42626300UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT1 *((volatile unsigned int*)(0x42626304UL)) +#define bFM4_INTREQ_IRQ070MON_MFSRINT *((volatile unsigned int*)(0x42626380UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT0 *((volatile unsigned int*)(0x42626400UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT1 *((volatile unsigned int*)(0x42626404UL)) +#define bFM4_INTREQ_IRQ072MON_MFSRINT *((volatile unsigned int*)(0x42626480UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT0 *((volatile unsigned int*)(0x42626500UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT1 *((volatile unsigned int*)(0x42626504UL)) +#define bFM4_INTREQ_IRQ074MON_MFSRINT *((volatile unsigned int*)(0x42626580UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT0 *((volatile unsigned int*)(0x42626600UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT1 *((volatile unsigned int*)(0x42626604UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT0 *((volatile unsigned int*)(0x42626680UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT1 *((volatile unsigned int*)(0x42626684UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT2 *((volatile unsigned int*)(0x42626688UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT3 *((volatile unsigned int*)(0x4262668CUL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT4 *((volatile unsigned int*)(0x42626690UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT0 *((volatile unsigned int*)(0x42626700UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT1 *((volatile unsigned int*)(0x42626704UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT2 *((volatile unsigned int*)(0x42626708UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT3 *((volatile unsigned int*)(0x4262670CUL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT4 *((volatile unsigned int*)(0x42626710UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile unsigned int*)(0x42626780UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile unsigned int*)(0x42626784UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile unsigned int*)(0x42626788UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile unsigned int*)(0x4262678CUL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile unsigned int*)(0x42626790UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT0 *((volatile unsigned int*)(0x42626800UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT1 *((volatile unsigned int*)(0x42626804UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT2 *((volatile unsigned int*)(0x42626808UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT3 *((volatile unsigned int*)(0x4262680CUL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT4 *((volatile unsigned int*)(0x42626810UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT5 *((volatile unsigned int*)(0x42626814UL)) +#define bFM4_INTREQ_IRQ080MON_CANINT *((volatile unsigned int*)(0x42626880UL)) +#define bFM4_INTREQ_IRQ081MON_CANINT *((volatile unsigned int*)(0x42626900UL)) +#define bFM4_INTREQ_IRQ082MON_MACSBD *((volatile unsigned int*)(0x42626980UL)) +#define bFM4_INTREQ_IRQ082MON_MACPMT *((volatile unsigned int*)(0x42626984UL)) +#define bFM4_INTREQ_IRQ082MON_MACLPI *((volatile unsigned int*)(0x42626988UL)) +#define bFM4_INTREQ_IRQ083MON_DMACINT *((volatile unsigned int*)(0x42626A00UL)) +#define bFM4_INTREQ_IRQ084MON_DMACINT *((volatile unsigned int*)(0x42626A80UL)) +#define bFM4_INTREQ_IRQ085MON_DMACINT *((volatile unsigned int*)(0x42626B00UL)) +#define bFM4_INTREQ_IRQ086MON_DMACINT *((volatile unsigned int*)(0x42626B80UL)) +#define bFM4_INTREQ_IRQ087MON_DMACINT *((volatile unsigned int*)(0x42626C00UL)) +#define bFM4_INTREQ_IRQ088MON_DMACINT *((volatile unsigned int*)(0x42626C80UL)) +#define bFM4_INTREQ_IRQ089MON_DMACINT *((volatile unsigned int*)(0x42626D00UL)) +#define bFM4_INTREQ_IRQ090MON_DMACINT *((volatile unsigned int*)(0x42626D80UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT0 *((volatile unsigned int*)(0x42626E00UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT1 *((volatile unsigned int*)(0x42626E04UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT0 *((volatile unsigned int*)(0x42626E80UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT1 *((volatile unsigned int*)(0x42626E84UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT2 *((volatile unsigned int*)(0x42626E88UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT3 *((volatile unsigned int*)(0x42626E8CUL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT0 *((volatile unsigned int*)(0x42626F00UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT1 *((volatile unsigned int*)(0x42626F04UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT2 *((volatile unsigned int*)(0x42626F08UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT3 *((volatile unsigned int*)(0x42626F0CUL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT0 *((volatile unsigned int*)(0x42626F80UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT1 *((volatile unsigned int*)(0x42626F84UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT2 *((volatile unsigned int*)(0x42626F88UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT3 *((volatile unsigned int*)(0x42626F8CUL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT0 *((volatile unsigned int*)(0x42627000UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT1 *((volatile unsigned int*)(0x42627004UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT2 *((volatile unsigned int*)(0x42627008UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT3 *((volatile unsigned int*)(0x4262700CUL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT0 *((volatile unsigned int*)(0x42627080UL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT1 *((volatile unsigned int*)(0x42627084UL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT2 *((volatile unsigned int*)(0x42627088UL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT3 *((volatile unsigned int*)(0x4262708CUL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT4 *((volatile unsigned int*)(0x42627090UL)) +#define bFM4_INTREQ_IRQ096MON_QUDINT5 *((volatile unsigned int*)(0x42627094UL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT0 *((volatile unsigned int*)(0x42627100UL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT1 *((volatile unsigned int*)(0x42627104UL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT2 *((volatile unsigned int*)(0x42627108UL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT3 *((volatile unsigned int*)(0x4262710CUL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT4 *((volatile unsigned int*)(0x42627110UL)) +#define bFM4_INTREQ_IRQ097MON_QUDINT5 *((volatile unsigned int*)(0x42627114UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT0 *((volatile unsigned int*)(0x42627180UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT1 *((volatile unsigned int*)(0x42627184UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT0 *((volatile unsigned int*)(0x42627200UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT1 *((volatile unsigned int*)(0x42627204UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT0 *((volatile unsigned int*)(0x42627280UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT1 *((volatile unsigned int*)(0x42627284UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT0 *((volatile unsigned int*)(0x42627300UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT1 *((volatile unsigned int*)(0x42627304UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT0 *((volatile unsigned int*)(0x42627380UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT1 *((volatile unsigned int*)(0x42627384UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT2 *((volatile unsigned int*)(0x42627388UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT3 *((volatile unsigned int*)(0x4262738CUL)) +#define bFM4_INTREQ_IRQ102MON_BTINT4 *((volatile unsigned int*)(0x42627390UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT5 *((volatile unsigned int*)(0x42627394UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT6 *((volatile unsigned int*)(0x42627398UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT7 *((volatile unsigned int*)(0x4262739CUL)) +#define bFM4_INTREQ_IRQ103MON_MFSRINT *((volatile unsigned int*)(0x42627400UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT0 *((volatile unsigned int*)(0x42627480UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT1 *((volatile unsigned int*)(0x42627484UL)) +#define bFM4_INTREQ_IRQ105MON_MFSRINT *((volatile unsigned int*)(0x42627500UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT0 *((volatile unsigned int*)(0x42627580UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT1 *((volatile unsigned int*)(0x42627584UL)) +#define bFM4_INTREQ_IRQ107MON_MFSRINT *((volatile unsigned int*)(0x42627600UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT0 *((volatile unsigned int*)(0x42627680UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT1 *((volatile unsigned int*)(0x42627684UL)) +#define bFM4_INTREQ_IRQ109MON_MFSRINT *((volatile unsigned int*)(0x42627700UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT0 *((volatile unsigned int*)(0x42627780UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT1 *((volatile unsigned int*)(0x42627784UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT0 *((volatile unsigned int*)(0x42627800UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT1 *((volatile unsigned int*)(0x42627804UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT2 *((volatile unsigned int*)(0x42627808UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT3 *((volatile unsigned int*)(0x4262780CUL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT4 *((volatile unsigned int*)(0x42627810UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile unsigned int*)(0x42627900UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile unsigned int*)(0x42627904UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile unsigned int*)(0x42627908UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile unsigned int*)(0x4262790CUL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile unsigned int*)(0x42627910UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT0 *((volatile unsigned int*)(0x42627980UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT1 *((volatile unsigned int*)(0x42627984UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT2 *((volatile unsigned int*)(0x42627988UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT3 *((volatile unsigned int*)(0x4262798CUL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT4 *((volatile unsigned int*)(0x42627990UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT5 *((volatile unsigned int*)(0x42627994UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT0 *((volatile unsigned int*)(0x42627B80UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT1 *((volatile unsigned int*)(0x42627B84UL)) +#define bFM4_INTREQ_IRQ119MON_FLINT *((volatile unsigned int*)(0x42627C00UL)) +#define bFM4_INTREQ_IRQ120MON_MFSRINT *((volatile unsigned int*)(0x42627C80UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT0 *((volatile unsigned int*)(0x42627D00UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT1 *((volatile unsigned int*)(0x42627D04UL)) +#define bFM4_INTREQ_IRQ122MON_MFSRINT *((volatile unsigned int*)(0x42627D80UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT0 *((volatile unsigned int*)(0x42627E00UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT1 *((volatile unsigned int*)(0x42627E04UL)) +#define bFM4_INTREQ_IRQ124MON_MFSRINT *((volatile unsigned int*)(0x42627E80UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT0 *((volatile unsigned int*)(0x42627F00UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT1 *((volatile unsigned int*)(0x42627F04UL)) +#define bFM4_INTREQ_IRQ126MON_MFSRINT *((volatile unsigned int*)(0x42627F80UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT0 *((volatile unsigned int*)(0x42628000UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT1 *((volatile unsigned int*)(0x42628004UL)) + +/* 12-bit DAC unit 0 registers */ +#define bFM4_DAC0_DACR_DAE *((volatile unsigned int*)(0x42660000UL)) +#define bFM4_DAC0_DACR_DRDY *((volatile unsigned int*)(0x42660004UL)) +#define bFM4_DAC0_DACR_DAC10 *((volatile unsigned int*)(0x42660010UL)) +#define bFM4_DAC0_DACR_DDAS *((volatile unsigned int*)(0x42660014UL)) +#define bFM4_DAC0_DADR_DA0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM4_DAC0_DADR_DA1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM4_DAC0_DADR_DA2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM4_DAC0_DADR_DA3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM4_DAC0_DADR_DA4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM4_DAC0_DADR_DA5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM4_DAC0_DADR_DA6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM4_DAC0_DADR_DA7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM4_DAC0_DADR_DA8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM4_DAC0_DADR_DA9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM4_DAC0_DADR_DA10 *((volatile unsigned int*)(0x426600A8UL)) +#define bFM4_DAC0_DADR_DA11 *((volatile unsigned int*)(0x426600ACUL)) + +/* 12-bit DAC unit 1 registers */ +#define bFM4_DAC1_DACR_DAE *((volatile unsigned int*)(0x42660100UL)) +#define bFM4_DAC1_DACR_DRDY *((volatile unsigned int*)(0x42660104UL)) +#define bFM4_DAC1_DACR_DAC10 *((volatile unsigned int*)(0x42660110UL)) +#define bFM4_DAC1_DACR_DDAS *((volatile unsigned int*)(0x42660114UL)) +#define bFM4_DAC1_DADR_DA0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM4_DAC1_DADR_DA1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM4_DAC1_DADR_DA2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM4_DAC1_DADR_DA3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM4_DAC1_DADR_DA4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM4_DAC1_DADR_DA5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM4_DAC1_DADR_DA6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM4_DAC1_DADR_DA7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM4_DAC1_DADR_DA8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM4_DAC1_DADR_DA9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM4_DAC1_DADR_DA10 *((volatile unsigned int*)(0x426601A8UL)) +#define bFM4_DAC1_DADR_DA11 *((volatile unsigned int*)(0x426601ACUL)) + +/* General purpose I/O registers */ +#define bFM4_GPIO_PFR0_P00 *((volatile unsigned int*)(0x42DE0000UL)) +#define bFM4_GPIO_PFR0_P01 *((volatile unsigned int*)(0x42DE0004UL)) +#define bFM4_GPIO_PFR0_P02 *((volatile unsigned int*)(0x42DE0008UL)) +#define bFM4_GPIO_PFR0_P03 *((volatile unsigned int*)(0x42DE000CUL)) +#define bFM4_GPIO_PFR0_P04 *((volatile unsigned int*)(0x42DE0010UL)) +#define bFM4_GPIO_PFR0_P05 *((volatile unsigned int*)(0x42DE0014UL)) +#define bFM4_GPIO_PFR0_P06 *((volatile unsigned int*)(0x42DE0018UL)) +#define bFM4_GPIO_PFR0_P07 *((volatile unsigned int*)(0x42DE001CUL)) +#define bFM4_GPIO_PFR0_P08 *((volatile unsigned int*)(0x42DE0020UL)) +#define bFM4_GPIO_PFR0_P09 *((volatile unsigned int*)(0x42DE0024UL)) +#define bFM4_GPIO_PFR0_P0A *((volatile unsigned int*)(0x42DE0028UL)) +#define bFM4_GPIO_PFR0_P0B *((volatile unsigned int*)(0x42DE002CUL)) +#define bFM4_GPIO_PFR0_P0C *((volatile unsigned int*)(0x42DE0030UL)) +#define bFM4_GPIO_PFR0_P0D *((volatile unsigned int*)(0x42DE0034UL)) +#define bFM4_GPIO_PFR0_P0E *((volatile unsigned int*)(0x42DE0038UL)) +#define bFM4_GPIO_PFR1_P10 *((volatile unsigned int*)(0x42DE0080UL)) +#define bFM4_GPIO_PFR1_P11 *((volatile unsigned int*)(0x42DE0084UL)) +#define bFM4_GPIO_PFR1_P12 *((volatile unsigned int*)(0x42DE0088UL)) +#define bFM4_GPIO_PFR1_P13 *((volatile unsigned int*)(0x42DE008CUL)) +#define bFM4_GPIO_PFR1_P14 *((volatile unsigned int*)(0x42DE0090UL)) +#define bFM4_GPIO_PFR1_P15 *((volatile unsigned int*)(0x42DE0094UL)) +#define bFM4_GPIO_PFR1_P16 *((volatile unsigned int*)(0x42DE0098UL)) +#define bFM4_GPIO_PFR1_P17 *((volatile unsigned int*)(0x42DE009CUL)) +#define bFM4_GPIO_PFR1_P18 *((volatile unsigned int*)(0x42DE00A0UL)) +#define bFM4_GPIO_PFR1_P19 *((volatile unsigned int*)(0x42DE00A4UL)) +#define bFM4_GPIO_PFR1_P1A *((volatile unsigned int*)(0x42DE00A8UL)) +#define bFM4_GPIO_PFR1_P1B *((volatile unsigned int*)(0x42DE00ACUL)) +#define bFM4_GPIO_PFR1_P1C *((volatile unsigned int*)(0x42DE00B0UL)) +#define bFM4_GPIO_PFR1_P1D *((volatile unsigned int*)(0x42DE00B4UL)) +#define bFM4_GPIO_PFR1_P1E *((volatile unsigned int*)(0x42DE00B8UL)) +#define bFM4_GPIO_PFR1_P1F *((volatile unsigned int*)(0x42DE00BCUL)) +#define bFM4_GPIO_PFR2_P20 *((volatile unsigned int*)(0x42DE0100UL)) +#define bFM4_GPIO_PFR2_P21 *((volatile unsigned int*)(0x42DE0104UL)) +#define bFM4_GPIO_PFR2_P22 *((volatile unsigned int*)(0x42DE0108UL)) +#define bFM4_GPIO_PFR2_P23 *((volatile unsigned int*)(0x42DE010CUL)) +#define bFM4_GPIO_PFR2_P24 *((volatile unsigned int*)(0x42DE0110UL)) +#define bFM4_GPIO_PFR2_P25 *((volatile unsigned int*)(0x42DE0114UL)) +#define bFM4_GPIO_PFR2_P26 *((volatile unsigned int*)(0x42DE0118UL)) +#define bFM4_GPIO_PFR2_P27 *((volatile unsigned int*)(0x42DE011CUL)) +#define bFM4_GPIO_PFR3_P30 *((volatile unsigned int*)(0x42DE0180UL)) +#define bFM4_GPIO_PFR3_P31 *((volatile unsigned int*)(0x42DE0184UL)) +#define bFM4_GPIO_PFR3_P32 *((volatile unsigned int*)(0x42DE0188UL)) +#define bFM4_GPIO_PFR3_P33 *((volatile unsigned int*)(0x42DE018CUL)) +#define bFM4_GPIO_PFR3_P34 *((volatile unsigned int*)(0x42DE0190UL)) +#define bFM4_GPIO_PFR3_P35 *((volatile unsigned int*)(0x42DE0194UL)) +#define bFM4_GPIO_PFR3_P36 *((volatile unsigned int*)(0x42DE0198UL)) +#define bFM4_GPIO_PFR3_P37 *((volatile unsigned int*)(0x42DE019CUL)) +#define bFM4_GPIO_PFR3_P38 *((volatile unsigned int*)(0x42DE01A0UL)) +#define bFM4_GPIO_PFR3_P39 *((volatile unsigned int*)(0x42DE01A4UL)) +#define bFM4_GPIO_PFR3_P3A *((volatile unsigned int*)(0x42DE01A8UL)) +#define bFM4_GPIO_PFR3_P3B *((volatile unsigned int*)(0x42DE01ACUL)) +#define bFM4_GPIO_PFR3_P3C *((volatile unsigned int*)(0x42DE01B0UL)) +#define bFM4_GPIO_PFR3_P3D *((volatile unsigned int*)(0x42DE01B4UL)) +#define bFM4_GPIO_PFR3_P3E *((volatile unsigned int*)(0x42DE01B8UL)) +#define bFM4_GPIO_PFR3_P3F *((volatile unsigned int*)(0x42DE01BCUL)) +#define bFM4_GPIO_PFR4_P40 *((volatile unsigned int*)(0x42DE0200UL)) +#define bFM4_GPIO_PFR4_P41 *((volatile unsigned int*)(0x42DE0204UL)) +#define bFM4_GPIO_PFR4_P42 *((volatile unsigned int*)(0x42DE0208UL)) +#define bFM4_GPIO_PFR4_P43 *((volatile unsigned int*)(0x42DE020CUL)) +#define bFM4_GPIO_PFR4_P44 *((volatile unsigned int*)(0x42DE0210UL)) +#define bFM4_GPIO_PFR4_P45 *((volatile unsigned int*)(0x42DE0214UL)) +#define bFM4_GPIO_PFR4_P46 *((volatile unsigned int*)(0x42DE0218UL)) +#define bFM4_GPIO_PFR4_P47 *((volatile unsigned int*)(0x42DE021CUL)) +#define bFM4_GPIO_PFR4_P48 *((volatile unsigned int*)(0x42DE0220UL)) +#define bFM4_GPIO_PFR4_P49 *((volatile unsigned int*)(0x42DE0224UL)) +#define bFM4_GPIO_PFR4_P4A *((volatile unsigned int*)(0x42DE0228UL)) +#define bFM4_GPIO_PFR4_P4B *((volatile unsigned int*)(0x42DE022CUL)) +#define bFM4_GPIO_PFR4_P4C *((volatile unsigned int*)(0x42DE0230UL)) +#define bFM4_GPIO_PFR4_P4D *((volatile unsigned int*)(0x42DE0234UL)) +#define bFM4_GPIO_PFR4_P4E *((volatile unsigned int*)(0x42DE0238UL)) +#define bFM4_GPIO_PFR5_P50 *((volatile unsigned int*)(0x42DE0280UL)) +#define bFM4_GPIO_PFR5_P51 *((volatile unsigned int*)(0x42DE0284UL)) +#define bFM4_GPIO_PFR5_P52 *((volatile unsigned int*)(0x42DE0288UL)) +#define bFM4_GPIO_PFR5_P53 *((volatile unsigned int*)(0x42DE028CUL)) +#define bFM4_GPIO_PFR5_P54 *((volatile unsigned int*)(0x42DE0290UL)) +#define bFM4_GPIO_PFR5_P55 *((volatile unsigned int*)(0x42DE0294UL)) +#define bFM4_GPIO_PFR5_P56 *((volatile unsigned int*)(0x42DE0298UL)) +#define bFM4_GPIO_PFR5_P57 *((volatile unsigned int*)(0x42DE029CUL)) +#define bFM4_GPIO_PFR5_P58 *((volatile unsigned int*)(0x42DE02A0UL)) +#define bFM4_GPIO_PFR5_P59 *((volatile unsigned int*)(0x42DE02A4UL)) +#define bFM4_GPIO_PFR5_P5A *((volatile unsigned int*)(0x42DE02A8UL)) +#define bFM4_GPIO_PFR5_P5B *((volatile unsigned int*)(0x42DE02ACUL)) +#define bFM4_GPIO_PFR6_P60 *((volatile unsigned int*)(0x42DE0300UL)) +#define bFM4_GPIO_PFR6_P61 *((volatile unsigned int*)(0x42DE0304UL)) +#define bFM4_GPIO_PFR6_P62 *((volatile unsigned int*)(0x42DE0308UL)) +#define bFM4_GPIO_PFR6_P63 *((volatile unsigned int*)(0x42DE030CUL)) +#define bFM4_GPIO_PFR6_P64 *((volatile unsigned int*)(0x42DE0310UL)) +#define bFM4_GPIO_PFR6_P65 *((volatile unsigned int*)(0x42DE0314UL)) +#define bFM4_GPIO_PFR6_P66 *((volatile unsigned int*)(0x42DE0318UL)) +#define bFM4_GPIO_PFR6_P67 *((volatile unsigned int*)(0x42DE031CUL)) +#define bFM4_GPIO_PFR6_P68 *((volatile unsigned int*)(0x42DE0320UL)) +#define bFM4_GPIO_PFR7_P70 *((volatile unsigned int*)(0x42DE0380UL)) +#define bFM4_GPIO_PFR7_P71 *((volatile unsigned int*)(0x42DE0384UL)) +#define bFM4_GPIO_PFR7_P72 *((volatile unsigned int*)(0x42DE0388UL)) +#define bFM4_GPIO_PFR7_P73 *((volatile unsigned int*)(0x42DE038CUL)) +#define bFM4_GPIO_PFR7_P74 *((volatile unsigned int*)(0x42DE0390UL)) +#define bFM4_GPIO_PFR8_P80 *((volatile unsigned int*)(0x42DE0400UL)) +#define bFM4_GPIO_PFR8_P81 *((volatile unsigned int*)(0x42DE0404UL)) +#define bFM4_GPIO_PFRE_PE0 *((volatile unsigned int*)(0x42DE0700UL)) +#define bFM4_GPIO_PFRE_PE2 *((volatile unsigned int*)(0x42DE0708UL)) +#define bFM4_GPIO_PFRE_PE3 *((volatile unsigned int*)(0x42DE070CUL)) +#define bFM4_GPIO_PCR0_P00 *((volatile unsigned int*)(0x42DE2000UL)) +#define bFM4_GPIO_PCR0_P01 *((volatile unsigned int*)(0x42DE2004UL)) +#define bFM4_GPIO_PCR0_P02 *((volatile unsigned int*)(0x42DE2008UL)) +#define bFM4_GPIO_PCR0_P03 *((volatile unsigned int*)(0x42DE200CUL)) +#define bFM4_GPIO_PCR0_P04 *((volatile unsigned int*)(0x42DE2010UL)) +#define bFM4_GPIO_PCR0_P05 *((volatile unsigned int*)(0x42DE2014UL)) +#define bFM4_GPIO_PCR0_P06 *((volatile unsigned int*)(0x42DE2018UL)) +#define bFM4_GPIO_PCR0_P07 *((volatile unsigned int*)(0x42DE201CUL)) +#define bFM4_GPIO_PCR0_P08 *((volatile unsigned int*)(0x42DE2020UL)) +#define bFM4_GPIO_PCR0_P09 *((volatile unsigned int*)(0x42DE2024UL)) +#define bFM4_GPIO_PCR0_P0A *((volatile unsigned int*)(0x42DE2028UL)) +#define bFM4_GPIO_PCR0_P0B *((volatile unsigned int*)(0x42DE202CUL)) +#define bFM4_GPIO_PCR0_P0C *((volatile unsigned int*)(0x42DE2030UL)) +#define bFM4_GPIO_PCR0_P0D *((volatile unsigned int*)(0x42DE2034UL)) +#define bFM4_GPIO_PCR0_P0E *((volatile unsigned int*)(0x42DE2038UL)) +#define bFM4_GPIO_PCR1_P10 *((volatile unsigned int*)(0x42DE2080UL)) +#define bFM4_GPIO_PCR1_P11 *((volatile unsigned int*)(0x42DE2084UL)) +#define bFM4_GPIO_PCR1_P12 *((volatile unsigned int*)(0x42DE2088UL)) +#define bFM4_GPIO_PCR1_P13 *((volatile unsigned int*)(0x42DE208CUL)) +#define bFM4_GPIO_PCR1_P14 *((volatile unsigned int*)(0x42DE2090UL)) +#define bFM4_GPIO_PCR1_P15 *((volatile unsigned int*)(0x42DE2094UL)) +#define bFM4_GPIO_PCR1_P16 *((volatile unsigned int*)(0x42DE2098UL)) +#define bFM4_GPIO_PCR1_P17 *((volatile unsigned int*)(0x42DE209CUL)) +#define bFM4_GPIO_PCR1_P18 *((volatile unsigned int*)(0x42DE20A0UL)) +#define bFM4_GPIO_PCR1_P19 *((volatile unsigned int*)(0x42DE20A4UL)) +#define bFM4_GPIO_PCR1_P1A *((volatile unsigned int*)(0x42DE20A8UL)) +#define bFM4_GPIO_PCR1_P1B *((volatile unsigned int*)(0x42DE20ACUL)) +#define bFM4_GPIO_PCR1_P1C *((volatile unsigned int*)(0x42DE20B0UL)) +#define bFM4_GPIO_PCR1_P1D *((volatile unsigned int*)(0x42DE20B4UL)) +#define bFM4_GPIO_PCR1_P1E *((volatile unsigned int*)(0x42DE20B8UL)) +#define bFM4_GPIO_PCR1_P1F *((volatile unsigned int*)(0x42DE20BCUL)) +#define bFM4_GPIO_PCR2_P20 *((volatile unsigned int*)(0x42DE2100UL)) +#define bFM4_GPIO_PCR2_P21 *((volatile unsigned int*)(0x42DE2104UL)) +#define bFM4_GPIO_PCR2_P22 *((volatile unsigned int*)(0x42DE2108UL)) +#define bFM4_GPIO_PCR2_P23 *((volatile unsigned int*)(0x42DE210CUL)) +#define bFM4_GPIO_PCR2_P24 *((volatile unsigned int*)(0x42DE2110UL)) +#define bFM4_GPIO_PCR2_P25 *((volatile unsigned int*)(0x42DE2114UL)) +#define bFM4_GPIO_PCR2_P26 *((volatile unsigned int*)(0x42DE2118UL)) +#define bFM4_GPIO_PCR2_P27 *((volatile unsigned int*)(0x42DE211CUL)) +#define bFM4_GPIO_PCR3_P30 *((volatile unsigned int*)(0x42DE2180UL)) +#define bFM4_GPIO_PCR3_P31 *((volatile unsigned int*)(0x42DE2184UL)) +#define bFM4_GPIO_PCR3_P32 *((volatile unsigned int*)(0x42DE2188UL)) +#define bFM4_GPIO_PCR3_P33 *((volatile unsigned int*)(0x42DE218CUL)) +#define bFM4_GPIO_PCR3_P34 *((volatile unsigned int*)(0x42DE2190UL)) +#define bFM4_GPIO_PCR3_P35 *((volatile unsigned int*)(0x42DE2194UL)) +#define bFM4_GPIO_PCR3_P36 *((volatile unsigned int*)(0x42DE2198UL)) +#define bFM4_GPIO_PCR3_P37 *((volatile unsigned int*)(0x42DE219CUL)) +#define bFM4_GPIO_PCR3_P38 *((volatile unsigned int*)(0x42DE21A0UL)) +#define bFM4_GPIO_PCR3_P39 *((volatile unsigned int*)(0x42DE21A4UL)) +#define bFM4_GPIO_PCR3_P3A *((volatile unsigned int*)(0x42DE21A8UL)) +#define bFM4_GPIO_PCR3_P3B *((volatile unsigned int*)(0x42DE21ACUL)) +#define bFM4_GPIO_PCR3_P3C *((volatile unsigned int*)(0x42DE21B0UL)) +#define bFM4_GPIO_PCR3_P3D *((volatile unsigned int*)(0x42DE21B4UL)) +#define bFM4_GPIO_PCR3_P3E *((volatile unsigned int*)(0x42DE21B8UL)) +#define bFM4_GPIO_PCR3_P3F *((volatile unsigned int*)(0x42DE21BCUL)) +#define bFM4_GPIO_PCR4_P40 *((volatile unsigned int*)(0x42DE2200UL)) +#define bFM4_GPIO_PCR4_P41 *((volatile unsigned int*)(0x42DE2204UL)) +#define bFM4_GPIO_PCR4_P42 *((volatile unsigned int*)(0x42DE2208UL)) +#define bFM4_GPIO_PCR4_P43 *((volatile unsigned int*)(0x42DE220CUL)) +#define bFM4_GPIO_PCR4_P44 *((volatile unsigned int*)(0x42DE2210UL)) +#define bFM4_GPIO_PCR4_P45 *((volatile unsigned int*)(0x42DE2214UL)) +#define bFM4_GPIO_PCR4_P46 *((volatile unsigned int*)(0x42DE2218UL)) +#define bFM4_GPIO_PCR4_P47 *((volatile unsigned int*)(0x42DE221CUL)) +#define bFM4_GPIO_PCR4_P48 *((volatile unsigned int*)(0x42DE2220UL)) +#define bFM4_GPIO_PCR4_P49 *((volatile unsigned int*)(0x42DE2224UL)) +#define bFM4_GPIO_PCR4_P4A *((volatile unsigned int*)(0x42DE2228UL)) +#define bFM4_GPIO_PCR4_P4B *((volatile unsigned int*)(0x42DE222CUL)) +#define bFM4_GPIO_PCR4_P4C *((volatile unsigned int*)(0x42DE2230UL)) +#define bFM4_GPIO_PCR4_P4D *((volatile unsigned int*)(0x42DE2234UL)) +#define bFM4_GPIO_PCR4_P4E *((volatile unsigned int*)(0x42DE2238UL)) +#define bFM4_GPIO_PCR5_P50 *((volatile unsigned int*)(0x42DE2280UL)) +#define bFM4_GPIO_PCR5_P51 *((volatile unsigned int*)(0x42DE2284UL)) +#define bFM4_GPIO_PCR5_P52 *((volatile unsigned int*)(0x42DE2288UL)) +#define bFM4_GPIO_PCR5_P53 *((volatile unsigned int*)(0x42DE228CUL)) +#define bFM4_GPIO_PCR5_P54 *((volatile unsigned int*)(0x42DE2290UL)) +#define bFM4_GPIO_PCR5_P55 *((volatile unsigned int*)(0x42DE2294UL)) +#define bFM4_GPIO_PCR5_P56 *((volatile unsigned int*)(0x42DE2298UL)) +#define bFM4_GPIO_PCR5_P57 *((volatile unsigned int*)(0x42DE229CUL)) +#define bFM4_GPIO_PCR5_P58 *((volatile unsigned int*)(0x42DE22A0UL)) +#define bFM4_GPIO_PCR5_P59 *((volatile unsigned int*)(0x42DE22A4UL)) +#define bFM4_GPIO_PCR5_P5A *((volatile unsigned int*)(0x42DE22A8UL)) +#define bFM4_GPIO_PCR5_P5B *((volatile unsigned int*)(0x42DE22ACUL)) +#define bFM4_GPIO_PCR6_P60 *((volatile unsigned int*)(0x42DE2300UL)) +#define bFM4_GPIO_PCR6_P61 *((volatile unsigned int*)(0x42DE2304UL)) +#define bFM4_GPIO_PCR6_P62 *((volatile unsigned int*)(0x42DE2308UL)) +#define bFM4_GPIO_PCR6_P63 *((volatile unsigned int*)(0x42DE230CUL)) +#define bFM4_GPIO_PCR6_P64 *((volatile unsigned int*)(0x42DE2310UL)) +#define bFM4_GPIO_PCR6_P65 *((volatile unsigned int*)(0x42DE2314UL)) +#define bFM4_GPIO_PCR6_P66 *((volatile unsigned int*)(0x42DE2318UL)) +#define bFM4_GPIO_PCR6_P67 *((volatile unsigned int*)(0x42DE231CUL)) +#define bFM4_GPIO_PCR6_P68 *((volatile unsigned int*)(0x42DE2320UL)) +#define bFM4_GPIO_PCR7_P70 *((volatile unsigned int*)(0x42DE2380UL)) +#define bFM4_GPIO_PCR7_P71 *((volatile unsigned int*)(0x42DE2384UL)) +#define bFM4_GPIO_PCR7_P72 *((volatile unsigned int*)(0x42DE2388UL)) +#define bFM4_GPIO_PCR7_P73 *((volatile unsigned int*)(0x42DE238CUL)) +#define bFM4_GPIO_PCR7_P74 *((volatile unsigned int*)(0x42DE2390UL)) +#define bFM4_GPIO_PCR8_P80 *((volatile unsigned int*)(0x42DE2400UL)) +#define bFM4_GPIO_PCR8_P81 *((volatile unsigned int*)(0x42DE2404UL)) +#define bFM4_GPIO_PCRE_PE0 *((volatile unsigned int*)(0x42DE2700UL)) +#define bFM4_GPIO_PCRE_PE2 *((volatile unsigned int*)(0x42DE2708UL)) +#define bFM4_GPIO_PCRE_PE3 *((volatile unsigned int*)(0x42DE270CUL)) +#define bFM4_GPIO_DDR0_P00 *((volatile unsigned int*)(0x42DE4000UL)) +#define bFM4_GPIO_DDR0_P01 *((volatile unsigned int*)(0x42DE4004UL)) +#define bFM4_GPIO_DDR0_P02 *((volatile unsigned int*)(0x42DE4008UL)) +#define bFM4_GPIO_DDR0_P03 *((volatile unsigned int*)(0x42DE400CUL)) +#define bFM4_GPIO_DDR0_P04 *((volatile unsigned int*)(0x42DE4010UL)) +#define bFM4_GPIO_DDR0_P05 *((volatile unsigned int*)(0x42DE4014UL)) +#define bFM4_GPIO_DDR0_P06 *((volatile unsigned int*)(0x42DE4018UL)) +#define bFM4_GPIO_DDR0_P07 *((volatile unsigned int*)(0x42DE401CUL)) +#define bFM4_GPIO_DDR0_P08 *((volatile unsigned int*)(0x42DE4020UL)) +#define bFM4_GPIO_DDR0_P09 *((volatile unsigned int*)(0x42DE4024UL)) +#define bFM4_GPIO_DDR0_P0A *((volatile unsigned int*)(0x42DE4028UL)) +#define bFM4_GPIO_DDR0_P0B *((volatile unsigned int*)(0x42DE402CUL)) +#define bFM4_GPIO_DDR0_P0C *((volatile unsigned int*)(0x42DE4030UL)) +#define bFM4_GPIO_DDR0_P0D *((volatile unsigned int*)(0x42DE4034UL)) +#define bFM4_GPIO_DDR0_P0E *((volatile unsigned int*)(0x42DE4038UL)) +#define bFM4_GPIO_DDR0_P0F *((volatile unsigned int*)(0x42DE403CUL)) +#define bFM4_GPIO_DDR1_P10 *((volatile unsigned int*)(0x42DE4080UL)) +#define bFM4_GPIO_DDR1_P11 *((volatile unsigned int*)(0x42DE4084UL)) +#define bFM4_GPIO_DDR1_P12 *((volatile unsigned int*)(0x42DE4088UL)) +#define bFM4_GPIO_DDR1_P13 *((volatile unsigned int*)(0x42DE408CUL)) +#define bFM4_GPIO_DDR1_P14 *((volatile unsigned int*)(0x42DE4090UL)) +#define bFM4_GPIO_DDR1_P15 *((volatile unsigned int*)(0x42DE4094UL)) +#define bFM4_GPIO_DDR1_P16 *((volatile unsigned int*)(0x42DE4098UL)) +#define bFM4_GPIO_DDR1_P17 *((volatile unsigned int*)(0x42DE409CUL)) +#define bFM4_GPIO_DDR1_P18 *((volatile unsigned int*)(0x42DE40A0UL)) +#define bFM4_GPIO_DDR1_P19 *((volatile unsigned int*)(0x42DE40A4UL)) +#define bFM4_GPIO_DDR1_P1A *((volatile unsigned int*)(0x42DE40A8UL)) +#define bFM4_GPIO_DDR1_P1B *((volatile unsigned int*)(0x42DE40ACUL)) +#define bFM4_GPIO_DDR1_P1C *((volatile unsigned int*)(0x42DE40B0UL)) +#define bFM4_GPIO_DDR1_P1D *((volatile unsigned int*)(0x42DE40B4UL)) +#define bFM4_GPIO_DDR1_P1E *((volatile unsigned int*)(0x42DE40B8UL)) +#define bFM4_GPIO_DDR1_P1F *((volatile unsigned int*)(0x42DE40BCUL)) +#define bFM4_GPIO_DDR2_P20 *((volatile unsigned int*)(0x42DE4100UL)) +#define bFM4_GPIO_DDR2_P21 *((volatile unsigned int*)(0x42DE4104UL)) +#define bFM4_GPIO_DDR2_P22 *((volatile unsigned int*)(0x42DE4108UL)) +#define bFM4_GPIO_DDR2_P23 *((volatile unsigned int*)(0x42DE410CUL)) +#define bFM4_GPIO_DDR2_P24 *((volatile unsigned int*)(0x42DE4110UL)) +#define bFM4_GPIO_DDR2_P25 *((volatile unsigned int*)(0x42DE4114UL)) +#define bFM4_GPIO_DDR2_P26 *((volatile unsigned int*)(0x42DE4118UL)) +#define bFM4_GPIO_DDR2_P27 *((volatile unsigned int*)(0x42DE411CUL)) +#define bFM4_GPIO_DDR3_P30 *((volatile unsigned int*)(0x42DE4180UL)) +#define bFM4_GPIO_DDR3_P31 *((volatile unsigned int*)(0x42DE4184UL)) +#define bFM4_GPIO_DDR3_P32 *((volatile unsigned int*)(0x42DE4188UL)) +#define bFM4_GPIO_DDR3_P33 *((volatile unsigned int*)(0x42DE418CUL)) +#define bFM4_GPIO_DDR3_P34 *((volatile unsigned int*)(0x42DE4190UL)) +#define bFM4_GPIO_DDR3_P35 *((volatile unsigned int*)(0x42DE4194UL)) +#define bFM4_GPIO_DDR3_P36 *((volatile unsigned int*)(0x42DE4198UL)) +#define bFM4_GPIO_DDR3_P37 *((volatile unsigned int*)(0x42DE419CUL)) +#define bFM4_GPIO_DDR3_P38 *((volatile unsigned int*)(0x42DE41A0UL)) +#define bFM4_GPIO_DDR3_P39 *((volatile unsigned int*)(0x42DE41A4UL)) +#define bFM4_GPIO_DDR3_P3A *((volatile unsigned int*)(0x42DE41A8UL)) +#define bFM4_GPIO_DDR3_P3B *((volatile unsigned int*)(0x42DE41ACUL)) +#define bFM4_GPIO_DDR3_P3C *((volatile unsigned int*)(0x42DE41B0UL)) +#define bFM4_GPIO_DDR3_P3D *((volatile unsigned int*)(0x42DE41B4UL)) +#define bFM4_GPIO_DDR3_P3E *((volatile unsigned int*)(0x42DE41B8UL)) +#define bFM4_GPIO_DDR3_P3F *((volatile unsigned int*)(0x42DE41BCUL)) +#define bFM4_GPIO_DDR4_P40 *((volatile unsigned int*)(0x42DE4200UL)) +#define bFM4_GPIO_DDR4_P41 *((volatile unsigned int*)(0x42DE4204UL)) +#define bFM4_GPIO_DDR4_P42 *((volatile unsigned int*)(0x42DE4208UL)) +#define bFM4_GPIO_DDR4_P43 *((volatile unsigned int*)(0x42DE420CUL)) +#define bFM4_GPIO_DDR4_P44 *((volatile unsigned int*)(0x42DE4210UL)) +#define bFM4_GPIO_DDR4_P45 *((volatile unsigned int*)(0x42DE4214UL)) +#define bFM4_GPIO_DDR4_P46 *((volatile unsigned int*)(0x42DE4218UL)) +#define bFM4_GPIO_DDR4_P47 *((volatile unsigned int*)(0x42DE421CUL)) +#define bFM4_GPIO_DDR4_P48 *((volatile unsigned int*)(0x42DE4220UL)) +#define bFM4_GPIO_DDR4_P49 *((volatile unsigned int*)(0x42DE4224UL)) +#define bFM4_GPIO_DDR4_P4A *((volatile unsigned int*)(0x42DE4228UL)) +#define bFM4_GPIO_DDR4_P4B *((volatile unsigned int*)(0x42DE422CUL)) +#define bFM4_GPIO_DDR4_P4C *((volatile unsigned int*)(0x42DE4230UL)) +#define bFM4_GPIO_DDR4_P4D *((volatile unsigned int*)(0x42DE4234UL)) +#define bFM4_GPIO_DDR4_P4E *((volatile unsigned int*)(0x42DE4238UL)) +#define bFM4_GPIO_DDR5_P50 *((volatile unsigned int*)(0x42DE4280UL)) +#define bFM4_GPIO_DDR5_P51 *((volatile unsigned int*)(0x42DE4284UL)) +#define bFM4_GPIO_DDR5_P52 *((volatile unsigned int*)(0x42DE4288UL)) +#define bFM4_GPIO_DDR5_P53 *((volatile unsigned int*)(0x42DE428CUL)) +#define bFM4_GPIO_DDR5_P54 *((volatile unsigned int*)(0x42DE4290UL)) +#define bFM4_GPIO_DDR5_P55 *((volatile unsigned int*)(0x42DE4294UL)) +#define bFM4_GPIO_DDR5_P56 *((volatile unsigned int*)(0x42DE4298UL)) +#define bFM4_GPIO_DDR5_P57 *((volatile unsigned int*)(0x42DE429CUL)) +#define bFM4_GPIO_DDR5_P58 *((volatile unsigned int*)(0x42DE42A0UL)) +#define bFM4_GPIO_DDR5_P59 *((volatile unsigned int*)(0x42DE42A4UL)) +#define bFM4_GPIO_DDR5_P5A *((volatile unsigned int*)(0x42DE42A8UL)) +#define bFM4_GPIO_DDR5_P5B *((volatile unsigned int*)(0x42DE42ACUL)) +#define bFM4_GPIO_DDR6_P60 *((volatile unsigned int*)(0x42DE4300UL)) +#define bFM4_GPIO_DDR6_P61 *((volatile unsigned int*)(0x42DE4304UL)) +#define bFM4_GPIO_DDR6_P62 *((volatile unsigned int*)(0x42DE4308UL)) +#define bFM4_GPIO_DDR6_P63 *((volatile unsigned int*)(0x42DE430CUL)) +#define bFM4_GPIO_DDR6_P64 *((volatile unsigned int*)(0x42DE4310UL)) +#define bFM4_GPIO_DDR6_P65 *((volatile unsigned int*)(0x42DE4314UL)) +#define bFM4_GPIO_DDR6_P66 *((volatile unsigned int*)(0x42DE4318UL)) +#define bFM4_GPIO_DDR6_P67 *((volatile unsigned int*)(0x42DE431CUL)) +#define bFM4_GPIO_DDR6_P68 *((volatile unsigned int*)(0x42DE4320UL)) +#define bFM4_GPIO_DDR7_P70 *((volatile unsigned int*)(0x42DE4380UL)) +#define bFM4_GPIO_DDR7_P71 *((volatile unsigned int*)(0x42DE4384UL)) +#define bFM4_GPIO_DDR7_P72 *((volatile unsigned int*)(0x42DE4388UL)) +#define bFM4_GPIO_DDR7_P73 *((volatile unsigned int*)(0x42DE438CUL)) +#define bFM4_GPIO_DDR7_P74 *((volatile unsigned int*)(0x42DE4390UL)) +#define bFM4_GPIO_DDR8_P80 *((volatile unsigned int*)(0x42DE4400UL)) +#define bFM4_GPIO_DDR8_P81 *((volatile unsigned int*)(0x42DE4404UL)) +#define bFM4_GPIO_DDRE_PE0 *((volatile unsigned int*)(0x42DE4700UL)) +#define bFM4_GPIO_DDRE_PE2 *((volatile unsigned int*)(0x42DE4708UL)) +#define bFM4_GPIO_DDRE_PE3 *((volatile unsigned int*)(0x42DE470CUL)) +#define bFM4_GPIO_PDIR0_P00 *((volatile unsigned int*)(0x42DE6000UL)) +#define bFM4_GPIO_PDIR0_P01 *((volatile unsigned int*)(0x42DE6004UL)) +#define bFM4_GPIO_PDIR0_P02 *((volatile unsigned int*)(0x42DE6008UL)) +#define bFM4_GPIO_PDIR0_P03 *((volatile unsigned int*)(0x42DE600CUL)) +#define bFM4_GPIO_PDIR0_P04 *((volatile unsigned int*)(0x42DE6010UL)) +#define bFM4_GPIO_PDIR0_P05 *((volatile unsigned int*)(0x42DE6014UL)) +#define bFM4_GPIO_PDIR0_P06 *((volatile unsigned int*)(0x42DE6018UL)) +#define bFM4_GPIO_PDIR0_P07 *((volatile unsigned int*)(0x42DE601CUL)) +#define bFM4_GPIO_PDIR0_P08 *((volatile unsigned int*)(0x42DE6020UL)) +#define bFM4_GPIO_PDIR0_P09 *((volatile unsigned int*)(0x42DE6024UL)) +#define bFM4_GPIO_PDIR0_P0A *((volatile unsigned int*)(0x42DE6028UL)) +#define bFM4_GPIO_PDIR0_P0B *((volatile unsigned int*)(0x42DE602CUL)) +#define bFM4_GPIO_PDIR0_P0C *((volatile unsigned int*)(0x42DE6030UL)) +#define bFM4_GPIO_PDIR0_P0D *((volatile unsigned int*)(0x42DE6034UL)) +#define bFM4_GPIO_PDIR0_P0E *((volatile unsigned int*)(0x42DE6038UL)) +#define bFM4_GPIO_PDIR0_P0F *((volatile unsigned int*)(0x42DE603CUL)) +#define bFM4_GPIO_PDIR1_P10 *((volatile unsigned int*)(0x42DE6080UL)) +#define bFM4_GPIO_PDIR1_P11 *((volatile unsigned int*)(0x42DE6084UL)) +#define bFM4_GPIO_PDIR1_P12 *((volatile unsigned int*)(0x42DE6088UL)) +#define bFM4_GPIO_PDIR1_P13 *((volatile unsigned int*)(0x42DE608CUL)) +#define bFM4_GPIO_PDIR1_P14 *((volatile unsigned int*)(0x42DE6090UL)) +#define bFM4_GPIO_PDIR1_P15 *((volatile unsigned int*)(0x42DE6094UL)) +#define bFM4_GPIO_PDIR1_P16 *((volatile unsigned int*)(0x42DE6098UL)) +#define bFM4_GPIO_PDIR1_P17 *((volatile unsigned int*)(0x42DE609CUL)) +#define bFM4_GPIO_PDIR1_P18 *((volatile unsigned int*)(0x42DE60A0UL)) +#define bFM4_GPIO_PDIR1_P19 *((volatile unsigned int*)(0x42DE60A4UL)) +#define bFM4_GPIO_PDIR1_P1A *((volatile unsigned int*)(0x42DE60A8UL)) +#define bFM4_GPIO_PDIR1_P1B *((volatile unsigned int*)(0x42DE60ACUL)) +#define bFM4_GPIO_PDIR1_P1C *((volatile unsigned int*)(0x42DE60B0UL)) +#define bFM4_GPIO_PDIR1_P1D *((volatile unsigned int*)(0x42DE60B4UL)) +#define bFM4_GPIO_PDIR1_P1E *((volatile unsigned int*)(0x42DE60B8UL)) +#define bFM4_GPIO_PDIR1_P1F *((volatile unsigned int*)(0x42DE60BCUL)) +#define bFM4_GPIO_PDIR2_P20 *((volatile unsigned int*)(0x42DE6100UL)) +#define bFM4_GPIO_PDIR2_P21 *((volatile unsigned int*)(0x42DE6104UL)) +#define bFM4_GPIO_PDIR2_P22 *((volatile unsigned int*)(0x42DE6108UL)) +#define bFM4_GPIO_PDIR2_P23 *((volatile unsigned int*)(0x42DE610CUL)) +#define bFM4_GPIO_PDIR2_P24 *((volatile unsigned int*)(0x42DE6110UL)) +#define bFM4_GPIO_PDIR2_P25 *((volatile unsigned int*)(0x42DE6114UL)) +#define bFM4_GPIO_PDIR2_P26 *((volatile unsigned int*)(0x42DE6118UL)) +#define bFM4_GPIO_PDIR2_P27 *((volatile unsigned int*)(0x42DE611CUL)) +#define bFM4_GPIO_PDIR3_P30 *((volatile unsigned int*)(0x42DE6180UL)) +#define bFM4_GPIO_PDIR3_P31 *((volatile unsigned int*)(0x42DE6184UL)) +#define bFM4_GPIO_PDIR3_P32 *((volatile unsigned int*)(0x42DE6188UL)) +#define bFM4_GPIO_PDIR3_P33 *((volatile unsigned int*)(0x42DE618CUL)) +#define bFM4_GPIO_PDIR3_P34 *((volatile unsigned int*)(0x42DE6190UL)) +#define bFM4_GPIO_PDIR3_P35 *((volatile unsigned int*)(0x42DE6194UL)) +#define bFM4_GPIO_PDIR3_P36 *((volatile unsigned int*)(0x42DE6198UL)) +#define bFM4_GPIO_PDIR3_P37 *((volatile unsigned int*)(0x42DE619CUL)) +#define bFM4_GPIO_PDIR3_P38 *((volatile unsigned int*)(0x42DE61A0UL)) +#define bFM4_GPIO_PDIR3_P39 *((volatile unsigned int*)(0x42DE61A4UL)) +#define bFM4_GPIO_PDIR3_P3A *((volatile unsigned int*)(0x42DE61A8UL)) +#define bFM4_GPIO_PDIR3_P3B *((volatile unsigned int*)(0x42DE61ACUL)) +#define bFM4_GPIO_PDIR3_P3C *((volatile unsigned int*)(0x42DE61B0UL)) +#define bFM4_GPIO_PDIR3_P3D *((volatile unsigned int*)(0x42DE61B4UL)) +#define bFM4_GPIO_PDIR3_P3E *((volatile unsigned int*)(0x42DE61B8UL)) +#define bFM4_GPIO_PDIR3_P3F *((volatile unsigned int*)(0x42DE61BCUL)) +#define bFM4_GPIO_PDIR4_P40 *((volatile unsigned int*)(0x42DE6200UL)) +#define bFM4_GPIO_PDIR4_P41 *((volatile unsigned int*)(0x42DE6204UL)) +#define bFM4_GPIO_PDIR4_P42 *((volatile unsigned int*)(0x42DE6208UL)) +#define bFM4_GPIO_PDIR4_P43 *((volatile unsigned int*)(0x42DE620CUL)) +#define bFM4_GPIO_PDIR4_P44 *((volatile unsigned int*)(0x42DE6210UL)) +#define bFM4_GPIO_PDIR4_P45 *((volatile unsigned int*)(0x42DE6214UL)) +#define bFM4_GPIO_PDIR4_P46 *((volatile unsigned int*)(0x42DE6218UL)) +#define bFM4_GPIO_PDIR4_P47 *((volatile unsigned int*)(0x42DE621CUL)) +#define bFM4_GPIO_PDIR4_P48 *((volatile unsigned int*)(0x42DE6220UL)) +#define bFM4_GPIO_PDIR4_P49 *((volatile unsigned int*)(0x42DE6224UL)) +#define bFM4_GPIO_PDIR4_P4A *((volatile unsigned int*)(0x42DE6228UL)) +#define bFM4_GPIO_PDIR4_P4B *((volatile unsigned int*)(0x42DE622CUL)) +#define bFM4_GPIO_PDIR4_P4C *((volatile unsigned int*)(0x42DE6230UL)) +#define bFM4_GPIO_PDIR4_P4D *((volatile unsigned int*)(0x42DE6234UL)) +#define bFM4_GPIO_PDIR4_P4E *((volatile unsigned int*)(0x42DE6238UL)) +#define bFM4_GPIO_PDIR5_P50 *((volatile unsigned int*)(0x42DE6280UL)) +#define bFM4_GPIO_PDIR5_P51 *((volatile unsigned int*)(0x42DE6284UL)) +#define bFM4_GPIO_PDIR5_P52 *((volatile unsigned int*)(0x42DE6288UL)) +#define bFM4_GPIO_PDIR5_P53 *((volatile unsigned int*)(0x42DE628CUL)) +#define bFM4_GPIO_PDIR5_P54 *((volatile unsigned int*)(0x42DE6290UL)) +#define bFM4_GPIO_PDIR5_P55 *((volatile unsigned int*)(0x42DE6294UL)) +#define bFM4_GPIO_PDIR5_P56 *((volatile unsigned int*)(0x42DE6298UL)) +#define bFM4_GPIO_PDIR5_P57 *((volatile unsigned int*)(0x42DE629CUL)) +#define bFM4_GPIO_PDIR5_P58 *((volatile unsigned int*)(0x42DE62A0UL)) +#define bFM4_GPIO_PDIR5_P59 *((volatile unsigned int*)(0x42DE62A4UL)) +#define bFM4_GPIO_PDIR5_P5A *((volatile unsigned int*)(0x42DE62A8UL)) +#define bFM4_GPIO_PDIR5_P5B *((volatile unsigned int*)(0x42DE62ACUL)) +#define bFM4_GPIO_PDIR6_P60 *((volatile unsigned int*)(0x42DE6300UL)) +#define bFM4_GPIO_PDIR6_P61 *((volatile unsigned int*)(0x42DE6304UL)) +#define bFM4_GPIO_PDIR6_P62 *((volatile unsigned int*)(0x42DE6308UL)) +#define bFM4_GPIO_PDIR6_P63 *((volatile unsigned int*)(0x42DE630CUL)) +#define bFM4_GPIO_PDIR6_P64 *((volatile unsigned int*)(0x42DE6310UL)) +#define bFM4_GPIO_PDIR6_P65 *((volatile unsigned int*)(0x42DE6314UL)) +#define bFM4_GPIO_PDIR6_P66 *((volatile unsigned int*)(0x42DE6318UL)) +#define bFM4_GPIO_PDIR6_P67 *((volatile unsigned int*)(0x42DE631CUL)) +#define bFM4_GPIO_PDIR6_P68 *((volatile unsigned int*)(0x42DE6320UL)) +#define bFM4_GPIO_PDIR7_P70 *((volatile unsigned int*)(0x42DE6380UL)) +#define bFM4_GPIO_PDIR7_P71 *((volatile unsigned int*)(0x42DE6384UL)) +#define bFM4_GPIO_PDIR7_P72 *((volatile unsigned int*)(0x42DE6388UL)) +#define bFM4_GPIO_PDIR7_P73 *((volatile unsigned int*)(0x42DE638CUL)) +#define bFM4_GPIO_PDIR7_P74 *((volatile unsigned int*)(0x42DE6390UL)) +#define bFM4_GPIO_PDIR8_P80 *((volatile unsigned int*)(0x42DE6400UL)) +#define bFM4_GPIO_PDIR8_P81 *((volatile unsigned int*)(0x42DE6404UL)) +#define bFM4_GPIO_PDIRE_PE0 *((volatile unsigned int*)(0x42DE6700UL)) +#define bFM4_GPIO_PDIRE_PE2 *((volatile unsigned int*)(0x42DE6708UL)) +#define bFM4_GPIO_PDIRE_PE3 *((volatile unsigned int*)(0x42DE670CUL)) +#define bFM4_GPIO_PDOR0_P00 *((volatile unsigned int*)(0x42DE8000UL)) +#define bFM4_GPIO_PDOR0_P01 *((volatile unsigned int*)(0x42DE8004UL)) +#define bFM4_GPIO_PDOR0_P02 *((volatile unsigned int*)(0x42DE8008UL)) +#define bFM4_GPIO_PDOR0_P03 *((volatile unsigned int*)(0x42DE800CUL)) +#define bFM4_GPIO_PDOR0_P04 *((volatile unsigned int*)(0x42DE8010UL)) +#define bFM4_GPIO_PDOR0_P05 *((volatile unsigned int*)(0x42DE8014UL)) +#define bFM4_GPIO_PDOR0_P06 *((volatile unsigned int*)(0x42DE8018UL)) +#define bFM4_GPIO_PDOR0_P07 *((volatile unsigned int*)(0x42DE801CUL)) +#define bFM4_GPIO_PDOR0_P08 *((volatile unsigned int*)(0x42DE8020UL)) +#define bFM4_GPIO_PDOR0_P09 *((volatile unsigned int*)(0x42DE8024UL)) +#define bFM4_GPIO_PDOR0_P0A *((volatile unsigned int*)(0x42DE8028UL)) +#define bFM4_GPIO_PDOR0_P0B *((volatile unsigned int*)(0x42DE802CUL)) +#define bFM4_GPIO_PDOR0_P0C *((volatile unsigned int*)(0x42DE8030UL)) +#define bFM4_GPIO_PDOR0_P0D *((volatile unsigned int*)(0x42DE8034UL)) +#define bFM4_GPIO_PDOR0_P0E *((volatile unsigned int*)(0x42DE8038UL)) +#define bFM4_GPIO_PDOR0_P0F *((volatile unsigned int*)(0x42DE803CUL)) +#define bFM4_GPIO_PDOR1_P10 *((volatile unsigned int*)(0x42DE8080UL)) +#define bFM4_GPIO_PDOR1_P11 *((volatile unsigned int*)(0x42DE8084UL)) +#define bFM4_GPIO_PDOR1_P12 *((volatile unsigned int*)(0x42DE8088UL)) +#define bFM4_GPIO_PDOR1_P13 *((volatile unsigned int*)(0x42DE808CUL)) +#define bFM4_GPIO_PDOR1_P14 *((volatile unsigned int*)(0x42DE8090UL)) +#define bFM4_GPIO_PDOR1_P15 *((volatile unsigned int*)(0x42DE8094UL)) +#define bFM4_GPIO_PDOR1_P16 *((volatile unsigned int*)(0x42DE8098UL)) +#define bFM4_GPIO_PDOR1_P17 *((volatile unsigned int*)(0x42DE809CUL)) +#define bFM4_GPIO_PDOR1_P18 *((volatile unsigned int*)(0x42DE80A0UL)) +#define bFM4_GPIO_PDOR1_P19 *((volatile unsigned int*)(0x42DE80A4UL)) +#define bFM4_GPIO_PDOR1_P1A *((volatile unsigned int*)(0x42DE80A8UL)) +#define bFM4_GPIO_PDOR1_P1B *((volatile unsigned int*)(0x42DE80ACUL)) +#define bFM4_GPIO_PDOR1_P1C *((volatile unsigned int*)(0x42DE80B0UL)) +#define bFM4_GPIO_PDOR1_P1D *((volatile unsigned int*)(0x42DE80B4UL)) +#define bFM4_GPIO_PDOR1_P1E *((volatile unsigned int*)(0x42DE80B8UL)) +#define bFM4_GPIO_PDOR1_P1F *((volatile unsigned int*)(0x42DE80BCUL)) +#define bFM4_GPIO_PDOR2_P20 *((volatile unsigned int*)(0x42DE8100UL)) +#define bFM4_GPIO_PDOR2_P21 *((volatile unsigned int*)(0x42DE8104UL)) +#define bFM4_GPIO_PDOR2_P22 *((volatile unsigned int*)(0x42DE8108UL)) +#define bFM4_GPIO_PDOR2_P23 *((volatile unsigned int*)(0x42DE810CUL)) +#define bFM4_GPIO_PDOR2_P24 *((volatile unsigned int*)(0x42DE8110UL)) +#define bFM4_GPIO_PDOR2_P25 *((volatile unsigned int*)(0x42DE8114UL)) +#define bFM4_GPIO_PDOR2_P26 *((volatile unsigned int*)(0x42DE8118UL)) +#define bFM4_GPIO_PDOR2_P27 *((volatile unsigned int*)(0x42DE811CUL)) +#define bFM4_GPIO_PDOR3_P30 *((volatile unsigned int*)(0x42DE8180UL)) +#define bFM4_GPIO_PDOR3_P31 *((volatile unsigned int*)(0x42DE8184UL)) +#define bFM4_GPIO_PDOR3_P32 *((volatile unsigned int*)(0x42DE8188UL)) +#define bFM4_GPIO_PDOR3_P33 *((volatile unsigned int*)(0x42DE818CUL)) +#define bFM4_GPIO_PDOR3_P34 *((volatile unsigned int*)(0x42DE8190UL)) +#define bFM4_GPIO_PDOR3_P35 *((volatile unsigned int*)(0x42DE8194UL)) +#define bFM4_GPIO_PDOR3_P36 *((volatile unsigned int*)(0x42DE8198UL)) +#define bFM4_GPIO_PDOR3_P37 *((volatile unsigned int*)(0x42DE819CUL)) +#define bFM4_GPIO_PDOR3_P38 *((volatile unsigned int*)(0x42DE81A0UL)) +#define bFM4_GPIO_PDOR3_P39 *((volatile unsigned int*)(0x42DE81A4UL)) +#define bFM4_GPIO_PDOR3_P3A *((volatile unsigned int*)(0x42DE81A8UL)) +#define bFM4_GPIO_PDOR3_P3B *((volatile unsigned int*)(0x42DE81ACUL)) +#define bFM4_GPIO_PDOR3_P3C *((volatile unsigned int*)(0x42DE81B0UL)) +#define bFM4_GPIO_PDOR3_P3D *((volatile unsigned int*)(0x42DE81B4UL)) +#define bFM4_GPIO_PDOR3_P3E *((volatile unsigned int*)(0x42DE81B8UL)) +#define bFM4_GPIO_PDOR3_P3F *((volatile unsigned int*)(0x42DE81BCUL)) +#define bFM4_GPIO_PDOR4_P40 *((volatile unsigned int*)(0x42DE8200UL)) +#define bFM4_GPIO_PDOR4_P41 *((volatile unsigned int*)(0x42DE8204UL)) +#define bFM4_GPIO_PDOR4_P42 *((volatile unsigned int*)(0x42DE8208UL)) +#define bFM4_GPIO_PDOR4_P43 *((volatile unsigned int*)(0x42DE820CUL)) +#define bFM4_GPIO_PDOR4_P44 *((volatile unsigned int*)(0x42DE8210UL)) +#define bFM4_GPIO_PDOR4_P45 *((volatile unsigned int*)(0x42DE8214UL)) +#define bFM4_GPIO_PDOR4_P46 *((volatile unsigned int*)(0x42DE8218UL)) +#define bFM4_GPIO_PDOR4_P47 *((volatile unsigned int*)(0x42DE821CUL)) +#define bFM4_GPIO_PDOR4_P48 *((volatile unsigned int*)(0x42DE8220UL)) +#define bFM4_GPIO_PDOR4_P49 *((volatile unsigned int*)(0x42DE8224UL)) +#define bFM4_GPIO_PDOR4_P4A *((volatile unsigned int*)(0x42DE8228UL)) +#define bFM4_GPIO_PDOR4_P4B *((volatile unsigned int*)(0x42DE822CUL)) +#define bFM4_GPIO_PDOR4_P4C *((volatile unsigned int*)(0x42DE8230UL)) +#define bFM4_GPIO_PDOR4_P4D *((volatile unsigned int*)(0x42DE8234UL)) +#define bFM4_GPIO_PDOR4_P4E *((volatile unsigned int*)(0x42DE8238UL)) +#define bFM4_GPIO_PDOR5_P50 *((volatile unsigned int*)(0x42DE8280UL)) +#define bFM4_GPIO_PDOR5_P51 *((volatile unsigned int*)(0x42DE8284UL)) +#define bFM4_GPIO_PDOR5_P52 *((volatile unsigned int*)(0x42DE8288UL)) +#define bFM4_GPIO_PDOR5_P53 *((volatile unsigned int*)(0x42DE828CUL)) +#define bFM4_GPIO_PDOR5_P54 *((volatile unsigned int*)(0x42DE8290UL)) +#define bFM4_GPIO_PDOR5_P55 *((volatile unsigned int*)(0x42DE8294UL)) +#define bFM4_GPIO_PDOR5_P56 *((volatile unsigned int*)(0x42DE8298UL)) +#define bFM4_GPIO_PDOR5_P57 *((volatile unsigned int*)(0x42DE829CUL)) +#define bFM4_GPIO_PDOR5_P58 *((volatile unsigned int*)(0x42DE82A0UL)) +#define bFM4_GPIO_PDOR5_P59 *((volatile unsigned int*)(0x42DE82A4UL)) +#define bFM4_GPIO_PDOR5_P5A *((volatile unsigned int*)(0x42DE82A8UL)) +#define bFM4_GPIO_PDOR5_P5B *((volatile unsigned int*)(0x42DE82ACUL)) +#define bFM4_GPIO_PDOR6_P60 *((volatile unsigned int*)(0x42DE8300UL)) +#define bFM4_GPIO_PDOR6_P61 *((volatile unsigned int*)(0x42DE8304UL)) +#define bFM4_GPIO_PDOR6_P62 *((volatile unsigned int*)(0x42DE8308UL)) +#define bFM4_GPIO_PDOR6_P63 *((volatile unsigned int*)(0x42DE830CUL)) +#define bFM4_GPIO_PDOR6_P64 *((volatile unsigned int*)(0x42DE8310UL)) +#define bFM4_GPIO_PDOR6_P65 *((volatile unsigned int*)(0x42DE8314UL)) +#define bFM4_GPIO_PDOR6_P66 *((volatile unsigned int*)(0x42DE8318UL)) +#define bFM4_GPIO_PDOR6_P67 *((volatile unsigned int*)(0x42DE831CUL)) +#define bFM4_GPIO_PDOR6_P68 *((volatile unsigned int*)(0x42DE8320UL)) +#define bFM4_GPIO_PDOR7_P70 *((volatile unsigned int*)(0x42DE8380UL)) +#define bFM4_GPIO_PDOR7_P71 *((volatile unsigned int*)(0x42DE8384UL)) +#define bFM4_GPIO_PDOR7_P72 *((volatile unsigned int*)(0x42DE8388UL)) +#define bFM4_GPIO_PDOR7_P73 *((volatile unsigned int*)(0x42DE838CUL)) +#define bFM4_GPIO_PDOR7_P74 *((volatile unsigned int*)(0x42DE8390UL)) +#define bFM4_GPIO_PDOR8_P80 *((volatile unsigned int*)(0x42DE8400UL)) +#define bFM4_GPIO_PDOR8_P81 *((volatile unsigned int*)(0x42DE8404UL)) +#define bFM4_GPIO_PDORE_PE0 *((volatile unsigned int*)(0x42DE8700UL)) +#define bFM4_GPIO_PDORE_PE2 *((volatile unsigned int*)(0x42DE8708UL)) +#define bFM4_GPIO_PDORE_PE3 *((volatile unsigned int*)(0x42DE870CUL)) +#define bFM4_GPIO_ADE_AN00 *((volatile unsigned int*)(0x42DEA000UL)) +#define bFM4_GPIO_ADE_AN01 *((volatile unsigned int*)(0x42DEA004UL)) +#define bFM4_GPIO_ADE_AN02 *((volatile unsigned int*)(0x42DEA008UL)) +#define bFM4_GPIO_ADE_AN03 *((volatile unsigned int*)(0x42DEA00CUL)) +#define bFM4_GPIO_ADE_AN04 *((volatile unsigned int*)(0x42DEA010UL)) +#define bFM4_GPIO_ADE_AN05 *((volatile unsigned int*)(0x42DEA014UL)) +#define bFM4_GPIO_ADE_AN06 *((volatile unsigned int*)(0x42DEA018UL)) +#define bFM4_GPIO_ADE_AN07 *((volatile unsigned int*)(0x42DEA01CUL)) +#define bFM4_GPIO_ADE_AN08 *((volatile unsigned int*)(0x42DEA020UL)) +#define bFM4_GPIO_ADE_AN09 *((volatile unsigned int*)(0x42DEA024UL)) +#define bFM4_GPIO_ADE_AN10 *((volatile unsigned int*)(0x42DEA028UL)) +#define bFM4_GPIO_ADE_AN11 *((volatile unsigned int*)(0x42DEA02CUL)) +#define bFM4_GPIO_ADE_AN12 *((volatile unsigned int*)(0x42DEA030UL)) +#define bFM4_GPIO_ADE_AN13 *((volatile unsigned int*)(0x42DEA034UL)) +#define bFM4_GPIO_ADE_AN14 *((volatile unsigned int*)(0x42DEA038UL)) +#define bFM4_GPIO_ADE_AN15 *((volatile unsigned int*)(0x42DEA03CUL)) +#define bFM4_GPIO_ADE_AN16 *((volatile unsigned int*)(0x42DEA040UL)) +#define bFM4_GPIO_ADE_AN17 *((volatile unsigned int*)(0x42DEA044UL)) +#define bFM4_GPIO_ADE_AN18 *((volatile unsigned int*)(0x42DEA048UL)) +#define bFM4_GPIO_ADE_AN19 *((volatile unsigned int*)(0x42DEA04CUL)) +#define bFM4_GPIO_ADE_AN20 *((volatile unsigned int*)(0x42DEA050UL)) +#define bFM4_GPIO_ADE_AN21 *((volatile unsigned int*)(0x42DEA054UL)) +#define bFM4_GPIO_ADE_AN22 *((volatile unsigned int*)(0x42DEA058UL)) +#define bFM4_GPIO_ADE_AN23 *((volatile unsigned int*)(0x42DEA05CUL)) +#define bFM4_GPIO_ADE_AN24 *((volatile unsigned int*)(0x42DEA060UL)) +#define bFM4_GPIO_ADE_AN25 *((volatile unsigned int*)(0x42DEA064UL)) +#define bFM4_GPIO_ADE_AN26 *((volatile unsigned int*)(0x42DEA068UL)) +#define bFM4_GPIO_ADE_AN27 *((volatile unsigned int*)(0x42DEA06CUL)) +#define bFM4_GPIO_ADE_AN28 *((volatile unsigned int*)(0x42DEA070UL)) +#define bFM4_GPIO_ADE_AN29 *((volatile unsigned int*)(0x42DEA074UL)) +#define bFM4_GPIO_ADE_AN30 *((volatile unsigned int*)(0x42DEA078UL)) +#define bFM4_GPIO_ADE_AN31 *((volatile unsigned int*)(0x42DEA07CUL)) +#define bFM4_GPIO_SPSR_MAINXC0 *((volatile unsigned int*)(0x42DEB008UL)) +#define bFM4_GPIO_SPSR_MAINXC1 *((volatile unsigned int*)(0x42DEB00CUL)) +#define bFM4_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x42DEB010UL)) +#define bFM4_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x42DEB014UL)) +#define bFM4_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x42DEC000UL)) +#define bFM4_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x42DEC004UL)) +#define bFM4_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x42DEC008UL)) +#define bFM4_GPIO_EPFR00_RTCCOE0 *((volatile unsigned int*)(0x42DEC010UL)) +#define bFM4_GPIO_EPFR00_RTCCOE1 *((volatile unsigned int*)(0x42DEC014UL)) +#define bFM4_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x42DEC018UL)) +#define bFM4_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x42DEC01CUL)) +#define bFM4_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x42DEC024UL)) +#define bFM4_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x42DEC034UL)) +#define bFM4_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x42DEC040UL)) +#define bFM4_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x42DEC044UL)) +#define bFM4_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x42DEC060UL)) +#define bFM4_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x42DEC064UL)) +#define bFM4_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x42DEC080UL)) +#define bFM4_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x42DEC084UL)) +#define bFM4_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x42DEC088UL)) +#define bFM4_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x42DEC08CUL)) +#define bFM4_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x42DEC090UL)) +#define bFM4_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x42DEC094UL)) +#define bFM4_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x42DEC098UL)) +#define bFM4_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x42DEC09CUL)) +#define bFM4_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x42DEC0A0UL)) +#define bFM4_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x42DEC0A4UL)) +#define bFM4_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x42DEC0A8UL)) +#define bFM4_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x42DEC0ACUL)) +#define bFM4_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x42DEC0B0UL)) +#define bFM4_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x42DEC0C0UL)) +#define bFM4_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x42DEC0C4UL)) +#define bFM4_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x42DEC0C8UL)) +#define bFM4_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x42DEC0CCUL)) +#define bFM4_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x42DEC0D0UL)) +#define bFM4_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x42DEC0D4UL)) +#define bFM4_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x42DEC0D8UL)) +#define bFM4_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x42DEC0DCUL)) +#define bFM4_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x42DEC0E0UL)) +#define bFM4_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x42DEC0E4UL)) +#define bFM4_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x42DEC0E8UL)) +#define bFM4_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x42DEC0ECUL)) +#define bFM4_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x42DEC0F0UL)) +#define bFM4_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x42DEC0F4UL)) +#define bFM4_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x42DEC0F8UL)) +#define bFM4_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x42DEC0FCUL)) +#define bFM4_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x42DEC100UL)) +#define bFM4_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x42DEC104UL)) +#define bFM4_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x42DEC108UL)) +#define bFM4_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x42DEC10CUL)) +#define bFM4_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x42DEC110UL)) +#define bFM4_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x42DEC114UL)) +#define bFM4_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x42DEC118UL)) +#define bFM4_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x42DEC11CUL)) +#define bFM4_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x42DEC120UL)) +#define bFM4_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x42DEC124UL)) +#define bFM4_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x42DEC128UL)) +#define bFM4_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x42DEC12CUL)) +#define bFM4_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x42DEC130UL)) +#define bFM4_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x42DEC140UL)) +#define bFM4_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x42DEC144UL)) +#define bFM4_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x42DEC148UL)) +#define bFM4_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x42DEC14CUL)) +#define bFM4_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x42DEC150UL)) +#define bFM4_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x42DEC154UL)) +#define bFM4_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x42DEC158UL)) +#define bFM4_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x42DEC15CUL)) +#define bFM4_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x42DEC160UL)) +#define bFM4_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x42DEC164UL)) +#define bFM4_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x42DEC168UL)) +#define bFM4_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x42DEC16CUL)) +#define bFM4_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x42DEC170UL)) +#define bFM4_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x42DEC174UL)) +#define bFM4_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x42DEC178UL)) +#define bFM4_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x42DEC17CUL)) +#define bFM4_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x42DEC180UL)) +#define bFM4_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x42DEC184UL)) +#define bFM4_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x42DEC188UL)) +#define bFM4_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x42DEC18CUL)) +#define bFM4_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x42DEC190UL)) +#define bFM4_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x42DEC194UL)) +#define bFM4_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x42DEC198UL)) +#define bFM4_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x42DEC19CUL)) +#define bFM4_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x42DEC1A0UL)) +#define bFM4_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x42DEC1A4UL)) +#define bFM4_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x42DEC1A8UL)) +#define bFM4_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x42DEC1ACUL)) +#define bFM4_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x42DEC1B0UL)) +#define bFM4_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x42DEC1C0UL)) +#define bFM4_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x42DEC1C4UL)) +#define bFM4_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x42DEC1C8UL)) +#define bFM4_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x42DEC1CCUL)) +#define bFM4_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x42DEC1D0UL)) +#define bFM4_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x42DEC1D4UL)) +#define bFM4_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x42DEC1D8UL)) +#define bFM4_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x42DEC1DCUL)) +#define bFM4_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x42DEC1E0UL)) +#define bFM4_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x42DEC1E4UL)) +#define bFM4_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x42DEC1E8UL)) +#define bFM4_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x42DEC1ECUL)) +#define bFM4_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x42DEC1F0UL)) +#define bFM4_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x42DEC1F4UL)) +#define bFM4_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x42DEC1F8UL)) +#define bFM4_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x42DEC1FCUL)) +#define bFM4_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x42DEC208UL)) +#define bFM4_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x42DEC20CUL)) +#define bFM4_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x42DEC210UL)) +#define bFM4_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x42DEC214UL)) +#define bFM4_GPIO_EPFR04_TIOB0S2 *((volatile unsigned int*)(0x42DEC218UL)) +#define bFM4_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x42DEC220UL)) +#define bFM4_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x42DEC224UL)) +#define bFM4_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x42DEC228UL)) +#define bFM4_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x42DEC22CUL)) +#define bFM4_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x42DEC230UL)) +#define bFM4_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x42DEC234UL)) +#define bFM4_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x42DEC248UL)) +#define bFM4_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x42DEC24CUL)) +#define bFM4_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x42DEC250UL)) +#define bFM4_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x42DEC254UL)) +#define bFM4_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x42DEC260UL)) +#define bFM4_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x42DEC264UL)) +#define bFM4_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x42DEC268UL)) +#define bFM4_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x42DEC26CUL)) +#define bFM4_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x42DEC270UL)) +#define bFM4_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x42DEC274UL)) +#define bFM4_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x42DEC288UL)) +#define bFM4_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x42DEC28CUL)) +#define bFM4_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x42DEC290UL)) +#define bFM4_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x42DEC294UL)) +#define bFM4_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x42DEC2A0UL)) +#define bFM4_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x42DEC2A4UL)) +#define bFM4_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x42DEC2A8UL)) +#define bFM4_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x42DEC2ACUL)) +#define bFM4_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x42DEC2B0UL)) +#define bFM4_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x42DEC2B4UL)) +#define bFM4_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x42DEC2C8UL)) +#define bFM4_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x42DEC2CCUL)) +#define bFM4_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x42DEC2D0UL)) +#define bFM4_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x42DEC2D4UL)) +#define bFM4_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x42DEC2E0UL)) +#define bFM4_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x42DEC2E4UL)) +#define bFM4_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x42DEC2E8UL)) +#define bFM4_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x42DEC2ECUL)) +#define bFM4_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x42DEC2F0UL)) +#define bFM4_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x42DEC2F4UL)) +#define bFM4_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x42DEC300UL)) +#define bFM4_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x42DEC304UL)) +#define bFM4_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x42DEC308UL)) +#define bFM4_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x42DEC30CUL)) +#define bFM4_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x42DEC310UL)) +#define bFM4_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x42DEC314UL)) +#define bFM4_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x42DEC318UL)) +#define bFM4_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x42DEC31CUL)) +#define bFM4_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x42DEC320UL)) +#define bFM4_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x42DEC324UL)) +#define bFM4_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x42DEC328UL)) +#define bFM4_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x42DEC32CUL)) +#define bFM4_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x42DEC330UL)) +#define bFM4_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x42DEC334UL)) +#define bFM4_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x42DEC338UL)) +#define bFM4_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x42DEC33CUL)) +#define bFM4_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x42DEC340UL)) +#define bFM4_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x42DEC344UL)) +#define bFM4_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x42DEC348UL)) +#define bFM4_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x42DEC34CUL)) +#define bFM4_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x42DEC350UL)) +#define bFM4_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x42DEC354UL)) +#define bFM4_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x42DEC358UL)) +#define bFM4_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x42DEC35CUL)) +#define bFM4_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x42DEC360UL)) +#define bFM4_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x42DEC364UL)) +#define bFM4_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x42DEC368UL)) +#define bFM4_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x42DEC36CUL)) +#define bFM4_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x42DEC370UL)) +#define bFM4_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x42DEC374UL)) +#define bFM4_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x42DEC378UL)) +#define bFM4_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x42DEC37CUL)) +#define bFM4_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x42DEC390UL)) +#define bFM4_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x42DEC394UL)) +#define bFM4_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x42DEC398UL)) +#define bFM4_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x42DEC39CUL)) +#define bFM4_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x42DEC3A0UL)) +#define bFM4_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x42DEC3A4UL)) +#define bFM4_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x42DEC3A8UL)) +#define bFM4_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x42DEC3ACUL)) +#define bFM4_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x42DEC3B0UL)) +#define bFM4_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x42DEC3B4UL)) +#define bFM4_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x42DEC3B8UL)) +#define bFM4_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x42DEC3BCUL)) +#define bFM4_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x42DEC3C0UL)) +#define bFM4_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x42DEC3C4UL)) +#define bFM4_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x42DEC3C8UL)) +#define bFM4_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x42DEC3CCUL)) +#define bFM4_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x42DEC3D0UL)) +#define bFM4_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x42DEC3D4UL)) +#define bFM4_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x42DEC3D8UL)) +#define bFM4_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x42DEC3DCUL)) +#define bFM4_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x42DEC3E0UL)) +#define bFM4_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x42DEC3E4UL)) +#define bFM4_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x42DEC3E8UL)) +#define bFM4_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x42DEC3ECUL)) +#define bFM4_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x42DEC400UL)) +#define bFM4_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x42DEC404UL)) +#define bFM4_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x42DEC408UL)) +#define bFM4_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x42DEC40CUL)) +#define bFM4_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x42DEC410UL)) +#define bFM4_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x42DEC414UL)) +#define bFM4_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x42DEC418UL)) +#define bFM4_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x42DEC41CUL)) +#define bFM4_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x42DEC420UL)) +#define bFM4_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x42DEC424UL)) +#define bFM4_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x42DEC428UL)) +#define bFM4_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x42DEC42CUL)) +#define bFM4_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x42DEC430UL)) +#define bFM4_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x42DEC434UL)) +#define bFM4_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x42DEC438UL)) +#define bFM4_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x42DEC43CUL)) +#define bFM4_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x42DEC440UL)) +#define bFM4_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x42DEC444UL)) +#define bFM4_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x42DEC448UL)) +#define bFM4_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x42DEC44CUL)) +#define bFM4_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x42DEC450UL)) +#define bFM4_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x42DEC454UL)) +#define bFM4_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x42DEC458UL)) +#define bFM4_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x42DEC45CUL)) +#define bFM4_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x42DEC460UL)) +#define bFM4_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x42DEC464UL)) +#define bFM4_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x42DEC468UL)) +#define bFM4_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x42DEC46CUL)) +#define bFM4_GPIO_EPFR08_RTS5E0 *((volatile unsigned int*)(0x42DEC470UL)) +#define bFM4_GPIO_EPFR08_RTS5E1 *((volatile unsigned int*)(0x42DEC474UL)) +#define bFM4_GPIO_EPFR08_CTS5S0 *((volatile unsigned int*)(0x42DEC478UL)) +#define bFM4_GPIO_EPFR08_CTS5S1 *((volatile unsigned int*)(0x42DEC47CUL)) +#define bFM4_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x42DEC480UL)) +#define bFM4_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x42DEC484UL)) +#define bFM4_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x42DEC488UL)) +#define bFM4_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x42DEC48CUL)) +#define bFM4_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x42DEC490UL)) +#define bFM4_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x42DEC494UL)) +#define bFM4_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x42DEC498UL)) +#define bFM4_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x42DEC49CUL)) +#define bFM4_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x42DEC4A0UL)) +#define bFM4_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x42DEC4A4UL)) +#define bFM4_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x42DEC4A8UL)) +#define bFM4_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x42DEC4ACUL)) +#define bFM4_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x42DEC4B0UL)) +#define bFM4_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x42DEC4B4UL)) +#define bFM4_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x42DEC4B8UL)) +#define bFM4_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x42DEC4BCUL)) +#define bFM4_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x42DEC4C0UL)) +#define bFM4_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x42DEC4C4UL)) +#define bFM4_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x42DEC4C8UL)) +#define bFM4_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x42DEC4CCUL)) +#define bFM4_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x42DEC4D0UL)) +#define bFM4_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x42DEC4D4UL)) +#define bFM4_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x42DEC4D8UL)) +#define bFM4_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x42DEC4DCUL)) +#define bFM4_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x42DEC4E0UL)) +#define bFM4_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x42DEC4E4UL)) +#define bFM4_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x42DEC4E8UL)) +#define bFM4_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x42DEC4ECUL)) +#define bFM4_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x42DEC4F0UL)) +#define bFM4_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x42DEC4F4UL)) +#define bFM4_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x42DEC4F8UL)) +#define bFM4_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x42DEC4FCUL)) +#define bFM4_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x42DEC500UL)) +#define bFM4_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x42DEC504UL)) +#define bFM4_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x42DEC508UL)) +#define bFM4_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x42DEC50CUL)) +#define bFM4_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x42DEC510UL)) +#define bFM4_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x42DEC514UL)) +#define bFM4_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x42DEC518UL)) +#define bFM4_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x42DEC51CUL)) +#define bFM4_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x42DEC520UL)) +#define bFM4_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x42DEC524UL)) +#define bFM4_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x42DEC528UL)) +#define bFM4_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x42DEC52CUL)) +#define bFM4_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x42DEC530UL)) +#define bFM4_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x42DEC534UL)) +#define bFM4_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x42DEC538UL)) +#define bFM4_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x42DEC53CUL)) +#define bFM4_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x42DEC540UL)) +#define bFM4_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x42DEC544UL)) +#define bFM4_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x42DEC548UL)) +#define bFM4_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x42DEC54CUL)) +#define bFM4_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x42DEC550UL)) +#define bFM4_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x42DEC554UL)) +#define bFM4_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x42DEC558UL)) +#define bFM4_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x42DEC55CUL)) +#define bFM4_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x42DEC560UL)) +#define bFM4_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x42DEC564UL)) +#define bFM4_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x42DEC568UL)) +#define bFM4_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x42DEC56CUL)) +#define bFM4_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x42DEC570UL)) +#define bFM4_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x42DEC574UL)) +#define bFM4_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x42DEC578UL)) +#define bFM4_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x42DEC57CUL)) +#define bFM4_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x42DEC580UL)) +#define bFM4_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x42DEC584UL)) +#define bFM4_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x42DEC588UL)) +#define bFM4_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x42DEC58CUL)) +#define bFM4_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x42DEC590UL)) +#define bFM4_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x42DEC594UL)) +#define bFM4_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x42DEC598UL)) +#define bFM4_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x42DEC59CUL)) +#define bFM4_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x42DEC5A0UL)) +#define bFM4_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x42DEC5A4UL)) +#define bFM4_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x42DEC5A8UL)) +#define bFM4_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x42DEC5ACUL)) +#define bFM4_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x42DEC5B0UL)) +#define bFM4_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x42DEC5B4UL)) +#define bFM4_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x42DEC5B8UL)) +#define bFM4_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x42DEC5BCUL)) +#define bFM4_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x42DEC5C0UL)) +#define bFM4_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x42DEC5C4UL)) +#define bFM4_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x42DEC5C8UL)) +#define bFM4_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x42DEC5CCUL)) +#define bFM4_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x42DEC5D0UL)) +#define bFM4_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x42DEC5D4UL)) +#define bFM4_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x42DEC5D8UL)) +#define bFM4_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x42DEC5DCUL)) +#define bFM4_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x42DEC5E0UL)) +#define bFM4_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x42DEC5E4UL)) +#define bFM4_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x42DEC608UL)) +#define bFM4_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x42DEC60CUL)) +#define bFM4_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x42DEC610UL)) +#define bFM4_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x42DEC614UL)) +#define bFM4_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x42DEC620UL)) +#define bFM4_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x42DEC624UL)) +#define bFM4_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x42DEC628UL)) +#define bFM4_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x42DEC62CUL)) +#define bFM4_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x42DEC630UL)) +#define bFM4_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x42DEC634UL)) +#define bFM4_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x42DEC648UL)) +#define bFM4_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x42DEC64CUL)) +#define bFM4_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x42DEC650UL)) +#define bFM4_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x42DEC654UL)) +#define bFM4_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x42DEC660UL)) +#define bFM4_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x42DEC664UL)) +#define bFM4_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x42DEC668UL)) +#define bFM4_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x42DEC66CUL)) +#define bFM4_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x42DEC670UL)) +#define bFM4_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x42DEC674UL)) +#define bFM4_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x42DEC688UL)) +#define bFM4_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x42DEC68CUL)) +#define bFM4_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x42DEC690UL)) +#define bFM4_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x42DEC694UL)) +#define bFM4_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x42DEC6A0UL)) +#define bFM4_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x42DEC6A4UL)) +#define bFM4_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x42DEC6A8UL)) +#define bFM4_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x42DEC6ACUL)) +#define bFM4_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x42DEC6B0UL)) +#define bFM4_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x42DEC6B4UL)) +#define bFM4_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x42DEC6C8UL)) +#define bFM4_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x42DEC6CCUL)) +#define bFM4_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x42DEC6D0UL)) +#define bFM4_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x42DEC6D4UL)) +#define bFM4_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x42DEC6E0UL)) +#define bFM4_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x42DEC6E4UL)) +#define bFM4_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x42DEC6E8UL)) +#define bFM4_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x42DEC6ECUL)) +#define bFM4_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x42DEC6F0UL)) +#define bFM4_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x42DEC6F4UL)) +#define bFM4_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x42DEC700UL)) +#define bFM4_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x42DEC704UL)) +#define bFM4_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x42DEC708UL)) +#define bFM4_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x42DEC70CUL)) +#define bFM4_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x42DEC710UL)) +#define bFM4_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x42DEC714UL)) +#define bFM4_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x42DEC748UL)) +#define bFM4_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x42DEC74CUL)) +#define bFM4_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x42DEC750UL)) +#define bFM4_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x42DEC754UL)) +#define bFM4_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x42DEC758UL)) +#define bFM4_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x42DEC75CUL)) +#define bFM4_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x42DEC760UL)) +#define bFM4_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x42DEC764UL)) +#define bFM4_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x42DEC768UL)) +#define bFM4_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x42DEC76CUL)) +#define bFM4_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x42DEC770UL)) +#define bFM4_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x42DEC774UL)) +#define bFM4_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x42DEC780UL)) +#define bFM4_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x42DEC784UL)) +#define bFM4_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x42DEC788UL)) +#define bFM4_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x42DEC78CUL)) +#define bFM4_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x42DEC790UL)) +#define bFM4_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x42DEC794UL)) +#define bFM4_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x42DEC798UL)) +#define bFM4_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x42DEC79CUL)) +#define bFM4_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x42DEC7A0UL)) +#define bFM4_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x42DEC7A4UL)) +#define bFM4_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x42DEC7A8UL)) +#define bFM4_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x42DEC7ACUL)) +#define bFM4_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x42DEC7B0UL)) +#define bFM4_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x42DEC7B4UL)) +#define bFM4_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x42DEC7B8UL)) +#define bFM4_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x42DEC7BCUL)) +#define bFM4_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x42DEC7C0UL)) +#define bFM4_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x42DEC7C4UL)) +#define bFM4_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x42DEC7C8UL)) +#define bFM4_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x42DEC7CCUL)) +#define bFM4_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x42DEC7D0UL)) +#define bFM4_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x42DEC7D4UL)) +#define bFM4_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x42DEC7D8UL)) +#define bFM4_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x42DEC7DCUL)) +#define bFM4_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x42DEC7E0UL)) +#define bFM4_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x42DEC7E4UL)) +#define bFM4_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x42DEC7E8UL)) +#define bFM4_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x42DEC7ECUL)) +#define bFM4_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x42DEC7F0UL)) +#define bFM4_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x42DEC7F4UL)) +#define bFM4_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x42DEC7F8UL)) +#define bFM4_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x42DEC7FCUL)) +#define bFM4_GPIO_EPFR16_SCS6B0 *((volatile unsigned int*)(0x42DEC800UL)) +#define bFM4_GPIO_EPFR16_SCS6B1 *((volatile unsigned int*)(0x42DEC804UL)) +#define bFM4_GPIO_EPFR16_SCS7B0 *((volatile unsigned int*)(0x42DEC808UL)) +#define bFM4_GPIO_EPFR16_SCS7B1 *((volatile unsigned int*)(0x42DEC80CUL)) +#define bFM4_GPIO_EPFR16_SIN8S0 *((volatile unsigned int*)(0x42DEC810UL)) +#define bFM4_GPIO_EPFR16_SIN8S1 *((volatile unsigned int*)(0x42DEC814UL)) +#define bFM4_GPIO_EPFR16_SOT8B0 *((volatile unsigned int*)(0x42DEC818UL)) +#define bFM4_GPIO_EPFR16_SOT8B1 *((volatile unsigned int*)(0x42DEC81CUL)) +#define bFM4_GPIO_EPFR16_SCK8B0 *((volatile unsigned int*)(0x42DEC820UL)) +#define bFM4_GPIO_EPFR16_SCK8B1 *((volatile unsigned int*)(0x42DEC824UL)) +#define bFM4_GPIO_EPFR16_SIN9S0 *((volatile unsigned int*)(0x42DEC828UL)) +#define bFM4_GPIO_EPFR16_SIN9S1 *((volatile unsigned int*)(0x42DEC82CUL)) +#define bFM4_GPIO_EPFR16_SOT9B0 *((volatile unsigned int*)(0x42DEC830UL)) +#define bFM4_GPIO_EPFR16_SOT9B1 *((volatile unsigned int*)(0x42DEC834UL)) +#define bFM4_GPIO_EPFR16_SCK9B0 *((volatile unsigned int*)(0x42DEC838UL)) +#define bFM4_GPIO_EPFR16_SCK9B1 *((volatile unsigned int*)(0x42DEC83CUL)) +#define bFM4_GPIO_EPFR16_SIN10S0 *((volatile unsigned int*)(0x42DEC840UL)) +#define bFM4_GPIO_EPFR16_SIN10S1 *((volatile unsigned int*)(0x42DEC844UL)) +#define bFM4_GPIO_EPFR16_SOT10B0 *((volatile unsigned int*)(0x42DEC848UL)) +#define bFM4_GPIO_EPFR16_SOT10B1 *((volatile unsigned int*)(0x42DEC84CUL)) +#define bFM4_GPIO_EPFR16_SCK10B0 *((volatile unsigned int*)(0x42DEC850UL)) +#define bFM4_GPIO_EPFR16_SCK10B1 *((volatile unsigned int*)(0x42DEC854UL)) +#define bFM4_GPIO_EPFR16_SIN11S0 *((volatile unsigned int*)(0x42DEC858UL)) +#define bFM4_GPIO_EPFR16_SIN11S1 *((volatile unsigned int*)(0x42DEC85CUL)) +#define bFM4_GPIO_EPFR16_SOT11B0 *((volatile unsigned int*)(0x42DEC860UL)) +#define bFM4_GPIO_EPFR16_SOT11B1 *((volatile unsigned int*)(0x42DEC864UL)) +#define bFM4_GPIO_EPFR16_SCK11B0 *((volatile unsigned int*)(0x42DEC868UL)) +#define bFM4_GPIO_EPFR16_SCK11B1 *((volatile unsigned int*)(0x42DEC86CUL)) +#define bFM4_GPIO_EPFR16_SFMPAC *((volatile unsigned int*)(0x42DEC870UL)) +#define bFM4_GPIO_EPFR16_SFMPBC *((volatile unsigned int*)(0x42DEC874UL)) +#define bFM4_GPIO_EPFR17_SIN12S0 *((volatile unsigned int*)(0x42DEC890UL)) +#define bFM4_GPIO_EPFR17_SIN12S1 *((volatile unsigned int*)(0x42DEC894UL)) +#define bFM4_GPIO_EPFR17_SOT12B0 *((volatile unsigned int*)(0x42DEC898UL)) +#define bFM4_GPIO_EPFR17_SOT12B1 *((volatile unsigned int*)(0x42DEC89CUL)) +#define bFM4_GPIO_EPFR17_SCK12B0 *((volatile unsigned int*)(0x42DEC8A0UL)) +#define bFM4_GPIO_EPFR17_SCK12B1 *((volatile unsigned int*)(0x42DEC8A4UL)) +#define bFM4_GPIO_EPFR17_SIN13S0 *((volatile unsigned int*)(0x42DEC8A8UL)) +#define bFM4_GPIO_EPFR17_SIN13S1 *((volatile unsigned int*)(0x42DEC8ACUL)) +#define bFM4_GPIO_EPFR17_SOT13B0 *((volatile unsigned int*)(0x42DEC8B0UL)) +#define bFM4_GPIO_EPFR17_SOT13B1 *((volatile unsigned int*)(0x42DEC8B4UL)) +#define bFM4_GPIO_EPFR17_SCK13B0 *((volatile unsigned int*)(0x42DEC8B8UL)) +#define bFM4_GPIO_EPFR17_SCK13B1 *((volatile unsigned int*)(0x42DEC8BCUL)) +#define bFM4_GPIO_EPFR17_SIN14S0 *((volatile unsigned int*)(0x42DEC8C0UL)) +#define bFM4_GPIO_EPFR17_SIN14S1 *((volatile unsigned int*)(0x42DEC8C4UL)) +#define bFM4_GPIO_EPFR17_SOT14B0 *((volatile unsigned int*)(0x42DEC8C8UL)) +#define bFM4_GPIO_EPFR17_SOT14B1 *((volatile unsigned int*)(0x42DEC8CCUL)) +#define bFM4_GPIO_EPFR17_SCK14B0 *((volatile unsigned int*)(0x42DEC8D0UL)) +#define bFM4_GPIO_EPFR17_SCK14B1 *((volatile unsigned int*)(0x42DEC8D4UL)) +#define bFM4_GPIO_EPFR17_SIN15S0 *((volatile unsigned int*)(0x42DEC8D8UL)) +#define bFM4_GPIO_EPFR17_SIN15S1 *((volatile unsigned int*)(0x42DEC8DCUL)) +#define bFM4_GPIO_EPFR17_SOT15B0 *((volatile unsigned int*)(0x42DEC8E0UL)) +#define bFM4_GPIO_EPFR17_SOT15B1 *((volatile unsigned int*)(0x42DEC8E4UL)) +#define bFM4_GPIO_EPFR17_SCK15B0 *((volatile unsigned int*)(0x42DEC8E8UL)) +#define bFM4_GPIO_EPFR17_SCK15B1 *((volatile unsigned int*)(0x42DEC8ECUL)) +#define bFM4_GPIO_EPFR18_QAIN3S0 *((volatile unsigned int*)(0x42DEC910UL)) +#define bFM4_GPIO_EPFR18_QAIN3S1 *((volatile unsigned int*)(0x42DEC914UL)) +#define bFM4_GPIO_EPFR18_QBIN3S0 *((volatile unsigned int*)(0x42DEC918UL)) +#define bFM4_GPIO_EPFR18_QBIN3S1 *((volatile unsigned int*)(0x42DEC91CUL)) +#define bFM4_GPIO_EPFR18_QZIN3S0 *((volatile unsigned int*)(0x42DEC920UL)) +#define bFM4_GPIO_EPFR18_QZIN3S1 *((volatile unsigned int*)(0x42DEC924UL)) +#define bFM4_GPIO_EPFR18_SDCLKE0 *((volatile unsigned int*)(0x42DEC938UL)) +#define bFM4_GPIO_EPFR18_SDCLKE1 *((volatile unsigned int*)(0x42DEC93CUL)) +#define bFM4_GPIO_EPFR18_SDCMDB0 *((volatile unsigned int*)(0x42DEC940UL)) +#define bFM4_GPIO_EPFR18_SDCMDB1 *((volatile unsigned int*)(0x42DEC944UL)) +#define bFM4_GPIO_EPFR18_SDDATA0B0 *((volatile unsigned int*)(0x42DEC948UL)) +#define bFM4_GPIO_EPFR18_SDDATA0B1 *((volatile unsigned int*)(0x42DEC94CUL)) +#define bFM4_GPIO_EPFR18_SDDATA1B0 *((volatile unsigned int*)(0x42DEC950UL)) +#define bFM4_GPIO_EPFR18_SDDATA1B1 *((volatile unsigned int*)(0x42DEC954UL)) +#define bFM4_GPIO_EPFR18_SDDATA2B0 *((volatile unsigned int*)(0x42DEC958UL)) +#define bFM4_GPIO_EPFR18_SDDATA2B1 *((volatile unsigned int*)(0x42DEC95CUL)) +#define bFM4_GPIO_EPFR18_SDDATA3B0 *((volatile unsigned int*)(0x42DEC960UL)) +#define bFM4_GPIO_EPFR18_SDDATA3B1 *((volatile unsigned int*)(0x42DEC964UL)) +#define bFM4_GPIO_EPFR18_SDCDS0 *((volatile unsigned int*)(0x42DEC968UL)) +#define bFM4_GPIO_EPFR18_SDCDS1 *((volatile unsigned int*)(0x42DEC96CUL)) +#define bFM4_GPIO_EPFR18_SDWPS0 *((volatile unsigned int*)(0x42DEC970UL)) +#define bFM4_GPIO_EPFR18_SDWPS1 *((volatile unsigned int*)(0x42DEC974UL)) +#define bFM4_GPIO_EPFR20_UESMCKE *((volatile unsigned int*)(0x42DECA00UL)) +#define bFM4_GPIO_EPFR20_UESMCEE *((volatile unsigned int*)(0x42DECA04UL)) +#define bFM4_GPIO_EPFR20_UERASE *((volatile unsigned int*)(0x42DECA08UL)) +#define bFM4_GPIO_EPFR20_UECASE *((volatile unsigned int*)(0x42DECA0CUL)) +#define bFM4_GPIO_EPFR20_UEDWEXE *((volatile unsigned int*)(0x42DECA10UL)) +#define bFM4_GPIO_EPFR20_UECSXE *((volatile unsigned int*)(0x42DECA14UL)) +#define bFM4_GPIO_EPFR20_UEDQM2E *((volatile unsigned int*)(0x42DECA18UL)) +#define bFM4_GPIO_EPFR20_UEDQM3E *((volatile unsigned int*)(0x42DECA1CUL)) +#define bFM4_GPIO_EPFR20_UEDTHHB *((volatile unsigned int*)(0x42DECA20UL)) +#define bFM4_GPIO_EPFR20_UED16B *((volatile unsigned int*)(0x42DECA24UL)) +#define bFM4_GPIO_EPFR20_UED17B *((volatile unsigned int*)(0x42DECA28UL)) +#define bFM4_GPIO_EPFR20_UED18B *((volatile unsigned int*)(0x42DECA2CUL)) +#define bFM4_GPIO_EPFR20_UED19B *((volatile unsigned int*)(0x42DECA30UL)) +#define bFM4_GPIO_EPFR20_UED20B *((volatile unsigned int*)(0x42DECA34UL)) +#define bFM4_GPIO_EPFR20_UED21B *((volatile unsigned int*)(0x42DECA38UL)) +#define bFM4_GPIO_EPFR20_UED22B *((volatile unsigned int*)(0x42DECA3CUL)) +#define bFM4_GPIO_EPFR20_UED23B *((volatile unsigned int*)(0x42DECA40UL)) +#define bFM4_GPIO_EPFR20_UED24B *((volatile unsigned int*)(0x42DECA44UL)) +#define bFM4_GPIO_EPFR20_UED25B *((volatile unsigned int*)(0x42DECA48UL)) +#define bFM4_GPIO_EPFR20_UED26B *((volatile unsigned int*)(0x42DECA4CUL)) +#define bFM4_GPIO_EPFR20_UED27B *((volatile unsigned int*)(0x42DECA50UL)) +#define bFM4_GPIO_EPFR20_UED28B *((volatile unsigned int*)(0x42DECA54UL)) +#define bFM4_GPIO_EPFR20_UED29B *((volatile unsigned int*)(0x42DECA58UL)) +#define bFM4_GPIO_EPFR20_UED30B *((volatile unsigned int*)(0x42DECA5CUL)) +#define bFM4_GPIO_EPFR20_UED31B *((volatile unsigned int*)(0x42DECA60UL)) +#define bFM4_GPIO_PZR0_P00 *((volatile unsigned int*)(0x42DEE000UL)) +#define bFM4_GPIO_PZR0_P01 *((volatile unsigned int*)(0x42DEE004UL)) +#define bFM4_GPIO_PZR0_P02 *((volatile unsigned int*)(0x42DEE008UL)) +#define bFM4_GPIO_PZR0_P03 *((volatile unsigned int*)(0x42DEE00CUL)) +#define bFM4_GPIO_PZR0_P04 *((volatile unsigned int*)(0x42DEE010UL)) +#define bFM4_GPIO_PZR0_P05 *((volatile unsigned int*)(0x42DEE014UL)) +#define bFM4_GPIO_PZR0_P06 *((volatile unsigned int*)(0x42DEE018UL)) +#define bFM4_GPIO_PZR0_P07 *((volatile unsigned int*)(0x42DEE01CUL)) +#define bFM4_GPIO_PZR0_P08 *((volatile unsigned int*)(0x42DEE020UL)) +#define bFM4_GPIO_PZR0_P09 *((volatile unsigned int*)(0x42DEE024UL)) +#define bFM4_GPIO_PZR0_P0A *((volatile unsigned int*)(0x42DEE028UL)) +#define bFM4_GPIO_PZR0_P0B *((volatile unsigned int*)(0x42DEE02CUL)) +#define bFM4_GPIO_PZR0_P0C *((volatile unsigned int*)(0x42DEE030UL)) +#define bFM4_GPIO_PZR0_P0D *((volatile unsigned int*)(0x42DEE034UL)) +#define bFM4_GPIO_PZR0_P0E *((volatile unsigned int*)(0x42DEE038UL)) +#define bFM4_GPIO_PZR0_P0F *((volatile unsigned int*)(0x42DEE03CUL)) +#define bFM4_GPIO_PZR1_P10 *((volatile unsigned int*)(0x42DEE080UL)) +#define bFM4_GPIO_PZR1_P11 *((volatile unsigned int*)(0x42DEE084UL)) +#define bFM4_GPIO_PZR1_P12 *((volatile unsigned int*)(0x42DEE088UL)) +#define bFM4_GPIO_PZR1_P13 *((volatile unsigned int*)(0x42DEE08CUL)) +#define bFM4_GPIO_PZR1_P14 *((volatile unsigned int*)(0x42DEE090UL)) +#define bFM4_GPIO_PZR1_P15 *((volatile unsigned int*)(0x42DEE094UL)) +#define bFM4_GPIO_PZR1_P16 *((volatile unsigned int*)(0x42DEE098UL)) +#define bFM4_GPIO_PZR1_P17 *((volatile unsigned int*)(0x42DEE09CUL)) +#define bFM4_GPIO_PZR1_P18 *((volatile unsigned int*)(0x42DEE0A0UL)) +#define bFM4_GPIO_PZR1_P19 *((volatile unsigned int*)(0x42DEE0A4UL)) +#define bFM4_GPIO_PZR1_P1A *((volatile unsigned int*)(0x42DEE0A8UL)) +#define bFM4_GPIO_PZR1_P1B *((volatile unsigned int*)(0x42DEE0ACUL)) +#define bFM4_GPIO_PZR1_P1C *((volatile unsigned int*)(0x42DEE0B0UL)) +#define bFM4_GPIO_PZR1_P1D *((volatile unsigned int*)(0x42DEE0B4UL)) +#define bFM4_GPIO_PZR1_P1E *((volatile unsigned int*)(0x42DEE0B8UL)) +#define bFM4_GPIO_PZR1_P1F *((volatile unsigned int*)(0x42DEE0BCUL)) +#define bFM4_GPIO_PZR2_P20 *((volatile unsigned int*)(0x42DEE100UL)) +#define bFM4_GPIO_PZR2_P21 *((volatile unsigned int*)(0x42DEE104UL)) +#define bFM4_GPIO_PZR2_P22 *((volatile unsigned int*)(0x42DEE108UL)) +#define bFM4_GPIO_PZR2_P23 *((volatile unsigned int*)(0x42DEE10CUL)) +#define bFM4_GPIO_PZR2_P24 *((volatile unsigned int*)(0x42DEE110UL)) +#define bFM4_GPIO_PZR2_P25 *((volatile unsigned int*)(0x42DEE114UL)) +#define bFM4_GPIO_PZR2_P26 *((volatile unsigned int*)(0x42DEE118UL)) +#define bFM4_GPIO_PZR2_P27 *((volatile unsigned int*)(0x42DEE11CUL)) +#define bFM4_GPIO_PZR3_P30 *((volatile unsigned int*)(0x42DEE180UL)) +#define bFM4_GPIO_PZR3_P31 *((volatile unsigned int*)(0x42DEE184UL)) +#define bFM4_GPIO_PZR3_P32 *((volatile unsigned int*)(0x42DEE188UL)) +#define bFM4_GPIO_PZR3_P33 *((volatile unsigned int*)(0x42DEE18CUL)) +#define bFM4_GPIO_PZR3_P34 *((volatile unsigned int*)(0x42DEE190UL)) +#define bFM4_GPIO_PZR3_P35 *((volatile unsigned int*)(0x42DEE194UL)) +#define bFM4_GPIO_PZR3_P36 *((volatile unsigned int*)(0x42DEE198UL)) +#define bFM4_GPIO_PZR3_P37 *((volatile unsigned int*)(0x42DEE19CUL)) +#define bFM4_GPIO_PZR3_P38 *((volatile unsigned int*)(0x42DEE1A0UL)) +#define bFM4_GPIO_PZR3_P39 *((volatile unsigned int*)(0x42DEE1A4UL)) +#define bFM4_GPIO_PZR3_P3A *((volatile unsigned int*)(0x42DEE1A8UL)) +#define bFM4_GPIO_PZR3_P3B *((volatile unsigned int*)(0x42DEE1ACUL)) +#define bFM4_GPIO_PZR3_P3C *((volatile unsigned int*)(0x42DEE1B0UL)) +#define bFM4_GPIO_PZR3_P3D *((volatile unsigned int*)(0x42DEE1B4UL)) +#define bFM4_GPIO_PZR3_P3E *((volatile unsigned int*)(0x42DEE1B8UL)) +#define bFM4_GPIO_PZR3_P3F *((volatile unsigned int*)(0x42DEE1BCUL)) +#define bFM4_GPIO_PZR4_P40 *((volatile unsigned int*)(0x42DEE200UL)) +#define bFM4_GPIO_PZR4_P41 *((volatile unsigned int*)(0x42DEE204UL)) +#define bFM4_GPIO_PZR4_P42 *((volatile unsigned int*)(0x42DEE208UL)) +#define bFM4_GPIO_PZR4_P43 *((volatile unsigned int*)(0x42DEE20CUL)) +#define bFM4_GPIO_PZR4_P44 *((volatile unsigned int*)(0x42DEE210UL)) +#define bFM4_GPIO_PZR4_P45 *((volatile unsigned int*)(0x42DEE214UL)) +#define bFM4_GPIO_PZR4_P46 *((volatile unsigned int*)(0x42DEE218UL)) +#define bFM4_GPIO_PZR4_P47 *((volatile unsigned int*)(0x42DEE21CUL)) +#define bFM4_GPIO_PZR4_P48 *((volatile unsigned int*)(0x42DEE220UL)) +#define bFM4_GPIO_PZR4_P49 *((volatile unsigned int*)(0x42DEE224UL)) +#define bFM4_GPIO_PZR4_P4A *((volatile unsigned int*)(0x42DEE228UL)) +#define bFM4_GPIO_PZR4_P4B *((volatile unsigned int*)(0x42DEE22CUL)) +#define bFM4_GPIO_PZR4_P4C *((volatile unsigned int*)(0x42DEE230UL)) +#define bFM4_GPIO_PZR4_P4D *((volatile unsigned int*)(0x42DEE234UL)) +#define bFM4_GPIO_PZR4_P4E *((volatile unsigned int*)(0x42DEE238UL)) +#define bFM4_GPIO_PZR5_P50 *((volatile unsigned int*)(0x42DEE280UL)) +#define bFM4_GPIO_PZR5_P51 *((volatile unsigned int*)(0x42DEE284UL)) +#define bFM4_GPIO_PZR5_P52 *((volatile unsigned int*)(0x42DEE288UL)) +#define bFM4_GPIO_PZR5_P53 *((volatile unsigned int*)(0x42DEE28CUL)) +#define bFM4_GPIO_PZR5_P54 *((volatile unsigned int*)(0x42DEE290UL)) +#define bFM4_GPIO_PZR5_P55 *((volatile unsigned int*)(0x42DEE294UL)) +#define bFM4_GPIO_PZR5_P56 *((volatile unsigned int*)(0x42DEE298UL)) +#define bFM4_GPIO_PZR5_P57 *((volatile unsigned int*)(0x42DEE29CUL)) +#define bFM4_GPIO_PZR5_P58 *((volatile unsigned int*)(0x42DEE2A0UL)) +#define bFM4_GPIO_PZR5_P59 *((volatile unsigned int*)(0x42DEE2A4UL)) +#define bFM4_GPIO_PZR5_P5A *((volatile unsigned int*)(0x42DEE2A8UL)) +#define bFM4_GPIO_PZR5_P5B *((volatile unsigned int*)(0x42DEE2ACUL)) +#define bFM4_GPIO_PZR6_P60 *((volatile unsigned int*)(0x42DEE300UL)) +#define bFM4_GPIO_PZR6_P61 *((volatile unsigned int*)(0x42DEE304UL)) +#define bFM4_GPIO_PZR6_P62 *((volatile unsigned int*)(0x42DEE308UL)) +#define bFM4_GPIO_PZR6_P63 *((volatile unsigned int*)(0x42DEE30CUL)) +#define bFM4_GPIO_PZR6_P64 *((volatile unsigned int*)(0x42DEE310UL)) +#define bFM4_GPIO_PZR6_P65 *((volatile unsigned int*)(0x42DEE314UL)) +#define bFM4_GPIO_PZR6_P66 *((volatile unsigned int*)(0x42DEE318UL)) +#define bFM4_GPIO_PZR6_P67 *((volatile unsigned int*)(0x42DEE31CUL)) +#define bFM4_GPIO_PZR6_P68 *((volatile unsigned int*)(0x42DEE320UL)) +#define bFM4_GPIO_PZR7_P70 *((volatile unsigned int*)(0x42DEE380UL)) +#define bFM4_GPIO_PZR7_P71 *((volatile unsigned int*)(0x42DEE384UL)) +#define bFM4_GPIO_PZR7_P72 *((volatile unsigned int*)(0x42DEE388UL)) +#define bFM4_GPIO_PZR7_P73 *((volatile unsigned int*)(0x42DEE38CUL)) +#define bFM4_GPIO_PZR7_P74 *((volatile unsigned int*)(0x42DEE390UL)) +#define bFM4_GPIO_PZR8_P80 *((volatile unsigned int*)(0x42DEE400UL)) +#define bFM4_GPIO_PZR8_P81 *((volatile unsigned int*)(0x42DEE404UL)) +#define bFM4_GPIO_PZRE_PE0 *((volatile unsigned int*)(0x42DEE700UL)) +#define bFM4_GPIO_PZRE_PE2 *((volatile unsigned int*)(0x42DEE708UL)) +#define bFM4_GPIO_PZRE_PE3 *((volatile unsigned int*)(0x42DEE70CUL)) + +/* Low voltage detection registers */ +#define bFM4_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM4_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM4_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM4_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM4_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM4_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM4_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM4_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* DS mode registers */ +#define bFM4_DS_RCK_CTL_RTCCKE *((volatile unsigned int*)(0x426A2080UL)) +#define bFM4_DS_PMD_CTL_RTCE *((volatile unsigned int*)(0x426B0000UL)) +#define bFM4_DS_WRFSR_WINITX *((volatile unsigned int*)(0x426B0080UL)) +#define bFM4_DS_WRFSR_WLVDH *((volatile unsigned int*)(0x426B0084UL)) +#define bFM4_DS_WIFSR_WRTCI *((volatile unsigned int*)(0x426B0100UL)) +#define bFM4_DS_WIFSR_WLVDI *((volatile unsigned int*)(0x426B0104UL)) +#define bFM4_DS_WIFSR_WUI0 *((volatile unsigned int*)(0x426B0108UL)) +#define bFM4_DS_WIFSR_WUI1 *((volatile unsigned int*)(0x426B010CUL)) +#define bFM4_DS_WIFSR_WUI2 *((volatile unsigned int*)(0x426B0110UL)) +#define bFM4_DS_WIFSR_WUI3 *((volatile unsigned int*)(0x426B0114UL)) +#define bFM4_DS_WIFSR_WUI4 *((volatile unsigned int*)(0x426B0118UL)) +#define bFM4_DS_WIFSR_WUI5 *((volatile unsigned int*)(0x426B011CUL)) +#define bFM4_DS_WIER_WRTCE *((volatile unsigned int*)(0x426B0180UL)) +#define bFM4_DS_WIER_WLVDE *((volatile unsigned int*)(0x426B0184UL)) +#define bFM4_DS_WIER_WUI1E *((volatile unsigned int*)(0x426B018CUL)) +#define bFM4_DS_WIER_WUI2E *((volatile unsigned int*)(0x426B0190UL)) +#define bFM4_DS_WIER_WUI3E *((volatile unsigned int*)(0x426B0194UL)) +#define bFM4_DS_WIER_WUI4E *((volatile unsigned int*)(0x426B0198UL)) +#define bFM4_DS_WIER_WUI5E *((volatile unsigned int*)(0x426B019CUL)) +#define bFM4_DS_WILVR_WUI1LV *((volatile unsigned int*)(0x426B0200UL)) +#define bFM4_DS_WILVR_WUI2LV *((volatile unsigned int*)(0x426B0204UL)) +#define bFM4_DS_WILVR_WUI3LV *((volatile unsigned int*)(0x426B0208UL)) +#define bFM4_DS_WILVR_WUI4LV *((volatile unsigned int*)(0x426B020CUL)) +#define bFM4_DS_WILVR_WUI5LV *((volatile unsigned int*)(0x426B0210UL)) +#define bFM4_DS_DSRAMR_SRAMR0 *((volatile unsigned int*)(0x426B0280UL)) +#define bFM4_DS_DSRAMR_SRAMR1 *((volatile unsigned int*)(0x426B0284UL)) + +/* USB clock registers */ +#define bFM4_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) +#define bFM4_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) +#define bFM4_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM4_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM4_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM4_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM4_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM4_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM4_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM4_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM4_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM4_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM4_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM4_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM4_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM4_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM4_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM4_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM4_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM4_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM4_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM4_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +/* CAN prescaler register */ +#define bFM4_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) +#define bFM4_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) +#define bFM4_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) +#define bFM4_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) + +/* MFS UART channel 0 registers */ +#define bFM4_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM4_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM4_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM4_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM4_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM4_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM4_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM4_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM4_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM4_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM4_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM4_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM4_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM4_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM4_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM4_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM4_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM4_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM4_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM4_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM4_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM4_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM4_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM4_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM4_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM4_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM4_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM4_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM4_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM4_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM4_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM4_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM4_MFS0_UART_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_UART_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_UART_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_UART_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_UART_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_UART_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_UART_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_UART_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_UART_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_UART_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_UART_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_UART_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_UART_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_UART_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_UART_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_UART_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_UART_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_UART_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) +#define bFM4_MFS0_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) + +/* MFS CSIO channel 0 registers */ +#define bFM4_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM4_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM4_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM4_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM4_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM4_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM4_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM4_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM4_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM4_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM4_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM4_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM4_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM4_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM4_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM4_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM4_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM4_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM4_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM4_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM4_MFS0_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42700098UL)) +#define bFM4_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM4_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM4_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM4_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM4_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM4_MFS0_CSIO_SSR_AWC *((volatile unsigned int*)(0x427000B0UL)) +#define bFM4_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM4_MFS0_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_CSIO_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_CSIO_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_CSIO_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42700380UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42700384UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42700388UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270038CUL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42700390UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42700394UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42700398UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270039CUL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427003A0UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427003A4UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427003A8UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427003ACUL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427003B0UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427003B4UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427003B8UL)) +#define bFM4_MFS0_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427003BCUL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42700400UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42700404UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42700408UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270040CUL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42700410UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42700414UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42700418UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270041CUL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42700420UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42700424UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42700428UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270042CUL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42700430UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42700434UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42700438UL)) +#define bFM4_MFS0_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270043CUL)) +#define bFM4_MFS0_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42700480UL)) +#define bFM4_MFS0_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42700484UL)) +#define bFM4_MFS0_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42700488UL)) +#define bFM4_MFS0_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270048CUL)) +#define bFM4_MFS0_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42700490UL)) +#define bFM4_MFS0_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42700498UL)) +#define bFM4_MFS0_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270049CUL)) +#define bFM4_MFS0_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427004A0UL)) +#define bFM4_MFS0_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427004ACUL)) +#define bFM4_MFS0_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427004B0UL)) +#define bFM4_MFS0_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427004B4UL)) +#define bFM4_MFS0_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42700500UL)) +#define bFM4_MFS0_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42700504UL)) +#define bFM4_MFS0_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42700508UL)) +#define bFM4_MFS0_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270050CUL)) +#define bFM4_MFS0_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42700510UL)) +#define bFM4_MFS0_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42700514UL)) +#define bFM4_MFS0_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42700518UL)) +#define bFM4_MFS0_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270051CUL)) +#define bFM4_MFS0_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42700520UL)) +#define bFM4_MFS0_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42700524UL)) +#define bFM4_MFS0_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42700528UL)) +#define bFM4_MFS0_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270052CUL)) +#define bFM4_MFS0_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42700530UL)) +#define bFM4_MFS0_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42700534UL)) +#define bFM4_MFS0_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42700538UL)) +#define bFM4_MFS0_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270053CUL)) +#define bFM4_MFS0_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42700580UL)) +#define bFM4_MFS0_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42700584UL)) +#define bFM4_MFS0_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42700588UL)) +#define bFM4_MFS0_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270058CUL)) +#define bFM4_MFS0_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42700590UL)) +#define bFM4_MFS0_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42700594UL)) +#define bFM4_MFS0_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42700598UL)) +#define bFM4_MFS0_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270059CUL)) +#define bFM4_MFS0_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427005A0UL)) +#define bFM4_MFS0_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427005A4UL)) +#define bFM4_MFS0_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427005A8UL)) +#define bFM4_MFS0_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427005ACUL)) +#define bFM4_MFS0_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427005B0UL)) +#define bFM4_MFS0_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427005B4UL)) +#define bFM4_MFS0_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427005B8UL)) +#define bFM4_MFS0_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427005BCUL)) +#define bFM4_MFS0_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42700600UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42700604UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42700614UL)) +#define bFM4_MFS0_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42700618UL)) +#define bFM4_MFS0_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270061CUL)) +#define bFM4_MFS0_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42700620UL)) +#define bFM4_MFS0_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42700624UL)) + +/* MFS LIN channel 0 registers */ +#define bFM4_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM4_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM4_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM4_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM4_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM4_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM4_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM4_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM4_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM4_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM4_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM4_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM4_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM4_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM4_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM4_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM4_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM4_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM4_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM4_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM4_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM4_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM4_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM4_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM4_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM4_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM4_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM4_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM4_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM4_MFS0_LIN_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_LIN_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_LIN_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_LIN_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_LIN_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_LIN_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_LIN_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_LIN_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_LIN_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_LIN_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) +#define bFM4_MFS0_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) + +/* MFS I2C channel 0 registers */ +#define bFM4_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM4_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM4_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM4_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM4_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM4_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM4_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM4_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM4_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM4_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM4_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM4_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM4_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM4_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM4_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM4_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM4_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM4_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM4_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM4_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM4_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM4_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM4_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM4_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM4_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM4_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM4_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM4_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM4_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM4_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM4_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM4_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM4_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM4_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM4_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM4_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM4_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM4_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM4_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM4_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM4_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM4_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM4_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM4_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM4_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM4_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) +#define bFM4_MFS0_I2C_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_I2C_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_I2C_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_I2C_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_I2C_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_I2C_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_I2C_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) +#define bFM4_MFS0_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) +#define bFM4_MFS0_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) +#define bFM4_MFS0_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) +#define bFM4_MFS0_I2C_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) +#define bFM4_MFS0_I2C_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) +#define bFM4_MFS0_I2C_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) +#define bFM4_MFS0_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) +#define bFM4_MFS0_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) +#define bFM4_MFS0_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) +#define bFM4_MFS0_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) +#define bFM4_MFS0_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) +#define bFM4_MFS0_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) +#define bFM4_MFS0_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) +#define bFM4_MFS0_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) +#define bFM4_MFS0_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) +#define bFM4_MFS0_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) +#define bFM4_MFS0_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) +#define bFM4_MFS0_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) + +/* MFS UART channel 1 registers */ +#define bFM4_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM4_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM4_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM4_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM4_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM4_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM4_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM4_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM4_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM4_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM4_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM4_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM4_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM4_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM4_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM4_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM4_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM4_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM4_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM4_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM4_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM4_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM4_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM4_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM4_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM4_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM4_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM4_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM4_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM4_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM4_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM4_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM4_MFS1_UART_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_UART_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_UART_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_UART_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_UART_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_UART_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_UART_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_UART_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_UART_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_UART_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_UART_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_UART_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_UART_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_UART_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_UART_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_UART_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_UART_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_UART_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) +#define bFM4_MFS1_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) + +/* MFS CSIO channel 1 registers */ +#define bFM4_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM4_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM4_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM4_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM4_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM4_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM4_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM4_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM4_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM4_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM4_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM4_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM4_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM4_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM4_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM4_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM4_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM4_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM4_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM4_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM4_MFS1_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42702098UL)) +#define bFM4_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM4_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM4_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM4_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM4_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM4_MFS1_CSIO_SSR_AWC *((volatile unsigned int*)(0x427020B0UL)) +#define bFM4_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM4_MFS1_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_CSIO_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_CSIO_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_CSIO_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42702380UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42702384UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42702388UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270238CUL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42702390UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42702394UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42702398UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270239CUL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427023A0UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427023A4UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427023A8UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427023ACUL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427023B0UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427023B4UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427023B8UL)) +#define bFM4_MFS1_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427023BCUL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42702400UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42702404UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42702408UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270240CUL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42702410UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42702414UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42702418UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270241CUL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42702420UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42702424UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42702428UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270242CUL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42702430UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42702434UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42702438UL)) +#define bFM4_MFS1_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270243CUL)) +#define bFM4_MFS1_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42702480UL)) +#define bFM4_MFS1_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42702484UL)) +#define bFM4_MFS1_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42702488UL)) +#define bFM4_MFS1_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270248CUL)) +#define bFM4_MFS1_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42702490UL)) +#define bFM4_MFS1_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42702498UL)) +#define bFM4_MFS1_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270249CUL)) +#define bFM4_MFS1_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427024A0UL)) +#define bFM4_MFS1_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427024ACUL)) +#define bFM4_MFS1_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427024B0UL)) +#define bFM4_MFS1_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427024B4UL)) +#define bFM4_MFS1_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42702500UL)) +#define bFM4_MFS1_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42702504UL)) +#define bFM4_MFS1_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42702508UL)) +#define bFM4_MFS1_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270250CUL)) +#define bFM4_MFS1_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42702510UL)) +#define bFM4_MFS1_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42702514UL)) +#define bFM4_MFS1_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42702518UL)) +#define bFM4_MFS1_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270251CUL)) +#define bFM4_MFS1_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42702520UL)) +#define bFM4_MFS1_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42702524UL)) +#define bFM4_MFS1_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42702528UL)) +#define bFM4_MFS1_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270252CUL)) +#define bFM4_MFS1_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42702530UL)) +#define bFM4_MFS1_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42702534UL)) +#define bFM4_MFS1_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42702538UL)) +#define bFM4_MFS1_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270253CUL)) +#define bFM4_MFS1_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42702580UL)) +#define bFM4_MFS1_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42702584UL)) +#define bFM4_MFS1_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42702588UL)) +#define bFM4_MFS1_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270258CUL)) +#define bFM4_MFS1_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42702590UL)) +#define bFM4_MFS1_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42702594UL)) +#define bFM4_MFS1_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42702598UL)) +#define bFM4_MFS1_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270259CUL)) +#define bFM4_MFS1_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427025A0UL)) +#define bFM4_MFS1_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427025A4UL)) +#define bFM4_MFS1_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427025A8UL)) +#define bFM4_MFS1_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427025ACUL)) +#define bFM4_MFS1_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427025B0UL)) +#define bFM4_MFS1_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427025B4UL)) +#define bFM4_MFS1_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427025B8UL)) +#define bFM4_MFS1_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427025BCUL)) +#define bFM4_MFS1_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42702600UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42702604UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42702614UL)) +#define bFM4_MFS1_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42702618UL)) +#define bFM4_MFS1_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270261CUL)) +#define bFM4_MFS1_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42702620UL)) +#define bFM4_MFS1_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42702624UL)) + +/* MFS LIN channel 1 registers */ +#define bFM4_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM4_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM4_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM4_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM4_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM4_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM4_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM4_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM4_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM4_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM4_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM4_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM4_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM4_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM4_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM4_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM4_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM4_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM4_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM4_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM4_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM4_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM4_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM4_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM4_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM4_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM4_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM4_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM4_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM4_MFS1_LIN_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_LIN_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_LIN_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_LIN_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_LIN_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_LIN_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_LIN_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_LIN_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_LIN_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_LIN_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) +#define bFM4_MFS1_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) + +/* MFS I2C channel 1 registers */ +#define bFM4_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM4_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM4_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM4_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM4_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM4_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM4_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM4_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM4_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM4_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM4_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM4_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM4_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM4_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM4_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM4_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM4_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM4_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM4_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM4_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM4_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM4_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM4_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM4_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM4_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM4_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM4_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM4_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM4_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM4_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM4_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM4_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM4_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM4_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM4_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM4_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM4_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM4_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM4_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM4_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM4_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM4_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM4_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM4_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM4_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM4_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) +#define bFM4_MFS1_I2C_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_I2C_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_I2C_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_I2C_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_I2C_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_I2C_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_I2C_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) +#define bFM4_MFS1_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) +#define bFM4_MFS1_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) +#define bFM4_MFS1_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) +#define bFM4_MFS1_I2C_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) +#define bFM4_MFS1_I2C_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) +#define bFM4_MFS1_I2C_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) +#define bFM4_MFS1_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) +#define bFM4_MFS1_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) +#define bFM4_MFS1_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) +#define bFM4_MFS1_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) +#define bFM4_MFS1_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) +#define bFM4_MFS1_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) +#define bFM4_MFS1_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) +#define bFM4_MFS1_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) +#define bFM4_MFS1_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) +#define bFM4_MFS1_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) +#define bFM4_MFS1_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) +#define bFM4_MFS1_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) + +/* MFS UART channel 2 registers */ +#define bFM4_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM4_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM4_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM4_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM4_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM4_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM4_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM4_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM4_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM4_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM4_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM4_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM4_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM4_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM4_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM4_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM4_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM4_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM4_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM4_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM4_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM4_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM4_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM4_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM4_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM4_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM4_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM4_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM4_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM4_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM4_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM4_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM4_MFS2_UART_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_UART_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_UART_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_UART_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_UART_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_UART_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_UART_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_UART_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_UART_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_UART_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_UART_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_UART_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_UART_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_UART_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_UART_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_UART_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_UART_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_UART_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) +#define bFM4_MFS2_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) + +/* MFS CSIO channel 2 registers */ +#define bFM4_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM4_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM4_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM4_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM4_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM4_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM4_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM4_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM4_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM4_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM4_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM4_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM4_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM4_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM4_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM4_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM4_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM4_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM4_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM4_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM4_MFS2_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42704098UL)) +#define bFM4_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM4_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM4_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM4_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM4_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM4_MFS2_CSIO_SSR_AWC *((volatile unsigned int*)(0x427040B0UL)) +#define bFM4_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM4_MFS2_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_CSIO_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_CSIO_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_CSIO_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42704380UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42704384UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42704388UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270438CUL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42704390UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42704394UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42704398UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270439CUL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427043A0UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427043A4UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427043A8UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427043ACUL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427043B0UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427043B4UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427043B8UL)) +#define bFM4_MFS2_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427043BCUL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42704400UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42704404UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42704408UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270440CUL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42704410UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42704414UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42704418UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270441CUL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42704420UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42704424UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42704428UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270442CUL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42704430UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42704434UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42704438UL)) +#define bFM4_MFS2_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270443CUL)) +#define bFM4_MFS2_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42704480UL)) +#define bFM4_MFS2_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42704484UL)) +#define bFM4_MFS2_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42704488UL)) +#define bFM4_MFS2_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270448CUL)) +#define bFM4_MFS2_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42704490UL)) +#define bFM4_MFS2_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42704498UL)) +#define bFM4_MFS2_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270449CUL)) +#define bFM4_MFS2_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427044A0UL)) +#define bFM4_MFS2_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427044ACUL)) +#define bFM4_MFS2_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427044B0UL)) +#define bFM4_MFS2_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427044B4UL)) +#define bFM4_MFS2_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42704500UL)) +#define bFM4_MFS2_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42704504UL)) +#define bFM4_MFS2_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42704508UL)) +#define bFM4_MFS2_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270450CUL)) +#define bFM4_MFS2_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42704510UL)) +#define bFM4_MFS2_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42704514UL)) +#define bFM4_MFS2_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42704518UL)) +#define bFM4_MFS2_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270451CUL)) +#define bFM4_MFS2_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42704520UL)) +#define bFM4_MFS2_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42704524UL)) +#define bFM4_MFS2_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42704528UL)) +#define bFM4_MFS2_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270452CUL)) +#define bFM4_MFS2_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42704530UL)) +#define bFM4_MFS2_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42704534UL)) +#define bFM4_MFS2_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42704538UL)) +#define bFM4_MFS2_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270453CUL)) +#define bFM4_MFS2_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42704580UL)) +#define bFM4_MFS2_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42704584UL)) +#define bFM4_MFS2_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42704588UL)) +#define bFM4_MFS2_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270458CUL)) +#define bFM4_MFS2_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42704590UL)) +#define bFM4_MFS2_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42704594UL)) +#define bFM4_MFS2_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42704598UL)) +#define bFM4_MFS2_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270459CUL)) +#define bFM4_MFS2_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427045A0UL)) +#define bFM4_MFS2_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427045A4UL)) +#define bFM4_MFS2_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427045A8UL)) +#define bFM4_MFS2_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427045ACUL)) +#define bFM4_MFS2_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427045B0UL)) +#define bFM4_MFS2_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427045B4UL)) +#define bFM4_MFS2_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427045B8UL)) +#define bFM4_MFS2_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427045BCUL)) +#define bFM4_MFS2_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42704600UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42704604UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42704614UL)) +#define bFM4_MFS2_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42704618UL)) +#define bFM4_MFS2_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270461CUL)) +#define bFM4_MFS2_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42704620UL)) +#define bFM4_MFS2_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42704624UL)) + +/* MFS LIN channel 2 registers */ +#define bFM4_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM4_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM4_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM4_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM4_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM4_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM4_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM4_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM4_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM4_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM4_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM4_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM4_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM4_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM4_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM4_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM4_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM4_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM4_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM4_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM4_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM4_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM4_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM4_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM4_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM4_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM4_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM4_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM4_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM4_MFS2_LIN_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_LIN_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_LIN_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_LIN_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_LIN_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_LIN_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_LIN_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_LIN_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_LIN_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_LIN_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) +#define bFM4_MFS2_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) + +/* MFS I2C channel 2 registers */ +#define bFM4_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM4_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM4_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM4_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM4_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM4_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM4_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM4_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM4_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM4_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM4_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM4_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM4_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM4_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM4_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM4_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM4_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM4_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM4_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM4_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM4_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM4_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM4_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM4_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM4_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM4_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM4_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM4_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM4_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM4_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM4_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM4_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM4_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM4_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM4_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM4_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM4_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM4_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM4_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM4_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM4_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM4_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM4_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM4_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM4_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM4_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) +#define bFM4_MFS2_I2C_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_I2C_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_I2C_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_I2C_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_I2C_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_I2C_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_I2C_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) +#define bFM4_MFS2_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) +#define bFM4_MFS2_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) +#define bFM4_MFS2_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) +#define bFM4_MFS2_I2C_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) +#define bFM4_MFS2_I2C_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) +#define bFM4_MFS2_I2C_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) +#define bFM4_MFS2_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) +#define bFM4_MFS2_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) +#define bFM4_MFS2_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) +#define bFM4_MFS2_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) +#define bFM4_MFS2_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) +#define bFM4_MFS2_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) +#define bFM4_MFS2_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) +#define bFM4_MFS2_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) +#define bFM4_MFS2_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) +#define bFM4_MFS2_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) +#define bFM4_MFS2_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) +#define bFM4_MFS2_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) + +/* MFS UART channel 3 registers */ +#define bFM4_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM4_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM4_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM4_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM4_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM4_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM4_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM4_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM4_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM4_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM4_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM4_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM4_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM4_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM4_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM4_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM4_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM4_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM4_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM4_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM4_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM4_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM4_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM4_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM4_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM4_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM4_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM4_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM4_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM4_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM4_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM4_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM4_MFS3_UART_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_UART_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_UART_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_UART_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_UART_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_UART_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_UART_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_UART_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_UART_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_UART_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_UART_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_UART_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_UART_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_UART_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_UART_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_UART_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_UART_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_UART_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) +#define bFM4_MFS3_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) + +/* MFS CSIO channel 3 registers */ +#define bFM4_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM4_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM4_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM4_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM4_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM4_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM4_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM4_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM4_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM4_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM4_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM4_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM4_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM4_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM4_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM4_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM4_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM4_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM4_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM4_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM4_MFS3_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42706098UL)) +#define bFM4_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM4_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM4_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM4_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM4_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM4_MFS3_CSIO_SSR_AWC *((volatile unsigned int*)(0x427060B0UL)) +#define bFM4_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM4_MFS3_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_CSIO_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_CSIO_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_CSIO_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42706380UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42706384UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42706388UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270638CUL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42706390UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42706394UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42706398UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270639CUL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427063A0UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427063A4UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427063A8UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427063ACUL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427063B0UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427063B4UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427063B8UL)) +#define bFM4_MFS3_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427063BCUL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42706400UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42706404UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42706408UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270640CUL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42706410UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42706414UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42706418UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270641CUL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42706420UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42706424UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42706428UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270642CUL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42706430UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42706434UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42706438UL)) +#define bFM4_MFS3_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270643CUL)) +#define bFM4_MFS3_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42706480UL)) +#define bFM4_MFS3_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42706484UL)) +#define bFM4_MFS3_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42706488UL)) +#define bFM4_MFS3_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270648CUL)) +#define bFM4_MFS3_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42706490UL)) +#define bFM4_MFS3_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42706498UL)) +#define bFM4_MFS3_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270649CUL)) +#define bFM4_MFS3_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427064A0UL)) +#define bFM4_MFS3_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427064ACUL)) +#define bFM4_MFS3_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427064B0UL)) +#define bFM4_MFS3_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427064B4UL)) +#define bFM4_MFS3_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42706500UL)) +#define bFM4_MFS3_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42706504UL)) +#define bFM4_MFS3_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42706508UL)) +#define bFM4_MFS3_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270650CUL)) +#define bFM4_MFS3_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42706510UL)) +#define bFM4_MFS3_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42706514UL)) +#define bFM4_MFS3_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42706518UL)) +#define bFM4_MFS3_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270651CUL)) +#define bFM4_MFS3_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42706520UL)) +#define bFM4_MFS3_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42706524UL)) +#define bFM4_MFS3_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42706528UL)) +#define bFM4_MFS3_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270652CUL)) +#define bFM4_MFS3_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42706530UL)) +#define bFM4_MFS3_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42706534UL)) +#define bFM4_MFS3_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42706538UL)) +#define bFM4_MFS3_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270653CUL)) +#define bFM4_MFS3_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42706580UL)) +#define bFM4_MFS3_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42706584UL)) +#define bFM4_MFS3_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42706588UL)) +#define bFM4_MFS3_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270658CUL)) +#define bFM4_MFS3_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42706590UL)) +#define bFM4_MFS3_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42706594UL)) +#define bFM4_MFS3_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42706598UL)) +#define bFM4_MFS3_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270659CUL)) +#define bFM4_MFS3_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427065A0UL)) +#define bFM4_MFS3_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427065A4UL)) +#define bFM4_MFS3_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427065A8UL)) +#define bFM4_MFS3_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427065ACUL)) +#define bFM4_MFS3_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427065B0UL)) +#define bFM4_MFS3_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427065B4UL)) +#define bFM4_MFS3_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427065B8UL)) +#define bFM4_MFS3_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427065BCUL)) +#define bFM4_MFS3_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42706600UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42706604UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42706614UL)) +#define bFM4_MFS3_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42706618UL)) +#define bFM4_MFS3_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270661CUL)) +#define bFM4_MFS3_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42706620UL)) +#define bFM4_MFS3_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42706624UL)) + +/* MFS LIN channel 3 registers */ +#define bFM4_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM4_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM4_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM4_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM4_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM4_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM4_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM4_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM4_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM4_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM4_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM4_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM4_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM4_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM4_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM4_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM4_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM4_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM4_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM4_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM4_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM4_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM4_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM4_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM4_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM4_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM4_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM4_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM4_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM4_MFS3_LIN_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_LIN_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_LIN_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_LIN_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_LIN_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_LIN_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_LIN_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_LIN_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_LIN_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_LIN_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) +#define bFM4_MFS3_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) + +/* MFS I2C channel 3 registers */ +#define bFM4_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM4_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM4_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM4_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM4_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM4_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM4_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM4_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM4_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM4_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM4_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM4_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM4_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM4_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM4_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM4_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM4_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM4_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM4_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM4_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM4_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM4_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM4_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM4_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM4_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM4_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM4_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM4_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM4_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM4_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM4_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM4_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM4_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM4_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM4_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM4_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM4_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM4_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM4_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM4_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM4_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM4_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM4_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM4_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM4_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM4_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) +#define bFM4_MFS3_I2C_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_I2C_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_I2C_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_I2C_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_I2C_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_I2C_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_I2C_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) +#define bFM4_MFS3_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) +#define bFM4_MFS3_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) +#define bFM4_MFS3_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) +#define bFM4_MFS3_I2C_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) +#define bFM4_MFS3_I2C_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) +#define bFM4_MFS3_I2C_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) +#define bFM4_MFS3_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) +#define bFM4_MFS3_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) +#define bFM4_MFS3_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) +#define bFM4_MFS3_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) +#define bFM4_MFS3_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) +#define bFM4_MFS3_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) +#define bFM4_MFS3_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) +#define bFM4_MFS3_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) +#define bFM4_MFS3_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) +#define bFM4_MFS3_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) +#define bFM4_MFS3_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) +#define bFM4_MFS3_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) + +/* MFS UART channel 4 registers */ +#define bFM4_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM4_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM4_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM4_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM4_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM4_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM4_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM4_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM4_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM4_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM4_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM4_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM4_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM4_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM4_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM4_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM4_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM4_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM4_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM4_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM4_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM4_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM4_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM4_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM4_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM4_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM4_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM4_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM4_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM4_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM4_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM4_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM4_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_UART_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM4_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* MFS CSIO channel 4 registers */ +#define bFM4_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM4_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM4_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM4_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM4_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM4_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM4_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM4_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM4_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM4_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM4_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM4_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM4_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM4_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM4_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM4_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM4_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM4_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM4_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM4_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM4_MFS4_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42708098UL)) +#define bFM4_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM4_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM4_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM4_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM4_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM4_MFS4_CSIO_SSR_AWC *((volatile unsigned int*)(0x427080B0UL)) +#define bFM4_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM4_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42708380UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42708384UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42708388UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270838CUL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42708390UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42708394UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42708398UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270839CUL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427083A0UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427083A4UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427083A8UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427083ACUL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427083B0UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427083B4UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427083B8UL)) +#define bFM4_MFS4_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427083BCUL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42708400UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42708404UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42708408UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270840CUL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42708410UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42708414UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42708418UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270841CUL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42708420UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42708424UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42708428UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270842CUL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42708430UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42708434UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42708438UL)) +#define bFM4_MFS4_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270843CUL)) +#define bFM4_MFS4_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42708480UL)) +#define bFM4_MFS4_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42708484UL)) +#define bFM4_MFS4_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42708488UL)) +#define bFM4_MFS4_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270848CUL)) +#define bFM4_MFS4_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42708490UL)) +#define bFM4_MFS4_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42708498UL)) +#define bFM4_MFS4_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270849CUL)) +#define bFM4_MFS4_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427084A0UL)) +#define bFM4_MFS4_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427084ACUL)) +#define bFM4_MFS4_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427084B0UL)) +#define bFM4_MFS4_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427084B4UL)) +#define bFM4_MFS4_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42708500UL)) +#define bFM4_MFS4_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42708504UL)) +#define bFM4_MFS4_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42708508UL)) +#define bFM4_MFS4_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270850CUL)) +#define bFM4_MFS4_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42708510UL)) +#define bFM4_MFS4_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42708514UL)) +#define bFM4_MFS4_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42708518UL)) +#define bFM4_MFS4_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270851CUL)) +#define bFM4_MFS4_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42708520UL)) +#define bFM4_MFS4_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42708524UL)) +#define bFM4_MFS4_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42708528UL)) +#define bFM4_MFS4_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270852CUL)) +#define bFM4_MFS4_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42708530UL)) +#define bFM4_MFS4_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42708534UL)) +#define bFM4_MFS4_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42708538UL)) +#define bFM4_MFS4_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270853CUL)) +#define bFM4_MFS4_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42708580UL)) +#define bFM4_MFS4_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42708584UL)) +#define bFM4_MFS4_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42708588UL)) +#define bFM4_MFS4_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270858CUL)) +#define bFM4_MFS4_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42708590UL)) +#define bFM4_MFS4_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42708594UL)) +#define bFM4_MFS4_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42708598UL)) +#define bFM4_MFS4_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270859CUL)) +#define bFM4_MFS4_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427085A0UL)) +#define bFM4_MFS4_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427085A4UL)) +#define bFM4_MFS4_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427085A8UL)) +#define bFM4_MFS4_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427085ACUL)) +#define bFM4_MFS4_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427085B0UL)) +#define bFM4_MFS4_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427085B4UL)) +#define bFM4_MFS4_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427085B8UL)) +#define bFM4_MFS4_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427085BCUL)) +#define bFM4_MFS4_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42708600UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42708604UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42708614UL)) +#define bFM4_MFS4_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42708618UL)) +#define bFM4_MFS4_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270861CUL)) +#define bFM4_MFS4_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42708620UL)) +#define bFM4_MFS4_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42708624UL)) + +/* MFS LIN channel 4 registers */ +#define bFM4_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM4_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM4_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM4_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM4_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM4_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM4_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM4_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM4_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM4_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM4_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM4_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM4_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM4_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM4_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM4_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM4_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM4_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM4_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM4_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM4_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM4_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM4_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM4_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM4_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM4_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM4_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM4_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM4_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM4_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM4_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* MFS I2C channel 4 registers */ +#define bFM4_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM4_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM4_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM4_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM4_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM4_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM4_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM4_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM4_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM4_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM4_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM4_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM4_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM4_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM4_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM4_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM4_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM4_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM4_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM4_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM4_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM4_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM4_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM4_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM4_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM4_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM4_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM4_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM4_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM4_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM4_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM4_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM4_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM4_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM4_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM4_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM4_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM4_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM4_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM4_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM4_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM4_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM4_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM4_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM4_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM4_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM4_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM4_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM4_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM4_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM4_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM4_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM4_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM4_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM4_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM4_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM4_MFS4_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM4_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM4_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM4_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM4_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM4_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM4_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM4_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM4_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* MFS UART channel 5 registers */ +#define bFM4_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM4_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM4_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM4_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM4_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM4_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM4_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM4_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM4_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM4_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM4_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM4_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM4_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM4_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM4_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM4_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM4_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM4_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM4_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM4_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM4_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM4_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM4_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM4_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM4_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM4_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM4_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM4_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM4_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM4_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM4_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM4_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM4_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM4_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* MFS CSIO channel 5 registers */ +#define bFM4_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM4_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM4_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM4_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM4_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM4_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM4_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM4_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM4_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM4_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM4_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM4_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM4_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM4_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM4_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM4_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM4_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM4_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM4_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM4_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM4_MFS5_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270A098UL)) +#define bFM4_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM4_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM4_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM4_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM4_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM4_MFS5_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM4_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM4_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270A380UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270A384UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270A388UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270A38CUL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270A390UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270A394UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270A398UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270A39CUL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270A3A0UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270A3A4UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270A3A8UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270A3ACUL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270A3B0UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270A3B4UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270A3B8UL)) +#define bFM4_MFS5_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270A3BCUL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270A400UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270A404UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270A408UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270A40CUL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270A410UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270A414UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270A418UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270A41CUL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270A420UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270A424UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270A428UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270A42CUL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270A430UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270A434UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270A438UL)) +#define bFM4_MFS5_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270A43CUL)) +#define bFM4_MFS5_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270A480UL)) +#define bFM4_MFS5_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270A484UL)) +#define bFM4_MFS5_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270A488UL)) +#define bFM4_MFS5_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270A48CUL)) +#define bFM4_MFS5_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270A490UL)) +#define bFM4_MFS5_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270A498UL)) +#define bFM4_MFS5_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270A49CUL)) +#define bFM4_MFS5_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270A4A0UL)) +#define bFM4_MFS5_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270A4ACUL)) +#define bFM4_MFS5_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270A4B0UL)) +#define bFM4_MFS5_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270A4B4UL)) +#define bFM4_MFS5_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270A500UL)) +#define bFM4_MFS5_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270A504UL)) +#define bFM4_MFS5_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270A508UL)) +#define bFM4_MFS5_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270A50CUL)) +#define bFM4_MFS5_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270A510UL)) +#define bFM4_MFS5_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270A514UL)) +#define bFM4_MFS5_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270A518UL)) +#define bFM4_MFS5_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270A51CUL)) +#define bFM4_MFS5_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270A520UL)) +#define bFM4_MFS5_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270A524UL)) +#define bFM4_MFS5_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270A528UL)) +#define bFM4_MFS5_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270A52CUL)) +#define bFM4_MFS5_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270A530UL)) +#define bFM4_MFS5_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270A534UL)) +#define bFM4_MFS5_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270A538UL)) +#define bFM4_MFS5_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270A53CUL)) +#define bFM4_MFS5_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270A580UL)) +#define bFM4_MFS5_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270A584UL)) +#define bFM4_MFS5_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270A588UL)) +#define bFM4_MFS5_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270A58CUL)) +#define bFM4_MFS5_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270A590UL)) +#define bFM4_MFS5_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270A594UL)) +#define bFM4_MFS5_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270A598UL)) +#define bFM4_MFS5_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270A59CUL)) +#define bFM4_MFS5_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270A5A0UL)) +#define bFM4_MFS5_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270A5A4UL)) +#define bFM4_MFS5_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270A5A8UL)) +#define bFM4_MFS5_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270A5ACUL)) +#define bFM4_MFS5_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270A5B0UL)) +#define bFM4_MFS5_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270A5B4UL)) +#define bFM4_MFS5_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270A5B8UL)) +#define bFM4_MFS5_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270A5BCUL)) +#define bFM4_MFS5_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270A600UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270A604UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270A614UL)) +#define bFM4_MFS5_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270A618UL)) +#define bFM4_MFS5_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270A61CUL)) +#define bFM4_MFS5_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270A620UL)) +#define bFM4_MFS5_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270A624UL)) + +/* MFS LIN channel 5 registers */ +#define bFM4_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM4_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM4_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM4_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM4_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM4_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM4_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM4_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM4_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM4_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM4_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM4_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM4_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM4_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM4_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM4_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM4_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM4_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM4_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM4_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM4_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM4_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM4_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM4_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM4_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM4_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM4_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM4_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM4_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM4_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM4_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* MFS I2C channel 5 registers */ +#define bFM4_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM4_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM4_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM4_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM4_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM4_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM4_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM4_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM4_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM4_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM4_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM4_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM4_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM4_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM4_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM4_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM4_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM4_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM4_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM4_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM4_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM4_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM4_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM4_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM4_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM4_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM4_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM4_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM4_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM4_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM4_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM4_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM4_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM4_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM4_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM4_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM4_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM4_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM4_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM4_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM4_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM4_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM4_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM4_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM4_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM4_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM4_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM4_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM4_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM4_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM4_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM4_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM4_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM4_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM4_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM4_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM4_MFS5_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM4_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM4_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM4_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM4_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM4_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM4_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM4_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM4_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* MFS UART channel 6 registers */ +#define bFM4_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM4_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM4_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM4_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM4_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM4_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM4_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM4_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM4_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM4_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM4_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM4_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM4_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM4_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM4_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM4_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM4_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM4_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM4_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM4_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM4_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM4_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM4_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM4_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM4_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM4_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM4_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM4_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM4_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM4_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM4_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM4_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM4_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM4_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* MFS CSIO channel 6 registers */ +#define bFM4_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM4_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM4_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM4_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM4_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM4_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM4_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM4_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM4_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM4_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM4_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM4_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM4_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM4_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM4_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM4_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM4_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM4_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM4_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM4_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM4_MFS6_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270C098UL)) +#define bFM4_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM4_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM4_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM4_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM4_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM4_MFS6_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM4_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM4_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270C380UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270C384UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270C388UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270C38CUL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270C390UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270C394UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270C398UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270C39CUL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270C3A0UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270C3A4UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270C3A8UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270C3ACUL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270C3B0UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270C3B4UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270C3B8UL)) +#define bFM4_MFS6_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270C3BCUL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270C400UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270C404UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270C408UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270C40CUL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270C410UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270C414UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270C418UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270C41CUL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270C420UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270C424UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270C428UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270C42CUL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270C430UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270C434UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270C438UL)) +#define bFM4_MFS6_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270C43CUL)) +#define bFM4_MFS6_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270C480UL)) +#define bFM4_MFS6_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270C484UL)) +#define bFM4_MFS6_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270C488UL)) +#define bFM4_MFS6_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270C48CUL)) +#define bFM4_MFS6_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270C490UL)) +#define bFM4_MFS6_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270C498UL)) +#define bFM4_MFS6_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270C49CUL)) +#define bFM4_MFS6_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270C4A0UL)) +#define bFM4_MFS6_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270C4ACUL)) +#define bFM4_MFS6_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270C4B0UL)) +#define bFM4_MFS6_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270C4B4UL)) +#define bFM4_MFS6_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270C500UL)) +#define bFM4_MFS6_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270C504UL)) +#define bFM4_MFS6_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270C508UL)) +#define bFM4_MFS6_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270C50CUL)) +#define bFM4_MFS6_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270C510UL)) +#define bFM4_MFS6_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270C514UL)) +#define bFM4_MFS6_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270C518UL)) +#define bFM4_MFS6_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270C51CUL)) +#define bFM4_MFS6_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270C520UL)) +#define bFM4_MFS6_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270C524UL)) +#define bFM4_MFS6_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270C528UL)) +#define bFM4_MFS6_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270C52CUL)) +#define bFM4_MFS6_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270C530UL)) +#define bFM4_MFS6_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270C534UL)) +#define bFM4_MFS6_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270C538UL)) +#define bFM4_MFS6_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270C53CUL)) +#define bFM4_MFS6_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270C580UL)) +#define bFM4_MFS6_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270C584UL)) +#define bFM4_MFS6_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270C588UL)) +#define bFM4_MFS6_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270C58CUL)) +#define bFM4_MFS6_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270C590UL)) +#define bFM4_MFS6_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270C594UL)) +#define bFM4_MFS6_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270C598UL)) +#define bFM4_MFS6_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270C59CUL)) +#define bFM4_MFS6_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270C5A0UL)) +#define bFM4_MFS6_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270C5A4UL)) +#define bFM4_MFS6_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270C5A8UL)) +#define bFM4_MFS6_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270C5ACUL)) +#define bFM4_MFS6_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270C5B0UL)) +#define bFM4_MFS6_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270C5B4UL)) +#define bFM4_MFS6_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270C5B8UL)) +#define bFM4_MFS6_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270C5BCUL)) +#define bFM4_MFS6_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270C600UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270C604UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270C614UL)) +#define bFM4_MFS6_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270C618UL)) +#define bFM4_MFS6_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270C61CUL)) +#define bFM4_MFS6_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270C620UL)) +#define bFM4_MFS6_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270C624UL)) + +/* MFS LIN channel 6 registers */ +#define bFM4_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM4_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM4_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM4_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM4_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM4_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM4_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM4_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM4_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM4_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM4_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM4_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM4_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM4_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM4_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM4_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM4_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM4_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM4_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM4_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM4_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM4_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM4_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM4_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM4_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM4_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM4_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM4_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM4_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM4_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM4_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* MFS I2C channel 6 registers */ +#define bFM4_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM4_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM4_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM4_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM4_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM4_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM4_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM4_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM4_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM4_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM4_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM4_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM4_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM4_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM4_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM4_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM4_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM4_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM4_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM4_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM4_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM4_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM4_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM4_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM4_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM4_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM4_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM4_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM4_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM4_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM4_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM4_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM4_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM4_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM4_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM4_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM4_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM4_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM4_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM4_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM4_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM4_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM4_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM4_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM4_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM4_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM4_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM4_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM4_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM4_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM4_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM4_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM4_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM4_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM4_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM4_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM4_MFS6_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM4_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM4_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM4_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM4_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM4_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM4_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM4_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM4_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* MFS UART channel 7 registers */ +#define bFM4_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM4_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM4_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM4_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM4_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM4_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM4_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM4_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM4_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM4_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM4_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM4_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM4_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM4_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM4_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM4_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM4_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM4_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM4_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM4_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM4_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM4_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM4_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM4_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM4_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM4_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM4_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM4_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM4_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM4_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM4_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM4_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM4_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM4_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* MFS CSIO channel 7 registers */ +#define bFM4_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM4_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM4_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM4_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM4_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM4_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM4_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM4_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM4_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM4_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM4_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM4_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM4_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM4_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM4_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM4_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM4_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM4_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM4_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM4_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM4_MFS7_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270E098UL)) +#define bFM4_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM4_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM4_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM4_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM4_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM4_MFS7_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM4_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM4_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270E380UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270E384UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270E388UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270E38CUL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270E390UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270E394UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270E398UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270E39CUL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270E3A0UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270E3A4UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270E3A8UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270E3ACUL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270E3B0UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270E3B4UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270E3B8UL)) +#define bFM4_MFS7_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270E3BCUL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270E400UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270E404UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270E408UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270E40CUL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270E410UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270E414UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270E418UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270E41CUL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270E420UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270E424UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270E428UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270E42CUL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270E430UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270E434UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270E438UL)) +#define bFM4_MFS7_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270E43CUL)) +#define bFM4_MFS7_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270E480UL)) +#define bFM4_MFS7_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270E484UL)) +#define bFM4_MFS7_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270E488UL)) +#define bFM4_MFS7_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270E48CUL)) +#define bFM4_MFS7_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270E490UL)) +#define bFM4_MFS7_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270E498UL)) +#define bFM4_MFS7_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270E49CUL)) +#define bFM4_MFS7_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270E4A0UL)) +#define bFM4_MFS7_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270E4ACUL)) +#define bFM4_MFS7_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270E4B0UL)) +#define bFM4_MFS7_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270E4B4UL)) +#define bFM4_MFS7_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270E500UL)) +#define bFM4_MFS7_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270E504UL)) +#define bFM4_MFS7_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270E508UL)) +#define bFM4_MFS7_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270E50CUL)) +#define bFM4_MFS7_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270E510UL)) +#define bFM4_MFS7_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270E514UL)) +#define bFM4_MFS7_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270E518UL)) +#define bFM4_MFS7_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270E51CUL)) +#define bFM4_MFS7_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270E520UL)) +#define bFM4_MFS7_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270E524UL)) +#define bFM4_MFS7_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270E528UL)) +#define bFM4_MFS7_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270E52CUL)) +#define bFM4_MFS7_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270E530UL)) +#define bFM4_MFS7_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270E534UL)) +#define bFM4_MFS7_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270E538UL)) +#define bFM4_MFS7_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270E53CUL)) +#define bFM4_MFS7_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270E580UL)) +#define bFM4_MFS7_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270E584UL)) +#define bFM4_MFS7_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270E588UL)) +#define bFM4_MFS7_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270E58CUL)) +#define bFM4_MFS7_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270E590UL)) +#define bFM4_MFS7_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270E594UL)) +#define bFM4_MFS7_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270E598UL)) +#define bFM4_MFS7_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270E59CUL)) +#define bFM4_MFS7_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270E5A0UL)) +#define bFM4_MFS7_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270E5A4UL)) +#define bFM4_MFS7_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270E5A8UL)) +#define bFM4_MFS7_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270E5ACUL)) +#define bFM4_MFS7_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270E5B0UL)) +#define bFM4_MFS7_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270E5B4UL)) +#define bFM4_MFS7_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270E5B8UL)) +#define bFM4_MFS7_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270E5BCUL)) +#define bFM4_MFS7_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270E600UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270E604UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270E614UL)) +#define bFM4_MFS7_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270E618UL)) +#define bFM4_MFS7_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270E61CUL)) +#define bFM4_MFS7_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270E620UL)) +#define bFM4_MFS7_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270E624UL)) + +/* MFS LIN channel 7 registers */ +#define bFM4_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM4_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM4_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM4_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM4_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM4_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM4_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM4_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM4_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM4_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM4_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM4_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM4_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM4_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM4_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM4_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM4_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM4_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM4_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM4_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM4_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM4_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM4_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM4_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM4_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM4_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM4_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM4_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM4_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM4_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM4_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* MFS I2C channel 7 registers */ +#define bFM4_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM4_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM4_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM4_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM4_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM4_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM4_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM4_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM4_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM4_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM4_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM4_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM4_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM4_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM4_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM4_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM4_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM4_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM4_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM4_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM4_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM4_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM4_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM4_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM4_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM4_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM4_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM4_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM4_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM4_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM4_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM4_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM4_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM4_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM4_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM4_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM4_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM4_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM4_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM4_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM4_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM4_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM4_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM4_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM4_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM4_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM4_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM4_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM4_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM4_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM4_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM4_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM4_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM4_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM4_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM4_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM4_MFS7_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM4_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM4_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM4_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM4_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM4_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM4_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM4_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM4_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* MFS UART channel 8 registers */ +#define bFM4_MFS8_UART_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) +#define bFM4_MFS8_UART_SMR_BDS *((volatile unsigned int*)(0x42710008UL)) +#define bFM4_MFS8_UART_SMR_SBL *((volatile unsigned int*)(0x4271000CUL)) +#define bFM4_MFS8_UART_SMR_WUCR *((volatile unsigned int*)(0x42710010UL)) +#define bFM4_MFS8_UART_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) +#define bFM4_MFS8_UART_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) +#define bFM4_MFS8_UART_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM4_MFS8_UART_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) +#define bFM4_MFS8_UART_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) +#define bFM4_MFS8_UART_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) +#define bFM4_MFS8_UART_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) +#define bFM4_MFS8_UART_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) +#define bFM4_MFS8_UART_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) +#define bFM4_MFS8_UART_ESCR_L0 *((volatile unsigned int*)(0x42710080UL)) +#define bFM4_MFS8_UART_ESCR_L1 *((volatile unsigned int*)(0x42710084UL)) +#define bFM4_MFS8_UART_ESCR_L2 *((volatile unsigned int*)(0x42710088UL)) +#define bFM4_MFS8_UART_ESCR_P *((volatile unsigned int*)(0x4271008CUL)) +#define bFM4_MFS8_UART_ESCR_PEN *((volatile unsigned int*)(0x42710090UL)) +#define bFM4_MFS8_UART_ESCR_INV *((volatile unsigned int*)(0x42710094UL)) +#define bFM4_MFS8_UART_ESCR_ESBL *((volatile unsigned int*)(0x42710098UL)) +#define bFM4_MFS8_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271009CUL)) +#define bFM4_MFS8_UART_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) +#define bFM4_MFS8_UART_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) +#define bFM4_MFS8_UART_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) +#define bFM4_MFS8_UART_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) +#define bFM4_MFS8_UART_SSR_FRE *((volatile unsigned int*)(0x427100B0UL)) +#define bFM4_MFS8_UART_SSR_PE *((volatile unsigned int*)(0x427100B4UL)) +#define bFM4_MFS8_UART_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) +#define bFM4_MFS8_UART_RDR_AD *((volatile unsigned int*)(0x42710120UL)) +#define bFM4_MFS8_UART_TDR_AD *((volatile unsigned int*)(0x42710120UL)) +#define bFM4_MFS8_UART_BGR_EXT *((volatile unsigned int*)(0x427101BCUL)) +#define bFM4_MFS8_UART_BGR1_EXT *((volatile unsigned int*)(0x427101BCUL)) +#define bFM4_MFS8_UART_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_UART_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_UART_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_UART_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_UART_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_UART_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_UART_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_UART_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_UART_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_UART_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_UART_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_UART_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_UART_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_UART_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_UART_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_UART_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_UART_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_UART_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) +#define bFM4_MFS8_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) + +/* MFS CSIO channel 8 registers */ +#define bFM4_MFS8_CSIO_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) +#define bFM4_MFS8_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42710004UL)) +#define bFM4_MFS8_CSIO_SMR_BDS *((volatile unsigned int*)(0x42710008UL)) +#define bFM4_MFS8_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271000CUL)) +#define bFM4_MFS8_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) +#define bFM4_MFS8_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) +#define bFM4_MFS8_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM4_MFS8_CSIO_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) +#define bFM4_MFS8_CSIO_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) +#define bFM4_MFS8_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) +#define bFM4_MFS8_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) +#define bFM4_MFS8_CSIO_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) +#define bFM4_MFS8_CSIO_SCR_SPI *((volatile unsigned int*)(0x42710034UL)) +#define bFM4_MFS8_CSIO_SCR_MS *((volatile unsigned int*)(0x42710038UL)) +#define bFM4_MFS8_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) +#define bFM4_MFS8_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42710080UL)) +#define bFM4_MFS8_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42710084UL)) +#define bFM4_MFS8_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42710088UL)) +#define bFM4_MFS8_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271008CUL)) +#define bFM4_MFS8_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42710090UL)) +#define bFM4_MFS8_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42710098UL)) +#define bFM4_MFS8_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271009CUL)) +#define bFM4_MFS8_CSIO_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) +#define bFM4_MFS8_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) +#define bFM4_MFS8_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) +#define bFM4_MFS8_CSIO_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) +#define bFM4_MFS8_CSIO_SSR_AWC *((volatile unsigned int*)(0x427100B0UL)) +#define bFM4_MFS8_CSIO_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) +#define bFM4_MFS8_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_CSIO_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_CSIO_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_CSIO_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42710380UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42710384UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42710388UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271038CUL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42710390UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42710394UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42710398UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271039CUL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427103A0UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427103A4UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427103A8UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427103ACUL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427103B0UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427103B4UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427103B8UL)) +#define bFM4_MFS8_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427103BCUL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42710400UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42710404UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42710408UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271040CUL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42710410UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42710414UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42710418UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271041CUL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42710420UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42710424UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42710428UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271042CUL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42710430UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42710434UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42710438UL)) +#define bFM4_MFS8_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271043CUL)) +#define bFM4_MFS8_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42710480UL)) +#define bFM4_MFS8_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42710484UL)) +#define bFM4_MFS8_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42710488UL)) +#define bFM4_MFS8_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271048CUL)) +#define bFM4_MFS8_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42710490UL)) +#define bFM4_MFS8_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42710498UL)) +#define bFM4_MFS8_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271049CUL)) +#define bFM4_MFS8_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427104A0UL)) +#define bFM4_MFS8_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427104ACUL)) +#define bFM4_MFS8_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427104B0UL)) +#define bFM4_MFS8_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427104B4UL)) +#define bFM4_MFS8_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42710500UL)) +#define bFM4_MFS8_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42710504UL)) +#define bFM4_MFS8_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42710508UL)) +#define bFM4_MFS8_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271050CUL)) +#define bFM4_MFS8_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42710510UL)) +#define bFM4_MFS8_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42710514UL)) +#define bFM4_MFS8_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42710518UL)) +#define bFM4_MFS8_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271051CUL)) +#define bFM4_MFS8_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42710520UL)) +#define bFM4_MFS8_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42710524UL)) +#define bFM4_MFS8_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42710528UL)) +#define bFM4_MFS8_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271052CUL)) +#define bFM4_MFS8_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42710530UL)) +#define bFM4_MFS8_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42710534UL)) +#define bFM4_MFS8_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42710538UL)) +#define bFM4_MFS8_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271053CUL)) +#define bFM4_MFS8_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42710580UL)) +#define bFM4_MFS8_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42710584UL)) +#define bFM4_MFS8_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42710588UL)) +#define bFM4_MFS8_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271058CUL)) +#define bFM4_MFS8_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42710590UL)) +#define bFM4_MFS8_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42710594UL)) +#define bFM4_MFS8_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42710598UL)) +#define bFM4_MFS8_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271059CUL)) +#define bFM4_MFS8_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427105A0UL)) +#define bFM4_MFS8_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427105A4UL)) +#define bFM4_MFS8_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427105A8UL)) +#define bFM4_MFS8_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427105ACUL)) +#define bFM4_MFS8_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427105B0UL)) +#define bFM4_MFS8_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427105B4UL)) +#define bFM4_MFS8_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427105B8UL)) +#define bFM4_MFS8_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427105BCUL)) +#define bFM4_MFS8_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42710600UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42710604UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42710614UL)) +#define bFM4_MFS8_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42710618UL)) +#define bFM4_MFS8_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271061CUL)) +#define bFM4_MFS8_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42710620UL)) +#define bFM4_MFS8_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42710624UL)) + +/* MFS LIN channel 8 registers */ +#define bFM4_MFS8_LIN_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) +#define bFM4_MFS8_LIN_SMR_SBL *((volatile unsigned int*)(0x4271000CUL)) +#define bFM4_MFS8_LIN_SMR_WUCR *((volatile unsigned int*)(0x42710010UL)) +#define bFM4_MFS8_LIN_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) +#define bFM4_MFS8_LIN_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) +#define bFM4_MFS8_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM4_MFS8_LIN_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) +#define bFM4_MFS8_LIN_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) +#define bFM4_MFS8_LIN_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) +#define bFM4_MFS8_LIN_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) +#define bFM4_MFS8_LIN_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) +#define bFM4_MFS8_LIN_SCR_LBR *((volatile unsigned int*)(0x42710034UL)) +#define bFM4_MFS8_LIN_SCR_MS *((volatile unsigned int*)(0x42710038UL)) +#define bFM4_MFS8_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) +#define bFM4_MFS8_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42710080UL)) +#define bFM4_MFS8_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42710084UL)) +#define bFM4_MFS8_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42710088UL)) +#define bFM4_MFS8_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271008CUL)) +#define bFM4_MFS8_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42710090UL)) +#define bFM4_MFS8_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42710098UL)) +#define bFM4_MFS8_LIN_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) +#define bFM4_MFS8_LIN_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) +#define bFM4_MFS8_LIN_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) +#define bFM4_MFS8_LIN_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) +#define bFM4_MFS8_LIN_SSR_FRE *((volatile unsigned int*)(0x427100B0UL)) +#define bFM4_MFS8_LIN_SSR_LBD *((volatile unsigned int*)(0x427100B4UL)) +#define bFM4_MFS8_LIN_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) +#define bFM4_MFS8_LIN_BGR_EXT *((volatile unsigned int*)(0x427101BCUL)) +#define bFM4_MFS8_LIN_BGR1_EXT *((volatile unsigned int*)(0x427101BCUL)) +#define bFM4_MFS8_LIN_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_LIN_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_LIN_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_LIN_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_LIN_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_LIN_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_LIN_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_LIN_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_LIN_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_LIN_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) +#define bFM4_MFS8_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) + +/* MFS I2C channel 8 registers */ +#define bFM4_MFS8_I2C_SMR_TIE *((volatile unsigned int*)(0x42710008UL)) +#define bFM4_MFS8_I2C_SMR_RIE *((volatile unsigned int*)(0x4271000CUL)) +#define bFM4_MFS8_I2C_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) +#define bFM4_MFS8_I2C_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) +#define bFM4_MFS8_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM4_MFS8_I2C_IBCR_INT *((volatile unsigned int*)(0x42710020UL)) +#define bFM4_MFS8_I2C_IBCR_BER *((volatile unsigned int*)(0x42710024UL)) +#define bFM4_MFS8_I2C_IBCR_INTE *((volatile unsigned int*)(0x42710028UL)) +#define bFM4_MFS8_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271002CUL)) +#define bFM4_MFS8_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42710030UL)) +#define bFM4_MFS8_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42710034UL)) +#define bFM4_MFS8_I2C_IBCR_ACT *((volatile unsigned int*)(0x42710038UL)) +#define bFM4_MFS8_I2C_IBCR_SCC *((volatile unsigned int*)(0x42710038UL)) +#define bFM4_MFS8_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271003CUL)) +#define bFM4_MFS8_I2C_IBSR_BB *((volatile unsigned int*)(0x42710080UL)) +#define bFM4_MFS8_I2C_IBSR_SPC *((volatile unsigned int*)(0x42710084UL)) +#define bFM4_MFS8_I2C_IBSR_RSC *((volatile unsigned int*)(0x42710088UL)) +#define bFM4_MFS8_I2C_IBSR_AL *((volatile unsigned int*)(0x4271008CUL)) +#define bFM4_MFS8_I2C_IBSR_TRX *((volatile unsigned int*)(0x42710090UL)) +#define bFM4_MFS8_I2C_IBSR_RSA *((volatile unsigned int*)(0x42710094UL)) +#define bFM4_MFS8_I2C_IBSR_RACK *((volatile unsigned int*)(0x42710098UL)) +#define bFM4_MFS8_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271009CUL)) +#define bFM4_MFS8_I2C_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) +#define bFM4_MFS8_I2C_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) +#define bFM4_MFS8_I2C_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) +#define bFM4_MFS8_I2C_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) +#define bFM4_MFS8_I2C_SSR_TBIE *((volatile unsigned int*)(0x427100B0UL)) +#define bFM4_MFS8_I2C_SSR_DMA *((volatile unsigned int*)(0x427100B4UL)) +#define bFM4_MFS8_I2C_SSR_TSET *((volatile unsigned int*)(0x427100B8UL)) +#define bFM4_MFS8_I2C_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) +#define bFM4_MFS8_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42710200UL)) +#define bFM4_MFS8_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42710204UL)) +#define bFM4_MFS8_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42710208UL)) +#define bFM4_MFS8_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271020CUL)) +#define bFM4_MFS8_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42710210UL)) +#define bFM4_MFS8_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42710214UL)) +#define bFM4_MFS8_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42710218UL)) +#define bFM4_MFS8_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271021CUL)) +#define bFM4_MFS8_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42710220UL)) +#define bFM4_MFS8_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42710224UL)) +#define bFM4_MFS8_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42710228UL)) +#define bFM4_MFS8_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271022CUL)) +#define bFM4_MFS8_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42710230UL)) +#define bFM4_MFS8_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42710234UL)) +#define bFM4_MFS8_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42710238UL)) +#define bFM4_MFS8_I2C_ISMK_EN *((volatile unsigned int*)(0x4271023CUL)) +#define bFM4_MFS8_I2C_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_I2C_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_I2C_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_I2C_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_I2C_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_I2C_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_I2C_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) +#define bFM4_MFS8_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) +#define bFM4_MFS8_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) +#define bFM4_MFS8_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) +#define bFM4_MFS8_I2C_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) +#define bFM4_MFS8_I2C_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) +#define bFM4_MFS8_I2C_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) +#define bFM4_MFS8_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) +#define bFM4_MFS8_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) +#define bFM4_MFS8_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) +#define bFM4_MFS8_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) +#define bFM4_MFS8_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) +#define bFM4_MFS8_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) +#define bFM4_MFS8_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) +#define bFM4_MFS8_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) +#define bFM4_MFS8_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) +#define bFM4_MFS8_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) +#define bFM4_MFS8_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) +#define bFM4_MFS8_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) + +/* MFS UART channel 9 registers */ +#define bFM4_MFS9_UART_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) +#define bFM4_MFS9_UART_SMR_BDS *((volatile unsigned int*)(0x42712008UL)) +#define bFM4_MFS9_UART_SMR_SBL *((volatile unsigned int*)(0x4271200CUL)) +#define bFM4_MFS9_UART_SMR_WUCR *((volatile unsigned int*)(0x42712010UL)) +#define bFM4_MFS9_UART_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) +#define bFM4_MFS9_UART_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) +#define bFM4_MFS9_UART_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) +#define bFM4_MFS9_UART_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) +#define bFM4_MFS9_UART_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) +#define bFM4_MFS9_UART_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) +#define bFM4_MFS9_UART_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) +#define bFM4_MFS9_UART_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) +#define bFM4_MFS9_UART_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) +#define bFM4_MFS9_UART_ESCR_L0 *((volatile unsigned int*)(0x42712080UL)) +#define bFM4_MFS9_UART_ESCR_L1 *((volatile unsigned int*)(0x42712084UL)) +#define bFM4_MFS9_UART_ESCR_L2 *((volatile unsigned int*)(0x42712088UL)) +#define bFM4_MFS9_UART_ESCR_P *((volatile unsigned int*)(0x4271208CUL)) +#define bFM4_MFS9_UART_ESCR_PEN *((volatile unsigned int*)(0x42712090UL)) +#define bFM4_MFS9_UART_ESCR_INV *((volatile unsigned int*)(0x42712094UL)) +#define bFM4_MFS9_UART_ESCR_ESBL *((volatile unsigned int*)(0x42712098UL)) +#define bFM4_MFS9_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271209CUL)) +#define bFM4_MFS9_UART_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) +#define bFM4_MFS9_UART_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) +#define bFM4_MFS9_UART_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) +#define bFM4_MFS9_UART_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) +#define bFM4_MFS9_UART_SSR_FRE *((volatile unsigned int*)(0x427120B0UL)) +#define bFM4_MFS9_UART_SSR_PE *((volatile unsigned int*)(0x427120B4UL)) +#define bFM4_MFS9_UART_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) +#define bFM4_MFS9_UART_RDR_AD *((volatile unsigned int*)(0x42712120UL)) +#define bFM4_MFS9_UART_TDR_AD *((volatile unsigned int*)(0x42712120UL)) +#define bFM4_MFS9_UART_BGR_EXT *((volatile unsigned int*)(0x427121BCUL)) +#define bFM4_MFS9_UART_BGR1_EXT *((volatile unsigned int*)(0x427121BCUL)) +#define bFM4_MFS9_UART_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_UART_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_UART_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_UART_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_UART_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_UART_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_UART_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_UART_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_UART_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_UART_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_UART_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_UART_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_UART_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_UART_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_UART_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_UART_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_UART_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_UART_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) +#define bFM4_MFS9_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) + +/* MFS CSIO channel 9 registers */ +#define bFM4_MFS9_CSIO_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) +#define bFM4_MFS9_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42712004UL)) +#define bFM4_MFS9_CSIO_SMR_BDS *((volatile unsigned int*)(0x42712008UL)) +#define bFM4_MFS9_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271200CUL)) +#define bFM4_MFS9_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) +#define bFM4_MFS9_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) +#define bFM4_MFS9_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) +#define bFM4_MFS9_CSIO_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) +#define bFM4_MFS9_CSIO_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) +#define bFM4_MFS9_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) +#define bFM4_MFS9_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) +#define bFM4_MFS9_CSIO_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) +#define bFM4_MFS9_CSIO_SCR_SPI *((volatile unsigned int*)(0x42712034UL)) +#define bFM4_MFS9_CSIO_SCR_MS *((volatile unsigned int*)(0x42712038UL)) +#define bFM4_MFS9_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) +#define bFM4_MFS9_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42712080UL)) +#define bFM4_MFS9_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42712084UL)) +#define bFM4_MFS9_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42712088UL)) +#define bFM4_MFS9_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271208CUL)) +#define bFM4_MFS9_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42712090UL)) +#define bFM4_MFS9_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42712098UL)) +#define bFM4_MFS9_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271209CUL)) +#define bFM4_MFS9_CSIO_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) +#define bFM4_MFS9_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) +#define bFM4_MFS9_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) +#define bFM4_MFS9_CSIO_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) +#define bFM4_MFS9_CSIO_SSR_AWC *((volatile unsigned int*)(0x427120B0UL)) +#define bFM4_MFS9_CSIO_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) +#define bFM4_MFS9_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_CSIO_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_CSIO_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_CSIO_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42712380UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42712384UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42712388UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271238CUL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42712390UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42712394UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42712398UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271239CUL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427123A0UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427123A4UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427123A8UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427123ACUL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427123B0UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427123B4UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427123B8UL)) +#define bFM4_MFS9_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427123BCUL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42712400UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42712404UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42712408UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271240CUL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42712410UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42712414UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42712418UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271241CUL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42712420UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42712424UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42712428UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271242CUL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42712430UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42712434UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42712438UL)) +#define bFM4_MFS9_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271243CUL)) +#define bFM4_MFS9_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42712480UL)) +#define bFM4_MFS9_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42712484UL)) +#define bFM4_MFS9_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42712488UL)) +#define bFM4_MFS9_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271248CUL)) +#define bFM4_MFS9_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42712490UL)) +#define bFM4_MFS9_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42712498UL)) +#define bFM4_MFS9_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271249CUL)) +#define bFM4_MFS9_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427124A0UL)) +#define bFM4_MFS9_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427124ACUL)) +#define bFM4_MFS9_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427124B0UL)) +#define bFM4_MFS9_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427124B4UL)) +#define bFM4_MFS9_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42712500UL)) +#define bFM4_MFS9_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42712504UL)) +#define bFM4_MFS9_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42712508UL)) +#define bFM4_MFS9_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271250CUL)) +#define bFM4_MFS9_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42712510UL)) +#define bFM4_MFS9_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42712514UL)) +#define bFM4_MFS9_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42712518UL)) +#define bFM4_MFS9_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271251CUL)) +#define bFM4_MFS9_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42712520UL)) +#define bFM4_MFS9_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42712524UL)) +#define bFM4_MFS9_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42712528UL)) +#define bFM4_MFS9_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271252CUL)) +#define bFM4_MFS9_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42712530UL)) +#define bFM4_MFS9_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42712534UL)) +#define bFM4_MFS9_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42712538UL)) +#define bFM4_MFS9_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271253CUL)) +#define bFM4_MFS9_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42712580UL)) +#define bFM4_MFS9_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42712584UL)) +#define bFM4_MFS9_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42712588UL)) +#define bFM4_MFS9_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271258CUL)) +#define bFM4_MFS9_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42712590UL)) +#define bFM4_MFS9_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42712594UL)) +#define bFM4_MFS9_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42712598UL)) +#define bFM4_MFS9_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271259CUL)) +#define bFM4_MFS9_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427125A0UL)) +#define bFM4_MFS9_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427125A4UL)) +#define bFM4_MFS9_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427125A8UL)) +#define bFM4_MFS9_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427125ACUL)) +#define bFM4_MFS9_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427125B0UL)) +#define bFM4_MFS9_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427125B4UL)) +#define bFM4_MFS9_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427125B8UL)) +#define bFM4_MFS9_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427125BCUL)) +#define bFM4_MFS9_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42712600UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42712604UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42712614UL)) +#define bFM4_MFS9_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42712618UL)) +#define bFM4_MFS9_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271261CUL)) +#define bFM4_MFS9_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42712620UL)) +#define bFM4_MFS9_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42712624UL)) + +/* MFS LIN channel 9 registers */ +#define bFM4_MFS9_LIN_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) +#define bFM4_MFS9_LIN_SMR_SBL *((volatile unsigned int*)(0x4271200CUL)) +#define bFM4_MFS9_LIN_SMR_WUCR *((volatile unsigned int*)(0x42712010UL)) +#define bFM4_MFS9_LIN_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) +#define bFM4_MFS9_LIN_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) +#define bFM4_MFS9_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) +#define bFM4_MFS9_LIN_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) +#define bFM4_MFS9_LIN_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) +#define bFM4_MFS9_LIN_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) +#define bFM4_MFS9_LIN_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) +#define bFM4_MFS9_LIN_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) +#define bFM4_MFS9_LIN_SCR_LBR *((volatile unsigned int*)(0x42712034UL)) +#define bFM4_MFS9_LIN_SCR_MS *((volatile unsigned int*)(0x42712038UL)) +#define bFM4_MFS9_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) +#define bFM4_MFS9_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42712080UL)) +#define bFM4_MFS9_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42712084UL)) +#define bFM4_MFS9_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42712088UL)) +#define bFM4_MFS9_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271208CUL)) +#define bFM4_MFS9_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42712090UL)) +#define bFM4_MFS9_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42712098UL)) +#define bFM4_MFS9_LIN_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) +#define bFM4_MFS9_LIN_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) +#define bFM4_MFS9_LIN_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) +#define bFM4_MFS9_LIN_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) +#define bFM4_MFS9_LIN_SSR_FRE *((volatile unsigned int*)(0x427120B0UL)) +#define bFM4_MFS9_LIN_SSR_LBD *((volatile unsigned int*)(0x427120B4UL)) +#define bFM4_MFS9_LIN_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) +#define bFM4_MFS9_LIN_BGR_EXT *((volatile unsigned int*)(0x427121BCUL)) +#define bFM4_MFS9_LIN_BGR1_EXT *((volatile unsigned int*)(0x427121BCUL)) +#define bFM4_MFS9_LIN_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_LIN_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_LIN_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_LIN_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_LIN_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_LIN_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_LIN_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_LIN_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_LIN_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_LIN_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) +#define bFM4_MFS9_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) + +/* MFS I2C channel 9 registers */ +#define bFM4_MFS9_I2C_SMR_TIE *((volatile unsigned int*)(0x42712008UL)) +#define bFM4_MFS9_I2C_SMR_RIE *((volatile unsigned int*)(0x4271200CUL)) +#define bFM4_MFS9_I2C_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) +#define bFM4_MFS9_I2C_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) +#define bFM4_MFS9_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) +#define bFM4_MFS9_I2C_IBCR_INT *((volatile unsigned int*)(0x42712020UL)) +#define bFM4_MFS9_I2C_IBCR_BER *((volatile unsigned int*)(0x42712024UL)) +#define bFM4_MFS9_I2C_IBCR_INTE *((volatile unsigned int*)(0x42712028UL)) +#define bFM4_MFS9_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271202CUL)) +#define bFM4_MFS9_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42712030UL)) +#define bFM4_MFS9_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42712034UL)) +#define bFM4_MFS9_I2C_IBCR_ACT *((volatile unsigned int*)(0x42712038UL)) +#define bFM4_MFS9_I2C_IBCR_SCC *((volatile unsigned int*)(0x42712038UL)) +#define bFM4_MFS9_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271203CUL)) +#define bFM4_MFS9_I2C_IBSR_BB *((volatile unsigned int*)(0x42712080UL)) +#define bFM4_MFS9_I2C_IBSR_SPC *((volatile unsigned int*)(0x42712084UL)) +#define bFM4_MFS9_I2C_IBSR_RSC *((volatile unsigned int*)(0x42712088UL)) +#define bFM4_MFS9_I2C_IBSR_AL *((volatile unsigned int*)(0x4271208CUL)) +#define bFM4_MFS9_I2C_IBSR_TRX *((volatile unsigned int*)(0x42712090UL)) +#define bFM4_MFS9_I2C_IBSR_RSA *((volatile unsigned int*)(0x42712094UL)) +#define bFM4_MFS9_I2C_IBSR_RACK *((volatile unsigned int*)(0x42712098UL)) +#define bFM4_MFS9_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271209CUL)) +#define bFM4_MFS9_I2C_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) +#define bFM4_MFS9_I2C_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) +#define bFM4_MFS9_I2C_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) +#define bFM4_MFS9_I2C_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) +#define bFM4_MFS9_I2C_SSR_TBIE *((volatile unsigned int*)(0x427120B0UL)) +#define bFM4_MFS9_I2C_SSR_DMA *((volatile unsigned int*)(0x427120B4UL)) +#define bFM4_MFS9_I2C_SSR_TSET *((volatile unsigned int*)(0x427120B8UL)) +#define bFM4_MFS9_I2C_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) +#define bFM4_MFS9_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42712200UL)) +#define bFM4_MFS9_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42712204UL)) +#define bFM4_MFS9_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42712208UL)) +#define bFM4_MFS9_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271220CUL)) +#define bFM4_MFS9_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42712210UL)) +#define bFM4_MFS9_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42712214UL)) +#define bFM4_MFS9_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42712218UL)) +#define bFM4_MFS9_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271221CUL)) +#define bFM4_MFS9_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42712220UL)) +#define bFM4_MFS9_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42712224UL)) +#define bFM4_MFS9_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42712228UL)) +#define bFM4_MFS9_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271222CUL)) +#define bFM4_MFS9_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42712230UL)) +#define bFM4_MFS9_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42712234UL)) +#define bFM4_MFS9_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42712238UL)) +#define bFM4_MFS9_I2C_ISMK_EN *((volatile unsigned int*)(0x4271223CUL)) +#define bFM4_MFS9_I2C_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_I2C_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_I2C_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_I2C_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_I2C_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_I2C_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_I2C_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) +#define bFM4_MFS9_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) +#define bFM4_MFS9_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) +#define bFM4_MFS9_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) +#define bFM4_MFS9_I2C_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) +#define bFM4_MFS9_I2C_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) +#define bFM4_MFS9_I2C_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) +#define bFM4_MFS9_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) +#define bFM4_MFS9_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) +#define bFM4_MFS9_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) +#define bFM4_MFS9_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) +#define bFM4_MFS9_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) +#define bFM4_MFS9_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) +#define bFM4_MFS9_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) +#define bFM4_MFS9_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) +#define bFM4_MFS9_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) +#define bFM4_MFS9_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) +#define bFM4_MFS9_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) +#define bFM4_MFS9_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) + +/* MFS UART channel 10 registers */ +#define bFM4_MFS10_UART_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) +#define bFM4_MFS10_UART_SMR_BDS *((volatile unsigned int*)(0x42714008UL)) +#define bFM4_MFS10_UART_SMR_SBL *((volatile unsigned int*)(0x4271400CUL)) +#define bFM4_MFS10_UART_SMR_WUCR *((volatile unsigned int*)(0x42714010UL)) +#define bFM4_MFS10_UART_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) +#define bFM4_MFS10_UART_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) +#define bFM4_MFS10_UART_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) +#define bFM4_MFS10_UART_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) +#define bFM4_MFS10_UART_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) +#define bFM4_MFS10_UART_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) +#define bFM4_MFS10_UART_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) +#define bFM4_MFS10_UART_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) +#define bFM4_MFS10_UART_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) +#define bFM4_MFS10_UART_ESCR_L0 *((volatile unsigned int*)(0x42714080UL)) +#define bFM4_MFS10_UART_ESCR_L1 *((volatile unsigned int*)(0x42714084UL)) +#define bFM4_MFS10_UART_ESCR_L2 *((volatile unsigned int*)(0x42714088UL)) +#define bFM4_MFS10_UART_ESCR_P *((volatile unsigned int*)(0x4271408CUL)) +#define bFM4_MFS10_UART_ESCR_PEN *((volatile unsigned int*)(0x42714090UL)) +#define bFM4_MFS10_UART_ESCR_INV *((volatile unsigned int*)(0x42714094UL)) +#define bFM4_MFS10_UART_ESCR_ESBL *((volatile unsigned int*)(0x42714098UL)) +#define bFM4_MFS10_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271409CUL)) +#define bFM4_MFS10_UART_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) +#define bFM4_MFS10_UART_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) +#define bFM4_MFS10_UART_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) +#define bFM4_MFS10_UART_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) +#define bFM4_MFS10_UART_SSR_FRE *((volatile unsigned int*)(0x427140B0UL)) +#define bFM4_MFS10_UART_SSR_PE *((volatile unsigned int*)(0x427140B4UL)) +#define bFM4_MFS10_UART_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) +#define bFM4_MFS10_UART_RDR_AD *((volatile unsigned int*)(0x42714120UL)) +#define bFM4_MFS10_UART_TDR_AD *((volatile unsigned int*)(0x42714120UL)) +#define bFM4_MFS10_UART_BGR_EXT *((volatile unsigned int*)(0x427141BCUL)) +#define bFM4_MFS10_UART_BGR1_EXT *((volatile unsigned int*)(0x427141BCUL)) +#define bFM4_MFS10_UART_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_UART_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_UART_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_UART_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_UART_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_UART_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_UART_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_UART_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_UART_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_UART_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_UART_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_UART_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_UART_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_UART_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_UART_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_UART_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_UART_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_UART_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) +#define bFM4_MFS10_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) + +/* MFS CSIO channel 10 registers */ +#define bFM4_MFS10_CSIO_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) +#define bFM4_MFS10_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42714004UL)) +#define bFM4_MFS10_CSIO_SMR_BDS *((volatile unsigned int*)(0x42714008UL)) +#define bFM4_MFS10_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271400CUL)) +#define bFM4_MFS10_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) +#define bFM4_MFS10_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) +#define bFM4_MFS10_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) +#define bFM4_MFS10_CSIO_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) +#define bFM4_MFS10_CSIO_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) +#define bFM4_MFS10_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) +#define bFM4_MFS10_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) +#define bFM4_MFS10_CSIO_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) +#define bFM4_MFS10_CSIO_SCR_SPI *((volatile unsigned int*)(0x42714034UL)) +#define bFM4_MFS10_CSIO_SCR_MS *((volatile unsigned int*)(0x42714038UL)) +#define bFM4_MFS10_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) +#define bFM4_MFS10_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42714080UL)) +#define bFM4_MFS10_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42714084UL)) +#define bFM4_MFS10_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42714088UL)) +#define bFM4_MFS10_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271408CUL)) +#define bFM4_MFS10_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42714090UL)) +#define bFM4_MFS10_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42714098UL)) +#define bFM4_MFS10_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271409CUL)) +#define bFM4_MFS10_CSIO_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) +#define bFM4_MFS10_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) +#define bFM4_MFS10_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) +#define bFM4_MFS10_CSIO_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) +#define bFM4_MFS10_CSIO_SSR_AWC *((volatile unsigned int*)(0x427140B0UL)) +#define bFM4_MFS10_CSIO_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) +#define bFM4_MFS10_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_CSIO_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_CSIO_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_CSIO_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42714380UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42714384UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42714388UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271438CUL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42714390UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42714394UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42714398UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271439CUL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427143A0UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427143A4UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427143A8UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427143ACUL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427143B0UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427143B4UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427143B8UL)) +#define bFM4_MFS10_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427143BCUL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42714400UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42714404UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42714408UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271440CUL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42714410UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42714414UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42714418UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271441CUL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42714420UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42714424UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42714428UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271442CUL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42714430UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42714434UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42714438UL)) +#define bFM4_MFS10_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271443CUL)) +#define bFM4_MFS10_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42714480UL)) +#define bFM4_MFS10_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42714484UL)) +#define bFM4_MFS10_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42714488UL)) +#define bFM4_MFS10_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271448CUL)) +#define bFM4_MFS10_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42714490UL)) +#define bFM4_MFS10_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42714498UL)) +#define bFM4_MFS10_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271449CUL)) +#define bFM4_MFS10_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427144A0UL)) +#define bFM4_MFS10_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427144ACUL)) +#define bFM4_MFS10_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427144B0UL)) +#define bFM4_MFS10_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427144B4UL)) +#define bFM4_MFS10_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42714500UL)) +#define bFM4_MFS10_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42714504UL)) +#define bFM4_MFS10_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42714508UL)) +#define bFM4_MFS10_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271450CUL)) +#define bFM4_MFS10_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42714510UL)) +#define bFM4_MFS10_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42714514UL)) +#define bFM4_MFS10_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42714518UL)) +#define bFM4_MFS10_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271451CUL)) +#define bFM4_MFS10_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42714520UL)) +#define bFM4_MFS10_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42714524UL)) +#define bFM4_MFS10_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42714528UL)) +#define bFM4_MFS10_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271452CUL)) +#define bFM4_MFS10_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42714530UL)) +#define bFM4_MFS10_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42714534UL)) +#define bFM4_MFS10_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42714538UL)) +#define bFM4_MFS10_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271453CUL)) +#define bFM4_MFS10_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42714580UL)) +#define bFM4_MFS10_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42714584UL)) +#define bFM4_MFS10_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42714588UL)) +#define bFM4_MFS10_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271458CUL)) +#define bFM4_MFS10_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42714590UL)) +#define bFM4_MFS10_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42714594UL)) +#define bFM4_MFS10_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42714598UL)) +#define bFM4_MFS10_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271459CUL)) +#define bFM4_MFS10_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427145A0UL)) +#define bFM4_MFS10_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427145A4UL)) +#define bFM4_MFS10_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427145A8UL)) +#define bFM4_MFS10_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427145ACUL)) +#define bFM4_MFS10_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427145B0UL)) +#define bFM4_MFS10_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427145B4UL)) +#define bFM4_MFS10_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427145B8UL)) +#define bFM4_MFS10_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427145BCUL)) +#define bFM4_MFS10_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42714600UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42714604UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42714614UL)) +#define bFM4_MFS10_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42714618UL)) +#define bFM4_MFS10_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271461CUL)) +#define bFM4_MFS10_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42714620UL)) +#define bFM4_MFS10_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42714624UL)) + +/* MFS LIN channel 10 registers */ +#define bFM4_MFS10_LIN_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) +#define bFM4_MFS10_LIN_SMR_SBL *((volatile unsigned int*)(0x4271400CUL)) +#define bFM4_MFS10_LIN_SMR_WUCR *((volatile unsigned int*)(0x42714010UL)) +#define bFM4_MFS10_LIN_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) +#define bFM4_MFS10_LIN_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) +#define bFM4_MFS10_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) +#define bFM4_MFS10_LIN_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) +#define bFM4_MFS10_LIN_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) +#define bFM4_MFS10_LIN_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) +#define bFM4_MFS10_LIN_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) +#define bFM4_MFS10_LIN_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) +#define bFM4_MFS10_LIN_SCR_LBR *((volatile unsigned int*)(0x42714034UL)) +#define bFM4_MFS10_LIN_SCR_MS *((volatile unsigned int*)(0x42714038UL)) +#define bFM4_MFS10_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) +#define bFM4_MFS10_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42714080UL)) +#define bFM4_MFS10_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42714084UL)) +#define bFM4_MFS10_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42714088UL)) +#define bFM4_MFS10_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271408CUL)) +#define bFM4_MFS10_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42714090UL)) +#define bFM4_MFS10_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42714098UL)) +#define bFM4_MFS10_LIN_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) +#define bFM4_MFS10_LIN_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) +#define bFM4_MFS10_LIN_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) +#define bFM4_MFS10_LIN_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) +#define bFM4_MFS10_LIN_SSR_FRE *((volatile unsigned int*)(0x427140B0UL)) +#define bFM4_MFS10_LIN_SSR_LBD *((volatile unsigned int*)(0x427140B4UL)) +#define bFM4_MFS10_LIN_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) +#define bFM4_MFS10_LIN_BGR_EXT *((volatile unsigned int*)(0x427141BCUL)) +#define bFM4_MFS10_LIN_BGR1_EXT *((volatile unsigned int*)(0x427141BCUL)) +#define bFM4_MFS10_LIN_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_LIN_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_LIN_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_LIN_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_LIN_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_LIN_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_LIN_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_LIN_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_LIN_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_LIN_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) +#define bFM4_MFS10_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) + +/* MFS I2C channel 10 registers */ +#define bFM4_MFS10_I2C_SMR_TIE *((volatile unsigned int*)(0x42714008UL)) +#define bFM4_MFS10_I2C_SMR_RIE *((volatile unsigned int*)(0x4271400CUL)) +#define bFM4_MFS10_I2C_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) +#define bFM4_MFS10_I2C_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) +#define bFM4_MFS10_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) +#define bFM4_MFS10_I2C_IBCR_INT *((volatile unsigned int*)(0x42714020UL)) +#define bFM4_MFS10_I2C_IBCR_BER *((volatile unsigned int*)(0x42714024UL)) +#define bFM4_MFS10_I2C_IBCR_INTE *((volatile unsigned int*)(0x42714028UL)) +#define bFM4_MFS10_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271402CUL)) +#define bFM4_MFS10_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42714030UL)) +#define bFM4_MFS10_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42714034UL)) +#define bFM4_MFS10_I2C_IBCR_ACT *((volatile unsigned int*)(0x42714038UL)) +#define bFM4_MFS10_I2C_IBCR_SCC *((volatile unsigned int*)(0x42714038UL)) +#define bFM4_MFS10_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271403CUL)) +#define bFM4_MFS10_I2C_IBSR_BB *((volatile unsigned int*)(0x42714080UL)) +#define bFM4_MFS10_I2C_IBSR_SPC *((volatile unsigned int*)(0x42714084UL)) +#define bFM4_MFS10_I2C_IBSR_RSC *((volatile unsigned int*)(0x42714088UL)) +#define bFM4_MFS10_I2C_IBSR_AL *((volatile unsigned int*)(0x4271408CUL)) +#define bFM4_MFS10_I2C_IBSR_TRX *((volatile unsigned int*)(0x42714090UL)) +#define bFM4_MFS10_I2C_IBSR_RSA *((volatile unsigned int*)(0x42714094UL)) +#define bFM4_MFS10_I2C_IBSR_RACK *((volatile unsigned int*)(0x42714098UL)) +#define bFM4_MFS10_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271409CUL)) +#define bFM4_MFS10_I2C_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) +#define bFM4_MFS10_I2C_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) +#define bFM4_MFS10_I2C_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) +#define bFM4_MFS10_I2C_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) +#define bFM4_MFS10_I2C_SSR_TBIE *((volatile unsigned int*)(0x427140B0UL)) +#define bFM4_MFS10_I2C_SSR_DMA *((volatile unsigned int*)(0x427140B4UL)) +#define bFM4_MFS10_I2C_SSR_TSET *((volatile unsigned int*)(0x427140B8UL)) +#define bFM4_MFS10_I2C_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) +#define bFM4_MFS10_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42714200UL)) +#define bFM4_MFS10_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42714204UL)) +#define bFM4_MFS10_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42714208UL)) +#define bFM4_MFS10_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271420CUL)) +#define bFM4_MFS10_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42714210UL)) +#define bFM4_MFS10_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42714214UL)) +#define bFM4_MFS10_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42714218UL)) +#define bFM4_MFS10_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271421CUL)) +#define bFM4_MFS10_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42714220UL)) +#define bFM4_MFS10_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42714224UL)) +#define bFM4_MFS10_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42714228UL)) +#define bFM4_MFS10_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271422CUL)) +#define bFM4_MFS10_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42714230UL)) +#define bFM4_MFS10_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42714234UL)) +#define bFM4_MFS10_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42714238UL)) +#define bFM4_MFS10_I2C_ISMK_EN *((volatile unsigned int*)(0x4271423CUL)) +#define bFM4_MFS10_I2C_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_I2C_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_I2C_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_I2C_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_I2C_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_I2C_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_I2C_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) +#define bFM4_MFS10_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) +#define bFM4_MFS10_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) +#define bFM4_MFS10_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) +#define bFM4_MFS10_I2C_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) +#define bFM4_MFS10_I2C_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) +#define bFM4_MFS10_I2C_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) +#define bFM4_MFS10_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) +#define bFM4_MFS10_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) +#define bFM4_MFS10_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) +#define bFM4_MFS10_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) +#define bFM4_MFS10_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) +#define bFM4_MFS10_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) +#define bFM4_MFS10_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) +#define bFM4_MFS10_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) +#define bFM4_MFS10_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) +#define bFM4_MFS10_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) +#define bFM4_MFS10_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) +#define bFM4_MFS10_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) + +/* MFS UART channel 11 registers */ +#define bFM4_MFS11_UART_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) +#define bFM4_MFS11_UART_SMR_BDS *((volatile unsigned int*)(0x42716008UL)) +#define bFM4_MFS11_UART_SMR_SBL *((volatile unsigned int*)(0x4271600CUL)) +#define bFM4_MFS11_UART_SMR_WUCR *((volatile unsigned int*)(0x42716010UL)) +#define bFM4_MFS11_UART_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) +#define bFM4_MFS11_UART_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) +#define bFM4_MFS11_UART_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) +#define bFM4_MFS11_UART_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) +#define bFM4_MFS11_UART_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) +#define bFM4_MFS11_UART_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) +#define bFM4_MFS11_UART_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) +#define bFM4_MFS11_UART_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) +#define bFM4_MFS11_UART_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) +#define bFM4_MFS11_UART_ESCR_L0 *((volatile unsigned int*)(0x42716080UL)) +#define bFM4_MFS11_UART_ESCR_L1 *((volatile unsigned int*)(0x42716084UL)) +#define bFM4_MFS11_UART_ESCR_L2 *((volatile unsigned int*)(0x42716088UL)) +#define bFM4_MFS11_UART_ESCR_P *((volatile unsigned int*)(0x4271608CUL)) +#define bFM4_MFS11_UART_ESCR_PEN *((volatile unsigned int*)(0x42716090UL)) +#define bFM4_MFS11_UART_ESCR_INV *((volatile unsigned int*)(0x42716094UL)) +#define bFM4_MFS11_UART_ESCR_ESBL *((volatile unsigned int*)(0x42716098UL)) +#define bFM4_MFS11_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271609CUL)) +#define bFM4_MFS11_UART_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) +#define bFM4_MFS11_UART_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) +#define bFM4_MFS11_UART_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) +#define bFM4_MFS11_UART_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) +#define bFM4_MFS11_UART_SSR_FRE *((volatile unsigned int*)(0x427160B0UL)) +#define bFM4_MFS11_UART_SSR_PE *((volatile unsigned int*)(0x427160B4UL)) +#define bFM4_MFS11_UART_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) +#define bFM4_MFS11_UART_RDR_AD *((volatile unsigned int*)(0x42716120UL)) +#define bFM4_MFS11_UART_TDR_AD *((volatile unsigned int*)(0x42716120UL)) +#define bFM4_MFS11_UART_BGR_EXT *((volatile unsigned int*)(0x427161BCUL)) +#define bFM4_MFS11_UART_BGR1_EXT *((volatile unsigned int*)(0x427161BCUL)) +#define bFM4_MFS11_UART_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_UART_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_UART_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_UART_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_UART_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_UART_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_UART_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_UART_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_UART_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_UART_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_UART_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_UART_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_UART_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_UART_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_UART_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_UART_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_UART_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_UART_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) +#define bFM4_MFS11_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) + +/* MFS CSIO channel 11 registers */ +#define bFM4_MFS11_CSIO_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) +#define bFM4_MFS11_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42716004UL)) +#define bFM4_MFS11_CSIO_SMR_BDS *((volatile unsigned int*)(0x42716008UL)) +#define bFM4_MFS11_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271600CUL)) +#define bFM4_MFS11_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) +#define bFM4_MFS11_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) +#define bFM4_MFS11_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) +#define bFM4_MFS11_CSIO_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) +#define bFM4_MFS11_CSIO_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) +#define bFM4_MFS11_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) +#define bFM4_MFS11_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) +#define bFM4_MFS11_CSIO_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) +#define bFM4_MFS11_CSIO_SCR_SPI *((volatile unsigned int*)(0x42716034UL)) +#define bFM4_MFS11_CSIO_SCR_MS *((volatile unsigned int*)(0x42716038UL)) +#define bFM4_MFS11_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) +#define bFM4_MFS11_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42716080UL)) +#define bFM4_MFS11_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42716084UL)) +#define bFM4_MFS11_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42716088UL)) +#define bFM4_MFS11_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271608CUL)) +#define bFM4_MFS11_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42716090UL)) +#define bFM4_MFS11_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42716098UL)) +#define bFM4_MFS11_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271609CUL)) +#define bFM4_MFS11_CSIO_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) +#define bFM4_MFS11_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) +#define bFM4_MFS11_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) +#define bFM4_MFS11_CSIO_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) +#define bFM4_MFS11_CSIO_SSR_AWC *((volatile unsigned int*)(0x427160B0UL)) +#define bFM4_MFS11_CSIO_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) +#define bFM4_MFS11_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_CSIO_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_CSIO_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_CSIO_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42716380UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42716384UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42716388UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271638CUL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42716390UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42716394UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42716398UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271639CUL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427163A0UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427163A4UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427163A8UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427163ACUL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427163B0UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427163B4UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427163B8UL)) +#define bFM4_MFS11_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427163BCUL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42716400UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42716404UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42716408UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271640CUL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42716410UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42716414UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42716418UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271641CUL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42716420UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42716424UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42716428UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271642CUL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42716430UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42716434UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42716438UL)) +#define bFM4_MFS11_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271643CUL)) +#define bFM4_MFS11_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42716480UL)) +#define bFM4_MFS11_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42716484UL)) +#define bFM4_MFS11_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42716488UL)) +#define bFM4_MFS11_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271648CUL)) +#define bFM4_MFS11_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42716490UL)) +#define bFM4_MFS11_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42716498UL)) +#define bFM4_MFS11_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271649CUL)) +#define bFM4_MFS11_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427164A0UL)) +#define bFM4_MFS11_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427164ACUL)) +#define bFM4_MFS11_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427164B0UL)) +#define bFM4_MFS11_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427164B4UL)) +#define bFM4_MFS11_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42716500UL)) +#define bFM4_MFS11_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42716504UL)) +#define bFM4_MFS11_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42716508UL)) +#define bFM4_MFS11_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271650CUL)) +#define bFM4_MFS11_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42716510UL)) +#define bFM4_MFS11_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42716514UL)) +#define bFM4_MFS11_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42716518UL)) +#define bFM4_MFS11_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271651CUL)) +#define bFM4_MFS11_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42716520UL)) +#define bFM4_MFS11_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42716524UL)) +#define bFM4_MFS11_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42716528UL)) +#define bFM4_MFS11_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271652CUL)) +#define bFM4_MFS11_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42716530UL)) +#define bFM4_MFS11_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42716534UL)) +#define bFM4_MFS11_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42716538UL)) +#define bFM4_MFS11_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271653CUL)) +#define bFM4_MFS11_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42716580UL)) +#define bFM4_MFS11_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42716584UL)) +#define bFM4_MFS11_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42716588UL)) +#define bFM4_MFS11_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271658CUL)) +#define bFM4_MFS11_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42716590UL)) +#define bFM4_MFS11_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42716594UL)) +#define bFM4_MFS11_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42716598UL)) +#define bFM4_MFS11_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271659CUL)) +#define bFM4_MFS11_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427165A0UL)) +#define bFM4_MFS11_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427165A4UL)) +#define bFM4_MFS11_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427165A8UL)) +#define bFM4_MFS11_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427165ACUL)) +#define bFM4_MFS11_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427165B0UL)) +#define bFM4_MFS11_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427165B4UL)) +#define bFM4_MFS11_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427165B8UL)) +#define bFM4_MFS11_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427165BCUL)) +#define bFM4_MFS11_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42716600UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42716604UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42716614UL)) +#define bFM4_MFS11_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42716618UL)) +#define bFM4_MFS11_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271661CUL)) +#define bFM4_MFS11_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42716620UL)) +#define bFM4_MFS11_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42716624UL)) + +/* MFS LIN channel 11 registers */ +#define bFM4_MFS11_LIN_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) +#define bFM4_MFS11_LIN_SMR_SBL *((volatile unsigned int*)(0x4271600CUL)) +#define bFM4_MFS11_LIN_SMR_WUCR *((volatile unsigned int*)(0x42716010UL)) +#define bFM4_MFS11_LIN_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) +#define bFM4_MFS11_LIN_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) +#define bFM4_MFS11_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) +#define bFM4_MFS11_LIN_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) +#define bFM4_MFS11_LIN_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) +#define bFM4_MFS11_LIN_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) +#define bFM4_MFS11_LIN_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) +#define bFM4_MFS11_LIN_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) +#define bFM4_MFS11_LIN_SCR_LBR *((volatile unsigned int*)(0x42716034UL)) +#define bFM4_MFS11_LIN_SCR_MS *((volatile unsigned int*)(0x42716038UL)) +#define bFM4_MFS11_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) +#define bFM4_MFS11_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42716080UL)) +#define bFM4_MFS11_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42716084UL)) +#define bFM4_MFS11_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42716088UL)) +#define bFM4_MFS11_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271608CUL)) +#define bFM4_MFS11_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42716090UL)) +#define bFM4_MFS11_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42716098UL)) +#define bFM4_MFS11_LIN_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) +#define bFM4_MFS11_LIN_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) +#define bFM4_MFS11_LIN_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) +#define bFM4_MFS11_LIN_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) +#define bFM4_MFS11_LIN_SSR_FRE *((volatile unsigned int*)(0x427160B0UL)) +#define bFM4_MFS11_LIN_SSR_LBD *((volatile unsigned int*)(0x427160B4UL)) +#define bFM4_MFS11_LIN_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) +#define bFM4_MFS11_LIN_BGR_EXT *((volatile unsigned int*)(0x427161BCUL)) +#define bFM4_MFS11_LIN_BGR1_EXT *((volatile unsigned int*)(0x427161BCUL)) +#define bFM4_MFS11_LIN_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_LIN_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_LIN_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_LIN_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_LIN_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_LIN_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_LIN_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_LIN_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_LIN_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_LIN_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) +#define bFM4_MFS11_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) + +/* MFS I2C channel 11 registers */ +#define bFM4_MFS11_I2C_SMR_TIE *((volatile unsigned int*)(0x42716008UL)) +#define bFM4_MFS11_I2C_SMR_RIE *((volatile unsigned int*)(0x4271600CUL)) +#define bFM4_MFS11_I2C_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) +#define bFM4_MFS11_I2C_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) +#define bFM4_MFS11_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) +#define bFM4_MFS11_I2C_IBCR_INT *((volatile unsigned int*)(0x42716020UL)) +#define bFM4_MFS11_I2C_IBCR_BER *((volatile unsigned int*)(0x42716024UL)) +#define bFM4_MFS11_I2C_IBCR_INTE *((volatile unsigned int*)(0x42716028UL)) +#define bFM4_MFS11_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271602CUL)) +#define bFM4_MFS11_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42716030UL)) +#define bFM4_MFS11_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42716034UL)) +#define bFM4_MFS11_I2C_IBCR_ACT *((volatile unsigned int*)(0x42716038UL)) +#define bFM4_MFS11_I2C_IBCR_SCC *((volatile unsigned int*)(0x42716038UL)) +#define bFM4_MFS11_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271603CUL)) +#define bFM4_MFS11_I2C_IBSR_BB *((volatile unsigned int*)(0x42716080UL)) +#define bFM4_MFS11_I2C_IBSR_SPC *((volatile unsigned int*)(0x42716084UL)) +#define bFM4_MFS11_I2C_IBSR_RSC *((volatile unsigned int*)(0x42716088UL)) +#define bFM4_MFS11_I2C_IBSR_AL *((volatile unsigned int*)(0x4271608CUL)) +#define bFM4_MFS11_I2C_IBSR_TRX *((volatile unsigned int*)(0x42716090UL)) +#define bFM4_MFS11_I2C_IBSR_RSA *((volatile unsigned int*)(0x42716094UL)) +#define bFM4_MFS11_I2C_IBSR_RACK *((volatile unsigned int*)(0x42716098UL)) +#define bFM4_MFS11_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271609CUL)) +#define bFM4_MFS11_I2C_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) +#define bFM4_MFS11_I2C_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) +#define bFM4_MFS11_I2C_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) +#define bFM4_MFS11_I2C_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) +#define bFM4_MFS11_I2C_SSR_TBIE *((volatile unsigned int*)(0x427160B0UL)) +#define bFM4_MFS11_I2C_SSR_DMA *((volatile unsigned int*)(0x427160B4UL)) +#define bFM4_MFS11_I2C_SSR_TSET *((volatile unsigned int*)(0x427160B8UL)) +#define bFM4_MFS11_I2C_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) +#define bFM4_MFS11_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42716200UL)) +#define bFM4_MFS11_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42716204UL)) +#define bFM4_MFS11_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42716208UL)) +#define bFM4_MFS11_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271620CUL)) +#define bFM4_MFS11_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42716210UL)) +#define bFM4_MFS11_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42716214UL)) +#define bFM4_MFS11_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42716218UL)) +#define bFM4_MFS11_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271621CUL)) +#define bFM4_MFS11_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42716220UL)) +#define bFM4_MFS11_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42716224UL)) +#define bFM4_MFS11_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42716228UL)) +#define bFM4_MFS11_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271622CUL)) +#define bFM4_MFS11_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42716230UL)) +#define bFM4_MFS11_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42716234UL)) +#define bFM4_MFS11_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42716238UL)) +#define bFM4_MFS11_I2C_ISMK_EN *((volatile unsigned int*)(0x4271623CUL)) +#define bFM4_MFS11_I2C_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_I2C_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_I2C_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_I2C_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_I2C_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_I2C_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_I2C_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) +#define bFM4_MFS11_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) +#define bFM4_MFS11_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) +#define bFM4_MFS11_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) +#define bFM4_MFS11_I2C_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) +#define bFM4_MFS11_I2C_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) +#define bFM4_MFS11_I2C_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) +#define bFM4_MFS11_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) +#define bFM4_MFS11_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) +#define bFM4_MFS11_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) +#define bFM4_MFS11_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) +#define bFM4_MFS11_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) +#define bFM4_MFS11_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) +#define bFM4_MFS11_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) +#define bFM4_MFS11_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) +#define bFM4_MFS11_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) +#define bFM4_MFS11_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) +#define bFM4_MFS11_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) +#define bFM4_MFS11_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) + +/* MFS UART channel 12 registers */ +#define bFM4_MFS12_UART_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) +#define bFM4_MFS12_UART_SMR_BDS *((volatile unsigned int*)(0x42718008UL)) +#define bFM4_MFS12_UART_SMR_SBL *((volatile unsigned int*)(0x4271800CUL)) +#define bFM4_MFS12_UART_SMR_WUCR *((volatile unsigned int*)(0x42718010UL)) +#define bFM4_MFS12_UART_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) +#define bFM4_MFS12_UART_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) +#define bFM4_MFS12_UART_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) +#define bFM4_MFS12_UART_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) +#define bFM4_MFS12_UART_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) +#define bFM4_MFS12_UART_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) +#define bFM4_MFS12_UART_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) +#define bFM4_MFS12_UART_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) +#define bFM4_MFS12_UART_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) +#define bFM4_MFS12_UART_ESCR_L0 *((volatile unsigned int*)(0x42718080UL)) +#define bFM4_MFS12_UART_ESCR_L1 *((volatile unsigned int*)(0x42718084UL)) +#define bFM4_MFS12_UART_ESCR_L2 *((volatile unsigned int*)(0x42718088UL)) +#define bFM4_MFS12_UART_ESCR_P *((volatile unsigned int*)(0x4271808CUL)) +#define bFM4_MFS12_UART_ESCR_PEN *((volatile unsigned int*)(0x42718090UL)) +#define bFM4_MFS12_UART_ESCR_INV *((volatile unsigned int*)(0x42718094UL)) +#define bFM4_MFS12_UART_ESCR_ESBL *((volatile unsigned int*)(0x42718098UL)) +#define bFM4_MFS12_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271809CUL)) +#define bFM4_MFS12_UART_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) +#define bFM4_MFS12_UART_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) +#define bFM4_MFS12_UART_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) +#define bFM4_MFS12_UART_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) +#define bFM4_MFS12_UART_SSR_FRE *((volatile unsigned int*)(0x427180B0UL)) +#define bFM4_MFS12_UART_SSR_PE *((volatile unsigned int*)(0x427180B4UL)) +#define bFM4_MFS12_UART_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) +#define bFM4_MFS12_UART_RDR_AD *((volatile unsigned int*)(0x42718120UL)) +#define bFM4_MFS12_UART_TDR_AD *((volatile unsigned int*)(0x42718120UL)) +#define bFM4_MFS12_UART_BGR_EXT *((volatile unsigned int*)(0x427181BCUL)) +#define bFM4_MFS12_UART_BGR1_EXT *((volatile unsigned int*)(0x427181BCUL)) +#define bFM4_MFS12_UART_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_UART_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_UART_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_UART_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_UART_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_UART_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_UART_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_UART_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_UART_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_UART_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_UART_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_UART_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_UART_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_UART_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_UART_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_UART_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_UART_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_UART_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) +#define bFM4_MFS12_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) + +/* MFS CSIO channel 12 registers */ +#define bFM4_MFS12_CSIO_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) +#define bFM4_MFS12_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42718004UL)) +#define bFM4_MFS12_CSIO_SMR_BDS *((volatile unsigned int*)(0x42718008UL)) +#define bFM4_MFS12_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271800CUL)) +#define bFM4_MFS12_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) +#define bFM4_MFS12_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) +#define bFM4_MFS12_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) +#define bFM4_MFS12_CSIO_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) +#define bFM4_MFS12_CSIO_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) +#define bFM4_MFS12_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) +#define bFM4_MFS12_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) +#define bFM4_MFS12_CSIO_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) +#define bFM4_MFS12_CSIO_SCR_SPI *((volatile unsigned int*)(0x42718034UL)) +#define bFM4_MFS12_CSIO_SCR_MS *((volatile unsigned int*)(0x42718038UL)) +#define bFM4_MFS12_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) +#define bFM4_MFS12_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42718080UL)) +#define bFM4_MFS12_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42718084UL)) +#define bFM4_MFS12_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42718088UL)) +#define bFM4_MFS12_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271808CUL)) +#define bFM4_MFS12_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42718090UL)) +#define bFM4_MFS12_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42718098UL)) +#define bFM4_MFS12_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271809CUL)) +#define bFM4_MFS12_CSIO_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) +#define bFM4_MFS12_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) +#define bFM4_MFS12_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) +#define bFM4_MFS12_CSIO_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) +#define bFM4_MFS12_CSIO_SSR_AWC *((volatile unsigned int*)(0x427180B0UL)) +#define bFM4_MFS12_CSIO_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) +#define bFM4_MFS12_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_CSIO_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_CSIO_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_CSIO_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42718380UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42718384UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42718388UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271838CUL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42718390UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42718394UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42718398UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271839CUL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427183A0UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427183A4UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427183A8UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427183ACUL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427183B0UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427183B4UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427183B8UL)) +#define bFM4_MFS12_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427183BCUL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42718400UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42718404UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42718408UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271840CUL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42718410UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42718414UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42718418UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271841CUL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42718420UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42718424UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42718428UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271842CUL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42718430UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42718434UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42718438UL)) +#define bFM4_MFS12_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271843CUL)) +#define bFM4_MFS12_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42718480UL)) +#define bFM4_MFS12_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42718484UL)) +#define bFM4_MFS12_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42718488UL)) +#define bFM4_MFS12_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271848CUL)) +#define bFM4_MFS12_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42718490UL)) +#define bFM4_MFS12_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42718498UL)) +#define bFM4_MFS12_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271849CUL)) +#define bFM4_MFS12_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427184A0UL)) +#define bFM4_MFS12_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427184ACUL)) +#define bFM4_MFS12_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427184B0UL)) +#define bFM4_MFS12_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427184B4UL)) +#define bFM4_MFS12_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42718500UL)) +#define bFM4_MFS12_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42718504UL)) +#define bFM4_MFS12_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42718508UL)) +#define bFM4_MFS12_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271850CUL)) +#define bFM4_MFS12_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42718510UL)) +#define bFM4_MFS12_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42718514UL)) +#define bFM4_MFS12_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42718518UL)) +#define bFM4_MFS12_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271851CUL)) +#define bFM4_MFS12_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42718520UL)) +#define bFM4_MFS12_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42718524UL)) +#define bFM4_MFS12_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42718528UL)) +#define bFM4_MFS12_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271852CUL)) +#define bFM4_MFS12_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42718530UL)) +#define bFM4_MFS12_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42718534UL)) +#define bFM4_MFS12_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42718538UL)) +#define bFM4_MFS12_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271853CUL)) +#define bFM4_MFS12_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42718580UL)) +#define bFM4_MFS12_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42718584UL)) +#define bFM4_MFS12_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42718588UL)) +#define bFM4_MFS12_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271858CUL)) +#define bFM4_MFS12_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42718590UL)) +#define bFM4_MFS12_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42718594UL)) +#define bFM4_MFS12_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42718598UL)) +#define bFM4_MFS12_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271859CUL)) +#define bFM4_MFS12_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427185A0UL)) +#define bFM4_MFS12_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427185A4UL)) +#define bFM4_MFS12_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427185A8UL)) +#define bFM4_MFS12_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427185ACUL)) +#define bFM4_MFS12_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427185B0UL)) +#define bFM4_MFS12_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427185B4UL)) +#define bFM4_MFS12_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427185B8UL)) +#define bFM4_MFS12_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427185BCUL)) +#define bFM4_MFS12_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42718600UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42718604UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42718614UL)) +#define bFM4_MFS12_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42718618UL)) +#define bFM4_MFS12_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271861CUL)) +#define bFM4_MFS12_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42718620UL)) +#define bFM4_MFS12_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42718624UL)) + +/* MFS LIN channel 12 registers */ +#define bFM4_MFS12_LIN_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) +#define bFM4_MFS12_LIN_SMR_SBL *((volatile unsigned int*)(0x4271800CUL)) +#define bFM4_MFS12_LIN_SMR_WUCR *((volatile unsigned int*)(0x42718010UL)) +#define bFM4_MFS12_LIN_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) +#define bFM4_MFS12_LIN_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) +#define bFM4_MFS12_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) +#define bFM4_MFS12_LIN_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) +#define bFM4_MFS12_LIN_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) +#define bFM4_MFS12_LIN_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) +#define bFM4_MFS12_LIN_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) +#define bFM4_MFS12_LIN_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) +#define bFM4_MFS12_LIN_SCR_LBR *((volatile unsigned int*)(0x42718034UL)) +#define bFM4_MFS12_LIN_SCR_MS *((volatile unsigned int*)(0x42718038UL)) +#define bFM4_MFS12_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) +#define bFM4_MFS12_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42718080UL)) +#define bFM4_MFS12_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42718084UL)) +#define bFM4_MFS12_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42718088UL)) +#define bFM4_MFS12_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271808CUL)) +#define bFM4_MFS12_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42718090UL)) +#define bFM4_MFS12_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42718098UL)) +#define bFM4_MFS12_LIN_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) +#define bFM4_MFS12_LIN_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) +#define bFM4_MFS12_LIN_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) +#define bFM4_MFS12_LIN_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) +#define bFM4_MFS12_LIN_SSR_FRE *((volatile unsigned int*)(0x427180B0UL)) +#define bFM4_MFS12_LIN_SSR_LBD *((volatile unsigned int*)(0x427180B4UL)) +#define bFM4_MFS12_LIN_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) +#define bFM4_MFS12_LIN_BGR_EXT *((volatile unsigned int*)(0x427181BCUL)) +#define bFM4_MFS12_LIN_BGR1_EXT *((volatile unsigned int*)(0x427181BCUL)) +#define bFM4_MFS12_LIN_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_LIN_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_LIN_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_LIN_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_LIN_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_LIN_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_LIN_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_LIN_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_LIN_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_LIN_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) +#define bFM4_MFS12_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) + +/* MFS I2C channel 12 registers */ +#define bFM4_MFS12_I2C_SMR_TIE *((volatile unsigned int*)(0x42718008UL)) +#define bFM4_MFS12_I2C_SMR_RIE *((volatile unsigned int*)(0x4271800CUL)) +#define bFM4_MFS12_I2C_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) +#define bFM4_MFS12_I2C_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) +#define bFM4_MFS12_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) +#define bFM4_MFS12_I2C_IBCR_INT *((volatile unsigned int*)(0x42718020UL)) +#define bFM4_MFS12_I2C_IBCR_BER *((volatile unsigned int*)(0x42718024UL)) +#define bFM4_MFS12_I2C_IBCR_INTE *((volatile unsigned int*)(0x42718028UL)) +#define bFM4_MFS12_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271802CUL)) +#define bFM4_MFS12_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42718030UL)) +#define bFM4_MFS12_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42718034UL)) +#define bFM4_MFS12_I2C_IBCR_ACT *((volatile unsigned int*)(0x42718038UL)) +#define bFM4_MFS12_I2C_IBCR_SCC *((volatile unsigned int*)(0x42718038UL)) +#define bFM4_MFS12_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271803CUL)) +#define bFM4_MFS12_I2C_IBSR_BB *((volatile unsigned int*)(0x42718080UL)) +#define bFM4_MFS12_I2C_IBSR_SPC *((volatile unsigned int*)(0x42718084UL)) +#define bFM4_MFS12_I2C_IBSR_RSC *((volatile unsigned int*)(0x42718088UL)) +#define bFM4_MFS12_I2C_IBSR_AL *((volatile unsigned int*)(0x4271808CUL)) +#define bFM4_MFS12_I2C_IBSR_TRX *((volatile unsigned int*)(0x42718090UL)) +#define bFM4_MFS12_I2C_IBSR_RSA *((volatile unsigned int*)(0x42718094UL)) +#define bFM4_MFS12_I2C_IBSR_RACK *((volatile unsigned int*)(0x42718098UL)) +#define bFM4_MFS12_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271809CUL)) +#define bFM4_MFS12_I2C_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) +#define bFM4_MFS12_I2C_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) +#define bFM4_MFS12_I2C_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) +#define bFM4_MFS12_I2C_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) +#define bFM4_MFS12_I2C_SSR_TBIE *((volatile unsigned int*)(0x427180B0UL)) +#define bFM4_MFS12_I2C_SSR_DMA *((volatile unsigned int*)(0x427180B4UL)) +#define bFM4_MFS12_I2C_SSR_TSET *((volatile unsigned int*)(0x427180B8UL)) +#define bFM4_MFS12_I2C_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) +#define bFM4_MFS12_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42718200UL)) +#define bFM4_MFS12_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42718204UL)) +#define bFM4_MFS12_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42718208UL)) +#define bFM4_MFS12_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271820CUL)) +#define bFM4_MFS12_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42718210UL)) +#define bFM4_MFS12_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42718214UL)) +#define bFM4_MFS12_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42718218UL)) +#define bFM4_MFS12_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271821CUL)) +#define bFM4_MFS12_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42718220UL)) +#define bFM4_MFS12_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42718224UL)) +#define bFM4_MFS12_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42718228UL)) +#define bFM4_MFS12_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271822CUL)) +#define bFM4_MFS12_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42718230UL)) +#define bFM4_MFS12_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42718234UL)) +#define bFM4_MFS12_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42718238UL)) +#define bFM4_MFS12_I2C_ISMK_EN *((volatile unsigned int*)(0x4271823CUL)) +#define bFM4_MFS12_I2C_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_I2C_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_I2C_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_I2C_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_I2C_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_I2C_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_I2C_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) +#define bFM4_MFS12_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) +#define bFM4_MFS12_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) +#define bFM4_MFS12_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) +#define bFM4_MFS12_I2C_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) +#define bFM4_MFS12_I2C_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) +#define bFM4_MFS12_I2C_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) +#define bFM4_MFS12_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) +#define bFM4_MFS12_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) +#define bFM4_MFS12_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) +#define bFM4_MFS12_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) +#define bFM4_MFS12_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) +#define bFM4_MFS12_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) +#define bFM4_MFS12_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) +#define bFM4_MFS12_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) +#define bFM4_MFS12_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) +#define bFM4_MFS12_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) +#define bFM4_MFS12_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) +#define bFM4_MFS12_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) + +/* MFS UART channel 13 registers */ +#define bFM4_MFS13_UART_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) +#define bFM4_MFS13_UART_SMR_BDS *((volatile unsigned int*)(0x4271A008UL)) +#define bFM4_MFS13_UART_SMR_SBL *((volatile unsigned int*)(0x4271A00CUL)) +#define bFM4_MFS13_UART_SMR_WUCR *((volatile unsigned int*)(0x4271A010UL)) +#define bFM4_MFS13_UART_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) +#define bFM4_MFS13_UART_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) +#define bFM4_MFS13_UART_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) +#define bFM4_MFS13_UART_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) +#define bFM4_MFS13_UART_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) +#define bFM4_MFS13_UART_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) +#define bFM4_MFS13_UART_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) +#define bFM4_MFS13_UART_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) +#define bFM4_MFS13_UART_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) +#define bFM4_MFS13_UART_ESCR_L0 *((volatile unsigned int*)(0x4271A080UL)) +#define bFM4_MFS13_UART_ESCR_L1 *((volatile unsigned int*)(0x4271A084UL)) +#define bFM4_MFS13_UART_ESCR_L2 *((volatile unsigned int*)(0x4271A088UL)) +#define bFM4_MFS13_UART_ESCR_P *((volatile unsigned int*)(0x4271A08CUL)) +#define bFM4_MFS13_UART_ESCR_PEN *((volatile unsigned int*)(0x4271A090UL)) +#define bFM4_MFS13_UART_ESCR_INV *((volatile unsigned int*)(0x4271A094UL)) +#define bFM4_MFS13_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271A098UL)) +#define bFM4_MFS13_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271A09CUL)) +#define bFM4_MFS13_UART_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) +#define bFM4_MFS13_UART_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) +#define bFM4_MFS13_UART_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) +#define bFM4_MFS13_UART_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) +#define bFM4_MFS13_UART_SSR_FRE *((volatile unsigned int*)(0x4271A0B0UL)) +#define bFM4_MFS13_UART_SSR_PE *((volatile unsigned int*)(0x4271A0B4UL)) +#define bFM4_MFS13_UART_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) +#define bFM4_MFS13_UART_RDR_AD *((volatile unsigned int*)(0x4271A120UL)) +#define bFM4_MFS13_UART_TDR_AD *((volatile unsigned int*)(0x4271A120UL)) +#define bFM4_MFS13_UART_BGR_EXT *((volatile unsigned int*)(0x4271A1BCUL)) +#define bFM4_MFS13_UART_BGR1_EXT *((volatile unsigned int*)(0x4271A1BCUL)) +#define bFM4_MFS13_UART_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_UART_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_UART_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_UART_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_UART_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_UART_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_UART_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_UART_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_UART_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_UART_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) +#define bFM4_MFS13_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) + +/* MFS CSIO channel 13 registers */ +#define bFM4_MFS13_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) +#define bFM4_MFS13_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271A004UL)) +#define bFM4_MFS13_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271A008UL)) +#define bFM4_MFS13_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271A00CUL)) +#define bFM4_MFS13_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) +#define bFM4_MFS13_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) +#define bFM4_MFS13_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) +#define bFM4_MFS13_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) +#define bFM4_MFS13_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) +#define bFM4_MFS13_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) +#define bFM4_MFS13_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) +#define bFM4_MFS13_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) +#define bFM4_MFS13_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271A034UL)) +#define bFM4_MFS13_CSIO_SCR_MS *((volatile unsigned int*)(0x4271A038UL)) +#define bFM4_MFS13_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) +#define bFM4_MFS13_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271A080UL)) +#define bFM4_MFS13_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271A084UL)) +#define bFM4_MFS13_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271A088UL)) +#define bFM4_MFS13_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271A08CUL)) +#define bFM4_MFS13_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271A090UL)) +#define bFM4_MFS13_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271A098UL)) +#define bFM4_MFS13_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271A09CUL)) +#define bFM4_MFS13_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) +#define bFM4_MFS13_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) +#define bFM4_MFS13_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) +#define bFM4_MFS13_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) +#define bFM4_MFS13_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271A0B0UL)) +#define bFM4_MFS13_CSIO_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) +#define bFM4_MFS13_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271A380UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271A384UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271A388UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271A38CUL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271A390UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271A394UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271A398UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271A39CUL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271A3A0UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271A3A4UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271A3A8UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271A3ACUL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271A3B0UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271A3B4UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271A3B8UL)) +#define bFM4_MFS13_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271A3BCUL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271A400UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271A404UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271A408UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271A40CUL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271A410UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271A414UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271A418UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271A41CUL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271A420UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271A424UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271A428UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271A42CUL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271A430UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271A434UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271A438UL)) +#define bFM4_MFS13_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271A43CUL)) +#define bFM4_MFS13_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271A480UL)) +#define bFM4_MFS13_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271A484UL)) +#define bFM4_MFS13_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271A488UL)) +#define bFM4_MFS13_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271A48CUL)) +#define bFM4_MFS13_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271A490UL)) +#define bFM4_MFS13_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271A498UL)) +#define bFM4_MFS13_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271A49CUL)) +#define bFM4_MFS13_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271A4A0UL)) +#define bFM4_MFS13_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271A4ACUL)) +#define bFM4_MFS13_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271A4B0UL)) +#define bFM4_MFS13_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271A4B4UL)) +#define bFM4_MFS13_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271A500UL)) +#define bFM4_MFS13_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271A504UL)) +#define bFM4_MFS13_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271A508UL)) +#define bFM4_MFS13_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271A50CUL)) +#define bFM4_MFS13_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271A510UL)) +#define bFM4_MFS13_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271A514UL)) +#define bFM4_MFS13_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271A518UL)) +#define bFM4_MFS13_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271A51CUL)) +#define bFM4_MFS13_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271A520UL)) +#define bFM4_MFS13_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271A524UL)) +#define bFM4_MFS13_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271A528UL)) +#define bFM4_MFS13_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271A52CUL)) +#define bFM4_MFS13_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271A530UL)) +#define bFM4_MFS13_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271A534UL)) +#define bFM4_MFS13_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271A538UL)) +#define bFM4_MFS13_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271A53CUL)) +#define bFM4_MFS13_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271A580UL)) +#define bFM4_MFS13_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271A584UL)) +#define bFM4_MFS13_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271A588UL)) +#define bFM4_MFS13_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271A58CUL)) +#define bFM4_MFS13_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271A590UL)) +#define bFM4_MFS13_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271A594UL)) +#define bFM4_MFS13_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271A598UL)) +#define bFM4_MFS13_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271A59CUL)) +#define bFM4_MFS13_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271A5A0UL)) +#define bFM4_MFS13_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271A5A4UL)) +#define bFM4_MFS13_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271A5A8UL)) +#define bFM4_MFS13_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271A5ACUL)) +#define bFM4_MFS13_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271A5B0UL)) +#define bFM4_MFS13_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271A5B4UL)) +#define bFM4_MFS13_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271A5B8UL)) +#define bFM4_MFS13_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271A5BCUL)) +#define bFM4_MFS13_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271A600UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271A604UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271A614UL)) +#define bFM4_MFS13_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271A618UL)) +#define bFM4_MFS13_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271A61CUL)) +#define bFM4_MFS13_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271A620UL)) +#define bFM4_MFS13_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271A624UL)) + +/* MFS LIN channel 13 registers */ +#define bFM4_MFS13_LIN_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) +#define bFM4_MFS13_LIN_SMR_SBL *((volatile unsigned int*)(0x4271A00CUL)) +#define bFM4_MFS13_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271A010UL)) +#define bFM4_MFS13_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) +#define bFM4_MFS13_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) +#define bFM4_MFS13_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) +#define bFM4_MFS13_LIN_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) +#define bFM4_MFS13_LIN_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) +#define bFM4_MFS13_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) +#define bFM4_MFS13_LIN_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) +#define bFM4_MFS13_LIN_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) +#define bFM4_MFS13_LIN_SCR_LBR *((volatile unsigned int*)(0x4271A034UL)) +#define bFM4_MFS13_LIN_SCR_MS *((volatile unsigned int*)(0x4271A038UL)) +#define bFM4_MFS13_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) +#define bFM4_MFS13_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271A080UL)) +#define bFM4_MFS13_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271A084UL)) +#define bFM4_MFS13_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271A088UL)) +#define bFM4_MFS13_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271A08CUL)) +#define bFM4_MFS13_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271A090UL)) +#define bFM4_MFS13_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271A098UL)) +#define bFM4_MFS13_LIN_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) +#define bFM4_MFS13_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) +#define bFM4_MFS13_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) +#define bFM4_MFS13_LIN_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) +#define bFM4_MFS13_LIN_SSR_FRE *((volatile unsigned int*)(0x4271A0B0UL)) +#define bFM4_MFS13_LIN_SSR_LBD *((volatile unsigned int*)(0x4271A0B4UL)) +#define bFM4_MFS13_LIN_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) +#define bFM4_MFS13_LIN_BGR_EXT *((volatile unsigned int*)(0x4271A1BCUL)) +#define bFM4_MFS13_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271A1BCUL)) +#define bFM4_MFS13_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_LIN_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_LIN_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_LIN_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) +#define bFM4_MFS13_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) + +/* MFS I2C channel 13 registers */ +#define bFM4_MFS13_I2C_SMR_TIE *((volatile unsigned int*)(0x4271A008UL)) +#define bFM4_MFS13_I2C_SMR_RIE *((volatile unsigned int*)(0x4271A00CUL)) +#define bFM4_MFS13_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) +#define bFM4_MFS13_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) +#define bFM4_MFS13_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) +#define bFM4_MFS13_I2C_IBCR_INT *((volatile unsigned int*)(0x4271A020UL)) +#define bFM4_MFS13_I2C_IBCR_BER *((volatile unsigned int*)(0x4271A024UL)) +#define bFM4_MFS13_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271A028UL)) +#define bFM4_MFS13_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271A02CUL)) +#define bFM4_MFS13_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271A030UL)) +#define bFM4_MFS13_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271A034UL)) +#define bFM4_MFS13_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271A038UL)) +#define bFM4_MFS13_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271A038UL)) +#define bFM4_MFS13_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271A03CUL)) +#define bFM4_MFS13_I2C_IBSR_BB *((volatile unsigned int*)(0x4271A080UL)) +#define bFM4_MFS13_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271A084UL)) +#define bFM4_MFS13_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271A088UL)) +#define bFM4_MFS13_I2C_IBSR_AL *((volatile unsigned int*)(0x4271A08CUL)) +#define bFM4_MFS13_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271A090UL)) +#define bFM4_MFS13_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271A094UL)) +#define bFM4_MFS13_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271A098UL)) +#define bFM4_MFS13_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271A09CUL)) +#define bFM4_MFS13_I2C_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) +#define bFM4_MFS13_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) +#define bFM4_MFS13_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) +#define bFM4_MFS13_I2C_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) +#define bFM4_MFS13_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271A0B0UL)) +#define bFM4_MFS13_I2C_SSR_DMA *((volatile unsigned int*)(0x4271A0B4UL)) +#define bFM4_MFS13_I2C_SSR_TSET *((volatile unsigned int*)(0x4271A0B8UL)) +#define bFM4_MFS13_I2C_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) +#define bFM4_MFS13_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271A200UL)) +#define bFM4_MFS13_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271A204UL)) +#define bFM4_MFS13_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271A208UL)) +#define bFM4_MFS13_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271A20CUL)) +#define bFM4_MFS13_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271A210UL)) +#define bFM4_MFS13_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271A214UL)) +#define bFM4_MFS13_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271A218UL)) +#define bFM4_MFS13_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271A21CUL)) +#define bFM4_MFS13_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271A220UL)) +#define bFM4_MFS13_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271A224UL)) +#define bFM4_MFS13_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271A228UL)) +#define bFM4_MFS13_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271A22CUL)) +#define bFM4_MFS13_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271A230UL)) +#define bFM4_MFS13_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271A234UL)) +#define bFM4_MFS13_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271A238UL)) +#define bFM4_MFS13_I2C_ISMK_EN *((volatile unsigned int*)(0x4271A23CUL)) +#define bFM4_MFS13_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_I2C_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_I2C_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_I2C_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) +#define bFM4_MFS13_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) +#define bFM4_MFS13_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) +#define bFM4_MFS13_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) +#define bFM4_MFS13_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) +#define bFM4_MFS13_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) +#define bFM4_MFS13_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) +#define bFM4_MFS13_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) +#define bFM4_MFS13_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) +#define bFM4_MFS13_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) +#define bFM4_MFS13_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) +#define bFM4_MFS13_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) +#define bFM4_MFS13_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) +#define bFM4_MFS13_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) +#define bFM4_MFS13_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) +#define bFM4_MFS13_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) +#define bFM4_MFS13_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) +#define bFM4_MFS13_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) +#define bFM4_MFS13_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) + +/* MFS UART channel 14 registers */ +#define bFM4_MFS14_UART_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) +#define bFM4_MFS14_UART_SMR_BDS *((volatile unsigned int*)(0x4271C008UL)) +#define bFM4_MFS14_UART_SMR_SBL *((volatile unsigned int*)(0x4271C00CUL)) +#define bFM4_MFS14_UART_SMR_WUCR *((volatile unsigned int*)(0x4271C010UL)) +#define bFM4_MFS14_UART_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) +#define bFM4_MFS14_UART_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) +#define bFM4_MFS14_UART_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) +#define bFM4_MFS14_UART_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) +#define bFM4_MFS14_UART_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) +#define bFM4_MFS14_UART_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) +#define bFM4_MFS14_UART_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) +#define bFM4_MFS14_UART_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) +#define bFM4_MFS14_UART_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) +#define bFM4_MFS14_UART_ESCR_L0 *((volatile unsigned int*)(0x4271C080UL)) +#define bFM4_MFS14_UART_ESCR_L1 *((volatile unsigned int*)(0x4271C084UL)) +#define bFM4_MFS14_UART_ESCR_L2 *((volatile unsigned int*)(0x4271C088UL)) +#define bFM4_MFS14_UART_ESCR_P *((volatile unsigned int*)(0x4271C08CUL)) +#define bFM4_MFS14_UART_ESCR_PEN *((volatile unsigned int*)(0x4271C090UL)) +#define bFM4_MFS14_UART_ESCR_INV *((volatile unsigned int*)(0x4271C094UL)) +#define bFM4_MFS14_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271C098UL)) +#define bFM4_MFS14_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271C09CUL)) +#define bFM4_MFS14_UART_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) +#define bFM4_MFS14_UART_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) +#define bFM4_MFS14_UART_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) +#define bFM4_MFS14_UART_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) +#define bFM4_MFS14_UART_SSR_FRE *((volatile unsigned int*)(0x4271C0B0UL)) +#define bFM4_MFS14_UART_SSR_PE *((volatile unsigned int*)(0x4271C0B4UL)) +#define bFM4_MFS14_UART_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) +#define bFM4_MFS14_UART_RDR_AD *((volatile unsigned int*)(0x4271C120UL)) +#define bFM4_MFS14_UART_TDR_AD *((volatile unsigned int*)(0x4271C120UL)) +#define bFM4_MFS14_UART_BGR_EXT *((volatile unsigned int*)(0x4271C1BCUL)) +#define bFM4_MFS14_UART_BGR1_EXT *((volatile unsigned int*)(0x4271C1BCUL)) +#define bFM4_MFS14_UART_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_UART_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_UART_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_UART_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_UART_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_UART_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_UART_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_UART_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_UART_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_UART_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) +#define bFM4_MFS14_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) + +/* MFS CSIO channel 14 registers */ +#define bFM4_MFS14_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) +#define bFM4_MFS14_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271C004UL)) +#define bFM4_MFS14_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271C008UL)) +#define bFM4_MFS14_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271C00CUL)) +#define bFM4_MFS14_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) +#define bFM4_MFS14_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) +#define bFM4_MFS14_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) +#define bFM4_MFS14_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) +#define bFM4_MFS14_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) +#define bFM4_MFS14_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) +#define bFM4_MFS14_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) +#define bFM4_MFS14_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) +#define bFM4_MFS14_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271C034UL)) +#define bFM4_MFS14_CSIO_SCR_MS *((volatile unsigned int*)(0x4271C038UL)) +#define bFM4_MFS14_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) +#define bFM4_MFS14_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271C080UL)) +#define bFM4_MFS14_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271C084UL)) +#define bFM4_MFS14_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271C088UL)) +#define bFM4_MFS14_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271C08CUL)) +#define bFM4_MFS14_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271C090UL)) +#define bFM4_MFS14_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271C098UL)) +#define bFM4_MFS14_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271C09CUL)) +#define bFM4_MFS14_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) +#define bFM4_MFS14_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) +#define bFM4_MFS14_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) +#define bFM4_MFS14_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) +#define bFM4_MFS14_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271C0B0UL)) +#define bFM4_MFS14_CSIO_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) +#define bFM4_MFS14_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271C380UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271C384UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271C388UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271C38CUL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271C390UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271C394UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271C398UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271C39CUL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271C3A0UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271C3A4UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271C3A8UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271C3ACUL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271C3B0UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271C3B4UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271C3B8UL)) +#define bFM4_MFS14_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271C3BCUL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271C400UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271C404UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271C408UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271C40CUL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271C410UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271C414UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271C418UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271C41CUL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271C420UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271C424UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271C428UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271C42CUL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271C430UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271C434UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271C438UL)) +#define bFM4_MFS14_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271C43CUL)) +#define bFM4_MFS14_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271C480UL)) +#define bFM4_MFS14_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271C484UL)) +#define bFM4_MFS14_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271C488UL)) +#define bFM4_MFS14_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271C48CUL)) +#define bFM4_MFS14_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271C490UL)) +#define bFM4_MFS14_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271C498UL)) +#define bFM4_MFS14_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271C49CUL)) +#define bFM4_MFS14_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271C4A0UL)) +#define bFM4_MFS14_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271C4ACUL)) +#define bFM4_MFS14_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271C4B0UL)) +#define bFM4_MFS14_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271C4B4UL)) +#define bFM4_MFS14_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271C500UL)) +#define bFM4_MFS14_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271C504UL)) +#define bFM4_MFS14_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271C508UL)) +#define bFM4_MFS14_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271C50CUL)) +#define bFM4_MFS14_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271C510UL)) +#define bFM4_MFS14_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271C514UL)) +#define bFM4_MFS14_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271C518UL)) +#define bFM4_MFS14_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271C51CUL)) +#define bFM4_MFS14_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271C520UL)) +#define bFM4_MFS14_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271C524UL)) +#define bFM4_MFS14_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271C528UL)) +#define bFM4_MFS14_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271C52CUL)) +#define bFM4_MFS14_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271C530UL)) +#define bFM4_MFS14_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271C534UL)) +#define bFM4_MFS14_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271C538UL)) +#define bFM4_MFS14_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271C53CUL)) +#define bFM4_MFS14_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271C580UL)) +#define bFM4_MFS14_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271C584UL)) +#define bFM4_MFS14_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271C588UL)) +#define bFM4_MFS14_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271C58CUL)) +#define bFM4_MFS14_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271C590UL)) +#define bFM4_MFS14_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271C594UL)) +#define bFM4_MFS14_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271C598UL)) +#define bFM4_MFS14_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271C59CUL)) +#define bFM4_MFS14_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271C5A0UL)) +#define bFM4_MFS14_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271C5A4UL)) +#define bFM4_MFS14_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271C5A8UL)) +#define bFM4_MFS14_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271C5ACUL)) +#define bFM4_MFS14_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271C5B0UL)) +#define bFM4_MFS14_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271C5B4UL)) +#define bFM4_MFS14_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271C5B8UL)) +#define bFM4_MFS14_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271C5BCUL)) +#define bFM4_MFS14_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271C600UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271C604UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271C614UL)) +#define bFM4_MFS14_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271C618UL)) +#define bFM4_MFS14_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271C61CUL)) +#define bFM4_MFS14_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271C620UL)) +#define bFM4_MFS14_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271C624UL)) + +/* MFS LIN channel 14 registers */ +#define bFM4_MFS14_LIN_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) +#define bFM4_MFS14_LIN_SMR_SBL *((volatile unsigned int*)(0x4271C00CUL)) +#define bFM4_MFS14_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271C010UL)) +#define bFM4_MFS14_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) +#define bFM4_MFS14_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) +#define bFM4_MFS14_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) +#define bFM4_MFS14_LIN_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) +#define bFM4_MFS14_LIN_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) +#define bFM4_MFS14_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) +#define bFM4_MFS14_LIN_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) +#define bFM4_MFS14_LIN_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) +#define bFM4_MFS14_LIN_SCR_LBR *((volatile unsigned int*)(0x4271C034UL)) +#define bFM4_MFS14_LIN_SCR_MS *((volatile unsigned int*)(0x4271C038UL)) +#define bFM4_MFS14_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) +#define bFM4_MFS14_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271C080UL)) +#define bFM4_MFS14_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271C084UL)) +#define bFM4_MFS14_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271C088UL)) +#define bFM4_MFS14_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271C08CUL)) +#define bFM4_MFS14_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271C090UL)) +#define bFM4_MFS14_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271C098UL)) +#define bFM4_MFS14_LIN_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) +#define bFM4_MFS14_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) +#define bFM4_MFS14_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) +#define bFM4_MFS14_LIN_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) +#define bFM4_MFS14_LIN_SSR_FRE *((volatile unsigned int*)(0x4271C0B0UL)) +#define bFM4_MFS14_LIN_SSR_LBD *((volatile unsigned int*)(0x4271C0B4UL)) +#define bFM4_MFS14_LIN_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) +#define bFM4_MFS14_LIN_BGR_EXT *((volatile unsigned int*)(0x4271C1BCUL)) +#define bFM4_MFS14_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271C1BCUL)) +#define bFM4_MFS14_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_LIN_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_LIN_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_LIN_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) +#define bFM4_MFS14_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) + +/* MFS I2C channel 14 registers */ +#define bFM4_MFS14_I2C_SMR_TIE *((volatile unsigned int*)(0x4271C008UL)) +#define bFM4_MFS14_I2C_SMR_RIE *((volatile unsigned int*)(0x4271C00CUL)) +#define bFM4_MFS14_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) +#define bFM4_MFS14_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) +#define bFM4_MFS14_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) +#define bFM4_MFS14_I2C_IBCR_INT *((volatile unsigned int*)(0x4271C020UL)) +#define bFM4_MFS14_I2C_IBCR_BER *((volatile unsigned int*)(0x4271C024UL)) +#define bFM4_MFS14_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271C028UL)) +#define bFM4_MFS14_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271C02CUL)) +#define bFM4_MFS14_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271C030UL)) +#define bFM4_MFS14_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271C034UL)) +#define bFM4_MFS14_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271C038UL)) +#define bFM4_MFS14_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271C038UL)) +#define bFM4_MFS14_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271C03CUL)) +#define bFM4_MFS14_I2C_IBSR_BB *((volatile unsigned int*)(0x4271C080UL)) +#define bFM4_MFS14_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271C084UL)) +#define bFM4_MFS14_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271C088UL)) +#define bFM4_MFS14_I2C_IBSR_AL *((volatile unsigned int*)(0x4271C08CUL)) +#define bFM4_MFS14_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271C090UL)) +#define bFM4_MFS14_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271C094UL)) +#define bFM4_MFS14_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271C098UL)) +#define bFM4_MFS14_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271C09CUL)) +#define bFM4_MFS14_I2C_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) +#define bFM4_MFS14_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) +#define bFM4_MFS14_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) +#define bFM4_MFS14_I2C_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) +#define bFM4_MFS14_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271C0B0UL)) +#define bFM4_MFS14_I2C_SSR_DMA *((volatile unsigned int*)(0x4271C0B4UL)) +#define bFM4_MFS14_I2C_SSR_TSET *((volatile unsigned int*)(0x4271C0B8UL)) +#define bFM4_MFS14_I2C_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) +#define bFM4_MFS14_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271C200UL)) +#define bFM4_MFS14_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271C204UL)) +#define bFM4_MFS14_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271C208UL)) +#define bFM4_MFS14_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271C20CUL)) +#define bFM4_MFS14_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271C210UL)) +#define bFM4_MFS14_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271C214UL)) +#define bFM4_MFS14_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271C218UL)) +#define bFM4_MFS14_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271C21CUL)) +#define bFM4_MFS14_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271C220UL)) +#define bFM4_MFS14_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271C224UL)) +#define bFM4_MFS14_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271C228UL)) +#define bFM4_MFS14_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271C22CUL)) +#define bFM4_MFS14_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271C230UL)) +#define bFM4_MFS14_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271C234UL)) +#define bFM4_MFS14_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271C238UL)) +#define bFM4_MFS14_I2C_ISMK_EN *((volatile unsigned int*)(0x4271C23CUL)) +#define bFM4_MFS14_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_I2C_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_I2C_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_I2C_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) +#define bFM4_MFS14_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) +#define bFM4_MFS14_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) +#define bFM4_MFS14_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) +#define bFM4_MFS14_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) +#define bFM4_MFS14_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) +#define bFM4_MFS14_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) +#define bFM4_MFS14_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) +#define bFM4_MFS14_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) +#define bFM4_MFS14_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) +#define bFM4_MFS14_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) +#define bFM4_MFS14_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) +#define bFM4_MFS14_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) +#define bFM4_MFS14_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) +#define bFM4_MFS14_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) +#define bFM4_MFS14_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) +#define bFM4_MFS14_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) +#define bFM4_MFS14_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) +#define bFM4_MFS14_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) + +/* MFS UART channel 15 registers */ +#define bFM4_MFS15_UART_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) +#define bFM4_MFS15_UART_SMR_BDS *((volatile unsigned int*)(0x4271E008UL)) +#define bFM4_MFS15_UART_SMR_SBL *((volatile unsigned int*)(0x4271E00CUL)) +#define bFM4_MFS15_UART_SMR_WUCR *((volatile unsigned int*)(0x4271E010UL)) +#define bFM4_MFS15_UART_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) +#define bFM4_MFS15_UART_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) +#define bFM4_MFS15_UART_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) +#define bFM4_MFS15_UART_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) +#define bFM4_MFS15_UART_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) +#define bFM4_MFS15_UART_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) +#define bFM4_MFS15_UART_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) +#define bFM4_MFS15_UART_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) +#define bFM4_MFS15_UART_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) +#define bFM4_MFS15_UART_ESCR_L0 *((volatile unsigned int*)(0x4271E080UL)) +#define bFM4_MFS15_UART_ESCR_L1 *((volatile unsigned int*)(0x4271E084UL)) +#define bFM4_MFS15_UART_ESCR_L2 *((volatile unsigned int*)(0x4271E088UL)) +#define bFM4_MFS15_UART_ESCR_P *((volatile unsigned int*)(0x4271E08CUL)) +#define bFM4_MFS15_UART_ESCR_PEN *((volatile unsigned int*)(0x4271E090UL)) +#define bFM4_MFS15_UART_ESCR_INV *((volatile unsigned int*)(0x4271E094UL)) +#define bFM4_MFS15_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271E098UL)) +#define bFM4_MFS15_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271E09CUL)) +#define bFM4_MFS15_UART_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) +#define bFM4_MFS15_UART_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) +#define bFM4_MFS15_UART_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) +#define bFM4_MFS15_UART_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) +#define bFM4_MFS15_UART_SSR_FRE *((volatile unsigned int*)(0x4271E0B0UL)) +#define bFM4_MFS15_UART_SSR_PE *((volatile unsigned int*)(0x4271E0B4UL)) +#define bFM4_MFS15_UART_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) +#define bFM4_MFS15_UART_RDR_AD *((volatile unsigned int*)(0x4271E120UL)) +#define bFM4_MFS15_UART_TDR_AD *((volatile unsigned int*)(0x4271E120UL)) +#define bFM4_MFS15_UART_BGR_EXT *((volatile unsigned int*)(0x4271E1BCUL)) +#define bFM4_MFS15_UART_BGR1_EXT *((volatile unsigned int*)(0x4271E1BCUL)) +#define bFM4_MFS15_UART_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_UART_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_UART_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_UART_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_UART_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_UART_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_UART_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_UART_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_UART_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_UART_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) +#define bFM4_MFS15_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) + +/* MFS CSIO channel 15 registers */ +#define bFM4_MFS15_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) +#define bFM4_MFS15_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271E004UL)) +#define bFM4_MFS15_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271E008UL)) +#define bFM4_MFS15_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271E00CUL)) +#define bFM4_MFS15_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) +#define bFM4_MFS15_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) +#define bFM4_MFS15_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) +#define bFM4_MFS15_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) +#define bFM4_MFS15_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) +#define bFM4_MFS15_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) +#define bFM4_MFS15_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) +#define bFM4_MFS15_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) +#define bFM4_MFS15_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271E034UL)) +#define bFM4_MFS15_CSIO_SCR_MS *((volatile unsigned int*)(0x4271E038UL)) +#define bFM4_MFS15_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) +#define bFM4_MFS15_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271E080UL)) +#define bFM4_MFS15_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271E084UL)) +#define bFM4_MFS15_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271E088UL)) +#define bFM4_MFS15_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271E08CUL)) +#define bFM4_MFS15_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271E090UL)) +#define bFM4_MFS15_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271E098UL)) +#define bFM4_MFS15_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271E09CUL)) +#define bFM4_MFS15_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) +#define bFM4_MFS15_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) +#define bFM4_MFS15_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) +#define bFM4_MFS15_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) +#define bFM4_MFS15_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271E0B0UL)) +#define bFM4_MFS15_CSIO_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) +#define bFM4_MFS15_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271E380UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271E384UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271E388UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271E38CUL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271E390UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271E394UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271E398UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271E39CUL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271E3A0UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271E3A4UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271E3A8UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271E3ACUL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271E3B0UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271E3B4UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271E3B8UL)) +#define bFM4_MFS15_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271E3BCUL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271E400UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271E404UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271E408UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271E40CUL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271E410UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271E414UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271E418UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271E41CUL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271E420UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271E424UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271E428UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271E42CUL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271E430UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271E434UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271E438UL)) +#define bFM4_MFS15_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271E43CUL)) +#define bFM4_MFS15_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271E480UL)) +#define bFM4_MFS15_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271E484UL)) +#define bFM4_MFS15_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271E488UL)) +#define bFM4_MFS15_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271E48CUL)) +#define bFM4_MFS15_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271E490UL)) +#define bFM4_MFS15_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271E498UL)) +#define bFM4_MFS15_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271E49CUL)) +#define bFM4_MFS15_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271E4A0UL)) +#define bFM4_MFS15_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271E4ACUL)) +#define bFM4_MFS15_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271E4B0UL)) +#define bFM4_MFS15_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271E4B4UL)) +#define bFM4_MFS15_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271E500UL)) +#define bFM4_MFS15_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271E504UL)) +#define bFM4_MFS15_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271E508UL)) +#define bFM4_MFS15_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271E50CUL)) +#define bFM4_MFS15_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271E510UL)) +#define bFM4_MFS15_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271E514UL)) +#define bFM4_MFS15_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271E518UL)) +#define bFM4_MFS15_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271E51CUL)) +#define bFM4_MFS15_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271E520UL)) +#define bFM4_MFS15_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271E524UL)) +#define bFM4_MFS15_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271E528UL)) +#define bFM4_MFS15_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271E52CUL)) +#define bFM4_MFS15_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271E530UL)) +#define bFM4_MFS15_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271E534UL)) +#define bFM4_MFS15_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271E538UL)) +#define bFM4_MFS15_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271E53CUL)) +#define bFM4_MFS15_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271E580UL)) +#define bFM4_MFS15_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271E584UL)) +#define bFM4_MFS15_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271E588UL)) +#define bFM4_MFS15_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271E58CUL)) +#define bFM4_MFS15_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271E590UL)) +#define bFM4_MFS15_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271E594UL)) +#define bFM4_MFS15_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271E598UL)) +#define bFM4_MFS15_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271E59CUL)) +#define bFM4_MFS15_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271E5A0UL)) +#define bFM4_MFS15_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271E5A4UL)) +#define bFM4_MFS15_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271E5A8UL)) +#define bFM4_MFS15_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271E5ACUL)) +#define bFM4_MFS15_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271E5B0UL)) +#define bFM4_MFS15_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271E5B4UL)) +#define bFM4_MFS15_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271E5B8UL)) +#define bFM4_MFS15_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271E5BCUL)) +#define bFM4_MFS15_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271E600UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271E604UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271E614UL)) +#define bFM4_MFS15_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271E618UL)) +#define bFM4_MFS15_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271E61CUL)) +#define bFM4_MFS15_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271E620UL)) +#define bFM4_MFS15_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271E624UL)) + +/* MFS LIN channel 15 registers */ +#define bFM4_MFS15_LIN_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) +#define bFM4_MFS15_LIN_SMR_SBL *((volatile unsigned int*)(0x4271E00CUL)) +#define bFM4_MFS15_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271E010UL)) +#define bFM4_MFS15_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) +#define bFM4_MFS15_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) +#define bFM4_MFS15_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) +#define bFM4_MFS15_LIN_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) +#define bFM4_MFS15_LIN_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) +#define bFM4_MFS15_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) +#define bFM4_MFS15_LIN_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) +#define bFM4_MFS15_LIN_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) +#define bFM4_MFS15_LIN_SCR_LBR *((volatile unsigned int*)(0x4271E034UL)) +#define bFM4_MFS15_LIN_SCR_MS *((volatile unsigned int*)(0x4271E038UL)) +#define bFM4_MFS15_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) +#define bFM4_MFS15_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271E080UL)) +#define bFM4_MFS15_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271E084UL)) +#define bFM4_MFS15_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271E088UL)) +#define bFM4_MFS15_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271E08CUL)) +#define bFM4_MFS15_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271E090UL)) +#define bFM4_MFS15_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271E098UL)) +#define bFM4_MFS15_LIN_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) +#define bFM4_MFS15_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) +#define bFM4_MFS15_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) +#define bFM4_MFS15_LIN_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) +#define bFM4_MFS15_LIN_SSR_FRE *((volatile unsigned int*)(0x4271E0B0UL)) +#define bFM4_MFS15_LIN_SSR_LBD *((volatile unsigned int*)(0x4271E0B4UL)) +#define bFM4_MFS15_LIN_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) +#define bFM4_MFS15_LIN_BGR_EXT *((volatile unsigned int*)(0x4271E1BCUL)) +#define bFM4_MFS15_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271E1BCUL)) +#define bFM4_MFS15_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_LIN_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_LIN_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_LIN_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) +#define bFM4_MFS15_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) + +/* MFS I2C channel 15 registers */ +#define bFM4_MFS15_I2C_SMR_TIE *((volatile unsigned int*)(0x4271E008UL)) +#define bFM4_MFS15_I2C_SMR_RIE *((volatile unsigned int*)(0x4271E00CUL)) +#define bFM4_MFS15_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) +#define bFM4_MFS15_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) +#define bFM4_MFS15_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) +#define bFM4_MFS15_I2C_IBCR_INT *((volatile unsigned int*)(0x4271E020UL)) +#define bFM4_MFS15_I2C_IBCR_BER *((volatile unsigned int*)(0x4271E024UL)) +#define bFM4_MFS15_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271E028UL)) +#define bFM4_MFS15_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271E02CUL)) +#define bFM4_MFS15_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271E030UL)) +#define bFM4_MFS15_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271E034UL)) +#define bFM4_MFS15_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271E038UL)) +#define bFM4_MFS15_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271E038UL)) +#define bFM4_MFS15_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271E03CUL)) +#define bFM4_MFS15_I2C_IBSR_BB *((volatile unsigned int*)(0x4271E080UL)) +#define bFM4_MFS15_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271E084UL)) +#define bFM4_MFS15_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271E088UL)) +#define bFM4_MFS15_I2C_IBSR_AL *((volatile unsigned int*)(0x4271E08CUL)) +#define bFM4_MFS15_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271E090UL)) +#define bFM4_MFS15_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271E094UL)) +#define bFM4_MFS15_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271E098UL)) +#define bFM4_MFS15_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271E09CUL)) +#define bFM4_MFS15_I2C_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) +#define bFM4_MFS15_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) +#define bFM4_MFS15_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) +#define bFM4_MFS15_I2C_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) +#define bFM4_MFS15_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271E0B0UL)) +#define bFM4_MFS15_I2C_SSR_DMA *((volatile unsigned int*)(0x4271E0B4UL)) +#define bFM4_MFS15_I2C_SSR_TSET *((volatile unsigned int*)(0x4271E0B8UL)) +#define bFM4_MFS15_I2C_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) +#define bFM4_MFS15_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271E200UL)) +#define bFM4_MFS15_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271E204UL)) +#define bFM4_MFS15_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271E208UL)) +#define bFM4_MFS15_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271E20CUL)) +#define bFM4_MFS15_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271E210UL)) +#define bFM4_MFS15_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271E214UL)) +#define bFM4_MFS15_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271E218UL)) +#define bFM4_MFS15_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271E21CUL)) +#define bFM4_MFS15_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271E220UL)) +#define bFM4_MFS15_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271E224UL)) +#define bFM4_MFS15_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271E228UL)) +#define bFM4_MFS15_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271E22CUL)) +#define bFM4_MFS15_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271E230UL)) +#define bFM4_MFS15_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271E234UL)) +#define bFM4_MFS15_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271E238UL)) +#define bFM4_MFS15_I2C_ISMK_EN *((volatile unsigned int*)(0x4271E23CUL)) +#define bFM4_MFS15_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_I2C_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_I2C_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_I2C_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) +#define bFM4_MFS15_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) +#define bFM4_MFS15_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) +#define bFM4_MFS15_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) +#define bFM4_MFS15_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) +#define bFM4_MFS15_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) +#define bFM4_MFS15_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) +#define bFM4_MFS15_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) +#define bFM4_MFS15_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) +#define bFM4_MFS15_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) +#define bFM4_MFS15_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) +#define bFM4_MFS15_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) +#define bFM4_MFS15_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) +#define bFM4_MFS15_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) +#define bFM4_MFS15_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) +#define bFM4_MFS15_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) +#define bFM4_MFS15_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) +#define bFM4_MFS15_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) +#define bFM4_MFS15_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) + +/* CRC registers */ +#define bFM4_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM4_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM4_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM4_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM4_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM4_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM4_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM4_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM4_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM4_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM4_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM4_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM4_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM4_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM4_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM4_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM4_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM4_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM4_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM4_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM4_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM4_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM4_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM4_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM4_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM4_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM4_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM4_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM4_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* Real time clock registers */ +#define bFM4_RTC_WTCR10_ST *((volatile unsigned int*)(0x42762000UL)) +#define bFM4_RTC_WTCR10_RUN *((volatile unsigned int*)(0x42762008UL)) +#define bFM4_RTC_WTCR10_SRST *((volatile unsigned int*)(0x4276200CUL)) +#define bFM4_RTC_WTCR10_SCST *((volatile unsigned int*)(0x42762010UL)) +#define bFM4_RTC_WTCR10_SCRST *((volatile unsigned int*)(0x42762014UL)) +#define bFM4_RTC_WTCR10_BUSY *((volatile unsigned int*)(0x42762018UL)) +#define bFM4_RTC_WTCR10_TRANS *((volatile unsigned int*)(0x4276201CUL)) +#define bFM4_RTC_WTCR11_MIEN *((volatile unsigned int*)(0x42762080UL)) +#define bFM4_RTC_WTCR11_HEN *((volatile unsigned int*)(0x42762084UL)) +#define bFM4_RTC_WTCR11_DEN *((volatile unsigned int*)(0x42762088UL)) +#define bFM4_RTC_WTCR11_MOEN *((volatile unsigned int*)(0x4276208CUL)) +#define bFM4_RTC_WTCR11_YEN *((volatile unsigned int*)(0x42762090UL)) +#define bFM4_RTC_WTCR12_INTSSI *((volatile unsigned int*)(0x42762100UL)) +#define bFM4_RTC_WTCR12_INTSI *((volatile unsigned int*)(0x42762104UL)) +#define bFM4_RTC_WTCR12_INTMI *((volatile unsigned int*)(0x42762108UL)) +#define bFM4_RTC_WTCR12_INTHI *((volatile unsigned int*)(0x4276210CUL)) +#define bFM4_RTC_WTCR12_INTTMI *((volatile unsigned int*)(0x42762110UL)) +#define bFM4_RTC_WTCR12_INTALI *((volatile unsigned int*)(0x42762114UL)) +#define bFM4_RTC_WTCR12_INTERI *((volatile unsigned int*)(0x42762118UL)) +#define bFM4_RTC_WTCR12_INTCRI *((volatile unsigned int*)(0x4276211CUL)) +#define bFM4_RTC_WTCR13_INTSSIE *((volatile unsigned int*)(0x42762180UL)) +#define bFM4_RTC_WTCR13_INTSIE *((volatile unsigned int*)(0x42762184UL)) +#define bFM4_RTC_WTCR13_INTMIE *((volatile unsigned int*)(0x42762188UL)) +#define bFM4_RTC_WTCR13_INTHIE *((volatile unsigned int*)(0x4276218CUL)) +#define bFM4_RTC_WTCR13_INTTMIE *((volatile unsigned int*)(0x42762190UL)) +#define bFM4_RTC_WTCR13_INTALIE *((volatile unsigned int*)(0x42762194UL)) +#define bFM4_RTC_WTCR13_INTERIE *((volatile unsigned int*)(0x42762198UL)) +#define bFM4_RTC_WTCR13_INTCRIE *((volatile unsigned int*)(0x4276219CUL)) +#define bFM4_RTC_WTCR20_CREAD *((volatile unsigned int*)(0x42762200UL)) +#define bFM4_RTC_WTCR20_CWRITE *((volatile unsigned int*)(0x42762204UL)) +#define bFM4_RTC_WTCR20_BREAD *((volatile unsigned int*)(0x42762208UL)) +#define bFM4_RTC_WTCR20_BWRITE *((volatile unsigned int*)(0x4276220CUL)) +#define bFM4_RTC_WTCR20_PREAD *((volatile unsigned int*)(0x42762210UL)) +#define bFM4_RTC_WTCR20_PWRITE *((volatile unsigned int*)(0x42762214UL)) +#define bFM4_RTC_WTCR21_TMST *((volatile unsigned int*)(0x42762280UL)) +#define bFM4_RTC_WTCR21_TMEN *((volatile unsigned int*)(0x42762284UL)) +#define bFM4_RTC_WTCR21_TMRUN *((volatile unsigned int*)(0x42762288UL)) +#define bFM4_RTC_WTSR_S0 *((volatile unsigned int*)(0x42762380UL)) +#define bFM4_RTC_WTSR_S1 *((volatile unsigned int*)(0x42762384UL)) +#define bFM4_RTC_WTSR_S2 *((volatile unsigned int*)(0x42762388UL)) +#define bFM4_RTC_WTSR_S3 *((volatile unsigned int*)(0x4276238CUL)) +#define bFM4_RTC_WTSR_TS0 *((volatile unsigned int*)(0x42762390UL)) +#define bFM4_RTC_WTSR_TS1 *((volatile unsigned int*)(0x42762394UL)) +#define bFM4_RTC_WTSR_TS2 *((volatile unsigned int*)(0x42762398UL)) +#define bFM4_RTC_WTMIR_MI0 *((volatile unsigned int*)(0x42762400UL)) +#define bFM4_RTC_WTMIR_MI1 *((volatile unsigned int*)(0x42762404UL)) +#define bFM4_RTC_WTMIR_MI2 *((volatile unsigned int*)(0x42762408UL)) +#define bFM4_RTC_WTMIR_MI3 *((volatile unsigned int*)(0x4276240CUL)) +#define bFM4_RTC_WTMIR_TMI0 *((volatile unsigned int*)(0x42762410UL)) +#define bFM4_RTC_WTMIR_TMI1 *((volatile unsigned int*)(0x42762414UL)) +#define bFM4_RTC_WTMIR_TMI2 *((volatile unsigned int*)(0x42762418UL)) +#define bFM4_RTC_WTHR_H0 *((volatile unsigned int*)(0x42762480UL)) +#define bFM4_RTC_WTHR_H1 *((volatile unsigned int*)(0x42762484UL)) +#define bFM4_RTC_WTHR_H2 *((volatile unsigned int*)(0x42762488UL)) +#define bFM4_RTC_WTHR_H3 *((volatile unsigned int*)(0x4276248CUL)) +#define bFM4_RTC_WTHR_TH0 *((volatile unsigned int*)(0x42762490UL)) +#define bFM4_RTC_WTHR_TH1 *((volatile unsigned int*)(0x42762494UL)) +#define bFM4_RTC_WTDR_D0 *((volatile unsigned int*)(0x42762500UL)) +#define bFM4_RTC_WTDR_D1 *((volatile unsigned int*)(0x42762504UL)) +#define bFM4_RTC_WTDR_D2 *((volatile unsigned int*)(0x42762508UL)) +#define bFM4_RTC_WTDR_D3 *((volatile unsigned int*)(0x4276250CUL)) +#define bFM4_RTC_WTDR_TD0 *((volatile unsigned int*)(0x42762510UL)) +#define bFM4_RTC_WTDR_TD1 *((volatile unsigned int*)(0x42762514UL)) +#define bFM4_RTC_WTDW_DW0 *((volatile unsigned int*)(0x42762580UL)) +#define bFM4_RTC_WTDW_DW1 *((volatile unsigned int*)(0x42762584UL)) +#define bFM4_RTC_WTDW_DW2 *((volatile unsigned int*)(0x42762588UL)) +#define bFM4_RTC_WTMOR_MO0 *((volatile unsigned int*)(0x42762600UL)) +#define bFM4_RTC_WTMOR_MO1 *((volatile unsigned int*)(0x42762604UL)) +#define bFM4_RTC_WTMOR_MO2 *((volatile unsigned int*)(0x42762608UL)) +#define bFM4_RTC_WTMOR_MO3 *((volatile unsigned int*)(0x4276260CUL)) +#define bFM4_RTC_WTMOR_TMO *((volatile unsigned int*)(0x42762610UL)) +#define bFM4_RTC_WTYR_Y0 *((volatile unsigned int*)(0x42762680UL)) +#define bFM4_RTC_WTYR_Y1 *((volatile unsigned int*)(0x42762684UL)) +#define bFM4_RTC_WTYR_Y2 *((volatile unsigned int*)(0x42762688UL)) +#define bFM4_RTC_WTYR_Y3 *((volatile unsigned int*)(0x4276268CUL)) +#define bFM4_RTC_WTYR_TY0 *((volatile unsigned int*)(0x42762690UL)) +#define bFM4_RTC_WTYR_TY1 *((volatile unsigned int*)(0x42762694UL)) +#define bFM4_RTC_WTYR_TY2 *((volatile unsigned int*)(0x42762698UL)) +#define bFM4_RTC_WTYR_TY3 *((volatile unsigned int*)(0x4276269CUL)) +#define bFM4_RTC_ALMIR_AMI0 *((volatile unsigned int*)(0x42762700UL)) +#define bFM4_RTC_ALMIR_AMI1 *((volatile unsigned int*)(0x42762704UL)) +#define bFM4_RTC_ALMIR_AMI2 *((volatile unsigned int*)(0x42762708UL)) +#define bFM4_RTC_ALMIR_AMI3 *((volatile unsigned int*)(0x4276270CUL)) +#define bFM4_RTC_ALMIR_TAMI0 *((volatile unsigned int*)(0x42762710UL)) +#define bFM4_RTC_ALMIR_TAMI1 *((volatile unsigned int*)(0x42762714UL)) +#define bFM4_RTC_ALMIR_TAMI2 *((volatile unsigned int*)(0x42762718UL)) +#define bFM4_RTC_ALHR_AH0 *((volatile unsigned int*)(0x42762780UL)) +#define bFM4_RTC_ALHR_AH1 *((volatile unsigned int*)(0x42762784UL)) +#define bFM4_RTC_ALHR_AH2 *((volatile unsigned int*)(0x42762788UL)) +#define bFM4_RTC_ALHR_AH3 *((volatile unsigned int*)(0x4276278CUL)) +#define bFM4_RTC_ALHR_TAH0 *((volatile unsigned int*)(0x42762790UL)) +#define bFM4_RTC_ALHR_TAH1 *((volatile unsigned int*)(0x42762794UL)) +#define bFM4_RTC_ALDR_AD0 *((volatile unsigned int*)(0x42762800UL)) +#define bFM4_RTC_ALDR_AD1 *((volatile unsigned int*)(0x42762804UL)) +#define bFM4_RTC_ALDR_AD2 *((volatile unsigned int*)(0x42762808UL)) +#define bFM4_RTC_ALDR_AD3 *((volatile unsigned int*)(0x4276280CUL)) +#define bFM4_RTC_ALDR_TAD0 *((volatile unsigned int*)(0x42762810UL)) +#define bFM4_RTC_ALDR_TAD1 *((volatile unsigned int*)(0x42762814UL)) +#define bFM4_RTC_ALMOR_AMO0 *((volatile unsigned int*)(0x42762880UL)) +#define bFM4_RTC_ALMOR_AMO1 *((volatile unsigned int*)(0x42762884UL)) +#define bFM4_RTC_ALMOR_AMO2 *((volatile unsigned int*)(0x42762888UL)) +#define bFM4_RTC_ALMOR_AMO3 *((volatile unsigned int*)(0x4276288CUL)) +#define bFM4_RTC_ALMOR_TAMO *((volatile unsigned int*)(0x42762890UL)) +#define bFM4_RTC_ALYR_AY0 *((volatile unsigned int*)(0x42762900UL)) +#define bFM4_RTC_ALYR_AY1 *((volatile unsigned int*)(0x42762904UL)) +#define bFM4_RTC_ALYR_AY2 *((volatile unsigned int*)(0x42762908UL)) +#define bFM4_RTC_ALYR_AY3 *((volatile unsigned int*)(0x4276290CUL)) +#define bFM4_RTC_ALYR_TAY0 *((volatile unsigned int*)(0x42762910UL)) +#define bFM4_RTC_ALYR_TAY1 *((volatile unsigned int*)(0x42762914UL)) +#define bFM4_RTC_ALYR_TAY2 *((volatile unsigned int*)(0x42762918UL)) +#define bFM4_RTC_ALYR_TAY3 *((volatile unsigned int*)(0x4276291CUL)) +#define bFM4_RTC_WTTR0_TM0 *((volatile unsigned int*)(0x42762980UL)) +#define bFM4_RTC_WTTR0_TM1 *((volatile unsigned int*)(0x42762984UL)) +#define bFM4_RTC_WTTR0_TM2 *((volatile unsigned int*)(0x42762988UL)) +#define bFM4_RTC_WTTR0_TM3 *((volatile unsigned int*)(0x4276298CUL)) +#define bFM4_RTC_WTTR0_TM4 *((volatile unsigned int*)(0x42762990UL)) +#define bFM4_RTC_WTTR0_TM5 *((volatile unsigned int*)(0x42762994UL)) +#define bFM4_RTC_WTTR0_TM6 *((volatile unsigned int*)(0x42762998UL)) +#define bFM4_RTC_WTTR0_TM7 *((volatile unsigned int*)(0x4276299CUL)) +#define bFM4_RTC_WTTR1_TM8 *((volatile unsigned int*)(0x42762A00UL)) +#define bFM4_RTC_WTTR1_TM9 *((volatile unsigned int*)(0x42762A04UL)) +#define bFM4_RTC_WTTR1_TM10 *((volatile unsigned int*)(0x42762A08UL)) +#define bFM4_RTC_WTTR1_TM11 *((volatile unsigned int*)(0x42762A0CUL)) +#define bFM4_RTC_WTTR1_TM12 *((volatile unsigned int*)(0x42762A10UL)) +#define bFM4_RTC_WTTR1_TM13 *((volatile unsigned int*)(0x42762A14UL)) +#define bFM4_RTC_WTTR1_TM14 *((volatile unsigned int*)(0x42762A18UL)) +#define bFM4_RTC_WTTR1_TM15 *((volatile unsigned int*)(0x42762A1CUL)) +#define bFM4_RTC_WTTR2_TM16 *((volatile unsigned int*)(0x42762A80UL)) +#define bFM4_RTC_WTTR2_TM17 *((volatile unsigned int*)(0x42762A84UL)) +#define bFM4_RTC_WTCAL1_WTCAL10 *((volatile unsigned int*)(0x42762B80UL)) +#define bFM4_RTC_WTCAL1_WTCAL11 *((volatile unsigned int*)(0x42762B84UL)) +#define bFM4_RTC_WTCALEN_WTCALEN *((volatile unsigned int*)(0x42762C00UL)) +#define bFM4_RTC_WTDIV_WTDIV0 *((volatile unsigned int*)(0x42762C80UL)) +#define bFM4_RTC_WTDIV_WTDIV1 *((volatile unsigned int*)(0x42762C84UL)) +#define bFM4_RTC_WTDIV_WTDIV2 *((volatile unsigned int*)(0x42762C88UL)) +#define bFM4_RTC_WTDIV_WTDIV3 *((volatile unsigned int*)(0x42762C8CUL)) +#define bFM4_RTC_WTDIVEN_WTDIVEN *((volatile unsigned int*)(0x42762D00UL)) +#define bFM4_RTC_WTDIVEN_WTDIVRDY *((volatile unsigned int*)(0x42762D04UL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD0 *((volatile unsigned int*)(0x42762D80UL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD1 *((volatile unsigned int*)(0x42762D84UL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD2 *((volatile unsigned int*)(0x42762D88UL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD3 *((volatile unsigned int*)(0x42762D8CUL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD4 *((volatile unsigned int*)(0x42762D90UL)) +#define bFM4_RTC_WTCALPRD_WTCALPRD5 *((volatile unsigned int*)(0x42762D94UL)) +#define bFM4_RTC_WTCOSEL_WTCOSEL *((volatile unsigned int*)(0x42762E00UL)) +#define bFM4_RTC_VB_CLKDIV_DIV0 *((volatile unsigned int*)(0x42762E80UL)) +#define bFM4_RTC_VB_CLKDIV_DIV1 *((volatile unsigned int*)(0x42762E84UL)) +#define bFM4_RTC_VB_CLKDIV_DIV2 *((volatile unsigned int*)(0x42762E88UL)) +#define bFM4_RTC_VB_CLKDIV_DIV3 *((volatile unsigned int*)(0x42762E8CUL)) +#define bFM4_RTC_VB_CLKDIV_DIV4 *((volatile unsigned int*)(0x42762E90UL)) +#define bFM4_RTC_VB_CLKDIV_DIV5 *((volatile unsigned int*)(0x42762E94UL)) +#define bFM4_RTC_VB_CLKDIV_DIV6 *((volatile unsigned int*)(0x42762E98UL)) +#define bFM4_RTC_VB_CLKDIV_DIV7 *((volatile unsigned int*)(0x42762E9CUL)) +#define bFM4_RTC_WTOSCCNT_SOSCEX *((volatile unsigned int*)(0x42762F00UL)) +#define bFM4_RTC_WTOSCCNT_SOSCNTL *((volatile unsigned int*)(0x42762F04UL)) +#define bFM4_RTC_BOOST_BOOST0 *((volatile unsigned int*)(0x42763100UL)) +#define bFM4_RTC_BOOST_BOOST1 *((volatile unsigned int*)(0x42763104UL)) +#define bFM4_RTC_EWKUP_WUP0 *((volatile unsigned int*)(0x42763180UL)) +#define bFM4_RTC_VDET_PON *((volatile unsigned int*)(0x4276321CUL)) +#define bFM4_RTC_HIBRST_HIBRST *((volatile unsigned int*)(0x42763300UL)) +#define bFM4_RTC_VBPFR_VPFR0 *((volatile unsigned int*)(0x42763380UL)) +#define bFM4_RTC_VBPFR_VPFR1 *((volatile unsigned int*)(0x42763384UL)) +#define bFM4_RTC_VBPFR_VPFR2 *((volatile unsigned int*)(0x42763388UL)) +#define bFM4_RTC_VBPFR_VPFR3 *((volatile unsigned int*)(0x4276338CUL)) +#define bFM4_RTC_VBPFR_SPSR0 *((volatile unsigned int*)(0x42763390UL)) +#define bFM4_RTC_VBPFR_SPSR1 *((volatile unsigned int*)(0x42763394UL)) +#define bFM4_RTC_VBPCR_VPCR0 *((volatile unsigned int*)(0x42763400UL)) +#define bFM4_RTC_VBPCR_VPCR1 *((volatile unsigned int*)(0x42763404UL)) +#define bFM4_RTC_VBPCR_VPCR2 *((volatile unsigned int*)(0x42763408UL)) +#define bFM4_RTC_VBPCR_VPCR3 *((volatile unsigned int*)(0x4276340CUL)) +#define bFM4_RTC_VBDDR_VDDR0 *((volatile unsigned int*)(0x42763480UL)) +#define bFM4_RTC_VBDDR_VDDR1 *((volatile unsigned int*)(0x42763484UL)) +#define bFM4_RTC_VBDDR_VDDR2 *((volatile unsigned int*)(0x42763488UL)) +#define bFM4_RTC_VBDDR_VDDR3 *((volatile unsigned int*)(0x4276348CUL)) +#define bFM4_RTC_VBDIR_VDIR0 *((volatile unsigned int*)(0x42763500UL)) +#define bFM4_RTC_VBDIR_VDIR1 *((volatile unsigned int*)(0x42763504UL)) +#define bFM4_RTC_VBDIR_VDIR2 *((volatile unsigned int*)(0x42763508UL)) +#define bFM4_RTC_VBDIR_VDIR3 *((volatile unsigned int*)(0x4276350CUL)) +#define bFM4_RTC_VBDOR_VDOR0 *((volatile unsigned int*)(0x42763580UL)) +#define bFM4_RTC_VBDOR_VDOR1 *((volatile unsigned int*)(0x42763584UL)) +#define bFM4_RTC_VBDOR_VDOR2 *((volatile unsigned int*)(0x42763588UL)) +#define bFM4_RTC_VBDOR_VDOR3 *((volatile unsigned int*)(0x4276358CUL)) +#define bFM4_RTC_VBPZR_VPZR0 *((volatile unsigned int*)(0x42763600UL)) +#define bFM4_RTC_VBPZR_VPZR1 *((volatile unsigned int*)(0x42763604UL)) + +/* Low-speed CR prescaler registers */ +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD0 *((volatile unsigned int*)(0x42780000UL)) +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD1 *((volatile unsigned int*)(0x42780004UL)) +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD2 *((volatile unsigned int*)(0x42780008UL)) +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD3 *((volatile unsigned int*)(0x4278000CUL)) +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD4 *((volatile unsigned int*)(0x42780010UL)) +#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD5 *((volatile unsigned int*)(0x42780014UL)) + +/* Peripheral Clock Gating registers */ +#define bFM4_CLK_GATING_CKEN0_MFSCK0 *((volatile unsigned int*)(0x42782000UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK1 *((volatile unsigned int*)(0x42782004UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK2 *((volatile unsigned int*)(0x42782008UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK3 *((volatile unsigned int*)(0x4278200CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK4 *((volatile unsigned int*)(0x42782010UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK5 *((volatile unsigned int*)(0x42782014UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK6 *((volatile unsigned int*)(0x42782018UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK7 *((volatile unsigned int*)(0x4278201CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK8 *((volatile unsigned int*)(0x42782020UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK9 *((volatile unsigned int*)(0x42782024UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK10 *((volatile unsigned int*)(0x42782028UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK11 *((volatile unsigned int*)(0x4278202CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK12 *((volatile unsigned int*)(0x42782030UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK13 *((volatile unsigned int*)(0x42782034UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK14 *((volatile unsigned int*)(0x42782038UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK15 *((volatile unsigned int*)(0x4278203CUL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK0 *((volatile unsigned int*)(0x42782040UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK1 *((volatile unsigned int*)(0x42782044UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK2 *((volatile unsigned int*)(0x42782048UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK3 *((volatile unsigned int*)(0x4278204CUL)) +#define bFM4_CLK_GATING_CKEN0_DMACK *((volatile unsigned int*)(0x42782060UL)) +#define bFM4_CLK_GATING_CKEN0_EXBCK *((volatile unsigned int*)(0x42782068UL)) +#define bFM4_CLK_GATING_CKEN0_GIOCK *((volatile unsigned int*)(0x42782070UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST0 *((volatile unsigned int*)(0x42782080UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST1 *((volatile unsigned int*)(0x42782084UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST2 *((volatile unsigned int*)(0x42782088UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST3 *((volatile unsigned int*)(0x4278208CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST4 *((volatile unsigned int*)(0x42782090UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST5 *((volatile unsigned int*)(0x42782094UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST6 *((volatile unsigned int*)(0x42782098UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST7 *((volatile unsigned int*)(0x4278209CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST8 *((volatile unsigned int*)(0x427820A0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST9 *((volatile unsigned int*)(0x427820A4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST10 *((volatile unsigned int*)(0x427820A8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST11 *((volatile unsigned int*)(0x427820ACUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST12 *((volatile unsigned int*)(0x427820B0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST13 *((volatile unsigned int*)(0x427820B4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST14 *((volatile unsigned int*)(0x427820B8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST15 *((volatile unsigned int*)(0x427820BCUL)) +#define bFM4_CLK_GATING_MRST0_ADCRST0 *((volatile unsigned int*)(0x427820C0UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST1 *((volatile unsigned int*)(0x427820C4UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST2 *((volatile unsigned int*)(0x427820C8UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST3 *((volatile unsigned int*)(0x427820CCUL)) +#define bFM4_CLK_GATING_MRST0_DMARST *((volatile unsigned int*)(0x427820E0UL)) +#define bFM4_CLK_GATING_MRST0_EXBRST *((volatile unsigned int*)(0x427820E8UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK0 *((volatile unsigned int*)(0x42782200UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK1 *((volatile unsigned int*)(0x42782204UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK2 *((volatile unsigned int*)(0x42782208UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK3 *((volatile unsigned int*)(0x4278220CUL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK0 *((volatile unsigned int*)(0x42782220UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK1 *((volatile unsigned int*)(0x42782224UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK2 *((volatile unsigned int*)(0x42782228UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK3 *((volatile unsigned int*)(0x4278222CUL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK0 *((volatile unsigned int*)(0x42782240UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK1 *((volatile unsigned int*)(0x42782244UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK2 *((volatile unsigned int*)(0x42782248UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK3 *((volatile unsigned int*)(0x4278224CUL)) +#define bFM4_CLK_GATING_MRST1_BTMRST0 *((volatile unsigned int*)(0x42782280UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST1 *((volatile unsigned int*)(0x42782284UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST2 *((volatile unsigned int*)(0x42782288UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST3 *((volatile unsigned int*)(0x4278228CUL)) +#define bFM4_CLK_GATING_MRST1_MFTRST0 *((volatile unsigned int*)(0x427822A0UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST1 *((volatile unsigned int*)(0x427822A4UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST2 *((volatile unsigned int*)(0x427822A8UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST3 *((volatile unsigned int*)(0x427822ACUL)) +#define bFM4_CLK_GATING_MRST1_QDURST0 *((volatile unsigned int*)(0x427822C0UL)) +#define bFM4_CLK_GATING_MRST1_QDURST1 *((volatile unsigned int*)(0x427822C4UL)) +#define bFM4_CLK_GATING_MRST1_QDURST2 *((volatile unsigned int*)(0x427822C8UL)) +#define bFM4_CLK_GATING_MRST1_QDURST3 *((volatile unsigned int*)(0x427822CCUL)) +#define bFM4_CLK_GATING_CKEN2_USBCK0 *((volatile unsigned int*)(0x42782400UL)) +#define bFM4_CLK_GATING_CKEN2_USBCK1 *((volatile unsigned int*)(0x42782404UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK0 *((volatile unsigned int*)(0x42782410UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK1 *((volatile unsigned int*)(0x42782414UL)) +#define bFM4_CLK_GATING_CKEN2_SDCCK *((volatile unsigned int*)(0x42782420UL)) +#define bFM4_CLK_GATING_MRST2_USBRST0 *((volatile unsigned int*)(0x42782480UL)) +#define bFM4_CLK_GATING_MRST2_USBRST1 *((volatile unsigned int*)(0x42782484UL)) +#define bFM4_CLK_GATING_MRST2_CANRST0 *((volatile unsigned int*)(0x42782490UL)) +#define bFM4_CLK_GATING_MRST2_CANRST1 *((volatile unsigned int*)(0x42782494UL)) +#define bFM4_CLK_GATING_MRST2_SDCRST *((volatile unsigned int*)(0x427824A0UL)) + +/* External bus interface registers */ +#define bFM4_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM4_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM4_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM4_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM4_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM4_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) +#define bFM4_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM4_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM4_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM4_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM4_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM4_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) +#define bFM4_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM4_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM4_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM4_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM4_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM4_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) +#define bFM4_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM4_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM4_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM4_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM4_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM4_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) +#define bFM4_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM4_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM4_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM4_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM4_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM4_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) +#define bFM4_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM4_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM4_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM4_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM4_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM4_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM4_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM4_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM4_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM4_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM4_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM4_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM4_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM4_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM4_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM4_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM4_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM4_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM4_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM4_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM4_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM4_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM4_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM4_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM4_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM4_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM4_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM4_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM4_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM4_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM4_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM4_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM4_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM4_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM4_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM4_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM4_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM4_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM4_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM4_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM4_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM4_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM4_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM4_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM4_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM4_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM4_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM4_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM4_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM4_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM4_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM4_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM4_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM4_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM4_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM4_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM4_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM4_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM4_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM4_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM4_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM4_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM4_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM4_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM4_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM4_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM4_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM4_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM4_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM4_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM4_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM4_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM4_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM4_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM4_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM4_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM4_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM4_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM4_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM4_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM4_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM4_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM4_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM4_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM4_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM4_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM4_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM4_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM4_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM4_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM4_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM4_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM4_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM4_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM4_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM4_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM4_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM4_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM4_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM4_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM4_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM4_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM4_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM4_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM4_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM4_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM4_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM4_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM4_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM4_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM4_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM4_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM4_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM4_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM4_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM4_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM4_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM4_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM4_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM4_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM4_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM4_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM4_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM4_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM4_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM4_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM4_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM4_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM4_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM4_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM4_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM4_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM4_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM4_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM4_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM4_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM4_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM4_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM4_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM4_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM4_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM4_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM4_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM4_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM4_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM4_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM4_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM4_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM4_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM4_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM4_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM4_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM4_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM4_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM4_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM4_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM4_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM4_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM4_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM4_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM4_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM4_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM4_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM4_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM4_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM4_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM4_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM4_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM4_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM4_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM4_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM4_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM4_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM4_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM4_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM4_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM4_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM4_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM4_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM4_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM4_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM4_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM4_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM4_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM4_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM4_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM4_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM4_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM4_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM4_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM4_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM4_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM4_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM4_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM4_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM4_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM4_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM4_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM4_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM4_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM4_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM4_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM4_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM4_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM4_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM4_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM4_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM4_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM4_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM4_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM4_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM4_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM4_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM4_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM4_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM4_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM4_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM4_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM4_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM4_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM4_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM4_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM4_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM4_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM4_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM4_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM4_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM4_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM4_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM4_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM4_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM4_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM4_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM4_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM4_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) + +/* USB channel 0 registers */ +#define bFM4_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM4_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM4_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM4_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM4_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM4_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM4_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM4_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM4_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM4_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM4_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM4_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM4_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM4_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM4_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM4_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM4_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM4_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM4_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM4_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM4_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM4_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM4_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM4_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM4_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM4_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM4_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM4_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM4_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM4_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM4_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM4_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM4_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM4_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM4_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM4_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM4_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM4_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM4_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM4_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM4_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM4_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM4_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM4_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM4_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM4_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM4_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM4_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM4_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM4_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM4_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM4_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM4_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM4_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM4_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM4_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM4_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM4_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM4_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM4_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM4_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM4_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM4_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM4_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM4_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM4_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM4_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM4_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM4_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM4_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM4_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM4_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM4_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM4_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM4_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM4_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM4_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM4_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM4_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM4_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM4_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM4_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM4_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM4_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM4_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM4_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM4_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM4_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM4_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM4_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM4_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM4_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM4_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM4_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM4_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM4_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM4_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM4_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM4_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM4_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM4_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM4_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM4_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM4_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM4_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM4_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM4_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM4_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM4_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM4_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM4_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM4_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM4_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM4_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM4_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM4_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM4_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM4_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM4_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM4_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM4_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM4_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM4_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM4_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM4_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM4_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM4_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM4_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM4_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM4_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM4_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM4_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM4_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM4_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM4_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM4_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM4_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM4_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM4_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM4_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM4_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM4_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM4_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM4_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM4_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM4_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM4_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM4_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM4_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM4_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM4_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM4_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM4_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM4_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM4_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM4_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM4_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM4_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM4_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM4_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM4_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM4_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM4_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM4_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM4_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM4_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM4_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM4_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM4_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM4_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM4_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM4_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM4_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM4_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM4_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM4_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM4_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM4_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM4_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM4_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM4_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM4_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM4_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM4_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM4_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM4_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM4_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM4_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM4_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM4_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM4_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM4_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM4_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM4_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM4_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM4_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM4_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM4_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM4_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM4_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM4_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM4_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM4_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM4_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM4_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM4_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM4_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM4_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM4_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM4_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM4_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM4_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM4_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM4_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM4_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM4_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM4_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM4_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM4_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM4_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM4_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM4_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM4_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM4_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM4_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM4_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM4_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM4_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM4_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM4_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM4_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM4_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM4_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM4_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM4_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM4_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM4_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM4_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM4_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM4_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM4_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM4_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM4_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM4_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM4_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM4_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM4_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM4_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM4_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM4_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM4_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM4_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM4_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM4_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM4_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM4_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM4_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM4_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM4_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM4_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM4_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM4_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM4_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM4_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM4_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM4_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM4_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM4_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM4_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM4_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM4_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM4_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM4_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM4_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM4_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM4_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM4_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM4_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM4_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM4_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM4_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) +#define bFM4_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM4_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM4_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM4_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM4_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM4_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM4_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM4_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM4_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM4_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM4_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM4_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM4_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM4_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM4_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM4_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM4_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM4_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM4_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM4_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM4_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM4_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM4_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM4_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM4_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM4_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM4_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM4_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM4_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM4_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM4_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM4_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM4_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM4_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM4_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM4_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM4_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM4_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM4_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM4_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM4_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM4_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM4_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM4_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM4_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM4_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM4_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM4_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM4_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM4_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM4_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM4_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM4_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM4_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM4_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM4_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM4_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM4_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* DMA controller */ +#define bFM4_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM4_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM4_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM4_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM4_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM4_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM4_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM4_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM4_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM4_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM4_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM4_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM4_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM4_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM4_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM4_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM4_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM4_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM4_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM4_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM4_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM4_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM4_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM4_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM4_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM4_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM4_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM4_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM4_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM4_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM4_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM4_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM4_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM4_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM4_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM4_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM4_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM4_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM4_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM4_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM4_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM4_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM4_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM4_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM4_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM4_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM4_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM4_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM4_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM4_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM4_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM4_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM4_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM4_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM4_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM4_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM4_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM4_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM4_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM4_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM4_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM4_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM4_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM4_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM4_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM4_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM4_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM4_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM4_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM4_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM4_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM4_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM4_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM4_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM4_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM4_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM4_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM4_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM4_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM4_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM4_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM4_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM4_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM4_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM4_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM4_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM4_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM4_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM4_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM4_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM4_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM4_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM4_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM4_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM4_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM4_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM4_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM4_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM4_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM4_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM4_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM4_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM4_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM4_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM4_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM4_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM4_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM4_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM4_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM4_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM4_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM4_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM4_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM4_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM4_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM4_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM4_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM4_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM4_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM4_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM4_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM4_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM4_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM4_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM4_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM4_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM4_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM4_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM4_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM4_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM4_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM4_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM4_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM4_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM4_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM4_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM4_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM4_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM4_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM4_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM4_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM4_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM4_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM4_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM4_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM4_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM4_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM4_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM4_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM4_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM4_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM4_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM4_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM4_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM4_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM4_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM4_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM4_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM4_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM4_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM4_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM4_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM4_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM4_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM4_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM4_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM4_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM4_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM4_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM4_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM4_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM4_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM4_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM4_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM4_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM4_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM4_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM4_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM4_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM4_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM4_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM4_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM4_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM4_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM4_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM4_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM4_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM4_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM4_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM4_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM4_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM4_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM4_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM4_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM4_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM4_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM4_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM4_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM4_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM4_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM4_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM4_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM4_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM4_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM4_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM4_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM4_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM4_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM4_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM4_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM4_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM4_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM4_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM4_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM4_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM4_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM4_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM4_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM4_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM4_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM4_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM4_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM4_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM4_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM4_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM4_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM4_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM4_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM4_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM4_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM4_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM4_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM4_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM4_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM4_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM4_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM4_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM4_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM4_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM4_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM4_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM4_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM4_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM4_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM4_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM4_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM4_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM4_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM4_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM4_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM4_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM4_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM4_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM4_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM4_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM4_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM4_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM4_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM4_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM4_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM4_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM4_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM4_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM4_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM4_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM4_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM4_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM4_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM4_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM4_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM4_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM4_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM4_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM4_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM4_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM4_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM4_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM4_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM4_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM4_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM4_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM4_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM4_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM4_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM4_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM4_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM4_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM4_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM4_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM4_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM4_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM4_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM4_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM4_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM4_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM4_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM4_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM4_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM4_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM4_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM4_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM4_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM4_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM4_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM4_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM4_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM4_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM4_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM4_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM4_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM4_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM4_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM4_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM4_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM4_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM4_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM4_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM4_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM4_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM4_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM4_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM4_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM4_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM4_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM4_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM4_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM4_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM4_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM4_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM4_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM4_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM4_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM4_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM4_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM4_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM4_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM4_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM4_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM4_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM4_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM4_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM4_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM4_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM4_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM4_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM4_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM4_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM4_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM4_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM4_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM4_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM4_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM4_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM4_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM4_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM4_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM4_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM4_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM4_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* CAN channel 0 registers */ +#define bFM4_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) +#define bFM4_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) +#define bFM4_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) +#define bFM4_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) +#define bFM4_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) +#define bFM4_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) +#define bFM4_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) +#define bFM4_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) +#define bFM4_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) +#define bFM4_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) +#define bFM4_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) +#define bFM4_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) +#define bFM4_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) +#define bFM4_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) +#define bFM4_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) +#define bFM4_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) +#define bFM4_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) +#define bFM4_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) +#define bFM4_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) +#define bFM4_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) +#define bFM4_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) +#define bFM4_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) +#define bFM4_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) +#define bFM4_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) +#define bFM4_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) +#define bFM4_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) +#define bFM4_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) +#define bFM4_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) +#define bFM4_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) +#define bFM4_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) +#define bFM4_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) +#define bFM4_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) +#define bFM4_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) +#define bFM4_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) +#define bFM4_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) +#define bFM4_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) +#define bFM4_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) +#define bFM4_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) +#define bFM4_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) +#define bFM4_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) +#define bFM4_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) +#define bFM4_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) +#define bFM4_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) +#define bFM4_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) +#define bFM4_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) +#define bFM4_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) +#define bFM4_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) +#define bFM4_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) +#define bFM4_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) +#define bFM4_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) +#define bFM4_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) +#define bFM4_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) +#define bFM4_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) +#define bFM4_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) +#define bFM4_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) +#define bFM4_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) +#define bFM4_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) +#define bFM4_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) +#define bFM4_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) +#define bFM4_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) +#define bFM4_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) +#define bFM4_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) +#define bFM4_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) +#define bFM4_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) +#define bFM4_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) +#define bFM4_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) +#define bFM4_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) +#define bFM4_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) +#define bFM4_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) +#define bFM4_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) +#define bFM4_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) +#define bFM4_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) +#define bFM4_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) +#define bFM4_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) +#define bFM4_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) +#define bFM4_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) +#define bFM4_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) +#define bFM4_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) +#define bFM4_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) +#define bFM4_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) +#define bFM4_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) +#define bFM4_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) +#define bFM4_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM4_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM4_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM4_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM4_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM4_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM4_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM4_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM4_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM4_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM4_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) +#define bFM4_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) +#define bFM4_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) +#define bFM4_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) +#define bFM4_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) +#define bFM4_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) +#define bFM4_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) +#define bFM4_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) +#define bFM4_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) +#define bFM4_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) +#define bFM4_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) +#define bFM4_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) +#define bFM4_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) +#define bFM4_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) +#define bFM4_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) +#define bFM4_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) +#define bFM4_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) +#define bFM4_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) +#define bFM4_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) +#define bFM4_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) +#define bFM4_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) +#define bFM4_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) +#define bFM4_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) +#define bFM4_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM4_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM4_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM4_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM4_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM4_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM4_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM4_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM4_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM4_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM4_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) +#define bFM4_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) +#define bFM4_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) +#define bFM4_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) +#define bFM4_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) +#define bFM4_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) +#define bFM4_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) +#define bFM4_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) +#define bFM4_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) +#define bFM4_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) +#define bFM4_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) +#define bFM4_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) +#define bFM4_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) +#define bFM4_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM4_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM4_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM4_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM4_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM4_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM4_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM4_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM4_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM4_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM4_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM4_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM4_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM4_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM4_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM4_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM4_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM4_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM4_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM4_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM4_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM4_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM4_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM4_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM4_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM4_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM4_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM4_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM4_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM4_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM4_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM4_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM4_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM4_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM4_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM4_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM4_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM4_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM4_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM4_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM4_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM4_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM4_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM4_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM4_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM4_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM4_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM4_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM4_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM4_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM4_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM4_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM4_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM4_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM4_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM4_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM4_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM4_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM4_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM4_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM4_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM4_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM4_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM4_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM4_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM4_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM4_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM4_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM4_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM4_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM4_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM4_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM4_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM4_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM4_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM4_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM4_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM4_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM4_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM4_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM4_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM4_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM4_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM4_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM4_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM4_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM4_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM4_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM4_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM4_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM4_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM4_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM4_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM4_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM4_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM4_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM4_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM4_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM4_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM4_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM4_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM4_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM4_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM4_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM4_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM4_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM4_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM4_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM4_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM4_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM4_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM4_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM4_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM4_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM4_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM4_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM4_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM4_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM4_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM4_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM4_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM4_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM4_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM4_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM4_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM4_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM4_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM4_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM4_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM4_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM4_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM4_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM4_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM4_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM4_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM4_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM4_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM4_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM4_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM4_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM4_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM4_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM4_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM4_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM4_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM4_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM4_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM4_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM4_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM4_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM4_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM4_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM4_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM4_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM4_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM4_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM4_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM4_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM4_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM4_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM4_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM4_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM4_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM4_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) + +/* CAN channel 1 registers */ +#define bFM4_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) +#define bFM4_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) +#define bFM4_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) +#define bFM4_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) +#define bFM4_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) +#define bFM4_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) +#define bFM4_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) +#define bFM4_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) +#define bFM4_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) +#define bFM4_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) +#define bFM4_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) +#define bFM4_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) +#define bFM4_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) +#define bFM4_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) +#define bFM4_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) +#define bFM4_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) +#define bFM4_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) +#define bFM4_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) +#define bFM4_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) +#define bFM4_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) +#define bFM4_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) +#define bFM4_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) +#define bFM4_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) +#define bFM4_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) +#define bFM4_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) +#define bFM4_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) +#define bFM4_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) +#define bFM4_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) +#define bFM4_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) +#define bFM4_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) +#define bFM4_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) +#define bFM4_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) +#define bFM4_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) +#define bFM4_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) +#define bFM4_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) +#define bFM4_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) +#define bFM4_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) +#define bFM4_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) +#define bFM4_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) +#define bFM4_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) +#define bFM4_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) +#define bFM4_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) +#define bFM4_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) +#define bFM4_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) +#define bFM4_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) +#define bFM4_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) +#define bFM4_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) +#define bFM4_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) +#define bFM4_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) +#define bFM4_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) +#define bFM4_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) +#define bFM4_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) +#define bFM4_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) +#define bFM4_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) +#define bFM4_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) +#define bFM4_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) +#define bFM4_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) +#define bFM4_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) +#define bFM4_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) +#define bFM4_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) +#define bFM4_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) +#define bFM4_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) +#define bFM4_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) +#define bFM4_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) +#define bFM4_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) +#define bFM4_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) +#define bFM4_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) +#define bFM4_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) +#define bFM4_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) +#define bFM4_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) +#define bFM4_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) +#define bFM4_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) +#define bFM4_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) +#define bFM4_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) +#define bFM4_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) +#define bFM4_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) +#define bFM4_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) +#define bFM4_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) +#define bFM4_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) +#define bFM4_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) +#define bFM4_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) +#define bFM4_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) +#define bFM4_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM4_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM4_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM4_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM4_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM4_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM4_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM4_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM4_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM4_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM4_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) +#define bFM4_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) +#define bFM4_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) +#define bFM4_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) +#define bFM4_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) +#define bFM4_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) +#define bFM4_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) +#define bFM4_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) +#define bFM4_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) +#define bFM4_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) +#define bFM4_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) +#define bFM4_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) +#define bFM4_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) +#define bFM4_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) +#define bFM4_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) +#define bFM4_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) +#define bFM4_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) +#define bFM4_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) +#define bFM4_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) +#define bFM4_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) +#define bFM4_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) +#define bFM4_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) +#define bFM4_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) +#define bFM4_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM4_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM4_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM4_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM4_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM4_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM4_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM4_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM4_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM4_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM4_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) +#define bFM4_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) +#define bFM4_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) +#define bFM4_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) +#define bFM4_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) +#define bFM4_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) +#define bFM4_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) +#define bFM4_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) +#define bFM4_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) +#define bFM4_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) +#define bFM4_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) +#define bFM4_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) +#define bFM4_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) +#define bFM4_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM4_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM4_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM4_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM4_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM4_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM4_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM4_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM4_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM4_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM4_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM4_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM4_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM4_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM4_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM4_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM4_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM4_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM4_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM4_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM4_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM4_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM4_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM4_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM4_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM4_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM4_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM4_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM4_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM4_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM4_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM4_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM4_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM4_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM4_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM4_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM4_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM4_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM4_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM4_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM4_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM4_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM4_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM4_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM4_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM4_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM4_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM4_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM4_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM4_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM4_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM4_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM4_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM4_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM4_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM4_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM4_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM4_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM4_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM4_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM4_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM4_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM4_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM4_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM4_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM4_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM4_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM4_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM4_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM4_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM4_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM4_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM4_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM4_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM4_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM4_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM4_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM4_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM4_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM4_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM4_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM4_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM4_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM4_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM4_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM4_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM4_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM4_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM4_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM4_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM4_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM4_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM4_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM4_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM4_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM4_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM4_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM4_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM4_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM4_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM4_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM4_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM4_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM4_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM4_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM4_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM4_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM4_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM4_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM4_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM4_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM4_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM4_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM4_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM4_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM4_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM4_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM4_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM4_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM4_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM4_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM4_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM4_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM4_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM4_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM4_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM4_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM4_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM4_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM4_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM4_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM4_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM4_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM4_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM4_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM4_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM4_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM4_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM4_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM4_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM4_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM4_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM4_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM4_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM4_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM4_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM4_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM4_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM4_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM4_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM4_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM4_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM4_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM4_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM4_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM4_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM4_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM4_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM4_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM4_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM4_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM4_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM4_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM4_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) + +/* SD IF registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9B560R_H_ */ + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c new file mode 100644 index 0000000000..f58f1ac2ad --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c @@ -0,0 +1,240 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/** + ****************************************************************************** + ** \file system_mb9abxxx.c + ** + ** FM3 system initialization functions + ** All adjustments can be done in belonging header file. + ** + ** History: + ** 2013-01-21 0.1 MWi AI: Unification to be done + ** 2013-01-23 0.2 MWi mcu.h inclusion changed to pdl.h + ** 2013-06-28 0.3 EH Added Trace Buffer enable + ******************************************************************************/ + +#include "mcu.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = __HCLK; + +/** + ****************************************************************************** + ** \brief Update the System Core Clock with current core Clock retrieved from + ** cpu registers. + ** \param none + ** \return none + ******************************************************************************/ +void SystemCoreClockUpdate (void) { + uint32_t masterClk; + uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance + + switch ((FM4_CRG->SCM_CTL >> 5U) & 0x07U) { + case 0u: /* internal High-speed Cr osc. */ + masterClk = __CLKHC; + break; + + case 1u: /* external main osc. */ + masterClk = __CLKMO; + break; + + case 2u: /* PLL clock */ + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violation: + // "Unordered accesses to a volatile location" + u32RegisterRead = (__CLKMO * (((uint32_t)(FM4_CRG->PLL_CTL2) & 0x3Fu) + 1u)); + masterClk = (u32RegisterRead / ((((uint32_t)(FM4_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u)); + break; + + case 4u: /* internal Low-speed CR osc. */ + masterClk = __CLKLC; + break; + + case 5u: /* external Sub osc. */ + masterClk = __CLKSO; + break; + + default: + masterClk = 0ul; + break; + } + + switch (FM4_CRG->BSC_PSR & 0x07u) { + case 0u: + SystemCoreClock = masterClk; + break; + + case 1u: + SystemCoreClock = masterClk / 2u; + break; + + case 2u: + SystemCoreClock = masterClk / 3u; + break; + + case 3u: + SystemCoreClock = masterClk / 4u; + break; + + case 4u: + SystemCoreClock = masterClk / 6u; + break; + + case 5u: + SystemCoreClock = masterClk /8u; + break; + + case 6u: + SystemCoreClock = masterClk /16u; + break; + + default: + SystemCoreClock = 0ul; + break; + } + +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit (void) { + + static uint8_t u8IoRegisterRead; // Workaround variable for MISRA C rule conformance + +#if (HWWD_DISABLE) /* HW Watchdog Disable */ + FM4_HWWDT->WDG_LCK = 0x1ACCE551u; /* HW Watchdog Unlock */ + FM4_HWWDT->WDG_LCK = 0xE5331AAEu; + FM4_HWWDT->WDG_CTL = 0u; /* HW Watchdog stop */ +#endif + +#if (TRACE_BUFFER_ENABLE) + FM4_FLASH_IF->FBFCR = 0x01; /* Trace Buffer enable */ +#endif + +#if (CLOCK_SETUP) /* Clock Setup */ + FM4_CRG->BSC_PSR = (uint8_t)BSC_PSR_Val; /* set System Clock presacaler */ + FM4_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val; /* set APB0 presacaler */ + FM4_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val; /* set APB1 presacaler */ + FM4_CRG->APBC2_PSR = (uint8_t)APBC2_PSR_Val; /* set APB2 presacaler */ + FM4_CRG->SWC_PSR = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */ + FM4_CRG->TTC_PSR = (uint8_t)TTC_PSR_Val; /* set Trace Clock presacaler */ + + FM4_CRG->CSW_TMR = (uint8_t)CSW_TMR_Val; /* set oscillation stabilization wait time */ + + if (SCM_CTL_Val & (1ul << 1u)) { /* Main clock oscillator enabled ? */ + FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 1u); /* enable main oscillator */ + + while (!((FM4_CRG->SCM_STR) & (uint8_t)(1ul << 1u))) /* wait for Main clock oscillation stable */ + {} + } + + if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ + // Initialize VBAT (Temporary process) + FM4_RTC->VDET = 0x00; + FM4_RTC->VBPFR = 0x1C; + FM4_RTC->CCB = 0x10; + FM4_RTC->CCS = 0x08; + + // VB_CLK is less or equal to 1MHz (Temporary process) + FM4_RTC->VB_CLKDIV = 0x4E; + FM4_RTC->BOOST = 0x03; + + // Enable SUB CLK oscilation (Temporary process) + FM4_RTC->WTOSCCNT_f.SOSCEX = 0; + FM4_RTC->WTOSCCNT_f.SOSCNTL = 1; + + // Transmit to VBAT domain (Temporary process) + FM4_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0 != FM4_RTC->WTCR10_f.TRANS) + + FM4_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ + while (!(FM4_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ + } + + FM4_CRG->PSW_TMR = (uint8_t)PSW_TMR_Val; /* set PLL stabilization wait time */ + FM4_CRG->PLL_CTL1 = (uint8_t) PLL_CTL1_Val; /* set PLLM and PLLK */ + FM4_CRG->PLL_CTL2 = (uint8_t)PLL_CTL2_Val; /* set PLLN */ + + if (SCM_CTL_Val & (uint8_t)(1ul << 4u)) { /* PLL enabled ? */ + FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 4u); /* enable PLL */ + while (!(FM4_CRG->SCM_STR & (uint8_t)(1ul << 4u))) /* wait for PLL stable */ + {} + } + + FM4_CRG->SCM_CTL |= (uint8_t)(SCM_CTL_Val & 0xE0u); /* Set Master Clock switch */ + + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violations: + // "Unordered reads and writes to or from same location" and + // "Unordered accesses to a volatile location" + do + { + u8IoRegisterRead = (FM4_CRG->SCM_CTL & 0xE0u); + }while ((FM4_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead); +#endif // (CLOCK_SETUP) + +#if (CR_TRIM_SETUP) + /* CR Trimming Data */ + if( 0x000003FFu != (FM4_FLASH_IF->CRTRMM & 0x000003FFu) ) + { + /* UnLock (MCR_FTRM) */ + FM4_CRTRIM->MCR_RLR = (uint32_t)0x1ACCE554u; + /* Set MCR_FTRM */ + FM4_CRTRIM->MCR_FTRM = (uint16_t)FM4_FLASH_IF->CRTRMM; + /* Lock (MCR_FTRM) */ + FM4_CRTRIM->MCR_RLR = (uint32_t)0x00000000u; + } +#endif // (CR_TRIM_SETUP) +} + + + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h new file mode 100644 index 0000000000..23cd07d188 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h @@ -0,0 +1,674 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/******************************************************************************/ +/** \file system_mb9bf56xr.h + ** + ** Headerfile for FM4 system parameters + ** + ** History: + ** 2013-01-21 0.1 MWi AI: Unification to be done + ** 2013-02-06 0.2 MWi CMSIS coding restored; unifying still to be done + ** 2013-06-28 0.3 EH Added Trace Buffer enable definition + ** 2013-08-15 0.4 EH Changed APB1 Prescaler value + ******************************************************************************/ + +#ifndef _SYSTEM_MB9ABXXX_H_ +#define _SYSTEM_MB9ABXXX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup Enable + ** (USER SETTING) + ** + ** - 0 = No clock setup done by system_mb9xfxxx.c + ** - 1 = Clock setup done by system_mb9xfxxx.c + ******************************************************************************/ +#define CLOCK_SETUP 1 // <<< Define clock setup here + +/** + ****************************************************************************** + ** \brief External Main Clock Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKMO ( 4000000ul) // <<< External 4MHz Crystal + +/** + ****************************************************************************** + ** \brief External Sub Clock Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKSO ( 32768ul) // <<< External 32KHz Crystal + +/** + ****************************************************************************** + ** \brief System Clock Mode Control Register value definition + ** (USER SETTING) + ** + ** SCM_CTL + ** + ** Bit#7-5 : RCS[2:0] + ** - 0 = Internal high-speed CR oscillation (default) + ** - 1 = Main oscillation clock + ** - 2 = PLL oscillation clock + ** - 3 = (not allowed) + ** - 4 = Internal low-speed CR oscillation + ** - 5 = Sub clock oscillation + ** - 6 = (not allowed) + ** - 7 = (not allowed) + ** + ** Bit#4 : PLLE + ** - 0 = Disable PLL (default) + ** - 1 = Enable PLL + ** + ** Bit#3 : SOSCE + ** - 0 = Disable sub oscillation (default) + ** - 1 = Enable sub oscillation + ** + ** Bit#2 : (reserved) + ** + ** Bit#1 : MOSCE + ** - 0 = Disable main oscillation (default) + ** - 1 = Enable main oscillation + ** + ** Bit#0 : (reserved) + ******************************************************************************/ +#define SCM_CTL_Val 0x00000052ul // <<< Define SCM_CTL here + +/** + ****************************************************************************** + ** \brief Base Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** BSC_PSR + ** + ** Bit#7-3 : (reserved) + ** + ** Bit#2-0 : BSR[2:0] + ** - 0 = HCLK = Master Clock + ** - 1 = HCLK = Master Clock / 2 + ** - 2 = HCLK = Master Clock / 3 + ** - 3 = HCLK = Master Clock / 4 + ** - 4 = HCLK = Master Clock / 6 + ** - 5 = HCLK = Master Clock / 8 + ** - 6 = HCLK = Master Clock / 16 + ** - 7 = (reserved) + ******************************************************************************/ +#define BSC_PSR_Val 0x00000000ul // <<< Define BSC_PSR here + +/** + ****************************************************************************** + ** \brief APB0 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC0_PSR + ** + ** Bit#7-2 : (reserved) + ** + ** Bit#1-0 : BSR[2:0] + ** - 0 = PCLK0 = HCLK + ** - 1 = PCLK0 = HCLK / 2 + ** - 2 = PCLK0 = HCLK / 4 + ** - 3 = PCLK0 = HCLK / 8 + ******************************************************************************/ +#define APBC0_PSR_Val 0x00000001UL // <<< Define APBC0_PSR here + +/** + ****************************************************************************** + ** \brief APB1 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC1_PSR + ** + ** Bit#7 : APBC1EN + ** - 0 = Disable PCLK1 output + ** - 1 = Enables PCLK1 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC1RST + ** - 0 = APB1 bus reset, inactive (default) + ** - 1 = APB1 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC1[2:0] + ** - 0 = PCLK1 = HCLK + ** - 1 = PCLK1 = HCLK / 2 + ** - 2 = PCLK1 = HCLK / 4 + ** - 3 = PCLK1 = HCLK / 8 + ******************************************************************************/ +#define APBC1_PSR_Val 0x00000080ul // <<< Define APBC1_PSR here + +/** + ****************************************************************************** + ** \brief APB2 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC2_PSR + ** + ** Bit#7 : APBC2EN + ** - 0 = Disable PCLK2 output + ** - 1 = Enables PCLK2 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC2RST + ** - 0 = APB2 bus reset, inactive (default) + ** - 1 = APB2 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC2[1:0] + ** - 0 = PCLK2 = HCLK + ** - 1 = PCLK2 = HCLK / 2 + ** - 2 = PCLK2 = HCLK / 4 + ** - 3 = PCLK2 = HCLK / 8 + ******************************************************************************/ +#define APBC2_PSR_Val 0x00000081ul // <<< Define APBC2_PSR here + +/** + ****************************************************************************** + ** \brief Software Watchdog Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** SWC_PSR + ** + ** Bit#7 : TESTB + ** - 0 = (not allowed) + ** - 1 = (always write "1" to this bit) + ** + ** Bit#6-2 : (reserved) + ** + ** Bit#1-0 : SWDS[2:0] + ** - 0 = SWDGOGCLK = PCLK0 + ** - 1 = SWDGOGCLK = PCLK0 / 2 + ** - 2 = SWDGOGCLK = PCLK0 / 4 + ** - 3 = SWDGOGCLK = PCLK0 / 8 + ******************************************************************************/ +#define SWC_PSR_Val 0x00000003ul // <<< Define SWC_PSR here + +/** + ****************************************************************************** + ** \brief Trace Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** TTC_PSR + ** + ** Bit#7-1 : (reserved) + ** + ** Bit#0 : TTC + ** - 0 = TPIUCLK = HCLK + ** - 1 = TPIUCLK = HCLK / 2 + ******************************************************************************/ +#define TTC_PSR_Val 0x00000000ul // <<< Define TTC_PSR here + +/** + ****************************************************************************** + ** \brief Clock Stabilization Wait Time Register value definition + ** (USER SETTING) + ** + ** CSW_TMR + ** + ** Bit#7 : (reserved) + ** + ** Bit#6-4 : SOWT[2:0] + ** - 0 = ~10.3 ms (default) + ** - 1 = ~20.5 ms + ** - 2 = ~41 ms + ** - 3 = ~82 ms + ** - 4 = ~164 ms + ** - 5 = ~327 ms + ** - 6 = ~655 ms + ** - 7 = ~1.31 s + ** + ** Bit#3-0 : MOWT[3:0] + ** - 0 = ~500 ns (default) + ** - 1 = ~8 us + ** - 2 = ~16 us + ** - 3 = ~32 us + ** - 4 = ~64 us + ** - 5 = ~128 us + ** - 6 = ~256 us + ** - 7 = ~512 us + ** - 8 = ~1.0 ms + ** - 9 = ~2.0 ms + ** - 10 = ~4.0 ms + ** - 11 = ~8.0 ms + ** - 12 = ~33.0 ms + ** - 13 = ~131 ms + ** - 14 = ~524 ms + ** - 15 = ~2.0 s + ******************************************************************************/ +#define CSW_TMR_Val 0x0000005Cul // <<< Define CSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Clock Stabilization Wait Time Setup Register value definition + ** (USER SETTING) + ** + ** PSW_TMR + ** + ** Bit#7-5 : (reserved) + ** + ** Bit#4 : PINC + ** - 0 = Selects CLKMO (main oscillation) (default) + ** - 1 = (setting diabled) + ** + ** Bit#3 : (reserved) + ** + ** Bit#2-0 : POWT[2:0] + ** - 0 = ~128 us (default) + ** - 1 = ~256 us + ** - 2 = ~512 us + ** - 3 = ~1.02 ms + ** - 4 = ~2.05 ms + ** - 5 = ~4.10 ms + ** - 6 = ~8.20 ms + ** - 7 = ~16.40 ms + ******************************************************************************/ +#define PSW_TMR_Val 0x00000000ul // <<< Define PSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Control Register 1 value definition + ** (USER SETTING) + ** + ** PLL_CTL1 + ** + ** Bit#7-4 : PLLK[3:0] + ** - 0 = Division(PLLK) = 1/1 (default) + ** - 1 = Division(PLLK) = 1/2 + ** - 2 = Division(PLLK) = 1/3 + ** - . . . + ** - 15 = Division(PLLK) = 1/16 + ** + ** Bit#3-0 : PLLM[3:0] + ** - 0 = Division(PLLM) = 1/1 (default) + ** - 1 = Division(PLLM) = 1/2 + ** - 2 = Division(PLLM) = 1/3 + ** - . . . + ** - 15 = Division(PLLM) = 1/16 + ******************************************************************************/ +#define PLL_CTL1_Val 0x00000001ul // <<< Define PLL_CTL1 here + +/** + ****************************************************************************** + ** \brief PLL Control Register 2 value definition + ** (USER SETTING) + ** + ** PLL_CTL2 + ** + ** Bit#7-6 : (reserved) + ** + ** Bit#5-0 : PLLN[5:0] + ** - 0 = Division(PLLN) = 1/1 (default) + ** - 1 = Division(PLLN) = 1/2 + ** - 2 = Division(PLLN) = 1/3 + ** - . . . + ** - 63 = Division(PLLN) = 1/64 + ******************************************************************************/ +#define PLL_CTL2_Val 0x00000027ul // <<< Define PLL_CTL2 here + +/** + ****************************************************************************** + ** \brief Hardware Watchdog disable definition + ** (USER SETTING) + ** + ** - 0 = Hardware Watchdog enable + ** - 1 = Hardware Watchdog disable + ******************************************************************************/ +#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here + +/** + ****************************************************************************** + ** \brief Trimming CR + ** (USER SETTING) + ** + ** - 0 = CR is not trimmed at startup + ** - 1 = CR is trimmed at startup + ******************************************************************************/ +#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here + +/** + ****************************************************************************** + ** brief Trace Buffer enable definition + ** (USER SETTING) + ** + ** - 0 = Trace Buffer disable + ** - 1 = Trace Buffer enable + ******************************************************************************/ +#define TRACE_BUFFER_ENABLE 1 // <<< Define Trace Buffer enable here + + +/******************************************************************************/ +/* */ +/* END OF USER SETTINGS HERE */ +/* ========================= */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Device dependent System Clock absolute maximum ranges */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKHC ( 4000000ul) /* Internal 4MHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKLC ( 100000ul) /* Internal 100KHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Any case minimum Main Clock frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMIN ( 4000000ul) + +/** + ****************************************************************************** + ** \brief Maximum Main Clock frequency using external clock (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMAX ( 48000000ul) + +/** + ****************************************************************************** + ** \brief Any case minimum Sub Clock frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMIN ( 32000ul) + +/** + ****************************************************************************** + ** \brief Maximum Sub Clock frequency using external clock (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMAX ( 100000ul) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL input frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMIN ( 4000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL input frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMAX ( 16000000ul) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL oscillation frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMIN (200000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL oscillation frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMAX (320000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum System Clock frequency (HCLK) (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __HCLKMAX (160000000ul) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking range (clock settings). + ** + ** \return 0 Within range + ** \return 1 Out of range + ******************************************************************************/ +#define CHECK_RANGE(val, min, max) (((val) < (min)) || ((val) > (max))) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking bits with mask (clock settings). + ** Prevents from setting reserved bits by mistake. + ** + ** \return 0 All bits within mask + ** \return 1 One or more bits out of mask + ******************************************************************************/ +#define CHECK_RSVD(val, mask) ((val) & (mask)) + + +/******************************************************************************/ +/* Check register settings */ +/******************************************************************************/ +#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FAul)) + #error "SCM_CTL: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x10ul) != 0x10ul) + #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" +#endif + +#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007Ful)) + #error "CSW_TMR: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0x10ul)) /* if PLL is used */ + #if (CHECK_RSVD((PSW_TMR_Val), ~0x00000017ul)) + #error "PSW_TMR: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FFul)) + #error "PLL_CTL1: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003Ful)) + #error "PLL_CTL2: Invalid values of reserved bits!" + #endif +#endif + +#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007ul)) + #error "BSC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003ul)) + #error "APBC0_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000093ul)) + #error "APBC1_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000093ul)) + #error "APBC2_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003ul)) + #error "SWC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000003ul)) + #error "TTC_PSR: Invalid values of reserved bits!" +#endif + +/******************************************************************************/ +/* Define clocks with checking settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Calculate PLL K factor from settings + ******************************************************************************/ +#define __PLLK (((PLL_CTL1_Val >> 4ul) & 0x0Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL N factor from settings + ******************************************************************************/ +#define __PLLN (((PLL_CTL2_Val ) & 0x3Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL M factor from settings + ******************************************************************************/ +#define __PLLM (((PLL_CTL1_Val ) & 0x0Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL output frequency from settings + ******************************************************************************/ +#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) + +/******************************************************************************/ +/* Determine core clock frequency according to settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Define Master Clock from settings + ******************************************************************************/ +#if (((SCM_CTL_Val >> 5ul) & 0x07UL) == 0ul) + #define __MASTERCLK (__CLKHC) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 1ul) + #define __MASTERCLK (__CLKMO) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 2ul) + #define __MASTERCLK (__PLLCLK) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 4ul) + #define __MASTERCLK (__CLKLC) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 5ul) + #define __MASTERCLK (__CLKSO) +#else + #define __MASTERCLK (0UL) +#endif + +/** + ****************************************************************************** + ** \brief Define System Clock Frequency (Core Clock) from settings + ******************************************************************************/ +#if ((BSC_PSR_Val & 0x07UL) == 0ul) + #define __HCLK (__MASTERCLK / 1ul) +#elif ((BSC_PSR_Val & 0x07UL) == 1ul) + #define __HCLK (__MASTERCLK / 2ul) +#elif ((BSC_PSR_Val & 0x07UL) == 2ul) + #define __HCLK (__MASTERCLK / 3ul) +#elif ((BSC_PSR_Val & 0x07UL) == 3ul) + #define __HCLK (__MASTERCLK / 4ul) +#elif ((BSC_PSR_Val & 0x07UL) == 4ul) + #define __HCLK (__MASTERCLK / 6ul) +#elif ((BSC_PSR_Val & 0x07UL) == 5ul) + #define __HCLK (__MASTERCLK / 8ul) +#elif ((BSC_PSR_Val & 0x07UL) == 6ul) + #define __HCLK (__MASTERCLK /16ul) +#else + #define __HCLK (0ul) +#endif + +/******************************************************************************/ +/* HCLK range check */ +/******************************************************************************/ +#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX)) + #error "Main Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX)) + #error "Sub Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX)) + #error "PLL input frequency out of range!" +#endif + +#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX)) + #error "PLL oscillation frequency out of range!" +#endif + +#if (CHECK_RANGE(__HCLK, 0UL, __HCLKMAX)) + #error "System Clock (HCLK) out of range!" +#endif + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +extern void SystemInit (void); // Initialize the system + +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MB9ABXXX_H_ */ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_common_tables.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..7245c4f12b --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,35 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_math.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..ffa03b6fd1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/arm_math.h @@ -0,0 +1,7051 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 15. July 2011 + * $Revision: V1.0.10 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of modules each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Processor Support + * + * The library is completely written in C and is fully CMSIS compliant. + * High performance is achieved through maximum use of Cortex-M4 intrinsics. + * + * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, + * with the DSP intrinsics being emulated through software. + * + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.21. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * Each library project have differant pre-processor macros. + * + * ARM_MATH_CMx: + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * ARM_MATH_BIG_ENDIAN: + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * ARM_MATH_MATRIX_CHECK: + * Define macro for checking on the input and output sizes of matrices + * + * ARM_MATH_ROUNDING: + * Define macro for rounding on support functions + * + * __FPU_PRESENT: + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the #define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" + #include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#define PI 3.14159265358979f + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#define __SIMD32(addr) (*(int32_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ(q31_t data); + + + static __INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return(count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + + +#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; + float32_t x1; + float32_t xSpacing; + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t *pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t *pSrc, + uint32_t fftLen, + q31_t *pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + + #ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0 )* in ; + + #else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + #endif + + #ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0] ; + acc += (q31_t) S->A2 * S->state[1] ; + + #else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); + + #endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues-1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i +1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, + q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, float32_t *pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, q31_t *pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, q15_t *pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) + { + return(0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex-1) * S->numCols ; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex-1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm0.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..9d7a19f9ae --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm0.h @@ -0,0 +1,665 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm3.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..1c688181af --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm3.h @@ -0,0 +1,1236 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..bf022ba67f --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4.h @@ -0,0 +1,1378 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + + +/** \mainpage CMSIS Cortex-M4 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + - Cortex-M SIMD instructions + + The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks to define __FPU_USED */ + #define __FPU_USED 0 +#endif + +#include /*!< standard types definitions */ +#include /*!< Core Instruction Access */ +#include /*!< Core Function Access */ +#include /*!< Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU CMSIS FPU + Type definitions for the Cortex-M Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4_simd.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 0000000000..e7b6765225 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ +/* intrinsic __SADD8 see intrinsics.h */ +/* intrinsic __QADD8 see intrinsics.h */ +/* intrinsic __SHADD8 see intrinsics.h */ +/* intrinsic __UADD8 see intrinsics.h */ +/* intrinsic __UQADD8 see intrinsics.h */ +/* intrinsic __UHADD8 see intrinsics.h */ +/* intrinsic __SSUB8 see intrinsics.h */ +/* intrinsic __QSUB8 see intrinsics.h */ +/* intrinsic __SHSUB8 see intrinsics.h */ +/* intrinsic __USUB8 see intrinsics.h */ +/* intrinsic __UQSUB8 see intrinsics.h */ +/* intrinsic __UHSUB8 see intrinsics.h */ +/* intrinsic __SADD16 see intrinsics.h */ +/* intrinsic __QADD16 see intrinsics.h */ +/* intrinsic __SHADD16 see intrinsics.h */ +/* intrinsic __UADD16 see intrinsics.h */ +/* intrinsic __UQADD16 see intrinsics.h */ +/* intrinsic __UHADD16 see intrinsics.h */ +/* intrinsic __SSUB16 see intrinsics.h */ +/* intrinsic __QSUB16 see intrinsics.h */ +/* intrinsic __SHSUB16 see intrinsics.h */ +/* intrinsic __USUB16 see intrinsics.h */ +/* intrinsic __UQSUB16 see intrinsics.h */ +/* intrinsic __UHSUB16 see intrinsics.h */ +/* intrinsic __SASX see intrinsics.h */ +/* intrinsic __QASX see intrinsics.h */ +/* intrinsic __SHASX see intrinsics.h */ +/* intrinsic __UASX see intrinsics.h */ +/* intrinsic __UQASX see intrinsics.h */ +/* intrinsic __UHASX see intrinsics.h */ +/* intrinsic __SSAX see intrinsics.h */ +/* intrinsic __QSAX see intrinsics.h */ +/* intrinsic __SHSAX see intrinsics.h */ +/* intrinsic __USAX see intrinsics.h */ +/* intrinsic __UQSAX see intrinsics.h */ +/* intrinsic __UHSAX see intrinsics.h */ +/* intrinsic __USAD8 see intrinsics.h */ +/* intrinsic __USADA8 see intrinsics.h */ +/* intrinsic __SSAT16 see intrinsics.h */ +/* intrinsic __USAT16 see intrinsics.h */ +/* intrinsic __UXTB16 see intrinsics.h */ +/* intrinsic __SXTB16 see intrinsics.h */ +/* intrinsic __UXTAB16 see intrinsics.h */ +/* intrinsic __SXTAB16 see intrinsics.h */ +/* intrinsic __SMUAD see intrinsics.h */ +/* intrinsic __SMUADX see intrinsics.h */ +/* intrinsic __SMLAD see intrinsics.h */ +/* intrinsic __SMLADX see intrinsics.h */ +/* intrinsic __SMLALD see intrinsics.h */ +/* intrinsic __SMLALDX see intrinsics.h */ +/* intrinsic __SMUSD see intrinsics.h */ +/* intrinsic __SMUSDX see intrinsics.h */ +/* intrinsic __SMLSD see intrinsics.h */ +/* intrinsic __SMLSDX see intrinsics.h */ +/* intrinsic __SMLSLD see intrinsics.h */ +/* intrinsic __SMLSLDX see intrinsics.h */ +/* intrinsic __SEL see intrinsics.h */ +/* intrinsic __QADD see intrinsics.h */ +/* intrinsic __QSUB see intrinsics.h */ +/* intrinsic __PKHBT see intrinsics.h */ +/* intrinsic __PKHTB see intrinsics.h */ + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmFunc.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..88819f9dd1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,609 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmInstr.h b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..78d2ef80ba --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/SConscript b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/SConscript new file mode 100644 index 0000000000..6ab907fca5 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('DeviceSupport/*.c') + +CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport'] + +# add for startup script +if rtconfig.CROSS_TOOL == 'keil': + src += ['DeviceSupport/arm/startup_mb9bf56xr.s'] + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['DeviceSupport/gcc/startup_mb9bf56xr.S'] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf568r/SConscript b/bsp/fujitsu/mb9x/mb9bf568r/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/fujitsu/mb9x/mb9bf568r/SConstruct b/bsp/fujitsu/mb9x/mb9bf568r/SConstruct new file mode 100644 index 0000000000..1725b1f69c --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/SConstruct @@ -0,0 +1,36 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-fm4.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/fujitsu/mb9x/mb9bf568r/applications/SConscript b/bsp/fujitsu/mb9x/mb9bf568r/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf568r/applications/application.c b/bsp/fujitsu/mb9x/mb9bf568r/applications/application.c new file mode 100644 index 0000000000..12199175b2 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/applications/application.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-24 Bernard the first version + */ + +/** + * @addtogroup FM4 + */ +/*@{*/ + +#include +#include "board.h" + +void rt_init_thread_entry(void *parameter) +{ +#ifdef RT_USING_COMPONENTS_INIT + /* initialization RT-Thread Components */ + rt_components_init(); +#endif + + + //finsh_system_init(); +#if !defined(RT_USING_POSIX_STDIO) && defined(RT_USING_DEVICE) + finsh_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /**< init led device */ + { + extern void rt_led_hw_init(void); + rt_led_hw_init(); + } + +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 8, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/applications/startup.c b/bsp/fujitsu/mb9x/mb9bf568r/applications/startup.c new file mode 100644 index 0000000000..263bd20a28 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/applications/startup.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +/** + * @addtogroup FM4 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM4_SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM4_SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM4_SRAM_END); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init application */ + rt_application_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/SConscript b/bsp/fujitsu/mb9x/mb9bf568r/drivers/SConscript new file mode 100644 index 0000000000..5bbef48785 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.c b/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.c new file mode 100644 index 0000000000..bd44ad80b1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +#include "serial.h" + +/** + * @addtogroup FM4 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This fucntion returns milliseconds since system passed + */ +rt_uint32_t rt_hw_tick_get_millisecond(void) +{ + rt_tick_t tick; + rt_uint32_t value; + +#define TICK_MS (1000/RT_TICK_PER_SECOND) + + tick = rt_tick_get(); + value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD; + + return value; +} + +/** + * This fucntion returns microseconds since system passed + */ +rt_uint32_t rt_hw_tick_get_microsecond(void) +{ + rt_tick_t tick; + rt_uint32_t value; + +#define TICK_US (1000000/RT_TICK_PER_SECOND) + + tick = rt_tick_get(); + value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; + + return value; +} + +/** +* This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init(void) +{ + /* disable all analog input. */ + FM4_GPIO->ADE = 0x00u; + + /* init systick */ + SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.h b/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.h new file mode 100644 index 0000000000..ed258f82a0 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include +#include +#include + +#include "serial.h" + + +#define FM4_SRAM_SIZE 128 +#define FM4_SRAM_END (0x1FFF0000 + FM4_SRAM_SIZE * 1024) + +/* RT_USING_UART */ +#define RT_USING_UART0 + +#define RT_UART_RX_BUFFER_SIZE 128 + +void rt_hw_board_init(void); +rt_uint32_t rt_hw_tick_get_millisecond(void); +rt_uint32_t rt_hw_tick_get_microsecond(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/led.c b/bsp/fujitsu/mb9x/mb9bf568r/drivers/led.c new file mode 100644 index 0000000000..db80b56fd0 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/led.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include "board.h" + +#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */ + +#define LED_NUM 3 +struct fm4_gpio_ctrl +{ + uint32_t led_num; + volatile uint32_t * PDOR; + volatile uint32_t * PDIR; +}; + +struct fm4_led +{ + /* inherit from rt_device */ + struct rt_device parent; + + struct fm4_gpio_ctrl fm4_gpio_ctrl[LED_NUM]; +}; + +static struct fm4_led fm4_led; + +static rt_err_t rt_led_init (rt_device_t dev) +{ + uint32_t i; + + /* led0-1-2 : P27-P38-PE0 */ + FM4_GPIO->PFR2 &= ~((1<<7) ); /* set P27 fuction is GPIO. */ + FM4_GPIO->DDR2 |= (1<<7) ; /* set P27 output. */ + FM4_GPIO->PFR3 &= ~((1<<8) ); /* set P38 fuction is GPIO. */ + FM4_GPIO->DDR3 |= (1<<8) ; /* set P38 output. */ + FM4_GPIO->PFRE &= ~((1<<0) ); /* set PE0 fuction is GPIO. */ + FM4_GPIO->DDRE |= (1<<0) ; /* set PE0 output. */ + + /* LED0 */ + i = 0; + fm4_led.fm4_gpio_ctrl[i].led_num = 7; + fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR2; + fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR2; + + /* LED1 */ + i++; + fm4_led.fm4_gpio_ctrl[i].led_num = 8; + fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR3; + fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR3; + + /* LED2 */ + i++; + fm4_led.fm4_gpio_ctrl[i].led_num = 0; + fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDORE; + fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIRE; + + return RT_EOK; +} + +static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_led_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_ubase_t index = 0; + rt_ubase_t nr = size; + rt_uint8_t * value = buffer; + + RT_ASSERT(dev == &fm4_led.parent); + RT_ASSERT((pos+size) <= LED_NUM ); + + for(index=0; index +void led(rt_uint32_t led, rt_uint32_t value) +{ + rt_uint8_t led_value = value; + rt_led_write(&fm4_led.parent, led, &led_value, 1); +} +FINSH_FUNCTION_EXPORT(led, e.g:led(0,0)/led(0,1).) +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/mcu.h b/bsp/fujitsu/mb9x/mb9bf568r/drivers/mcu.h new file mode 100644 index 0000000000..5717ff37cc --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/mcu.h @@ -0,0 +1,65 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/** + ****************************************************************************** + ** \file mcu.h + ** + ** Header File for device dependent includes + ** + ** History: + ** 2011-05-19 V1.00 MWi first version + ** + ******************************************************************************/ + +#define PDL_INT_TYPE_C 1 +#define PDL_INT_TYPE_A 2 + +#define PDL_MCU_INT_TYPE PDL_INT_TYPE_A + +/** + ****************************************************************************** + ** \brief MCU header file include + ** + ******************************************************************************/ +#ifndef _MB9B560R_H_ + #include "mb9b560r.h" +#endif + +/** + ****************************************************************************** + ** \brief MCU system start-up header file include + ** + ******************************************************************************/ +#ifndef _SYSTEM_MB9ABXXX_H_ + #include "system_mb9bf56xr.h" +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.c b/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.c new file mode 100644 index 0000000000..6c3a132216 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.c @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#include + +#include "serial.h" + +/** + * @addtogroup FM4 MB9BF568R + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + UART_ENABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + UART_DISABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->SSR & SSR_RDRF) + { + *ptr = uart->uart_device->RDR & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = '\r'; + } + + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = (*ptr & 0x1FF); + + ++ptr; + --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, + rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->SSR & SSR_RDRF) + { + rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +#ifdef RT_USING_UART0 +/* UART0 device driver structure */ +#define UART0 FM4_MFS0 +struct serial_int_rx uart0_int_rx; +struct serial_device uart0 = +{ + UART0, + MFS0_RX_IRQn, + MFS0_TX_IRQn, + &uart0_int_rx, + RT_NULL +}; +struct rt_device uart0_device; + +void MFS0_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart0_device); + /* leave interrupt */ + rt_interrupt_leave(); +} + + +#endif /**< #ifdef RT_USING_UART0 */ + + +void rt_hw_serial_init(void) +{ + uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); + +#ifdef RT_USING_UART0 + // Initialize ports for MFS0 + FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 + FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; + FM4_GPIO->EPFR07 |= 0x00000040ul; + + // Initialize MFS to UART asynchronous mode + + uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ + uart0.uart_device->ESCR = ESCR_DATABITS_8; + uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + /* register UART0 device */ + rt_hw_serial_register(&uart0_device, + "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); + + +#endif /**< #ifdef RT_USING_UART0 */ + +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.h b/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.h new file mode 100644 index 0000000000..776b2a3877 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/drivers/serial.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#include "board.h" + +#define SMR_SOE 0x01U +#define SMR_BDS 0x04U +#define SMR_SBL 0x08U +#define SMR_WUCR 0x10U +#define SMR_MD_UART 0x00U +#define SMR_MD_UART_MP 0x20U +#define SMR_MD_SIO 0x40U +#define SMR_MD_LIN 0x60U +#define SMR_MD_I2C 0x80U + +#define SCR_TXE 0x01U +#define SCR_RXE 0x02U +#define SCR_TBIE 0x04U +#define SCR_TIE 0x08U +#define SCR_RIE 0x10U +#define SCR_UPGL 0x80U + +#define SSR_TBI 0x01U +#define SSR_TDRE 0x02U +#define SSR_RDRF 0x04U +#define SSR_ORE 0x08U +#define SSR_FRE 0x10U +#define SSR_PE 0x20U +#define SSR_REC 0x80U + +#define ESCR_P 0x08U +#define ESCR_PEN 0x10U +#define ESCR_INV 0x20U +#define ESCR_ESBL 0x40U +#define ESCR_FLWEN 0x80U +#define ESCR_DATABITS_8 0x00U +#define ESCR_DATABITS_5 0x01U +#define ESCR_DATABITS_6 0x02U +#define ESCR_DATABITS_7 0x03U +#define ESCR_DATABITS_9 0x04U + +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 128 +#define UART_TX_BUFFER_SIZE 128 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +/* + * Enable/DISABLE Interrupt Controller + */ +/* deviation from MISRA-C:2004 Rule 19.7 */ +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct serial_device +{ + FM4_MFS_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +void rt_hw_serial_isr(rt_device_t device); +void rt_hw_serial_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/project.uvopt b/bsp/fujitsu/mb9x/mb9bf568r/project.uvopt new file mode 100644 index 0000000000..c7c71b2bbf --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/project.uvopt @@ -0,0 +1,172 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread-fm4 + 0x4 + ARM-ADS + + 4000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000 + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj new file mode 100644 index 0000000000..2518cee715 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj @@ -0,0 +1,629 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread-fm4 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template_mb9b56xx + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x200c0000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff0000 + 0x10000 + + + 0 + 0x20038000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;CMSIS\Include;CMSIS\DeviceSupport;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + + + + + + + + + Applications + + + startup.c + 1 + applications\startup.c + + + + + application.c + 1 + applications\application.c + + + + + CMSIS + + + startup_mb9bf56xr.s + 2 + CMSIS\DeviceSupport\arm\startup_mb9bf56xr.s + + + + + system_mb9abxxx.c + 1 + CMSIS\DeviceSupport\system_mb9abxxx.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + + + CPU + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Drivers + + + serial.c + 1 + drivers\serial.c + + + + + board.c + 1 + drivers\board.c + + + + + led.c + 1 + drivers\led.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + Kernel + + + object.c + 1 + ..\..\src\object.c + + + + + clock.c + 1 + ..\..\src\clock.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.h b/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.h new file mode 100644 index 0000000000..8191fc8e65 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.h @@ -0,0 +1,75 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 64 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +// +#define RT_USING_COMPONENTS_INIT + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE + +/* SECTION: Console options */ +/* #define RT_TINY_SIZE */ +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart0" + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_STACK_SIZE 1024 + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.py b/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.py new file mode 100644 index 0000000000..abee5014b2 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/rtconfig.py @@ -0,0 +1,86 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' +BOARD_NAME = 'mb9bf568r' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_MDK_471' +elif CROSS_TOOL == 'iar': + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-' + BOARD_NAME + '.map,-cref,-u,Reset_Handler -T rtthread-' + BOARD_NAME + '.ld -nostartfiles' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread_' + \ + BOARD_NAME + '.map --scatter rtthread-' + BOARD_NAME + '.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' diff --git a/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.ld b/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.ld new file mode 100644 index 0000000000..c6700b9535 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.ld @@ -0,0 +1,221 @@ +/* Linker script to configure memory regions + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1024k */ + ram (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 /* 64k */ +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + + .heap : + { + *(.heap) + } >ram + + __bss_end = .; + + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.sct b/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.sct new file mode 100644 index 0000000000..5b025eb611 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/rtthread-mb9bf568r.sct @@ -0,0 +1,23 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x1FFF0000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x20038000 0x00010000 { + .ANY (+RW +ZI) + } +} + +LR_IROM2 0x200C0000 0x00008000 { + ER_IROM2 0x200C0000 0x00008000 { ; load address = execution address + .ANY (+RO) + } +} diff --git a/bsp/fujitsu/mb9x/mb9bf568r/template.uvopt b/bsp/fujitsu/mb9x/mb9bf568r/template.uvopt new file mode 100644 index 0000000000..c7c71b2bbf --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/template.uvopt @@ -0,0 +1,172 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread-fm4 + 0x4 + ARM-ADS + + 4000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000 + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/fujitsu/mb9x/mb9bf568r/template.uvproj b/bsp/fujitsu/mb9x/mb9bf568r/template.uvproj new file mode 100644 index 0000000000..b65281bbef --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf568r/template.uvproj @@ -0,0 +1,398 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-fm4 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template_mb9b56xx + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x200c0000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff0000 + 0x10000 + + + 0 + 0x20038000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + + + + + + + + + Source Group 1 + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h new file mode 100644 index 0000000000..374040f314 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h @@ -0,0 +1,29269 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9BF618S */ +/* Version V1.00 */ +/* Date 2011-08-04 */ +/* */ +/************************************************************************/ + +#ifndef _MB9BF618S_H_ +#define _MB9BF618S_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_31_IRQn = 5, /* External Interrupt Request ch.8 to ch.31 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM0_7_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + ETHER_MAC0_IRQn = 32, /* Ethernet MAC ch.0 */ + ETHER_MAC1_IRQn = 33, /* Ethernet MAC ch.1 */ + USB0F_IRQn = 34, /* USB Function ch.0 */ + USB0F_USB0H_IRQn = 35, /* USB Function ch.0 / USB Host ch.0 */ + USB1F_IRQn = 36, /* USB Function ch.1 */ + USB1F_USB1H_IRQn = 37, /* USB Function ch.1 / USB Host ch.1 */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45, /* DMAC ch.7 */ + BTIM8_15_IRQn = 46 /* Base Timer ch.8 to ch.15 */ + /* Reserved = 47 */ +} IRQn_Type; + + +#include +#include "system_mb9bf61x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Peripheral register bit fields + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash_IF_MODULE register bit fields */ +typedef struct stc_flash_if_faszr_field +{ + __IO uint32_t ASZ0 : 1; + __IO uint32_t ASZ1 : 1; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + __IO uint32_t RWT0 : 1; + __IO uint32_t RWT1 : 1; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY : 1; + __IO uint32_t HNG : 1; + __IO uint32_t EER : 1; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + __IO uint32_t TRMM0 : 1; + __IO uint32_t TRMM1 : 1; + __IO uint32_t TRMM2 : 1; + __IO uint32_t TRMM3 : 1; + __IO uint32_t TRMM4 : 1; + __IO uint32_t TRMM5 : 1; + __IO uint32_t TRMM6 : 1; + __IO uint32_t TRMM7 : 1; + __IO uint32_t TRMM8 : 1; + __IO uint32_t TRMM9 : 1; +} stc_flash_if_crtrmm_field_t; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock_Reset_MODULE register bit fields */ +typedef struct stc_crg_scm_ctl_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MOSCE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SOSCE : 1; + __IO uint8_t PLLE : 1; + __IO uint8_t RCS0 : 1; + __IO uint8_t RCS1 : 1; + __IO uint8_t RCS2 : 1; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MORDY : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SORDY : 1; + __IO uint8_t PLRDY : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t RCM2 : 1; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint16_t PONR : 1; + __IO uint16_t INITX : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SWDT : 1; + __IO uint16_t HWDT : 1; + __IO uint16_t CSVR : 1; + __IO uint16_t FCSR : 1; + __IO uint16_t SRST : 1; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + __IO uint8_t BSR0 : 1; + __IO uint8_t BSR1 : 1; + __IO uint8_t BSR2 : 1; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + __IO uint8_t APBC00 : 1; + __IO uint8_t APBC01 : 1; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + __IO uint8_t APBC10 : 1; + __IO uint8_t APBC11 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC1RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC1EN : 1; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + __IO uint8_t APBC20 : 1; + __IO uint8_t APBC21 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC2RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC2EN : 1; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + __IO uint8_t SWDS0 : 1; + __IO uint8_t SWDS1 : 1; + uint8_t RESERVED1 : 5; + __IO uint8_t TESTB : 1; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + __IO uint8_t TTC0 : 1; + __IO uint8_t TTC1 : 1; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + __IO uint8_t MOWT0 : 1; + __IO uint8_t MOWT1 : 1; + __IO uint8_t MOWT2 : 1; + __IO uint8_t MOWT3 : 1; + __IO uint8_t SOWT0 : 1; + __IO uint8_t SOWT1 : 1; + __IO uint8_t SOWT2 : 1; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + __IO uint8_t POWT0 : 1; + __IO uint8_t POWT1 : 1; + __IO uint8_t POWT2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t PINC : 1; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + __IO uint8_t PLLM0 : 1; + __IO uint8_t PLLM1 : 1; + __IO uint8_t PLLM2 : 1; + __IO uint8_t PLLM3 : 1; + __IO uint8_t PLLK0 : 1; + __IO uint8_t PLLK1 : 1; + __IO uint8_t PLLK2 : 1; + __IO uint8_t PLLK3 : 1; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + __IO uint8_t PLLN0 : 1; + __IO uint8_t PLLN1 : 1; + __IO uint8_t PLLN2 : 1; + __IO uint8_t PLLN3 : 1; + __IO uint8_t PLLN4 : 1; + __IO uint8_t PLLN5 : 1; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + __IO uint16_t MCSVE : 1; + __IO uint16_t SCSVE : 1; + uint16_t RESERVED1 : 6; + __IO uint16_t FCSDE : 1; + __IO uint16_t FCSRE : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t FCD0 : 1; + __IO uint16_t FCD1 : 1; + __IO uint16_t FCD2 : 1; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint8_t MCMF : 1; + __IO uint8_t SCMF : 1; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + uint8_t RESERVED1 : 5; + __IO uint8_t DPSWBE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t DPHWBE : 1; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint8_t MCSE : 1; + __IO uint8_t SCSE : 1; + __IO uint8_t PCSE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSE : 1; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint8_t MCSI : 1; + __IO uint8_t SCSI : 1; + __IO uint8_t PCSI : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSI : 1; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint8_t MCSC : 1; + __IO uint8_t SCSC : 1; + __IO uint8_t PCSC : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSC : 1; +} stc_crg_int_clr_field_t; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* HWWDT_MODULE register bit fields */ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint8_t RIS : 1; +} stc_hwwdt_wdg_ris_field_t; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* SWWDT_MODULE register bit fields */ +typedef struct stc_swwdt_wdogcontrol_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint8_t RIS : 1; +} stc_swwdt_wdogris_field_t; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* DTIM_MODULE register bit fields */ +typedef struct stc_dtim_timer1control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer1control_field_t; + +typedef struct stc_dtim_timer1ris_field +{ + __IO uint32_t TIMER1RIS : 1; +} stc_dtim_timer1ris_field_t; + +typedef struct stc_dtim_timer1mis_field +{ + __IO uint32_t TIMER1MIS : 1; +} stc_dtim_timer1mis_field_t; + +typedef struct stc_dtim_timer2control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer2control_field_t; + +typedef struct stc_dtim_timer2ris_field +{ + __IO uint32_t TIMER2RIS : 1; +} stc_dtim_timer2ris_field_t; + +typedef struct stc_dtim_timer2mis_field +{ + __IO uint32_t TIMER2MIS : 1; +} stc_dtim_timer2mis_field_t; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* MFT_FRT_MODULE register bit fields */ +typedef struct stc_mft_frt_tcsa0_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsb0_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb0_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsb1_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb1_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsb2_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb2_field_t; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* MFT_OCU_MODULE register bit fields */ +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST2 : 1; + __IO uint8_t CST3 : 1; + __IO uint8_t BDIS2 : 1; + __IO uint8_t BDIS3 : 1; + __IO uint8_t IOE2 : 1; + __IO uint8_t IOE3 : 1; + __IO uint8_t IOP2 : 1; + __IO uint8_t IOP3 : 1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD2 : 1; + __IO uint8_t OTD3 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS2 : 1; + __IO uint8_t BTS3 : 1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST4 : 1; + __IO uint8_t CST5 : 1; + __IO uint8_t BDIS4 : 1; + __IO uint8_t BDIS5 : 1; + __IO uint8_t IOE4 : 1; + __IO uint8_t IOE5 : 1; + __IO uint8_t IOP4 : 1; + __IO uint8_t IOP5 : 1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD4 : 1; + __IO uint8_t OTD5 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS4 : 1; + __IO uint8_t BTS5 : 1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 : 1; + __IO uint8_t MOD1 : 1; + __IO uint8_t MOD2 : 1; + __IO uint8_t MOD3 : 1; + __IO uint8_t MOD4 : 1; + __IO uint8_t MOD5 : 1; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + __IO uint8_t FSO20 : 1; + __IO uint8_t FSO21 : 1; + __IO uint8_t FSO22 : 1; + __IO uint8_t FSO23 : 1; + __IO uint8_t FSO30 : 1; + __IO uint8_t FSO31 : 1; + __IO uint8_t FSO32 : 1; + __IO uint8_t FSO33 : 1; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + __IO uint8_t FSO40 : 1; + __IO uint8_t FSO41 : 1; + __IO uint8_t FSO42 : 1; + __IO uint8_t FSO43 : 1; + __IO uint8_t FSO50 : 1; + __IO uint8_t FSO51 : 1; + __IO uint8_t FSO52 : 1; + __IO uint8_t FSO53 : 1; +} stc_mft_ocu_ocfs54_field_t; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* MFT_WFG_MODULE register bit fields */ +typedef struct stc_mft_wfg_wfsa10_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD0 : 1; + __IO uint16_t TMD1 : 1; + __IO uint16_t TMD2 : 1; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIF : 1; + __IO uint16_t DTIC : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t TMIF10 : 1; + __IO uint16_t TMIC10 : 1; + __IO uint16_t TMIE10 : 1; + __IO uint16_t TMIS10 : 1; + __IO uint16_t TMIF32 : 1; + __IO uint16_t TMIC32 : 1; + __IO uint16_t TMIE32 : 1; + __IO uint16_t TMIS32 : 1; + __IO uint16_t TMIF54 : 1; + __IO uint16_t TMIC54 : 1; + __IO uint16_t TMIE54 : 1; + __IO uint16_t TMIS54 : 1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + __IO uint16_t DTIE : 1; + __IO uint16_t NWS0 : 1; + __IO uint16_t NWS1 : 1; + __IO uint16_t NWS2 : 1; + __IO uint16_t SDTI : 1; +} stc_mft_wfg_nzcl_field_t; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* MFT_ICU_MODULE register bit fields */ +typedef struct stc_mft_icu_icfs10_field +{ + __IO uint8_t FSI00 : 1; + __IO uint8_t FSI01 : 1; + __IO uint8_t FSI02 : 1; + __IO uint8_t FSI03 : 1; + __IO uint8_t FSI10 : 1; + __IO uint8_t FSI11 : 1; + __IO uint8_t FSI12 : 1; + __IO uint8_t FSI13 : 1; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + __IO uint8_t FSI20 : 1; + __IO uint8_t FSI21 : 1; + __IO uint8_t FSI22 : 1; + __IO uint8_t FSI23 : 1; + __IO uint8_t FSI30 : 1; + __IO uint8_t FSI31 : 1; + __IO uint8_t FSI32 : 1; + __IO uint8_t FSI33 : 1; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + __IO uint8_t EG00 : 1; + __IO uint8_t EG01 : 1; + __IO uint8_t EG10 : 1; + __IO uint8_t EG11 : 1; + __IO uint8_t ICE0 : 1; + __IO uint8_t ICE1 : 1; + __IO uint8_t ICP0 : 1; + __IO uint8_t ICP1 : 1; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 : 1; + __IO uint8_t IEI1 : 1; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + __IO uint8_t EG20 : 1; + __IO uint8_t EG21 : 1; + __IO uint8_t EG30 : 1; + __IO uint8_t EG31 : 1; + __IO uint8_t ICE2 : 1; + __IO uint8_t ICE3 : 1; + __IO uint8_t ICP2 : 1; + __IO uint8_t ICP3 : 1; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI2 : 1; + __IO uint8_t IEI3 : 1; +} stc_mft_icu_icsb32_field_t; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* MFT_ADCMP_MODULE register bit fields */ +typedef struct stc_mft_adcmp_acsb_field +{ + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t BDIS2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; + __IO uint8_t BTS2 : 1; +} stc_mft_adcmp_acsb_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + __IO uint16_t CE00 : 1; + __IO uint16_t CE01 : 1; + __IO uint16_t CE10 : 1; + __IO uint16_t CE11 : 1; + __IO uint16_t CE20 : 1; + __IO uint16_t CE21 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SEL00 : 1; + __IO uint16_t SEL01 : 1; + __IO uint16_t SEL10 : 1; + __IO uint16_t SEL11 : 1; + __IO uint16_t SEL20 : 1; + __IO uint16_t SEL21 : 1; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_atsa_field +{ + __IO uint16_t AD0S0 : 1; + __IO uint16_t AD0S1 : 1; + __IO uint16_t AD1S0 : 1; + __IO uint16_t AD1S1 : 1; + __IO uint16_t AD2S0 : 1; + __IO uint16_t AD2S1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t AD0P0 : 1; + __IO uint16_t AD0P1 : 1; + __IO uint16_t AD1P0 : 1; + __IO uint16_t AD1P1 : 1; + __IO uint16_t AD2P0 : 1; + __IO uint16_t AD2P1 : 1; +} stc_mft_adcmp_atsa_field_t; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* MFT_PPG_MODULE register bit fields */ +typedef struct stc_mft_ppg_ttcr0_field +{ + __IO uint8_t STR0 : 1; + __IO uint8_t MONI0 : 1; + __IO uint8_t CS00 : 1; + __IO uint8_t CS01 : 1; + __IO uint8_t TRG0O : 1; + __IO uint8_t TRG2O : 1; + __IO uint8_t TRG4O : 1; + __IO uint8_t TRG6O : 1; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + __IO uint8_t STR1 : 1; + __IO uint8_t MONI1 : 1; + __IO uint8_t CS10 : 1; + __IO uint8_t CS11 : 1; + __IO uint8_t TRG1O : 1; + __IO uint8_t TRG3O : 1; + __IO uint8_t TRG5O : 1; + __IO uint8_t TRG7O : 1; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_ttcr2_field +{ + __IO uint8_t STR2 : 1; + __IO uint8_t MONI2 : 1; + __IO uint8_t CS20 : 1; + __IO uint8_t CS21 : 1; + __IO uint8_t TRG16O : 1; + __IO uint8_t TRG18O : 1; + __IO uint8_t TRG20O : 1; + __IO uint8_t TRG22O : 1; +} stc_mft_ppg_ttcr2_field_t; + +typedef struct stc_mft_ppg_trg_field +{ + __IO uint16_t PEN00 : 1; + __IO uint16_t PEN01 : 1; + __IO uint16_t PEN02 : 1; + __IO uint16_t PEN03 : 1; + __IO uint16_t PEN04 : 1; + __IO uint16_t PEN05 : 1; + __IO uint16_t PEN06 : 1; + __IO uint16_t PEN07 : 1; + __IO uint16_t PEN08 : 1; + __IO uint16_t PEN09 : 1; + __IO uint16_t PEN10 : 1; + __IO uint16_t PEN11 : 1; + __IO uint16_t PEN12 : 1; + __IO uint16_t PEN13 : 1; + __IO uint16_t PEN14 : 1; + __IO uint16_t PEN15 : 1; +} stc_mft_ppg_trg_field_t; + +typedef struct stc_mft_ppg_trg1_field +{ + __IO uint16_t PEN16 : 1; + __IO uint16_t PEN17 : 1; + __IO uint16_t PEN18 : 1; + __IO uint16_t PEN19 : 1; + __IO uint16_t PEN20 : 1; + __IO uint16_t PEN21 : 1; + __IO uint16_t PEN22 : 1; + __IO uint16_t PEN23 : 1; +} stc_mft_ppg_trg1_field_t; + +typedef struct stc_mft_ppg_revc_field +{ + __IO uint16_t REV00 : 1; + __IO uint16_t REV01 : 1; + __IO uint16_t REV02 : 1; + __IO uint16_t REV03 : 1; + __IO uint16_t REV04 : 1; + __IO uint16_t REV05 : 1; + __IO uint16_t REV06 : 1; + __IO uint16_t REV07 : 1; + __IO uint16_t REV08 : 1; + __IO uint16_t REV09 : 1; + __IO uint16_t REV10 : 1; + __IO uint16_t REV11 : 1; + __IO uint16_t REV12 : 1; + __IO uint16_t REV13 : 1; + __IO uint16_t REV14 : 1; + __IO uint16_t REV15 : 1; +} stc_mft_ppg_revc_field_t; + +typedef struct stc_mft_ppg_revc1_field +{ + __IO uint16_t REV16 : 1; + __IO uint16_t REV17 : 1; + __IO uint16_t REV18 : 1; + __IO uint16_t REV19 : 1; + __IO uint16_t REV20 : 1; + __IO uint16_t REV21 : 1; + __IO uint16_t REV22 : 1; + __IO uint16_t REV23 : 1; +} stc_mft_ppg_revc1_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 : 1; + __IO uint8_t STRG0 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE2 : 1; + __IO uint8_t STRG2 : 1; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 : 1; + __IO uint8_t STRG4 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE6 : 1; + __IO uint8_t STRG6 : 1; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 : 1; + __IO uint8_t STRG8 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE10 : 1; + __IO uint8_t STRG10 : 1; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 : 1; + __IO uint8_t STRG12 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE14 : 1; + __IO uint8_t STRG14 : 1; +} stc_mft_ppg_gatec12_field_t; + +typedef struct stc_mft_ppg_ppgc17_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc17_field_t; + +typedef struct stc_mft_ppg_ppgc16_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc16_field_t; + +typedef struct stc_mft_ppg_ppgc19_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc19_field_t; + +typedef struct stc_mft_ppg_ppgc18_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc18_field_t; + +typedef struct stc_mft_ppg_gatec16_field +{ + __IO uint8_t EDGE16 : 1; + __IO uint8_t STRG16 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE18 : 1; + __IO uint8_t STRG18 : 1; +} stc_mft_ppg_gatec16_field_t; + +typedef struct stc_mft_ppg_ppgc21_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc21_field_t; + +typedef struct stc_mft_ppg_ppgc20_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc20_field_t; + +typedef struct stc_mft_ppg_ppgc23_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc23_field_t; + +typedef struct stc_mft_ppg_ppgc22_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc22_field_t; + +typedef struct stc_mft_ppg_gatec20_field +{ + __IO uint8_t EDGE20 : 1; + __IO uint8_t STRG20 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE22 : 1; + __IO uint8_t STRG22 : 1; +} stc_mft_ppg_gatec20_field_t; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* BT_PPG_MODULE register bit fields */ +typedef struct stc_bt_ppg_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_ppg_tmcr2_field_t; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* BT_PWM_MODULE register bit fields */ +typedef struct stc_bt_pwm_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR : 1; + __IO uint8_t DTIR : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t UDIE : 1; + __IO uint8_t DTIE : 1; + __IO uint8_t TGIE : 1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwm_tmcr2_field_t; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* BT_RT_MODULE register bit fields */ +typedef struct stc_bt_rt_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_rt_tmcr2_field_t; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* BT_PWC_MODULE register bit fields */ +typedef struct stc_bt_pwc_tmcr_field +{ + uint16_t RESERVED1 : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FMD0 : 1; + __IO uint16_t FMD1 : 1; + __IO uint16_t FMD2 : 1; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t EGS2 : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t EDIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t OVIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t EDIE : 1; + __IO uint8_t ERR : 1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwc_tmcr2_field_t; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* BTIOSEL03_MODULE register bit fields */ +typedef struct stc_btiosel03_btsel0123_field +{ + __IO uint8_t SEL01_0 : 1; + __IO uint8_t SEL01_1 : 1; + __IO uint8_t SEL01_2 : 1; + __IO uint8_t SEL01_3 : 1; + __IO uint8_t SEL23_0 : 1; + __IO uint8_t SEL23_1 : 1; + __IO uint8_t SEL23_2 : 1; + __IO uint8_t SEL23_3 : 1; +} stc_btiosel03_btsel0123_field_t; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* BTIOSEL47_MODULE register bit fields */ +typedef struct stc_btiosel47_btsel4567_field +{ + __IO uint8_t SEL45_0 : 1; + __IO uint8_t SEL45_1 : 1; + __IO uint8_t SEL45_2 : 1; + __IO uint8_t SEL45_3 : 1; + __IO uint8_t SEL67_0 : 1; + __IO uint8_t SEL67_1 : 1; + __IO uint8_t SEL67_2 : 1; + __IO uint8_t SEL67_3 : 1; +} stc_btiosel47_btsel4567_field_t; + +/****************************************************************************** + * BTIOSEL811_MODULE + ******************************************************************************/ +/* BTIOSEL811_MODULE register bit fields */ +typedef struct stc_btiosel8b_btsel89ab_field +{ + __IO uint8_t SEL89_0 : 1; + __IO uint8_t SEL89_1 : 1; + __IO uint8_t SEL89_2 : 1; + __IO uint8_t SEL89_3 : 1; + __IO uint8_t SELAB_0 : 1; + __IO uint8_t SELAB_1 : 1; + __IO uint8_t SELAB_2 : 1; + __IO uint8_t SELAB_3 : 1; +} stc_btiosel8b_btsel89ab_field_t; + +/****************************************************************************** + * BTIOSEL1215_MODULE + ******************************************************************************/ +/* BTIOSEL1215_MODULE register bit fields */ +typedef struct stc_btioselcf_btselcdef_field +{ + __IO uint8_t SELCD_0 : 1; + __IO uint8_t SELCD_1 : 1; + __IO uint8_t SELCD_2 : 1; + __IO uint8_t SELCD_3 : 1; + __IO uint8_t SELEF_0 : 1; + __IO uint8_t SELEF_1 : 1; + __IO uint8_t SELEF_2 : 1; + __IO uint8_t SELEF_3 : 1; +} stc_btioselcf_btselcdef_field_t; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* SBSSR_MODULE register bit fields */ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSR0 : 1; + __IO uint16_t SSR1 : 1; + __IO uint16_t SSR2 : 1; + __IO uint16_t SSR3 : 1; + __IO uint16_t SSR4 : 1; + __IO uint16_t SSR5 : 1; + __IO uint16_t SSR6 : 1; + __IO uint16_t SSR7 : 1; + __IO uint16_t SSR8 : 1; + __IO uint16_t SSR9 : 1; + __IO uint16_t SSR10 : 1; + __IO uint16_t SSR11 : 1; + __IO uint16_t SSR12 : 1; + __IO uint16_t SSR13 : 1; + __IO uint16_t SSR14 : 1; + __IO uint16_t SSR15 : 1; +} stc_sbssr_btsssr_field_t; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* QPRC_MODULE register bit fields */ +typedef struct stc_qprc_qicr_field +{ + __IO uint16_t QPCMIE : 1; + __IO uint16_t QPCMF : 1; + __IO uint16_t QPRCMIE : 1; + __IO uint16_t QPRCMF : 1; + __IO uint16_t OUZIE : 1; + __IO uint16_t UFDF : 1; + __IO uint16_t OFDF : 1; + __IO uint16_t ZIIF : 1; + __IO uint16_t CDCIE : 1; + __IO uint16_t CDCF : 1; + __IO uint16_t DIRPC : 1; + __IO uint16_t DIROU : 1; + __IO uint16_t QPCNRCMIE : 1; + __IO uint16_t QPCNRCMF : 1; +} stc_qprc_qicr_field_t; + +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE : 1; + __IO uint8_t QPCMF : 1; + __IO uint8_t QPRCMIE : 1; + __IO uint8_t QPRCMF : 1; + __IO uint8_t OUZIE : 1; + __IO uint8_t UFDF : 1; + __IO uint8_t OFDF : 1; + __IO uint8_t ZIIF : 1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE : 1; + __IO uint8_t CDCF : 1; + __IO uint8_t DIRPC : 1; + __IO uint8_t DIROU : 1; + __IO uint8_t QPCNRCMIE : 1; + __IO uint8_t QPCNRCMF : 1; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + __IO uint16_t PCM0 : 1; + __IO uint16_t PCM1 : 1; + __IO uint16_t RCM0 : 1; + __IO uint16_t RCM1 : 1; + __IO uint16_t PSTP : 1; + __IO uint16_t CGSC : 1; + __IO uint16_t RSEL : 1; + __IO uint16_t SWAP : 1; + __IO uint16_t PCRM0 : 1; + __IO uint16_t PCRM1 : 1; + __IO uint16_t AES0 : 1; + __IO uint16_t AES1 : 1; + __IO uint16_t BES0 : 1; + __IO uint16_t BES1 : 1; + __IO uint16_t CGE0 : 1; + __IO uint16_t CGE1 : 1; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qcrl_field +{ + __IO uint8_t PCM0 : 1; + __IO uint8_t PCM1 : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t PSTP : 1; + __IO uint8_t CGSC : 1; + __IO uint8_t RSEL : 1; + __IO uint8_t SWAP : 1; +} stc_qprc_qcrl_field_t; + +typedef struct stc_qprc_qcrh_field +{ + __IO uint8_t PCRM0 : 1; + __IO uint8_t PCRM1 : 1; + __IO uint8_t AES0 : 1; + __IO uint8_t AES1 : 1; + __IO uint8_t BES0 : 1; + __IO uint8_t BES1 : 1; + __IO uint8_t CGE0 : 1; + __IO uint8_t CGE1 : 1; +} stc_qprc_qcrh_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD : 1; + __IO uint16_t ORNGF : 1; + __IO uint16_t ORNGIE : 1; +} stc_qprc_qecr_field_t; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* ADC12_MODULE register bit fields */ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS : 1; + __IO uint8_t PCS : 1; + __IO uint8_t PCNS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t FDAS : 1; + __IO uint8_t ADSTP : 1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE : 1; + __IO uint8_t CMPIE : 1; + __IO uint8_t PCIE : 1; + __IO uint8_t SCIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t CMPIF : 1; + __IO uint8_t PCIF : 1; + __IO uint8_t SCIF : 1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + __IO uint8_t SFS0 : 1; + __IO uint8_t SFS1 : 1; + __IO uint8_t SFS2 : 1; + __IO uint8_t SFS3 : 1; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR : 1; + __IO uint8_t SHEN : 1; + __IO uint8_t RPT : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t SFCLR : 1; + __IO uint8_t SOVR : 1; + __IO uint8_t SFUL : 1; + __IO uint8_t SEMP : 1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_field +{ + __IO uint32_t SC0 : 1; + __IO uint32_t SC1 : 1; + __IO uint32_t SC2 : 1; + __IO uint32_t SC3 : 1; + __IO uint32_t SC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; + __IO uint32_t SD3 : 1; + __IO uint32_t SD4 : 1; + __IO uint32_t SD5 : 1; + __IO uint32_t SD6 : 1; + __IO uint32_t SD7 : 1; + __IO uint32_t SD8 : 1; + __IO uint32_t SD9 : 1; + __IO uint32_t SD10 : 1; + __IO uint32_t SD11 : 1; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scfdl_field +{ + __IO uint16_t SC0 : 1; + __IO uint16_t SC1 : 1; + __IO uint16_t SC2 : 1; + __IO uint16_t SC3 : 1; + __IO uint16_t SC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t INVL : 1; +} stc_adc_scfdl_field_t; + +typedef struct stc_adc_scfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t SD0 : 1; + __IO uint16_t SD1 : 1; + __IO uint16_t SD2 : 1; + __IO uint16_t SD3 : 1; + __IO uint16_t SD4 : 1; + __IO uint16_t SD5 : 1; + __IO uint16_t SD6 : 1; + __IO uint16_t SD7 : 1; + __IO uint16_t SD8 : 1; + __IO uint16_t SD9 : 1; + __IO uint16_t SD10 : 1; + __IO uint16_t SD11 : 1; +} stc_adc_scfdh_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 : 1; + __IO uint16_t AN17 : 1; + __IO uint16_t AN18 : 1; + __IO uint16_t AN19 : 1; + __IO uint16_t AN20 : 1; + __IO uint16_t AN21 : 1; + __IO uint16_t AN22 : 1; + __IO uint16_t AN23 : 1; + __IO uint16_t AN24 : 1; + __IO uint16_t AN25 : 1; + __IO uint16_t AN26 : 1; + __IO uint16_t AN27 : 1; + __IO uint16_t AN28 : 1; + __IO uint16_t AN29 : 1; + __IO uint16_t AN30 : 1; + __IO uint16_t AN31 : 1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis2_field +{ + __IO uint8_t AN16 : 1; + __IO uint8_t AN17 : 1; + __IO uint8_t AN18 : 1; + __IO uint8_t AN19 : 1; + __IO uint8_t AN20 : 1; + __IO uint8_t AN21 : 1; + __IO uint8_t AN22 : 1; + __IO uint8_t AN23 : 1; +} stc_adc_scis2_field_t; + +typedef struct stc_adc_scis3_field +{ + __IO uint8_t AN24 : 1; + __IO uint8_t AN25 : 1; + __IO uint8_t AN26 : 1; + __IO uint8_t AN27 : 1; + __IO uint8_t AN28 : 1; + __IO uint8_t AN29 : 1; + __IO uint8_t AN30 : 1; + __IO uint8_t AN31 : 1; +} stc_adc_scis3_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 : 1; + __IO uint16_t AN1 : 1; + __IO uint16_t AN2 : 1; + __IO uint16_t AN3 : 1; + __IO uint16_t AN4 : 1; + __IO uint16_t AN5 : 1; + __IO uint16_t AN6 : 1; + __IO uint16_t AN7 : 1; + __IO uint16_t AN8 : 1; + __IO uint16_t AN9 : 1; + __IO uint16_t AN10 : 1; + __IO uint16_t AN11 : 1; + __IO uint16_t AN12 : 1; + __IO uint16_t AN13 : 1; + __IO uint16_t AN14 : 1; + __IO uint16_t AN15 : 1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_scis0_field +{ + __IO uint8_t AN0 : 1; + __IO uint8_t AN1 : 1; + __IO uint8_t AN2 : 1; + __IO uint8_t AN3 : 1; + __IO uint8_t AN4 : 1; + __IO uint8_t AN5 : 1; + __IO uint8_t AN6 : 1; + __IO uint8_t AN7 : 1; +} stc_adc_scis0_field_t; + +typedef struct stc_adc_scis1_field +{ + __IO uint8_t AN8 : 1; + __IO uint8_t AN9 : 1; + __IO uint8_t AN10 : 1; + __IO uint8_t AN11 : 1; + __IO uint8_t AN12 : 1; + __IO uint8_t AN13 : 1; + __IO uint8_t AN14 : 1; + __IO uint8_t AN15 : 1; +} stc_adc_scis1_field_t; + +typedef struct stc_adc_pfns_field +{ + __IO uint8_t PFS0 : 1; + __IO uint8_t PFS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t TEST0 : 1; + __IO uint8_t TEST1 : 1; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR : 1; + __IO uint8_t PHEN : 1; + __IO uint8_t PEEN : 1; + __IO uint8_t ESCE : 1; + __IO uint8_t PFCLR : 1; + __IO uint8_t POVR : 1; + __IO uint8_t PFUL : 1; + __IO uint8_t PEMP : 1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_field +{ + __IO uint32_t PC0 : 1; + __IO uint32_t PC1 : 1; + __IO uint32_t PC2 : 1; + __IO uint32_t PC3 : 1; + __IO uint32_t PC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t PD0 : 1; + __IO uint32_t PD1 : 1; + __IO uint32_t PD2 : 1; + __IO uint32_t PD3 : 1; + __IO uint32_t PD4 : 1; + __IO uint32_t PD5 : 1; + __IO uint32_t PD6 : 1; + __IO uint32_t PD7 : 1; + __IO uint32_t PD8 : 1; + __IO uint32_t PD9 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcfdl_field +{ + __IO uint16_t PC0 : 1; + __IO uint16_t PC1 : 1; + __IO uint16_t PC2 : 1; + __IO uint16_t PC3 : 1; + __IO uint16_t PC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + __IO uint16_t RS2 : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t INVL : 1; +} stc_adc_pcfdl_field_t; + +typedef struct stc_adc_pcfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t PD0 : 1; + __IO uint16_t PD1 : 1; + __IO uint16_t PD2 : 1; + __IO uint16_t PD3 : 1; + __IO uint16_t PD4 : 1; + __IO uint16_t PD5 : 1; + __IO uint16_t PD6 : 1; + __IO uint16_t PD7 : 1; + __IO uint16_t PD8 : 1; + __IO uint16_t PD9 : 1; + __IO uint16_t PD10 : 1; + __IO uint16_t PD11 : 1; +} stc_adc_pcfdh_field_t; + +typedef struct stc_adc_pcis_field +{ + __IO uint8_t P1A0 : 1; + __IO uint8_t P1A1 : 1; + __IO uint8_t P1A2 : 1; + __IO uint8_t P2A0 : 1; + __IO uint8_t P2A1 : 1; + __IO uint8_t P2A2 : 1; + __IO uint8_t P2A3 : 1; + __IO uint8_t P2A4 : 1; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + __IO uint8_t CCH0 : 1; + __IO uint8_t CCH1 : 1; + __IO uint8_t CCH2 : 1; + __IO uint8_t CCH3 : 1; + __IO uint8_t CCH4 : 1; + __IO uint8_t CMD0 : 1; + __IO uint8_t CMD1 : 1; + __IO uint8_t CMPEN : 1; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + uint16_t RESERVED1 : 6; + __IO uint16_t CMAD2 : 1; + __IO uint16_t CMAD3 : 1; + __IO uint16_t CMAD4 : 1; + __IO uint16_t CMAD5 : 1; + __IO uint16_t CMAD6 : 1; + __IO uint16_t CMAD7 : 1; + __IO uint16_t CMAD8 : 1; + __IO uint16_t CMAD9 : 1; + __IO uint16_t CMAD10 : 1; + __IO uint16_t CMAD11 : 1; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 : 1; + __IO uint16_t TS17 : 1; + __IO uint16_t TS18 : 1; + __IO uint16_t TS19 : 1; + __IO uint16_t TS20 : 1; + __IO uint16_t TS21 : 1; + __IO uint16_t TS22 : 1; + __IO uint16_t TS23 : 1; + __IO uint16_t TS24 : 1; + __IO uint16_t TS25 : 1; + __IO uint16_t TS26 : 1; + __IO uint16_t TS27 : 1; + __IO uint16_t TS28 : 1; + __IO uint16_t TS29 : 1; + __IO uint16_t TS30 : 1; + __IO uint16_t TS31 : 1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss2_field +{ + __IO uint8_t TS16 : 1; + __IO uint8_t TS17 : 1; + __IO uint8_t TS18 : 1; + __IO uint8_t TS19 : 1; + __IO uint8_t TS20 : 1; + __IO uint8_t TS21 : 1; + __IO uint8_t TS22 : 1; + __IO uint8_t TS23 : 1; +} stc_adc_adss2_field_t; + +typedef struct stc_adc_adss3_field +{ + __IO uint8_t TS24 : 1; + __IO uint8_t TS25 : 1; + __IO uint8_t TS26 : 1; + __IO uint8_t TS27 : 1; + __IO uint8_t TS28 : 1; + __IO uint8_t TS29 : 1; + __IO uint8_t TS30 : 1; + __IO uint8_t TS31 : 1; +} stc_adc_adss3_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 : 1; + __IO uint16_t TS1 : 1; + __IO uint16_t TS2 : 1; + __IO uint16_t TS3 : 1; + __IO uint16_t TS4 : 1; + __IO uint16_t TS5 : 1; + __IO uint16_t TS6 : 1; + __IO uint16_t TS7 : 1; + __IO uint16_t TS8 : 1; + __IO uint16_t TS9 : 1; + __IO uint16_t TS10 : 1; + __IO uint16_t TS11 : 1; + __IO uint16_t TS12 : 1; + __IO uint16_t TS13 : 1; + __IO uint16_t TS14 : 1; + __IO uint16_t TS15 : 1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adss0_field +{ + __IO uint8_t TS0 : 1; + __IO uint8_t TS1 : 1; + __IO uint8_t TS2 : 1; + __IO uint8_t TS3 : 1; + __IO uint8_t TS4 : 1; + __IO uint8_t TS5 : 1; + __IO uint8_t TS6 : 1; + __IO uint8_t TS7 : 1; +} stc_adc_adss0_field_t; + +typedef struct stc_adc_adss1_field +{ + __IO uint8_t TS8 : 1; + __IO uint8_t TS9 : 1; + __IO uint8_t TS10 : 1; + __IO uint8_t TS11 : 1; + __IO uint8_t TS12 : 1; + __IO uint8_t TS13 : 1; + __IO uint8_t TS14 : 1; + __IO uint8_t TS15 : 1; +} stc_adc_adss1_field_t; + +typedef struct stc_adc_adst01_field +{ + __IO uint16_t ST10 : 1; + __IO uint16_t ST11 : 1; + __IO uint16_t ST12 : 1; + __IO uint16_t ST13 : 1; + __IO uint16_t ST14 : 1; + __IO uint16_t STX10 : 1; + __IO uint16_t STX11 : 1; + __IO uint16_t STX12 : 1; + __IO uint16_t ST00 : 1; + __IO uint16_t ST01 : 1; + __IO uint16_t ST02 : 1; + __IO uint16_t ST03 : 1; + __IO uint16_t ST04 : 1; + __IO uint16_t STX00 : 1; + __IO uint16_t STX01 : 1; + __IO uint16_t STX02 : 1; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adst1_field +{ + __IO uint8_t ST10 : 1; + __IO uint8_t ST11 : 1; + __IO uint8_t ST12 : 1; + __IO uint8_t ST13 : 1; + __IO uint8_t ST14 : 1; + __IO uint8_t STX10 : 1; + __IO uint8_t STX11 : 1; + __IO uint8_t STX12 : 1; +} stc_adc_adst1_field_t; + +typedef struct stc_adc_adst0_field +{ + __IO uint8_t ST00 : 1; + __IO uint8_t ST01 : 1; + __IO uint8_t ST02 : 1; + __IO uint8_t ST03 : 1; + __IO uint8_t ST04 : 1; + __IO uint8_t STX00 : 1; + __IO uint8_t STX01 : 1; + __IO uint8_t STX02 : 1; +} stc_adc_adst0_field_t; + +typedef struct stc_adc_adct_field +{ + __IO uint8_t CT0 : 1; + __IO uint8_t CT1 : 1; + __IO uint8_t CT2 : 1; + __IO uint8_t CT3 : 1; + __IO uint8_t CT4 : 1; + __IO uint8_t CT5 : 1; + __IO uint8_t CT6 : 1; + __IO uint8_t CT7 : 1; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + __IO uint8_t PRTSL0 : 1; + __IO uint8_t PRTSL1 : 1; + __IO uint8_t PRTSL2 : 1; + __IO uint8_t PRTSL3 : 1; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + __IO uint8_t SCTSL0 : 1; + __IO uint8_t SCTSL1 : 1; + __IO uint8_t SCTSL2 : 1; + __IO uint8_t SCTSL3 : 1; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + __IO uint8_t ENBL : 1; + __IO uint8_t READY : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CYCLSL0 : 1; + __IO uint8_t CYCLSL1 : 1; +} stc_adc_adcen_field_t; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CRTRIM_MODULE register bit fields */ +typedef struct stc_crtrim_mcr_psr_field +{ + __IO uint8_t CSR0 : 1; + __IO uint8_t CSR1 : 1; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + __IO uint16_t TRD0 : 1; + __IO uint16_t TRD1 : 1; + __IO uint16_t TRD2 : 1; + __IO uint16_t TRD3 : 1; + __IO uint16_t TRD4 : 1; + __IO uint16_t TRD5 : 1; + __IO uint16_t TRD6 : 1; + __IO uint16_t TRD7 : 1; +} stc_crtrim_mcr_ftrm_field_t; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* EXTI_MODULE registEN bit fields */ +typedef struct stc_exti_enir_field +{ + __IO uint16_t EN0 : 1; + __IO uint16_t EN1 : 1; + __IO uint16_t EN2 : 1; + __IO uint16_t EN3 : 1; + __IO uint16_t EN4 : 1; + __IO uint16_t EN5 : 1; + __IO uint16_t EN6 : 1; + __IO uint16_t EN7 : 1; + __IO uint16_t EN8 : 1; + __IO uint16_t EN9 : 1; + __IO uint16_t EN10 : 1; + __IO uint16_t EN11 : 1; + __IO uint16_t EN12 : 1; + __IO uint16_t EN13 : 1; + __IO uint16_t EN14 : 1; + __IO uint16_t EN15 : 1; + __IO uint16_t EN16 : 1; + __IO uint16_t EN17 : 1; + __IO uint16_t EN18 : 1; + __IO uint16_t EN19 : 1; + __IO uint16_t EN20 : 1; + __IO uint16_t EN21 : 1; + __IO uint16_t EN22 : 1; + __IO uint16_t EN23 : 1; + __IO uint16_t EN24 : 1; + __IO uint16_t EN25 : 1; + __IO uint16_t EN26 : 1; + __IO uint16_t EN27 : 1; + __IO uint16_t EN28 : 1; + __IO uint16_t EN29 : 1; + __IO uint16_t EN30 : 1; + __IO uint16_t EN31 : 1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint16_t ER0 : 1; + __IO uint16_t ER1 : 1; + __IO uint16_t ER2 : 1; + __IO uint16_t ER3 : 1; + __IO uint16_t ER4 : 1; + __IO uint16_t ER5 : 1; + __IO uint16_t ER6 : 1; + __IO uint16_t ER7 : 1; + __IO uint16_t ER8 : 1; + __IO uint16_t ER9 : 1; + __IO uint16_t ER10 : 1; + __IO uint16_t ER11 : 1; + __IO uint16_t ER12 : 1; + __IO uint16_t ER13 : 1; + __IO uint16_t ER14 : 1; + __IO uint16_t ER15 : 1; + __IO uint16_t ER16 : 1; + __IO uint16_t ER17 : 1; + __IO uint16_t ER18 : 1; + __IO uint16_t ER19 : 1; + __IO uint16_t ER20 : 1; + __IO uint16_t ER21 : 1; + __IO uint16_t ER22 : 1; + __IO uint16_t ER23 : 1; + __IO uint16_t ER24 : 1; + __IO uint16_t ER25 : 1; + __IO uint16_t ER26 : 1; + __IO uint16_t ER27 : 1; + __IO uint16_t ER28 : 1; + __IO uint16_t ER29 : 1; + __IO uint16_t ER30 : 1; + __IO uint16_t ER31 : 1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint16_t ECL0 : 1; + __IO uint16_t ECL1 : 1; + __IO uint16_t ECL2 : 1; + __IO uint16_t ECL3 : 1; + __IO uint16_t ECL4 : 1; + __IO uint16_t ECL5 : 1; + __IO uint16_t ECL6 : 1; + __IO uint16_t ECL7 : 1; + __IO uint16_t ECL8 : 1; + __IO uint16_t ECL9 : 1; + __IO uint16_t ECL10 : 1; + __IO uint16_t ECL11 : 1; + __IO uint16_t ECL12 : 1; + __IO uint16_t ECL13 : 1; + __IO uint16_t ECL14 : 1; + __IO uint16_t ECL15 : 1; + __IO uint16_t ECL16 : 1; + __IO uint16_t ECL17 : 1; + __IO uint16_t ECL18 : 1; + __IO uint16_t ECL19 : 1; + __IO uint16_t ECL20 : 1; + __IO uint16_t ECL21 : 1; + __IO uint16_t ECL22 : 1; + __IO uint16_t ECL23 : 1; + __IO uint16_t ECL24 : 1; + __IO uint16_t ECL25 : 1; + __IO uint16_t ECL26 : 1; + __IO uint16_t ECL27 : 1; + __IO uint16_t ECL28 : 1; + __IO uint16_t ECL29 : 1; + __IO uint16_t ECL30 : 1; + __IO uint16_t ECL31 : 1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 : 1; + __IO uint32_t LB0 : 1; + __IO uint32_t LA1 : 1; + __IO uint32_t LB1 : 1; + __IO uint32_t LA2 : 1; + __IO uint32_t LB2 : 1; + __IO uint32_t LA3 : 1; + __IO uint32_t LB3 : 1; + __IO uint32_t LA4 : 1; + __IO uint32_t LB4 : 1; + __IO uint32_t LA5 : 1; + __IO uint32_t LB5 : 1; + __IO uint32_t LA6 : 1; + __IO uint32_t LB6 : 1; + __IO uint32_t LA7 : 1; + __IO uint32_t LB7 : 1; + __IO uint32_t LA8 : 1; + __IO uint32_t LB8 : 1; + __IO uint32_t LA9 : 1; + __IO uint32_t LB9 : 1; + __IO uint32_t LA10 : 1; + __IO uint32_t LB10 : 1; + __IO uint32_t LA11 : 1; + __IO uint32_t LB11 : 1; + __IO uint32_t LA12 : 1; + __IO uint32_t LB12 : 1; + __IO uint32_t LA13 : 1; + __IO uint32_t LB13 : 1; + __IO uint32_t LA14 : 1; + __IO uint32_t LB14 : 1; + __IO uint32_t LA15 : 1; + __IO uint32_t LB15 : 1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_elvr1_field +{ + __IO uint32_t LA16 : 1; + __IO uint32_t LB16 : 1; + __IO uint32_t LA17 : 1; + __IO uint32_t LB17 : 1; + __IO uint32_t LA18 : 1; + __IO uint32_t LB18 : 1; + __IO uint32_t LA19 : 1; + __IO uint32_t LB19 : 1; + __IO uint32_t LA20 : 1; + __IO uint32_t LB20 : 1; + __IO uint32_t LA21 : 1; + __IO uint32_t LB21 : 1; + __IO uint32_t LA22 : 1; + __IO uint32_t LB22 : 1; + __IO uint32_t LA23 : 1; + __IO uint32_t LB23 : 1; + __IO uint32_t LA24 : 1; + __IO uint32_t LB24 : 1; + __IO uint32_t LA25 : 1; + __IO uint32_t LB25 : 1; + __IO uint32_t LA26 : 1; + __IO uint32_t LB26 : 1; + __IO uint32_t LA27 : 1; + __IO uint32_t LB27 : 1; + __IO uint32_t LA28 : 1; + __IO uint32_t LB28 : 1; + __IO uint32_t LA29 : 1; + __IO uint32_t LB29 : 1; + __IO uint32_t LA30 : 1; + __IO uint32_t LB30 : 1; + __IO uint32_t LA31 : 1; + __IO uint32_t LB31 : 1; +} stc_exti_elvr1_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint8_t NR0 : 1; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint8_t NCL0 : 1; +} stc_exti_nmicl_field_t; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* INTREQ_MODULE register bit fields */ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t DRQSEL0 : 1; + __IO uint32_t DRQSEL1 : 1; + __IO uint32_t DRQSEL2 : 1; + __IO uint32_t DRQSEL3 : 1; + __IO uint32_t DRQSEL4 : 1; + __IO uint32_t DRQSEL5 : 1; + __IO uint32_t DRQSEL6 : 1; + __IO uint32_t DRQSEL7 : 1; + __IO uint32_t DRQSEL8 : 1; + __IO uint32_t DRQSEL9 : 1; + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; + __IO uint32_t DRQSEL15 : 1; + __IO uint32_t DRQSEL16 : 1; + __IO uint32_t DRQSEL17 : 1; + __IO uint32_t DRQSEL18 : 1; + __IO uint32_t DRQSEL19 : 1; + __IO uint32_t DRQSEL20 : 1; + __IO uint32_t DRQSEL21 : 1; + __IO uint32_t DRQSEL22 : 1; + __IO uint32_t DRQSEL23 : 1; + __IO uint32_t DRQSEL24 : 1; + __IO uint32_t DRQSEL25 : 1; + __IO uint32_t DRQSEL26 : 1; + __IO uint32_t DRQSEL27 : 1; + __IO uint32_t DRQSEL28 : 1; + __IO uint32_t DRQSEL29 : 1; + __IO uint32_t DRQSEL30 : 1; + __IO uint32_t DRQSEL31 : 1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_oddpks_field +{ + __IO uint8_t ODDPKS0 : 1; + __IO uint8_t ODDPKS1 : 1; + __IO uint8_t ODDPKS2 : 1; + __IO uint8_t ODDPKS3 : 1; + __IO uint8_t ODDPKS4 : 1; +} stc_intreq_oddpks_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI : 1; + __IO uint32_t HWINT : 1; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq00mon_field +{ + __IO uint32_t FCSINT : 1; +} stc_intreq_irq00mon_field_t; + +typedef struct stc_intreq_irq01mon_field +{ + __IO uint32_t SWWDTINT : 1; +} stc_intreq_irq01mon_field_t; + +typedef struct stc_intreq_irq02mon_field +{ + __IO uint32_t LVDINT : 1; +} stc_intreq_irq02mon_field_t; + +typedef struct stc_intreq_irq03mon_field +{ + __IO uint32_t WAVE0INT0 : 1; + __IO uint32_t WAVE0INT1 : 1; + __IO uint32_t WAVE0INT2 : 1; + __IO uint32_t WAVE0INT3 : 1; + __IO uint32_t WAVE1INT0 : 1; + __IO uint32_t WAVE1INT1 : 1; + __IO uint32_t WAVE1INT2 : 1; + __IO uint32_t WAVE1INT3 : 1; + __IO uint32_t WAVE2INT0 : 1; + __IO uint32_t WAVE2INT1 : 1; + __IO uint32_t WAVE2INT2 : 1; + __IO uint32_t WAVE2INT3 : 1; +} stc_intreq_irq03mon_field_t; + +typedef struct stc_intreq_irq04mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; +} stc_intreq_irq04mon_field_t; + +typedef struct stc_intreq_irq05mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; + __IO uint32_t EXTINT8 : 1; + __IO uint32_t EXTINT9 : 1; + __IO uint32_t EXTINT10 : 1; + __IO uint32_t EXTINT11 : 1; + __IO uint32_t EXTINT12 : 1; + __IO uint32_t EXTINT13 : 1; + __IO uint32_t EXTINT14 : 1; + __IO uint32_t EXTINT15 : 1; + __IO uint32_t EXTINT16 : 1; + __IO uint32_t EXTINT17 : 1; + __IO uint32_t EXTINT18 : 1; + __IO uint32_t EXTINT19 : 1; + __IO uint32_t EXTINT20 : 1; + __IO uint32_t EXTINT21 : 1; + __IO uint32_t EXTINT22 : 1; + __IO uint32_t EXTINT23 : 1; +} stc_intreq_irq05mon_field_t; + +typedef struct stc_intreq_irq06mon_field +{ + __IO uint32_t TIMINT1 : 1; + __IO uint32_t TIMINT2 : 1; + __IO uint32_t QUD0INT0 : 1; + __IO uint32_t QUD0INT1 : 1; + __IO uint32_t QUD0INT2 : 1; + __IO uint32_t QUD0INT3 : 1; + __IO uint32_t QUD0INT4 : 1; + __IO uint32_t QUD0INT5 : 1; + __IO uint32_t QUD1INT0 : 1; + __IO uint32_t QUD1INT1 : 1; + __IO uint32_t QUD1INT2 : 1; + __IO uint32_t QUD1INT3 : 1; + __IO uint32_t QUD1INT4 : 1; + __IO uint32_t QUD1INT5 : 1; + __IO uint32_t QUD2INT0 : 1; + __IO uint32_t QUD2INT1 : 1; + __IO uint32_t QUD2INT2 : 1; + __IO uint32_t QUD2INT3 : 1; + __IO uint32_t QUD2INT4 : 1; + __IO uint32_t QUD2INT5 : 1; +} stc_intreq_irq06mon_field_t; + +typedef struct stc_intreq_irq07mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq07mon_field_t; + +typedef struct stc_intreq_irq08mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq08mon_field_t; + +typedef struct stc_intreq_irq09mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq09mon_field_t; + +typedef struct stc_intreq_irq10mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq10mon_field_t; + +typedef struct stc_intreq_irq11mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq11mon_field_t; + +typedef struct stc_intreq_irq12mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq12mon_field_t; + +typedef struct stc_intreq_irq13mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq13mon_field_t; + +typedef struct stc_intreq_irq14mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq14mon_field_t; + +typedef struct stc_intreq_irq15mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq15mon_field_t; + +typedef struct stc_intreq_irq16mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq16mon_field_t; + +typedef struct stc_intreq_irq17mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq17mon_field_t; + +typedef struct stc_intreq_irq18mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq18mon_field_t; + +typedef struct stc_intreq_irq19mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq19mon_field_t; + +typedef struct stc_intreq_irq20mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq20mon_field_t; + +typedef struct stc_intreq_irq21mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq21mon_field_t; + +typedef struct stc_intreq_irq22mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq22mon_field_t; + +typedef struct stc_intreq_irq23mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; + __IO uint32_t PPGINT3 : 1; + __IO uint32_t PPGINT4 : 1; + __IO uint32_t PPGINT5 : 1; + __IO uint32_t PPGINT6 : 1; + __IO uint32_t PPGINT7 : 1; + __IO uint32_t PPGINT8 : 1; +} stc_intreq_irq23mon_field_t; + +typedef struct stc_intreq_irq24mon_field +{ + __IO uint32_t MOSCINT : 1; + __IO uint32_t SOSCINT : 1; + __IO uint32_t MPLLINT : 1; + __IO uint32_t UPLLINT : 1; + __IO uint32_t WCINT : 1; +} stc_intreq_irq24mon_field_t; + +typedef struct stc_intreq_irq25mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq25mon_field_t; + +typedef struct stc_intreq_irq26mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq26mon_field_t; + +typedef struct stc_intreq_irq27mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq27mon_field_t; + +typedef struct stc_intreq_irq28mon_field +{ + __IO uint32_t FRT0INT0 : 1; + __IO uint32_t FRT0INT1 : 1; + __IO uint32_t FRT0INT2 : 1; + __IO uint32_t FRT0INT3 : 1; + __IO uint32_t FRT0INT4 : 1; + __IO uint32_t FRT0INT5 : 1; + __IO uint32_t FRT1INT0 : 1; + __IO uint32_t FRT1INT1 : 1; + __IO uint32_t FRT1INT2 : 1; + __IO uint32_t FRT1INT3 : 1; + __IO uint32_t FRT1INT4 : 1; + __IO uint32_t FRT1INT5 : 1; + __IO uint32_t FRT2INT0 : 1; + __IO uint32_t FRT2INT1 : 1; + __IO uint32_t FRT2INT2 : 1; + __IO uint32_t FRT2INT3 : 1; + __IO uint32_t FRT2INT4 : 1; + __IO uint32_t FRT2INT5 : 1; +} stc_intreq_irq28mon_field_t; + +typedef struct stc_intreq_irq29mon_field +{ + __IO uint32_t ICU0INT0 : 1; + __IO uint32_t ICU0INT1 : 1; + __IO uint32_t ICU0INT2 : 1; + __IO uint32_t ICU0INT3 : 1; + __IO uint32_t ICU1INT0 : 1; + __IO uint32_t ICU1INT1 : 1; + __IO uint32_t ICU1INT2 : 1; + __IO uint32_t ICU1INT3 : 1; + __IO uint32_t ICU2INT0 : 1; + __IO uint32_t ICU2INT1 : 1; + __IO uint32_t ICU2INT2 : 1; + __IO uint32_t ICU2INT3 : 1; +} stc_intreq_irq29mon_field_t; + +typedef struct stc_intreq_irq30mon_field +{ + __IO uint32_t OCU0INT0 : 1; + __IO uint32_t OCU0INT1 : 1; + __IO uint32_t OCU0INT2 : 1; + __IO uint32_t OCU0INT3 : 1; + __IO uint32_t OCU0INT4 : 1; + __IO uint32_t OCU0INT5 : 1; + __IO uint32_t OCU1INT0 : 1; + __IO uint32_t OCU1INT1 : 1; + __IO uint32_t OCU1INT2 : 1; + __IO uint32_t OCU1INT3 : 1; + __IO uint32_t OCU1INT4 : 1; + __IO uint32_t OCU1INT5 : 1; + __IO uint32_t OCU2INT0 : 1; + __IO uint32_t OCU2INT1 : 1; + __IO uint32_t OCU2INT2 : 1; + __IO uint32_t OCU2INT3 : 1; + __IO uint32_t OCU2INT4 : 1; + __IO uint32_t OCU2INT5 : 1; +} stc_intreq_irq30mon_field_t; + +typedef struct stc_intreq_irq31mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; + __IO uint32_t BTINT8 : 1; + __IO uint32_t BTINT9 : 1; + __IO uint32_t BTINT10 : 1; + __IO uint32_t BTINT11 : 1; + __IO uint32_t BTINT12 : 1; + __IO uint32_t BTINT13 : 1; + __IO uint32_t BTINT14 : 1; + __IO uint32_t BTINT15 : 1; +} stc_intreq_irq31mon_field_t; + +typedef struct stc_intreq_irq32mon_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t MAC0SBD : 1; + __IO uint32_t MAC0PMI : 1; + __IO uint32_t MAC0LPI : 1; +} stc_intreq_irq32mon_field_t; + +typedef struct stc_intreq_irq33mon_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t MAC1SBD : 1; + __IO uint32_t MAC1PMI : 1; +} stc_intreq_irq33mon_field_t; + +typedef struct stc_intreq_irq34mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; +} stc_intreq_irq34mon_field_t; + +typedef struct stc_intreq_irq35mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; + __IO uint32_t USB0INT5 : 1; +} stc_intreq_irq35mon_field_t; + +typedef struct stc_intreq_irq36mon_field +{ + __IO uint32_t USB1INT0 : 1; + __IO uint32_t USB1INT1 : 1; + __IO uint32_t USB1INT2 : 1; + __IO uint32_t USB1INT3 : 1; + __IO uint32_t USB1INT4 : 1; +} stc_intreq_irq36mon_field_t; + +typedef struct stc_intreq_irq37mon_field +{ + __IO uint32_t USB1INT0 : 1; + __IO uint32_t USB1INT1 : 1; + __IO uint32_t USB1INT2 : 1; + __IO uint32_t USB1INT3 : 1; + __IO uint32_t USB1INT4 : 1; + __IO uint32_t USB1INT5 : 1; +} stc_intreq_irq37mon_field_t; + +typedef struct stc_intreq_irq38mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq38mon_field_t; + +typedef struct stc_intreq_irq39mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq39mon_field_t; + +typedef struct stc_intreq_irq40mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq40mon_field_t; + +typedef struct stc_intreq_irq41mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq41mon_field_t; + +typedef struct stc_intreq_irq42mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq42mon_field_t; + +typedef struct stc_intreq_irq43mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq43mon_field_t; + +typedef struct stc_intreq_irq44mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq44mon_field_t; + +typedef struct stc_intreq_irq45mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq45mon_field_t; + +typedef struct stc_intreq_irq46mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; + __IO uint32_t BTINT8 : 1; + __IO uint32_t BTINT9 : 1; + __IO uint32_t BTINT10 : 1; + __IO uint32_t BTINT11 : 1; + __IO uint32_t BTINT12 : 1; + __IO uint32_t BTINT13 : 1; + __IO uint32_t BTINT14 : 1; + __IO uint32_t BTINT15 : 1; +} stc_intreq_irq46mon_field_t; + +typedef struct stc_intreq_drqsel1_field +{ + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; +} stc_intreq_drqsel1_field_t; + +typedef struct stc_intreq_dqesel_field +{ + __IO uint32_t ESEL100 : 1; + __IO uint32_t ESEL101 : 1; + __IO uint32_t ESEL102 : 1; + __IO uint32_t ESEL103 : 1; + __IO uint32_t ESEL110 : 1; + __IO uint32_t ESEL111 : 1; + __IO uint32_t ESEL112 : 1; + __IO uint32_t ESEL113 : 1; + __IO uint32_t ESEL240 : 1; + __IO uint32_t ESEL241 : 1; + __IO uint32_t ESEL242 : 1; + __IO uint32_t ESEL243 : 1; + __IO uint32_t ESEL250 : 1; + __IO uint32_t ESEL251 : 1; + __IO uint32_t ESEL252 : 1; + __IO uint32_t ESEL253 : 1; + __IO uint32_t ESEL260 : 1; + __IO uint32_t ESEL261 : 1; + __IO uint32_t ESEL262 : 1; + __IO uint32_t ESEL263 : 1; + __IO uint32_t ESEL270 : 1; + __IO uint32_t ESEL271 : 1; + __IO uint32_t ESEL272 : 1; + __IO uint32_t ESEL273 : 1; + __IO uint32_t ESEL300 : 1; + __IO uint32_t ESEL301 : 1; + __IO uint32_t ESEL302 : 1; + __IO uint32_t ESEL303 : 1; + __IO uint32_t ESEL310 : 1; + __IO uint32_t ESEL311 : 1; + __IO uint32_t ESEL312 : 1; + __IO uint32_t ESEL313 : 1; +} stc_intreq_dqesel_field_t; + +typedef struct stc_intreq_oddpks1_field +{ + __IO uint8_t ODDPKS10 : 1; + __IO uint8_t ODDPKS11 : 1; + __IO uint8_t ODDPKS12 : 1; + __IO uint8_t ODDPKS13 : 1; + __IO uint8_t ODDPKS14 : 1; +} stc_intreq_oddpks1_field_t; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* GPIO_MODULE register bit fields */ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pfr5_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfr8_field_t; + + +typedef struct stc_gpio_pfra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pfra_field_t; + +typedef struct stc_gpio_pfrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfrc_field_t; + +typedef struct stc_gpio_pfrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfrd_field_t; + +typedef struct stc_gpio_pfre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfre_field_t; + +typedef struct stc_gpio_pfrf_field +{ + uint32_t RESERVED1 : 5; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pfrf_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pcr5_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_pcra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pcra_field_t; + +typedef struct stc_gpio_pcrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcrc_field_t; + +typedef struct stc_gpio_pcrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pcrd_field_t; + +typedef struct stc_gpio_pcre_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pcre_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_ddr5_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_ddra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_ddra_field_t; + +typedef struct stc_gpio_ddrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddrc_field_t; + +typedef struct stc_gpio_ddrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddrd_field_t; + +typedef struct stc_gpio_ddre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddre_field_t; + +typedef struct stc_gpio_ddrf_field +{ + uint32_t RESERVED1 : 5; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_ddrf_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pdir5_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdira_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdira_field_t; + +typedef struct stc_gpio_pdirc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdirc_field_t; + +typedef struct stc_gpio_pdird_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdird_field_t; + +typedef struct stc_gpio_pdire_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdire_field_t; + +typedef struct stc_gpio_pdirf_field +{ + uint32_t RESERVED1 : 5; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pdirf_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pdor5_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_pdora_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdora_field_t; + +typedef struct stc_gpio_pdorc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdorc_field_t; + +typedef struct stc_gpio_pdord_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdord_field_t; + +typedef struct stc_gpio_pdore_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdore_field_t; + +typedef struct stc_gpio_pdorf_field +{ + uint32_t RESERVED1 : 5; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pdorf_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN0 : 1; + __IO uint32_t AN1 : 1; + __IO uint32_t AN2 : 1; + __IO uint32_t AN3 : 1; + __IO uint32_t AN4 : 1; + __IO uint32_t AN5 : 1; + __IO uint32_t AN6 : 1; + __IO uint32_t AN7 : 1; + __IO uint32_t AN8 : 1; + __IO uint32_t AN9 : 1; + __IO uint32_t AN10 : 1; + __IO uint32_t AN11 : 1; + __IO uint32_t AN12 : 1; + __IO uint32_t AN13 : 1; + __IO uint32_t AN14 : 1; + __IO uint32_t AN15 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t AN24 : 1; + __IO uint32_t AN25 : 1; + __IO uint32_t AN26 : 1; + __IO uint32_t AN27 : 1; + __IO uint32_t AN28 : 1; + __IO uint32_t AN29 : 1; + __IO uint32_t AN30 : 1; + __IO uint32_t AN31 : 1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + __IO uint32_t SUBXC : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MAINXC : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t USB0C : 1; + __IO uint32_t USB1C : 1; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + __IO uint32_t NMIS : 1; + __IO uint32_t CROUTE0 : 1; + __IO uint32_t CROUTE1 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SUBOUTE0 : 1; + __IO uint32_t SUBOUTE1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t USBP0E : 1; + uint32_t RESERVED3 : 3; + __IO uint32_t USBP1E : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t JTAGEN0B : 1; + __IO uint32_t JTAGEN1S : 1; + uint32_t RESERVED5 : 6; + __IO uint32_t TRC0E : 1; + __IO uint32_t TRC1E : 1; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + __IO uint32_t RTO00E0 : 1; + __IO uint32_t RTO00E1 : 1; + __IO uint32_t RTO01E0 : 1; + __IO uint32_t RTO01E1 : 1; + __IO uint32_t RTO02E0 : 1; + __IO uint32_t RTO02E1 : 1; + __IO uint32_t RTO03E0 : 1; + __IO uint32_t RTO03E1 : 1; + __IO uint32_t RTO04E0 : 1; + __IO uint32_t RTO04E1 : 1; + __IO uint32_t RTO05E0 : 1; + __IO uint32_t RTO05E1 : 1; + __IO uint32_t DTTI0C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI0S0 : 1; + __IO uint32_t DTTI0S1 : 1; + __IO uint32_t FRCK0S0 : 1; + __IO uint32_t FRCK0S1 : 1; + __IO uint32_t IC00S0 : 1; + __IO uint32_t IC00S1 : 1; + __IO uint32_t IC00S2 : 1; + __IO uint32_t IC01S0 : 1; + __IO uint32_t IC01S1 : 1; + __IO uint32_t IC01S2 : 1; + __IO uint32_t IC02S0 : 1; + __IO uint32_t IC02S1 : 1; + __IO uint32_t IC02S2 : 1; + __IO uint32_t IC03S0 : 1; + __IO uint32_t IC03S1 : 1; + __IO uint32_t IC03S2 : 1; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + __IO uint32_t RTO10E0 : 1; + __IO uint32_t RTO10E1 : 1; + __IO uint32_t RTO11E0 : 1; + __IO uint32_t RTO11E1 : 1; + __IO uint32_t RTO12E0 : 1; + __IO uint32_t RTO12E1 : 1; + __IO uint32_t RTO13E0 : 1; + __IO uint32_t RTO13E1 : 1; + __IO uint32_t RTO14E0 : 1; + __IO uint32_t RTO14E1 : 1; + __IO uint32_t RTO15E0 : 1; + __IO uint32_t RTO15E1 : 1; + __IO uint32_t DTTI1C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI1S0 : 1; + __IO uint32_t DTTI1S1 : 1; + __IO uint32_t FRCK1S0 : 1; + __IO uint32_t FRCK1S1 : 1; + __IO uint32_t IC10S0 : 1; + __IO uint32_t IC10S1 : 1; + __IO uint32_t IC10S2 : 1; + __IO uint32_t IC11S0 : 1; + __IO uint32_t IC11S1 : 1; + __IO uint32_t IC11S2 : 1; + __IO uint32_t IC12S0 : 1; + __IO uint32_t IC12S1 : 1; + __IO uint32_t IC12S2 : 1; + __IO uint32_t IC13S0 : 1; + __IO uint32_t IC13S1 : 1; + __IO uint32_t IC13S2 : 1; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr03_field +{ + __IO uint32_t RTO20E0 : 1; + __IO uint32_t RTO20E1 : 1; + __IO uint32_t RTO21E0 : 1; + __IO uint32_t RTO21E1 : 1; + __IO uint32_t RTO22E0 : 1; + __IO uint32_t RTO22E1 : 1; + __IO uint32_t RTO23E0 : 1; + __IO uint32_t RTO23E1 : 1; + __IO uint32_t RTO24E0 : 1; + __IO uint32_t RTO24E1 : 1; + __IO uint32_t RTO25E0 : 1; + __IO uint32_t RTO25E1 : 1; + __IO uint32_t DTTI2C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI2S0 : 1; + __IO uint32_t DTTI2S1 : 1; + __IO uint32_t FRCK2S0 : 1; + __IO uint32_t FRCK2S1 : 1; + __IO uint32_t IC20S0 : 1; + __IO uint32_t IC20S1 : 1; + __IO uint32_t IC20S2 : 1; + __IO uint32_t IC21S0 : 1; + __IO uint32_t IC21S1 : 1; + __IO uint32_t IC21S2 : 1; + __IO uint32_t IC22S0 : 1; + __IO uint32_t IC22S1 : 1; + __IO uint32_t IC22S2 : 1; + __IO uint32_t IC23S0 : 1; + __IO uint32_t IC23S1 : 1; + __IO uint32_t IC23S2 : 1; +} stc_gpio_epfr03_field_t; + +typedef struct stc_gpio_epfr04_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA0E0 : 1; + __IO uint32_t TIOA0E1 : 1; + __IO uint32_t TIOB0S0 : 1; + __IO uint32_t TIOB0S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA1S0 : 1; + __IO uint32_t TIOA1S1 : 1; + __IO uint32_t TIOA1E0 : 1; + __IO uint32_t TIOA1E1 : 1; + __IO uint32_t TIOB1S0 : 1; + __IO uint32_t TIOB1S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA2E0 : 1; + __IO uint32_t TIOA2E1 : 1; + __IO uint32_t TIOB2S0 : 1; + __IO uint32_t TIOB2S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA3S0 : 1; + __IO uint32_t TIOA3S1 : 1; + __IO uint32_t TIOA3E0 : 1; + __IO uint32_t TIOA3E1 : 1; + __IO uint32_t TIOB3S0 : 1; + __IO uint32_t TIOB3S1 : 1; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA4E0 : 1; + __IO uint32_t TIOA4E1 : 1; + __IO uint32_t TIOB4S0 : 1; + __IO uint32_t TIOB4S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA5S0 : 1; + __IO uint32_t TIOA5S1 : 1; + __IO uint32_t TIOA5E0 : 1; + __IO uint32_t TIOA5E1 : 1; + __IO uint32_t TIOB5S0 : 1; + __IO uint32_t TIOB5S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA6E0 : 1; + __IO uint32_t TIOA6E1 : 1; + __IO uint32_t TIOB6S0 : 1; + __IO uint32_t TIOB6S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA7S0 : 1; + __IO uint32_t TIOA7S1 : 1; + __IO uint32_t TIOA7E0 : 1; + __IO uint32_t TIOA7E1 : 1; + __IO uint32_t TIOB7S0 : 1; + __IO uint32_t TIOB7S1 : 1; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + __IO uint32_t EINT00S0 : 1; + __IO uint32_t EINT00S1 : 1; + __IO uint32_t EINT01S0 : 1; + __IO uint32_t EINT01S1 : 1; + __IO uint32_t EINT02S0 : 1; + __IO uint32_t EINT02S1 : 1; + __IO uint32_t EINT03S0 : 1; + __IO uint32_t EINT03S1 : 1; + __IO uint32_t EINT04S0 : 1; + __IO uint32_t EINT04S1 : 1; + __IO uint32_t EINT05S0 : 1; + __IO uint32_t EINT05S1 : 1; + __IO uint32_t EINT06S0 : 1; + __IO uint32_t EINT06S1 : 1; + __IO uint32_t EINT07S0 : 1; + __IO uint32_t EINT07S1 : 1; + __IO uint32_t EINT08S0 : 1; + __IO uint32_t EINT08S1 : 1; + __IO uint32_t EINT09S0 : 1; + __IO uint32_t EINT09S1 : 1; + __IO uint32_t EINT10S0 : 1; + __IO uint32_t EINT10S1 : 1; + __IO uint32_t EINT11S0 : 1; + __IO uint32_t EINT11S1 : 1; + __IO uint32_t EINT12S0 : 1; + __IO uint32_t EINT12S1 : 1; + __IO uint32_t EINT13S0 : 1; + __IO uint32_t EINT13S1 : 1; + __IO uint32_t EINT14S0 : 1; + __IO uint32_t EINT14S1 : 1; + __IO uint32_t EINT15S0 : 1; + __IO uint32_t EINT15S1 : 1; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + uint32_t RESERVED1 : 4; + __IO uint32_t SIN0S0 : 1; + __IO uint32_t SIN0S1 : 1; + __IO uint32_t SOT0B0 : 1; + __IO uint32_t SOT0B1 : 1; + __IO uint32_t SCK0B0 : 1; + __IO uint32_t SCK0B1 : 1; + __IO uint32_t SIN1S0 : 1; + __IO uint32_t SIN1S1 : 1; + __IO uint32_t SOT1B0 : 1; + __IO uint32_t SOT1B1 : 1; + __IO uint32_t SCK1B0 : 1; + __IO uint32_t SCK1B1 : 1; + __IO uint32_t SIN2S0 : 1; + __IO uint32_t SIN2S1 : 1; + __IO uint32_t SOT2B0 : 1; + __IO uint32_t SOT2B1 : 1; + __IO uint32_t SCK2B0 : 1; + __IO uint32_t SCK2B1 : 1; + __IO uint32_t SIN3S0 : 1; + __IO uint32_t SIN3S1 : 1; + __IO uint32_t SOT3B0 : 1; + __IO uint32_t SOT3B1 : 1; + __IO uint32_t SCK3B0 : 1; + __IO uint32_t SCK3B1 : 1; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + __IO uint32_t RTS4E0 : 1; + __IO uint32_t RTS4E1 : 1; + __IO uint32_t CTS4S0 : 1; + __IO uint32_t CTS4S1 : 1; + __IO uint32_t SIN4S0 : 1; + __IO uint32_t SIN4S1 : 1; + __IO uint32_t SOT4B0 : 1; + __IO uint32_t SOT4B1 : 1; + __IO uint32_t SCK4B0 : 1; + __IO uint32_t SCK4B1 : 1; + __IO uint32_t SIN5S0 : 1; + __IO uint32_t SIN5S1 : 1; + __IO uint32_t SOT5B0 : 1; + __IO uint32_t SOT5B1 : 1; + __IO uint32_t SCK5B0 : 1; + __IO uint32_t SCK5B1 : 1; + __IO uint32_t SIN6S0 : 1; + __IO uint32_t SIN6S1 : 1; + __IO uint32_t SOT6B0 : 1; + __IO uint32_t SOT6B1 : 1; + __IO uint32_t SCK6B0 : 1; + __IO uint32_t SCK6B1 : 1; + __IO uint32_t SIN7S0 : 1; + __IO uint32_t SIN7S1 : 1; + __IO uint32_t SOT7B0 : 1; + __IO uint32_t SOT7B1 : 1; + __IO uint32_t SCK7B0 : 1; + __IO uint32_t SCK7B1 : 1; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + __IO uint32_t QAIN0S0 : 1; + __IO uint32_t QAIN0S1 : 1; + __IO uint32_t QBIN0S0 : 1; + __IO uint32_t QBIN0S1 : 1; + __IO uint32_t QZIN0S0 : 1; + __IO uint32_t QZIN0S1 : 1; + __IO uint32_t QAIN1S0 : 1; + __IO uint32_t QAIN1S1 : 1; + __IO uint32_t QBIN1S0 : 1; + __IO uint32_t QBIN1S1 : 1; + __IO uint32_t QZIN1S0 : 1; + __IO uint32_t QZIN1S1 : 1; + __IO uint32_t ADTRG0S0 : 1; + __IO uint32_t ADTRG0S1 : 1; + __IO uint32_t ADTRG0S2 : 1; + __IO uint32_t ADTRG0S3 : 1; + __IO uint32_t ADTRG1S0 : 1; + __IO uint32_t ADTRG1S1 : 1; + __IO uint32_t ADTRG1S2 : 1; + __IO uint32_t ADTRG1S3 : 1; + __IO uint32_t ADTRG2S0 : 1; + __IO uint32_t ADTRG2S1 : 1; + __IO uint32_t ADTRG2S2 : 1; + __IO uint32_t ADTRG2S3 : 1; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB : 1; + __IO uint32_t UEDTHB : 1; + __IO uint32_t UECLKE : 1; + __IO uint32_t UEWEXE : 1; + __IO uint32_t UEDQME : 1; + __IO uint32_t UEOEXE : 1; + __IO uint32_t UEFLSE : 1; + __IO uint32_t UECS1E : 1; + __IO uint32_t UECS2E : 1; + __IO uint32_t UECS3E : 1; + __IO uint32_t UECS4E : 1; + __IO uint32_t UECS5E : 1; + __IO uint32_t UECS6E : 1; + __IO uint32_t UECS7E : 1; + __IO uint32_t UEAOOE : 1; + __IO uint32_t UEA08E : 1; + __IO uint32_t UEA09E : 1; + __IO uint32_t UEA10E : 1; + __IO uint32_t UEA11E : 1; + __IO uint32_t UEA12E : 1; + __IO uint32_t UEA13E : 1; + __IO uint32_t UEA14E : 1; + __IO uint32_t UEA15E : 1; + __IO uint32_t UEA16E : 1; + __IO uint32_t UEA17E : 1; + __IO uint32_t UEA18E : 1; +} stc_gpio_epfr10_field_t; + +typedef struct stc_gpio_epfr11_field +{ + __IO uint32_t UEALEE : 1; + __IO uint32_t UECS0E : 1; + __IO uint32_t UEA01E : 1; + __IO uint32_t UEA02E : 1; + __IO uint32_t UEA03E : 1; + __IO uint32_t UEA04E : 1; + __IO uint32_t UEA05E : 1; + __IO uint32_t UEA06E : 1; + __IO uint32_t UEA07E : 1; + __IO uint32_t UED00B : 1; + __IO uint32_t UED01B : 1; + __IO uint32_t UED02B : 1; + __IO uint32_t UED03B : 1; + __IO uint32_t UED04B : 1; + __IO uint32_t UED05B : 1; + __IO uint32_t UED06B : 1; + __IO uint32_t UED07B : 1; + __IO uint32_t UED08B : 1; + __IO uint32_t UED09B : 1; + __IO uint32_t UED10B : 1; + __IO uint32_t UED11B : 1; + __IO uint32_t UED12B : 1; + __IO uint32_t UED13B : 1; + __IO uint32_t UED14B : 1; + __IO uint32_t UED15B : 1; + __IO uint32_t UERLC : 1; +} stc_gpio_epfr11_field_t; + +typedef struct stc_gpio_epfr12_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA8E0 : 1; + __IO uint32_t TIOA8E1 : 1; + __IO uint32_t TIOB8S0 : 1; + __IO uint32_t TIOB8S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA9S0 : 1; + __IO uint32_t TIOA9S1 : 1; + __IO uint32_t TIOA9E0 : 1; + __IO uint32_t TIOA9E1 : 1; + __IO uint32_t TIOB9S0 : 1; + __IO uint32_t TIOB9S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA10E0 : 1; + __IO uint32_t TIOA10E1 : 1; + __IO uint32_t TIOB10S0 : 1; + __IO uint32_t TIOB10S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA11S0 : 1; + __IO uint32_t TIOA11S1 : 1; + __IO uint32_t TIOA11E0 : 1; + __IO uint32_t TIOA11E1 : 1; + __IO uint32_t TIOB11S0 : 1; + __IO uint32_t TIOB11S1 : 1; +} stc_gpio_epfr12_field_t; + +typedef struct stc_gpio_epfr13_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA12E0 : 1; + __IO uint32_t TIOA12E1 : 1; + __IO uint32_t TIOB12S0 : 1; + __IO uint32_t TIOB12S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA13S0 : 1; + __IO uint32_t TIOA13S1 : 1; + __IO uint32_t TIOA13E0 : 1; + __IO uint32_t TIOA13E1 : 1; + __IO uint32_t TIOB13S0 : 1; + __IO uint32_t TIOB13S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA14E0 : 1; + __IO uint32_t TIOA14E1 : 1; + __IO uint32_t TIOB14S0 : 1; + __IO uint32_t TIOB14S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA15S0 : 1; + __IO uint32_t TIOA15S1 : 1; + __IO uint32_t TIOA15E0 : 1; + __IO uint32_t TIOA15E1 : 1; + __IO uint32_t TIOB15S0 : 1; + __IO uint32_t TIOB15S1 : 1; +} stc_gpio_epfr13_field_t; + +typedef struct stc_gpio_epfr14_field +{ + __IO uint32_t QAIN2S0 : 1; + __IO uint32_t QAIN2S1 : 1; + __IO uint32_t QBIN2S0 : 1; + __IO uint32_t QBIN2S1 : 1; + __IO uint32_t QZIN2S0 : 1; + __IO uint32_t QZIN2S1 : 1; + uint32_t RESERVED1 : 12; + __IO uint32_t E_TD0E : 1; + __IO uint32_t E_TD1E : 1; + __IO uint32_t E_TE0E : 1; + __IO uint32_t E_TE1E : 1; + __IO uint32_t E_MC0E : 1; + __IO uint32_t E_MC1B : 1; + __IO uint32_t E_MD0B : 1; + __IO uint32_t E_MD1B : 1; + __IO uint32_t E_CKE : 1; + __IO uint32_t E_PSE : 1; + __IO uint32_t E_SPLC0 : 1; + __IO uint32_t E_SPLC1 : 1; +} stc_gpio_epfr14_field_t; + +typedef struct stc_gpio_epfr15_field +{ + __IO uint32_t EINT16S0 : 1; + __IO uint32_t EINT16S1 : 1; + __IO uint32_t EINT17S0 : 1; + __IO uint32_t EINT17S1 : 1; + __IO uint32_t EINT18S0 : 1; + __IO uint32_t EINT18S1 : 1; + __IO uint32_t EINT19S0 : 1; + __IO uint32_t EINT19S1 : 1; + __IO uint32_t EINT20S0 : 1; + __IO uint32_t EINT20S1 : 1; + __IO uint32_t EINT21S0 : 1; + __IO uint32_t EINT21S1 : 1; + __IO uint32_t EINT22S0 : 1; + __IO uint32_t EINT22S1 : 1; + __IO uint32_t EINT23S0 : 1; + __IO uint32_t EINT23S1 : 1; + __IO uint32_t EINT24S0 : 1; + __IO uint32_t EINT24S1 : 1; + __IO uint32_t EINT25S0 : 1; + __IO uint32_t EINT25S1 : 1; + __IO uint32_t EINT26S0 : 1; + __IO uint32_t EINT26S1 : 1; + __IO uint32_t EINT27S0 : 1; + __IO uint32_t EINT27S1 : 1; + __IO uint32_t EINT28S0 : 1; + __IO uint32_t EINT28S1 : 1; + __IO uint32_t EINT29S0 : 1; + __IO uint32_t EINT29S1 : 1; + __IO uint32_t EINT30S0 : 1; + __IO uint32_t EINT30S1 : 1; + __IO uint32_t EINT31S0 : 1; + __IO uint32_t EINT31S1 : 1; +} stc_gpio_epfr15_field_t; + +typedef struct stc_gpio_pzr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pzr0_field_t; + +typedef struct stc_gpio_pzr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzr1_field_t; + +typedef struct stc_gpio_pzr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pzr2_field_t; + +typedef struct stc_gpio_pzr3_field +{ + uint32_t RESERVED1 : 6; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzr3_field_t; + +typedef struct stc_gpio_pzr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pzr4_field_t; + +typedef struct stc_gpio_pzr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; +} stc_gpio_pzr5_field_t; + +typedef struct stc_gpio_pzr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pzr6_field_t; + +typedef struct stc_gpio_pzr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; +} stc_gpio_pzr7_field_t; + +typedef struct stc_gpio_pzr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzr8_field_t; + +typedef struct stc_gpio_pzra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pzra_field_t; + +typedef struct stc_gpio_pzrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzrc_field_t; + +typedef struct stc_gpio_pzrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzrd_field_t; + +typedef struct stc_gpio_pzre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzre_field_t; + +typedef struct stc_gpio_pzrf_field +{ + uint32_t RESERVED1 : 5; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pzrf_field_t; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* LVD_MODULE register bit fields */ +typedef struct stc_lvd_lvd_ctl_field +{ + uint8_t RESERVED1 : 2; + __IO uint8_t SVHI0 : 1; + __IO uint8_t SVHI1 : 1; + __IO uint8_t SVHI2 : 1; + __IO uint8_t SVHI3 : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t LVDIE : 1; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIR : 1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDCL : 1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIRDY : 1; +} stc_lvd_lvd_str2_field_t; + +/****************************************************************************** + * USB Ethernet CLK + ******************************************************************************/ +/* USB ETHERNET CLK register bit fields */ +typedef struct stc_usbethernetclk_uccr_field +{ + __IO uint8_t UCEN0 : 1; + __IO uint8_t UCSEL0 : 1; + __IO uint8_t UCSEL1 : 1; + __IO uint8_t UCEN1 : 1; + __IO uint8_t ECEN : 1; + __IO uint8_t ECSEL0 : 1; + __IO uint8_t ECSEL1 : 1; +} stc_usbethernetclk_uccr_field_t; + +typedef struct stc_usbethernetclk_upcr1_field +{ + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; +} stc_usbethernetclk_upcr1_field_t; + +typedef struct stc_usbethernetclk_upcr2_field +{ + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; +} stc_usbethernetclk_upcr2_field_t; + +typedef struct stc_usbethernetclk_upcr3_field +{ + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; +} stc_usbethernetclk_upcr3_field_t; + +typedef struct stc_usbethernetclk_upcr4_field +{ + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; +} stc_usbethernetclk_upcr4_field_t; + +typedef struct stc_usbethernetclk_up_str_field +{ + __IO uint8_t UPRDY : 1; +} stc_usbethernetclk_up_str_field_t; + +typedef struct stc_usbethernetclk_upint_enr_field +{ + __IO uint8_t UPCSE : 1; +} stc_usbethernetclk_upint_enr_field_t; + +typedef struct stc_usbethernetclk_upint_clr_field +{ + __IO uint8_t UPCSC : 1; +} stc_usbethernetclk_upint_clr_field_t; + +typedef struct stc_usbethernetclk_upint_str_field +{ + __IO uint8_t UPCSI : 1; +} stc_usbethernetclk_upint_str_field_t; + +typedef struct stc_usbethernetclk_upcr5_field +{ + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; +} stc_usbethernetclk_upcr5_field_t; + +typedef struct stc_usbethernetclk_upcr6_field +{ + __IO uint8_t UBSR0 : 1; + __IO uint8_t UBSR1 : 1; + __IO uint8_t UBSR2 : 1; + __IO uint8_t UBSR3 : 1; +} stc_usbethernetclk_upcr6_field_t; + +typedef struct stc_usbethernetclk_upcr7_field +{ + __IO uint8_t EPLLEN : 1; +} stc_usbethernetclk_upcr7_field_t; + +typedef struct stc_usbethernetclk_usben0_field +{ + __IO uint8_t USBEN0 : 1; +} stc_usbethernetclk_usben0_field_t; + +typedef struct stc_usbethernetclk_usben1_field +{ + __IO uint8_t USBEN1 : 1; +} stc_usbethernetclk_usben1_field_t; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* MFS03_UART_MODULE register bit fields */ +typedef struct stc_mfs03_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_uart_smr_field_t; + +typedef struct stc_mfs03_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs03_uart_scr_field_t; + +typedef struct stc_mfs03_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs03_uart_escr_field_t; + +typedef struct stc_mfs03_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_uart_ssr_field_t; + +typedef struct stc_mfs03_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_rdr_field_t; + +typedef struct stc_mfs03_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_tdr_field_t; + +typedef struct stc_mfs03_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_uart_bgr_field_t; + +typedef struct stc_mfs03_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_uart_bgr1_field_t; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* MFS03_CSIO_MODULE register bit fields */ +typedef struct stc_mfs03_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_csio_smr_field_t; + +typedef struct stc_mfs03_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_csio_scr_field_t; + +typedef struct stc_mfs03_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs03_csio_escr_field_t; + +typedef struct stc_mfs03_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs03_csio_ssr_field_t; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* MFS03_LIN_MODULE register bit fields */ +typedef struct stc_mfs03_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_lin_smr_field_t; + +typedef struct stc_mfs03_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_lin_scr_field_t; + +typedef struct stc_mfs03_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs03_lin_escr_field_t; + +typedef struct stc_mfs03_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_lin_ssr_field_t; + +typedef struct stc_mfs03_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_lin_bgr_field_t; + +typedef struct stc_mfs03_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_lin_bgr1_field_t; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* MFS03_I2C_MODULE register bit fields */ +typedef struct stc_mfs03_i2c_smr_field +{ + __IO uint8_t ITST0 : 1; + __IO uint8_t ITST1 : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs03_i2c_smr_field_t; + +typedef struct stc_mfs03_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs03_i2c_ibcr_field_t; + +typedef struct stc_mfs03_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs03_i2c_ibsr_field_t; + +typedef struct stc_mfs03_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs03_i2c_ssr_field_t; + +typedef struct stc_mfs03_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs03_i2c_isba_field_t; + +typedef struct stc_mfs03_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs03_i2c_ismk_field_t; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* MFS47_UART_MODULE register bit fields */ +typedef struct stc_mfs47_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_uart_smr_field_t; + +typedef struct stc_mfs47_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs47_uart_scr_field_t; + +typedef struct stc_mfs47_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs47_uart_escr_field_t; + +typedef struct stc_mfs47_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_uart_ssr_field_t; + +typedef struct stc_mfs47_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_rdr_field_t; + +typedef struct stc_mfs47_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_tdr_field_t; + +typedef struct stc_mfs47_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_uart_bgr_field_t; + +typedef struct stc_mfs47_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_uart_bgr1_field_t; + +typedef struct stc_mfs47_uart_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_uart_fcr_field_t; + +typedef struct stc_mfs47_uart_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_uart_fcr0_field_t; + +typedef struct stc_mfs47_uart_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_uart_fcr1_field_t; + +typedef struct stc_mfs47_uart_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_uart_fbyte_field_t; + +typedef struct stc_mfs47_uart_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_uart_fbyte1_field_t; + +typedef struct stc_mfs47_uart_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_uart_fbyte2_field_t; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* MFS47_CSIO_MODULE register bit fields */ +typedef struct stc_mfs47_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_csio_smr_field_t; + +typedef struct stc_mfs47_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_csio_scr_field_t; + +typedef struct stc_mfs47_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs47_csio_escr_field_t; + +typedef struct stc_mfs47_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs47_csio_ssr_field_t; + +typedef struct stc_mfs47_csio_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_csio_fcr_field_t; + +typedef struct stc_mfs47_csio_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_csio_fcr0_field_t; + +typedef struct stc_mfs47_csio_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_csio_fcr1_field_t; + +typedef struct stc_mfs47_csio_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_csio_fbyte_field_t; + +typedef struct stc_mfs47_csio_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_csio_fbyte1_field_t; + +typedef struct stc_mfs47_csio_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_csio_fbyte2_field_t; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* MFS47_LIN_MODULE register bit fields */ +typedef struct stc_mfs47_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_lin_smr_field_t; + +typedef struct stc_mfs47_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_lin_scr_field_t; + +typedef struct stc_mfs47_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs47_lin_escr_field_t; + +typedef struct stc_mfs47_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_lin_ssr_field_t; + +typedef struct stc_mfs47_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_lin_bgr_field_t; + +typedef struct stc_mfs47_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_lin_bgr1_field_t; + +typedef struct stc_mfs47_lin_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_lin_fcr_field_t; + +typedef struct stc_mfs47_lin_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_lin_fcr0_field_t; + +typedef struct stc_mfs47_lin_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_lin_fcr1_field_t; + +typedef struct stc_mfs47_lin_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_lin_fbyte_field_t; + +typedef struct stc_mfs47_lin_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_lin_fbyte1_field_t; + +typedef struct stc_mfs47_lin_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_lin_fbyte2_field_t; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* MFS47_I2C_MODULE register bit fields */ +typedef struct stc_mfs47_i2c_smr_field +{ + __IO uint8_t ITST0 : 1; + __IO uint8_t ITST1 : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD0 : 1; + __IO uint8_t MD1 : 1; + __IO uint8_t MD2 : 1; +} stc_mfs47_i2c_smr_field_t; + +typedef struct stc_mfs47_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs47_i2c_ibcr_field_t; + +typedef struct stc_mfs47_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs47_i2c_ibsr_field_t; + +typedef struct stc_mfs47_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs47_i2c_ssr_field_t; + +typedef struct stc_mfs47_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs47_i2c_isba_field_t; + +typedef struct stc_mfs47_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs47_i2c_ismk_field_t; + +typedef struct stc_mfs47_i2c_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_i2c_fcr_field_t; + +typedef struct stc_mfs47_i2c_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_i2c_fcr0_field_t; + +typedef struct stc_mfs47_i2c_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_i2c_fcr1_field_t; + +typedef struct stc_mfs47_i2c_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_i2c_fbyte_field_t; + +typedef struct stc_mfs47_i2c_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_i2c_fbyte1_field_t; + +typedef struct stc_mfs47_i2c_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_i2c_fbyte2_field_t; + +/****************************************************************************** + * MFS_NFC_MODULE + ******************************************************************************/ +/* MFS_NFC_MODULE register bit fields */ +typedef struct stc_mfs_nfc_i2cdnf_field +{ + __IO uint16_t I2CDNF00 : 1; + __IO uint16_t I2CDNF01 : 1; + __IO uint16_t I2CDNF10 : 1; + __IO uint16_t I2CDNF11 : 1; + __IO uint16_t I2CDNF20 : 1; + __IO uint16_t I2CDNF21 : 1; + __IO uint16_t I2CDNF30 : 1; + __IO uint16_t I2CDNF31 : 1; + __IO uint16_t I2CDNF40 : 1; + __IO uint16_t I2CDNF41 : 1; + __IO uint16_t I2CDNF50 : 1; + __IO uint16_t I2CDNF51 : 1; + __IO uint16_t I2CDNF60 : 1; + __IO uint16_t I2CDNF61 : 1; + __IO uint16_t I2CDNF70 : 1; + __IO uint16_t I2CDNF71 : 1; +} stc_mfs_nfc_i2cdnf_field_t; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC_MODULE register bit fields */ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT : 1; + __IO uint8_t CRC32 : 1; + __IO uint8_t LTLEND : 1; + __IO uint8_t LSBFST : 1; + __IO uint8_t CRCLTE : 1; + __IO uint8_t CRCLSF : 1; + __IO uint8_t FXOR : 1; +} stc_crc_crccr_field_t; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* WC_MODULE register bit fields */ +typedef struct stc_wc_wcrd_field +{ + __IO uint8_t CTR0 : 1; + __IO uint8_t CTR1 : 1; + __IO uint8_t CTR2 : 1; + __IO uint8_t CTR3 : 1; + __IO uint8_t CTR4 : 1; + __IO uint8_t CTR5 : 1; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + __IO uint8_t RLC0 : 1; + __IO uint8_t RLC1 : 1; + __IO uint8_t RLC2 : 1; + __IO uint8_t RLC3 : 1; + __IO uint8_t RLC4 : 1; + __IO uint8_t RLC5 : 1; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + __IO uint8_t WCIF : 1; + __IO uint8_t WCIE : 1; + __IO uint8_t CS0 : 1; + __IO uint8_t CS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t WCOP : 1; + __IO uint8_t WCEN : 1; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + __IO uint16_t SEL_IN : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t SEL_OUT : 1; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN : 1; + __IO uint8_t CLK_EN_R : 1; +} stc_wc_clk_en_field_t; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* EXBUS_MODULE register bit fields */ +typedef struct stc_exbus_mode0_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode0_field_t; + +typedef struct stc_exbus_mode1_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode1_field_t; + +typedef struct stc_exbus_mode2_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode2_field_t; + +typedef struct stc_exbus_mode3_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode3_field_t; + +typedef struct stc_exbus_mode4_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode4_field_t; + +typedef struct stc_exbus_mode5_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode5_field_t; + +typedef struct stc_exbus_mode6_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode6_field_t; + +typedef struct stc_exbus_mode7_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode7_field_t; + +typedef struct stc_exbus_tim0_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim0_field_t; + +typedef struct stc_exbus_tim1_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim1_field_t; + +typedef struct stc_exbus_tim2_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim2_field_t; + +typedef struct stc_exbus_tim3_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim3_field_t; + +typedef struct stc_exbus_tim4_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim4_field_t; + +typedef struct stc_exbus_tim5_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim5_field_t; + +typedef struct stc_exbus_tim6_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim6_field_t; + +typedef struct stc_exbus_tim7_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim7_field_t; + +typedef struct stc_exbus_area0_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area0_field_t; + +typedef struct stc_exbus_area1_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area1_field_t; + +typedef struct stc_exbus_area2_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area2_field_t; + +typedef struct stc_exbus_area3_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area3_field_t; + +typedef struct stc_exbus_area4_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area4_field_t; + +typedef struct stc_exbus_area5_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area5_field_t; + +typedef struct stc_exbus_area6_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area6_field_t; + +typedef struct stc_exbus_area7_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area7_field_t; + +typedef struct stc_exbus_atim0_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim0_field_t; + +typedef struct stc_exbus_atim1_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim1_field_t; + +typedef struct stc_exbus_atim2_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim2_field_t; + +typedef struct stc_exbus_atim3_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim3_field_t; + +typedef struct stc_exbus_atim4_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim4_field_t; + +typedef struct stc_exbus_atim5_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim5_field_t; + +typedef struct stc_exbus_atim6_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim6_field_t; + +typedef struct stc_exbus_atim7_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim7_field_t; + +typedef struct stc_exbus_dclkr_field +{ + __IO uint8_t MDIV0 : 1; + __IO uint8_t MDIV1 : 1; + __IO uint8_t MDIV2 : 1; + __IO uint8_t MDIV3 : 1; + __IO uint8_t MCLKON : 1; +} stc_exbus_dclkr_field_t; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB_MODULE register bit fields */ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST : 1; + __IO uint16_t URST : 1; + __IO uint16_t SOFIRE : 1; + __IO uint16_t DIRE : 1; + __IO uint16_t CNNIRE : 1; + __IO uint16_t CMPIRE : 1; + __IO uint16_t URIRE : 1; + __IO uint16_t RWKIRE : 1; + __IO uint16_t RETRY : 1; + __IO uint16_t CANCEL : 1; + __IO uint16_t SOFSTEP : 1; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hcnt0_field +{ + __IO uint8_t HOST : 1; + __IO uint8_t URST : 1; + __IO uint8_t SOFIRE : 1; + __IO uint8_t DIRE : 1; + __IO uint8_t CNNIRE : 1; + __IO uint8_t CMPIRE : 1; + __IO uint8_t URIRE : 1; + __IO uint8_t RWKIRE : 1; +} stc_usb_hcnt0_field_t; + +typedef struct stc_usb_hcnt1_field +{ + __IO uint8_t RETRY : 1; + __IO uint8_t CANCEL : 1; + __IO uint8_t SOFSTEP : 1; +} stc_usb_hcnt1_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ : 1; + __IO uint8_t DIRQ : 1; + __IO uint8_t CNNIRQ : 1; + __IO uint8_t CMPIRQ : 1; + __IO uint8_t URIRQ : 1; + __IO uint8_t RWKIRQ : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TCAN : 1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + __IO uint8_t HS0 : 1; + __IO uint8_t HS1 : 1; + __IO uint8_t STUFF : 1; + __IO uint8_t TGERR : 1; + __IO uint8_t CRC : 1; + __IO uint8_t TOUT : 1; + __IO uint8_t RERR : 1; + __IO uint8_t LSTOF : 1; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT : 1; + __IO uint8_t TMODE : 1; + __IO uint8_t SUSP : 1; + __IO uint8_t SOFBUSY : 1; + __IO uint8_t CLKSEL : 1; + __IO uint8_t ALIVE : 1; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + __IO uint8_t FRAMECOMP0 : 1; + __IO uint8_t FRAMECOMP1 : 1; + __IO uint8_t FRAMECOMP2 : 1; + __IO uint8_t FRAMECOMP3 : 1; + __IO uint8_t FRAMECOMP4 : 1; + __IO uint8_t FRAMECOMP5 : 1; + __IO uint8_t FRAMECOMP6 : 1; + __IO uint8_t FRAMECOMP7 : 1; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + __IO uint16_t RTIMER0 : 1; + __IO uint16_t RTIMER1 : 1; + __IO uint16_t RTIMER2 : 1; + __IO uint16_t RTIMER3 : 1; + __IO uint16_t RTIMER4 : 1; + __IO uint16_t RTIMER5 : 1; + __IO uint16_t RTIMER6 : 1; + __IO uint16_t RTIMER7 : 1; + __IO uint16_t RTIMER8 : 1; + __IO uint16_t RTIMER9 : 1; + __IO uint16_t RTIMER10 : 1; + __IO uint16_t RTIMER11 : 1; + __IO uint16_t RTIMER12 : 1; + __IO uint16_t RTIMER13 : 1; + __IO uint16_t RTIMER14 : 1; + __IO uint16_t RTIMER15 : 1; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer0_field +{ + __IO uint8_t RTIMER00 : 1; + __IO uint8_t RTIMER01 : 1; + __IO uint8_t RTIMER02 : 1; + __IO uint8_t RTIMER03 : 1; + __IO uint8_t RTIMER04 : 1; + __IO uint8_t RTIMER05 : 1; + __IO uint8_t RTIMER06 : 1; + __IO uint8_t RTIMER07 : 1; +} stc_usb_hrtimer0_field_t; + +typedef struct stc_usb_hrtimer1_field +{ + __IO uint8_t RTIMER10 : 1; + __IO uint8_t RTIMER11 : 1; + __IO uint8_t RTIMER12 : 1; + __IO uint8_t RTIMER13 : 1; + __IO uint8_t RTIMER14 : 1; + __IO uint8_t RTIMER15 : 1; + __IO uint8_t RTIMER16 : 1; + __IO uint8_t RTIMER17 : 1; +} stc_usb_hrtimer1_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + __IO uint8_t RTIMER20 : 1; + __IO uint8_t RTIMER21 : 1; + __IO uint8_t RTIMER22 : 1; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + __IO uint8_t ADDRESS0 : 1; + __IO uint8_t ADDRESS1 : 1; + __IO uint8_t ADDRESS2 : 1; + __IO uint8_t ADDRESS3 : 1; + __IO uint8_t ADDRESS4 : 1; + __IO uint8_t ADDRESS5 : 1; + __IO uint8_t ADDRESS6 : 1; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + __IO uint16_t EOF0 : 1; + __IO uint16_t EOF1 : 1; + __IO uint16_t EOF2 : 1; + __IO uint16_t EOF3 : 1; + __IO uint16_t EOF4 : 1; + __IO uint16_t EOF5 : 1; + __IO uint16_t EOF6 : 1; + __IO uint16_t EOF7 : 1; + __IO uint16_t EOF8 : 1; + __IO uint16_t EOF9 : 1; + __IO uint16_t EOF10 : 1; + __IO uint16_t EOF11 : 1; + __IO uint16_t EOF12 : 1; + __IO uint16_t EOF13 : 1; + __IO uint16_t EOF14 : 1; + __IO uint16_t EOF15 : 1; +} stc_usb_heof_field_t; + +typedef struct stc_usb_heof0_field +{ + __IO uint8_t EOF00 : 1; + __IO uint8_t EOF01 : 1; + __IO uint8_t EOF02 : 1; + __IO uint8_t EOF03 : 1; + __IO uint8_t EOF04 : 1; + __IO uint8_t EOF05 : 1; + __IO uint8_t EOF06 : 1; + __IO uint8_t EOF07 : 1; +} stc_usb_heof0_field_t; + +typedef struct stc_usb_heof1_field +{ + __IO uint8_t EOF10 : 1; + __IO uint8_t EOF11 : 1; + __IO uint8_t EOF12 : 1; + __IO uint8_t EOF13 : 1; + __IO uint8_t EOF14 : 1; + __IO uint8_t EOF15 : 1; +} stc_usb_heof1_field_t; + +typedef struct stc_usb_hframe_field +{ + __IO uint16_t FRAME0 : 1; + __IO uint16_t FRAME1 : 1; + __IO uint16_t FRAME2 : 1; + __IO uint16_t FRAME3 : 1; + __IO uint16_t FRAME4 : 1; + __IO uint16_t FRAME5 : 1; + __IO uint16_t FRAME6 : 1; + __IO uint16_t FRAME7 : 1; + __IO uint16_t FRAME8 : 1; + __IO uint16_t FRAME9 : 1; + __IO uint16_t FRAME10 : 1; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_hframe0_field +{ + __IO uint8_t FRAME00 : 1; + __IO uint8_t FRAME01 : 1; + __IO uint8_t FRAME02 : 1; + __IO uint8_t FRAME03 : 1; + __IO uint8_t FRAME04 : 1; + __IO uint8_t FRAME05 : 1; + __IO uint8_t FRAME06 : 1; + __IO uint8_t FRAME07 : 1; +} stc_usb_hframe0_field_t; + +typedef struct stc_usb_hframe1_field +{ + __IO uint8_t FRAME10 : 1; + __IO uint8_t FRAME11 : 1; + __IO uint8_t FRAME12 : 1; + __IO uint8_t FRAME13 : 1; +} stc_usb_hframe1_field_t; + +typedef struct stc_usb_htoken_field +{ + __IO uint8_t ENDPT0 : 1; + __IO uint8_t ENDPT1 : 1; + __IO uint8_t ENDPT2 : 1; + __IO uint8_t ENDPT3 : 1; + __IO uint8_t TKNEN0 : 1; + __IO uint8_t TKNEN1 : 1; + __IO uint8_t TKNEN2 : 1; + __IO uint8_t TGGL : 1; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC : 1; + __IO uint16_t RFBK : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t STALCLREN : 1; + __IO uint16_t USTP : 1; + __IO uint16_t HCONX : 1; + __IO uint16_t RESUM : 1; + __IO uint16_t RST : 1; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + __IO uint16_t PKS00 : 1; + __IO uint16_t PKS01 : 1; + __IO uint16_t PKS02 : 1; + __IO uint16_t PKS03 : 1; + __IO uint16_t PKS04 : 1; + __IO uint16_t PKS05 : 1; + __IO uint16_t PKS06 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + __IO uint16_t PKS10 : 1; + __IO uint16_t PKS11 : 1; + __IO uint16_t PKS12 : 1; + __IO uint16_t PKS13 : 1; + __IO uint16_t PKS14 : 1; + __IO uint16_t PKS15 : 1; + __IO uint16_t PKS16 : 1; + __IO uint16_t PKS17 : 1; + __IO uint16_t PKS18 : 1; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + __IO uint16_t PKS20 : 1; + __IO uint16_t PKS21 : 1; + __IO uint16_t PKS22 : 1; + __IO uint16_t PKS23 : 1; + __IO uint16_t PKS24 : 1; + __IO uint16_t PKS25 : 1; + __IO uint16_t PKS26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + __IO uint16_t PKS30 : 1; + __IO uint16_t PKS31 : 1; + __IO uint16_t PKS32 : 1; + __IO uint16_t PKS33 : 1; + __IO uint16_t PKS34 : 1; + __IO uint16_t PKS35 : 1; + __IO uint16_t PKS36 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + __IO uint16_t PKS40 : 1; + __IO uint16_t PKS41 : 1; + __IO uint16_t PKS42 : 1; + __IO uint16_t PKS43 : 1; + __IO uint16_t PKS44 : 1; + __IO uint16_t PKS45 : 1; + __IO uint16_t PKS46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + __IO uint16_t PKS50 : 1; + __IO uint16_t PKS51 : 1; + __IO uint16_t PKS52 : 1; + __IO uint16_t PKS53 : 1; + __IO uint16_t PKS54 : 1; + __IO uint16_t PKS55 : 1; + __IO uint16_t PKS56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + __IO uint16_t TMSP0 : 1; + __IO uint16_t TMSP1 : 1; + __IO uint16_t TMSP2 : 1; + __IO uint16_t TMSP3 : 1; + __IO uint16_t TMSP4 : 1; + __IO uint16_t TMSP5 : 1; + __IO uint16_t TMSP6 : 1; + __IO uint16_t TMSP7 : 1; + __IO uint16_t TMSP8 : 1; + __IO uint16_t TMSP9 : 1; + __IO uint16_t TMSP10 : 1; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF : 1; + __IO uint8_t SETP : 1; + __IO uint8_t WKUP : 1; + __IO uint8_t BRST : 1; + __IO uint8_t SOF : 1; + __IO uint8_t SUSP : 1; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE : 1; + __IO uint8_t CONFN : 1; + __IO uint8_t WKUPIE : 1; + __IO uint8_t BRSTIE : 1; + __IO uint8_t SOFIE : 1; + __IO uint8_t SUSPIE : 1; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + uint16_t RESERVED1 : 10; + __IO uint16_t DRQI : 1; + uint16_t RESERVED2 : 3; + __IO uint16_t DRQIIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + __IO uint16_t SIZE0 : 1; + __IO uint16_t SIZE1 : 1; + __IO uint16_t SIZE2 : 1; + __IO uint16_t SIZE3 : 1; + __IO uint16_t SIZE4 : 1; + __IO uint16_t SIZE5 : 1; + __IO uint16_t SIZE6 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQO : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQOIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + __IO uint16_t SIZE10 : 1; + __IO uint16_t SIZE11 : 1; + __IO uint16_t SIZE12 : 1; + __IO uint16_t SIZE13 : 1; + __IO uint16_t SIZE14 : 1; + __IO uint16_t SIZE15 : 1; + __IO uint16_t SIZE16 : 1; + __IO uint16_t SIZE17 : 1; + __IO uint16_t SIZE18 : 1; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + __IO uint16_t SIZE20 : 1; + __IO uint16_t SIZE21 : 1; + __IO uint16_t SIZE22 : 1; + __IO uint16_t SIZE23 : 1; + __IO uint16_t SIZE24 : 1; + __IO uint16_t SIZE25 : 1; + __IO uint16_t SIZE26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep4s_field +{ + __IO uint16_t SIZE40 : 1; + __IO uint16_t SIZE41 : 1; + __IO uint16_t SIZE42 : 1; + __IO uint16_t SIZE43 : 1; + __IO uint16_t SIZE44 : 1; + __IO uint16_t SIZE45 : 1; + __IO uint16_t SIZE46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + __IO uint16_t SIZE50 : 1; + __IO uint16_t SIZE51 : 1; + __IO uint16_t SIZE52 : 1; + __IO uint16_t SIZE53 : 1; + __IO uint16_t SIZE54 : 1; + __IO uint16_t SIZE55 : 1; + __IO uint16_t SIZE56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep5s_field_t; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMAC_MODULE register bit fields */ +typedef struct stc_dmac_dmacr_field +{ + uint32_t RESERVED1 : 24; + __IO uint32_t DH0 : 1; + __IO uint32_t DH1 : 1; + __IO uint32_t DH2 : 1; + __IO uint32_t DH3 : 1; + __IO uint32_t PR : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t DS : 1; + __IO uint32_t DE : 1; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb7_field_t; + +/****************************************************************************** + * ETHERNET_MAC_MODULE + ******************************************************************************/ +/* ETHERNET_MAC_MODULE register bit fields */ +typedef struct stc_ethernet_mac_mcr_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t DC : 1; + __IO uint32_t BL0 : 1; + __IO uint32_t BL1 : 1; + __IO uint32_t ACS : 1; + __IO uint32_t LUD : 1; + __IO uint32_t DR : 1; + __IO uint32_t IPC : 1; + __IO uint32_t DM : 1; + __IO uint32_t LM : 1; + __IO uint32_t DO : 1; + __IO uint32_t FES : 1; + __IO uint32_t PS : 1; + __IO uint32_t DCRS : 1; + __IO uint32_t IFG0 : 1; + __IO uint32_t IFG1 : 1; + __IO uint32_t IFG2 : 1; + __IO uint32_t JE : 1; + __IO uint32_t BE : 1; + __IO uint32_t JD : 1; + __IO uint32_t WD : 1; + __IO uint32_t TC : 1; + __IO uint32_t CST : 1; +} stc_ethernet_mac_mcr_field_t; + +typedef struct stc_ethernet_mac_mffr_field +{ + __IO uint32_t PR : 1; + __IO uint32_t HUC : 1; + __IO uint32_t HMC : 1; + __IO uint32_t DAIF : 1; + __IO uint32_t PM : 1; + __IO uint32_t DB : 1; + __IO uint32_t PCF0 : 1; + __IO uint32_t PCF1 : 1; + __IO uint32_t SAIF : 1; + __IO uint32_t SAF : 1; + __IO uint32_t HPF : 1; + uint32_t RESERVED1 :20; + __IO uint32_t RA : 1; +} stc_ethernet_mac_mffr_field_t; + +typedef struct stc_ethernet_mac_mhtrh_field +{ + __IO uint32_t HTH0 : 1; + __IO uint32_t HTH1 : 1; + __IO uint32_t HTH2 : 1; + __IO uint32_t HTH3 : 1; + __IO uint32_t HTH4 : 1; + __IO uint32_t HTH5 : 1; + __IO uint32_t HTH6 : 1; + __IO uint32_t HTH7 : 1; + __IO uint32_t HTH8 : 1; + __IO uint32_t HTH9 : 1; + __IO uint32_t HTH10 : 1; + __IO uint32_t HTH11 : 1; + __IO uint32_t HTH12 : 1; + __IO uint32_t HTH13 : 1; + __IO uint32_t HTH14 : 1; + __IO uint32_t HTH15 : 1; + __IO uint32_t HTH16 : 1; + __IO uint32_t HTH17 : 1; + __IO uint32_t HTH18 : 1; + __IO uint32_t HTH19 : 1; + __IO uint32_t HTH20 : 1; + __IO uint32_t HTH21 : 1; + __IO uint32_t HTH22 : 1; + __IO uint32_t HTH23 : 1; + __IO uint32_t HTH24 : 1; + __IO uint32_t HTH25 : 1; + __IO uint32_t HTH26 : 1; + __IO uint32_t HTH27 : 1; + __IO uint32_t HTH28 : 1; + __IO uint32_t HTH29 : 1; + __IO uint32_t HTH30 : 1; + __IO uint32_t HTH31 : 1; +} stc_ethernet_mac_mhtrh_field_t; + +typedef struct stc_ethernet_mac_mhtrl_field +{ + __IO uint32_t HTL0 : 1; + __IO uint32_t HTL1 : 1; + __IO uint32_t HTL2 : 1; + __IO uint32_t HTL3 : 1; + __IO uint32_t HTL4 : 1; + __IO uint32_t HTL5 : 1; + __IO uint32_t HTL6 : 1; + __IO uint32_t HTL7 : 1; + __IO uint32_t HTL8 : 1; + __IO uint32_t HTL9 : 1; + __IO uint32_t HTL10 : 1; + __IO uint32_t HTL11 : 1; + __IO uint32_t HTL12 : 1; + __IO uint32_t HTL13 : 1; + __IO uint32_t HTL14 : 1; + __IO uint32_t HTL15 : 1; + __IO uint32_t HTL16 : 1; + __IO uint32_t HTL17 : 1; + __IO uint32_t HTL18 : 1; + __IO uint32_t HTL19 : 1; + __IO uint32_t HTL20 : 1; + __IO uint32_t HTL21 : 1; + __IO uint32_t HTL22 : 1; + __IO uint32_t HTL23 : 1; + __IO uint32_t HTL24 : 1; + __IO uint32_t HTL25 : 1; + __IO uint32_t HTL26 : 1; + __IO uint32_t HTL27 : 1; + __IO uint32_t HTL28 : 1; + __IO uint32_t HTL29 : 1; + __IO uint32_t HTL30 : 1; + __IO uint32_t HTL31 : 1; +} stc_ethernet_mac_mhtrl_field_t; + +typedef struct stc_ethernet_mac_gar_field +{ + __IO uint32_t GB : 1; + __IO uint32_t GW : 1; + __IO uint32_t CR0 : 1; + __IO uint32_t CR1 : 1; + __IO uint32_t CR2 : 1; + __IO uint32_t CR3 : 1; + __IO uint32_t GR0 : 1; + __IO uint32_t GR1 : 1; + __IO uint32_t GR2 : 1; + __IO uint32_t GR3 : 1; + __IO uint32_t GR4 : 1; + __IO uint32_t PA0 : 1; + __IO uint32_t PA1 : 1; + __IO uint32_t PA2 : 1; + __IO uint32_t PA3 : 1; + __IO uint32_t PA4 : 1; +} stc_ethernet_mac_gar_field_t; + +typedef struct stc_ethernet_mac_gdr_field +{ + __IO uint32_t GD0 : 1; + __IO uint32_t GD1 : 1; + __IO uint32_t GD2 : 1; + __IO uint32_t GD3 : 1; + __IO uint32_t GD4 : 1; + __IO uint32_t GD5 : 1; + __IO uint32_t GD6 : 1; + __IO uint32_t GD7 : 1; + __IO uint32_t GD8 : 1; + __IO uint32_t GD9 : 1; + __IO uint32_t GD10 : 1; + __IO uint32_t GD11 : 1; + __IO uint32_t GD12 : 1; + __IO uint32_t GD13 : 1; + __IO uint32_t GD14 : 1; + __IO uint32_t GD15 : 1; +} stc_ethernet_mac_gdr_field_t; + +typedef struct stc_ethernet_mac_fcr_field +{ + __IO uint32_t FCB_BPA : 1; + __IO uint32_t TFE : 1; + __IO uint32_t RFE : 1; + __IO uint32_t UP : 1; + __IO uint32_t PLT0 : 1; + __IO uint32_t PLT1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t DZPQ : 1; + uint32_t RESERVED2 : 8; + __IO uint32_t PT0 : 1; + __IO uint32_t PT1 : 1; + __IO uint32_t PT2 : 1; + __IO uint32_t PT3 : 1; + __IO uint32_t PT4 : 1; + __IO uint32_t PT5 : 1; + __IO uint32_t PT6 : 1; + __IO uint32_t PT7 : 1; + __IO uint32_t PT8 : 1; + __IO uint32_t PT9 : 1; + __IO uint32_t PT10 : 1; + __IO uint32_t PT11 : 1; + __IO uint32_t PT12 : 1; + __IO uint32_t PT13 : 1; + __IO uint32_t PT14 : 1; + __IO uint32_t PT15 : 1; +} stc_ethernet_mac_fcr_field_t; + +typedef struct stc_ethernet_mac_vtr_field +{ + __IO uint32_t VL0 : 1; + __IO uint32_t VL1 : 1; + __IO uint32_t VL2 : 1; + __IO uint32_t VL3 : 1; + __IO uint32_t VL4 : 1; + __IO uint32_t VL5 : 1; + __IO uint32_t VL6 : 1; + __IO uint32_t VL7 : 1; + __IO uint32_t VL8 : 1; + __IO uint32_t VL9 : 1; + __IO uint32_t VL10 : 1; + __IO uint32_t VL11 : 1; + __IO uint32_t VL12 : 1; + __IO uint32_t VL13 : 1; + __IO uint32_t VL14 : 1; + __IO uint32_t VL15 : 1; + __IO uint32_t ETV : 1; +} stc_ethernet_mac_vtr_field_t; + +typedef struct stc_ethernet_mac_rwffr_field +{ + __IO uint32_t RWFFR0 : 1; + __IO uint32_t RWFFR1 : 1; + __IO uint32_t RWFFR2 : 1; + __IO uint32_t RWFFR3 : 1; + __IO uint32_t RWFFR4 : 1; + __IO uint32_t RWFFR5 : 1; + __IO uint32_t RWFFR6 : 1; + __IO uint32_t RWFFR7 : 1; + __IO uint32_t RWFFR8 : 1; + __IO uint32_t RWFFR9 : 1; + __IO uint32_t RWFFR10 : 1; + __IO uint32_t RWFFR11 : 1; + __IO uint32_t RWFFR12 : 1; + __IO uint32_t RWFFR13 : 1; + __IO uint32_t RWFFR14 : 1; + __IO uint32_t RWFFR15 : 1; + __IO uint32_t RWFFR16 : 1; + __IO uint32_t RWFFR17 : 1; + __IO uint32_t RWFFR18 : 1; + __IO uint32_t RWFFR19 : 1; + __IO uint32_t RWFFR20 : 1; + __IO uint32_t RWFFR21 : 1; + __IO uint32_t RWFFR22 : 1; + __IO uint32_t RWFFR23 : 1; + __IO uint32_t RWFFR24 : 1; + __IO uint32_t RWFFR25 : 1; + __IO uint32_t RWFFR26 : 1; + __IO uint32_t RWFFR27 : 1; + __IO uint32_t RWFFR28 : 1; + __IO uint32_t RWFFR29 : 1; + __IO uint32_t RWFFR30 : 1; + __IO uint32_t RWFFR31 : 1; +} stc_ethernet_mac_rwffr_field_t; + +typedef struct stc_ethernet_mac_pmtr_field +{ + __IO uint32_t PD : 1; + __IO uint32_t MPE : 1; + __IO uint32_t WFE : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t MPR : 1; + __IO uint32_t WPR : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t GU : 1; + uint32_t RESERVED3 :21; + __IO uint32_t RWFFRPR : 1; +} stc_ethernet_mac_pmtr_field_t; + +typedef struct stc_ethernet_mac_lpicsr_field +{ + __IO uint32_t TLPIEN : 1; + __IO uint32_t TLPIEX : 1; + __IO uint32_t RLPIEN : 1; + __IO uint32_t RLPIEX : 1; + uint32_t RESERVED1 : 4; + __IO uint32_t TLPIST : 1; + __IO uint32_t RLPIST : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t LPIEN : 1; + __IO uint32_t PLS : 1; + __IO uint32_t PLSEN : 1; + __IO uint32_t LPITXA : 1; +} stc_ethernet_mac_lpicsr_field_t; + +typedef struct stc_ethernet_mac_lpitcr_field +{ + __IO uint32_t TWT0 : 1; + __IO uint32_t TWT1 : 1; + __IO uint32_t TWT2 : 1; + __IO uint32_t TWT3 : 1; + __IO uint32_t TWT4 : 1; + __IO uint32_t TWT5 : 1; + __IO uint32_t TWT6 : 1; + __IO uint32_t TWT7 : 1; + __IO uint32_t TWT8 : 1; + __IO uint32_t TWT9 : 1; + __IO uint32_t TWT10 : 1; + __IO uint32_t TWT11 : 1; + __IO uint32_t TWT12 : 1; + __IO uint32_t TWT13 : 1; + __IO uint32_t TWT14 : 1; + __IO uint32_t TWT15 : 1; + __IO uint32_t LIT0 : 1; + __IO uint32_t LIT1 : 1; + __IO uint32_t LIT2 : 1; + __IO uint32_t LIT3 : 1; + __IO uint32_t LIT4 : 1; + __IO uint32_t LIT5 : 1; + __IO uint32_t LIT6 : 1; + __IO uint32_t LIT7 : 1; + __IO uint32_t LIT8 : 1; + __IO uint32_t LIT9 : 1; +} stc_ethernet_mac_lpitcr_field_t; + +typedef struct stc_ethernet_mac_isr_field +{ + __IO uint32_t RGIS : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t PIS : 1; + __IO uint32_t MIS : 1; + __IO uint32_t RIS : 1; + __IO uint32_t TIS : 1; + __IO uint32_t COIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TSIS : 1; + __IO uint32_t LPIIS : 1; +} stc_ethernet_mac_isr_field_t; + +typedef struct stc_ethernet_mac_imr_field +{ + __IO uint32_t RGIM : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t PIM : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t TSIM : 1; + __IO uint32_t LPIIM : 1; +} stc_ethernet_mac_imr_field_t; + +typedef struct stc_ethernet_mac_mar0h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 :15; + __IO uint32_t MO : 1; +} stc_ethernet_mac_mar0h_field_t; + +typedef struct stc_ethernet_mac_mar0l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar0l_field_t; + +typedef struct stc_ethernet_mac_mar1h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar1h_field_t; + +typedef struct stc_ethernet_mac_mar1l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar1l_field_t; + +typedef struct stc_ethernet_mac_mar2h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar2h_field_t; + +typedef struct stc_ethernet_mac_mar2l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar2l_field_t; + +typedef struct stc_ethernet_mac_mar3h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar3h_field_t; + +typedef struct stc_ethernet_mac_mar3l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar3l_field_t; + +typedef struct stc_ethernet_mac_mar4h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar4h_field_t; + +typedef struct stc_ethernet_mac_mar4l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar4l_field_t; + +typedef struct stc_ethernet_mac_mar5h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar5h_field_t; + +typedef struct stc_ethernet_mac_mar5l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar5l_field_t; + +typedef struct stc_ethernet_mac_mar6h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar6h_field_t; + +typedef struct stc_ethernet_mac_mar6l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar6l_field_t; + +typedef struct stc_ethernet_mac_mar7h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar7h_field_t; + +typedef struct stc_ethernet_mac_mar7l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar7l_field_t; + +typedef struct stc_ethernet_mac_mar8h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar8h_field_t; + +typedef struct stc_ethernet_mac_mar8l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar8l_field_t; + +typedef struct stc_ethernet_mac_mar9h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar9h_field_t; + +typedef struct stc_ethernet_mac_mar9l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar9l_field_t; + +typedef struct stc_ethernet_mac_mar10h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar10h_field_t; + +typedef struct stc_ethernet_mac_mar10l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar10l_field_t; + +typedef struct stc_ethernet_mac_mar11h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar11h_field_t; + +typedef struct stc_ethernet_mac_mar11l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar11l_field_t; + +typedef struct stc_ethernet_mac_mar12h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar12h_field_t; + +typedef struct stc_ethernet_mac_mar12l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar12l_field_t; + +typedef struct stc_ethernet_mac_mar13h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar13h_field_t; + +typedef struct stc_ethernet_mac_mar13l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar13l_field_t; + +typedef struct stc_ethernet_mac_mar14h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar14h_field_t; + +typedef struct stc_ethernet_mac_mar14l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar14l_field_t; + +typedef struct stc_ethernet_mac_mar15h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar15h_field_t; + +typedef struct stc_ethernet_mac_mar15l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar15l_field_t; + +typedef struct stc_ethernet_mac_rgsr_field +{ + __IO uint32_t LM : 1; + __IO uint32_t LSP0 : 1; + __IO uint32_t LSP1 : 1; + __IO uint32_t LS : 1; +} stc_ethernet_mac_rgsr_field_t; + +typedef struct stc_ethernet_mac_tscr_field +{ + __IO uint32_t TSE : 1; + __IO uint32_t TFCU : 1; + __IO uint32_t TSI : 1; + __IO uint32_t TSU : 1; + __IO uint32_t TITE : 1; + __IO uint32_t TARU : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t TSEA : 1; + __IO uint32_t TSDB : 1; + __IO uint32_t TSV2E : 1; + __IO uint32_t TETSP : 1; + __IO uint32_t TSIP6E : 1; + __IO uint32_t TSIP4E : 1; + __IO uint32_t TETSEM : 1; + __IO uint32_t TSMRM : 1; + __IO uint32_t TSPS0 : 1; + __IO uint32_t TSPS1 : 1; + __IO uint32_t TSENMF : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t ATSFC : 1; +} stc_ethernet_mac_tscr_field_t; + +typedef struct stc_ethernet_mac_ssir_field +{ + __IO uint32_t SSINC0 : 1; + __IO uint32_t SSINC1 : 1; + __IO uint32_t SSINC2 : 1; + __IO uint32_t SSINC3 : 1; + __IO uint32_t SSINC4 : 1; + __IO uint32_t SSINC5 : 1; + __IO uint32_t SSINC6 : 1; + __IO uint32_t SSINC7 : 1; +} stc_ethernet_mac_ssir_field_t; + +typedef struct stc_ethernet_mac_stsr_field +{ + __IO uint32_t TSS0 : 1; + __IO uint32_t TSS1 : 1; + __IO uint32_t TSS2 : 1; + __IO uint32_t TSS3 : 1; + __IO uint32_t TSS4 : 1; + __IO uint32_t TSS5 : 1; + __IO uint32_t TSS6 : 1; + __IO uint32_t TSS7 : 1; + __IO uint32_t TSS8 : 1; + __IO uint32_t TSS9 : 1; + __IO uint32_t TSS10 : 1; + __IO uint32_t TSS11 : 1; + __IO uint32_t TSS12 : 1; + __IO uint32_t TSS13 : 1; + __IO uint32_t TSS14 : 1; + __IO uint32_t TSS15 : 1; + __IO uint32_t TSS16 : 1; + __IO uint32_t TSS17 : 1; + __IO uint32_t TSS18 : 1; + __IO uint32_t TSS19 : 1; + __IO uint32_t TSS20 : 1; + __IO uint32_t TSS21 : 1; + __IO uint32_t TSS22 : 1; + __IO uint32_t TSS23 : 1; + __IO uint32_t TSS24 : 1; + __IO uint32_t TSS25 : 1; + __IO uint32_t TSS26 : 1; + __IO uint32_t TSS27 : 1; + __IO uint32_t TSS28 : 1; + __IO uint32_t TSS29 : 1; + __IO uint32_t TSS30 : 1; + __IO uint32_t TSS31 : 1; +} stc_ethernet_mac_stsr_field_t; + +typedef struct stc_ethernet_mac_stnr_field +{ + __IO uint32_t TSSS0 : 1; + __IO uint32_t TSSS1 : 1; + __IO uint32_t TSSS2 : 1; + __IO uint32_t TSSS3 : 1; + __IO uint32_t TSSS4 : 1; + __IO uint32_t TSSS5 : 1; + __IO uint32_t TSSS6 : 1; + __IO uint32_t TSSS7 : 1; + __IO uint32_t TSSS8 : 1; + __IO uint32_t TSSS9 : 1; + __IO uint32_t TSSS10 : 1; + __IO uint32_t TSSS11 : 1; + __IO uint32_t TSSS12 : 1; + __IO uint32_t TSSS13 : 1; + __IO uint32_t TSSS14 : 1; + __IO uint32_t TSSS15 : 1; + __IO uint32_t TSSS16 : 1; + __IO uint32_t TSSS17 : 1; + __IO uint32_t TSSS18 : 1; + __IO uint32_t TSSS19 : 1; + __IO uint32_t TSSS20 : 1; + __IO uint32_t TSSS21 : 1; + __IO uint32_t TSSS22 : 1; + __IO uint32_t TSSS23 : 1; + __IO uint32_t TSSS24 : 1; + __IO uint32_t TSSS25 : 1; + __IO uint32_t TSSS26 : 1; + __IO uint32_t TSSS27 : 1; + __IO uint32_t TSSS28 : 1; + __IO uint32_t TSSS29 : 1; + __IO uint32_t TSSS30 : 1; +} stc_ethernet_mac_stnr_field_t; + +typedef struct stc_ethernet_mac_stsur_field +{ + __IO uint32_t TSS0 : 1; + __IO uint32_t TSS1 : 1; + __IO uint32_t TSS2 : 1; + __IO uint32_t TSS3 : 1; + __IO uint32_t TSS4 : 1; + __IO uint32_t TSS5 : 1; + __IO uint32_t TSS6 : 1; + __IO uint32_t TSS7 : 1; + __IO uint32_t TSS8 : 1; + __IO uint32_t TSS9 : 1; + __IO uint32_t TSS10 : 1; + __IO uint32_t TSS11 : 1; + __IO uint32_t TSS12 : 1; + __IO uint32_t TSS13 : 1; + __IO uint32_t TSS14 : 1; + __IO uint32_t TSS15 : 1; + __IO uint32_t TSS16 : 1; + __IO uint32_t TSS17 : 1; + __IO uint32_t TSS18 : 1; + __IO uint32_t TSS19 : 1; + __IO uint32_t TSS20 : 1; + __IO uint32_t TSS21 : 1; + __IO uint32_t TSS22 : 1; + __IO uint32_t TSS23 : 1; + __IO uint32_t TSS24 : 1; + __IO uint32_t TSS25 : 1; + __IO uint32_t TSS26 : 1; + __IO uint32_t TSS27 : 1; + __IO uint32_t TSS28 : 1; + __IO uint32_t TSS29 : 1; + __IO uint32_t TSS30 : 1; + __IO uint32_t TSS31 : 1; +} stc_ethernet_mac_stsur_field_t; + +typedef struct stc_ethernet_mac_stnur_field +{ + __IO uint32_t TSSS0 : 1; + __IO uint32_t TSSS1 : 1; + __IO uint32_t TSSS2 : 1; + __IO uint32_t TSSS3 : 1; + __IO uint32_t TSSS4 : 1; + __IO uint32_t TSSS5 : 1; + __IO uint32_t TSSS6 : 1; + __IO uint32_t TSSS7 : 1; + __IO uint32_t TSSS8 : 1; + __IO uint32_t TSSS9 : 1; + __IO uint32_t TSSS10 : 1; + __IO uint32_t TSSS11 : 1; + __IO uint32_t TSSS12 : 1; + __IO uint32_t TSSS13 : 1; + __IO uint32_t TSSS14 : 1; + __IO uint32_t TSSS15 : 1; + __IO uint32_t TSSS16 : 1; + __IO uint32_t TSSS17 : 1; + __IO uint32_t TSSS18 : 1; + __IO uint32_t TSSS19 : 1; + __IO uint32_t TSSS20 : 1; + __IO uint32_t TSSS21 : 1; + __IO uint32_t TSSS22 : 1; + __IO uint32_t TSSS23 : 1; + __IO uint32_t TSSS24 : 1; + __IO uint32_t TSSS25 : 1; + __IO uint32_t TSSS26 : 1; + __IO uint32_t TSSS27 : 1; + __IO uint32_t TSSS28 : 1; + __IO uint32_t TSSS29 : 1; + __IO uint32_t TSSS30 : 1; + __IO uint32_t ADDSUB : 1; +} stc_ethernet_mac_stnur_field_t; + +typedef struct stc_ethernet_mac_tsar_field +{ + __IO uint32_t TSAR0 : 1; + __IO uint32_t TSAR1 : 1; + __IO uint32_t TSAR2 : 1; + __IO uint32_t TSAR3 : 1; + __IO uint32_t TSAR4 : 1; + __IO uint32_t TSAR5 : 1; + __IO uint32_t TSAR6 : 1; + __IO uint32_t TSAR7 : 1; + __IO uint32_t TSAR8 : 1; + __IO uint32_t TSAR9 : 1; + __IO uint32_t TSAR10 : 1; + __IO uint32_t TSAR11 : 1; + __IO uint32_t TSAR12 : 1; + __IO uint32_t TSAR13 : 1; + __IO uint32_t TSAR14 : 1; + __IO uint32_t TSAR15 : 1; + __IO uint32_t TSAR16 : 1; + __IO uint32_t TSAR17 : 1; + __IO uint32_t TSAR18 : 1; + __IO uint32_t TSAR19 : 1; + __IO uint32_t TSAR20 : 1; + __IO uint32_t TSAR21 : 1; + __IO uint32_t TSAR22 : 1; + __IO uint32_t TSAR23 : 1; + __IO uint32_t TSAR24 : 1; + __IO uint32_t TSAR25 : 1; + __IO uint32_t TSAR26 : 1; + __IO uint32_t TSAR27 : 1; + __IO uint32_t TSAR28 : 1; + __IO uint32_t TSAR29 : 1; + __IO uint32_t TSAR30 : 1; + __IO uint32_t TSAR31 : 1; +} stc_ethernet_mac_tsar_field_t; + +typedef struct stc_ethernet_mac_ttsr_field +{ + __IO uint32_t TSTR0 : 1; + __IO uint32_t TSTR1 : 1; + __IO uint32_t TSTR2 : 1; + __IO uint32_t TSTR3 : 1; + __IO uint32_t TSTR4 : 1; + __IO uint32_t TSTR5 : 1; + __IO uint32_t TSTR6 : 1; + __IO uint32_t TSTR7 : 1; + __IO uint32_t TSTR8 : 1; + __IO uint32_t TSTR9 : 1; + __IO uint32_t TSTR10 : 1; + __IO uint32_t TSTR11 : 1; + __IO uint32_t TSTR12 : 1; + __IO uint32_t TSTR13 : 1; + __IO uint32_t TSTR14 : 1; + __IO uint32_t TSTR15 : 1; + __IO uint32_t TSTR16 : 1; + __IO uint32_t TSTR17 : 1; + __IO uint32_t TSTR18 : 1; + __IO uint32_t TSTR19 : 1; + __IO uint32_t TSTR20 : 1; + __IO uint32_t TSTR21 : 1; + __IO uint32_t TSTR22 : 1; + __IO uint32_t TSTR23 : 1; + __IO uint32_t TSTR24 : 1; + __IO uint32_t TSTR25 : 1; + __IO uint32_t TSTR26 : 1; + __IO uint32_t TSTR27 : 1; + __IO uint32_t TSTR28 : 1; + __IO uint32_t TSTR29 : 1; + __IO uint32_t TSTR30 : 1; + __IO uint32_t TSTR31 : 1; +} stc_ethernet_mac_ttsr_field_t; + +typedef struct stc_ethernet_mac_ttnr_field +{ + __IO uint32_t TSTR0 : 1; + __IO uint32_t TSTR1 : 1; + __IO uint32_t TSTR2 : 1; + __IO uint32_t TSTR3 : 1; + __IO uint32_t TSTR4 : 1; + __IO uint32_t TSTR5 : 1; + __IO uint32_t TSTR6 : 1; + __IO uint32_t TSTR7 : 1; + __IO uint32_t TSTR8 : 1; + __IO uint32_t TSTR9 : 1; + __IO uint32_t TSTR10 : 1; + __IO uint32_t TSTR11 : 1; + __IO uint32_t TSTR12 : 1; + __IO uint32_t TSTR13 : 1; + __IO uint32_t TSTR14 : 1; + __IO uint32_t TSTR15 : 1; + __IO uint32_t TSTR16 : 1; + __IO uint32_t TSTR17 : 1; + __IO uint32_t TSTR18 : 1; + __IO uint32_t TSTR19 : 1; + __IO uint32_t TSTR20 : 1; + __IO uint32_t TSTR21 : 1; + __IO uint32_t TSTR22 : 1; + __IO uint32_t TSTR23 : 1; + __IO uint32_t TSTR24 : 1; + __IO uint32_t TSTR25 : 1; + __IO uint32_t TSTR26 : 1; + __IO uint32_t TSTR27 : 1; + __IO uint32_t TSTR28 : 1; + __IO uint32_t TSTR29 : 1; + __IO uint32_t TSTR30 : 1; +} stc_ethernet_mac_ttnr_field_t; + +typedef struct stc_ethernet_mac_sthwsr_field +{ + __IO uint32_t TSHWR0 : 1; + __IO uint32_t TSHWR1 : 1; + __IO uint32_t TSHWR2 : 1; + __IO uint32_t TSHWR3 : 1; + __IO uint32_t TSHWR4 : 1; + __IO uint32_t TSHWR5 : 1; + __IO uint32_t TSHWR6 : 1; + __IO uint32_t TSHWR7 : 1; + __IO uint32_t TSHWR8 : 1; + __IO uint32_t TSHWR9 : 1; + __IO uint32_t TSHWR10 : 1; + __IO uint32_t TSHWR11 : 1; + __IO uint32_t TSHWR12 : 1; + __IO uint32_t TSHWR13 : 1; + __IO uint32_t TSHWR14 : 1; + __IO uint32_t TSHWR15 : 1; +} stc_ethernet_mac_sthwsr_field_t; + +typedef struct stc_ethernet_mac_tsr_field +{ + __IO uint32_t TSSOVF : 1; + __IO uint32_t TSTART : 1; + __IO uint32_t ATSTS : 1; + __IO uint32_t TRGTER : 1; + uint32_t RESERVED1 :20; + __IO uint32_t ATSSTM : 1; + __IO uint32_t ATSNS0 : 1; + __IO uint32_t ATSNS1 : 1; + __IO uint32_t ATSNS2 : 1; +} stc_ethernet_mac_tsr_field_t; + +typedef struct stc_ethernet_mac_ppscr_field +{ + __IO uint32_t PPSCTRL0 : 1; + __IO uint32_t PPSCTRL1 : 1; + __IO uint32_t PPSCTRL2 : 1; + __IO uint32_t PPSCTRL3 : 1; +} stc_ethernet_mac_ppscr_field_t; + +typedef struct stc_ethernet_mac_atnr_field +{ + __IO uint32_t ATN0 : 1; + __IO uint32_t ATN1 : 1; + __IO uint32_t ATN2 : 1; + __IO uint32_t ATN3 : 1; + __IO uint32_t ATN4 : 1; + __IO uint32_t ATN5 : 1; + __IO uint32_t ATN6 : 1; + __IO uint32_t ATN7 : 1; + __IO uint32_t ATN8 : 1; + __IO uint32_t ATN9 : 1; + __IO uint32_t ATN10 : 1; + __IO uint32_t ATN11 : 1; + __IO uint32_t ATN12 : 1; + __IO uint32_t ATN13 : 1; + __IO uint32_t ATN14 : 1; + __IO uint32_t ATN15 : 1; + __IO uint32_t ATN16 : 1; + __IO uint32_t ATN17 : 1; + __IO uint32_t ATN18 : 1; + __IO uint32_t ATN19 : 1; + __IO uint32_t ATN20 : 1; + __IO uint32_t ATN21 : 1; + __IO uint32_t ATN22 : 1; + __IO uint32_t ATN23 : 1; + __IO uint32_t ATN24 : 1; + __IO uint32_t ATN25 : 1; + __IO uint32_t ATN26 : 1; + __IO uint32_t ATN27 : 1; + __IO uint32_t ATN28 : 1; + __IO uint32_t ATN29 : 1; + __IO uint32_t ATN30 : 1; +} stc_ethernet_mac_atnr_field_t; + +typedef struct stc_ethernet_mac_atsr_field +{ + __IO uint32_t ATS0 : 1; + __IO uint32_t ATS1 : 1; + __IO uint32_t ATS2 : 1; + __IO uint32_t ATS3 : 1; + __IO uint32_t ATS4 : 1; + __IO uint32_t ATS5 : 1; + __IO uint32_t ATS6 : 1; + __IO uint32_t ATS7 : 1; + __IO uint32_t ATS8 : 1; + __IO uint32_t ATS9 : 1; + __IO uint32_t ATS10 : 1; + __IO uint32_t ATS11 : 1; + __IO uint32_t ATS12 : 1; + __IO uint32_t ATS13 : 1; + __IO uint32_t ATS14 : 1; + __IO uint32_t ATS15 : 1; + __IO uint32_t ATS16 : 1; + __IO uint32_t ATS17 : 1; + __IO uint32_t ATS18 : 1; + __IO uint32_t ATS19 : 1; + __IO uint32_t ATS20 : 1; + __IO uint32_t ATS21 : 1; + __IO uint32_t ATS22 : 1; + __IO uint32_t ATS23 : 1; + __IO uint32_t ATS24 : 1; + __IO uint32_t ATS25 : 1; + __IO uint32_t ATS26 : 1; + __IO uint32_t ATS27 : 1; + __IO uint32_t ATS28 : 1; + __IO uint32_t ATS29 : 1; + __IO uint32_t ATS30 : 1; + __IO uint32_t ATS31 : 1; +} stc_ethernet_mac_atsr_field_t; + +typedef struct stc_ethernet_mac_mar16h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar16h_field_t; + +typedef struct stc_ethernet_mac_mar16l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar16l_field_t; + +typedef struct stc_ethernet_mac_mar17h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar17h_field_t; + +typedef struct stc_ethernet_mac_mar17l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar17l_field_t; + +typedef struct stc_ethernet_mac_mar18h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar18h_field_t; + +typedef struct stc_ethernet_mac_mar18l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar18l_field_t; + +typedef struct stc_ethernet_mac_mar19h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar19h_field_t; + +typedef struct stc_ethernet_mac_mar19l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar19l_field_t; + +typedef struct stc_ethernet_mac_mar20h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar20h_field_t; + +typedef struct stc_ethernet_mac_mar20l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar20l_field_t; + +typedef struct stc_ethernet_mac_mar21h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar21h_field_t; + +typedef struct stc_ethernet_mac_mar21l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar21l_field_t; + +typedef struct stc_ethernet_mac_mar22h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar22h_field_t; + +typedef struct stc_ethernet_mac_mar22l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar22l_field_t; + +typedef struct stc_ethernet_mac_mar23h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar23h_field_t; + +typedef struct stc_ethernet_mac_mar23l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar23l_field_t; + +typedef struct stc_ethernet_mac_mar24h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar24h_field_t; + +typedef struct stc_ethernet_mac_mar24l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar24l_field_t; + +typedef struct stc_ethernet_mac_mar25h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar25h_field_t; + +typedef struct stc_ethernet_mac_mar25l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar25l_field_t; + +typedef struct stc_ethernet_mac_mar26h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar26h_field_t; + +typedef struct stc_ethernet_mac_mar26l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar26l_field_t; + +typedef struct stc_ethernet_mac_mar27h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar27h_field_t; + +typedef struct stc_ethernet_mac_mar27l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar27l_field_t; + +typedef struct stc_ethernet_mac_mar28h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar28h_field_t; + +typedef struct stc_ethernet_mac_mar28l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar28l_field_t; + +typedef struct stc_ethernet_mac_mar29h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar29h_field_t; + +typedef struct stc_ethernet_mac_mar29l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar29l_field_t; + +typedef struct stc_ethernet_mac_mar30h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar30h_field_t; + +typedef struct stc_ethernet_mac_mar30l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar30l_field_t; + +typedef struct stc_ethernet_mac_mar31h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar31h_field_t; + +typedef struct stc_ethernet_mac_mar31l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar31l_field_t; + +typedef struct stc_ethernet_mac_bmr_field +{ + __IO uint32_t SWR : 1; + __IO uint32_t DA : 1; + __IO uint32_t DSL0 : 1; + __IO uint32_t DSL1 : 1; + __IO uint32_t DSL2 : 1; + __IO uint32_t DSL3 : 1; + __IO uint32_t DSL4 : 1; + __IO uint32_t ATDS : 1; + __IO uint32_t PBL0 : 1; + __IO uint32_t PBL1 : 1; + __IO uint32_t PBL2 : 1; + __IO uint32_t PBL3 : 1; + __IO uint32_t PBL4 : 1; + __IO uint32_t PBL5 : 1; + __IO uint32_t PR0 : 1; + __IO uint32_t PR1 : 1; + __IO uint32_t FB : 1; + __IO uint32_t RPBL0 : 1; + __IO uint32_t RPBL1 : 1; + __IO uint32_t RPBL2 : 1; + __IO uint32_t RPBL3 : 1; + __IO uint32_t RPBL4 : 1; + __IO uint32_t RPBL5 : 1; + __IO uint32_t USP : 1; + __IO uint32_t _8XPBL : 1; + __IO uint32_t AAL : 1; + __IO uint32_t MB : 1; + __IO uint32_t TXPR : 1; +} stc_ethernet_mac_bmr_field_t; + +typedef struct stc_ethernet_mac_tpdr_field +{ + __IO uint32_t TPD0 : 1; + __IO uint32_t TPD1 : 1; + __IO uint32_t TPD2 : 1; + __IO uint32_t TPD3 : 1; + __IO uint32_t TPD4 : 1; + __IO uint32_t TPD5 : 1; + __IO uint32_t TPD6 : 1; + __IO uint32_t TPD7 : 1; + __IO uint32_t TPD8 : 1; + __IO uint32_t TPD9 : 1; + __IO uint32_t TPD10 : 1; + __IO uint32_t TPD11 : 1; + __IO uint32_t TPD12 : 1; + __IO uint32_t TPD13 : 1; + __IO uint32_t TPD14 : 1; + __IO uint32_t TPD15 : 1; + __IO uint32_t TPD16 : 1; + __IO uint32_t TPD17 : 1; + __IO uint32_t TPD18 : 1; + __IO uint32_t TPD19 : 1; + __IO uint32_t TPD20 : 1; + __IO uint32_t TPD21 : 1; + __IO uint32_t TPD22 : 1; + __IO uint32_t TPD23 : 1; + __IO uint32_t TPD24 : 1; + __IO uint32_t TPD25 : 1; + __IO uint32_t TPD26 : 1; + __IO uint32_t TPD27 : 1; + __IO uint32_t TPD28 : 1; + __IO uint32_t TPD29 : 1; + __IO uint32_t TPD30 : 1; + __IO uint32_t TPD31 : 1; +} stc_ethernet_mac_tpdr_field_t; + +typedef struct stc_ethernet_mac_rpdr_field +{ + __IO uint32_t RPD0 : 1; + __IO uint32_t RPD1 : 1; + __IO uint32_t RPD2 : 1; + __IO uint32_t RPD3 : 1; + __IO uint32_t RPD4 : 1; + __IO uint32_t RPD5 : 1; + __IO uint32_t RPD6 : 1; + __IO uint32_t RPD7 : 1; + __IO uint32_t RPD8 : 1; + __IO uint32_t RPD9 : 1; + __IO uint32_t RPD10 : 1; + __IO uint32_t RPD11 : 1; + __IO uint32_t RPD12 : 1; + __IO uint32_t RPD13 : 1; + __IO uint32_t RPD14 : 1; + __IO uint32_t RPD15 : 1; + __IO uint32_t RPD16 : 1; + __IO uint32_t RPD17 : 1; + __IO uint32_t RPD18 : 1; + __IO uint32_t RPD19 : 1; + __IO uint32_t RPD20 : 1; + __IO uint32_t RPD21 : 1; + __IO uint32_t RPD22 : 1; + __IO uint32_t RPD23 : 1; + __IO uint32_t RPD24 : 1; + __IO uint32_t RPD25 : 1; + __IO uint32_t RPD26 : 1; + __IO uint32_t RPD27 : 1; + __IO uint32_t RPD28 : 1; + __IO uint32_t RPD29 : 1; + __IO uint32_t RPD30 : 1; + __IO uint32_t RPD31 : 1; +} stc_ethernet_mac_rpdr_field_t; + +typedef struct stc_ethernet_mac_rdlar_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t SRL2 : 1; + __IO uint32_t SRL3 : 1; + __IO uint32_t SRL4 : 1; + __IO uint32_t SRL5 : 1; + __IO uint32_t SRL6 : 1; + __IO uint32_t SRL7 : 1; + __IO uint32_t SRL8 : 1; + __IO uint32_t SRL9 : 1; + __IO uint32_t SRL10 : 1; + __IO uint32_t SRL11 : 1; + __IO uint32_t SRL12 : 1; + __IO uint32_t SRL13 : 1; + __IO uint32_t SRL14 : 1; + __IO uint32_t SRL15 : 1; + __IO uint32_t SRL16 : 1; + __IO uint32_t SRL17 : 1; + __IO uint32_t SRL18 : 1; + __IO uint32_t SRL19 : 1; + __IO uint32_t SRL20 : 1; + __IO uint32_t SRL21 : 1; + __IO uint32_t SRL22 : 1; + __IO uint32_t SRL23 : 1; + __IO uint32_t SRL24 : 1; + __IO uint32_t SRL25 : 1; + __IO uint32_t SRL26 : 1; + __IO uint32_t SRL27 : 1; + __IO uint32_t SRL28 : 1; + __IO uint32_t SRL29 : 1; + __IO uint32_t SRL30 : 1; + __IO uint32_t SRL31 : 1; +} stc_ethernet_mac_rdlar_field_t; + +typedef struct stc_ethernet_mac_tdlar_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t STL2 : 1; + __IO uint32_t STL3 : 1; + __IO uint32_t STL4 : 1; + __IO uint32_t STL5 : 1; + __IO uint32_t STL6 : 1; + __IO uint32_t STL7 : 1; + __IO uint32_t STL8 : 1; + __IO uint32_t STL9 : 1; + __IO uint32_t STL10 : 1; + __IO uint32_t STL11 : 1; + __IO uint32_t STL12 : 1; + __IO uint32_t STL13 : 1; + __IO uint32_t STL14 : 1; + __IO uint32_t STL15 : 1; + __IO uint32_t STL16 : 1; + __IO uint32_t STL17 : 1; + __IO uint32_t STL18 : 1; + __IO uint32_t STL19 : 1; + __IO uint32_t STL20 : 1; + __IO uint32_t STL21 : 1; + __IO uint32_t STL22 : 1; + __IO uint32_t STL23 : 1; + __IO uint32_t STL24 : 1; + __IO uint32_t STL25 : 1; + __IO uint32_t STL26 : 1; + __IO uint32_t STL27 : 1; + __IO uint32_t STL28 : 1; + __IO uint32_t STL29 : 1; + __IO uint32_t STL30 : 1; + __IO uint32_t STL31 : 1; +} stc_ethernet_mac_tdlar_field_t; + +typedef struct stc_ethernet_mac_sr_field +{ + __IO uint32_t TI : 1; + __IO uint32_t TPS : 1; + __IO uint32_t TU : 1; + __IO uint32_t TJT : 1; + __IO uint32_t OVF : 1; + __IO uint32_t UNF : 1; + __IO uint32_t RI : 1; + __IO uint32_t RU : 1; + __IO uint32_t RPS : 1; + __IO uint32_t RWT : 1; + __IO uint32_t ETI : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t FBI : 1; + __IO uint32_t ERI : 1; + __IO uint32_t AIS : 1; + __IO uint32_t NIS : 1; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + __IO uint32_t TS0 : 1; + __IO uint32_t TS1 : 1; + __IO uint32_t TS2 : 1; + __IO uint32_t EB0 : 1; + __IO uint32_t EB1 : 1; + __IO uint32_t EB2 : 1; + __IO uint32_t GLI : 1; + __IO uint32_t GMI : 1; + __IO uint32_t GPI : 1; + __IO uint32_t TTI : 1; + __IO uint32_t GLPII : 1; +} stc_ethernet_mac_sr_field_t; + +typedef struct stc_ethernet_mac_omr_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t SR : 1; + __IO uint32_t OSF : 1; + __IO uint32_t RTC0 : 1; + __IO uint32_t RTC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t FUF : 1; + __IO uint32_t FEF : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t ST : 1; + __IO uint32_t TTC0 : 1; + __IO uint32_t TTC1 : 1; + __IO uint32_t TTC2 : 1; + uint32_t RESERVED4 : 3; + __IO uint32_t FTF : 1; + __IO uint32_t TSF : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t DFF : 1; + __IO uint32_t RSF : 1; + __IO uint32_t DT : 1; +} stc_ethernet_mac_omr_field_t; + +typedef struct stc_ethernet_mac_ier_field +{ + __IO uint32_t TIE : 1; + __IO uint32_t TSE : 1; + __IO uint32_t TUE : 1; + __IO uint32_t TJE : 1; + __IO uint32_t OVE : 1; + __IO uint32_t UNE : 1; + __IO uint32_t RIE : 1; + __IO uint32_t RUE : 1; + __IO uint32_t RSE : 1; + __IO uint32_t RWE : 1; + __IO uint32_t ETE : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t FBE : 1; + __IO uint32_t ERE : 1; + __IO uint32_t AIE : 1; + __IO uint32_t NIE : 1; +} stc_ethernet_mac_ier_field_t; + +typedef struct stc_ethernet_mac_mfbocr_field +{ + __IO uint32_t NMFH0 : 1; + __IO uint32_t NMFH1 : 1; + __IO uint32_t NMFH2 : 1; + __IO uint32_t NMFH3 : 1; + __IO uint32_t NMFH4 : 1; + __IO uint32_t NMFH5 : 1; + __IO uint32_t NMFH6 : 1; + __IO uint32_t NMFH7 : 1; + __IO uint32_t NMFH8 : 1; + __IO uint32_t NMFH9 : 1; + __IO uint32_t NMFH10 : 1; + __IO uint32_t NMFH11 : 1; + __IO uint32_t NMFH12 : 1; + __IO uint32_t NMFH13 : 1; + __IO uint32_t NMFH14 : 1; + __IO uint32_t NMFH15 : 1; + __IO uint32_t ONMFH : 1; + __IO uint32_t NMFF0 : 1; + __IO uint32_t NMFF1 : 1; + __IO uint32_t NMFF2 : 1; + __IO uint32_t NMFF3 : 1; + __IO uint32_t NMFF4 : 1; + __IO uint32_t NMFF5 : 1; + __IO uint32_t NMFF6 : 1; + __IO uint32_t NMFF7 : 1; + __IO uint32_t NMFF8 : 1; + __IO uint32_t NMFF9 : 1; + __IO uint32_t NMFF10 : 1; + __IO uint32_t ONMFF : 1; +} stc_ethernet_mac_mfbocr_field_t; + +typedef struct stc_ethernet_mac_riwtr_field +{ + __IO uint32_t RIWT0 : 1; + __IO uint32_t RIWT1 : 1; + __IO uint32_t RIWT2 : 1; + __IO uint32_t RIWT3 : 1; + __IO uint32_t RIWT4 : 1; + __IO uint32_t RIWT5 : 1; + __IO uint32_t RIWT6 : 1; + __IO uint32_t RIWT7 : 1; +} stc_ethernet_mac_riwtr_field_t; + +typedef struct stc_ethernet_mac_ahbsr_field +{ + __IO uint32_t AHBS : 1; +} stc_ethernet_mac_ahbsr_field_t; + +typedef struct stc_ethernet_mac_chtdr_field +{ + __IO uint32_t HTDAP0 : 1; + __IO uint32_t HTDAP1 : 1; + __IO uint32_t HTDAP2 : 1; + __IO uint32_t HTDAP3 : 1; + __IO uint32_t HTDAP4 : 1; + __IO uint32_t HTDAP5 : 1; + __IO uint32_t HTDAP6 : 1; + __IO uint32_t HTDAP7 : 1; + __IO uint32_t HTDAP8 : 1; + __IO uint32_t HTDAP9 : 1; + __IO uint32_t HTDAP10 : 1; + __IO uint32_t HTDAP11 : 1; + __IO uint32_t HTDAP12 : 1; + __IO uint32_t HTDAP13 : 1; + __IO uint32_t HTDAP14 : 1; + __IO uint32_t HTDAP15 : 1; + __IO uint32_t HTDAP16 : 1; + __IO uint32_t HTDAP17 : 1; + __IO uint32_t HTDAP18 : 1; + __IO uint32_t HTDAP19 : 1; + __IO uint32_t HTDAP20 : 1; + __IO uint32_t HTDAP21 : 1; + __IO uint32_t HTDAP22 : 1; + __IO uint32_t HTDAP23 : 1; + __IO uint32_t HTDAP24 : 1; + __IO uint32_t HTDAP25 : 1; + __IO uint32_t HTDAP26 : 1; + __IO uint32_t HTDAP27 : 1; + __IO uint32_t HTDAP28 : 1; + __IO uint32_t HTDAP29 : 1; + __IO uint32_t HTDAP30 : 1; + __IO uint32_t HTDAP31 : 1; +} stc_ethernet_mac_chtdr_field_t; + +typedef struct stc_ethernet_mac_chrdr_field +{ + __IO uint32_t HRDAP0 : 1; + __IO uint32_t HRDAP1 : 1; + __IO uint32_t HRDAP2 : 1; + __IO uint32_t HRDAP3 : 1; + __IO uint32_t HRDAP4 : 1; + __IO uint32_t HRDAP5 : 1; + __IO uint32_t HRDAP6 : 1; + __IO uint32_t HRDAP7 : 1; + __IO uint32_t HRDAP8 : 1; + __IO uint32_t HRDAP9 : 1; + __IO uint32_t HRDAP10 : 1; + __IO uint32_t HRDAP11 : 1; + __IO uint32_t HRDAP12 : 1; + __IO uint32_t HRDAP13 : 1; + __IO uint32_t HRDAP14 : 1; + __IO uint32_t HRDAP15 : 1; + __IO uint32_t HRDAP16 : 1; + __IO uint32_t HRDAP17 : 1; + __IO uint32_t HRDAP18 : 1; + __IO uint32_t HRDAP19 : 1; + __IO uint32_t HRDAP20 : 1; + __IO uint32_t HRDAP21 : 1; + __IO uint32_t HRDAP22 : 1; + __IO uint32_t HRDAP23 : 1; + __IO uint32_t HRDAP24 : 1; + __IO uint32_t HRDAP25 : 1; + __IO uint32_t HRDAP26 : 1; + __IO uint32_t HRDAP27 : 1; + __IO uint32_t HRDAP28 : 1; + __IO uint32_t HRDAP29 : 1; + __IO uint32_t HRDAP30 : 1; + __IO uint32_t HRDAP31 : 1; +} stc_ethernet_mac_chrdr_field_t; + +typedef struct stc_ethernet_mac_chtbar_field +{ + __IO uint32_t HTBAR0 : 1; + __IO uint32_t HTBAR1 : 1; + __IO uint32_t HTBAR2 : 1; + __IO uint32_t HTBAR3 : 1; + __IO uint32_t HTBAR4 : 1; + __IO uint32_t HTBAR5 : 1; + __IO uint32_t HTBAR6 : 1; + __IO uint32_t HTBAR7 : 1; + __IO uint32_t HTBAR8 : 1; + __IO uint32_t HTBAR9 : 1; + __IO uint32_t HTBAR10 : 1; + __IO uint32_t HTBAR11 : 1; + __IO uint32_t HTBAR12 : 1; + __IO uint32_t HTBAR13 : 1; + __IO uint32_t HTBAR14 : 1; + __IO uint32_t HTBAR15 : 1; + __IO uint32_t HTBAR16 : 1; + __IO uint32_t HTBAR17 : 1; + __IO uint32_t HTBAR18 : 1; + __IO uint32_t HTBAR19 : 1; + __IO uint32_t HTBAR20 : 1; + __IO uint32_t HTBAR21 : 1; + __IO uint32_t HTBAR22 : 1; + __IO uint32_t HTBAR23 : 1; + __IO uint32_t HTBAR24 : 1; + __IO uint32_t HTBAR25 : 1; + __IO uint32_t HTBAR26 : 1; + __IO uint32_t HTBAR27 : 1; + __IO uint32_t HTBAR28 : 1; + __IO uint32_t HTBAR29 : 1; + __IO uint32_t HTBAR30 : 1; + __IO uint32_t HTBAR31 : 1; +} stc_ethernet_mac_chtbar_field_t; + +typedef struct stc_ethernet_mac_chrbar_field +{ + __IO uint32_t HRBAR0 : 1; + __IO uint32_t HRBAR1 : 1; + __IO uint32_t HRBAR2 : 1; + __IO uint32_t HRBAR3 : 1; + __IO uint32_t HRBAR4 : 1; + __IO uint32_t HRBAR5 : 1; + __IO uint32_t HRBAR6 : 1; + __IO uint32_t HRBAR7 : 1; + __IO uint32_t HRBAR8 : 1; + __IO uint32_t HRBAR9 : 1; + __IO uint32_t HRBAR10 : 1; + __IO uint32_t HRBAR11 : 1; + __IO uint32_t HRBAR12 : 1; + __IO uint32_t HRBAR13 : 1; + __IO uint32_t HRBAR14 : 1; + __IO uint32_t HRBAR15 : 1; + __IO uint32_t HRBAR16 : 1; + __IO uint32_t HRBAR17 : 1; + __IO uint32_t HRBAR18 : 1; + __IO uint32_t HRBAR19 : 1; + __IO uint32_t HRBAR20 : 1; + __IO uint32_t HRBAR21 : 1; + __IO uint32_t HRBAR22 : 1; + __IO uint32_t HRBAR23 : 1; + __IO uint32_t HRBAR24 : 1; + __IO uint32_t HRBAR25 : 1; + __IO uint32_t HRBAR26 : 1; + __IO uint32_t HRBAR27 : 1; + __IO uint32_t HRBAR28 : 1; + __IO uint32_t HRBAR29 : 1; + __IO uint32_t HRBAR30 : 1; + __IO uint32_t HRBAR31 : 1; +} stc_ethernet_mac_chrbar_field_t; + +/* ETHERNET_CONTROL_MODULE register bit fields */ +typedef struct stc_ethernet_control_eth_mode_field +{ + __IO uint32_t IFMODE : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t RST0 : 1; + __IO uint32_t RST1 : 1; + uint32_t RESERVED2 :18; + __IO uint32_t ASZPPSSEL : 1; +} stc_ethernet_control_eth_mode_field_t; + +typedef struct stc_ethernet_control_eth_clkg_field +{ + __IO uint32_t MACEN0 : 1; + __IO uint32_t MACEN1 : 1; +} stc_ethernet_control_eth_clkg_field_t; + +/****************************************************************************** + * Peripheral register structures + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + }; + uint8_t RESERVED0[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + }; + uint8_t RESERVED1[236]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + }; +}FM3_FLASH_IF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + union { + __IO uint8_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + }; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + union { + __IO uint16_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + }; + uint8_t RESERVED7[7]; + union { + __IO uint8_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + }; + uint8_t RESERVED8[7]; + union { + __IO uint8_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint16_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint8_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + }; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + union { + __IO uint8_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + }; + uint8_t RESERVED18[11]; + union { + __IO uint8_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + }; + uint8_t RESERVED19[3]; + union { + __IO uint8_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + }; + uint8_t RESERVED20[3]; + union { + __IO uint8_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + }; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + union { + __IO uint8_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + }; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + }; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + union { + __IO uint8_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + union { + __IO uint8_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + }; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + union { + __IO uint32_t TIMER1CONTROL; + stc_dtim_timer1control_field_t TIMER1CONTROL_f; + }; + __IO uint32_t TIMER1INTCLR; + union { + __IO uint32_t TIMER1RIS; + stc_dtim_timer1ris_field_t TIMER1RIS_f; + }; + union { + __IO uint32_t TIMER1MIS; + stc_dtim_timer1mis_field_t TIMER1MIS_f; + }; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + union { + __IO uint32_t TIMER2CONTROL; + stc_dtim_timer2control_field_t TIMER2CONTROL_f; + }; + __IO uint32_t TIMER2INTCLR; + union { + __IO uint32_t TIMER2RIS; + stc_dtim_timer2ris_field_t TIMER2RIS_f; + }; + union { + __IO uint32_t TIMER2MIS; + stc_dtim_timer2mis_field_t TIMER2MIS_f; + }; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t TCSB0; + stc_mft_frt_tcsb0_field_t TCSB0_f; + }; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t TCSB1; + stc_mft_frt_tcsb1_field_t TCSB1_f; + }; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t TCSB2; + stc_mft_frt_tcsb2_field_t TCSB2_f; + }; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + uint8_t RESERVED9[50]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + }; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ACSB; + stc_mft_adcmp_acsb_field_t ACSB_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ATSA; + stc_mft_adcmp_atsa_field_t ATSA_f; + }; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[12]; + union { + __IO uint8_t TTCR2; + stc_mft_ppg_ttcr2_field_t TTCR2_f; + }; + uint8_t RESERVED11[7]; + __IO uint8_t COMP8; + uint8_t RESERVED12[2]; + __IO uint8_t COMP10; + uint8_t RESERVED13[4]; + __IO uint8_t COMP12; + uint8_t RESERVED14[2]; + __IO uint8_t COMP14; + uint8_t RESERVED15[171]; + union { + __IO uint16_t TRG; + stc_mft_ppg_trg_field_t TRG_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t REVC; + stc_mft_ppg_revc_field_t REVC_f; + }; + uint8_t RESERVED17[58]; + union { + __IO uint16_t TRG1; + stc_mft_ppg_trg1_field_t TRG1_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t REVC1; + stc_mft_ppg_revc1_field_t REVC1_f; + }; + uint8_t RESERVED19[186]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + uint8_t RESERVED20[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + uint8_t RESERVED26[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + uint8_t RESERVED27[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED32[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + uint8_t RESERVED33[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + uint8_t RESERVED34[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED39[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + uint8_t RESERVED40[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + uint8_t RESERVED41[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + uint8_t RESERVED42[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED43[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED44[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED45[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED46[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; + uint8_t RESERVED47[39]; + union { + __IO uint8_t PPGC17; + stc_mft_ppg_ppgc17_field_t PPGC17_f; + }; + union { + __IO uint8_t PPGC16; + stc_mft_ppg_ppgc16_field_t PPGC16_f; + }; + uint8_t RESERVED48[2]; + union { + __IO uint8_t PPGC19; + stc_mft_ppg_ppgc19_field_t PPGC19_f; + }; + union { + __IO uint8_t PPGC18; + stc_mft_ppg_ppgc18_field_t PPGC18_f; + }; + uint8_t RESERVED49[2]; + union { + __IO uint16_t PRL16; + struct { + __IO uint8_t PRLL16; + __IO uint8_t PRLH16; + }; + }; + uint8_t RESERVED50[2]; + union { + __IO uint16_t PRL17; + struct { + __IO uint8_t PRLL17; + __IO uint8_t PRLH17; + }; + }; + uint8_t RESERVED51[2]; + union { + __IO uint16_t PRL18; + struct { + __IO uint8_t PRLL18; + __IO uint8_t PRLH18; + }; + }; + uint8_t RESERVED52[2]; + union { + __IO uint16_t PRL19; + struct { + __IO uint8_t PRLL19; + __IO uint8_t PRLH19; + }; + }; + uint8_t RESERVED53[2]; + union { + __IO uint8_t GATEC16; + stc_mft_ppg_gatec16_field_t GATEC16_f; + }; + uint8_t RESERVED54[39]; + union { + __IO uint8_t PPGC21; + stc_mft_ppg_ppgc21_field_t PPGC21_f; + }; + union { + __IO uint8_t PPGC20; + stc_mft_ppg_ppgc20_field_t PPGC20_f; + }; + uint8_t RESERVED55[2]; + union { + __IO uint8_t PPGC23; + stc_mft_ppg_ppgc23_field_t PPGC23_f; + }; + union { + __IO uint8_t PPGC22; + stc_mft_ppg_ppgc22_field_t PPGC22_f; + }; + uint8_t RESERVED56[2]; + union { + __IO uint16_t PRL20; + struct { + __IO uint8_t PRLL20; + __IO uint8_t PRLH20; + }; + }; + uint8_t RESERVED57[2]; + union { + __IO uint16_t PRL21; + struct { + __IO uint8_t PRLL21; + __IO uint8_t PRLH21; + }; + }; + uint8_t RESERVED58[2]; + union { + __IO uint16_t PRL22; + struct { + __IO uint8_t PRLL22; + __IO uint8_t PRLH22; + }; + }; + uint8_t RESERVED59[2]; + union { + __IO uint16_t PRL23; + struct { + __IO uint8_t PRLL23; + __IO uint8_t PRLH23; + }; + }; + uint8_t RESERVED60[2]; + union { + __IO uint8_t GATEC20; + stc_mft_ppg_gatec20_field_t GATEC20_f; + }; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * BTIOSEL8B_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 8 - channel 11 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL89AB; + stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; + }; +}FM3_BTIOSEL8B_TypeDef; + +/****************************************************************************** + * BTIOSELCF_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 12 - channel 15 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSELCDEF; + stc_btioselcf_btselcdef_field_t BTSELCDEF_f; + }; +}FM3_BTIOSELCF_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + }; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t QICR; + stc_qprc_qicr_field_t QICR_f; + }; + struct { + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + }; + struct { + union { + __IO uint8_t QCRL; + stc_qprc_qcrl_field_t QCRL_f; + }; + union { + __IO uint8_t QCRH; + stc_qprc_qcrh_field_t QCRH_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + }; + uint8_t RESERVED7[30]; + __IO uint16_t QRCRR; + __IO uint16_t QPCRR; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + }; + struct { + union { + __IO uint16_t SCFDL; + stc_adc_scfdl_field_t SCFDL_f; + }; + union { + __IO uint16_t SCFDH; + stc_adc_scfdh_field_t SCFDH_f; + }; + }; + }; + union { + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + }; + struct { + union { + __IO uint8_t SCIS2; + stc_adc_scis2_field_t SCIS2_f; + }; + union { + __IO uint8_t SCIS3; + stc_adc_scis3_field_t SCIS3_f; + }; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + }; + struct { + union { + __IO uint8_t SCIS0; + stc_adc_scis0_field_t SCIS0_f; + }; + union { + __IO uint8_t SCIS1; + stc_adc_scis1_field_t SCIS1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + }; + struct { + union { + __IO uint16_t PCFDL; + stc_adc_pcfdl_field_t PCFDL_f; + }; + union { + __IO uint16_t PCFDH; + stc_adc_pcfdh_field_t PCFDH_f; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + uint8_t RESERVED6; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + }; + union { + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + }; + struct { + union { + __IO uint8_t ADSS2; + stc_adc_adss2_field_t ADSS2_f; + }; + union { + __IO uint8_t ADSS3; + stc_adc_adss3_field_t ADSS3_f; + }; + }; + }; + uint8_t RESERVED7[2]; + union { + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + }; + struct { + union { + __IO uint8_t ADSS0; + stc_adc_adss0_field_t ADSS0_f; + }; + union { + __IO uint8_t ADSS1; + stc_adc_adss1_field_t ADSS1_f; + }; + }; + }; + uint8_t RESERVED8[2]; + union { + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + }; + struct { + union { + __IO uint8_t ADST1; + stc_adc_adst1_field_t ADST1_f; + }; + union { + __IO uint8_t ADST0; + stc_adc_adst0_field_t ADST0_f; + }; + }; + }; + uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint8_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + }; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint16_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + }; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + union { + __IO uint32_t ENIR; + stc_exti_enir_field_t ENIR_f; + }; + union { + __IO uint32_t EIRR; + stc_exti_eirr_field_t EIRR_f; + }; + union { + __IO uint32_t EICL; + stc_exti_eicl_field_t EICL_f; + }; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + }; + union { + __IO uint32_t ELVR1; + stc_exti_elvr1_field_t ELVR1_f; + }; + union { + __IO uint8_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + }; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + }; + uint8_t RESERVED0[7]; + union { + __IO uint8_t ODDPKS; + stc_intreq_oddpks_field_t ODDPKS_f; + }; + uint8_t RESERVED1[4]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + }; + union { + __IO uint32_t IRQ00MON; + stc_intreq_irq00mon_field_t IRQ00MON_f; + }; + union { + __IO uint32_t IRQ01MON; + stc_intreq_irq01mon_field_t IRQ01MON_f; + }; + union { + __IO uint32_t IRQ02MON; + stc_intreq_irq02mon_field_t IRQ02MON_f; + }; + union { + __IO uint32_t IRQ03MON; + stc_intreq_irq03mon_field_t IRQ03MON_f; + }; + union { + __IO uint32_t IRQ04MON; + stc_intreq_irq04mon_field_t IRQ04MON_f; + }; + union { + __IO uint32_t IRQ05MON; + stc_intreq_irq05mon_field_t IRQ05MON_f; + }; + union { + __IO uint32_t IRQ06MON; + stc_intreq_irq06mon_field_t IRQ06MON_f; + }; + union { + __IO uint32_t IRQ07MON; + stc_intreq_irq07mon_field_t IRQ07MON_f; + }; + union { + __IO uint32_t IRQ08MON; + stc_intreq_irq08mon_field_t IRQ08MON_f; + }; + union { + __IO uint32_t IRQ09MON; + stc_intreq_irq09mon_field_t IRQ09MON_f; + }; + union { + __IO uint32_t IRQ10MON; + stc_intreq_irq10mon_field_t IRQ10MON_f; + }; + union { + __IO uint32_t IRQ11MON; + stc_intreq_irq11mon_field_t IRQ11MON_f; + }; + union { + __IO uint32_t IRQ12MON; + stc_intreq_irq12mon_field_t IRQ12MON_f; + }; + union { + __IO uint32_t IRQ13MON; + stc_intreq_irq13mon_field_t IRQ13MON_f; + }; + union { + __IO uint32_t IRQ14MON; + stc_intreq_irq14mon_field_t IRQ14MON_f; + }; + union { + __IO uint32_t IRQ15MON; + stc_intreq_irq15mon_field_t IRQ15MON_f; + }; + union { + __IO uint32_t IRQ16MON; + stc_intreq_irq16mon_field_t IRQ16MON_f; + }; + union { + __IO uint32_t IRQ17MON; + stc_intreq_irq17mon_field_t IRQ17MON_f; + }; + union { + __IO uint32_t IRQ18MON; + stc_intreq_irq18mon_field_t IRQ18MON_f; + }; + union { + __IO uint32_t IRQ19MON; + stc_intreq_irq19mon_field_t IRQ19MON_f; + }; + union { + __IO uint32_t IRQ20MON; + stc_intreq_irq20mon_field_t IRQ20MON_f; + }; + union { + __IO uint32_t IRQ21MON; + stc_intreq_irq21mon_field_t IRQ21MON_f; + }; + union { + __IO uint32_t IRQ22MON; + stc_intreq_irq22mon_field_t IRQ22MON_f; + }; + union { + __IO uint32_t IRQ23MON; + stc_intreq_irq23mon_field_t IRQ23MON_f; + }; + union { + __IO uint32_t IRQ24MON; + stc_intreq_irq24mon_field_t IRQ24MON_f; + }; + union { + __IO uint32_t IRQ25MON; + stc_intreq_irq25mon_field_t IRQ25MON_f; + }; + union { + __IO uint32_t IRQ26MON; + stc_intreq_irq26mon_field_t IRQ26MON_f; + }; + union { + __IO uint32_t IRQ27MON; + stc_intreq_irq27mon_field_t IRQ27MON_f; + }; + union { + __IO uint32_t IRQ28MON; + stc_intreq_irq28mon_field_t IRQ28MON_f; + }; + union { + __IO uint32_t IRQ29MON; + stc_intreq_irq29mon_field_t IRQ29MON_f; + }; + union { + __IO uint32_t IRQ30MON; + stc_intreq_irq30mon_field_t IRQ30MON_f; + }; + union { + __IO uint32_t IRQ31MON; + stc_intreq_irq31mon_field_t IRQ31MON_f; + }; + union { + __IO uint32_t IRQ32MON; + stc_intreq_irq32mon_field_t IRQ32MON_f; + }; + union { + __IO uint32_t IRQ33MON; + stc_intreq_irq33mon_field_t IRQ33MON_f; + }; + union { + __IO uint32_t IRQ34MON; + stc_intreq_irq34mon_field_t IRQ34MON_f; + }; + union { + __IO uint32_t IRQ35MON; + stc_intreq_irq35mon_field_t IRQ35MON_f; + }; + union { + __IO uint32_t IRQ36MON; + stc_intreq_irq36mon_field_t IRQ36MON_f; + }; + union { + __IO uint32_t IRQ37MON; + stc_intreq_irq37mon_field_t IRQ37MON_f; + }; + union { + __IO uint32_t IRQ38MON; + stc_intreq_irq38mon_field_t IRQ38MON_f; + }; + union { + __IO uint32_t IRQ39MON; + stc_intreq_irq39mon_field_t IRQ39MON_f; + }; + union { + __IO uint32_t IRQ40MON; + stc_intreq_irq40mon_field_t IRQ40MON_f; + }; + union { + __IO uint32_t IRQ41MON; + stc_intreq_irq41mon_field_t IRQ41MON_f; + }; + union { + __IO uint32_t IRQ42MON; + stc_intreq_irq42mon_field_t IRQ42MON_f; + }; + union { + __IO uint32_t IRQ43MON; + stc_intreq_irq43mon_field_t IRQ43MON_f; + }; + union { + __IO uint32_t IRQ44MON; + stc_intreq_irq44mon_field_t IRQ44MON_f; + }; + union { + __IO uint32_t IRQ45MON; + stc_intreq_irq45mon_field_t IRQ45MON_f; + }; + union { + __IO uint32_t IRQ46MON; + stc_intreq_irq46mon_field_t IRQ46MON_f; + }; + uint8_t RESERVED2[300]; + union { + __IO uint32_t DRQSEL1; + stc_intreq_drqsel1_field_t DRQSEL1_f; + }; + union { + __IO uint32_t DQESEL; + stc_intreq_dqesel_field_t DQESEL_f; + }; + uint8_t RESERVED3[7]; + union { + __IO uint8_t ODDPKS1; + stc_intreq_oddpks1_field_t ODDPKS1_f; + }; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + }; + union { + __IO uint32_t PFR5; + stc_gpio_pfr5_field_t PFR5_f; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + }; + __IO uint32_t PFR9; + union { + __IO uint32_t PFRA; + stc_gpio_pfra_field_t PFRA_f; + }; + __IO uint32_t PFRB; + union { + __IO uint32_t PFRC; + stc_gpio_pfrc_field_t PFRC_f; + }; + union { + __IO uint32_t PFRD; + stc_gpio_pfrd_field_t PFRD_f; + }; + union { + __IO uint32_t PFRE; + stc_gpio_pfre_field_t PFRE_f; + }; + union { + __IO uint32_t PFRF; + stc_gpio_pfrf_field_t PFRF_f; + }; + uint8_t RESERVED0[192]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + }; + union { + __IO uint32_t PCR5; + stc_gpio_pcr5_field_t PCR5_f; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + }; + __IO uint32_t PCR8; + __IO uint32_t PCR9; + union { + __IO uint32_t PCRA; + stc_gpio_pcra_field_t PCRA_f; + }; + __IO uint32_t PCRB; + union { + __IO uint32_t PCRC; + stc_gpio_pcrc_field_t PCRC_f; + }; + union { + __IO uint32_t PCRD; + stc_gpio_pcrd_field_t PCRD_f; + }; + union { + __IO uint32_t PCRE; + stc_gpio_pcre_field_t PCRE_f; + }; + __IO uint32_t PCRF; + uint8_t RESERVED1[192]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + }; + union { + __IO uint32_t DDR5; + stc_gpio_ddr5_field_t DDR5_f; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + }; + __IO uint32_t DDR9; + union { + __IO uint32_t DDRA; + stc_gpio_ddra_field_t DDRA_f; + }; + __IO uint32_t DDRB; + union { + __IO uint32_t DDRC; + stc_gpio_ddrc_field_t DDRC_f; + }; + union { + __IO uint32_t DDRD; + stc_gpio_ddrd_field_t DDRD_f; + }; + union { + __IO uint32_t DDRE; + stc_gpio_ddre_field_t DDRE_f; + }; + union { + __IO uint32_t DDRF; + stc_gpio_ddrf_field_t DDRF_f; + }; + uint8_t RESERVED2[192]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + }; + union { + __IO uint32_t PDIR5; + stc_gpio_pdir5_field_t PDIR5_f; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + }; + __IO uint32_t PDIR9; + union { + __IO uint32_t PDIRA; + stc_gpio_pdira_field_t PDIRA_f; + }; + __IO uint32_t PDIRB; + union { + __IO uint32_t PDIRC; + stc_gpio_pdirc_field_t PDIRC_f; + }; + union { + __IO uint32_t PDIRD; + stc_gpio_pdird_field_t PDIRD_f; + }; + union { + __IO uint32_t PDIRE; + stc_gpio_pdire_field_t PDIRE_f; + }; + union { + __IO uint32_t PDIRF; + stc_gpio_pdirf_field_t PDIRF_f; + }; + uint8_t RESERVED3[192]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + }; + union { + __IO uint32_t PDOR5; + stc_gpio_pdor5_field_t PDOR5_f; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + }; + __IO uint32_t PDOR9; + union { + __IO uint32_t PDORA; + stc_gpio_pdora_field_t PDORA_f; + }; + __IO uint32_t PDORB; + union { + __IO uint32_t PDORC; + stc_gpio_pdorc_field_t PDORC_f; + }; + union { + __IO uint32_t PDORD; + stc_gpio_pdord_field_t PDORD_f; + }; + union { + __IO uint32_t PDORE; + stc_gpio_pdore_field_t PDORE_f; + }; + union { + __IO uint32_t PDORF; + stc_gpio_pdorf_field_t PDORF_f; + }; + uint8_t RESERVED4[192]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + }; + uint8_t RESERVED5[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + }; + uint8_t RESERVED6[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + }; + union { + __IO uint32_t EPFR03; + stc_gpio_epfr03_field_t EPFR03_f; + }; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + }; + union { + __IO uint32_t EPFR11; + stc_gpio_epfr11_field_t EPFR11_f; + }; + union { + __IO uint32_t EPFR12; + stc_gpio_epfr12_field_t EPFR12_f; + }; + union { + __IO uint32_t EPFR13; + stc_gpio_epfr13_field_t EPFR13_f; + }; + union { + __IO uint32_t EPFR14; + stc_gpio_epfr14_field_t EPFR14_f; + }; + union { + __IO uint32_t EPFR15; + stc_gpio_epfr15_field_t EPFR15_f; + }; + uint8_t RESERVED7[192]; + union { + __IO uint32_t PZR0; + stc_gpio_pzr0_field_t PZR0_f; + }; + union { + __IO uint32_t PZR1; + stc_gpio_pzr1_field_t PZR1_f; + }; + union { + __IO uint32_t PZR2; + stc_gpio_pzr2_field_t PZR2_f; + }; + union { + __IO uint32_t PZR3; + stc_gpio_pzr3_field_t PZR3_f; + }; + union { + __IO uint32_t PZR4; + stc_gpio_pzr4_field_t PZR4_f; + }; + union { + __IO uint32_t PZR5; + stc_gpio_pzr5_field_t PZR5_f; + }; + union { + __IO uint32_t PZR6; + stc_gpio_pzr6_field_t PZR6_f; + }; + union { + __IO uint32_t PZR7; + stc_gpio_pzr7_field_t PZR7_f; + }; + union { + __IO uint32_t PZR8; + stc_gpio_pzr8_field_t PZR8_f; + }; + __IO uint32_t PZR9; + union { + __IO uint32_t PZRA; + stc_gpio_pzra_field_t PZRA_f; + }; + __IO uint32_t PZRB; + union { + __IO uint32_t PZRC; + stc_gpio_pzrc_field_t PZRC_f; + }; + union { + __IO uint32_t PZRD; + stc_gpio_pzrd_field_t PZRD_f; + }; + union { + __IO uint32_t PZRE; + stc_gpio_pzre_field_t PZRE_f; + }; + union { + __IO uint32_t PZRF; + stc_gpio_pzrf_field_t PZRF_f; + }; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBETHERNETCLK + ******************************************************************************/ +/* USB Ethernet clock registers */ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbethernetclk_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbethernetclk_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbethernetclk_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbethernetclk_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbethernetclk_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbethernetclk_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbethernetclk_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbethernetclk_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t UPCR6; + stc_usbethernetclk_upcr6_field_t UPCR6_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t UPCR7; + stc_usbethernetclk_upcr7_field_t UPCR7_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t USBEN0; + stc_usbethernetclk_usben0_field_t USBEN0_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t USBEN1; + stc_usbethernetclk_usben1_field_t USBEN1_f; + }; +}FM3_USBETHERNETCLK_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs03_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs03_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_uart_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_lin_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs03_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs03_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs03_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs03_i2c_ismk_field_t ISMK_f; + }; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs47_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs47_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_uart_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_uart_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_uart_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_uart_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_uart_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_uart_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_uart_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_csio_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_csio_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_csio_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_csio_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_csio_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_csio_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_lin_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_lin_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_lin_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_lin_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_lin_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_lin_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_lin_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs47_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs47_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs47_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs47_i2c_ismk_field_t ISMK_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_i2c_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_i2c_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_i2c_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_i2c_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * MFS_NFC_MODULE + ******************************************************************************/ +/* MFS_NFC_MODULE register bit fields */ +typedef struct +{ + union { + __IO uint16_t I2CDNF; + stc_mfs_nfc_i2cdnf_field_t I2CDNF_f; + }; +}FM3_MFS_NFC_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode0_field_t MODE0_f; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode1_field_t MODE1_f; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode2_field_t MODE2_f; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode3_field_t MODE3_f; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode4_field_t MODE4_f; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode5_field_t MODE5_f; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode6_field_t MODE6_f; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode7_field_t MODE7_f; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim0_field_t TIM0_f; + }; + union { + __IO uint32_t TIM1; + stc_exbus_tim1_field_t TIM1_f; + }; + union { + __IO uint32_t TIM2; + stc_exbus_tim2_field_t TIM2_f; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim3_field_t TIM3_f; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim4_field_t TIM4_f; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim5_field_t TIM5_f; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim6_field_t TIM6_f; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim7_field_t TIM7_f; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area0_field_t AREA0_f; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area1_field_t AREA1_f; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area2_field_t AREA2_f; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area3_field_t AREA3_f; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area4_field_t AREA4_f; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area5_field_t AREA5_f; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area6_field_t AREA6_f; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area7_field_t AREA7_f; + }; + union { + __IO uint16_t ATIM0; + stc_exbus_atim0_field_t ATIM0_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint16_t ATIM1; + stc_exbus_atim1_field_t ATIM1_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t ATIM2; + stc_exbus_atim2_field_t ATIM2_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t ATIM3; + stc_exbus_atim3_field_t ATIM3_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t ATIM4; + stc_exbus_atim4_field_t ATIM4_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t ATIM5; + stc_exbus_atim5_field_t ATIM5_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t ATIM6; + stc_exbus_atim6_field_t ATIM6_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t ATIM7; + stc_exbus_atim7_field_t ATIM7_f; + }; + uint8_t RESERVED7[642]; + union { + __IO uint8_t DCLKR; + stc_exbus_dclkr_field_t DCLKR_f; + }; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + }; + struct { + union { + __IO uint8_t HCNT0; + stc_usb_hcnt0_field_t HCNT0_f; + }; + union { + __IO uint8_t HCNT1; + stc_usb_hcnt1_field_t HCNT1_f; + }; + }; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + }; + struct { + union { + __IO uint8_t HRTIMER0; + stc_usb_hrtimer0_field_t HRTIMER0_f; + }; + union { + __IO uint8_t HRTIMER1; + stc_usb_hrtimer1_field_t HRTIMER1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + }; + struct { + union { + __IO uint8_t HEOF0; + stc_usb_heof0_field_t HEOF0_f; + }; + union { + __IO uint8_t HEOF1; + stc_usb_heof1_field_t HEOF1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + }; + struct { + union { + __IO uint8_t HFRAME0; + stc_usb_hframe0_field_t HFRAME0_f; + }; + union { + __IO uint8_t HFRAME1; + stc_usb_hframe1_field_t HFRAME1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + }; + uint8_t RESERVED19[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + }; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + }; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + }; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + }; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + }; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + }; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + }; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + }; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + }; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * ETHERNET_MAC_MODULE + ******************************************************************************/ +/* ETHERNET-MAC registers */ +typedef struct +{ + union { + __IO uint32_t MCR; + stc_ethernet_mac_mcr_field_t MCR_f; + }; + union { + __IO uint32_t MFFR; + stc_ethernet_mac_mffr_field_t MFFR_f; + }; + union { + __IO uint32_t MHTRH; + stc_ethernet_mac_mhtrh_field_t MHTRH_f; + }; + union { + __IO uint32_t MHTRL; + stc_ethernet_mac_mhtrl_field_t MHTRL_f; + }; + union { + __IO uint32_t GAR; + stc_ethernet_mac_gar_field_t GAR_f; + }; + union { + __IO uint32_t GDR; + stc_ethernet_mac_gdr_field_t GDR_f; + }; + union { + __IO uint32_t FCR; + stc_ethernet_mac_fcr_field_t FCR_f; + }; + union { + __IO uint32_t VTR; + stc_ethernet_mac_vtr_field_t VTR_f; + }; + uint8_t RESERVED0[8]; + union { + __IO uint32_t RWFFR; + stc_ethernet_mac_rwffr_field_t RWFFR_f; + }; + union { + __IO uint32_t PMTR; + stc_ethernet_mac_pmtr_field_t PMTR_f; + }; + union { + __IO uint32_t LPICSR; + stc_ethernet_mac_lpicsr_field_t LPICSR_f; + }; + union { + __IO uint32_t LPITCR; + stc_ethernet_mac_lpitcr_field_t LPITCR_f; + }; + union { + __IO uint32_t ISR; + stc_ethernet_mac_isr_field_t ISR_f; + }; + union { + __IO uint32_t IMR; + stc_ethernet_mac_imr_field_t IMR_f; + }; + union { + __IO uint32_t MAR0H; + stc_ethernet_mac_mar0h_field_t MAR0H_f; + }; + union { + __IO uint32_t MAR0L; + stc_ethernet_mac_mar0l_field_t MAR0L_f; + }; + union { + __IO uint32_t MAR1H; + stc_ethernet_mac_mar1h_field_t MAR1H_f; + }; + union { + __IO uint32_t MAR1L; + stc_ethernet_mac_mar1l_field_t MAR1L_f; + }; + union { + __IO uint32_t MAR2H; + stc_ethernet_mac_mar2h_field_t MAR2H_f; + }; + union { + __IO uint32_t MAR2L; + stc_ethernet_mac_mar2l_field_t MAR2L_f; + }; + union { + __IO uint32_t MAR3H; + stc_ethernet_mac_mar3h_field_t MAR3H_f; + }; + union { + __IO uint32_t MAR3L; + stc_ethernet_mac_mar3l_field_t MAR3L_f; + }; + union { + __IO uint32_t MAR4H; + stc_ethernet_mac_mar4h_field_t MAR4H_f; + }; + union { + __IO uint32_t MAR4L; + stc_ethernet_mac_mar4l_field_t MAR4L_f; + }; + union { + __IO uint32_t MAR5H; + stc_ethernet_mac_mar5h_field_t MAR5H_f; + }; + union { + __IO uint32_t MAR5L; + stc_ethernet_mac_mar5l_field_t MAR5L_f; + }; + union { + __IO uint32_t MAR6H; + stc_ethernet_mac_mar6h_field_t MAR6H_f; + }; + union { + __IO uint32_t MAR6L; + stc_ethernet_mac_mar6l_field_t MAR6L_f; + }; + union { + __IO uint32_t MAR7H; + stc_ethernet_mac_mar7h_field_t MAR7H_f; + }; + union { + __IO uint32_t MAR7L; + stc_ethernet_mac_mar7l_field_t MAR7L_f; + }; + union { + __IO uint32_t MAR8H; + stc_ethernet_mac_mar8h_field_t MAR8H_f; + }; + union { + __IO uint32_t MAR8L; + stc_ethernet_mac_mar8l_field_t MAR8L_f; + }; + union { + __IO uint32_t MAR9H; + stc_ethernet_mac_mar9h_field_t MAR9H_f; + }; + union { + __IO uint32_t MAR9L; + stc_ethernet_mac_mar9l_field_t MAR9L_f; + }; + union { + __IO uint32_t MAR10H; + stc_ethernet_mac_mar10h_field_t MAR10H_f; + }; + union { + __IO uint32_t MAR10L; + stc_ethernet_mac_mar10l_field_t MAR10L_f; + }; + union { + __IO uint32_t MAR11H; + stc_ethernet_mac_mar11h_field_t MAR11H_f; + }; + union { + __IO uint32_t MAR11L; + stc_ethernet_mac_mar11l_field_t MAR11L_f; + }; + union { + __IO uint32_t MAR12H; + stc_ethernet_mac_mar12h_field_t MAR12H_f; + }; + union { + __IO uint32_t MAR12L; + stc_ethernet_mac_mar12l_field_t MAR12L_f; + }; + union { + __IO uint32_t MAR13H; + stc_ethernet_mac_mar13h_field_t MAR13H_f; + }; + union { + __IO uint32_t MAR13L; + stc_ethernet_mac_mar13l_field_t MAR13L_f; + }; + union { + __IO uint32_t MAR14H; + stc_ethernet_mac_mar14h_field_t MAR14H_f; + }; + union { + __IO uint32_t MAR14L; + stc_ethernet_mac_mar14l_field_t MAR14L_f; + }; + union { + __IO uint32_t MAR15H; + stc_ethernet_mac_mar15h_field_t MAR15H_f; + }; + union { + __IO uint32_t MAR15L; + stc_ethernet_mac_mar15l_field_t MAR15L_f; + }; + uint8_t RESERVED1[24]; + union { + __IO uint32_t RGSR; + stc_ethernet_mac_rgsr_field_t RGSR_f; + }; + uint8_t RESERVED2[36]; + __IO uint32_t mmc_cntl; + __IO uint32_t mmc_intr_rx; + __IO uint32_t mmc_intr_tx; + __IO uint32_t mmc_intr_mask_rx; + __IO uint32_t mmc_intr_mask_tx; + __IO uint32_t txoctetcount_gb; + __IO uint32_t txframecount_gb; + __IO uint32_t txbroadcastframes_g; + __IO uint32_t txmulticastframes_g; + __IO uint32_t tx64octets_gb; + __IO uint32_t tx65to127octets_gb; + __IO uint32_t tx128to255octets_gb; + __IO uint32_t tx256to511octets_gb; + __IO uint32_t tx512to1023octets_gb; + __IO uint32_t tx1024tomaxoctets_gb; + __IO uint32_t txunicastframes_gb; + __IO uint32_t txmulticastframes_gb; + __IO uint32_t txbroadcastframes_gb; + __IO uint32_t txunderflowerror; + __IO uint32_t txsinglecol_g; + __IO uint32_t txmulticol_g; + __IO uint32_t txdeferred; + __IO uint32_t txlatecol; + __IO uint32_t txexesscol; + __IO uint32_t txcarriererror; + __IO uint32_t txoctetcount_g; + __IO uint32_t txframecount_g; + __IO uint32_t txexecessdef_g; + __IO uint32_t txpauseframes; + __IO uint32_t txvlanframes_g; + uint8_t RESERVED3[8]; + __IO uint32_t rxframecount_gb; + __IO uint32_t rxoctetcount_gb; + __IO uint32_t rxoctetcount_g; + __IO uint32_t rxbroadcastframes_g; + __IO uint32_t rxmulticastframes_g; + __IO uint32_t rxcrcerror; + __IO uint32_t rxallignmenterror; + __IO uint32_t rxrunterror; + __IO uint32_t rxjabbererror; + __IO uint32_t rxundersize_g; + __IO uint32_t rxoversize_g; + __IO uint32_t rx64octets_gb; + __IO uint32_t rx65to127octets_gb; + __IO uint32_t rx128to255octets_gb; + __IO uint32_t rx256to511octets_gb; + __IO uint32_t rx512to1023octets_gb; + __IO uint32_t rx1024tomaxoctets_gb; + __IO uint32_t rxunicastframes_g; + __IO uint32_t rxlengtherror; + __IO uint32_t rxoutofrangetype; + __IO uint32_t rxpauseframes; + __IO uint32_t rxfifooverflow; + __IO uint32_t rxvlanframes_gb; + __IO uint32_t rxwatchdogerror; + uint8_t RESERVED4[32]; + __IO uint32_t mmc_ipc_intr_mask_rx; + uint8_t RESERVED5[4]; + __IO uint32_t mmc_ipc_intr_rx; + uint8_t RESERVED6[4]; + __IO uint32_t rxipv4_gd_frms; + __IO uint32_t rxipv4_hdrerr_frms; + __IO uint32_t rxipv4_nopay_frms; + __IO uint32_t rxipv4_frag_frms; + __IO uint32_t rxipv4_udsbl_frms; + __IO uint32_t rxipv6_gd_frms; + __IO uint32_t rxipv6_hdrerr_frms; + __IO uint32_t rxipv6_nopay_frms; + __IO uint32_t rxudp_gd_frms; + __IO uint32_t rxudp_err_frms; + __IO uint32_t rxtcp_gd_frms; + __IO uint32_t rxtcp_err_frms; + __IO uint32_t rxicmp_gd_frms; + __IO uint32_t rxicmp_err_frms; + uint8_t RESERVED7[8]; + __IO uint32_t rxipv4_gd_octets; + __IO uint32_t rxipv4_hdrerr_octets; + __IO uint32_t rxipv4_nopay_octets; + __IO uint32_t rxipv4_frag_octets; + __IO uint32_t rxipv4_udsbl_octets; + __IO uint32_t rxipv6_gd_octets; + __IO uint32_t rxipv6_hdrerr_octets; + __IO uint32_t rxipv6_nopay_octets; + __IO uint32_t rxudp_gd_octets; + __IO uint32_t rxudp_err_octets; + __IO uint32_t rxtcp_gd_octets; + __IO uint32_t rxtcp_err_octets; + __IO uint32_t rxicmp_gd_octets; + __IO uint32_t rxicmp_err_octets; + uint8_t RESERVED8[1144]; + union { + __IO uint32_t TSCR; + stc_ethernet_mac_tscr_field_t TSCR_f; + }; + union { + __IO uint32_t SSIR; + stc_ethernet_mac_ssir_field_t SSIR_f; + }; + union { + __IO uint32_t STSR; + stc_ethernet_mac_stsr_field_t STSR_f; + }; + union { + __IO uint32_t STNR; + stc_ethernet_mac_stnr_field_t STNR_f; + }; + union { + __IO uint32_t STSUR; + stc_ethernet_mac_stsur_field_t STSUR_f; + }; + union { + __IO uint32_t STNUR; + stc_ethernet_mac_stnur_field_t STNUR_f; + }; + union { + __IO uint32_t TSAR; + stc_ethernet_mac_tsar_field_t TSAR_f; + }; + union { + __IO uint32_t TTSR; + stc_ethernet_mac_ttsr_field_t TTSR_f; + }; + union { + __IO uint32_t TTNR; + stc_ethernet_mac_ttnr_field_t TTNR_f; + }; + union { + __IO uint32_t STHWSR; + stc_ethernet_mac_sthwsr_field_t STHWSR_f; + }; + union { + __IO uint32_t TSR; + stc_ethernet_mac_tsr_field_t TSR_f; + }; + union { + __IO uint32_t PPSCR; + stc_ethernet_mac_ppscr_field_t PPSCR_f; + }; + union { + __IO uint32_t ATNR; + stc_ethernet_mac_atnr_field_t ATNR_f; + }; + union { + __IO uint32_t ATSR; + stc_ethernet_mac_atsr_field_t ATSR_f; + }; + uint8_t RESERVED9[200]; + union { + __IO uint32_t MAR16H; + stc_ethernet_mac_mar16h_field_t MAR16H_f; + }; + union { + __IO uint32_t MAR16L; + stc_ethernet_mac_mar16l_field_t MAR16L_f; + }; + union { + __IO uint32_t MAR17H; + stc_ethernet_mac_mar17h_field_t MAR17H_f; + }; + union { + __IO uint32_t MAR17L; + stc_ethernet_mac_mar17l_field_t MAR17L_f; + }; + union { + __IO uint32_t MAR18H; + stc_ethernet_mac_mar18h_field_t MAR18H_f; + }; + union { + __IO uint32_t MAR18L; + stc_ethernet_mac_mar18l_field_t MAR18L_f; + }; + union { + __IO uint32_t MAR19H; + stc_ethernet_mac_mar19h_field_t MAR19H_f; + }; + union { + __IO uint32_t MAR19L; + stc_ethernet_mac_mar19l_field_t MAR19L_f; + }; + union { + __IO uint32_t MAR20H; + stc_ethernet_mac_mar20h_field_t MAR20H_f; + }; + union { + __IO uint32_t MAR20L; + stc_ethernet_mac_mar20l_field_t MAR20L_f; + }; + union { + __IO uint32_t MAR21H; + stc_ethernet_mac_mar21h_field_t MAR21H_f; + }; + union { + __IO uint32_t MAR21L; + stc_ethernet_mac_mar21l_field_t MAR21L_f; + }; + union { + __IO uint32_t MAR22H; + stc_ethernet_mac_mar22h_field_t MAR22H_f; + }; + union { + __IO uint32_t MAR22L; + stc_ethernet_mac_mar22l_field_t MAR22L_f; + }; + union { + __IO uint32_t MAR23H; + stc_ethernet_mac_mar23h_field_t MAR23H_f; + }; + union { + __IO uint32_t MAR23L; + stc_ethernet_mac_mar23l_field_t MAR23L_f; + }; + union { + __IO uint32_t MAR24H; + stc_ethernet_mac_mar24h_field_t MAR24H_f; + }; + union { + __IO uint32_t MAR24L; + stc_ethernet_mac_mar24l_field_t MAR24L_f; + }; + union { + __IO uint32_t MAR25H; + stc_ethernet_mac_mar25h_field_t MAR25H_f; + }; + union { + __IO uint32_t MAR25L; + stc_ethernet_mac_mar25l_field_t MAR25L_f; + }; + union { + __IO uint32_t MAR26H; + stc_ethernet_mac_mar26h_field_t MAR26H_f; + }; + union { + __IO uint32_t MAR26L; + stc_ethernet_mac_mar26l_field_t MAR26L_f; + }; + union { + __IO uint32_t MAR27H; + stc_ethernet_mac_mar27h_field_t MAR27H_f; + }; + union { + __IO uint32_t MAR27L; + stc_ethernet_mac_mar27l_field_t MAR27L_f; + }; + union { + __IO uint32_t MAR28H; + stc_ethernet_mac_mar28h_field_t MAR28H_f; + }; + union { + __IO uint32_t MAR28L; + stc_ethernet_mac_mar28l_field_t MAR28L_f; + }; + union { + __IO uint32_t MAR29H; + stc_ethernet_mac_mar29h_field_t MAR29H_f; + }; + union { + __IO uint32_t MAR29L; + stc_ethernet_mac_mar29l_field_t MAR29L_f; + }; + union { + __IO uint32_t MAR30H; + stc_ethernet_mac_mar30h_field_t MAR30H_f; + }; + union { + __IO uint32_t MAR30L; + stc_ethernet_mac_mar30l_field_t MAR30L_f; + }; + union { + __IO uint32_t MAR31H; + stc_ethernet_mac_mar31h_field_t MAR31H_f; + }; + union { + __IO uint32_t MAR31L; + stc_ethernet_mac_mar31l_field_t MAR31L_f; + }; + uint8_t RESERVED10[1920]; + union { + __IO uint32_t BMR; + stc_ethernet_mac_bmr_field_t BMR_f; + }; + union { + __IO uint32_t TPDR; + stc_ethernet_mac_tpdr_field_t TPDR_f; + }; + union { + __IO uint32_t RPDR; + stc_ethernet_mac_rpdr_field_t RPDR_f; + }; + union { + __IO uint32_t RDLAR; + stc_ethernet_mac_rdlar_field_t RDLAR_f; + }; + union { + __IO uint32_t TDLAR; + stc_ethernet_mac_tdlar_field_t TDLAR_f; + }; + union { + __IO uint32_t SR; + stc_ethernet_mac_sr_field_t SR_f; + }; + union { + __IO uint32_t OMR; + stc_ethernet_mac_omr_field_t OMR_f; + }; + union { + __IO uint32_t IER; + stc_ethernet_mac_ier_field_t IER_f; + }; + union { + __IO uint32_t MFBOCR; + stc_ethernet_mac_mfbocr_field_t MFBOCR_f; + }; + union { + __IO uint32_t RIWTR; + stc_ethernet_mac_riwtr_field_t RIWTR_f; + }; + uint8_t RESERVED11[4]; + union { + __IO uint32_t AHBSR; + stc_ethernet_mac_ahbsr_field_t AHBSR_f; + }; + uint8_t RESERVED12[24]; + union { + __IO uint32_t CHTDR; + stc_ethernet_mac_chtdr_field_t CHTDR_f; + }; + union { + __IO uint32_t CHRDR; + stc_ethernet_mac_chrdr_field_t CHRDR_f; + }; + union { + __IO uint32_t CHTBAR; + stc_ethernet_mac_chtbar_field_t CHTBAR_f; + }; + union { + __IO uint32_t CHRBAR; + stc_ethernet_mac_chrbar_field_t CHRBAR_f; + }; +}FM3_ETHERNET_MAC_TypeDef; + +/* ETHERNET-CONTROL registers */ +typedef struct +{ + union { + __IO uint32_t ETH_MODE; + stc_ethernet_control_eth_mode_field_t ETH_MODE_f; + }; + uint8_t RESERVED1[4]; + union { + __IO uint32_t ETH_CLKG; + stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f; + }; +}FM3_ETHERNET_CONTROL_TypeDef; + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT2_FRT_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Free Running Timer registers */ +#define FM3_MFT2_OCU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ +#define FM3_MFT2_WFG_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT2_ICU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ +#define FM3_MFT2_ADCMP_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_BT8_PPG_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ +#define FM3_BT8_PWM_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ +#define FM3_BT8_RT_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ +#define FM3_BT8_PWC_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ +#define FM3_BT9_PPG_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ +#define FM3_BT9_PWM_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ +#define FM3_BT9_RT_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ +#define FM3_BT9_PWC_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ +#define FM3_BT10_PPG_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ +#define FM3_BT10_PWM_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ +#define FM3_BT10_RT_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ +#define FM3_BT10_PWC_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ +#define FM3_BT11_PPG_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ +#define FM3_BT11_PWM_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ +#define FM3_BT11_RT_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ +#define FM3_BT11_PWC_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ +#define FM3_BT12_PPG_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ +#define FM3_BT12_PWM_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ +#define FM3_BT12_RT_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ +#define FM3_BT12_PWC_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ +#define FM3_BT13_PPG_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ +#define FM3_BT13_PWM_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ +#define FM3_BT13_RT_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ +#define FM3_BT13_PWC_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ +#define FM3_BT14_PPG_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ +#define FM3_BT14_PWM_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ +#define FM3_BT14_RT_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ +#define FM3_BT14_PWC_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ +#define FM3_BT15_PPG_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ +#define FM3_BT15_PWM_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ +#define FM3_BT15_RT_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ +#define FM3_BT15_PWC_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ +#define FM3_BTIOSEL8B_BASE (FM3_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ +#define FM3_BTIOSELCF_BASE (FM3_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_QPRC2_BASE (FM3_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_MFS_NFC_BASE (FM3_PERIPH_BASE + 0x38800UL) /* MFS Noise Filter Control register */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_USB1_BASE (FM3_PERIPH_BASE + 0x52100UL) /* USB channel 1 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_ETHERNET_MAC0_BASE (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers */ +#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers */ +#define FM3_ETHERNET_MAC1_BASE (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT2_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE) +#define FM3_MFT2_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE) +#define FM3_MFT2_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE) +#define FM3_MFT2_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE) +#define FM3_MFT2_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_BT8_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE) +#define FM3_BT8_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE) +#define FM3_BT8_RT ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE) +#define FM3_BT8_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE) +#define FM3_BT9_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE) +#define FM3_BT9_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE) +#define FM3_BT9_RT ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE) +#define FM3_BT9_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE) +#define FM3_BT10_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE) +#define FM3_BT10_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE) +#define FM3_BT10_RT ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE) +#define FM3_BT10_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE) +#define FM3_BT11_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE) +#define FM3_BT11_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE) +#define FM3_BT11_RT ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE) +#define FM3_BT11_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE) +#define FM3_BT12_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE) +#define FM3_BT12_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE) +#define FM3_BT12_RT ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE) +#define FM3_BT12_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE) +#define FM3_BT13_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE) +#define FM3_BT13_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE) +#define FM3_BT13_RT ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE) +#define FM3_BT13_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE) +#define FM3_BT14_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE) +#define FM3_BT14_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE) +#define FM3_BT14_RT ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE) +#define FM3_BT14_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE) +#define FM3_BT15_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE) +#define FM3_BT15_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE) +#define FM3_BT15_RT ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE) +#define FM3_BT15_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE) +#define FM3_BTIOSEL8B ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE) +#define FM3_BTIOSELCF ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_QPRC3 ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_MFS_NFC ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_USB1 ((FM3_USB_TypeDef *)FM3_USB1_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_ETHERNET_MAC0 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE) +#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_CONTROL_TypeDef *)FM3_ETHERNET_CONTROL_BASE) +#define FM3_ETHERNET_MAC1 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMER1RIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMER1MIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMER2RIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMER2MIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) +#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) +#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) +#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) +#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) +#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) +#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer unit 2 Free Running Timer registers */ +#define bFM3_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42440600UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42440604UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42440608UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244060CUL)) +#define bFM3_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42440610UL)) +#define bFM3_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42440614UL)) +#define bFM3_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42440618UL)) +#define bFM3_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244061CUL)) +#define bFM3_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42440620UL)) +#define bFM3_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42440624UL)) +#define bFM3_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42440634UL)) +#define bFM3_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42440638UL)) +#define bFM3_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244063CUL)) +#define bFM3_MFT2_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42440680UL)) +#define bFM3_MFT2_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42440684UL)) +#define bFM3_MFT2_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42440688UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42440800UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42440804UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42440808UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4244080CUL)) +#define bFM3_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42440810UL)) +#define bFM3_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42440814UL)) +#define bFM3_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42440818UL)) +#define bFM3_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4244081CUL)) +#define bFM3_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42440820UL)) +#define bFM3_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42440824UL)) +#define bFM3_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42440834UL)) +#define bFM3_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42440838UL)) +#define bFM3_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4244083CUL)) +#define bFM3_MFT2_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42440880UL)) +#define bFM3_MFT2_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42440884UL)) +#define bFM3_MFT2_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42440888UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42440A00UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42440A04UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42440A08UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42440A0CUL)) +#define bFM3_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42440A10UL)) +#define bFM3_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42440A14UL)) +#define bFM3_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42440A18UL)) +#define bFM3_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42440A1CUL)) +#define bFM3_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42440A20UL)) +#define bFM3_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42440A24UL)) +#define bFM3_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42440A34UL)) +#define bFM3_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42440A38UL)) +#define bFM3_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42440A3CUL)) +#define bFM3_MFT2_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42440A80UL)) +#define bFM3_MFT2_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42440A84UL)) +#define bFM3_MFT2_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42440A88UL)) + +/* Multifunction Timer unit 2 Output Compare Unit registers */ +#define bFM3_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42440300UL)) +#define bFM3_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42440304UL)) +#define bFM3_MFT2_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42440308UL)) +#define bFM3_MFT2_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4244030CUL)) +#define bFM3_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42440310UL)) +#define bFM3_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42440314UL)) +#define bFM3_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42440318UL)) +#define bFM3_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244031CUL)) +#define bFM3_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42440320UL)) +#define bFM3_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42440324UL)) +#define bFM3_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42440330UL)) +#define bFM3_MFT2_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42440334UL)) +#define bFM3_MFT2_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42440338UL)) +#define bFM3_MFT2_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42440380UL)) +#define bFM3_MFT2_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42440384UL)) +#define bFM3_MFT2_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42440388UL)) +#define bFM3_MFT2_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4244038CUL)) +#define bFM3_MFT2_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42440390UL)) +#define bFM3_MFT2_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42440394UL)) +#define bFM3_MFT2_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42440398UL)) +#define bFM3_MFT2_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4244039CUL)) +#define bFM3_MFT2_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424403A0UL)) +#define bFM3_MFT2_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424403A4UL)) +#define bFM3_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424403B0UL)) +#define bFM3_MFT2_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424403B4UL)) +#define bFM3_MFT2_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424403B8UL)) +#define bFM3_MFT2_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42440400UL)) +#define bFM3_MFT2_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42440404UL)) +#define bFM3_MFT2_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42440408UL)) +#define bFM3_MFT2_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4244040CUL)) +#define bFM3_MFT2_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42440410UL)) +#define bFM3_MFT2_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42440414UL)) +#define bFM3_MFT2_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42440418UL)) +#define bFM3_MFT2_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4244041CUL)) +#define bFM3_MFT2_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42440420UL)) +#define bFM3_MFT2_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42440424UL)) +#define bFM3_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42440430UL)) +#define bFM3_MFT2_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42440434UL)) +#define bFM3_MFT2_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42440438UL)) +#define bFM3_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424404A0UL)) +#define bFM3_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424404A4UL)) +#define bFM3_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424404A8UL)) +#define bFM3_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424404ACUL)) +#define bFM3_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424404B0UL)) +#define bFM3_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424404B4UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42440B00UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42440B04UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42440B08UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42440B0CUL)) +#define bFM3_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42440B10UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42440B14UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42440B18UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42440B1CUL)) +#define bFM3_MFT2_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42440B20UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42440B24UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42440B28UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42440B2CUL)) +#define bFM3_MFT2_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42440B30UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42440B34UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42440B38UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42440B3CUL)) +#define bFM3_MFT2_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42440B80UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42440B84UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42440B88UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42440B8CUL)) +#define bFM3_MFT2_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42440B90UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42440B94UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42440B98UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42440B9CUL)) + +/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42441180UL)) +#define bFM3_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42441184UL)) +#define bFM3_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42441188UL)) +#define bFM3_MFT2_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4244118CUL)) +#define bFM3_MFT2_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42441190UL)) +#define bFM3_MFT2_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42441194UL)) +#define bFM3_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42441198UL)) +#define bFM3_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244119CUL)) +#define bFM3_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424411A0UL)) +#define bFM3_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424411A4UL)) +#define bFM3_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424411A8UL)) +#define bFM3_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424411ACUL)) +#define bFM3_MFT2_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424411B0UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42441200UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42441204UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42441208UL)) +#define bFM3_MFT2_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4244120CUL)) +#define bFM3_MFT2_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42441210UL)) +#define bFM3_MFT2_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42441214UL)) +#define bFM3_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42441218UL)) +#define bFM3_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244121CUL)) +#define bFM3_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42441220UL)) +#define bFM3_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42441224UL)) +#define bFM3_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42441228UL)) +#define bFM3_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244122CUL)) +#define bFM3_MFT2_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42441230UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42441280UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42441284UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42441288UL)) +#define bFM3_MFT2_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4244128CUL)) +#define bFM3_MFT2_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42441290UL)) +#define bFM3_MFT2_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42441294UL)) +#define bFM3_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42441298UL)) +#define bFM3_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244129CUL)) +#define bFM3_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424412A0UL)) +#define bFM3_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424412A4UL)) +#define bFM3_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424412A8UL)) +#define bFM3_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424412ACUL)) +#define bFM3_MFT2_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424412B0UL)) +#define bFM3_MFT2_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42441300UL)) +#define bFM3_MFT2_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42441304UL)) +#define bFM3_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42441310UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42441314UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42441318UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244131CUL)) +#define bFM3_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42441320UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42441324UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42441328UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244132CUL)) +#define bFM3_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42441330UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42441334UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42441338UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244133CUL)) +#define bFM3_MFT2_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42441380UL)) +#define bFM3_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42441384UL)) +#define bFM3_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42441388UL)) +#define bFM3_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244138CUL)) +#define bFM3_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42441390UL)) + +/* Multifunction Timer unit 2 Input Capture Unit registers */ +#define bFM3_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42440C00UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42440C04UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42440C08UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42440C0CUL)) +#define bFM3_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42440C10UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42440C14UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42440C18UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42440C1CUL)) +#define bFM3_MFT2_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42440C20UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42440C24UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42440C28UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42440C2CUL)) +#define bFM3_MFT2_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42440C30UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42440C34UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42440C38UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42440C3CUL)) +#define bFM3_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42440F00UL)) +#define bFM3_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42440F04UL)) +#define bFM3_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42440F08UL)) +#define bFM3_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42440F0CUL)) +#define bFM3_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42440F10UL)) +#define bFM3_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42440F14UL)) +#define bFM3_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42440F18UL)) +#define bFM3_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42440F1CUL)) +#define bFM3_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42440F20UL)) +#define bFM3_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42440F24UL)) +#define bFM3_MFT2_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42440F80UL)) +#define bFM3_MFT2_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42440F84UL)) +#define bFM3_MFT2_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42440F88UL)) +#define bFM3_MFT2_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42440F8CUL)) +#define bFM3_MFT2_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42440F90UL)) +#define bFM3_MFT2_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42440F94UL)) +#define bFM3_MFT2_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42440F98UL)) +#define bFM3_MFT2_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42440F9CUL)) +#define bFM3_MFT2_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42440FA0UL)) +#define bFM3_MFT2_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42440FA4UL)) + +/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define bFM3_MFT2_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42441700UL)) +#define bFM3_MFT2_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42441704UL)) +#define bFM3_MFT2_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42441708UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42441710UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42441714UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42441718UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42441780UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42441784UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42441788UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4244178CUL)) +#define bFM3_MFT2_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42441790UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42441794UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424417A0UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424417A4UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424417A8UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424417ACUL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424417B0UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424417B4UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42441800UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42441804UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42441808UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4244180CUL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42441810UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42441814UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42441820UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42441824UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42441828UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4244182CUL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42441830UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42441834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) +#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) +#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) +#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) +#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) +#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) +#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) +#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) +#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) +#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) +#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) +#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) +#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) +#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) +#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) +#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) +#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) +#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) +#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) +#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) +#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) +#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) +#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) +#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) +#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) +#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) +#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) +#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) +#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) +#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) +#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) +#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) +#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) +#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) +#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) +#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) +#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) +#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) +#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) +#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) +#define bFM3_MFT_PPG_PPGC17_MD0 *((volatile unsigned int*)(0x42486004UL)) +#define bFM3_MFT_PPG_PPGC17_MD1 *((volatile unsigned int*)(0x42486008UL)) +#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) +#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) +#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) +#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) +#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) +#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) +#define bFM3_MFT_PPG_PPGC16_MD0 *((volatile unsigned int*)(0x42486024UL)) +#define bFM3_MFT_PPG_PPGC16_MD1 *((volatile unsigned int*)(0x42486028UL)) +#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) +#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) +#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) +#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) +#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) +#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) +#define bFM3_MFT_PPG_PPGC19_MD0 *((volatile unsigned int*)(0x42486084UL)) +#define bFM3_MFT_PPG_PPGC19_MD1 *((volatile unsigned int*)(0x42486088UL)) +#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) +#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) +#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) +#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) +#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) +#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) +#define bFM3_MFT_PPG_PPGC18_MD0 *((volatile unsigned int*)(0x424860A4UL)) +#define bFM3_MFT_PPG_PPGC18_MD1 *((volatile unsigned int*)(0x424860A8UL)) +#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) +#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) +#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) +#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) +#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) +#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) +#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) +#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) +#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) +#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) +#define bFM3_MFT_PPG_PPGC21_MD0 *((volatile unsigned int*)(0x42486804UL)) +#define bFM3_MFT_PPG_PPGC21_MD1 *((volatile unsigned int*)(0x42486808UL)) +#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) +#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) +#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) +#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) +#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) +#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) +#define bFM3_MFT_PPG_PPGC20_MD0 *((volatile unsigned int*)(0x42486824UL)) +#define bFM3_MFT_PPG_PPGC20_MD1 *((volatile unsigned int*)(0x42486828UL)) +#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) +#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) +#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) +#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) +#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) +#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) +#define bFM3_MFT_PPG_PPGC23_MD0 *((volatile unsigned int*)(0x42486884UL)) +#define bFM3_MFT_PPG_PPGC23_MD1 *((volatile unsigned int*)(0x42486888UL)) +#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) +#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) +#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) +#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) +#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) +#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) +#define bFM3_MFT_PPG_PPGC22_MD0 *((volatile unsigned int*)(0x424868A4UL)) +#define bFM3_MFT_PPG_PPGC22_MD1 *((volatile unsigned int*)(0x424868A8UL)) +#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) +#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) +#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) +#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) +#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) +#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) +#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) +#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) +#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Base Timer 8 PPG registers */ +#define bFM3_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) +#define bFM3_BT8_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) +#define bFM3_BT8_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) +#define bFM3_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM3_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWM registers */ +#define bFM3_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) +#define bFM3_BT8_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) +#define bFM3_BT8_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) +#define bFM3_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM3_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) +#define bFM3_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) +#define bFM3_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 RT registers */ +#define bFM3_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) +#define bFM3_BT8_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) +#define bFM3_BT8_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) +#define bFM3_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM3_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWC registers */ +#define bFM3_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) +#define bFM3_BT8_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) +#define bFM3_BT8_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) +#define bFM3_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM3_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) +#define bFM3_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 9 PPG registers */ +#define bFM3_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) +#define bFM3_BT9_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) +#define bFM3_BT9_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) +#define bFM3_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM3_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWM registers */ +#define bFM3_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) +#define bFM3_BT9_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) +#define bFM3_BT9_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) +#define bFM3_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM3_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) +#define bFM3_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) +#define bFM3_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 RT registers */ +#define bFM3_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) +#define bFM3_BT9_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) +#define bFM3_BT9_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) +#define bFM3_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM3_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWC registers */ +#define bFM3_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) +#define bFM3_BT9_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) +#define bFM3_BT9_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) +#define bFM3_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM3_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) +#define bFM3_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 10 PPG registers */ +#define bFM3_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) +#define bFM3_BT10_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) +#define bFM3_BT10_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) +#define bFM3_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM3_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWM registers */ +#define bFM3_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) +#define bFM3_BT10_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) +#define bFM3_BT10_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) +#define bFM3_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM3_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) +#define bFM3_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) +#define bFM3_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 RT registers */ +#define bFM3_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) +#define bFM3_BT10_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) +#define bFM3_BT10_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) +#define bFM3_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM3_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWC registers */ +#define bFM3_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) +#define bFM3_BT10_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) +#define bFM3_BT10_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) +#define bFM3_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM3_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) +#define bFM3_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 11 PPG registers */ +#define bFM3_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) +#define bFM3_BT11_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) +#define bFM3_BT11_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) +#define bFM3_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM3_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWM registers */ +#define bFM3_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) +#define bFM3_BT11_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) +#define bFM3_BT11_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) +#define bFM3_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM3_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) +#define bFM3_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) +#define bFM3_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 RT registers */ +#define bFM3_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) +#define bFM3_BT11_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) +#define bFM3_BT11_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) +#define bFM3_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM3_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWC registers */ +#define bFM3_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) +#define bFM3_BT11_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) +#define bFM3_BT11_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) +#define bFM3_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM3_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) +#define bFM3_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 12 PPG registers */ +#define bFM3_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) +#define bFM3_BT12_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) +#define bFM3_BT12_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) +#define bFM3_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM3_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWM registers */ +#define bFM3_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) +#define bFM3_BT12_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) +#define bFM3_BT12_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) +#define bFM3_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM3_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) +#define bFM3_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) +#define bFM3_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 RT registers */ +#define bFM3_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) +#define bFM3_BT12_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) +#define bFM3_BT12_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) +#define bFM3_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM3_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWC registers */ +#define bFM3_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) +#define bFM3_BT12_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) +#define bFM3_BT12_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) +#define bFM3_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM3_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) +#define bFM3_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 13 PPG registers */ +#define bFM3_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) +#define bFM3_BT13_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) +#define bFM3_BT13_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) +#define bFM3_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM3_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWM registers */ +#define bFM3_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) +#define bFM3_BT13_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) +#define bFM3_BT13_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) +#define bFM3_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM3_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) +#define bFM3_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) +#define bFM3_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 RT registers */ +#define bFM3_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) +#define bFM3_BT13_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) +#define bFM3_BT13_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) +#define bFM3_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM3_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWC registers */ +#define bFM3_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) +#define bFM3_BT13_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) +#define bFM3_BT13_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) +#define bFM3_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM3_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) +#define bFM3_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 14 PPG registers */ +#define bFM3_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) +#define bFM3_BT14_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) +#define bFM3_BT14_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) +#define bFM3_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM3_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWM registers */ +#define bFM3_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) +#define bFM3_BT14_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) +#define bFM3_BT14_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) +#define bFM3_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM3_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) +#define bFM3_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) +#define bFM3_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 RT registers */ +#define bFM3_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) +#define bFM3_BT14_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) +#define bFM3_BT14_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) +#define bFM3_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM3_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWC registers */ +#define bFM3_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) +#define bFM3_BT14_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) +#define bFM3_BT14_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) +#define bFM3_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM3_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) +#define bFM3_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 15 PPG registers */ +#define bFM3_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) +#define bFM3_BT15_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) +#define bFM3_BT15_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) +#define bFM3_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM3_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWM registers */ +#define bFM3_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) +#define bFM3_BT15_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) +#define bFM3_BT15_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) +#define bFM3_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM3_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) +#define bFM3_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) +#define bFM3_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 RT registers */ +#define bFM3_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) +#define bFM3_BT15_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) +#define bFM3_BT15_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) +#define bFM3_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM3_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWC registers */ +#define bFM3_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) +#define bFM3_BT15_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) +#define bFM3_BT15_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) +#define bFM3_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM3_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) +#define bFM3_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer I/O selector channel 8 - channel 11 registers */ +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) + +/* Base Timer I/O selector channel 12 - channel 15 registers */ +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* Quad position and revolution counter channel 2 registers */ +#define bFM3_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM3_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM3_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM3_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM3_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM3_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM3_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM3_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM3_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM3_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM3_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM3_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM3_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM3_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM3_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM3_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM3_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM3_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM3_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM3_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM3_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM3_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM3_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM3_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM3_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM3_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM3_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM3_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM3_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM3_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM3_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM3_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM3_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM3_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM3_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM3_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM3_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM3_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM3_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM3_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM3_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM3_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM3_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM3_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM3_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM3_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM3_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM3_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM3_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM3_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM3_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM3_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM3_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM3_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM3_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM3_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM3_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM3_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM3_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM3_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM3_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) +#define bFM3_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) +#define bFM3_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) +#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) +#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) +#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) +#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) +#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) +#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) +#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) +#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) +#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) +#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) +#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) +#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) +#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) +#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) +#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) +#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) +#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) +#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) +#define bFM3_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) +#define bFM3_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) +#define bFM3_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) +#define bFM3_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) +#define bFM3_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) +#define bFM3_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) +#define bFM3_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) +#define bFM3_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) +#define bFM3_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) +#define bFM3_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) +#define bFM3_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) +#define bFM3_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) +#define bFM3_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) +#define bFM3_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) +#define bFM3_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) +#define bFM3_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) +#define bFM3_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) +#define bFM3_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) +#define bFM3_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) +#define bFM3_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) +#define bFM3_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) +#define bFM3_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) +#define bFM3_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) +#define bFM3_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) +#define bFM3_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) +#define bFM3_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) +#define bFM3_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) +#define bFM3_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) +#define bFM3_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) +#define bFM3_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) +#define bFM3_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) +#define bFM3_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) +#define bFM3_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) +#define bFM3_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) +#define bFM3_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) +#define bFM3_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) +#define bFM3_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) +#define bFM3_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) +#define bFM3_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) +#define bFM3_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) +#define bFM3_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) +#define bFM3_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) +#define bFM3_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) +#define bFM3_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) +#define bFM3_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_ELVR_LA16 *((volatile unsigned int*)(0x42600200UL)) +#define bFM3_EXTI_ELVR_LB16 *((volatile unsigned int*)(0x42600204UL)) +#define bFM3_EXTI_ELVR_LA17 *((volatile unsigned int*)(0x42600208UL)) +#define bFM3_EXTI_ELVR_LB17 *((volatile unsigned int*)(0x4260020CUL)) +#define bFM3_EXTI_ELVR_LA18 *((volatile unsigned int*)(0x42600210UL)) +#define bFM3_EXTI_ELVR_LB18 *((volatile unsigned int*)(0x42600214UL)) +#define bFM3_EXTI_ELVR_LA19 *((volatile unsigned int*)(0x42600218UL)) +#define bFM3_EXTI_ELVR_LB19 *((volatile unsigned int*)(0x4260021CUL)) +#define bFM3_EXTI_ELVR_LA20 *((volatile unsigned int*)(0x42600220UL)) +#define bFM3_EXTI_ELVR_LB20 *((volatile unsigned int*)(0x42600224UL)) +#define bFM3_EXTI_ELVR_LA21 *((volatile unsigned int*)(0x42600228UL)) +#define bFM3_EXTI_ELVR_LB21 *((volatile unsigned int*)(0x4260022CUL)) +#define bFM3_EXTI_ELVR_LA22 *((volatile unsigned int*)(0x42600230UL)) +#define bFM3_EXTI_ELVR_LB22 *((volatile unsigned int*)(0x42600234UL)) +#define bFM3_EXTI_ELVR_LA23 *((volatile unsigned int*)(0x42600238UL)) +#define bFM3_EXTI_ELVR_LB23 *((volatile unsigned int*)(0x4260023CUL)) +#define bFM3_EXTI_ELVR_LA24 *((volatile unsigned int*)(0x42600240UL)) +#define bFM3_EXTI_ELVR_LB24 *((volatile unsigned int*)(0x42600244UL)) +#define bFM3_EXTI_ELVR_LA25 *((volatile unsigned int*)(0x42600248UL)) +#define bFM3_EXTI_ELVR_LB25 *((volatile unsigned int*)(0x4260024CUL)) +#define bFM3_EXTI_ELVR_LA26 *((volatile unsigned int*)(0x42600250UL)) +#define bFM3_EXTI_ELVR_LB26 *((volatile unsigned int*)(0x42600254UL)) +#define bFM3_EXTI_ELVR_LA27 *((volatile unsigned int*)(0x42600258UL)) +#define bFM3_EXTI_ELVR_LB27 *((volatile unsigned int*)(0x4260025CUL)) +#define bFM3_EXTI_ELVR_LA28 *((volatile unsigned int*)(0x42600260UL)) +#define bFM3_EXTI_ELVR_LB28 *((volatile unsigned int*)(0x42600264UL)) +#define bFM3_EXTI_ELVR_LA29 *((volatile unsigned int*)(0x42600268UL)) +#define bFM3_EXTI_ELVR_LB29 *((volatile unsigned int*)(0x4260026CUL)) +#define bFM3_EXTI_ELVR_LA30 *((volatile unsigned int*)(0x42600270UL)) +#define bFM3_EXTI_ELVR_LB30 *((volatile unsigned int*)(0x42600274UL)) +#define bFM3_EXTI_ELVR_LA31 *((volatile unsigned int*)(0x42600278UL)) +#define bFM3_EXTI_ELVR_LB31 *((volatile unsigned int*)(0x4260027CUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned char*)(0x42620160UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned char*)(0x42620164UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned char*)(0x42620168UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned char*)(0x4262016CUL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned char*)(0x42620170UL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT0 *((volatile unsigned int*)(0x42620420UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT1 *((volatile unsigned int*)(0x42620424UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT2 *((volatile unsigned int*)(0x42620428UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT3 *((volatile unsigned int*)(0x4262042CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT8 *((volatile unsigned int*)(0x42620520UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT9 *((volatile unsigned int*)(0x42620524UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT10 *((volatile unsigned int*)(0x42620528UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT11 *((volatile unsigned int*)(0x4262052CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT12 *((volatile unsigned int*)(0x42620530UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT13 *((volatile unsigned int*)(0x42620534UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT14 *((volatile unsigned int*)(0x42620538UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT15 *((volatile unsigned int*)(0x4262053CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT16 *((volatile unsigned int*)(0x42620540UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT17 *((volatile unsigned int*)(0x42620544UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT18 *((volatile unsigned int*)(0x42620548UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT19 *((volatile unsigned int*)(0x4262054CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT20 *((volatile unsigned int*)(0x42620550UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT21 *((volatile unsigned int*)(0x42620554UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT22 *((volatile unsigned int*)(0x42620558UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT23 *((volatile unsigned int*)(0x4262055CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT2 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT0 *((volatile unsigned int*)(0x426205B8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT1 *((volatile unsigned int*)(0x426205BCUL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT2 *((volatile unsigned int*)(0x426205C0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT3 *((volatile unsigned int*)(0x426205C4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT4 *((volatile unsigned int*)(0x426205C8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT5 *((volatile unsigned int*)(0x426205CCUL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT6 *((volatile unsigned int*)(0x42620E18UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT7 *((volatile unsigned int*)(0x42620E1CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT8 *((volatile unsigned int*)(0x42620E20UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT0 *((volatile unsigned int*)(0x426210B0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT1 *((volatile unsigned int*)(0x426210B4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT2 *((volatile unsigned int*)(0x426210B8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT3 *((volatile unsigned int*)(0x426210BCUL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT4 *((volatile unsigned int*)(0x426210C0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT5 *((volatile unsigned int*)(0x426210C4UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT0 *((volatile unsigned int*)(0x42621120UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT1 *((volatile unsigned int*)(0x42621124UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT2 *((volatile unsigned int*)(0x42621128UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT3 *((volatile unsigned int*)(0x4262112CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT0 *((volatile unsigned int*)(0x426211B0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT1 *((volatile unsigned int*)(0x426211B4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT2 *((volatile unsigned int*)(0x426211B8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT3 *((volatile unsigned int*)(0x426211BCUL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT4 *((volatile unsigned int*)(0x426211C0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT5 *((volatile unsigned int*)(0x426211C4UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_MAC0SBD *((volatile unsigned int*)(0x42621284UL)) +#define bFM3_INTREQ_IRQ32MON_MAC0PMI *((volatile unsigned int*)(0x42621288UL)) +#define bFM3_INTREQ_IRQ32MON_MAC0LPI *((volatile unsigned int*)(0x4262128CUL)) +#define bFM3_INTREQ_IRQ33MON_MAC1SBD *((volatile unsigned int*)(0x42621304UL)) +#define bFM3_INTREQ_IRQ33MON_MAC1PMI *((volatile unsigned int*)(0x42621308UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT0 *((volatile unsigned int*)(0x42621480UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT1 *((volatile unsigned int*)(0x42621484UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT2 *((volatile unsigned int*)(0x42621488UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT3 *((volatile unsigned int*)(0x4262148CUL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT4 *((volatile unsigned int*)(0x42621490UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT0 *((volatile unsigned int*)(0x42621500UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT1 *((volatile unsigned int*)(0x42621504UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT2 *((volatile unsigned int*)(0x42621508UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT3 *((volatile unsigned int*)(0x4262150CUL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT4 *((volatile unsigned int*)(0x42621510UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT5 *((volatile unsigned int*)(0x42621514UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT0 *((volatile unsigned int*)(0x42621980UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT1 *((volatile unsigned int*)(0x42621984UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT2 *((volatile unsigned int*)(0x42621988UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT3 *((volatile unsigned int*)(0x4262198CUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT4 *((volatile unsigned int*)(0x42621990UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT5 *((volatile unsigned int*)(0x42621994UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT6 *((volatile unsigned int*)(0x42621998UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT7 *((volatile unsigned int*)(0x4262199CUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT8 *((volatile unsigned int*)(0x426219A0UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT9 *((volatile unsigned int*)(0x426219A4UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT10 *((volatile unsigned int*)(0x426219A8UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT11 *((volatile unsigned int*)(0x426219ACUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT12 *((volatile unsigned int*)(0x426219B0UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT13 *((volatile unsigned int*)(0x426219B4UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT14 *((volatile unsigned int*)(0x426219B8UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT15 *((volatile unsigned int*)(0x426219BCUL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL10 *((volatile unsigned int*)(0x42624000UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL11 *((volatile unsigned int*)(0x42624004UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL12 *((volatile unsigned int*)(0x42624008UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL13 *((volatile unsigned int*)(0x4262400CUL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL14 *((volatile unsigned int*)(0x42624010UL)) +#define bFM3_INTREQ_DQESEL_ESEL100 *((volatile unsigned int*)(0x42624080UL)) +#define bFM3_INTREQ_DQESEL_ESEL101 *((volatile unsigned int*)(0x42624084UL)) +#define bFM3_INTREQ_DQESEL_ESEL102 *((volatile unsigned int*)(0x42624088UL)) +#define bFM3_INTREQ_DQESEL_ESEL103 *((volatile unsigned int*)(0x4262408CUL)) +#define bFM3_INTREQ_DQESEL_ESEL110 *((volatile unsigned int*)(0x42624090UL)) +#define bFM3_INTREQ_DQESEL_ESEL111 *((volatile unsigned int*)(0x42624094UL)) +#define bFM3_INTREQ_DQESEL_ESEL112 *((volatile unsigned int*)(0x42624098UL)) +#define bFM3_INTREQ_DQESEL_ESEL113 *((volatile unsigned int*)(0x4262409CUL)) +#define bFM3_INTREQ_DQESEL_ESEL240 *((volatile unsigned int*)(0x426240A0UL)) +#define bFM3_INTREQ_DQESEL_ESEL241 *((volatile unsigned int*)(0x426240A4UL)) +#define bFM3_INTREQ_DQESEL_ESEL242 *((volatile unsigned int*)(0x426240A8UL)) +#define bFM3_INTREQ_DQESEL_ESEL243 *((volatile unsigned int*)(0x426240ACUL)) +#define bFM3_INTREQ_DQESEL_ESEL250 *((volatile unsigned int*)(0x426240B0UL)) +#define bFM3_INTREQ_DQESEL_ESEL251 *((volatile unsigned int*)(0x426240B4UL)) +#define bFM3_INTREQ_DQESEL_ESEL252 *((volatile unsigned int*)(0x426240B8UL)) +#define bFM3_INTREQ_DQESEL_ESEL253 *((volatile unsigned int*)(0x426240BCUL)) +#define bFM3_INTREQ_DQESEL_ESEL260 *((volatile unsigned int*)(0x426240C0UL)) +#define bFM3_INTREQ_DQESEL_ESEL261 *((volatile unsigned int*)(0x426240C4UL)) +#define bFM3_INTREQ_DQESEL_ESEL262 *((volatile unsigned int*)(0x426240C8UL)) +#define bFM3_INTREQ_DQESEL_ESEL263 *((volatile unsigned int*)(0x426240CCUL)) +#define bFM3_INTREQ_DQESEL_ESEL270 *((volatile unsigned int*)(0x426240D0UL)) +#define bFM3_INTREQ_DQESEL_ESEL271 *((volatile unsigned int*)(0x426240D4UL)) +#define bFM3_INTREQ_DQESEL_ESEL272 *((volatile unsigned int*)(0x426240D8UL)) +#define bFM3_INTREQ_DQESEL_ESEL273 *((volatile unsigned int*)(0x426240DCUL)) +#define bFM3_INTREQ_DQESEL_ESEL300 *((volatile unsigned int*)(0x426240E0UL)) +#define bFM3_INTREQ_DQESEL_ESEL301 *((volatile unsigned int*)(0x426240E4UL)) +#define bFM3_INTREQ_DQESEL_ESEL302 *((volatile unsigned int*)(0x426240E8UL)) +#define bFM3_INTREQ_DQESEL_ESEL303 *((volatile unsigned int*)(0x426240ECUL)) +#define bFM3_INTREQ_DQESEL_ESEL310 *((volatile unsigned int*)(0x426240F0UL)) +#define bFM3_INTREQ_DQESEL_ESEL311 *((volatile unsigned int*)(0x426240F4UL)) +#define bFM3_INTREQ_DQESEL_ESEL312 *((volatile unsigned int*)(0x426240F8UL)) +#define bFM3_INTREQ_DQESEL_ESEL313 *((volatile unsigned int*)(0x426240FCUL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS10 *((volatile unsigned char*)(0x426241E0UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS11 *((volatile unsigned char*)(0x426241E4UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS12 *((volatile unsigned char*)(0x426241E8UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS13 *((volatile unsigned char*)(0x426241ECUL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS14 *((volatile unsigned char*)(0x426241F0UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR2_P9 *((volatile unsigned int*)(0x42660124UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR7_P5 *((volatile unsigned int*)(0x42660394UL)) +#define bFM3_GPIO_PFR7_P6 *((volatile unsigned int*)(0x42660398UL)) +#define bFM3_GPIO_PFR7_P7 *((volatile unsigned int*)(0x4266039CUL)) +#define bFM3_GPIO_PFR7_P8 *((volatile unsigned int*)(0x426603A0UL)) +#define bFM3_GPIO_PFR7_P9 *((volatile unsigned int*)(0x426603A4UL)) +#define bFM3_GPIO_PFR7_PA *((volatile unsigned int*)(0x426603A8UL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PFR8_P2 *((volatile unsigned int*)(0x42660408UL)) +#define bFM3_GPIO_PFR8_P3 *((volatile unsigned int*)(0x4266040CUL)) +#define bFM3_GPIO_PFRA_P0 *((volatile unsigned int*)(0x42660500UL)) +#define bFM3_GPIO_PFRA_P1 *((volatile unsigned int*)(0x42660504UL)) +#define bFM3_GPIO_PFRA_P2 *((volatile unsigned int*)(0x42660508UL)) +#define bFM3_GPIO_PFRA_P3 *((volatile unsigned int*)(0x4266050CUL)) +#define bFM3_GPIO_PFRA_P4 *((volatile unsigned int*)(0x42660510UL)) +#define bFM3_GPIO_PFRA_P5 *((volatile unsigned int*)(0x42660514UL)) +#define bFM3_GPIO_PFRC_P0 *((volatile unsigned int*)(0x42660600UL)) +#define bFM3_GPIO_PFRC_P1 *((volatile unsigned int*)(0x42660604UL)) +#define bFM3_GPIO_PFRC_P2 *((volatile unsigned int*)(0x42660608UL)) +#define bFM3_GPIO_PFRC_P3 *((volatile unsigned int*)(0x4266060CUL)) +#define bFM3_GPIO_PFRC_P4 *((volatile unsigned int*)(0x42660610UL)) +#define bFM3_GPIO_PFRC_P5 *((volatile unsigned int*)(0x42660614UL)) +#define bFM3_GPIO_PFRC_P6 *((volatile unsigned int*)(0x42660618UL)) +#define bFM3_GPIO_PFRC_P7 *((volatile unsigned int*)(0x4266061CUL)) +#define bFM3_GPIO_PFRC_P8 *((volatile unsigned int*)(0x42660620UL)) +#define bFM3_GPIO_PFRC_P9 *((volatile unsigned int*)(0x42660624UL)) +#define bFM3_GPIO_PFRC_PA *((volatile unsigned int*)(0x42660628UL)) +#define bFM3_GPIO_PFRC_PB *((volatile unsigned int*)(0x4266062CUL)) +#define bFM3_GPIO_PFRC_PC *((volatile unsigned int*)(0x42660630UL)) +#define bFM3_GPIO_PFRC_PD *((volatile unsigned int*)(0x42660634UL)) +#define bFM3_GPIO_PFRC_PE *((volatile unsigned int*)(0x42660638UL)) +#define bFM3_GPIO_PFRC_PF *((volatile unsigned int*)(0x4266063CUL)) +#define bFM3_GPIO_PFRD_P0 *((volatile unsigned int*)(0x42660680UL)) +#define bFM3_GPIO_PFRD_P1 *((volatile unsigned int*)(0x42660684UL)) +#define bFM3_GPIO_PFRD_P2 *((volatile unsigned int*)(0x42660688UL)) +#define bFM3_GPIO_PFRD_P3 *((volatile unsigned int*)(0x4266068CUL)) +#define bFM3_GPIO_PFRE_P0 *((volatile unsigned int*)(0x42660700UL)) +#define bFM3_GPIO_PFRE_P2 *((volatile unsigned int*)(0x42660708UL)) +#define bFM3_GPIO_PFRE_P3 *((volatile unsigned int*)(0x4266070CUL)) +#define bFM3_GPIO_PFRF_P5 *((volatile unsigned int*)(0x42660794UL)) +#define bFM3_GPIO_PFRF_P6 *((volatile unsigned int*)(0x42660798UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR2_P9 *((volatile unsigned int*)(0x42662124UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_PCR7_P5 *((volatile unsigned int*)(0x42662394UL)) +#define bFM3_GPIO_PCR7_P6 *((volatile unsigned int*)(0x42662398UL)) +#define bFM3_GPIO_PCR7_P7 *((volatile unsigned int*)(0x4266239CUL)) +#define bFM3_GPIO_PCR7_P8 *((volatile unsigned int*)(0x426623A0UL)) +#define bFM3_GPIO_PCR7_P9 *((volatile unsigned int*)(0x426623A4UL)) +#define bFM3_GPIO_PCR7_PA *((volatile unsigned int*)(0x426623A8UL)) +#define bFM3_GPIO_PCRA_P0 *((volatile unsigned int*)(0x42662500UL)) +#define bFM3_GPIO_PCRA_P1 *((volatile unsigned int*)(0x42662504UL)) +#define bFM3_GPIO_PCRA_P2 *((volatile unsigned int*)(0x42662508UL)) +#define bFM3_GPIO_PCRA_P3 *((volatile unsigned int*)(0x4266250CUL)) +#define bFM3_GPIO_PCRA_P4 *((volatile unsigned int*)(0x42662510UL)) +#define bFM3_GPIO_PCRA_P5 *((volatile unsigned int*)(0x42662514UL)) +#define bFM3_GPIO_PCRC_P0 *((volatile unsigned int*)(0x42662600UL)) +#define bFM3_GPIO_PCRC_P1 *((volatile unsigned int*)(0x42662604UL)) +#define bFM3_GPIO_PCRC_P2 *((volatile unsigned int*)(0x42662608UL)) +#define bFM3_GPIO_PCRC_P3 *((volatile unsigned int*)(0x4266260CUL)) +#define bFM3_GPIO_PCRC_P4 *((volatile unsigned int*)(0x42662610UL)) +#define bFM3_GPIO_PCRC_P5 *((volatile unsigned int*)(0x42662614UL)) +#define bFM3_GPIO_PCRC_P6 *((volatile unsigned int*)(0x42662618UL)) +#define bFM3_GPIO_PCRC_P7 *((volatile unsigned int*)(0x4266261CUL)) +#define bFM3_GPIO_PCRC_P8 *((volatile unsigned int*)(0x42662620UL)) +#define bFM3_GPIO_PCRC_P9 *((volatile unsigned int*)(0x42662624UL)) +#define bFM3_GPIO_PCRC_PA *((volatile unsigned int*)(0x42662628UL)) +#define bFM3_GPIO_PCRC_PB *((volatile unsigned int*)(0x4266262CUL)) +#define bFM3_GPIO_PCRC_PC *((volatile unsigned int*)(0x42662630UL)) +#define bFM3_GPIO_PCRC_PD *((volatile unsigned int*)(0x42662634UL)) +#define bFM3_GPIO_PCRC_PE *((volatile unsigned int*)(0x42662638UL)) +#define bFM3_GPIO_PCRC_PF *((volatile unsigned int*)(0x4266263CUL)) +#define bFM3_GPIO_PCRD_P0 *((volatile unsigned int*)(0x42662680UL)) +#define bFM3_GPIO_PCRD_P1 *((volatile unsigned int*)(0x42662684UL)) +#define bFM3_GPIO_PCRD_P2 *((volatile unsigned int*)(0x42662688UL)) +#define bFM3_GPIO_PCRD_P3 *((volatile unsigned int*)(0x4266268CUL)) +#define bFM3_GPIO_PCRE_P2 *((volatile unsigned int*)(0x42662708UL)) +#define bFM3_GPIO_PCRE_P3 *((volatile unsigned int*)(0x4266270CUL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR2_P9 *((volatile unsigned int*)(0x42664124UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR7_P5 *((volatile unsigned int*)(0x42664394UL)) +#define bFM3_GPIO_DDR7_P6 *((volatile unsigned int*)(0x42664398UL)) +#define bFM3_GPIO_DDR7_P7 *((volatile unsigned int*)(0x4266439CUL)) +#define bFM3_GPIO_DDR7_P8 *((volatile unsigned int*)(0x426643A0UL)) +#define bFM3_GPIO_DDR7_P9 *((volatile unsigned int*)(0x426643A4UL)) +#define bFM3_GPIO_DDR7_PA *((volatile unsigned int*)(0x426643A8UL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_DDR8_P2 *((volatile unsigned int*)(0x42664408UL)) +#define bFM3_GPIO_DDR8_P3 *((volatile unsigned int*)(0x4266440CUL)) +#define bFM3_GPIO_DDRA_P0 *((volatile unsigned int*)(0x42664500UL)) +#define bFM3_GPIO_DDRA_P1 *((volatile unsigned int*)(0x42664504UL)) +#define bFM3_GPIO_DDRA_P2 *((volatile unsigned int*)(0x42664508UL)) +#define bFM3_GPIO_DDRA_P3 *((volatile unsigned int*)(0x4266450CUL)) +#define bFM3_GPIO_DDRA_P4 *((volatile unsigned int*)(0x42664510UL)) +#define bFM3_GPIO_DDRA_P5 *((volatile unsigned int*)(0x42664514UL)) +#define bFM3_GPIO_DDRC_P0 *((volatile unsigned int*)(0x42664600UL)) +#define bFM3_GPIO_DDRC_P1 *((volatile unsigned int*)(0x42664604UL)) +#define bFM3_GPIO_DDRC_P2 *((volatile unsigned int*)(0x42664608UL)) +#define bFM3_GPIO_DDRC_P3 *((volatile unsigned int*)(0x4266460CUL)) +#define bFM3_GPIO_DDRC_P4 *((volatile unsigned int*)(0x42664610UL)) +#define bFM3_GPIO_DDRC_P5 *((volatile unsigned int*)(0x42664614UL)) +#define bFM3_GPIO_DDRC_P6 *((volatile unsigned int*)(0x42664618UL)) +#define bFM3_GPIO_DDRC_P7 *((volatile unsigned int*)(0x4266461CUL)) +#define bFM3_GPIO_DDRC_P8 *((volatile unsigned int*)(0x42664620UL)) +#define bFM3_GPIO_DDRC_P9 *((volatile unsigned int*)(0x42664624UL)) +#define bFM3_GPIO_DDRC_PA *((volatile unsigned int*)(0x42664628UL)) +#define bFM3_GPIO_DDRC_PB *((volatile unsigned int*)(0x4266462CUL)) +#define bFM3_GPIO_DDRC_PC *((volatile unsigned int*)(0x42664630UL)) +#define bFM3_GPIO_DDRC_PD *((volatile unsigned int*)(0x42664634UL)) +#define bFM3_GPIO_DDRC_PE *((volatile unsigned int*)(0x42664638UL)) +#define bFM3_GPIO_DDRC_PF *((volatile unsigned int*)(0x4266463CUL)) +#define bFM3_GPIO_DDRD_P0 *((volatile unsigned int*)(0x42664680UL)) +#define bFM3_GPIO_DDRD_P1 *((volatile unsigned int*)(0x42664684UL)) +#define bFM3_GPIO_DDRD_P2 *((volatile unsigned int*)(0x42664688UL)) +#define bFM3_GPIO_DDRD_P3 *((volatile unsigned int*)(0x4266468CUL)) +#define bFM3_GPIO_DDRE_P0 *((volatile unsigned int*)(0x42664700UL)) +#define bFM3_GPIO_DDRE_P2 *((volatile unsigned int*)(0x42664708UL)) +#define bFM3_GPIO_DDRE_P3 *((volatile unsigned int*)(0x4266470CUL)) +#define bFM3_GPIO_DDRF_P5 *((volatile unsigned int*)(0x42664794UL)) +#define bFM3_GPIO_DDRF_P6 *((volatile unsigned int*)(0x42664798UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR2_P9 *((volatile unsigned int*)(0x42666124UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR7_P5 *((volatile unsigned int*)(0x42666394UL)) +#define bFM3_GPIO_PDIR7_P6 *((volatile unsigned int*)(0x42666398UL)) +#define bFM3_GPIO_PDIR7_P7 *((volatile unsigned int*)(0x4266639CUL)) +#define bFM3_GPIO_PDIR7_P8 *((volatile unsigned int*)(0x426663A0UL)) +#define bFM3_GPIO_PDIR7_P9 *((volatile unsigned int*)(0x426663A4UL)) +#define bFM3_GPIO_PDIR7_PA *((volatile unsigned int*)(0x426663A8UL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDIR8_P2 *((volatile unsigned int*)(0x42666408UL)) +#define bFM3_GPIO_PDIR8_P3 *((volatile unsigned int*)(0x4266640CUL)) +#define bFM3_GPIO_PDIRA_P0 *((volatile unsigned int*)(0x42666500UL)) +#define bFM3_GPIO_PDIRA_P1 *((volatile unsigned int*)(0x42666504UL)) +#define bFM3_GPIO_PDIRA_P2 *((volatile unsigned int*)(0x42666508UL)) +#define bFM3_GPIO_PDIRA_P3 *((volatile unsigned int*)(0x4266650CUL)) +#define bFM3_GPIO_PDIRA_P4 *((volatile unsigned int*)(0x42666510UL)) +#define bFM3_GPIO_PDIRA_P5 *((volatile unsigned int*)(0x42666514UL)) +#define bFM3_GPIO_PDIRC_P0 *((volatile unsigned int*)(0x42666600UL)) +#define bFM3_GPIO_PDIRC_P1 *((volatile unsigned int*)(0x42666604UL)) +#define bFM3_GPIO_PDIRC_P2 *((volatile unsigned int*)(0x42666608UL)) +#define bFM3_GPIO_PDIRC_P3 *((volatile unsigned int*)(0x4266660CUL)) +#define bFM3_GPIO_PDIRC_P4 *((volatile unsigned int*)(0x42666610UL)) +#define bFM3_GPIO_PDIRC_P5 *((volatile unsigned int*)(0x42666614UL)) +#define bFM3_GPIO_PDIRC_P6 *((volatile unsigned int*)(0x42666618UL)) +#define bFM3_GPIO_PDIRC_P7 *((volatile unsigned int*)(0x4266661CUL)) +#define bFM3_GPIO_PDIRC_P8 *((volatile unsigned int*)(0x42666620UL)) +#define bFM3_GPIO_PDIRC_P9 *((volatile unsigned int*)(0x42666624UL)) +#define bFM3_GPIO_PDIRC_PA *((volatile unsigned int*)(0x42666628UL)) +#define bFM3_GPIO_PDIRC_PB *((volatile unsigned int*)(0x4266662CUL)) +#define bFM3_GPIO_PDIRC_PC *((volatile unsigned int*)(0x42666630UL)) +#define bFM3_GPIO_PDIRC_PD *((volatile unsigned int*)(0x42666634UL)) +#define bFM3_GPIO_PDIRC_PE *((volatile unsigned int*)(0x42666638UL)) +#define bFM3_GPIO_PDIRC_PF *((volatile unsigned int*)(0x4266663CUL)) +#define bFM3_GPIO_PDIRD_P0 *((volatile unsigned int*)(0x42666680UL)) +#define bFM3_GPIO_PDIRD_P1 *((volatile unsigned int*)(0x42666684UL)) +#define bFM3_GPIO_PDIRD_P2 *((volatile unsigned int*)(0x42666688UL)) +#define bFM3_GPIO_PDIRD_P3 *((volatile unsigned int*)(0x4266668CUL)) +#define bFM3_GPIO_PDIRE_P0 *((volatile unsigned int*)(0x42666700UL)) +#define bFM3_GPIO_PDIRE_P2 *((volatile unsigned int*)(0x42666708UL)) +#define bFM3_GPIO_PDIRE_P3 *((volatile unsigned int*)(0x4266670CUL)) +#define bFM3_GPIO_PDIRF_P5 *((volatile unsigned int*)(0x42666794UL)) +#define bFM3_GPIO_PDIRF_P6 *((volatile unsigned int*)(0x42666798UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR2_P9 *((volatile unsigned int*)(0x42668124UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR7_P5 *((volatile unsigned int*)(0x42668394UL)) +#define bFM3_GPIO_PDOR7_P6 *((volatile unsigned int*)(0x42668398UL)) +#define bFM3_GPIO_PDOR7_P7 *((volatile unsigned int*)(0x4266839CUL)) +#define bFM3_GPIO_PDOR7_P8 *((volatile unsigned int*)(0x426683A0UL)) +#define bFM3_GPIO_PDOR7_P9 *((volatile unsigned int*)(0x426683A4UL)) +#define bFM3_GPIO_PDOR7_PA *((volatile unsigned int*)(0x426683A8UL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_PDOR8_P2 *((volatile unsigned int*)(0x42668408UL)) +#define bFM3_GPIO_PDOR8_P3 *((volatile unsigned int*)(0x4266840CUL)) +#define bFM3_GPIO_PDORA_P0 *((volatile unsigned int*)(0x42668500UL)) +#define bFM3_GPIO_PDORA_P1 *((volatile unsigned int*)(0x42668504UL)) +#define bFM3_GPIO_PDORA_P2 *((volatile unsigned int*)(0x42668508UL)) +#define bFM3_GPIO_PDORA_P3 *((volatile unsigned int*)(0x4266850CUL)) +#define bFM3_GPIO_PDORA_P4 *((volatile unsigned int*)(0x42668510UL)) +#define bFM3_GPIO_PDORA_P5 *((volatile unsigned int*)(0x42668514UL)) +#define bFM3_GPIO_PDORC_P0 *((volatile unsigned int*)(0x42668600UL)) +#define bFM3_GPIO_PDORC_P1 *((volatile unsigned int*)(0x42668604UL)) +#define bFM3_GPIO_PDORC_P2 *((volatile unsigned int*)(0x42668608UL)) +#define bFM3_GPIO_PDORC_P3 *((volatile unsigned int*)(0x4266860CUL)) +#define bFM3_GPIO_PDORC_P4 *((volatile unsigned int*)(0x42668610UL)) +#define bFM3_GPIO_PDORC_P5 *((volatile unsigned int*)(0x42668614UL)) +#define bFM3_GPIO_PDORC_P6 *((volatile unsigned int*)(0x42668618UL)) +#define bFM3_GPIO_PDORC_P7 *((volatile unsigned int*)(0x4266861CUL)) +#define bFM3_GPIO_PDORC_P8 *((volatile unsigned int*)(0x42668620UL)) +#define bFM3_GPIO_PDORC_P9 *((volatile unsigned int*)(0x42668624UL)) +#define bFM3_GPIO_PDORC_PA *((volatile unsigned int*)(0x42668628UL)) +#define bFM3_GPIO_PDORC_PB *((volatile unsigned int*)(0x4266862CUL)) +#define bFM3_GPIO_PDORC_PC *((volatile unsigned int*)(0x42668630UL)) +#define bFM3_GPIO_PDORC_PD *((volatile unsigned int*)(0x42668634UL)) +#define bFM3_GPIO_PDORC_PE *((volatile unsigned int*)(0x42668638UL)) +#define bFM3_GPIO_PDORC_PF *((volatile unsigned int*)(0x4266863CUL)) +#define bFM3_GPIO_PDORD_P0 *((volatile unsigned int*)(0x42668680UL)) +#define bFM3_GPIO_PDORD_P1 *((volatile unsigned int*)(0x42668684UL)) +#define bFM3_GPIO_PDORD_P2 *((volatile unsigned int*)(0x42668688UL)) +#define bFM3_GPIO_PDORD_P3 *((volatile unsigned int*)(0x4266868CUL)) +#define bFM3_GPIO_PDORE_P0 *((volatile unsigned int*)(0x42668700UL)) +#define bFM3_GPIO_PDORE_P2 *((volatile unsigned int*)(0x42668708UL)) +#define bFM3_GPIO_PDORE_P3 *((volatile unsigned int*)(0x4266870CUL)) +#define bFM3_GPIO_PDORF_P5 *((volatile unsigned int*)(0x42668794UL)) +#define bFM3_GPIO_PDORF_P6 *((volatile unsigned int*)(0x42668798UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_AN10 *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_AN11 *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_AN12 *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AN13 *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_AN14 *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_AN15 *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_ADE_AN24 *((volatile unsigned int*)(0x4266A060UL)) +#define bFM3_GPIO_ADE_AN25 *((volatile unsigned int*)(0x4266A064UL)) +#define bFM3_GPIO_ADE_AN26 *((volatile unsigned int*)(0x4266A068UL)) +#define bFM3_GPIO_ADE_AN27 *((volatile unsigned int*)(0x4266A06CUL)) +#define bFM3_GPIO_ADE_AN28 *((volatile unsigned int*)(0x4266A070UL)) +#define bFM3_GPIO_ADE_AN29 *((volatile unsigned int*)(0x4266A074UL)) +#define bFM3_GPIO_ADE_AN30 *((volatile unsigned int*)(0x4266A078UL)) +#define bFM3_GPIO_ADE_AN31 *((volatile unsigned int*)(0x4266A07CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_MAINXC *((volatile unsigned int*)(0x4266B008UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x4266B014UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x4266C008UL)) +#define bFM3_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x4266C018UL)) +#define bFM3_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x4266C01CUL)) +#define bFM3_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x4266C034UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x4266C180UL)) +#define bFM3_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x4266C184UL)) +#define bFM3_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x4266C188UL)) +#define bFM3_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x4266C18CUL)) +#define bFM3_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x4266C190UL)) +#define bFM3_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x4266C194UL)) +#define bFM3_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x4266C198UL)) +#define bFM3_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x4266C19CUL)) +#define bFM3_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x4266C1A0UL)) +#define bFM3_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x4266C1A4UL)) +#define bFM3_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x4266C1A8UL)) +#define bFM3_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x4266C1ACUL)) +#define bFM3_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x4266C1B0UL)) +#define bFM3_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x4266C1C0UL)) +#define bFM3_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x4266C1C4UL)) +#define bFM3_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x4266C1C8UL)) +#define bFM3_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x4266C1CCUL)) +#define bFM3_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x4266C1D0UL)) +#define bFM3_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x4266C1D4UL)) +#define bFM3_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x4266C1D8UL)) +#define bFM3_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x4266C1DCUL)) +#define bFM3_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x4266C1E0UL)) +#define bFM3_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x4266C1E4UL)) +#define bFM3_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x4266C1E8UL)) +#define bFM3_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x4266C1ECUL)) +#define bFM3_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x4266C1F0UL)) +#define bFM3_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x4266C1F4UL)) +#define bFM3_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x4266C1F8UL)) +#define bFM3_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x4266C1FCUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x4266C580UL)) +#define bFM3_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x4266C584UL)) +#define bFM3_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x4266C588UL)) +#define bFM3_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x4266C58CUL)) +#define bFM3_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x4266C590UL)) +#define bFM3_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x4266C594UL)) +#define bFM3_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x4266C598UL)) +#define bFM3_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x4266C59CUL)) +#define bFM3_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x4266C5A0UL)) +#define bFM3_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x4266C5A4UL)) +#define bFM3_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x4266C5A8UL)) +#define bFM3_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x4266C5ACUL)) +#define bFM3_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x4266C5B0UL)) +#define bFM3_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x4266C5B4UL)) +#define bFM3_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x4266C5B8UL)) +#define bFM3_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x4266C5BCUL)) +#define bFM3_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x4266C5C0UL)) +#define bFM3_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x4266C5C4UL)) +#define bFM3_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x4266C5C8UL)) +#define bFM3_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x4266C5CCUL)) +#define bFM3_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x4266C5D0UL)) +#define bFM3_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x4266C5D4UL)) +#define bFM3_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x4266C5D8UL)) +#define bFM3_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x4266C5DCUL)) +#define bFM3_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x4266C5E0UL)) +#define bFM3_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x4266C5E4UL)) +#define bFM3_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x4266C608UL)) +#define bFM3_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x4266C60CUL)) +#define bFM3_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x4266C610UL)) +#define bFM3_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x4266C614UL)) +#define bFM3_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x4266C620UL)) +#define bFM3_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x4266C624UL)) +#define bFM3_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x4266C628UL)) +#define bFM3_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x4266C62CUL)) +#define bFM3_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x4266C630UL)) +#define bFM3_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x4266C634UL)) +#define bFM3_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x4266C648UL)) +#define bFM3_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x4266C64CUL)) +#define bFM3_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x4266C650UL)) +#define bFM3_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x4266C654UL)) +#define bFM3_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x4266C660UL)) +#define bFM3_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x4266C664UL)) +#define bFM3_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x4266C668UL)) +#define bFM3_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x4266C66CUL)) +#define bFM3_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x4266C670UL)) +#define bFM3_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x4266C674UL)) +#define bFM3_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x4266C688UL)) +#define bFM3_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x4266C68CUL)) +#define bFM3_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x4266C690UL)) +#define bFM3_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x4266C694UL)) +#define bFM3_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x4266C6A0UL)) +#define bFM3_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x4266C6A4UL)) +#define bFM3_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x4266C6A8UL)) +#define bFM3_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x4266C6ACUL)) +#define bFM3_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x4266C6B0UL)) +#define bFM3_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x4266C6B4UL)) +#define bFM3_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x4266C6C8UL)) +#define bFM3_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x4266C6CCUL)) +#define bFM3_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x4266C6D0UL)) +#define bFM3_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x4266C6D4UL)) +#define bFM3_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x4266C6E0UL)) +#define bFM3_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x4266C6E4UL)) +#define bFM3_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x4266C6E8UL)) +#define bFM3_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x4266C6ECUL)) +#define bFM3_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x4266C6F0UL)) +#define bFM3_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x4266C6F4UL)) +#define bFM3_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x4266C700UL)) +#define bFM3_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x4266C704UL)) +#define bFM3_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x4266C708UL)) +#define bFM3_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x4266C70CUL)) +#define bFM3_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x4266C710UL)) +#define bFM3_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x4266C714UL)) +#define bFM3_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x4266C748UL)) +#define bFM3_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x4266C74CUL)) +#define bFM3_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x4266C750UL)) +#define bFM3_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x4266C754UL)) +#define bFM3_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x4266C758UL)) +#define bFM3_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x4266C75CUL)) +#define bFM3_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x4266C760UL)) +#define bFM3_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x4266C764UL)) +#define bFM3_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x4266C768UL)) +#define bFM3_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x4266C76CUL)) +#define bFM3_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x4266C770UL)) +#define bFM3_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x4266C774UL)) +#define bFM3_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x4266C780UL)) +#define bFM3_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x4266C784UL)) +#define bFM3_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x4266C788UL)) +#define bFM3_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x4266C78CUL)) +#define bFM3_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x4266C790UL)) +#define bFM3_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x4266C794UL)) +#define bFM3_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x4266C798UL)) +#define bFM3_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x4266C79CUL)) +#define bFM3_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x4266C7A0UL)) +#define bFM3_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x4266C7A4UL)) +#define bFM3_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x4266C7A8UL)) +#define bFM3_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x4266C7ACUL)) +#define bFM3_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x4266C7B0UL)) +#define bFM3_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x4266C7B4UL)) +#define bFM3_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x4266C7B8UL)) +#define bFM3_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x4266C7BCUL)) +#define bFM3_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x4266C7C0UL)) +#define bFM3_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x4266C7C4UL)) +#define bFM3_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x4266C7C8UL)) +#define bFM3_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x4266C7CCUL)) +#define bFM3_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x4266C7D0UL)) +#define bFM3_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x4266C7D4UL)) +#define bFM3_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x4266C7D8UL)) +#define bFM3_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x4266C7DCUL)) +#define bFM3_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x4266C7E0UL)) +#define bFM3_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x4266C7E4UL)) +#define bFM3_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x4266C7E8UL)) +#define bFM3_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x4266C7ECUL)) +#define bFM3_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x4266C7F0UL)) +#define bFM3_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x4266C7F4UL)) +#define bFM3_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x4266C7F8UL)) +#define bFM3_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x4266C7FCUL)) +#define bFM3_GPIO_PZR0_P0 *((volatile unsigned int*)(0x4266E000UL)) +#define bFM3_GPIO_PZR0_P1 *((volatile unsigned int*)(0x4266E004UL)) +#define bFM3_GPIO_PZR0_P2 *((volatile unsigned int*)(0x4266E008UL)) +#define bFM3_GPIO_PZR0_P3 *((volatile unsigned int*)(0x4266E00CUL)) +#define bFM3_GPIO_PZR0_P4 *((volatile unsigned int*)(0x4266E010UL)) +#define bFM3_GPIO_PZR0_P5 *((volatile unsigned int*)(0x4266E014UL)) +#define bFM3_GPIO_PZR0_P6 *((volatile unsigned int*)(0x4266E018UL)) +#define bFM3_GPIO_PZR0_P7 *((volatile unsigned int*)(0x4266E01CUL)) +#define bFM3_GPIO_PZR0_P8 *((volatile unsigned int*)(0x4266E020UL)) +#define bFM3_GPIO_PZR0_P9 *((volatile unsigned int*)(0x4266E024UL)) +#define bFM3_GPIO_PZR1_P0 *((volatile unsigned int*)(0x4266E080UL)) +#define bFM3_GPIO_PZR1_P1 *((volatile unsigned int*)(0x4266E084UL)) +#define bFM3_GPIO_PZR1_P2 *((volatile unsigned int*)(0x4266E088UL)) +#define bFM3_GPIO_PZR1_P3 *((volatile unsigned int*)(0x4266E08CUL)) +#define bFM3_GPIO_PZR1_P4 *((volatile unsigned int*)(0x4266E090UL)) +#define bFM3_GPIO_PZR1_P5 *((volatile unsigned int*)(0x4266E094UL)) +#define bFM3_GPIO_PZR1_P6 *((volatile unsigned int*)(0x4266E098UL)) +#define bFM3_GPIO_PZR1_P7 *((volatile unsigned int*)(0x4266E09CUL)) +#define bFM3_GPIO_PZR1_P8 *((volatile unsigned int*)(0x4266E0A0UL)) +#define bFM3_GPIO_PZR1_P9 *((volatile unsigned int*)(0x4266E0A4UL)) +#define bFM3_GPIO_PZR1_PA *((volatile unsigned int*)(0x4266E0A8UL)) +#define bFM3_GPIO_PZR1_PB *((volatile unsigned int*)(0x4266E0ACUL)) +#define bFM3_GPIO_PZR1_PC *((volatile unsigned int*)(0x4266E0B0UL)) +#define bFM3_GPIO_PZR1_PD *((volatile unsigned int*)(0x4266E0B4UL)) +#define bFM3_GPIO_PZR1_PE *((volatile unsigned int*)(0x4266E0B8UL)) +#define bFM3_GPIO_PZR1_PF *((volatile unsigned int*)(0x4266E0BCUL)) +#define bFM3_GPIO_PZR2_P0 *((volatile unsigned int*)(0x4266E100UL)) +#define bFM3_GPIO_PZR2_P1 *((volatile unsigned int*)(0x4266E104UL)) +#define bFM3_GPIO_PZR2_P2 *((volatile unsigned int*)(0x4266E108UL)) +#define bFM3_GPIO_PZR2_P3 *((volatile unsigned int*)(0x4266E10CUL)) +#define bFM3_GPIO_PZR2_P4 *((volatile unsigned int*)(0x4266E110UL)) +#define bFM3_GPIO_PZR2_P5 *((volatile unsigned int*)(0x4266E114UL)) +#define bFM3_GPIO_PZR2_P6 *((volatile unsigned int*)(0x4266E118UL)) +#define bFM3_GPIO_PZR2_P7 *((volatile unsigned int*)(0x4266E11CUL)) +#define bFM3_GPIO_PZR2_P8 *((volatile unsigned int*)(0x4266E120UL)) +#define bFM3_GPIO_PZR2_P9 *((volatile unsigned int*)(0x4266E124UL)) +#define bFM3_GPIO_PZR3_P6 *((volatile unsigned int*)(0x4266E198UL)) +#define bFM3_GPIO_PZR3_P7 *((volatile unsigned int*)(0x4266E19CUL)) +#define bFM3_GPIO_PZR3_P8 *((volatile unsigned int*)(0x4266E1A0UL)) +#define bFM3_GPIO_PZR3_P9 *((volatile unsigned int*)(0x4266E1A4UL)) +#define bFM3_GPIO_PZR3_PA *((volatile unsigned int*)(0x4266E1A8UL)) +#define bFM3_GPIO_PZR3_PB *((volatile unsigned int*)(0x4266E1ACUL)) +#define bFM3_GPIO_PZR3_PC *((volatile unsigned int*)(0x4266E1B0UL)) +#define bFM3_GPIO_PZR3_PD *((volatile unsigned int*)(0x4266E1B4UL)) +#define bFM3_GPIO_PZR3_PE *((volatile unsigned int*)(0x4266E1B8UL)) +#define bFM3_GPIO_PZR3_PF *((volatile unsigned int*)(0x4266E1BCUL)) +#define bFM3_GPIO_PZR4_P0 *((volatile unsigned int*)(0x4266E200UL)) +#define bFM3_GPIO_PZR4_P1 *((volatile unsigned int*)(0x4266E204UL)) +#define bFM3_GPIO_PZR4_P2 *((volatile unsigned int*)(0x4266E208UL)) +#define bFM3_GPIO_PZR4_P3 *((volatile unsigned int*)(0x4266E20CUL)) +#define bFM3_GPIO_PZR4_P4 *((volatile unsigned int*)(0x4266E210UL)) +#define bFM3_GPIO_PZR4_P5 *((volatile unsigned int*)(0x4266E214UL)) +#define bFM3_GPIO_PZR4_P6 *((volatile unsigned int*)(0x4266E218UL)) +#define bFM3_GPIO_PZR4_P7 *((volatile unsigned int*)(0x4266E21CUL)) +#define bFM3_GPIO_PZR4_P8 *((volatile unsigned int*)(0x4266E220UL)) +#define bFM3_GPIO_PZR4_P9 *((volatile unsigned int*)(0x4266E224UL)) +#define bFM3_GPIO_PZR4_PA *((volatile unsigned int*)(0x4266E228UL)) +#define bFM3_GPIO_PZR4_PB *((volatile unsigned int*)(0x4266E22CUL)) +#define bFM3_GPIO_PZR4_PC *((volatile unsigned int*)(0x4266E230UL)) +#define bFM3_GPIO_PZR4_PD *((volatile unsigned int*)(0x4266E234UL)) +#define bFM3_GPIO_PZR4_PE *((volatile unsigned int*)(0x4266E238UL)) +#define bFM3_GPIO_PZR5_P0 *((volatile unsigned int*)(0x4266E280UL)) +#define bFM3_GPIO_PZR5_P1 *((volatile unsigned int*)(0x4266E284UL)) +#define bFM3_GPIO_PZR5_P2 *((volatile unsigned int*)(0x4266E288UL)) +#define bFM3_GPIO_PZR5_P3 *((volatile unsigned int*)(0x4266E28CUL)) +#define bFM3_GPIO_PZR5_P4 *((volatile unsigned int*)(0x4266E290UL)) +#define bFM3_GPIO_PZR5_P5 *((volatile unsigned int*)(0x4266E294UL)) +#define bFM3_GPIO_PZR5_P6 *((volatile unsigned int*)(0x4266E298UL)) +#define bFM3_GPIO_PZR5_P7 *((volatile unsigned int*)(0x4266E29CUL)) +#define bFM3_GPIO_PZR5_P8 *((volatile unsigned int*)(0x4266E2A0UL)) +#define bFM3_GPIO_PZR5_P9 *((volatile unsigned int*)(0x4266E2A4UL)) +#define bFM3_GPIO_PZR5_PA *((volatile unsigned int*)(0x4266E2A8UL)) +#define bFM3_GPIO_PZR5_PB *((volatile unsigned int*)(0x4266E2ACUL)) +#define bFM3_GPIO_PZR6_P0 *((volatile unsigned int*)(0x4266E300UL)) +#define bFM3_GPIO_PZR6_P1 *((volatile unsigned int*)(0x4266E304UL)) +#define bFM3_GPIO_PZR6_P2 *((volatile unsigned int*)(0x4266E308UL)) +#define bFM3_GPIO_PZR7_P0 *((volatile unsigned int*)(0x4266E380UL)) +#define bFM3_GPIO_PZR7_P1 *((volatile unsigned int*)(0x4266E384UL)) +#define bFM3_GPIO_PZR7_P2 *((volatile unsigned int*)(0x4266E388UL)) +#define bFM3_GPIO_PZR7_P3 *((volatile unsigned int*)(0x4266E38CUL)) +#define bFM3_GPIO_PZR7_P4 *((volatile unsigned int*)(0x4266E390UL)) +#define bFM3_GPIO_PZR7_P5 *((volatile unsigned int*)(0x4266E394UL)) +#define bFM3_GPIO_PZR7_P6 *((volatile unsigned int*)(0x4266E398UL)) +#define bFM3_GPIO_PZR7_P7 *((volatile unsigned int*)(0x4266E39CUL)) +#define bFM3_GPIO_PZR7_P8 *((volatile unsigned int*)(0x4266E3A0UL)) +#define bFM3_GPIO_PZR7_P9 *((volatile unsigned int*)(0x4266E3A4UL)) +#define bFM3_GPIO_PZR7_PA *((volatile unsigned int*)(0x4266E3A8UL)) +#define bFM3_GPIO_PZR8_P0 *((volatile unsigned int*)(0x4266E400UL)) +#define bFM3_GPIO_PZR8_P1 *((volatile unsigned int*)(0x4266E404UL)) +#define bFM3_GPIO_PZR8_P2 *((volatile unsigned int*)(0x4266E408UL)) +#define bFM3_GPIO_PZR8_P3 *((volatile unsigned int*)(0x4266E40CUL)) +#define bFM3_GPIO_PZRA_P0 *((volatile unsigned int*)(0x4266E500UL)) +#define bFM3_GPIO_PZRA_P1 *((volatile unsigned int*)(0x4266E504UL)) +#define bFM3_GPIO_PZRA_P2 *((volatile unsigned int*)(0x4266E508UL)) +#define bFM3_GPIO_PZRA_P3 *((volatile unsigned int*)(0x4266E50CUL)) +#define bFM3_GPIO_PZRA_P4 *((volatile unsigned int*)(0x4266E510UL)) +#define bFM3_GPIO_PZRA_P5 *((volatile unsigned int*)(0x4266E514UL)) +#define bFM3_GPIO_PZRC_P0 *((volatile unsigned int*)(0x4266E600UL)) +#define bFM3_GPIO_PZRC_P1 *((volatile unsigned int*)(0x4266E604UL)) +#define bFM3_GPIO_PZRC_P2 *((volatile unsigned int*)(0x4266E608UL)) +#define bFM3_GPIO_PZRC_P3 *((volatile unsigned int*)(0x4266E60CUL)) +#define bFM3_GPIO_PZRC_P4 *((volatile unsigned int*)(0x4266E610UL)) +#define bFM3_GPIO_PZRC_P5 *((volatile unsigned int*)(0x4266E614UL)) +#define bFM3_GPIO_PZRC_P6 *((volatile unsigned int*)(0x4266E618UL)) +#define bFM3_GPIO_PZRC_P7 *((volatile unsigned int*)(0x4266E61CUL)) +#define bFM3_GPIO_PZRC_P8 *((volatile unsigned int*)(0x4266E620UL)) +#define bFM3_GPIO_PZRC_P9 *((volatile unsigned int*)(0x4266E624UL)) +#define bFM3_GPIO_PZRC_PA *((volatile unsigned int*)(0x4266E628UL)) +#define bFM3_GPIO_PZRC_PB *((volatile unsigned int*)(0x4266E62CUL)) +#define bFM3_GPIO_PZRC_PC *((volatile unsigned int*)(0x4266E630UL)) +#define bFM3_GPIO_PZRC_PD *((volatile unsigned int*)(0x4266E634UL)) +#define bFM3_GPIO_PZRC_PE *((volatile unsigned int*)(0x4266E638UL)) +#define bFM3_GPIO_PZRC_PF *((volatile unsigned int*)(0x4266E63CUL)) +#define bFM3_GPIO_PZRD_P0 *((volatile unsigned int*)(0x4266E680UL)) +#define bFM3_GPIO_PZRD_P1 *((volatile unsigned int*)(0x4266E684UL)) +#define bFM3_GPIO_PZRD_P2 *((volatile unsigned int*)(0x4266E688UL)) +#define bFM3_GPIO_PZRD_P3 *((volatile unsigned int*)(0x4266E68CUL)) +#define bFM3_GPIO_PZRE_P0 *((volatile unsigned int*)(0x4266E700UL)) +#define bFM3_GPIO_PZRE_P2 *((volatile unsigned int*)(0x4266E708UL)) +#define bFM3_GPIO_PZRE_P3 *((volatile unsigned int*)(0x4266E70CUL)) +#define bFM3_GPIO_PZRF_P5 *((volatile unsigned int*)(0x4266E794UL)) +#define bFM3_GPIO_PZRF_P6 *((volatile unsigned int*)(0x4266E798UL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBETHERNETCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) +#define bFM3_USBETHERNETCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) +#define bFM3_USBETHERNETCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) +#define bFM3_USBETHERNETCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) +#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBETHERNETCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) +#define bFM3_USBETHERNETCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) +#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) +#define bFM3_USBETHERNETCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) +#define bFM3_USBETHERNETCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* MFS Noise Filter Control registers */ +#define bFM3_MFS_NFC_I2CDNF_I2CDNF00 *((volatile unsigned int*)(0x42710000UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF01 *((volatile unsigned int*)(0x42710004UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF10 *((volatile unsigned int*)(0x42710008UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF11 *((volatile unsigned int*)(0x4271000CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF20 *((volatile unsigned int*)(0x42710010UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF21 *((volatile unsigned int*)(0x42710014UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF30 *((volatile unsigned int*)(0x42710018UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF31 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF40 *((volatile unsigned int*)(0x42710020UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF41 *((volatile unsigned int*)(0x42710024UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF50 *((volatile unsigned int*)(0x42710028UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF51 *((volatile unsigned int*)(0x4271002CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF60 *((volatile unsigned int*)(0x42710030UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF61 *((volatile unsigned int*)(0x42710034UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF70 *((volatile unsigned int*)(0x42710038UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF71 *((volatile unsigned int*)(0x4271003CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_RDY *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE0_SHRTDOUT *((volatile unsigned int*)(0x427E001CUL)) +#define bFM3_EXBUS_MODE0_MPXMODE *((volatile unsigned int*)(0x427E0020UL)) +#define bFM3_EXBUS_MODE0_ALEINV *((volatile unsigned int*)(0x427E0024UL)) +#define bFM3_EXBUS_MODE0_MPXDOFF *((volatile unsigned int*)(0x427E002CUL)) +#define bFM3_EXBUS_MODE0_MPXCSOF *((volatile unsigned int*)(0x427E0030UL)) +#define bFM3_EXBUS_MODE0_MOEXEUP *((volatile unsigned int*)(0x427E0034UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_RDY *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE1_SHRTDOUT *((volatile unsigned int*)(0x427E009CUL)) +#define bFM3_EXBUS_MODE1_MPXMODE *((volatile unsigned int*)(0x427E00A0UL)) +#define bFM3_EXBUS_MODE1_ALEINV *((volatile unsigned int*)(0x427E00A4UL)) +#define bFM3_EXBUS_MODE1_MPXDOFF *((volatile unsigned int*)(0x427E00ACUL)) +#define bFM3_EXBUS_MODE1_MPXCSOF *((volatile unsigned int*)(0x427E00B0UL)) +#define bFM3_EXBUS_MODE1_MOEXEUP *((volatile unsigned int*)(0x427E00B4UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_RDY *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE2_SHRTDOUT *((volatile unsigned int*)(0x427E011CUL)) +#define bFM3_EXBUS_MODE2_MPXMODE *((volatile unsigned int*)(0x427E0120UL)) +#define bFM3_EXBUS_MODE2_ALEINV *((volatile unsigned int*)(0x427E0124UL)) +#define bFM3_EXBUS_MODE2_MPXDOFF *((volatile unsigned int*)(0x427E012CUL)) +#define bFM3_EXBUS_MODE2_MPXCSOF *((volatile unsigned int*)(0x427E0130UL)) +#define bFM3_EXBUS_MODE2_MOEXEUP *((volatile unsigned int*)(0x427E0134UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_RDY *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE3_SHRTDOUT *((volatile unsigned int*)(0x427E019CUL)) +#define bFM3_EXBUS_MODE3_MPXMODE *((volatile unsigned int*)(0x427E01A0UL)) +#define bFM3_EXBUS_MODE3_ALEINV *((volatile unsigned int*)(0x427E01A4UL)) +#define bFM3_EXBUS_MODE3_MPXDOFF *((volatile unsigned int*)(0x427E01ACUL)) +#define bFM3_EXBUS_MODE3_MPXCSOF *((volatile unsigned int*)(0x427E01B0UL)) +#define bFM3_EXBUS_MODE3_MOEXEUP *((volatile unsigned int*)(0x427E01B4UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_RDY *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE4_SHRTDOUT *((volatile unsigned int*)(0x427E021CUL)) +#define bFM3_EXBUS_MODE4_MPXMODE *((volatile unsigned int*)(0x427E0220UL)) +#define bFM3_EXBUS_MODE4_ALEINV *((volatile unsigned int*)(0x427E0224UL)) +#define bFM3_EXBUS_MODE4_MPXDOFF *((volatile unsigned int*)(0x427E022CUL)) +#define bFM3_EXBUS_MODE4_MPXCSOF *((volatile unsigned int*)(0x427E0230UL)) +#define bFM3_EXBUS_MODE4_MOEXEUP *((volatile unsigned int*)(0x427E0234UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_RDY *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE5_SHRTDOUT *((volatile unsigned int*)(0x427E029CUL)) +#define bFM3_EXBUS_MODE5_MPXMODE *((volatile unsigned int*)(0x427E02A0UL)) +#define bFM3_EXBUS_MODE5_ALEINV *((volatile unsigned int*)(0x427E02A4UL)) +#define bFM3_EXBUS_MODE5_MPXDOFF *((volatile unsigned int*)(0x427E02ACUL)) +#define bFM3_EXBUS_MODE5_MPXCSOF *((volatile unsigned int*)(0x427E02B0UL)) +#define bFM3_EXBUS_MODE5_MOEXEUP *((volatile unsigned int*)(0x427E02B4UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_RDY *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE6_SHRTDOUT *((volatile unsigned int*)(0x427E031CUL)) +#define bFM3_EXBUS_MODE6_MPXMODE *((volatile unsigned int*)(0x427E0320UL)) +#define bFM3_EXBUS_MODE6_ALEINV *((volatile unsigned int*)(0x427E0324UL)) +#define bFM3_EXBUS_MODE6_MPXDOFF *((volatile unsigned int*)(0x427E032CUL)) +#define bFM3_EXBUS_MODE6_MPXCSOF *((volatile unsigned int*)(0x427E0330UL)) +#define bFM3_EXBUS_MODE6_MOEXEUP *((volatile unsigned int*)(0x427E0334UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_RDY *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_MODE7_SHRTDOUT *((volatile unsigned int*)(0x427E039CUL)) +#define bFM3_EXBUS_MODE7_MPXMODE *((volatile unsigned int*)(0x427E03A0UL)) +#define bFM3_EXBUS_MODE7_ALEINV *((volatile unsigned int*)(0x427E03A4UL)) +#define bFM3_EXBUS_MODE7_MPXDOFF *((volatile unsigned int*)(0x427E03ACUL)) +#define bFM3_EXBUS_MODE7_MPXCSOF *((volatile unsigned int*)(0x427E03B0UL)) +#define bFM3_EXBUS_MODE7_MOEXEUP *((volatile unsigned int*)(0x427E03B4UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) +#define bFM3_EXBUS_ATIM0_ALC0 *((volatile unsigned int*)(0x427E0C00UL)) +#define bFM3_EXBUS_ATIM0_ALC1 *((volatile unsigned int*)(0x427E0C04UL)) +#define bFM3_EXBUS_ATIM0_ALC2 *((volatile unsigned int*)(0x427E0C08UL)) +#define bFM3_EXBUS_ATIM0_ALC3 *((volatile unsigned int*)(0x427E0C0CUL)) +#define bFM3_EXBUS_ATIM0_ALES0 *((volatile unsigned int*)(0x427E0C10UL)) +#define bFM3_EXBUS_ATIM0_ALES1 *((volatile unsigned int*)(0x427E0C14UL)) +#define bFM3_EXBUS_ATIM0_ALES2 *((volatile unsigned int*)(0x427E0C18UL)) +#define bFM3_EXBUS_ATIM0_ALES3 *((volatile unsigned int*)(0x427E0C1CUL)) +#define bFM3_EXBUS_ATIM0_ALEW0 *((volatile unsigned int*)(0x427E0C20UL)) +#define bFM3_EXBUS_ATIM0_ALEW1 *((volatile unsigned int*)(0x427E0C24UL)) +#define bFM3_EXBUS_ATIM0_ALEW2 *((volatile unsigned int*)(0x427E0C28UL)) +#define bFM3_EXBUS_ATIM0_ALEW3 *((volatile unsigned int*)(0x427E0C2CUL)) +#define bFM3_EXBUS_ATIM1_ALC0 *((volatile unsigned int*)(0x427E0C80UL)) +#define bFM3_EXBUS_ATIM1_ALC1 *((volatile unsigned int*)(0x427E0C84UL)) +#define bFM3_EXBUS_ATIM1_ALC2 *((volatile unsigned int*)(0x427E0C88UL)) +#define bFM3_EXBUS_ATIM1_ALC3 *((volatile unsigned int*)(0x427E0C8CUL)) +#define bFM3_EXBUS_ATIM1_ALES0 *((volatile unsigned int*)(0x427E0C90UL)) +#define bFM3_EXBUS_ATIM1_ALES1 *((volatile unsigned int*)(0x427E0C94UL)) +#define bFM3_EXBUS_ATIM1_ALES2 *((volatile unsigned int*)(0x427E0C98UL)) +#define bFM3_EXBUS_ATIM1_ALES3 *((volatile unsigned int*)(0x427E0C9CUL)) +#define bFM3_EXBUS_ATIM1_ALEW0 *((volatile unsigned int*)(0x427E0CA0UL)) +#define bFM3_EXBUS_ATIM1_ALEW1 *((volatile unsigned int*)(0x427E0CA4UL)) +#define bFM3_EXBUS_ATIM1_ALEW2 *((volatile unsigned int*)(0x427E0CA8UL)) +#define bFM3_EXBUS_ATIM1_ALEW3 *((volatile unsigned int*)(0x427E0CACUL)) +#define bFM3_EXBUS_ATIM2_ALC0 *((volatile unsigned int*)(0x427E0D00UL)) +#define bFM3_EXBUS_ATIM2_ALC1 *((volatile unsigned int*)(0x427E0D04UL)) +#define bFM3_EXBUS_ATIM2_ALC2 *((volatile unsigned int*)(0x427E0D08UL)) +#define bFM3_EXBUS_ATIM2_ALC3 *((volatile unsigned int*)(0x427E0D0CUL)) +#define bFM3_EXBUS_ATIM2_ALES0 *((volatile unsigned int*)(0x427E0D10UL)) +#define bFM3_EXBUS_ATIM2_ALES1 *((volatile unsigned int*)(0x427E0D14UL)) +#define bFM3_EXBUS_ATIM2_ALES2 *((volatile unsigned int*)(0x427E0D18UL)) +#define bFM3_EXBUS_ATIM2_ALES3 *((volatile unsigned int*)(0x427E0D1CUL)) +#define bFM3_EXBUS_ATIM2_ALEW0 *((volatile unsigned int*)(0x427E0D20UL)) +#define bFM3_EXBUS_ATIM2_ALEW1 *((volatile unsigned int*)(0x427E0D24UL)) +#define bFM3_EXBUS_ATIM2_ALEW2 *((volatile unsigned int*)(0x427E0D28UL)) +#define bFM3_EXBUS_ATIM2_ALEW3 *((volatile unsigned int*)(0x427E0D2CUL)) +#define bFM3_EXBUS_ATIM3_ALC0 *((volatile unsigned int*)(0x427E0D80UL)) +#define bFM3_EXBUS_ATIM3_ALC1 *((volatile unsigned int*)(0x427E0D84UL)) +#define bFM3_EXBUS_ATIM3_ALC2 *((volatile unsigned int*)(0x427E0D88UL)) +#define bFM3_EXBUS_ATIM3_ALC3 *((volatile unsigned int*)(0x427E0D8CUL)) +#define bFM3_EXBUS_ATIM3_ALES0 *((volatile unsigned int*)(0x427E0D90UL)) +#define bFM3_EXBUS_ATIM3_ALES1 *((volatile unsigned int*)(0x427E0D94UL)) +#define bFM3_EXBUS_ATIM3_ALES2 *((volatile unsigned int*)(0x427E0D98UL)) +#define bFM3_EXBUS_ATIM3_ALES3 *((volatile unsigned int*)(0x427E0D9CUL)) +#define bFM3_EXBUS_ATIM3_ALEW0 *((volatile unsigned int*)(0x427E0DA0UL)) +#define bFM3_EXBUS_ATIM3_ALEW1 *((volatile unsigned int*)(0x427E0DA4UL)) +#define bFM3_EXBUS_ATIM3_ALEW2 *((volatile unsigned int*)(0x427E0DA8UL)) +#define bFM3_EXBUS_ATIM3_ALEW3 *((volatile unsigned int*)(0x427E0DACUL)) +#define bFM3_EXBUS_ATIM4_ALC0 *((volatile unsigned int*)(0x427E0E00UL)) +#define bFM3_EXBUS_ATIM4_ALC1 *((volatile unsigned int*)(0x427E0E04UL)) +#define bFM3_EXBUS_ATIM4_ALC2 *((volatile unsigned int*)(0x427E0E08UL)) +#define bFM3_EXBUS_ATIM4_ALC3 *((volatile unsigned int*)(0x427E0E0CUL)) +#define bFM3_EXBUS_ATIM4_ALES0 *((volatile unsigned int*)(0x427E0E10UL)) +#define bFM3_EXBUS_ATIM4_ALES1 *((volatile unsigned int*)(0x427E0E14UL)) +#define bFM3_EXBUS_ATIM4_ALES2 *((volatile unsigned int*)(0x427E0E18UL)) +#define bFM3_EXBUS_ATIM4_ALES3 *((volatile unsigned int*)(0x427E0E1CUL)) +#define bFM3_EXBUS_ATIM4_ALEW0 *((volatile unsigned int*)(0x427E0E20UL)) +#define bFM3_EXBUS_ATIM4_ALEW1 *((volatile unsigned int*)(0x427E0E24UL)) +#define bFM3_EXBUS_ATIM4_ALEW2 *((volatile unsigned int*)(0x427E0E28UL)) +#define bFM3_EXBUS_ATIM4_ALEW3 *((volatile unsigned int*)(0x427E0E2CUL)) +#define bFM3_EXBUS_ATIM5_ALC0 *((volatile unsigned int*)(0x427E0E80UL)) +#define bFM3_EXBUS_ATIM5_ALC1 *((volatile unsigned int*)(0x427E0E84UL)) +#define bFM3_EXBUS_ATIM5_ALC2 *((volatile unsigned int*)(0x427E0E88UL)) +#define bFM3_EXBUS_ATIM5_ALC3 *((volatile unsigned int*)(0x427E0E8CUL)) +#define bFM3_EXBUS_ATIM5_ALES0 *((volatile unsigned int*)(0x427E0E90UL)) +#define bFM3_EXBUS_ATIM5_ALES1 *((volatile unsigned int*)(0x427E0E94UL)) +#define bFM3_EXBUS_ATIM5_ALES2 *((volatile unsigned int*)(0x427E0E98UL)) +#define bFM3_EXBUS_ATIM5_ALES3 *((volatile unsigned int*)(0x427E0E9CUL)) +#define bFM3_EXBUS_ATIM5_ALEW0 *((volatile unsigned int*)(0x427E0EA0UL)) +#define bFM3_EXBUS_ATIM5_ALEW1 *((volatile unsigned int*)(0x427E0EA4UL)) +#define bFM3_EXBUS_ATIM5_ALEW2 *((volatile unsigned int*)(0x427E0EA8UL)) +#define bFM3_EXBUS_ATIM5_ALEW3 *((volatile unsigned int*)(0x427E0EACUL)) +#define bFM3_EXBUS_ATIM6_ALC0 *((volatile unsigned int*)(0x427E0F00UL)) +#define bFM3_EXBUS_ATIM6_ALC1 *((volatile unsigned int*)(0x427E0F04UL)) +#define bFM3_EXBUS_ATIM6_ALC2 *((volatile unsigned int*)(0x427E0F08UL)) +#define bFM3_EXBUS_ATIM6_ALC3 *((volatile unsigned int*)(0x427E0F0CUL)) +#define bFM3_EXBUS_ATIM6_ALES0 *((volatile unsigned int*)(0x427E0F10UL)) +#define bFM3_EXBUS_ATIM6_ALES1 *((volatile unsigned int*)(0x427E0F14UL)) +#define bFM3_EXBUS_ATIM6_ALES2 *((volatile unsigned int*)(0x427E0F18UL)) +#define bFM3_EXBUS_ATIM6_ALES3 *((volatile unsigned int*)(0x427E0F1CUL)) +#define bFM3_EXBUS_ATIM6_ALEW0 *((volatile unsigned int*)(0x427E0F20UL)) +#define bFM3_EXBUS_ATIM6_ALEW1 *((volatile unsigned int*)(0x427E0F24UL)) +#define bFM3_EXBUS_ATIM6_ALEW2 *((volatile unsigned int*)(0x427E0F28UL)) +#define bFM3_EXBUS_ATIM6_ALEW3 *((volatile unsigned int*)(0x427E0F2CUL)) +#define bFM3_EXBUS_ATIM7_ALC0 *((volatile unsigned int*)(0x427E0F80UL)) +#define bFM3_EXBUS_ATIM7_ALC1 *((volatile unsigned int*)(0x427E0F84UL)) +#define bFM3_EXBUS_ATIM7_ALC2 *((volatile unsigned int*)(0x427E0F88UL)) +#define bFM3_EXBUS_ATIM7_ALC3 *((volatile unsigned int*)(0x427E0F8CUL)) +#define bFM3_EXBUS_ATIM7_ALES0 *((volatile unsigned int*)(0x427E0F90UL)) +#define bFM3_EXBUS_ATIM7_ALES1 *((volatile unsigned int*)(0x427E0F94UL)) +#define bFM3_EXBUS_ATIM7_ALES2 *((volatile unsigned int*)(0x427E0F98UL)) +#define bFM3_EXBUS_ATIM7_ALES3 *((volatile unsigned int*)(0x427E0F9CUL)) +#define bFM3_EXBUS_ATIM7_ALEW0 *((volatile unsigned int*)(0x427E0FA0UL)) +#define bFM3_EXBUS_ATIM7_ALEW1 *((volatile unsigned int*)(0x427E0FA4UL)) +#define bFM3_EXBUS_ATIM7_ALEW2 *((volatile unsigned int*)(0x427E0FA8UL)) +#define bFM3_EXBUS_ATIM7_ALEW3 *((volatile unsigned int*)(0x427E0FACUL)) +#define bFM3_EXBUS_DCLKR_MDIV0 *((volatile unsigned int*)(0x427E6000UL)) +#define bFM3_EXBUS_DCLKR_MDIV1 *((volatile unsigned int*)(0x427E6004UL)) +#define bFM3_EXBUS_DCLKR_MDIV2 *((volatile unsigned int*)(0x427E6008UL)) +#define bFM3_EXBUS_DCLKR_MDIV3 *((volatile unsigned int*)(0x427E600CUL)) +#define bFM3_EXBUS_DCLKR_MCLKON *((volatile unsigned int*)(0x427E6010UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* USB channel 1 registers */ +#define bFM3_USB1_HCNT_HOST *((volatile unsigned int*)(0x42A42000UL)) +#define bFM3_USB1_HCNT_URST *((volatile unsigned int*)(0x42A42004UL)) +#define bFM3_USB1_HCNT_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) +#define bFM3_USB1_HCNT_DIRE *((volatile unsigned int*)(0x42A4200CUL)) +#define bFM3_USB1_HCNT_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) +#define bFM3_USB1_HCNT_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) +#define bFM3_USB1_HCNT_URIRE *((volatile unsigned int*)(0x42A42018UL)) +#define bFM3_USB1_HCNT_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) +#define bFM3_USB1_HCNT_RETRY *((volatile unsigned int*)(0x42A42020UL)) +#define bFM3_USB1_HCNT_CANCEL *((volatile unsigned int*)(0x42A42024UL)) +#define bFM3_USB1_HCNT_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) +#define bFM3_USB1_HCNT0_HOST *((volatile unsigned int*)(0x42A42000UL)) +#define bFM3_USB1_HCNT0_URST *((volatile unsigned int*)(0x42A42004UL)) +#define bFM3_USB1_HCNT0_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) +#define bFM3_USB1_HCNT0_DIRE *((volatile unsigned int*)(0x42A4200CUL)) +#define bFM3_USB1_HCNT0_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) +#define bFM3_USB1_HCNT0_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) +#define bFM3_USB1_HCNT0_URIRE *((volatile unsigned int*)(0x42A42018UL)) +#define bFM3_USB1_HCNT0_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) +#define bFM3_USB1_HCNT1_RETRY *((volatile unsigned int*)(0x42A42020UL)) +#define bFM3_USB1_HCNT1_CANCEL *((volatile unsigned int*)(0x42A42024UL)) +#define bFM3_USB1_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) +#define bFM3_USB1_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42A42080UL)) +#define bFM3_USB1_HIRQ_DIRQ *((volatile unsigned int*)(0x42A42084UL)) +#define bFM3_USB1_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42A42088UL)) +#define bFM3_USB1_HIRQ_CMPIRQ *((volatile unsigned int*)(0x42A4208CUL)) +#define bFM3_USB1_HIRQ_URIRQ *((volatile unsigned int*)(0x42A42090UL)) +#define bFM3_USB1_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42A42094UL)) +#define bFM3_USB1_HIRQ_TCAN *((volatile unsigned int*)(0x42A4209CUL)) +#define bFM3_USB1_HERR_HS0 *((volatile unsigned int*)(0x42A420A0UL)) +#define bFM3_USB1_HERR_HS1 *((volatile unsigned int*)(0x42A420A4UL)) +#define bFM3_USB1_HERR_STUFF *((volatile unsigned int*)(0x42A420A8UL)) +#define bFM3_USB1_HERR_TGERR *((volatile unsigned int*)(0x42A420ACUL)) +#define bFM3_USB1_HERR_CRC *((volatile unsigned int*)(0x42A420B0UL)) +#define bFM3_USB1_HERR_TOUT *((volatile unsigned int*)(0x42A420B4UL)) +#define bFM3_USB1_HERR_RERR *((volatile unsigned int*)(0x42A420B8UL)) +#define bFM3_USB1_HERR_LSTOF *((volatile unsigned int*)(0x42A420BCUL)) +#define bFM3_USB1_HSTATE_CSTAT *((volatile unsigned int*)(0x42A42100UL)) +#define bFM3_USB1_HSTATE_TMODE *((volatile unsigned int*)(0x42A42104UL)) +#define bFM3_USB1_HSTATE_SUSP *((volatile unsigned int*)(0x42A42108UL)) +#define bFM3_USB1_HSTATE_SOFBUSY *((volatile unsigned int*)(0x42A4210CUL)) +#define bFM3_USB1_HSTATE_CLKSEL *((volatile unsigned int*)(0x42A42110UL)) +#define bFM3_USB1_HSTATE_ALIVE *((volatile unsigned int*)(0x42A42114UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42A42120UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42A42124UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42A42128UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x42A4212CUL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42A42130UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42A42134UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42A42138UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x42A4213CUL)) +#define bFM3_USB1_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42A42180UL)) +#define bFM3_USB1_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42A42184UL)) +#define bFM3_USB1_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42A42188UL)) +#define bFM3_USB1_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x42A4218CUL)) +#define bFM3_USB1_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42A42190UL)) +#define bFM3_USB1_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42A42194UL)) +#define bFM3_USB1_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42A42198UL)) +#define bFM3_USB1_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x42A4219CUL)) +#define bFM3_USB1_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x42A421A0UL)) +#define bFM3_USB1_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x42A421A4UL)) +#define bFM3_USB1_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x42A421A8UL)) +#define bFM3_USB1_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x42A421ACUL)) +#define bFM3_USB1_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x42A421B0UL)) +#define bFM3_USB1_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x42A421B4UL)) +#define bFM3_USB1_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x42A421B8UL)) +#define bFM3_USB1_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x42A421BCUL)) +#define bFM3_USB1_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42A42180UL)) +#define bFM3_USB1_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42A42184UL)) +#define bFM3_USB1_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42A42188UL)) +#define bFM3_USB1_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x42A4218CUL)) +#define bFM3_USB1_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42A42190UL)) +#define bFM3_USB1_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42A42194UL)) +#define bFM3_USB1_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42A42198UL)) +#define bFM3_USB1_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x42A4219CUL)) +#define bFM3_USB1_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x42A421A0UL)) +#define bFM3_USB1_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x42A421A4UL)) +#define bFM3_USB1_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x42A421A8UL)) +#define bFM3_USB1_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x42A421ACUL)) +#define bFM3_USB1_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x42A421B0UL)) +#define bFM3_USB1_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x42A421B4UL)) +#define bFM3_USB1_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x42A421B8UL)) +#define bFM3_USB1_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x42A421BCUL)) +#define bFM3_USB1_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42A42200UL)) +#define bFM3_USB1_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42A42204UL)) +#define bFM3_USB1_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42A42208UL)) +#define bFM3_USB1_HADR_ADDRESS0 *((volatile unsigned int*)(0x42A42220UL)) +#define bFM3_USB1_HADR_ADDRESS1 *((volatile unsigned int*)(0x42A42224UL)) +#define bFM3_USB1_HADR_ADDRESS2 *((volatile unsigned int*)(0x42A42228UL)) +#define bFM3_USB1_HADR_ADDRESS3 *((volatile unsigned int*)(0x42A4222CUL)) +#define bFM3_USB1_HADR_ADDRESS4 *((volatile unsigned int*)(0x42A42230UL)) +#define bFM3_USB1_HADR_ADDRESS5 *((volatile unsigned int*)(0x42A42234UL)) +#define bFM3_USB1_HADR_ADDRESS6 *((volatile unsigned int*)(0x42A42238UL)) +#define bFM3_USB1_HEOF_EOF0 *((volatile unsigned int*)(0x42A42280UL)) +#define bFM3_USB1_HEOF_EOF1 *((volatile unsigned int*)(0x42A42284UL)) +#define bFM3_USB1_HEOF_EOF2 *((volatile unsigned int*)(0x42A42288UL)) +#define bFM3_USB1_HEOF_EOF3 *((volatile unsigned int*)(0x42A4228CUL)) +#define bFM3_USB1_HEOF_EOF4 *((volatile unsigned int*)(0x42A42290UL)) +#define bFM3_USB1_HEOF_EOF5 *((volatile unsigned int*)(0x42A42294UL)) +#define bFM3_USB1_HEOF_EOF6 *((volatile unsigned int*)(0x42A42298UL)) +#define bFM3_USB1_HEOF_EOF7 *((volatile unsigned int*)(0x42A4229CUL)) +#define bFM3_USB1_HEOF_EOF8 *((volatile unsigned int*)(0x42A422A0UL)) +#define bFM3_USB1_HEOF_EOF9 *((volatile unsigned int*)(0x42A422A4UL)) +#define bFM3_USB1_HEOF_EOF10 *((volatile unsigned int*)(0x42A422A8UL)) +#define bFM3_USB1_HEOF_EOF11 *((volatile unsigned int*)(0x42A422ACUL)) +#define bFM3_USB1_HEOF_EOF12 *((volatile unsigned int*)(0x42A422B0UL)) +#define bFM3_USB1_HEOF_EOF13 *((volatile unsigned int*)(0x42A422B4UL)) +#define bFM3_USB1_HEOF_EOF14 *((volatile unsigned int*)(0x42A422B8UL)) +#define bFM3_USB1_HEOF_EOF15 *((volatile unsigned int*)(0x42A422BCUL)) +#define bFM3_USB1_HEOF0_EOF00 *((volatile unsigned int*)(0x42A42280UL)) +#define bFM3_USB1_HEOF0_EOF01 *((volatile unsigned int*)(0x42A42284UL)) +#define bFM3_USB1_HEOF0_EOF02 *((volatile unsigned int*)(0x42A42288UL)) +#define bFM3_USB1_HEOF0_EOF03 *((volatile unsigned int*)(0x42A4228CUL)) +#define bFM3_USB1_HEOF0_EOF04 *((volatile unsigned int*)(0x42A42290UL)) +#define bFM3_USB1_HEOF0_EOF05 *((volatile unsigned int*)(0x42A42294UL)) +#define bFM3_USB1_HEOF0_EOF06 *((volatile unsigned int*)(0x42A42298UL)) +#define bFM3_USB1_HEOF0_EOF07 *((volatile unsigned int*)(0x42A4229CUL)) +#define bFM3_USB1_HEOF1_EOF10 *((volatile unsigned int*)(0x42A422A0UL)) +#define bFM3_USB1_HEOF1_EOF11 *((volatile unsigned int*)(0x42A422A4UL)) +#define bFM3_USB1_HEOF1_EOF12 *((volatile unsigned int*)(0x42A422A8UL)) +#define bFM3_USB1_HEOF1_EOF13 *((volatile unsigned int*)(0x42A422ACUL)) +#define bFM3_USB1_HEOF1_EOF14 *((volatile unsigned int*)(0x42A422B0UL)) +#define bFM3_USB1_HEOF1_EOF15 *((volatile unsigned int*)(0x42A422B4UL)) +#define bFM3_USB1_HFRAME_FRAME0 *((volatile unsigned int*)(0x42A42300UL)) +#define bFM3_USB1_HFRAME_FRAME1 *((volatile unsigned int*)(0x42A42304UL)) +#define bFM3_USB1_HFRAME_FRAME2 *((volatile unsigned int*)(0x42A42308UL)) +#define bFM3_USB1_HFRAME_FRAME3 *((volatile unsigned int*)(0x42A4230CUL)) +#define bFM3_USB1_HFRAME_FRAME4 *((volatile unsigned int*)(0x42A42310UL)) +#define bFM3_USB1_HFRAME_FRAME5 *((volatile unsigned int*)(0x42A42314UL)) +#define bFM3_USB1_HFRAME_FRAME6 *((volatile unsigned int*)(0x42A42318UL)) +#define bFM3_USB1_HFRAME_FRAME7 *((volatile unsigned int*)(0x42A4231CUL)) +#define bFM3_USB1_HFRAME_FRAME8 *((volatile unsigned int*)(0x42A42320UL)) +#define bFM3_USB1_HFRAME_FRAME9 *((volatile unsigned int*)(0x42A42324UL)) +#define bFM3_USB1_HFRAME_FRAME10 *((volatile unsigned int*)(0x42A42328UL)) +#define bFM3_USB1_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42A42300UL)) +#define bFM3_USB1_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42A42304UL)) +#define bFM3_USB1_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42A42308UL)) +#define bFM3_USB1_HFRAME0_FRAME03 *((volatile unsigned int*)(0x42A4230CUL)) +#define bFM3_USB1_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42A42310UL)) +#define bFM3_USB1_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42A42314UL)) +#define bFM3_USB1_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42A42318UL)) +#define bFM3_USB1_HFRAME0_FRAME07 *((volatile unsigned int*)(0x42A4231CUL)) +#define bFM3_USB1_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42A42320UL)) +#define bFM3_USB1_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42A42324UL)) +#define bFM3_USB1_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42A42328UL)) +#define bFM3_USB1_HFRAME1_FRAME13 *((volatile unsigned int*)(0x42A4232CUL)) +#define bFM3_USB1_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42A42380UL)) +#define bFM3_USB1_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42A42384UL)) +#define bFM3_USB1_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42A42388UL)) +#define bFM3_USB1_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x42A4238CUL)) +#define bFM3_USB1_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42A42390UL)) +#define bFM3_USB1_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42A42394UL)) +#define bFM3_USB1_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42A42398UL)) +#define bFM3_USB1_HTOKEN_TGGL *((volatile unsigned int*)(0x42A4239CUL)) +#define bFM3_USB1_UDCC_PWC *((volatile unsigned int*)(0x42A42400UL)) +#define bFM3_USB1_UDCC_RFBK *((volatile unsigned int*)(0x42A42404UL)) +#define bFM3_USB1_UDCC_STALCLREN *((volatile unsigned int*)(0x42A4240CUL)) +#define bFM3_USB1_UDCC_USTP *((volatile unsigned int*)(0x42A42410UL)) +#define bFM3_USB1_UDCC_HCONX *((volatile unsigned int*)(0x42A42414UL)) +#define bFM3_USB1_UDCC_RESUM *((volatile unsigned int*)(0x42A42418UL)) +#define bFM3_USB1_UDCC_RST *((volatile unsigned int*)(0x42A4241CUL)) +#define bFM3_USB1_EP0C_PKS00 *((volatile unsigned int*)(0x42A42480UL)) +#define bFM3_USB1_EP0C_PKS01 *((volatile unsigned int*)(0x42A42484UL)) +#define bFM3_USB1_EP0C_PKS02 *((volatile unsigned int*)(0x42A42488UL)) +#define bFM3_USB1_EP0C_PKS03 *((volatile unsigned int*)(0x42A4248CUL)) +#define bFM3_USB1_EP0C_PKS04 *((volatile unsigned int*)(0x42A42490UL)) +#define bFM3_USB1_EP0C_PKS05 *((volatile unsigned int*)(0x42A42494UL)) +#define bFM3_USB1_EP0C_PKS06 *((volatile unsigned int*)(0x42A42498UL)) +#define bFM3_USB1_EP0C_STAL *((volatile unsigned int*)(0x42A424A4UL)) +#define bFM3_USB1_EP1C_PKS10 *((volatile unsigned int*)(0x42A42500UL)) +#define bFM3_USB1_EP1C_PKS11 *((volatile unsigned int*)(0x42A42504UL)) +#define bFM3_USB1_EP1C_PKS12 *((volatile unsigned int*)(0x42A42508UL)) +#define bFM3_USB1_EP1C_PKS13 *((volatile unsigned int*)(0x42A4250CUL)) +#define bFM3_USB1_EP1C_PKS14 *((volatile unsigned int*)(0x42A42510UL)) +#define bFM3_USB1_EP1C_PKS15 *((volatile unsigned int*)(0x42A42514UL)) +#define bFM3_USB1_EP1C_PKS16 *((volatile unsigned int*)(0x42A42518UL)) +#define bFM3_USB1_EP1C_PKS17 *((volatile unsigned int*)(0x42A4251CUL)) +#define bFM3_USB1_EP1C_PKS18 *((volatile unsigned int*)(0x42A42520UL)) +#define bFM3_USB1_EP1C_STAL *((volatile unsigned int*)(0x42A42524UL)) +#define bFM3_USB1_EP1C_NULE *((volatile unsigned int*)(0x42A42528UL)) +#define bFM3_USB1_EP1C_DMAE *((volatile unsigned int*)(0x42A4252CUL)) +#define bFM3_USB1_EP1C_DIR *((volatile unsigned int*)(0x42A42530UL)) +#define bFM3_USB1_EP1C_TYPE0 *((volatile unsigned int*)(0x42A42534UL)) +#define bFM3_USB1_EP1C_TYPE1 *((volatile unsigned int*)(0x42A42538UL)) +#define bFM3_USB1_EP1C_EPEN *((volatile unsigned int*)(0x42A4253CUL)) +#define bFM3_USB1_EP2C_PKS20 *((volatile unsigned int*)(0x42A42580UL)) +#define bFM3_USB1_EP2C_PKS21 *((volatile unsigned int*)(0x42A42584UL)) +#define bFM3_USB1_EP2C_PKS22 *((volatile unsigned int*)(0x42A42588UL)) +#define bFM3_USB1_EP2C_PKS23 *((volatile unsigned int*)(0x42A4258CUL)) +#define bFM3_USB1_EP2C_PKS24 *((volatile unsigned int*)(0x42A42590UL)) +#define bFM3_USB1_EP2C_PKS25 *((volatile unsigned int*)(0x42A42594UL)) +#define bFM3_USB1_EP2C_PKS26 *((volatile unsigned int*)(0x42A42598UL)) +#define bFM3_USB1_EP2C_STAL *((volatile unsigned int*)(0x42A425A4UL)) +#define bFM3_USB1_EP2C_NULE *((volatile unsigned int*)(0x42A425A8UL)) +#define bFM3_USB1_EP2C_DMAE *((volatile unsigned int*)(0x42A425ACUL)) +#define bFM3_USB1_EP2C_DIR *((volatile unsigned int*)(0x42A425B0UL)) +#define bFM3_USB1_EP2C_TYPE0 *((volatile unsigned int*)(0x42A425B4UL)) +#define bFM3_USB1_EP2C_TYPE1 *((volatile unsigned int*)(0x42A425B8UL)) +#define bFM3_USB1_EP2C_EPEN *((volatile unsigned int*)(0x42A425BCUL)) +#define bFM3_USB1_EP3C_PKS30 *((volatile unsigned int*)(0x42A42600UL)) +#define bFM3_USB1_EP3C_PKS31 *((volatile unsigned int*)(0x42A42604UL)) +#define bFM3_USB1_EP3C_PKS32 *((volatile unsigned int*)(0x42A42608UL)) +#define bFM3_USB1_EP3C_PKS33 *((volatile unsigned int*)(0x42A4260CUL)) +#define bFM3_USB1_EP3C_PKS34 *((volatile unsigned int*)(0x42A42610UL)) +#define bFM3_USB1_EP3C_PKS35 *((volatile unsigned int*)(0x42A42614UL)) +#define bFM3_USB1_EP3C_PKS36 *((volatile unsigned int*)(0x42A42618UL)) +#define bFM3_USB1_EP3C_STAL *((volatile unsigned int*)(0x42A42624UL)) +#define bFM3_USB1_EP3C_NULE *((volatile unsigned int*)(0x42A42628UL)) +#define bFM3_USB1_EP3C_DMAE *((volatile unsigned int*)(0x42A4262CUL)) +#define bFM3_USB1_EP3C_DIR *((volatile unsigned int*)(0x42A42630UL)) +#define bFM3_USB1_EP3C_TYPE0 *((volatile unsigned int*)(0x42A42634UL)) +#define bFM3_USB1_EP3C_TYPE1 *((volatile unsigned int*)(0x42A42638UL)) +#define bFM3_USB1_EP3C_EPEN *((volatile unsigned int*)(0x42A4263CUL)) +#define bFM3_USB1_EP4C_PKS40 *((volatile unsigned int*)(0x42A42680UL)) +#define bFM3_USB1_EP4C_PKS41 *((volatile unsigned int*)(0x42A42684UL)) +#define bFM3_USB1_EP4C_PKS42 *((volatile unsigned int*)(0x42A42688UL)) +#define bFM3_USB1_EP4C_PKS43 *((volatile unsigned int*)(0x42A4268CUL)) +#define bFM3_USB1_EP4C_PKS44 *((volatile unsigned int*)(0x42A42690UL)) +#define bFM3_USB1_EP4C_PKS45 *((volatile unsigned int*)(0x42A42694UL)) +#define bFM3_USB1_EP4C_PKS46 *((volatile unsigned int*)(0x42A42698UL)) +#define bFM3_USB1_EP4C_STAL *((volatile unsigned int*)(0x42A426A4UL)) +#define bFM3_USB1_EP4C_NULE *((volatile unsigned int*)(0x42A426A8UL)) +#define bFM3_USB1_EP4C_DMAE *((volatile unsigned int*)(0x42A426ACUL)) +#define bFM3_USB1_EP4C_DIR *((volatile unsigned int*)(0x42A426B0UL)) +#define bFM3_USB1_EP4C_TYPE0 *((volatile unsigned int*)(0x42A426B4UL)) +#define bFM3_USB1_EP4C_TYPE1 *((volatile unsigned int*)(0x42A426B8UL)) +#define bFM3_USB1_EP4C_EPEN *((volatile unsigned int*)(0x42A426BCUL)) +#define bFM3_USB1_EP5C_PKS50 *((volatile unsigned int*)(0x42A42700UL)) +#define bFM3_USB1_EP5C_PKS51 *((volatile unsigned int*)(0x42A42704UL)) +#define bFM3_USB1_EP5C_PKS52 *((volatile unsigned int*)(0x42A42708UL)) +#define bFM3_USB1_EP5C_PKS53 *((volatile unsigned int*)(0x42A4270CUL)) +#define bFM3_USB1_EP5C_PKS54 *((volatile unsigned int*)(0x42A42710UL)) +#define bFM3_USB1_EP5C_PKS55 *((volatile unsigned int*)(0x42A42714UL)) +#define bFM3_USB1_EP5C_PKS56 *((volatile unsigned int*)(0x42A42718UL)) +#define bFM3_USB1_EP5C_STAL *((volatile unsigned int*)(0x42A42724UL)) +#define bFM3_USB1_EP5C_NULE *((volatile unsigned int*)(0x42A42728UL)) +#define bFM3_USB1_EP5C_DMAE *((volatile unsigned int*)(0x42A4272CUL)) +#define bFM3_USB1_EP5C_DIR *((volatile unsigned int*)(0x42A42730UL)) +#define bFM3_USB1_EP5C_TYPE0 *((volatile unsigned int*)(0x42A42734UL)) +#define bFM3_USB1_EP5C_TYPE1 *((volatile unsigned int*)(0x42A42738UL)) +#define bFM3_USB1_EP5C_EPEN *((volatile unsigned int*)(0x42A4273CUL)) +#define bFM3_USB1_TMSP_TMSP0 *((volatile unsigned int*)(0x42A42780UL)) +#define bFM3_USB1_TMSP_TMSP1 *((volatile unsigned int*)(0x42A42784UL)) +#define bFM3_USB1_TMSP_TMSP2 *((volatile unsigned int*)(0x42A42788UL)) +#define bFM3_USB1_TMSP_TMSP3 *((volatile unsigned int*)(0x42A4278CUL)) +#define bFM3_USB1_TMSP_TMSP4 *((volatile unsigned int*)(0x42A42790UL)) +#define bFM3_USB1_TMSP_TMSP5 *((volatile unsigned int*)(0x42A42794UL)) +#define bFM3_USB1_TMSP_TMSP6 *((volatile unsigned int*)(0x42A42798UL)) +#define bFM3_USB1_TMSP_TMSP7 *((volatile unsigned int*)(0x42A4279CUL)) +#define bFM3_USB1_TMSP_TMSP8 *((volatile unsigned int*)(0x42A427A0UL)) +#define bFM3_USB1_TMSP_TMSP9 *((volatile unsigned int*)(0x42A427A4UL)) +#define bFM3_USB1_TMSP_TMSP10 *((volatile unsigned int*)(0x42A427A8UL)) +#define bFM3_USB1_UDCS_CONF *((volatile unsigned int*)(0x42A42800UL)) +#define bFM3_USB1_UDCS_SETP *((volatile unsigned int*)(0x42A42804UL)) +#define bFM3_USB1_UDCS_WKUP *((volatile unsigned int*)(0x42A42808UL)) +#define bFM3_USB1_UDCS_BRST *((volatile unsigned int*)(0x42A4280CUL)) +#define bFM3_USB1_UDCS_SOF *((volatile unsigned int*)(0x42A42810UL)) +#define bFM3_USB1_UDCS_SUSP *((volatile unsigned int*)(0x42A42814UL)) +#define bFM3_USB1_UDCIE_CONFIE *((volatile unsigned int*)(0x42A42820UL)) +#define bFM3_USB1_UDCIE_CONFN *((volatile unsigned int*)(0x42A42824UL)) +#define bFM3_USB1_UDCIE_WKUPIE *((volatile unsigned int*)(0x42A42828UL)) +#define bFM3_USB1_UDCIE_BRSTIE *((volatile unsigned int*)(0x42A4282CUL)) +#define bFM3_USB1_UDCIE_SOFIE *((volatile unsigned int*)(0x42A42830UL)) +#define bFM3_USB1_UDCIE_SUSPIE *((volatile unsigned int*)(0x42A42834UL)) +#define bFM3_USB1_EP0IS_DRQI *((volatile unsigned int*)(0x42A428A8UL)) +#define bFM3_USB1_EP0IS_DRQIIE *((volatile unsigned int*)(0x42A428B8UL)) +#define bFM3_USB1_EP0IS_BFINI *((volatile unsigned int*)(0x42A428BCUL)) +#define bFM3_USB1_EP0OS_SIZE0 *((volatile unsigned int*)(0x42A42900UL)) +#define bFM3_USB1_EP0OS_SIZE1 *((volatile unsigned int*)(0x42A42904UL)) +#define bFM3_USB1_EP0OS_SIZE2 *((volatile unsigned int*)(0x42A42908UL)) +#define bFM3_USB1_EP0OS_SIZE3 *((volatile unsigned int*)(0x42A4290CUL)) +#define bFM3_USB1_EP0OS_SIZE4 *((volatile unsigned int*)(0x42A42910UL)) +#define bFM3_USB1_EP0OS_SIZE5 *((volatile unsigned int*)(0x42A42914UL)) +#define bFM3_USB1_EP0OS_SIZE6 *((volatile unsigned int*)(0x42A42918UL)) +#define bFM3_USB1_EP0OS_SPK *((volatile unsigned int*)(0x42A42924UL)) +#define bFM3_USB1_EP0OS_DRQO *((volatile unsigned int*)(0x42A42928UL)) +#define bFM3_USB1_EP0OS_SPKIE *((volatile unsigned int*)(0x42A42934UL)) +#define bFM3_USB1_EP0OS_DRQOIE *((volatile unsigned int*)(0x42A42938UL)) +#define bFM3_USB1_EP0OS_BFINI *((volatile unsigned int*)(0x42A4293CUL)) +#define bFM3_USB1_EP1S_SIZE10 *((volatile unsigned int*)(0x42A42980UL)) +#define bFM3_USB1_EP1S_SIZE11 *((volatile unsigned int*)(0x42A42984UL)) +#define bFM3_USB1_EP1S_SIZE12 *((volatile unsigned int*)(0x42A42988UL)) +#define bFM3_USB1_EP1S_SIZE13 *((volatile unsigned int*)(0x42A4298CUL)) +#define bFM3_USB1_EP1S_SIZE14 *((volatile unsigned int*)(0x42A42990UL)) +#define bFM3_USB1_EP1S_SIZE15 *((volatile unsigned int*)(0x42A42994UL)) +#define bFM3_USB1_EP1S_SIZE16 *((volatile unsigned int*)(0x42A42998UL)) +#define bFM3_USB1_EP1S_SIZE17 *((volatile unsigned int*)(0x42A4299CUL)) +#define bFM3_USB1_EP1S_SIZE18 *((volatile unsigned int*)(0x42A429A0UL)) +#define bFM3_USB1_EP1S_SPK *((volatile unsigned int*)(0x42A429A4UL)) +#define bFM3_USB1_EP1S_DRQ *((volatile unsigned int*)(0x42A429A8UL)) +#define bFM3_USB1_EP1S_BUSY *((volatile unsigned int*)(0x42A429ACUL)) +#define bFM3_USB1_EP1S_SPKIE *((volatile unsigned int*)(0x42A429B4UL)) +#define bFM3_USB1_EP1S_DRQIE *((volatile unsigned int*)(0x42A429B8UL)) +#define bFM3_USB1_EP1S_BFINI *((volatile unsigned int*)(0x42A429BCUL)) +#define bFM3_USB1_EP2S_SIZE20 *((volatile unsigned int*)(0x42A42A00UL)) +#define bFM3_USB1_EP2S_SIZE21 *((volatile unsigned int*)(0x42A42A04UL)) +#define bFM3_USB1_EP2S_SIZE22 *((volatile unsigned int*)(0x42A42A08UL)) +#define bFM3_USB1_EP2S_SIZE23 *((volatile unsigned int*)(0x42A42A0CUL)) +#define bFM3_USB1_EP2S_SIZE24 *((volatile unsigned int*)(0x42A42A10UL)) +#define bFM3_USB1_EP2S_SIZE25 *((volatile unsigned int*)(0x42A42A14UL)) +#define bFM3_USB1_EP2S_SIZE26 *((volatile unsigned int*)(0x42A42A18UL)) +#define bFM3_USB1_EP2S_SPK *((volatile unsigned int*)(0x42A42A24UL)) +#define bFM3_USB1_EP2S_DRQ *((volatile unsigned int*)(0x42A42A28UL)) +#define bFM3_USB1_EP2S_BUSY *((volatile unsigned int*)(0x42A42A2CUL)) +#define bFM3_USB1_EP2S_SPKIE *((volatile unsigned int*)(0x42A42A34UL)) +#define bFM3_USB1_EP2S_DRQIE *((volatile unsigned int*)(0x42A42A38UL)) +#define bFM3_USB1_EP2S_BFINI *((volatile unsigned int*)(0x42A42A3CUL)) +#define bFM3_USB1_EP3S_SIZE30 *((volatile unsigned int*)(0x42A42A80UL)) +#define bFM3_USB1_EP3S_SIZE31 *((volatile unsigned int*)(0x42A42A84UL)) +#define bFM3_USB1_EP3S_SIZE32 *((volatile unsigned int*)(0x42A42A88UL)) +#define bFM3_USB1_EP3S_SIZE33 *((volatile unsigned int*)(0x42A42A8CUL)) +#define bFM3_USB1_EP3S_SIZE34 *((volatile unsigned int*)(0x42A42A90UL)) +#define bFM3_USB1_EP3S_SIZE35 *((volatile unsigned int*)(0x42A42A94UL)) +#define bFM3_USB1_EP3S_SIZE36 *((volatile unsigned int*)(0x42A42A98UL)) +#define bFM3_USB1_EP3S_SPK *((volatile unsigned int*)(0x42A42AA4UL)) +#define bFM3_USB1_EP3S_DRQ *((volatile unsigned int*)(0x42A42AA8UL)) +#define bFM3_USB1_EP3S_BUSY *((volatile unsigned int*)(0x42A42AACUL)) +#define bFM3_USB1_EP3S_SPKIE *((volatile unsigned int*)(0x42A42AB4UL)) +#define bFM3_USB1_EP3S_DRQIE *((volatile unsigned int*)(0x42A42AB8UL)) +#define bFM3_USB1_EP3S_BFINI *((volatile unsigned int*)(0x42A42ABCUL)) +#define bFM3_USB1_EP4S_SIZE40 *((volatile unsigned int*)(0x42A42B00UL)) +#define bFM3_USB1_EP4S_SIZE41 *((volatile unsigned int*)(0x42A42B04UL)) +#define bFM3_USB1_EP4S_SIZE42 *((volatile unsigned int*)(0x42A42B08UL)) +#define bFM3_USB1_EP4S_SIZE43 *((volatile unsigned int*)(0x42A42B0CUL)) +#define bFM3_USB1_EP4S_SIZE44 *((volatile unsigned int*)(0x42A42B10UL)) +#define bFM3_USB1_EP4S_SIZE45 *((volatile unsigned int*)(0x42A42B14UL)) +#define bFM3_USB1_EP4S_SIZE46 *((volatile unsigned int*)(0x42A42B18UL)) +#define bFM3_USB1_EP4S_SPK *((volatile unsigned int*)(0x42A42B24UL)) +#define bFM3_USB1_EP4S_DRQ *((volatile unsigned int*)(0x42A42B28UL)) +#define bFM3_USB1_EP4S_BUSY *((volatile unsigned int*)(0x42A42B2CUL)) +#define bFM3_USB1_EP4S_SPKIE *((volatile unsigned int*)(0x42A42B34UL)) +#define bFM3_USB1_EP4S_DRQIE *((volatile unsigned int*)(0x42A42B38UL)) +#define bFM3_USB1_EP4S_BFINI *((volatile unsigned int*)(0x42A42B3CUL)) +#define bFM3_USB1_EP5S_SIZE50 *((volatile unsigned int*)(0x42A42B80UL)) +#define bFM3_USB1_EP5S_SIZE51 *((volatile unsigned int*)(0x42A42B84UL)) +#define bFM3_USB1_EP5S_SIZE52 *((volatile unsigned int*)(0x42A42B88UL)) +#define bFM3_USB1_EP5S_SIZE53 *((volatile unsigned int*)(0x42A42B8CUL)) +#define bFM3_USB1_EP5S_SIZE54 *((volatile unsigned int*)(0x42A42B90UL)) +#define bFM3_USB1_EP5S_SIZE55 *((volatile unsigned int*)(0x42A42B94UL)) +#define bFM3_USB1_EP5S_SIZE56 *((volatile unsigned int*)(0x42A42B98UL)) +#define bFM3_USB1_EP5S_SPK *((volatile unsigned int*)(0x42A42BA4UL)) +#define bFM3_USB1_EP5S_DRQ *((volatile unsigned int*)(0x42A42BA8UL)) +#define bFM3_USB1_EP5S_BUSY *((volatile unsigned int*)(0x42A42BACUL)) +#define bFM3_USB1_EP5S_SPKIE *((volatile unsigned int*)(0x42A42BB4UL)) +#define bFM3_USB1_EP5S_DRQIE *((volatile unsigned int*)(0x42A42BB8UL)) +#define bFM3_USB1_EP5S_BFINI *((volatile unsigned int*)(0x42A42BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* ETHERNET-MAC0 registers*/ +#define bFM3_ETHERNET_MAC0_MCR_RE *((volatile unsigned int*)(0x42C80008UL)) +#define bFM3_ETHERNET_MAC0_MCR_TE *((volatile unsigned int*)(0x42C8000CUL)) +#define bFM3_ETHERNET_MAC0_MCR_DC *((volatile unsigned int*)(0x42C80010UL)) +#define bFM3_ETHERNET_MAC0_MCR_BL0 *((volatile unsigned int*)(0x42C80014UL)) +#define bFM3_ETHERNET_MAC0_MCR_BL1 *((volatile unsigned int*)(0x42C80018UL)) +#define bFM3_ETHERNET_MAC0_MCR_ACS *((volatile unsigned int*)(0x42C8001CUL)) +#define bFM3_ETHERNET_MAC0_MCR_LUD *((volatile unsigned int*)(0x42C80020UL)) +#define bFM3_ETHERNET_MAC0_MCR_DR *((volatile unsigned int*)(0x42C80024UL)) +#define bFM3_ETHERNET_MAC0_MCR_IPC *((volatile unsigned int*)(0x42C80028UL)) +#define bFM3_ETHERNET_MAC0_MCR_DM *((volatile unsigned int*)(0x42C8002CUL)) +#define bFM3_ETHERNET_MAC0_MCR_LM *((volatile unsigned int*)(0x42C80030UL)) +#define bFM3_ETHERNET_MAC0_MCR_DO *((volatile unsigned int*)(0x42C80034UL)) +#define bFM3_ETHERNET_MAC0_MCR_FES *((volatile unsigned int*)(0x42C80038UL)) +#define bFM3_ETHERNET_MAC0_MCR_PS *((volatile unsigned int*)(0x42C8003CUL)) +#define bFM3_ETHERNET_MAC0_MCR_DCRS *((volatile unsigned int*)(0x42C80040UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG0 *((volatile unsigned int*)(0x42C80044UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG1 *((volatile unsigned int*)(0x42C80048UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG2 *((volatile unsigned int*)(0x42C8004CUL)) +#define bFM3_ETHERNET_MAC0_MCR_JE *((volatile unsigned int*)(0x42C80050UL)) +#define bFM3_ETHERNET_MAC0_MCR_BE *((volatile unsigned int*)(0x42C80054UL)) +#define bFM3_ETHERNET_MAC0_MCR_JD *((volatile unsigned int*)(0x42C80058UL)) +#define bFM3_ETHERNET_MAC0_MCR_WD *((volatile unsigned int*)(0x42C8005CUL)) +#define bFM3_ETHERNET_MAC0_MCR_TC *((volatile unsigned int*)(0x42C80060UL)) +#define bFM3_ETHERNET_MAC0_MCR_CST *((volatile unsigned int*)(0x42C80064UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PR *((volatile unsigned int*)(0x42C80080UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HUC *((volatile unsigned int*)(0x42C80084UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HMC *((volatile unsigned int*)(0x42C80088UL)) +#define bFM3_ETHERNET_MAC0_MFFR_DAIF *((volatile unsigned int*)(0x42C8008CUL)) +#define bFM3_ETHERNET_MAC0_MFFR_PM *((volatile unsigned int*)(0x42C80090UL)) +#define bFM3_ETHERNET_MAC0_MFFR_DB *((volatile unsigned int*)(0x42C80094UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PCF0 *((volatile unsigned int*)(0x42C80098UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PCF1 *((volatile unsigned int*)(0x42C8009CUL)) +#define bFM3_ETHERNET_MAC0_MFFR_SAIF *((volatile unsigned int*)(0x42C800A0UL)) +#define bFM3_ETHERNET_MAC0_MFFR_SAF *((volatile unsigned int*)(0x42C800A4UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HPF *((volatile unsigned int*)(0x42C800A8UL)) +#define bFM3_ETHERNET_MAC0_MFFR_RA *((volatile unsigned int*)(0x42C800FCUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH0 *((volatile unsigned int*)(0x42C80100UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH1 *((volatile unsigned int*)(0x42C80104UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH2 *((volatile unsigned int*)(0x42C80108UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH3 *((volatile unsigned int*)(0x42C8010CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH4 *((volatile unsigned int*)(0x42C80110UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH5 *((volatile unsigned int*)(0x42C80114UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH6 *((volatile unsigned int*)(0x42C80118UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH7 *((volatile unsigned int*)(0x42C8011CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH8 *((volatile unsigned int*)(0x42C80120UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH9 *((volatile unsigned int*)(0x42C80124UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH10 *((volatile unsigned int*)(0x42C80128UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH11 *((volatile unsigned int*)(0x42C8012CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH12 *((volatile unsigned int*)(0x42C80130UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH13 *((volatile unsigned int*)(0x42C80134UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH14 *((volatile unsigned int*)(0x42C80138UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH15 *((volatile unsigned int*)(0x42C8013CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH16 *((volatile unsigned int*)(0x42C80140UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH17 *((volatile unsigned int*)(0x42C80144UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH18 *((volatile unsigned int*)(0x42C80148UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH19 *((volatile unsigned int*)(0x42C8014CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH20 *((volatile unsigned int*)(0x42C80150UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH21 *((volatile unsigned int*)(0x42C80154UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH22 *((volatile unsigned int*)(0x42C80158UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH23 *((volatile unsigned int*)(0x42C8015CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH24 *((volatile unsigned int*)(0x42C80160UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH25 *((volatile unsigned int*)(0x42C80164UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH26 *((volatile unsigned int*)(0x42C80168UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH27 *((volatile unsigned int*)(0x42C8016CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH28 *((volatile unsigned int*)(0x42C80170UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH29 *((volatile unsigned int*)(0x42C80174UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH30 *((volatile unsigned int*)(0x42C80178UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH31 *((volatile unsigned int*)(0x42C8017CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL0 *((volatile unsigned int*)(0x42C80180UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL1 *((volatile unsigned int*)(0x42C80184UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL2 *((volatile unsigned int*)(0x42C80188UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL3 *((volatile unsigned int*)(0x42C8018CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL4 *((volatile unsigned int*)(0x42C80190UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL5 *((volatile unsigned int*)(0x42C80194UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL6 *((volatile unsigned int*)(0x42C80198UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL7 *((volatile unsigned int*)(0x42C8019CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL8 *((volatile unsigned int*)(0x42C801A0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL9 *((volatile unsigned int*)(0x42C801A4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL10 *((volatile unsigned int*)(0x42C801A8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL11 *((volatile unsigned int*)(0x42C801ACUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL12 *((volatile unsigned int*)(0x42C801B0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL13 *((volatile unsigned int*)(0x42C801B4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL14 *((volatile unsigned int*)(0x42C801B8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL15 *((volatile unsigned int*)(0x42C801BCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL16 *((volatile unsigned int*)(0x42C801C0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL17 *((volatile unsigned int*)(0x42C801C4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL18 *((volatile unsigned int*)(0x42C801C8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL19 *((volatile unsigned int*)(0x42C801CCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL20 *((volatile unsigned int*)(0x42C801D0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL21 *((volatile unsigned int*)(0x42C801D4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL22 *((volatile unsigned int*)(0x42C801D8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL23 *((volatile unsigned int*)(0x42C801DCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL24 *((volatile unsigned int*)(0x42C801E0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL25 *((volatile unsigned int*)(0x42C801E4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL26 *((volatile unsigned int*)(0x42C801E8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL27 *((volatile unsigned int*)(0x42C801ECUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL28 *((volatile unsigned int*)(0x42C801F0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL29 *((volatile unsigned int*)(0x42C801F4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL30 *((volatile unsigned int*)(0x42C801F8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL31 *((volatile unsigned int*)(0x42C801FCUL)) +#define bFM3_ETHERNET_MAC0_GAR_GB *((volatile unsigned int*)(0x42C80200UL)) +#define bFM3_ETHERNET_MAC0_GAR_GW *((volatile unsigned int*)(0x42C80204UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR0 *((volatile unsigned int*)(0x42C80208UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR1 *((volatile unsigned int*)(0x42C8020CUL)) +#define bFM3_ETHERNET_MAC0_GAR_CR2 *((volatile unsigned int*)(0x42C80210UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR3 *((volatile unsigned int*)(0x42C80214UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR0 *((volatile unsigned int*)(0x42C80218UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR1 *((volatile unsigned int*)(0x42C8021CUL)) +#define bFM3_ETHERNET_MAC0_GAR_GR2 *((volatile unsigned int*)(0x42C80220UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR3 *((volatile unsigned int*)(0x42C80224UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR4 *((volatile unsigned int*)(0x42C80228UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA0 *((volatile unsigned int*)(0x42C8022CUL)) +#define bFM3_ETHERNET_MAC0_GAR_PA1 *((volatile unsigned int*)(0x42C80230UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA2 *((volatile unsigned int*)(0x42C80234UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA3 *((volatile unsigned int*)(0x42C80238UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA4 *((volatile unsigned int*)(0x42C8023CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD0 *((volatile unsigned int*)(0x42C80280UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD1 *((volatile unsigned int*)(0x42C80284UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD2 *((volatile unsigned int*)(0x42C80288UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD3 *((volatile unsigned int*)(0x42C8028CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD4 *((volatile unsigned int*)(0x42C80290UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD5 *((volatile unsigned int*)(0x42C80294UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD6 *((volatile unsigned int*)(0x42C80298UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD7 *((volatile unsigned int*)(0x42C8029CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD8 *((volatile unsigned int*)(0x42C802A0UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD9 *((volatile unsigned int*)(0x42C802A4UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD10 *((volatile unsigned int*)(0x42C802A8UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD11 *((volatile unsigned int*)(0x42C802ACUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD12 *((volatile unsigned int*)(0x42C802B0UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD13 *((volatile unsigned int*)(0x42C802B4UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD14 *((volatile unsigned int*)(0x42C802B8UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD15 *((volatile unsigned int*)(0x42C802BCUL)) +#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA *((volatile unsigned int*)(0x42C80300UL)) +#define bFM3_ETHERNET_MAC0_FCR_TFE *((volatile unsigned int*)(0x42C80304UL)) +#define bFM3_ETHERNET_MAC0_FCR_RFE *((volatile unsigned int*)(0x42C80308UL)) +#define bFM3_ETHERNET_MAC0_FCR_UP *((volatile unsigned int*)(0x42C8030CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PLT0 *((volatile unsigned int*)(0x42C80310UL)) +#define bFM3_ETHERNET_MAC0_FCR_PLT1 *((volatile unsigned int*)(0x42C80314UL)) +#define bFM3_ETHERNET_MAC0_FCR_DZPQ *((volatile unsigned int*)(0x42C8031CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT0 *((volatile unsigned int*)(0x42C80340UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT1 *((volatile unsigned int*)(0x42C80344UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT2 *((volatile unsigned int*)(0x42C80348UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT3 *((volatile unsigned int*)(0x42C8034CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT4 *((volatile unsigned int*)(0x42C80350UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT5 *((volatile unsigned int*)(0x42C80354UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT6 *((volatile unsigned int*)(0x42C80358UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT7 *((volatile unsigned int*)(0x42C8035CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT8 *((volatile unsigned int*)(0x42C80360UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT9 *((volatile unsigned int*)(0x42C80364UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT10 *((volatile unsigned int*)(0x42C80368UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT11 *((volatile unsigned int*)(0x42C8036CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT12 *((volatile unsigned int*)(0x42C80370UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT13 *((volatile unsigned int*)(0x42C80374UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT14 *((volatile unsigned int*)(0x42C80378UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT15 *((volatile unsigned int*)(0x42C8037CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL0 *((volatile unsigned int*)(0x42C80380UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL1 *((volatile unsigned int*)(0x42C80384UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL2 *((volatile unsigned int*)(0x42C80388UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL3 *((volatile unsigned int*)(0x42C8038CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL4 *((volatile unsigned int*)(0x42C80390UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL5 *((volatile unsigned int*)(0x42C80394UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL6 *((volatile unsigned int*)(0x42C80398UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL7 *((volatile unsigned int*)(0x42C8039CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL8 *((volatile unsigned int*)(0x42C803A0UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL9 *((volatile unsigned int*)(0x42C803A4UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL10 *((volatile unsigned int*)(0x42C803A8UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL11 *((volatile unsigned int*)(0x42C803ACUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL12 *((volatile unsigned int*)(0x42C803B0UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL13 *((volatile unsigned int*)(0x42C803B4UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL14 *((volatile unsigned int*)(0x42C803B8UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL15 *((volatile unsigned int*)(0x42C803BCUL)) +#define bFM3_ETHERNET_MAC0_VTR_ETV *((volatile unsigned int*)(0x42C803C0UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42C80500UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42C80504UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42C80508UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42C8050CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42C80510UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42C80514UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42C80518UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42C8051CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42C80520UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42C80524UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42C80528UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42C8052CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42C80530UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42C80534UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42C80538UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42C8053CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42C80540UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42C80544UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42C80548UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42C8054CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42C80550UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42C80554UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42C80558UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42C8055CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42C80560UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42C80564UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42C80568UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42C8056CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42C80570UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42C80574UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42C80578UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42C8057CUL)) +#define bFM3_ETHERNET_MAC0_PMTR_PD *((volatile unsigned int*)(0x42C80580UL)) +#define bFM3_ETHERNET_MAC0_PMTR_MPE *((volatile unsigned int*)(0x42C80584UL)) +#define bFM3_ETHERNET_MAC0_PMTR_WFE *((volatile unsigned int*)(0x42C80588UL)) +#define bFM3_ETHERNET_MAC0_PMTR_MPR *((volatile unsigned int*)(0x42C80594UL)) +#define bFM3_ETHERNET_MAC0_PMTR_WPR *((volatile unsigned int*)(0x42C80598UL)) +#define bFM3_ETHERNET_MAC0_PMTR_GU *((volatile unsigned int*)(0x42C805A4UL)) +#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR *((volatile unsigned int*)(0x42C805FCUL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN *((volatile unsigned int*)(0x42C80600UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX *((volatile unsigned int*)(0x42C80604UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN *((volatile unsigned int*)(0x42C80608UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX *((volatile unsigned int*)(0x42C8060CUL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST *((volatile unsigned int*)(0x42C80620UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST *((volatile unsigned int*)(0x42C80624UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN *((volatile unsigned int*)(0x42C80640UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_PLS *((volatile unsigned int*)(0x42C80644UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN *((volatile unsigned int*)(0x42C80648UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA *((volatile unsigned int*)(0x42C8064CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT0 *((volatile unsigned int*)(0x42C80680UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT1 *((volatile unsigned int*)(0x42C80684UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT2 *((volatile unsigned int*)(0x42C80688UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT3 *((volatile unsigned int*)(0x42C8068CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT4 *((volatile unsigned int*)(0x42C80690UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT5 *((volatile unsigned int*)(0x42C80694UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT6 *((volatile unsigned int*)(0x42C80698UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT7 *((volatile unsigned int*)(0x42C8069CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT8 *((volatile unsigned int*)(0x42C806A0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT9 *((volatile unsigned int*)(0x42C806A4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT10 *((volatile unsigned int*)(0x42C806A8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT11 *((volatile unsigned int*)(0x42C806ACUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT12 *((volatile unsigned int*)(0x42C806B0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT13 *((volatile unsigned int*)(0x42C806B4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT14 *((volatile unsigned int*)(0x42C806B8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT15 *((volatile unsigned int*)(0x42C806BCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT0 *((volatile unsigned int*)(0x42C806C0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT1 *((volatile unsigned int*)(0x42C806C4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT2 *((volatile unsigned int*)(0x42C806C8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT3 *((volatile unsigned int*)(0x42C806CCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT4 *((volatile unsigned int*)(0x42C806D0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT5 *((volatile unsigned int*)(0x42C806D4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT6 *((volatile unsigned int*)(0x42C806D8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT7 *((volatile unsigned int*)(0x42C806DCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT8 *((volatile unsigned int*)(0x42C806E0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT9 *((volatile unsigned int*)(0x42C806E4UL)) +#define bFM3_ETHERNET_MAC0_ISR_RGIS *((volatile unsigned int*)(0x42C80700UL)) +#define bFM3_ETHERNET_MAC0_ISR_PIS *((volatile unsigned int*)(0x42C8070CUL)) +#define bFM3_ETHERNET_MAC0_ISR_MIS *((volatile unsigned int*)(0x42C80710UL)) +#define bFM3_ETHERNET_MAC0_ISR_RIS *((volatile unsigned int*)(0x42C80714UL)) +#define bFM3_ETHERNET_MAC0_ISR_TIS *((volatile unsigned int*)(0x42C80718UL)) +#define bFM3_ETHERNET_MAC0_ISR_COIS *((volatile unsigned int*)(0x42C8071CUL)) +#define bFM3_ETHERNET_MAC0_ISR_TSIS *((volatile unsigned int*)(0x42C80724UL)) +#define bFM3_ETHERNET_MAC0_ISR_LPIIS *((volatile unsigned int*)(0x42C80728UL)) +#define bFM3_ETHERNET_MAC0_IMR_RGIM *((volatile unsigned int*)(0x42C80780UL)) +#define bFM3_ETHERNET_MAC0_IMR_PIM *((volatile unsigned int*)(0x42C8078CUL)) +#define bFM3_ETHERNET_MAC0_IMR_TSIM *((volatile unsigned int*)(0x42C80794UL)) +#define bFM3_ETHERNET_MAC0_IMR_LPIIM *((volatile unsigned int*)(0x42C80798UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A32 *((volatile unsigned int*)(0x42C80800UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A33 *((volatile unsigned int*)(0x42C80804UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A34 *((volatile unsigned int*)(0x42C80808UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A35 *((volatile unsigned int*)(0x42C8080CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A36 *((volatile unsigned int*)(0x42C80810UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A37 *((volatile unsigned int*)(0x42C80814UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A38 *((volatile unsigned int*)(0x42C80818UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A39 *((volatile unsigned int*)(0x42C8081CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A40 *((volatile unsigned int*)(0x42C80820UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A41 *((volatile unsigned int*)(0x42C80824UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A42 *((volatile unsigned int*)(0x42C80828UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A43 *((volatile unsigned int*)(0x42C8082CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A44 *((volatile unsigned int*)(0x42C80830UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A45 *((volatile unsigned int*)(0x42C80834UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A46 *((volatile unsigned int*)(0x42C80838UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A47 *((volatile unsigned int*)(0x42C8083CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_MO *((volatile unsigned int*)(0x42C8087CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A0 *((volatile unsigned int*)(0x42C80880UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A1 *((volatile unsigned int*)(0x42C80884UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A2 *((volatile unsigned int*)(0x42C80888UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A3 *((volatile unsigned int*)(0x42C8088CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A4 *((volatile unsigned int*)(0x42C80890UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A5 *((volatile unsigned int*)(0x42C80894UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A6 *((volatile unsigned int*)(0x42C80898UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A7 *((volatile unsigned int*)(0x42C8089CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A8 *((volatile unsigned int*)(0x42C808A0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A9 *((volatile unsigned int*)(0x42C808A4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A10 *((volatile unsigned int*)(0x42C808A8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A11 *((volatile unsigned int*)(0x42C808ACUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A12 *((volatile unsigned int*)(0x42C808B0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A13 *((volatile unsigned int*)(0x42C808B4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A14 *((volatile unsigned int*)(0x42C808B8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A15 *((volatile unsigned int*)(0x42C808BCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A16 *((volatile unsigned int*)(0x42C808C0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A17 *((volatile unsigned int*)(0x42C808C4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A18 *((volatile unsigned int*)(0x42C808C8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A19 *((volatile unsigned int*)(0x42C808CCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A20 *((volatile unsigned int*)(0x42C808D0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A21 *((volatile unsigned int*)(0x42C808D4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A22 *((volatile unsigned int*)(0x42C808D8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A23 *((volatile unsigned int*)(0x42C808DCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A24 *((volatile unsigned int*)(0x42C808E0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A25 *((volatile unsigned int*)(0x42C808E4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A26 *((volatile unsigned int*)(0x42C808E8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A27 *((volatile unsigned int*)(0x42C808ECUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A28 *((volatile unsigned int*)(0x42C808F0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A29 *((volatile unsigned int*)(0x42C808F4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A30 *((volatile unsigned int*)(0x42C808F8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A31 *((volatile unsigned int*)(0x42C808FCUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A32 *((volatile unsigned int*)(0x42C80900UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A33 *((volatile unsigned int*)(0x42C80904UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A34 *((volatile unsigned int*)(0x42C80908UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A35 *((volatile unsigned int*)(0x42C8090CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A36 *((volatile unsigned int*)(0x42C80910UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A37 *((volatile unsigned int*)(0x42C80914UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A38 *((volatile unsigned int*)(0x42C80918UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A39 *((volatile unsigned int*)(0x42C8091CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A40 *((volatile unsigned int*)(0x42C80920UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A41 *((volatile unsigned int*)(0x42C80924UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A42 *((volatile unsigned int*)(0x42C80928UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A43 *((volatile unsigned int*)(0x42C8092CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A44 *((volatile unsigned int*)(0x42C80930UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A45 *((volatile unsigned int*)(0x42C80934UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A46 *((volatile unsigned int*)(0x42C80938UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A47 *((volatile unsigned int*)(0x42C8093CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC0 *((volatile unsigned int*)(0x42C80960UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC1 *((volatile unsigned int*)(0x42C80964UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC2 *((volatile unsigned int*)(0x42C80968UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC3 *((volatile unsigned int*)(0x42C8096CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC4 *((volatile unsigned int*)(0x42C80970UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC5 *((volatile unsigned int*)(0x42C80974UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_SA *((volatile unsigned int*)(0x42C80978UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_AE *((volatile unsigned int*)(0x42C8097CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A0 *((volatile unsigned int*)(0x42C80980UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A1 *((volatile unsigned int*)(0x42C80984UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A2 *((volatile unsigned int*)(0x42C80988UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A3 *((volatile unsigned int*)(0x42C8098CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A4 *((volatile unsigned int*)(0x42C80990UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A5 *((volatile unsigned int*)(0x42C80994UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A6 *((volatile unsigned int*)(0x42C80998UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A7 *((volatile unsigned int*)(0x42C8099CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A8 *((volatile unsigned int*)(0x42C809A0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A9 *((volatile unsigned int*)(0x42C809A4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A10 *((volatile unsigned int*)(0x42C809A8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A11 *((volatile unsigned int*)(0x42C809ACUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A12 *((volatile unsigned int*)(0x42C809B0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A13 *((volatile unsigned int*)(0x42C809B4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A14 *((volatile unsigned int*)(0x42C809B8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A15 *((volatile unsigned int*)(0x42C809BCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A16 *((volatile unsigned int*)(0x42C809C0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A17 *((volatile unsigned int*)(0x42C809C4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A18 *((volatile unsigned int*)(0x42C809C8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A19 *((volatile unsigned int*)(0x42C809CCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A20 *((volatile unsigned int*)(0x42C809D0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A21 *((volatile unsigned int*)(0x42C809D4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A22 *((volatile unsigned int*)(0x42C809D8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A23 *((volatile unsigned int*)(0x42C809DCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A24 *((volatile unsigned int*)(0x42C809E0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A25 *((volatile unsigned int*)(0x42C809E4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A26 *((volatile unsigned int*)(0x42C809E8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A27 *((volatile unsigned int*)(0x42C809ECUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A28 *((volatile unsigned int*)(0x42C809F0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A29 *((volatile unsigned int*)(0x42C809F4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A30 *((volatile unsigned int*)(0x42C809F8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A31 *((volatile unsigned int*)(0x42C809FCUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A32 *((volatile unsigned int*)(0x42C80A00UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A33 *((volatile unsigned int*)(0x42C80A04UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A34 *((volatile unsigned int*)(0x42C80A08UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A35 *((volatile unsigned int*)(0x42C80A0CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A36 *((volatile unsigned int*)(0x42C80A10UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A37 *((volatile unsigned int*)(0x42C80A14UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A38 *((volatile unsigned int*)(0x42C80A18UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A39 *((volatile unsigned int*)(0x42C80A1CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A40 *((volatile unsigned int*)(0x42C80A20UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A41 *((volatile unsigned int*)(0x42C80A24UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A42 *((volatile unsigned int*)(0x42C80A28UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A43 *((volatile unsigned int*)(0x42C80A2CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A44 *((volatile unsigned int*)(0x42C80A30UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A45 *((volatile unsigned int*)(0x42C80A34UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A46 *((volatile unsigned int*)(0x42C80A38UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A47 *((volatile unsigned int*)(0x42C80A3CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC0 *((volatile unsigned int*)(0x42C80A60UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC1 *((volatile unsigned int*)(0x42C80A64UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC2 *((volatile unsigned int*)(0x42C80A68UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC3 *((volatile unsigned int*)(0x42C80A6CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC4 *((volatile unsigned int*)(0x42C80A70UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC5 *((volatile unsigned int*)(0x42C80A74UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_SA *((volatile unsigned int*)(0x42C80A78UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_AE *((volatile unsigned int*)(0x42C80A7CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A0 *((volatile unsigned int*)(0x42C80A80UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A1 *((volatile unsigned int*)(0x42C80A84UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A2 *((volatile unsigned int*)(0x42C80A88UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A3 *((volatile unsigned int*)(0x42C80A8CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A4 *((volatile unsigned int*)(0x42C80A90UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A5 *((volatile unsigned int*)(0x42C80A94UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A6 *((volatile unsigned int*)(0x42C80A98UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A7 *((volatile unsigned int*)(0x42C80A9CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A8 *((volatile unsigned int*)(0x42C80AA0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A9 *((volatile unsigned int*)(0x42C80AA4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A10 *((volatile unsigned int*)(0x42C80AA8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A11 *((volatile unsigned int*)(0x42C80AACUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A12 *((volatile unsigned int*)(0x42C80AB0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A13 *((volatile unsigned int*)(0x42C80AB4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A14 *((volatile unsigned int*)(0x42C80AB8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A15 *((volatile unsigned int*)(0x42C80ABCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A16 *((volatile unsigned int*)(0x42C80AC0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A17 *((volatile unsigned int*)(0x42C80AC4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A18 *((volatile unsigned int*)(0x42C80AC8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A19 *((volatile unsigned int*)(0x42C80ACCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A20 *((volatile unsigned int*)(0x42C80AD0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A21 *((volatile unsigned int*)(0x42C80AD4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A22 *((volatile unsigned int*)(0x42C80AD8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A23 *((volatile unsigned int*)(0x42C80ADCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A24 *((volatile unsigned int*)(0x42C80AE0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A25 *((volatile unsigned int*)(0x42C80AE4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A26 *((volatile unsigned int*)(0x42C80AE8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A27 *((volatile unsigned int*)(0x42C80AECUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A28 *((volatile unsigned int*)(0x42C80AF0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A29 *((volatile unsigned int*)(0x42C80AF4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A30 *((volatile unsigned int*)(0x42C80AF8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A31 *((volatile unsigned int*)(0x42C80AFCUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A32 *((volatile unsigned int*)(0x42C80B00UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A33 *((volatile unsigned int*)(0x42C80B04UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A34 *((volatile unsigned int*)(0x42C80B08UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A35 *((volatile unsigned int*)(0x42C80B0CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A36 *((volatile unsigned int*)(0x42C80B10UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A37 *((volatile unsigned int*)(0x42C80B14UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A38 *((volatile unsigned int*)(0x42C80B18UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A39 *((volatile unsigned int*)(0x42C80B1CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A40 *((volatile unsigned int*)(0x42C80B20UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A41 *((volatile unsigned int*)(0x42C80B24UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A42 *((volatile unsigned int*)(0x42C80B28UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A43 *((volatile unsigned int*)(0x42C80B2CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A44 *((volatile unsigned int*)(0x42C80B30UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A45 *((volatile unsigned int*)(0x42C80B34UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A46 *((volatile unsigned int*)(0x42C80B38UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A47 *((volatile unsigned int*)(0x42C80B3CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC0 *((volatile unsigned int*)(0x42C80B60UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC1 *((volatile unsigned int*)(0x42C80B64UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC2 *((volatile unsigned int*)(0x42C80B68UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC3 *((volatile unsigned int*)(0x42C80B6CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC4 *((volatile unsigned int*)(0x42C80B70UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC5 *((volatile unsigned int*)(0x42C80B74UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_SA *((volatile unsigned int*)(0x42C80B78UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_AE *((volatile unsigned int*)(0x42C80B7CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A0 *((volatile unsigned int*)(0x42C80B80UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A1 *((volatile unsigned int*)(0x42C80B84UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A2 *((volatile unsigned int*)(0x42C80B88UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A3 *((volatile unsigned int*)(0x42C80B8CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A4 *((volatile unsigned int*)(0x42C80B90UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A5 *((volatile unsigned int*)(0x42C80B94UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A6 *((volatile unsigned int*)(0x42C80B98UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A7 *((volatile unsigned int*)(0x42C80B9CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A8 *((volatile unsigned int*)(0x42C80BA0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A9 *((volatile unsigned int*)(0x42C80BA4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A10 *((volatile unsigned int*)(0x42C80BA8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A11 *((volatile unsigned int*)(0x42C80BACUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A12 *((volatile unsigned int*)(0x42C80BB0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A13 *((volatile unsigned int*)(0x42C80BB4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A14 *((volatile unsigned int*)(0x42C80BB8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A15 *((volatile unsigned int*)(0x42C80BBCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A16 *((volatile unsigned int*)(0x42C80BC0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A17 *((volatile unsigned int*)(0x42C80BC4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A18 *((volatile unsigned int*)(0x42C80BC8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A19 *((volatile unsigned int*)(0x42C80BCCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A20 *((volatile unsigned int*)(0x42C80BD0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A21 *((volatile unsigned int*)(0x42C80BD4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A22 *((volatile unsigned int*)(0x42C80BD8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A23 *((volatile unsigned int*)(0x42C80BDCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A24 *((volatile unsigned int*)(0x42C80BE0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A25 *((volatile unsigned int*)(0x42C80BE4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A26 *((volatile unsigned int*)(0x42C80BE8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A27 *((volatile unsigned int*)(0x42C80BECUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A28 *((volatile unsigned int*)(0x42C80BF0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A29 *((volatile unsigned int*)(0x42C80BF4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A30 *((volatile unsigned int*)(0x42C80BF8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A31 *((volatile unsigned int*)(0x42C80BFCUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A32 *((volatile unsigned int*)(0x42C80C00UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A33 *((volatile unsigned int*)(0x42C80C04UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A34 *((volatile unsigned int*)(0x42C80C08UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A35 *((volatile unsigned int*)(0x42C80C0CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A36 *((volatile unsigned int*)(0x42C80C10UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A37 *((volatile unsigned int*)(0x42C80C14UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A38 *((volatile unsigned int*)(0x42C80C18UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A39 *((volatile unsigned int*)(0x42C80C1CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A40 *((volatile unsigned int*)(0x42C80C20UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A41 *((volatile unsigned int*)(0x42C80C24UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A42 *((volatile unsigned int*)(0x42C80C28UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A43 *((volatile unsigned int*)(0x42C80C2CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A44 *((volatile unsigned int*)(0x42C80C30UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A45 *((volatile unsigned int*)(0x42C80C34UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A46 *((volatile unsigned int*)(0x42C80C38UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A47 *((volatile unsigned int*)(0x42C80C3CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC0 *((volatile unsigned int*)(0x42C80C60UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC1 *((volatile unsigned int*)(0x42C80C64UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC2 *((volatile unsigned int*)(0x42C80C68UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC3 *((volatile unsigned int*)(0x42C80C6CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC4 *((volatile unsigned int*)(0x42C80C70UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC5 *((volatile unsigned int*)(0x42C80C74UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_SA *((volatile unsigned int*)(0x42C80C78UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_AE *((volatile unsigned int*)(0x42C80C7CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A0 *((volatile unsigned int*)(0x42C80C80UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A1 *((volatile unsigned int*)(0x42C80C84UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A2 *((volatile unsigned int*)(0x42C80C88UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A3 *((volatile unsigned int*)(0x42C80C8CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A4 *((volatile unsigned int*)(0x42C80C90UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A5 *((volatile unsigned int*)(0x42C80C94UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A6 *((volatile unsigned int*)(0x42C80C98UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A7 *((volatile unsigned int*)(0x42C80C9CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A8 *((volatile unsigned int*)(0x42C80CA0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A9 *((volatile unsigned int*)(0x42C80CA4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A10 *((volatile unsigned int*)(0x42C80CA8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A11 *((volatile unsigned int*)(0x42C80CACUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A12 *((volatile unsigned int*)(0x42C80CB0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A13 *((volatile unsigned int*)(0x42C80CB4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A14 *((volatile unsigned int*)(0x42C80CB8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A15 *((volatile unsigned int*)(0x42C80CBCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A16 *((volatile unsigned int*)(0x42C80CC0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A17 *((volatile unsigned int*)(0x42C80CC4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A18 *((volatile unsigned int*)(0x42C80CC8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A19 *((volatile unsigned int*)(0x42C80CCCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A20 *((volatile unsigned int*)(0x42C80CD0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A21 *((volatile unsigned int*)(0x42C80CD4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A22 *((volatile unsigned int*)(0x42C80CD8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A23 *((volatile unsigned int*)(0x42C80CDCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A24 *((volatile unsigned int*)(0x42C80CE0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A25 *((volatile unsigned int*)(0x42C80CE4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A26 *((volatile unsigned int*)(0x42C80CE8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A27 *((volatile unsigned int*)(0x42C80CECUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A28 *((volatile unsigned int*)(0x42C80CF0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A29 *((volatile unsigned int*)(0x42C80CF4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A30 *((volatile unsigned int*)(0x42C80CF8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A31 *((volatile unsigned int*)(0x42C80CFCUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A32 *((volatile unsigned int*)(0x42C80D00UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A33 *((volatile unsigned int*)(0x42C80D04UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A34 *((volatile unsigned int*)(0x42C80D08UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A35 *((volatile unsigned int*)(0x42C80D0CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A36 *((volatile unsigned int*)(0x42C80D10UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A37 *((volatile unsigned int*)(0x42C80D14UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A38 *((volatile unsigned int*)(0x42C80D18UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A39 *((volatile unsigned int*)(0x42C80D1CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A40 *((volatile unsigned int*)(0x42C80D20UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A41 *((volatile unsigned int*)(0x42C80D24UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A42 *((volatile unsigned int*)(0x42C80D28UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A43 *((volatile unsigned int*)(0x42C80D2CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A44 *((volatile unsigned int*)(0x42C80D30UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A45 *((volatile unsigned int*)(0x42C80D34UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A46 *((volatile unsigned int*)(0x42C80D38UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A47 *((volatile unsigned int*)(0x42C80D3CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC0 *((volatile unsigned int*)(0x42C80D60UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC1 *((volatile unsigned int*)(0x42C80D64UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC2 *((volatile unsigned int*)(0x42C80D68UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC3 *((volatile unsigned int*)(0x42C80D6CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC4 *((volatile unsigned int*)(0x42C80D70UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC5 *((volatile unsigned int*)(0x42C80D74UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_SA *((volatile unsigned int*)(0x42C80D78UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_AE *((volatile unsigned int*)(0x42C80D7CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A0 *((volatile unsigned int*)(0x42C80D80UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A1 *((volatile unsigned int*)(0x42C80D84UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A2 *((volatile unsigned int*)(0x42C80D88UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A3 *((volatile unsigned int*)(0x42C80D8CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A4 *((volatile unsigned int*)(0x42C80D90UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A5 *((volatile unsigned int*)(0x42C80D94UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A6 *((volatile unsigned int*)(0x42C80D98UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A7 *((volatile unsigned int*)(0x42C80D9CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A8 *((volatile unsigned int*)(0x42C80DA0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A9 *((volatile unsigned int*)(0x42C80DA4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A10 *((volatile unsigned int*)(0x42C80DA8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A11 *((volatile unsigned int*)(0x42C80DACUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A12 *((volatile unsigned int*)(0x42C80DB0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A13 *((volatile unsigned int*)(0x42C80DB4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A14 *((volatile unsigned int*)(0x42C80DB8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A15 *((volatile unsigned int*)(0x42C80DBCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A16 *((volatile unsigned int*)(0x42C80DC0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A17 *((volatile unsigned int*)(0x42C80DC4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A18 *((volatile unsigned int*)(0x42C80DC8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A19 *((volatile unsigned int*)(0x42C80DCCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A20 *((volatile unsigned int*)(0x42C80DD0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A21 *((volatile unsigned int*)(0x42C80DD4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A22 *((volatile unsigned int*)(0x42C80DD8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A23 *((volatile unsigned int*)(0x42C80DDCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A24 *((volatile unsigned int*)(0x42C80DE0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A25 *((volatile unsigned int*)(0x42C80DE4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A26 *((volatile unsigned int*)(0x42C80DE8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A27 *((volatile unsigned int*)(0x42C80DECUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A28 *((volatile unsigned int*)(0x42C80DF0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A29 *((volatile unsigned int*)(0x42C80DF4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A30 *((volatile unsigned int*)(0x42C80DF8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A31 *((volatile unsigned int*)(0x42C80DFCUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A32 *((volatile unsigned int*)(0x42C80E00UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A33 *((volatile unsigned int*)(0x42C80E04UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A34 *((volatile unsigned int*)(0x42C80E08UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A35 *((volatile unsigned int*)(0x42C80E0CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A36 *((volatile unsigned int*)(0x42C80E10UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A37 *((volatile unsigned int*)(0x42C80E14UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A38 *((volatile unsigned int*)(0x42C80E18UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A39 *((volatile unsigned int*)(0x42C80E1CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A40 *((volatile unsigned int*)(0x42C80E20UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A41 *((volatile unsigned int*)(0x42C80E24UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A42 *((volatile unsigned int*)(0x42C80E28UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A43 *((volatile unsigned int*)(0x42C80E2CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A44 *((volatile unsigned int*)(0x42C80E30UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A45 *((volatile unsigned int*)(0x42C80E34UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A46 *((volatile unsigned int*)(0x42C80E38UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A47 *((volatile unsigned int*)(0x42C80E3CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC0 *((volatile unsigned int*)(0x42C80E60UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC1 *((volatile unsigned int*)(0x42C80E64UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC2 *((volatile unsigned int*)(0x42C80E68UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC3 *((volatile unsigned int*)(0x42C80E6CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC4 *((volatile unsigned int*)(0x42C80E70UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC5 *((volatile unsigned int*)(0x42C80E74UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_SA *((volatile unsigned int*)(0x42C80E78UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_AE *((volatile unsigned int*)(0x42C80E7CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A0 *((volatile unsigned int*)(0x42C80E80UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A1 *((volatile unsigned int*)(0x42C80E84UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A2 *((volatile unsigned int*)(0x42C80E88UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A3 *((volatile unsigned int*)(0x42C80E8CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A4 *((volatile unsigned int*)(0x42C80E90UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A5 *((volatile unsigned int*)(0x42C80E94UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A6 *((volatile unsigned int*)(0x42C80E98UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A7 *((volatile unsigned int*)(0x42C80E9CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A8 *((volatile unsigned int*)(0x42C80EA0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A9 *((volatile unsigned int*)(0x42C80EA4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A10 *((volatile unsigned int*)(0x42C80EA8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A11 *((volatile unsigned int*)(0x42C80EACUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A12 *((volatile unsigned int*)(0x42C80EB0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A13 *((volatile unsigned int*)(0x42C80EB4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A14 *((volatile unsigned int*)(0x42C80EB8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A15 *((volatile unsigned int*)(0x42C80EBCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A16 *((volatile unsigned int*)(0x42C80EC0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A17 *((volatile unsigned int*)(0x42C80EC4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A18 *((volatile unsigned int*)(0x42C80EC8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A19 *((volatile unsigned int*)(0x42C80ECCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A20 *((volatile unsigned int*)(0x42C80ED0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A21 *((volatile unsigned int*)(0x42C80ED4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A22 *((volatile unsigned int*)(0x42C80ED8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A23 *((volatile unsigned int*)(0x42C80EDCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A24 *((volatile unsigned int*)(0x42C80EE0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A25 *((volatile unsigned int*)(0x42C80EE4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A26 *((volatile unsigned int*)(0x42C80EE8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A27 *((volatile unsigned int*)(0x42C80EECUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A28 *((volatile unsigned int*)(0x42C80EF0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A29 *((volatile unsigned int*)(0x42C80EF4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A30 *((volatile unsigned int*)(0x42C80EF8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A31 *((volatile unsigned int*)(0x42C80EFCUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A32 *((volatile unsigned int*)(0x42C80F00UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A33 *((volatile unsigned int*)(0x42C80F04UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A34 *((volatile unsigned int*)(0x42C80F08UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A35 *((volatile unsigned int*)(0x42C80F0CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A36 *((volatile unsigned int*)(0x42C80F10UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A37 *((volatile unsigned int*)(0x42C80F14UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A38 *((volatile unsigned int*)(0x42C80F18UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A39 *((volatile unsigned int*)(0x42C80F1CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A40 *((volatile unsigned int*)(0x42C80F20UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A41 *((volatile unsigned int*)(0x42C80F24UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A42 *((volatile unsigned int*)(0x42C80F28UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A43 *((volatile unsigned int*)(0x42C80F2CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A44 *((volatile unsigned int*)(0x42C80F30UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A45 *((volatile unsigned int*)(0x42C80F34UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A46 *((volatile unsigned int*)(0x42C80F38UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A47 *((volatile unsigned int*)(0x42C80F3CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC0 *((volatile unsigned int*)(0x42C80F60UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC1 *((volatile unsigned int*)(0x42C80F64UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC2 *((volatile unsigned int*)(0x42C80F68UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC3 *((volatile unsigned int*)(0x42C80F6CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC4 *((volatile unsigned int*)(0x42C80F70UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC5 *((volatile unsigned int*)(0x42C80F74UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_SA *((volatile unsigned int*)(0x42C80F78UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_AE *((volatile unsigned int*)(0x42C80F7CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A0 *((volatile unsigned int*)(0x42C80F80UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A1 *((volatile unsigned int*)(0x42C80F84UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A2 *((volatile unsigned int*)(0x42C80F88UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A3 *((volatile unsigned int*)(0x42C80F8CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A4 *((volatile unsigned int*)(0x42C80F90UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A5 *((volatile unsigned int*)(0x42C80F94UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A6 *((volatile unsigned int*)(0x42C80F98UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A7 *((volatile unsigned int*)(0x42C80F9CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A8 *((volatile unsigned int*)(0x42C80FA0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A9 *((volatile unsigned int*)(0x42C80FA4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A10 *((volatile unsigned int*)(0x42C80FA8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A11 *((volatile unsigned int*)(0x42C80FACUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A12 *((volatile unsigned int*)(0x42C80FB0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A13 *((volatile unsigned int*)(0x42C80FB4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A14 *((volatile unsigned int*)(0x42C80FB8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A15 *((volatile unsigned int*)(0x42C80FBCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A16 *((volatile unsigned int*)(0x42C80FC0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A17 *((volatile unsigned int*)(0x42C80FC4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A18 *((volatile unsigned int*)(0x42C80FC8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A19 *((volatile unsigned int*)(0x42C80FCCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A20 *((volatile unsigned int*)(0x42C80FD0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A21 *((volatile unsigned int*)(0x42C80FD4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A22 *((volatile unsigned int*)(0x42C80FD8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A23 *((volatile unsigned int*)(0x42C80FDCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A24 *((volatile unsigned int*)(0x42C80FE0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A25 *((volatile unsigned int*)(0x42C80FE4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A26 *((volatile unsigned int*)(0x42C80FE8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A27 *((volatile unsigned int*)(0x42C80FECUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A28 *((volatile unsigned int*)(0x42C80FF0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A29 *((volatile unsigned int*)(0x42C80FF4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A30 *((volatile unsigned int*)(0x42C80FF8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A31 *((volatile unsigned int*)(0x42C80FFCUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A32 *((volatile unsigned int*)(0x42C81000UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A33 *((volatile unsigned int*)(0x42C81004UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A34 *((volatile unsigned int*)(0x42C81008UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A35 *((volatile unsigned int*)(0x42C8100CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A36 *((volatile unsigned int*)(0x42C81010UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A37 *((volatile unsigned int*)(0x42C81014UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A38 *((volatile unsigned int*)(0x42C81018UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A39 *((volatile unsigned int*)(0x42C8101CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A40 *((volatile unsigned int*)(0x42C81020UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A41 *((volatile unsigned int*)(0x42C81024UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A42 *((volatile unsigned int*)(0x42C81028UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A43 *((volatile unsigned int*)(0x42C8102CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A44 *((volatile unsigned int*)(0x42C81030UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A45 *((volatile unsigned int*)(0x42C81034UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A46 *((volatile unsigned int*)(0x42C81038UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A47 *((volatile unsigned int*)(0x42C8103CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC0 *((volatile unsigned int*)(0x42C81060UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC1 *((volatile unsigned int*)(0x42C81064UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC2 *((volatile unsigned int*)(0x42C81068UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC3 *((volatile unsigned int*)(0x42C8106CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC4 *((volatile unsigned int*)(0x42C81070UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC5 *((volatile unsigned int*)(0x42C81074UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_SA *((volatile unsigned int*)(0x42C81078UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_AE *((volatile unsigned int*)(0x42C8107CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A0 *((volatile unsigned int*)(0x42C81080UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A1 *((volatile unsigned int*)(0x42C81084UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A2 *((volatile unsigned int*)(0x42C81088UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A3 *((volatile unsigned int*)(0x42C8108CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A4 *((volatile unsigned int*)(0x42C81090UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A5 *((volatile unsigned int*)(0x42C81094UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A6 *((volatile unsigned int*)(0x42C81098UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A7 *((volatile unsigned int*)(0x42C8109CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A8 *((volatile unsigned int*)(0x42C810A0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A9 *((volatile unsigned int*)(0x42C810A4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A10 *((volatile unsigned int*)(0x42C810A8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A11 *((volatile unsigned int*)(0x42C810ACUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A12 *((volatile unsigned int*)(0x42C810B0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A13 *((volatile unsigned int*)(0x42C810B4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A14 *((volatile unsigned int*)(0x42C810B8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A15 *((volatile unsigned int*)(0x42C810BCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A16 *((volatile unsigned int*)(0x42C810C0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A17 *((volatile unsigned int*)(0x42C810C4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A18 *((volatile unsigned int*)(0x42C810C8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A19 *((volatile unsigned int*)(0x42C810CCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A20 *((volatile unsigned int*)(0x42C810D0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A21 *((volatile unsigned int*)(0x42C810D4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A22 *((volatile unsigned int*)(0x42C810D8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A23 *((volatile unsigned int*)(0x42C810DCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A24 *((volatile unsigned int*)(0x42C810E0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A25 *((volatile unsigned int*)(0x42C810E4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A26 *((volatile unsigned int*)(0x42C810E8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A27 *((volatile unsigned int*)(0x42C810ECUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A28 *((volatile unsigned int*)(0x42C810F0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A29 *((volatile unsigned int*)(0x42C810F4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A30 *((volatile unsigned int*)(0x42C810F8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A31 *((volatile unsigned int*)(0x42C810FCUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A32 *((volatile unsigned int*)(0x42C81100UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A33 *((volatile unsigned int*)(0x42C81104UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A34 *((volatile unsigned int*)(0x42C81108UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A35 *((volatile unsigned int*)(0x42C8110CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A36 *((volatile unsigned int*)(0x42C81110UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A37 *((volatile unsigned int*)(0x42C81114UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A38 *((volatile unsigned int*)(0x42C81118UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A39 *((volatile unsigned int*)(0x42C8111CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A40 *((volatile unsigned int*)(0x42C81120UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A41 *((volatile unsigned int*)(0x42C81124UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A42 *((volatile unsigned int*)(0x42C81128UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A43 *((volatile unsigned int*)(0x42C8112CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A44 *((volatile unsigned int*)(0x42C81130UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A45 *((volatile unsigned int*)(0x42C81134UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A46 *((volatile unsigned int*)(0x42C81138UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A47 *((volatile unsigned int*)(0x42C8113CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC0 *((volatile unsigned int*)(0x42C81160UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC1 *((volatile unsigned int*)(0x42C81164UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC2 *((volatile unsigned int*)(0x42C81168UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC3 *((volatile unsigned int*)(0x42C8116CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC4 *((volatile unsigned int*)(0x42C81170UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC5 *((volatile unsigned int*)(0x42C81174UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_SA *((volatile unsigned int*)(0x42C81178UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_AE *((volatile unsigned int*)(0x42C8117CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A0 *((volatile unsigned int*)(0x42C81180UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A1 *((volatile unsigned int*)(0x42C81184UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A2 *((volatile unsigned int*)(0x42C81188UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A3 *((volatile unsigned int*)(0x42C8118CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A4 *((volatile unsigned int*)(0x42C81190UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A5 *((volatile unsigned int*)(0x42C81194UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A6 *((volatile unsigned int*)(0x42C81198UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A7 *((volatile unsigned int*)(0x42C8119CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A8 *((volatile unsigned int*)(0x42C811A0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A9 *((volatile unsigned int*)(0x42C811A4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A10 *((volatile unsigned int*)(0x42C811A8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A11 *((volatile unsigned int*)(0x42C811ACUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A12 *((volatile unsigned int*)(0x42C811B0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A13 *((volatile unsigned int*)(0x42C811B4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A14 *((volatile unsigned int*)(0x42C811B8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A15 *((volatile unsigned int*)(0x42C811BCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A16 *((volatile unsigned int*)(0x42C811C0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A17 *((volatile unsigned int*)(0x42C811C4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A18 *((volatile unsigned int*)(0x42C811C8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A19 *((volatile unsigned int*)(0x42C811CCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A20 *((volatile unsigned int*)(0x42C811D0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A21 *((volatile unsigned int*)(0x42C811D4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A22 *((volatile unsigned int*)(0x42C811D8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A23 *((volatile unsigned int*)(0x42C811DCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A24 *((volatile unsigned int*)(0x42C811E0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A25 *((volatile unsigned int*)(0x42C811E4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A26 *((volatile unsigned int*)(0x42C811E8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A27 *((volatile unsigned int*)(0x42C811ECUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A28 *((volatile unsigned int*)(0x42C811F0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A29 *((volatile unsigned int*)(0x42C811F4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A30 *((volatile unsigned int*)(0x42C811F8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A31 *((volatile unsigned int*)(0x42C811FCUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A32 *((volatile unsigned int*)(0x42C81200UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A33 *((volatile unsigned int*)(0x42C81204UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A34 *((volatile unsigned int*)(0x42C81208UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A35 *((volatile unsigned int*)(0x42C8120CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A36 *((volatile unsigned int*)(0x42C81210UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A37 *((volatile unsigned int*)(0x42C81214UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A38 *((volatile unsigned int*)(0x42C81218UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A39 *((volatile unsigned int*)(0x42C8121CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A40 *((volatile unsigned int*)(0x42C81220UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A41 *((volatile unsigned int*)(0x42C81224UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A42 *((volatile unsigned int*)(0x42C81228UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A43 *((volatile unsigned int*)(0x42C8122CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A44 *((volatile unsigned int*)(0x42C81230UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A45 *((volatile unsigned int*)(0x42C81234UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A46 *((volatile unsigned int*)(0x42C81238UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A47 *((volatile unsigned int*)(0x42C8123CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC0 *((volatile unsigned int*)(0x42C81260UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC1 *((volatile unsigned int*)(0x42C81264UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC2 *((volatile unsigned int*)(0x42C81268UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC3 *((volatile unsigned int*)(0x42C8126CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC4 *((volatile unsigned int*)(0x42C81270UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC5 *((volatile unsigned int*)(0x42C81274UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_SA *((volatile unsigned int*)(0x42C81278UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_AE *((volatile unsigned int*)(0x42C8127CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A0 *((volatile unsigned int*)(0x42C81280UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A1 *((volatile unsigned int*)(0x42C81284UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A2 *((volatile unsigned int*)(0x42C81288UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A3 *((volatile unsigned int*)(0x42C8128CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A4 *((volatile unsigned int*)(0x42C81290UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A5 *((volatile unsigned int*)(0x42C81294UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A6 *((volatile unsigned int*)(0x42C81298UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A7 *((volatile unsigned int*)(0x42C8129CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A8 *((volatile unsigned int*)(0x42C812A0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A9 *((volatile unsigned int*)(0x42C812A4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A10 *((volatile unsigned int*)(0x42C812A8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A11 *((volatile unsigned int*)(0x42C812ACUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A12 *((volatile unsigned int*)(0x42C812B0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A13 *((volatile unsigned int*)(0x42C812B4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A14 *((volatile unsigned int*)(0x42C812B8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A15 *((volatile unsigned int*)(0x42C812BCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A16 *((volatile unsigned int*)(0x42C812C0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A17 *((volatile unsigned int*)(0x42C812C4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A18 *((volatile unsigned int*)(0x42C812C8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A19 *((volatile unsigned int*)(0x42C812CCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A20 *((volatile unsigned int*)(0x42C812D0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A21 *((volatile unsigned int*)(0x42C812D4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A22 *((volatile unsigned int*)(0x42C812D8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A23 *((volatile unsigned int*)(0x42C812DCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A24 *((volatile unsigned int*)(0x42C812E0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A25 *((volatile unsigned int*)(0x42C812E4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A26 *((volatile unsigned int*)(0x42C812E8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A27 *((volatile unsigned int*)(0x42C812ECUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A28 *((volatile unsigned int*)(0x42C812F0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A29 *((volatile unsigned int*)(0x42C812F4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A30 *((volatile unsigned int*)(0x42C812F8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A31 *((volatile unsigned int*)(0x42C812FCUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A32 *((volatile unsigned int*)(0x42C81300UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A33 *((volatile unsigned int*)(0x42C81304UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A34 *((volatile unsigned int*)(0x42C81308UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A35 *((volatile unsigned int*)(0x42C8130CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A36 *((volatile unsigned int*)(0x42C81310UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A37 *((volatile unsigned int*)(0x42C81314UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A38 *((volatile unsigned int*)(0x42C81318UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A39 *((volatile unsigned int*)(0x42C8131CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A40 *((volatile unsigned int*)(0x42C81320UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A41 *((volatile unsigned int*)(0x42C81324UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A42 *((volatile unsigned int*)(0x42C81328UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A43 *((volatile unsigned int*)(0x42C8132CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A44 *((volatile unsigned int*)(0x42C81330UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A45 *((volatile unsigned int*)(0x42C81334UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A46 *((volatile unsigned int*)(0x42C81338UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A47 *((volatile unsigned int*)(0x42C8133CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC0 *((volatile unsigned int*)(0x42C81360UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC1 *((volatile unsigned int*)(0x42C81364UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC2 *((volatile unsigned int*)(0x42C81368UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC3 *((volatile unsigned int*)(0x42C8136CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC4 *((volatile unsigned int*)(0x42C81370UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC5 *((volatile unsigned int*)(0x42C81374UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_SA *((volatile unsigned int*)(0x42C81378UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_AE *((volatile unsigned int*)(0x42C8137CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A0 *((volatile unsigned int*)(0x42C81380UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A1 *((volatile unsigned int*)(0x42C81384UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A2 *((volatile unsigned int*)(0x42C81388UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A3 *((volatile unsigned int*)(0x42C8138CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A4 *((volatile unsigned int*)(0x42C81390UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A5 *((volatile unsigned int*)(0x42C81394UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A6 *((volatile unsigned int*)(0x42C81398UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A7 *((volatile unsigned int*)(0x42C8139CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A8 *((volatile unsigned int*)(0x42C813A0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A9 *((volatile unsigned int*)(0x42C813A4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A10 *((volatile unsigned int*)(0x42C813A8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A11 *((volatile unsigned int*)(0x42C813ACUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A12 *((volatile unsigned int*)(0x42C813B0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A13 *((volatile unsigned int*)(0x42C813B4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A14 *((volatile unsigned int*)(0x42C813B8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A15 *((volatile unsigned int*)(0x42C813BCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A16 *((volatile unsigned int*)(0x42C813C0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A17 *((volatile unsigned int*)(0x42C813C4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A18 *((volatile unsigned int*)(0x42C813C8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A19 *((volatile unsigned int*)(0x42C813CCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A20 *((volatile unsigned int*)(0x42C813D0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A21 *((volatile unsigned int*)(0x42C813D4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A22 *((volatile unsigned int*)(0x42C813D8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A23 *((volatile unsigned int*)(0x42C813DCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A24 *((volatile unsigned int*)(0x42C813E0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A25 *((volatile unsigned int*)(0x42C813E4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A26 *((volatile unsigned int*)(0x42C813E8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A27 *((volatile unsigned int*)(0x42C813ECUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A28 *((volatile unsigned int*)(0x42C813F0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A29 *((volatile unsigned int*)(0x42C813F4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A30 *((volatile unsigned int*)(0x42C813F8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A31 *((volatile unsigned int*)(0x42C813FCUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A32 *((volatile unsigned int*)(0x42C81400UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A33 *((volatile unsigned int*)(0x42C81404UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A34 *((volatile unsigned int*)(0x42C81408UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A35 *((volatile unsigned int*)(0x42C8140CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A36 *((volatile unsigned int*)(0x42C81410UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A37 *((volatile unsigned int*)(0x42C81414UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A38 *((volatile unsigned int*)(0x42C81418UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A39 *((volatile unsigned int*)(0x42C8141CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A40 *((volatile unsigned int*)(0x42C81420UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A41 *((volatile unsigned int*)(0x42C81424UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A42 *((volatile unsigned int*)(0x42C81428UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A43 *((volatile unsigned int*)(0x42C8142CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A44 *((volatile unsigned int*)(0x42C81430UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A45 *((volatile unsigned int*)(0x42C81434UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A46 *((volatile unsigned int*)(0x42C81438UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A47 *((volatile unsigned int*)(0x42C8143CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC0 *((volatile unsigned int*)(0x42C81460UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC1 *((volatile unsigned int*)(0x42C81464UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC2 *((volatile unsigned int*)(0x42C81468UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC3 *((volatile unsigned int*)(0x42C8146CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC4 *((volatile unsigned int*)(0x42C81470UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC5 *((volatile unsigned int*)(0x42C81474UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_SA *((volatile unsigned int*)(0x42C81478UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_AE *((volatile unsigned int*)(0x42C8147CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A0 *((volatile unsigned int*)(0x42C81480UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A1 *((volatile unsigned int*)(0x42C81484UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A2 *((volatile unsigned int*)(0x42C81488UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A3 *((volatile unsigned int*)(0x42C8148CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A4 *((volatile unsigned int*)(0x42C81490UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A5 *((volatile unsigned int*)(0x42C81494UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A6 *((volatile unsigned int*)(0x42C81498UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A7 *((volatile unsigned int*)(0x42C8149CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A8 *((volatile unsigned int*)(0x42C814A0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A9 *((volatile unsigned int*)(0x42C814A4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A10 *((volatile unsigned int*)(0x42C814A8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A11 *((volatile unsigned int*)(0x42C814ACUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A12 *((volatile unsigned int*)(0x42C814B0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A13 *((volatile unsigned int*)(0x42C814B4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A14 *((volatile unsigned int*)(0x42C814B8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A15 *((volatile unsigned int*)(0x42C814BCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A16 *((volatile unsigned int*)(0x42C814C0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A17 *((volatile unsigned int*)(0x42C814C4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A18 *((volatile unsigned int*)(0x42C814C8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A19 *((volatile unsigned int*)(0x42C814CCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A20 *((volatile unsigned int*)(0x42C814D0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A21 *((volatile unsigned int*)(0x42C814D4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A22 *((volatile unsigned int*)(0x42C814D8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A23 *((volatile unsigned int*)(0x42C814DCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A24 *((volatile unsigned int*)(0x42C814E0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A25 *((volatile unsigned int*)(0x42C814E4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A26 *((volatile unsigned int*)(0x42C814E8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A27 *((volatile unsigned int*)(0x42C814ECUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A28 *((volatile unsigned int*)(0x42C814F0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A29 *((volatile unsigned int*)(0x42C814F4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A30 *((volatile unsigned int*)(0x42C814F8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A31 *((volatile unsigned int*)(0x42C814FCUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A32 *((volatile unsigned int*)(0x42C81500UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A33 *((volatile unsigned int*)(0x42C81504UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A34 *((volatile unsigned int*)(0x42C81508UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A35 *((volatile unsigned int*)(0x42C8150CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A36 *((volatile unsigned int*)(0x42C81510UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A37 *((volatile unsigned int*)(0x42C81514UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A38 *((volatile unsigned int*)(0x42C81518UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A39 *((volatile unsigned int*)(0x42C8151CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A40 *((volatile unsigned int*)(0x42C81520UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A41 *((volatile unsigned int*)(0x42C81524UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A42 *((volatile unsigned int*)(0x42C81528UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A43 *((volatile unsigned int*)(0x42C8152CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A44 *((volatile unsigned int*)(0x42C81530UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A45 *((volatile unsigned int*)(0x42C81534UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A46 *((volatile unsigned int*)(0x42C81538UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A47 *((volatile unsigned int*)(0x42C8153CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC0 *((volatile unsigned int*)(0x42C81560UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC1 *((volatile unsigned int*)(0x42C81564UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC2 *((volatile unsigned int*)(0x42C81568UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC3 *((volatile unsigned int*)(0x42C8156CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC4 *((volatile unsigned int*)(0x42C81570UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC5 *((volatile unsigned int*)(0x42C81574UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_SA *((volatile unsigned int*)(0x42C81578UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_AE *((volatile unsigned int*)(0x42C8157CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A0 *((volatile unsigned int*)(0x42C81580UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A1 *((volatile unsigned int*)(0x42C81584UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A2 *((volatile unsigned int*)(0x42C81588UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A3 *((volatile unsigned int*)(0x42C8158CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A4 *((volatile unsigned int*)(0x42C81590UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A5 *((volatile unsigned int*)(0x42C81594UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A6 *((volatile unsigned int*)(0x42C81598UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A7 *((volatile unsigned int*)(0x42C8159CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A8 *((volatile unsigned int*)(0x42C815A0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A9 *((volatile unsigned int*)(0x42C815A4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A10 *((volatile unsigned int*)(0x42C815A8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A11 *((volatile unsigned int*)(0x42C815ACUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A12 *((volatile unsigned int*)(0x42C815B0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A13 *((volatile unsigned int*)(0x42C815B4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A14 *((volatile unsigned int*)(0x42C815B8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A15 *((volatile unsigned int*)(0x42C815BCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A16 *((volatile unsigned int*)(0x42C815C0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A17 *((volatile unsigned int*)(0x42C815C4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A18 *((volatile unsigned int*)(0x42C815C8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A19 *((volatile unsigned int*)(0x42C815CCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A20 *((volatile unsigned int*)(0x42C815D0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A21 *((volatile unsigned int*)(0x42C815D4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A22 *((volatile unsigned int*)(0x42C815D8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A23 *((volatile unsigned int*)(0x42C815DCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A24 *((volatile unsigned int*)(0x42C815E0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A25 *((volatile unsigned int*)(0x42C815E4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A26 *((volatile unsigned int*)(0x42C815E8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A27 *((volatile unsigned int*)(0x42C815ECUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A28 *((volatile unsigned int*)(0x42C815F0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A29 *((volatile unsigned int*)(0x42C815F4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A30 *((volatile unsigned int*)(0x42C815F8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A31 *((volatile unsigned int*)(0x42C815FCUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A32 *((volatile unsigned int*)(0x42C81600UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A33 *((volatile unsigned int*)(0x42C81604UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A34 *((volatile unsigned int*)(0x42C81608UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A35 *((volatile unsigned int*)(0x42C8160CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A36 *((volatile unsigned int*)(0x42C81610UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A37 *((volatile unsigned int*)(0x42C81614UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A38 *((volatile unsigned int*)(0x42C81618UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A39 *((volatile unsigned int*)(0x42C8161CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A40 *((volatile unsigned int*)(0x42C81620UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A41 *((volatile unsigned int*)(0x42C81624UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A42 *((volatile unsigned int*)(0x42C81628UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A43 *((volatile unsigned int*)(0x42C8162CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A44 *((volatile unsigned int*)(0x42C81630UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A45 *((volatile unsigned int*)(0x42C81634UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A46 *((volatile unsigned int*)(0x42C81638UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A47 *((volatile unsigned int*)(0x42C8163CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC0 *((volatile unsigned int*)(0x42C81660UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC1 *((volatile unsigned int*)(0x42C81664UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC2 *((volatile unsigned int*)(0x42C81668UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC3 *((volatile unsigned int*)(0x42C8166CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC4 *((volatile unsigned int*)(0x42C81670UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC5 *((volatile unsigned int*)(0x42C81674UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_SA *((volatile unsigned int*)(0x42C81678UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_AE *((volatile unsigned int*)(0x42C8167CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A0 *((volatile unsigned int*)(0x42C81680UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A1 *((volatile unsigned int*)(0x42C81684UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A2 *((volatile unsigned int*)(0x42C81688UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A3 *((volatile unsigned int*)(0x42C8168CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A4 *((volatile unsigned int*)(0x42C81690UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A5 *((volatile unsigned int*)(0x42C81694UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A6 *((volatile unsigned int*)(0x42C81698UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A7 *((volatile unsigned int*)(0x42C8169CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A8 *((volatile unsigned int*)(0x42C816A0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A9 *((volatile unsigned int*)(0x42C816A4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A10 *((volatile unsigned int*)(0x42C816A8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A11 *((volatile unsigned int*)(0x42C816ACUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A12 *((volatile unsigned int*)(0x42C816B0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A13 *((volatile unsigned int*)(0x42C816B4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A14 *((volatile unsigned int*)(0x42C816B8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A15 *((volatile unsigned int*)(0x42C816BCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A16 *((volatile unsigned int*)(0x42C816C0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A17 *((volatile unsigned int*)(0x42C816C4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A18 *((volatile unsigned int*)(0x42C816C8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A19 *((volatile unsigned int*)(0x42C816CCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A20 *((volatile unsigned int*)(0x42C816D0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A21 *((volatile unsigned int*)(0x42C816D4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A22 *((volatile unsigned int*)(0x42C816D8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A23 *((volatile unsigned int*)(0x42C816DCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A24 *((volatile unsigned int*)(0x42C816E0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A25 *((volatile unsigned int*)(0x42C816E4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A26 *((volatile unsigned int*)(0x42C816E8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A27 *((volatile unsigned int*)(0x42C816ECUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A28 *((volatile unsigned int*)(0x42C816F0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A29 *((volatile unsigned int*)(0x42C816F4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A30 *((volatile unsigned int*)(0x42C816F8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A31 *((volatile unsigned int*)(0x42C816FCUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A32 *((volatile unsigned int*)(0x42C81700UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A33 *((volatile unsigned int*)(0x42C81704UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A34 *((volatile unsigned int*)(0x42C81708UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A35 *((volatile unsigned int*)(0x42C8170CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A36 *((volatile unsigned int*)(0x42C81710UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A37 *((volatile unsigned int*)(0x42C81714UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A38 *((volatile unsigned int*)(0x42C81718UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A39 *((volatile unsigned int*)(0x42C8171CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A40 *((volatile unsigned int*)(0x42C81720UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A41 *((volatile unsigned int*)(0x42C81724UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A42 *((volatile unsigned int*)(0x42C81728UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A43 *((volatile unsigned int*)(0x42C8172CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A44 *((volatile unsigned int*)(0x42C81730UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A45 *((volatile unsigned int*)(0x42C81734UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A46 *((volatile unsigned int*)(0x42C81738UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A47 *((volatile unsigned int*)(0x42C8173CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC0 *((volatile unsigned int*)(0x42C81760UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC1 *((volatile unsigned int*)(0x42C81764UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC2 *((volatile unsigned int*)(0x42C81768UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC3 *((volatile unsigned int*)(0x42C8176CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC4 *((volatile unsigned int*)(0x42C81770UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC5 *((volatile unsigned int*)(0x42C81774UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_SA *((volatile unsigned int*)(0x42C81778UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_AE *((volatile unsigned int*)(0x42C8177CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A0 *((volatile unsigned int*)(0x42C81780UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A1 *((volatile unsigned int*)(0x42C81784UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A2 *((volatile unsigned int*)(0x42C81788UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A3 *((volatile unsigned int*)(0x42C8178CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A4 *((volatile unsigned int*)(0x42C81790UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A5 *((volatile unsigned int*)(0x42C81794UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A6 *((volatile unsigned int*)(0x42C81798UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A7 *((volatile unsigned int*)(0x42C8179CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A8 *((volatile unsigned int*)(0x42C817A0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A9 *((volatile unsigned int*)(0x42C817A4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A10 *((volatile unsigned int*)(0x42C817A8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A11 *((volatile unsigned int*)(0x42C817ACUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A12 *((volatile unsigned int*)(0x42C817B0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A13 *((volatile unsigned int*)(0x42C817B4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A14 *((volatile unsigned int*)(0x42C817B8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A15 *((volatile unsigned int*)(0x42C817BCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A16 *((volatile unsigned int*)(0x42C817C0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A17 *((volatile unsigned int*)(0x42C817C4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A18 *((volatile unsigned int*)(0x42C817C8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A19 *((volatile unsigned int*)(0x42C817CCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A20 *((volatile unsigned int*)(0x42C817D0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A21 *((volatile unsigned int*)(0x42C817D4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A22 *((volatile unsigned int*)(0x42C817D8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A23 *((volatile unsigned int*)(0x42C817DCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A24 *((volatile unsigned int*)(0x42C817E0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A25 *((volatile unsigned int*)(0x42C817E4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A26 *((volatile unsigned int*)(0x42C817E8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A27 *((volatile unsigned int*)(0x42C817ECUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A28 *((volatile unsigned int*)(0x42C817F0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A29 *((volatile unsigned int*)(0x42C817F4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A30 *((volatile unsigned int*)(0x42C817F8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A31 *((volatile unsigned int*)(0x42C817FCUL)) +#define bFM3_ETHERNET_MAC0_RGSR_LM *((volatile unsigned int*)(0x42C81B00UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LSP0 *((volatile unsigned int*)(0x42C81B04UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LSP1 *((volatile unsigned int*)(0x42C81B08UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LS *((volatile unsigned int*)(0x42C81B0CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSE *((volatile unsigned int*)(0x42C8E000UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TFCU *((volatile unsigned int*)(0x42C8E004UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSI *((volatile unsigned int*)(0x42C8E008UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSU *((volatile unsigned int*)(0x42C8E00CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TITE *((volatile unsigned int*)(0x42C8E010UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TARU *((volatile unsigned int*)(0x42C8E014UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSEA *((volatile unsigned int*)(0x42C8E020UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSDB *((volatile unsigned int*)(0x42C8E024UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSV2E *((volatile unsigned int*)(0x42C8E028UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TETSP *((volatile unsigned int*)(0x42C8E02CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E *((volatile unsigned int*)(0x42C8E030UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E *((volatile unsigned int*)(0x42C8E034UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TETSEM *((volatile unsigned int*)(0x42C8E038UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSMRM *((volatile unsigned int*)(0x42C8E03CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSPS0 *((volatile unsigned int*)(0x42C8E040UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSPS1 *((volatile unsigned int*)(0x42C8E044UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSENMF *((volatile unsigned int*)(0x42C8E048UL)) +#define bFM3_ETHERNET_MAC0_TSCR_ATSFC *((volatile unsigned int*)(0x42C8E060UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC0 *((volatile unsigned int*)(0x42C8E080UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC1 *((volatile unsigned int*)(0x42C8E084UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC2 *((volatile unsigned int*)(0x42C8E088UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC3 *((volatile unsigned int*)(0x42C8E08CUL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC4 *((volatile unsigned int*)(0x42C8E090UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC5 *((volatile unsigned int*)(0x42C8E094UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC6 *((volatile unsigned int*)(0x42C8E098UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC7 *((volatile unsigned int*)(0x42C8E09CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS0 *((volatile unsigned int*)(0x42C8E100UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS1 *((volatile unsigned int*)(0x42C8E104UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS2 *((volatile unsigned int*)(0x42C8E108UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS3 *((volatile unsigned int*)(0x42C8E10CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS4 *((volatile unsigned int*)(0x42C8E110UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS5 *((volatile unsigned int*)(0x42C8E114UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS6 *((volatile unsigned int*)(0x42C8E118UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS7 *((volatile unsigned int*)(0x42C8E11CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS8 *((volatile unsigned int*)(0x42C8E120UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS9 *((volatile unsigned int*)(0x42C8E124UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS10 *((volatile unsigned int*)(0x42C8E128UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS11 *((volatile unsigned int*)(0x42C8E12CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS12 *((volatile unsigned int*)(0x42C8E130UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS13 *((volatile unsigned int*)(0x42C8E134UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS14 *((volatile unsigned int*)(0x42C8E138UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS15 *((volatile unsigned int*)(0x42C8E13CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS16 *((volatile unsigned int*)(0x42C8E140UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS17 *((volatile unsigned int*)(0x42C8E144UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS18 *((volatile unsigned int*)(0x42C8E148UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS19 *((volatile unsigned int*)(0x42C8E14CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS20 *((volatile unsigned int*)(0x42C8E150UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS21 *((volatile unsigned int*)(0x42C8E154UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS22 *((volatile unsigned int*)(0x42C8E158UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS23 *((volatile unsigned int*)(0x42C8E15CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS24 *((volatile unsigned int*)(0x42C8E160UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS25 *((volatile unsigned int*)(0x42C8E164UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS26 *((volatile unsigned int*)(0x42C8E168UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS27 *((volatile unsigned int*)(0x42C8E16CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS28 *((volatile unsigned int*)(0x42C8E170UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS29 *((volatile unsigned int*)(0x42C8E174UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS30 *((volatile unsigned int*)(0x42C8E178UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS31 *((volatile unsigned int*)(0x42C8E17CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS0 *((volatile unsigned int*)(0x42C8E080UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS1 *((volatile unsigned int*)(0x42C8E084UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS2 *((volatile unsigned int*)(0x42C8E088UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS3 *((volatile unsigned int*)(0x42C8E08CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS4 *((volatile unsigned int*)(0x42C8E090UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS5 *((volatile unsigned int*)(0x42C8E094UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS6 *((volatile unsigned int*)(0x42C8E098UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS7 *((volatile unsigned int*)(0x42C8E09CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS8 *((volatile unsigned int*)(0x42C8E0A0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS9 *((volatile unsigned int*)(0x42C8E0A4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS10 *((volatile unsigned int*)(0x42C8E0A8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS11 *((volatile unsigned int*)(0x42C8E0ACUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS12 *((volatile unsigned int*)(0x42C8E0B0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS13 *((volatile unsigned int*)(0x42C8E0B4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS14 *((volatile unsigned int*)(0x42C8E0B8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS15 *((volatile unsigned int*)(0x42C8E0BCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS16 *((volatile unsigned int*)(0x42C8E0C0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS17 *((volatile unsigned int*)(0x42C8E0C4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS18 *((volatile unsigned int*)(0x42C8E0C8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS19 *((volatile unsigned int*)(0x42C8E0CCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS20 *((volatile unsigned int*)(0x42C8E0D0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS21 *((volatile unsigned int*)(0x42C8E0D4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS22 *((volatile unsigned int*)(0x42C8E0D8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS23 *((volatile unsigned int*)(0x42C8E0DCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS24 *((volatile unsigned int*)(0x42C8E0E0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS25 *((volatile unsigned int*)(0x42C8E0E4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS26 *((volatile unsigned int*)(0x42C8E0E8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS27 *((volatile unsigned int*)(0x42C8E0ECUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS28 *((volatile unsigned int*)(0x42C8E0F0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS29 *((volatile unsigned int*)(0x42C8E0F4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS30 *((volatile unsigned int*)(0x42C8E0F8UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS0 *((volatile unsigned int*)(0x42C8E200UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS1 *((volatile unsigned int*)(0x42C8E204UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS2 *((volatile unsigned int*)(0x42C8E208UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS3 *((volatile unsigned int*)(0x42C8E20CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS4 *((volatile unsigned int*)(0x42C8E210UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS5 *((volatile unsigned int*)(0x42C8E214UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS6 *((volatile unsigned int*)(0x42C8E218UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS7 *((volatile unsigned int*)(0x42C8E21CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS8 *((volatile unsigned int*)(0x42C8E220UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS9 *((volatile unsigned int*)(0x42C8E224UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS10 *((volatile unsigned int*)(0x42C8E228UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS11 *((volatile unsigned int*)(0x42C8E22CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS12 *((volatile unsigned int*)(0x42C8E230UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS13 *((volatile unsigned int*)(0x42C8E234UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS14 *((volatile unsigned int*)(0x42C8E238UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS15 *((volatile unsigned int*)(0x42C8E23CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS16 *((volatile unsigned int*)(0x42C8E240UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS17 *((volatile unsigned int*)(0x42C8E244UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS18 *((volatile unsigned int*)(0x42C8E248UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS19 *((volatile unsigned int*)(0x42C8E24CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS20 *((volatile unsigned int*)(0x42C8E250UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS21 *((volatile unsigned int*)(0x42C8E254UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS22 *((volatile unsigned int*)(0x42C8E258UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS23 *((volatile unsigned int*)(0x42C8E25CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS24 *((volatile unsigned int*)(0x42C8E260UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS25 *((volatile unsigned int*)(0x42C8E264UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS26 *((volatile unsigned int*)(0x42C8E268UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS27 *((volatile unsigned int*)(0x42C8E26CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS28 *((volatile unsigned int*)(0x42C8E270UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS29 *((volatile unsigned int*)(0x42C8E274UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS30 *((volatile unsigned int*)(0x42C8E278UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS31 *((volatile unsigned int*)(0x42C8E27CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS0 *((volatile unsigned int*)(0x42C8E280UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS1 *((volatile unsigned int*)(0x42C8E284UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS2 *((volatile unsigned int*)(0x42C8E288UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS3 *((volatile unsigned int*)(0x42C8E28CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS4 *((volatile unsigned int*)(0x42C8E290UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS5 *((volatile unsigned int*)(0x42C8E294UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS6 *((volatile unsigned int*)(0x42C8E298UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS7 *((volatile unsigned int*)(0x42C8E29CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS8 *((volatile unsigned int*)(0x42C8E2A0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS9 *((volatile unsigned int*)(0x42C8E2A4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS10 *((volatile unsigned int*)(0x42C8E2A8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS11 *((volatile unsigned int*)(0x42C8E2ACUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS12 *((volatile unsigned int*)(0x42C8E2B0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS13 *((volatile unsigned int*)(0x42C8E2B4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS14 *((volatile unsigned int*)(0x42C8E2B8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS15 *((volatile unsigned int*)(0x42C8E2BCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS16 *((volatile unsigned int*)(0x42C8E2C0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS17 *((volatile unsigned int*)(0x42C8E2C4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS18 *((volatile unsigned int*)(0x42C8E2C8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS19 *((volatile unsigned int*)(0x42C8E2CCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS20 *((volatile unsigned int*)(0x42C8E2D0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS21 *((volatile unsigned int*)(0x42C8E2D4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS22 *((volatile unsigned int*)(0x42C8E2D8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS23 *((volatile unsigned int*)(0x42C8E2DCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS24 *((volatile unsigned int*)(0x42C8E2E0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS25 *((volatile unsigned int*)(0x42C8E2E4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS26 *((volatile unsigned int*)(0x42C8E2E8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS27 *((volatile unsigned int*)(0x42C8E2ECUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS28 *((volatile unsigned int*)(0x42C8E2F0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS29 *((volatile unsigned int*)(0x42C8E2F4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS30 *((volatile unsigned int*)(0x42C8E2F8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB *((volatile unsigned int*)(0x42C8E2FCUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR0 *((volatile unsigned int*)(0x42C8E300UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR1 *((volatile unsigned int*)(0x42C8E304UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR2 *((volatile unsigned int*)(0x42C8E308UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR3 *((volatile unsigned int*)(0x42C8E30CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR4 *((volatile unsigned int*)(0x42C8E310UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR5 *((volatile unsigned int*)(0x42C8E314UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR6 *((volatile unsigned int*)(0x42C8E318UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR7 *((volatile unsigned int*)(0x42C8E31CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR8 *((volatile unsigned int*)(0x42C8E320UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR9 *((volatile unsigned int*)(0x42C8E324UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR10 *((volatile unsigned int*)(0x42C8E328UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR11 *((volatile unsigned int*)(0x42C8E32CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR12 *((volatile unsigned int*)(0x42C8E330UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR13 *((volatile unsigned int*)(0x42C8E334UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR14 *((volatile unsigned int*)(0x42C8E338UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR15 *((volatile unsigned int*)(0x42C8E33CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR16 *((volatile unsigned int*)(0x42C8E340UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR17 *((volatile unsigned int*)(0x42C8E344UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR18 *((volatile unsigned int*)(0x42C8E348UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR19 *((volatile unsigned int*)(0x42C8E34CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR20 *((volatile unsigned int*)(0x42C8E350UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR21 *((volatile unsigned int*)(0x42C8E354UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR22 *((volatile unsigned int*)(0x42C8E358UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR23 *((volatile unsigned int*)(0x42C8E35CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR24 *((volatile unsigned int*)(0x42C8E360UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR25 *((volatile unsigned int*)(0x42C8E364UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR26 *((volatile unsigned int*)(0x42C8E368UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR27 *((volatile unsigned int*)(0x42C8E36CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR28 *((volatile unsigned int*)(0x42C8E370UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR29 *((volatile unsigned int*)(0x42C8E374UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR30 *((volatile unsigned int*)(0x42C8E378UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR31 *((volatile unsigned int*)(0x42C8E37CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR0 *((volatile unsigned int*)(0x42C8E380UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR1 *((volatile unsigned int*)(0x42C8E384UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR2 *((volatile unsigned int*)(0x42C8E388UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR3 *((volatile unsigned int*)(0x42C8E38CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR4 *((volatile unsigned int*)(0x42C8E390UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR5 *((volatile unsigned int*)(0x42C8E394UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR6 *((volatile unsigned int*)(0x42C8E398UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR7 *((volatile unsigned int*)(0x42C8E39CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR8 *((volatile unsigned int*)(0x42C8E3A0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR9 *((volatile unsigned int*)(0x42C8E3A4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR10 *((volatile unsigned int*)(0x42C8E3A8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR11 *((volatile unsigned int*)(0x42C8E3ACUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR12 *((volatile unsigned int*)(0x42C8E3B0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR13 *((volatile unsigned int*)(0x42C8E3B4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR14 *((volatile unsigned int*)(0x42C8E3B8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR15 *((volatile unsigned int*)(0x42C8E3BCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR16 *((volatile unsigned int*)(0x42C8E3C0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR17 *((volatile unsigned int*)(0x42C8E3C4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR18 *((volatile unsigned int*)(0x42C8E3C8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR19 *((volatile unsigned int*)(0x42C8E3CCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR20 *((volatile unsigned int*)(0x42C8E3D0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR21 *((volatile unsigned int*)(0x42C8E3D4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR22 *((volatile unsigned int*)(0x42C8E3D8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR23 *((volatile unsigned int*)(0x42C8E3DCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR24 *((volatile unsigned int*)(0x42C8E3E0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR25 *((volatile unsigned int*)(0x42C8E3E4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR26 *((volatile unsigned int*)(0x42C8E3E8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR27 *((volatile unsigned int*)(0x42C8E3ECUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR28 *((volatile unsigned int*)(0x42C8E3F0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR29 *((volatile unsigned int*)(0x42C8E3F4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR30 *((volatile unsigned int*)(0x42C8E3F8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR31 *((volatile unsigned int*)(0x42C8E3FCUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR0 *((volatile unsigned int*)(0x42C8E400UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR1 *((volatile unsigned int*)(0x42C8E404UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR2 *((volatile unsigned int*)(0x42C8E408UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR3 *((volatile unsigned int*)(0x42C8E40CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR4 *((volatile unsigned int*)(0x42C8E410UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR5 *((volatile unsigned int*)(0x42C8E414UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR6 *((volatile unsigned int*)(0x42C8E418UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR7 *((volatile unsigned int*)(0x42C8E41CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR8 *((volatile unsigned int*)(0x42C8E420UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR9 *((volatile unsigned int*)(0x42C8E424UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR10 *((volatile unsigned int*)(0x42C8E428UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR11 *((volatile unsigned int*)(0x42C8E42CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR12 *((volatile unsigned int*)(0x42C8E430UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR13 *((volatile unsigned int*)(0x42C8E434UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR14 *((volatile unsigned int*)(0x42C8E438UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR15 *((volatile unsigned int*)(0x42C8E43CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR16 *((volatile unsigned int*)(0x42C8E440UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR17 *((volatile unsigned int*)(0x42C8E444UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR18 *((volatile unsigned int*)(0x42C8E448UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR19 *((volatile unsigned int*)(0x42C8E44CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR20 *((volatile unsigned int*)(0x42C8E450UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR21 *((volatile unsigned int*)(0x42C8E454UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR22 *((volatile unsigned int*)(0x42C8E458UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR23 *((volatile unsigned int*)(0x42C8E45CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR24 *((volatile unsigned int*)(0x42C8E460UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR25 *((volatile unsigned int*)(0x42C8E464UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR26 *((volatile unsigned int*)(0x42C8E468UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR27 *((volatile unsigned int*)(0x42C8E46CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR28 *((volatile unsigned int*)(0x42C8E470UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR29 *((volatile unsigned int*)(0x42C8E474UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR30 *((volatile unsigned int*)(0x42C8E478UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42C8E480UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42C8E484UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42C8E488UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42C8E48CUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42C8E490UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42C8E494UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42C8E498UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42C8E49CUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42C8E4A0UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42C8E4A4UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42C8E4A8UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42C8E4ACUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42C8E4B0UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42C8E4B4UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42C8E4B8UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42C8E4BCUL)) +#define bFM3_ETHERNET_MAC0_TSR_TSSOVF *((volatile unsigned int*)(0x42C8E500UL)) +#define bFM3_ETHERNET_MAC0_TSR_TSTART *((volatile unsigned int*)(0x42C8E504UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSTS *((volatile unsigned int*)(0x42C8E508UL)) +#define bFM3_ETHERNET_MAC0_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSSTM *((volatile unsigned int*)(0x42C8E560UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS0 *((volatile unsigned int*)(0x42C8E564UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS1 *((volatile unsigned int*)(0x42C8E568UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS2 *((volatile unsigned int*)(0x42C8E56CUL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42C8E580UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42C8E584UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42C8E588UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42C8E58CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN0 *((volatile unsigned int*)(0x42C8E600UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN1 *((volatile unsigned int*)(0x42C8E604UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN2 *((volatile unsigned int*)(0x42C8E608UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN3 *((volatile unsigned int*)(0x42C8E60CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN4 *((volatile unsigned int*)(0x42C8E610UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN5 *((volatile unsigned int*)(0x42C8E614UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN6 *((volatile unsigned int*)(0x42C8E618UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN7 *((volatile unsigned int*)(0x42C8E61CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN8 *((volatile unsigned int*)(0x42C8E620UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN9 *((volatile unsigned int*)(0x42C8E624UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN10 *((volatile unsigned int*)(0x42C8E628UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN11 *((volatile unsigned int*)(0x42C8E62CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN12 *((volatile unsigned int*)(0x42C8E630UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN13 *((volatile unsigned int*)(0x42C8E634UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN14 *((volatile unsigned int*)(0x42C8E638UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN15 *((volatile unsigned int*)(0x42C8E63CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN16 *((volatile unsigned int*)(0x42C8E640UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN17 *((volatile unsigned int*)(0x42C8E644UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN18 *((volatile unsigned int*)(0x42C8E648UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN19 *((volatile unsigned int*)(0x42C8E64CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN20 *((volatile unsigned int*)(0x42C8E650UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN21 *((volatile unsigned int*)(0x42C8E654UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN22 *((volatile unsigned int*)(0x42C8E658UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN23 *((volatile unsigned int*)(0x42C8E65CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN24 *((volatile unsigned int*)(0x42C8E660UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN25 *((volatile unsigned int*)(0x42C8E664UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN26 *((volatile unsigned int*)(0x42C8E668UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN27 *((volatile unsigned int*)(0x42C8E66CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN28 *((volatile unsigned int*)(0x42C8E670UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN29 *((volatile unsigned int*)(0x42C8E674UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN30 *((volatile unsigned int*)(0x42C8E678UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS0 *((volatile unsigned int*)(0x42C8E680UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS1 *((volatile unsigned int*)(0x42C8E684UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS2 *((volatile unsigned int*)(0x42C8E688UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS3 *((volatile unsigned int*)(0x42C8E68CUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS4 *((volatile unsigned int*)(0x42C8E690UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS5 *((volatile unsigned int*)(0x42C8E694UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS6 *((volatile unsigned int*)(0x42C8E698UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS7 *((volatile unsigned int*)(0x42C8E69CUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS8 *((volatile unsigned int*)(0x42C8E6A0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS9 *((volatile unsigned int*)(0x42C8E6A4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS10 *((volatile unsigned int*)(0x42C8E6A8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS11 *((volatile unsigned int*)(0x42C8E6ACUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS12 *((volatile unsigned int*)(0x42C8E6B0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS13 *((volatile unsigned int*)(0x42C8E6B4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS14 *((volatile unsigned int*)(0x42C8E6B8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS15 *((volatile unsigned int*)(0x42C8E6BCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS16 *((volatile unsigned int*)(0x42C8E6C0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS17 *((volatile unsigned int*)(0x42C8E6C4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS18 *((volatile unsigned int*)(0x42C8E6C8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS19 *((volatile unsigned int*)(0x42C8E6CCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS20 *((volatile unsigned int*)(0x42C8E6D0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS21 *((volatile unsigned int*)(0x42C8E6D4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS22 *((volatile unsigned int*)(0x42C8E6D8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS23 *((volatile unsigned int*)(0x42C8E6DCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS24 *((volatile unsigned int*)(0x42C8E6E0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS25 *((volatile unsigned int*)(0x42C8E6E4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS26 *((volatile unsigned int*)(0x42C8E6E8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS27 *((volatile unsigned int*)(0x42C8E6ECUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS28 *((volatile unsigned int*)(0x42C8E6F0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS29 *((volatile unsigned int*)(0x42C8E6F4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS30 *((volatile unsigned int*)(0x42C8E6F8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS31 *((volatile unsigned int*)(0x42C8E6FCUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A32 *((volatile unsigned int*)(0x42C90000UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A33 *((volatile unsigned int*)(0x42C90004UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A34 *((volatile unsigned int*)(0x42C90008UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A35 *((volatile unsigned int*)(0x42C9000CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A36 *((volatile unsigned int*)(0x42C90010UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A37 *((volatile unsigned int*)(0x42C90014UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A38 *((volatile unsigned int*)(0x42C90018UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A39 *((volatile unsigned int*)(0x42C9001CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A40 *((volatile unsigned int*)(0x42C90020UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A41 *((volatile unsigned int*)(0x42C90024UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A42 *((volatile unsigned int*)(0x42C90028UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A43 *((volatile unsigned int*)(0x42C9002CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A44 *((volatile unsigned int*)(0x42C90030UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A45 *((volatile unsigned int*)(0x42C90034UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A46 *((volatile unsigned int*)(0x42C90038UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A47 *((volatile unsigned int*)(0x42C9003CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC0 *((volatile unsigned int*)(0x42C90060UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC1 *((volatile unsigned int*)(0x42C90064UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC2 *((volatile unsigned int*)(0x42C90068UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC3 *((volatile unsigned int*)(0x42C9006CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC4 *((volatile unsigned int*)(0x42C90070UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC5 *((volatile unsigned int*)(0x42C90074UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_SA *((volatile unsigned int*)(0x42C90078UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_AE *((volatile unsigned int*)(0x42C9007CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A0 *((volatile unsigned int*)(0x42C90080UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A1 *((volatile unsigned int*)(0x42C90084UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A2 *((volatile unsigned int*)(0x42C90088UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A3 *((volatile unsigned int*)(0x42C9008CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A4 *((volatile unsigned int*)(0x42C90090UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A5 *((volatile unsigned int*)(0x42C90094UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A6 *((volatile unsigned int*)(0x42C90098UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A7 *((volatile unsigned int*)(0x42C9009CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A8 *((volatile unsigned int*)(0x42C900A0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A9 *((volatile unsigned int*)(0x42C900A4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A10 *((volatile unsigned int*)(0x42C900A8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A11 *((volatile unsigned int*)(0x42C900ACUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A12 *((volatile unsigned int*)(0x42C900B0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A13 *((volatile unsigned int*)(0x42C900B4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A14 *((volatile unsigned int*)(0x42C900B8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A15 *((volatile unsigned int*)(0x42C900BCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A16 *((volatile unsigned int*)(0x42C900C0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A17 *((volatile unsigned int*)(0x42C900C4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A18 *((volatile unsigned int*)(0x42C900C8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A19 *((volatile unsigned int*)(0x42C900CCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A20 *((volatile unsigned int*)(0x42C900D0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A21 *((volatile unsigned int*)(0x42C900D4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A22 *((volatile unsigned int*)(0x42C900D8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A23 *((volatile unsigned int*)(0x42C900DCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A24 *((volatile unsigned int*)(0x42C900E0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A25 *((volatile unsigned int*)(0x42C900E4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A26 *((volatile unsigned int*)(0x42C900E8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A27 *((volatile unsigned int*)(0x42C900ECUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A28 *((volatile unsigned int*)(0x42C900F0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A29 *((volatile unsigned int*)(0x42C900F4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A30 *((volatile unsigned int*)(0x42C900F8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A31 *((volatile unsigned int*)(0x42C900FCUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A32 *((volatile unsigned int*)(0x42C90100UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A33 *((volatile unsigned int*)(0x42C90104UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A34 *((volatile unsigned int*)(0x42C90108UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A35 *((volatile unsigned int*)(0x42C9010CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A36 *((volatile unsigned int*)(0x42C90110UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A37 *((volatile unsigned int*)(0x42C90114UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A38 *((volatile unsigned int*)(0x42C90118UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A39 *((volatile unsigned int*)(0x42C9011CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A40 *((volatile unsigned int*)(0x42C90120UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A41 *((volatile unsigned int*)(0x42C90124UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A42 *((volatile unsigned int*)(0x42C90128UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A43 *((volatile unsigned int*)(0x42C9012CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A44 *((volatile unsigned int*)(0x42C90130UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A45 *((volatile unsigned int*)(0x42C90134UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A46 *((volatile unsigned int*)(0x42C90138UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A47 *((volatile unsigned int*)(0x42C9013CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC0 *((volatile unsigned int*)(0x42C90160UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC1 *((volatile unsigned int*)(0x42C90164UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC2 *((volatile unsigned int*)(0x42C90168UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC3 *((volatile unsigned int*)(0x42C9016CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC4 *((volatile unsigned int*)(0x42C90170UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC5 *((volatile unsigned int*)(0x42C90174UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_SA *((volatile unsigned int*)(0x42C90178UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_AE *((volatile unsigned int*)(0x42C9017CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A0 *((volatile unsigned int*)(0x42C90180UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A1 *((volatile unsigned int*)(0x42C90184UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A2 *((volatile unsigned int*)(0x42C90188UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A3 *((volatile unsigned int*)(0x42C9018CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A4 *((volatile unsigned int*)(0x42C90190UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A5 *((volatile unsigned int*)(0x42C90194UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A6 *((volatile unsigned int*)(0x42C90198UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A7 *((volatile unsigned int*)(0x42C9019CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A8 *((volatile unsigned int*)(0x42C901A0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A9 *((volatile unsigned int*)(0x42C901A4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A10 *((volatile unsigned int*)(0x42C901A8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A11 *((volatile unsigned int*)(0x42C901ACUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A12 *((volatile unsigned int*)(0x42C901B0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A13 *((volatile unsigned int*)(0x42C901B4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A14 *((volatile unsigned int*)(0x42C901B8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A15 *((volatile unsigned int*)(0x42C901BCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A16 *((volatile unsigned int*)(0x42C901C0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A17 *((volatile unsigned int*)(0x42C901C4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A18 *((volatile unsigned int*)(0x42C901C8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A19 *((volatile unsigned int*)(0x42C901CCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A20 *((volatile unsigned int*)(0x42C901D0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A21 *((volatile unsigned int*)(0x42C901D4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A22 *((volatile unsigned int*)(0x42C901D8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A23 *((volatile unsigned int*)(0x42C901DCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A24 *((volatile unsigned int*)(0x42C901E0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A25 *((volatile unsigned int*)(0x42C901E4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A26 *((volatile unsigned int*)(0x42C901E8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A27 *((volatile unsigned int*)(0x42C901ECUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A28 *((volatile unsigned int*)(0x42C901F0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A29 *((volatile unsigned int*)(0x42C901F4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A30 *((volatile unsigned int*)(0x42C901F8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A31 *((volatile unsigned int*)(0x42C901FCUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A32 *((volatile unsigned int*)(0x42C90200UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A33 *((volatile unsigned int*)(0x42C90204UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A34 *((volatile unsigned int*)(0x42C90208UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A35 *((volatile unsigned int*)(0x42C9020CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A36 *((volatile unsigned int*)(0x42C90210UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A37 *((volatile unsigned int*)(0x42C90214UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A38 *((volatile unsigned int*)(0x42C90218UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A39 *((volatile unsigned int*)(0x42C9021CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A40 *((volatile unsigned int*)(0x42C90220UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A41 *((volatile unsigned int*)(0x42C90224UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A42 *((volatile unsigned int*)(0x42C90228UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A43 *((volatile unsigned int*)(0x42C9022CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A44 *((volatile unsigned int*)(0x42C90230UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A45 *((volatile unsigned int*)(0x42C90234UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A46 *((volatile unsigned int*)(0x42C90238UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A47 *((volatile unsigned int*)(0x42C9023CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC0 *((volatile unsigned int*)(0x42C90260UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC1 *((volatile unsigned int*)(0x42C90264UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC2 *((volatile unsigned int*)(0x42C90268UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC3 *((volatile unsigned int*)(0x42C9026CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC4 *((volatile unsigned int*)(0x42C90270UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC5 *((volatile unsigned int*)(0x42C90274UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_SA *((volatile unsigned int*)(0x42C90278UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_AE *((volatile unsigned int*)(0x42C9027CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A0 *((volatile unsigned int*)(0x42C90280UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A1 *((volatile unsigned int*)(0x42C90284UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A2 *((volatile unsigned int*)(0x42C90288UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A3 *((volatile unsigned int*)(0x42C9028CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A4 *((volatile unsigned int*)(0x42C90290UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A5 *((volatile unsigned int*)(0x42C90294UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A6 *((volatile unsigned int*)(0x42C90298UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A7 *((volatile unsigned int*)(0x42C9029CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A8 *((volatile unsigned int*)(0x42C902A0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A9 *((volatile unsigned int*)(0x42C902A4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A10 *((volatile unsigned int*)(0x42C902A8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A11 *((volatile unsigned int*)(0x42C902ACUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A12 *((volatile unsigned int*)(0x42C902B0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A13 *((volatile unsigned int*)(0x42C902B4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A14 *((volatile unsigned int*)(0x42C902B8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A15 *((volatile unsigned int*)(0x42C902BCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A16 *((volatile unsigned int*)(0x42C902C0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A17 *((volatile unsigned int*)(0x42C902C4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A18 *((volatile unsigned int*)(0x42C902C8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A19 *((volatile unsigned int*)(0x42C902CCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A20 *((volatile unsigned int*)(0x42C902D0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A21 *((volatile unsigned int*)(0x42C902D4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A22 *((volatile unsigned int*)(0x42C902D8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A23 *((volatile unsigned int*)(0x42C902DCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A24 *((volatile unsigned int*)(0x42C902E0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A25 *((volatile unsigned int*)(0x42C902E4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A26 *((volatile unsigned int*)(0x42C902E8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A27 *((volatile unsigned int*)(0x42C902ECUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A28 *((volatile unsigned int*)(0x42C902F0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A29 *((volatile unsigned int*)(0x42C902F4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A30 *((volatile unsigned int*)(0x42C902F8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A31 *((volatile unsigned int*)(0x42C902FCUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A32 *((volatile unsigned int*)(0x42C90300UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A33 *((volatile unsigned int*)(0x42C90304UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A34 *((volatile unsigned int*)(0x42C90308UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A35 *((volatile unsigned int*)(0x42C9030CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A36 *((volatile unsigned int*)(0x42C90310UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A37 *((volatile unsigned int*)(0x42C90314UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A38 *((volatile unsigned int*)(0x42C90318UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A39 *((volatile unsigned int*)(0x42C9031CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A40 *((volatile unsigned int*)(0x42C90320UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A41 *((volatile unsigned int*)(0x42C90324UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A42 *((volatile unsigned int*)(0x42C90328UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A43 *((volatile unsigned int*)(0x42C9032CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A44 *((volatile unsigned int*)(0x42C90330UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A45 *((volatile unsigned int*)(0x42C90334UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A46 *((volatile unsigned int*)(0x42C90338UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A47 *((volatile unsigned int*)(0x42C9033CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC0 *((volatile unsigned int*)(0x42C90360UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC1 *((volatile unsigned int*)(0x42C90364UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC2 *((volatile unsigned int*)(0x42C90368UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC3 *((volatile unsigned int*)(0x42C9036CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC4 *((volatile unsigned int*)(0x42C90370UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC5 *((volatile unsigned int*)(0x42C90374UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_SA *((volatile unsigned int*)(0x42C90378UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_AE *((volatile unsigned int*)(0x42C9037CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A0 *((volatile unsigned int*)(0x42C90380UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A1 *((volatile unsigned int*)(0x42C90384UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A2 *((volatile unsigned int*)(0x42C90388UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A3 *((volatile unsigned int*)(0x42C9038CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A4 *((volatile unsigned int*)(0x42C90390UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A5 *((volatile unsigned int*)(0x42C90394UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A6 *((volatile unsigned int*)(0x42C90398UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A7 *((volatile unsigned int*)(0x42C9039CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A8 *((volatile unsigned int*)(0x42C903A0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A9 *((volatile unsigned int*)(0x42C903A4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A10 *((volatile unsigned int*)(0x42C903A8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A11 *((volatile unsigned int*)(0x42C903ACUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A12 *((volatile unsigned int*)(0x42C903B0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A13 *((volatile unsigned int*)(0x42C903B4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A14 *((volatile unsigned int*)(0x42C903B8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A15 *((volatile unsigned int*)(0x42C903BCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A16 *((volatile unsigned int*)(0x42C903C0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A17 *((volatile unsigned int*)(0x42C903C4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A18 *((volatile unsigned int*)(0x42C903C8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A19 *((volatile unsigned int*)(0x42C903CCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A20 *((volatile unsigned int*)(0x42C903D0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A21 *((volatile unsigned int*)(0x42C903D4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A22 *((volatile unsigned int*)(0x42C903D8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A23 *((volatile unsigned int*)(0x42C903DCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A24 *((volatile unsigned int*)(0x42C903E0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A25 *((volatile unsigned int*)(0x42C903E4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A26 *((volatile unsigned int*)(0x42C903E8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A27 *((volatile unsigned int*)(0x42C903ECUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A28 *((volatile unsigned int*)(0x42C903F0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A29 *((volatile unsigned int*)(0x42C903F4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A30 *((volatile unsigned int*)(0x42C903F8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A31 *((volatile unsigned int*)(0x42C903FCUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A32 *((volatile unsigned int*)(0x42C90400UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A33 *((volatile unsigned int*)(0x42C90404UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A34 *((volatile unsigned int*)(0x42C90408UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A35 *((volatile unsigned int*)(0x42C9040CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A36 *((volatile unsigned int*)(0x42C90410UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A37 *((volatile unsigned int*)(0x42C90414UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A38 *((volatile unsigned int*)(0x42C90418UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A39 *((volatile unsigned int*)(0x42C9041CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A40 *((volatile unsigned int*)(0x42C90420UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A41 *((volatile unsigned int*)(0x42C90424UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A42 *((volatile unsigned int*)(0x42C90428UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A43 *((volatile unsigned int*)(0x42C9042CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A44 *((volatile unsigned int*)(0x42C90430UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A45 *((volatile unsigned int*)(0x42C90434UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A46 *((volatile unsigned int*)(0x42C90438UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A47 *((volatile unsigned int*)(0x42C9043CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC0 *((volatile unsigned int*)(0x42C90460UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC1 *((volatile unsigned int*)(0x42C90464UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC2 *((volatile unsigned int*)(0x42C90468UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC3 *((volatile unsigned int*)(0x42C9046CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC4 *((volatile unsigned int*)(0x42C90470UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC5 *((volatile unsigned int*)(0x42C90474UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_SA *((volatile unsigned int*)(0x42C90478UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_AE *((volatile unsigned int*)(0x42C9047CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A0 *((volatile unsigned int*)(0x42C90480UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A1 *((volatile unsigned int*)(0x42C90484UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A2 *((volatile unsigned int*)(0x42C90488UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A3 *((volatile unsigned int*)(0x42C9048CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A4 *((volatile unsigned int*)(0x42C90490UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A5 *((volatile unsigned int*)(0x42C90494UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A6 *((volatile unsigned int*)(0x42C90498UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A7 *((volatile unsigned int*)(0x42C9049CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A8 *((volatile unsigned int*)(0x42C904A0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A9 *((volatile unsigned int*)(0x42C904A4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A10 *((volatile unsigned int*)(0x42C904A8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A11 *((volatile unsigned int*)(0x42C904ACUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A12 *((volatile unsigned int*)(0x42C904B0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A13 *((volatile unsigned int*)(0x42C904B4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A14 *((volatile unsigned int*)(0x42C904B8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A15 *((volatile unsigned int*)(0x42C904BCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A16 *((volatile unsigned int*)(0x42C904C0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A17 *((volatile unsigned int*)(0x42C904C4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A18 *((volatile unsigned int*)(0x42C904C8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A19 *((volatile unsigned int*)(0x42C904CCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A20 *((volatile unsigned int*)(0x42C904D0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A21 *((volatile unsigned int*)(0x42C904D4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A22 *((volatile unsigned int*)(0x42C904D8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A23 *((volatile unsigned int*)(0x42C904DCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A24 *((volatile unsigned int*)(0x42C904E0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A25 *((volatile unsigned int*)(0x42C904E4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A26 *((volatile unsigned int*)(0x42C904E8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A27 *((volatile unsigned int*)(0x42C904ECUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A28 *((volatile unsigned int*)(0x42C904F0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A29 *((volatile unsigned int*)(0x42C904F4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A30 *((volatile unsigned int*)(0x42C904F8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A31 *((volatile unsigned int*)(0x42C904FCUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A32 *((volatile unsigned int*)(0x42C90500UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A33 *((volatile unsigned int*)(0x42C90504UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A34 *((volatile unsigned int*)(0x42C90508UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A35 *((volatile unsigned int*)(0x42C9050CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A36 *((volatile unsigned int*)(0x42C90510UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A37 *((volatile unsigned int*)(0x42C90514UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A38 *((volatile unsigned int*)(0x42C90518UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A39 *((volatile unsigned int*)(0x42C9051CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A40 *((volatile unsigned int*)(0x42C90520UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A41 *((volatile unsigned int*)(0x42C90524UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A42 *((volatile unsigned int*)(0x42C90528UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A43 *((volatile unsigned int*)(0x42C9052CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A44 *((volatile unsigned int*)(0x42C90530UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A45 *((volatile unsigned int*)(0x42C90534UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A46 *((volatile unsigned int*)(0x42C90538UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A47 *((volatile unsigned int*)(0x42C9053CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC0 *((volatile unsigned int*)(0x42C90560UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC1 *((volatile unsigned int*)(0x42C90564UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC2 *((volatile unsigned int*)(0x42C90568UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC3 *((volatile unsigned int*)(0x42C9056CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC4 *((volatile unsigned int*)(0x42C90570UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC5 *((volatile unsigned int*)(0x42C90574UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_SA *((volatile unsigned int*)(0x42C90578UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_AE *((volatile unsigned int*)(0x42C9057CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A0 *((volatile unsigned int*)(0x42C90580UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A1 *((volatile unsigned int*)(0x42C90584UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A2 *((volatile unsigned int*)(0x42C90588UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A3 *((volatile unsigned int*)(0x42C9058CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A4 *((volatile unsigned int*)(0x42C90590UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A5 *((volatile unsigned int*)(0x42C90594UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A6 *((volatile unsigned int*)(0x42C90598UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A7 *((volatile unsigned int*)(0x42C9059CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A8 *((volatile unsigned int*)(0x42C905A0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A9 *((volatile unsigned int*)(0x42C905A4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A10 *((volatile unsigned int*)(0x42C905A8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A11 *((volatile unsigned int*)(0x42C905ACUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A12 *((volatile unsigned int*)(0x42C905B0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A13 *((volatile unsigned int*)(0x42C905B4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A14 *((volatile unsigned int*)(0x42C905B8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A15 *((volatile unsigned int*)(0x42C905BCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A16 *((volatile unsigned int*)(0x42C905C0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A17 *((volatile unsigned int*)(0x42C905C4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A18 *((volatile unsigned int*)(0x42C905C8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A19 *((volatile unsigned int*)(0x42C905CCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A20 *((volatile unsigned int*)(0x42C905D0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A21 *((volatile unsigned int*)(0x42C905D4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A22 *((volatile unsigned int*)(0x42C905D8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A23 *((volatile unsigned int*)(0x42C905DCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A24 *((volatile unsigned int*)(0x42C905E0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A25 *((volatile unsigned int*)(0x42C905E4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A26 *((volatile unsigned int*)(0x42C905E8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A27 *((volatile unsigned int*)(0x42C905ECUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A28 *((volatile unsigned int*)(0x42C905F0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A29 *((volatile unsigned int*)(0x42C905F4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A30 *((volatile unsigned int*)(0x42C905F8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A31 *((volatile unsigned int*)(0x42C905FCUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A32 *((volatile unsigned int*)(0x42C90600UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A33 *((volatile unsigned int*)(0x42C90604UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A34 *((volatile unsigned int*)(0x42C90608UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A35 *((volatile unsigned int*)(0x42C9060CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A36 *((volatile unsigned int*)(0x42C90610UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A37 *((volatile unsigned int*)(0x42C90614UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A38 *((volatile unsigned int*)(0x42C90618UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A39 *((volatile unsigned int*)(0x42C9061CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A40 *((volatile unsigned int*)(0x42C90620UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A41 *((volatile unsigned int*)(0x42C90624UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A42 *((volatile unsigned int*)(0x42C90628UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A43 *((volatile unsigned int*)(0x42C9062CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A44 *((volatile unsigned int*)(0x42C90630UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A45 *((volatile unsigned int*)(0x42C90634UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A46 *((volatile unsigned int*)(0x42C90638UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A47 *((volatile unsigned int*)(0x42C9063CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC0 *((volatile unsigned int*)(0x42C90660UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC1 *((volatile unsigned int*)(0x42C90664UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC2 *((volatile unsigned int*)(0x42C90668UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC3 *((volatile unsigned int*)(0x42C9066CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC4 *((volatile unsigned int*)(0x42C90670UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC5 *((volatile unsigned int*)(0x42C90674UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_SA *((volatile unsigned int*)(0x42C90678UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_AE *((volatile unsigned int*)(0x42C9067CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A0 *((volatile unsigned int*)(0x42C90680UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A1 *((volatile unsigned int*)(0x42C90684UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A2 *((volatile unsigned int*)(0x42C90688UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A3 *((volatile unsigned int*)(0x42C9068CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A4 *((volatile unsigned int*)(0x42C90690UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A5 *((volatile unsigned int*)(0x42C90694UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A6 *((volatile unsigned int*)(0x42C90698UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A7 *((volatile unsigned int*)(0x42C9069CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A8 *((volatile unsigned int*)(0x42C906A0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A9 *((volatile unsigned int*)(0x42C906A4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A10 *((volatile unsigned int*)(0x42C906A8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A11 *((volatile unsigned int*)(0x42C906ACUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A12 *((volatile unsigned int*)(0x42C906B0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A13 *((volatile unsigned int*)(0x42C906B4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A14 *((volatile unsigned int*)(0x42C906B8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A15 *((volatile unsigned int*)(0x42C906BCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A16 *((volatile unsigned int*)(0x42C906C0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A17 *((volatile unsigned int*)(0x42C906C4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A18 *((volatile unsigned int*)(0x42C906C8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A19 *((volatile unsigned int*)(0x42C906CCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A20 *((volatile unsigned int*)(0x42C906D0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A21 *((volatile unsigned int*)(0x42C906D4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A22 *((volatile unsigned int*)(0x42C906D8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A23 *((volatile unsigned int*)(0x42C906DCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A24 *((volatile unsigned int*)(0x42C906E0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A25 *((volatile unsigned int*)(0x42C906E4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A26 *((volatile unsigned int*)(0x42C906E8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A27 *((volatile unsigned int*)(0x42C906ECUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A28 *((volatile unsigned int*)(0x42C906F0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A29 *((volatile unsigned int*)(0x42C906F4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A30 *((volatile unsigned int*)(0x42C906F8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A31 *((volatile unsigned int*)(0x42C906FCUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A32 *((volatile unsigned int*)(0x42C90700UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A33 *((volatile unsigned int*)(0x42C90704UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A34 *((volatile unsigned int*)(0x42C90708UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A35 *((volatile unsigned int*)(0x42C9070CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A36 *((volatile unsigned int*)(0x42C90710UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A37 *((volatile unsigned int*)(0x42C90714UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A38 *((volatile unsigned int*)(0x42C90718UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A39 *((volatile unsigned int*)(0x42C9071CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A40 *((volatile unsigned int*)(0x42C90720UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A41 *((volatile unsigned int*)(0x42C90724UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A42 *((volatile unsigned int*)(0x42C90728UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A43 *((volatile unsigned int*)(0x42C9072CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A44 *((volatile unsigned int*)(0x42C90730UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A45 *((volatile unsigned int*)(0x42C90734UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A46 *((volatile unsigned int*)(0x42C90738UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A47 *((volatile unsigned int*)(0x42C9073CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC0 *((volatile unsigned int*)(0x42C90760UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC1 *((volatile unsigned int*)(0x42C90764UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC2 *((volatile unsigned int*)(0x42C90768UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC3 *((volatile unsigned int*)(0x42C9076CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC4 *((volatile unsigned int*)(0x42C90770UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC5 *((volatile unsigned int*)(0x42C90774UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_SA *((volatile unsigned int*)(0x42C90778UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_AE *((volatile unsigned int*)(0x42C9077CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A0 *((volatile unsigned int*)(0x42C90780UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A1 *((volatile unsigned int*)(0x42C90784UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A2 *((volatile unsigned int*)(0x42C90788UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A3 *((volatile unsigned int*)(0x42C9078CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A4 *((volatile unsigned int*)(0x42C90790UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A5 *((volatile unsigned int*)(0x42C90794UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A6 *((volatile unsigned int*)(0x42C90798UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A7 *((volatile unsigned int*)(0x42C9079CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A8 *((volatile unsigned int*)(0x42C907A0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A9 *((volatile unsigned int*)(0x42C907A4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A10 *((volatile unsigned int*)(0x42C907A8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A11 *((volatile unsigned int*)(0x42C907ACUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A12 *((volatile unsigned int*)(0x42C907B0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A13 *((volatile unsigned int*)(0x42C907B4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A14 *((volatile unsigned int*)(0x42C907B8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A15 *((volatile unsigned int*)(0x42C907BCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A16 *((volatile unsigned int*)(0x42C907C0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A17 *((volatile unsigned int*)(0x42C907C4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A18 *((volatile unsigned int*)(0x42C907C8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A19 *((volatile unsigned int*)(0x42C907CCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A20 *((volatile unsigned int*)(0x42C907D0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A21 *((volatile unsigned int*)(0x42C907D4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A22 *((volatile unsigned int*)(0x42C907D8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A23 *((volatile unsigned int*)(0x42C907DCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A24 *((volatile unsigned int*)(0x42C907E0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A25 *((volatile unsigned int*)(0x42C907E4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A26 *((volatile unsigned int*)(0x42C907E8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A27 *((volatile unsigned int*)(0x42C907ECUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A28 *((volatile unsigned int*)(0x42C907F0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A29 *((volatile unsigned int*)(0x42C907F4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A30 *((volatile unsigned int*)(0x42C907F8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A31 *((volatile unsigned int*)(0x42C907FCUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A32 *((volatile unsigned int*)(0x42C90800UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A33 *((volatile unsigned int*)(0x42C90804UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A34 *((volatile unsigned int*)(0x42C90808UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A35 *((volatile unsigned int*)(0x42C9080CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A36 *((volatile unsigned int*)(0x42C90810UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A37 *((volatile unsigned int*)(0x42C90814UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A38 *((volatile unsigned int*)(0x42C90818UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A39 *((volatile unsigned int*)(0x42C9081CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A40 *((volatile unsigned int*)(0x42C90820UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A41 *((volatile unsigned int*)(0x42C90824UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A42 *((volatile unsigned int*)(0x42C90828UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A43 *((volatile unsigned int*)(0x42C9082CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A44 *((volatile unsigned int*)(0x42C90830UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A45 *((volatile unsigned int*)(0x42C90834UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A46 *((volatile unsigned int*)(0x42C90838UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A47 *((volatile unsigned int*)(0x42C9083CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC0 *((volatile unsigned int*)(0x42C90860UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC1 *((volatile unsigned int*)(0x42C90864UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC2 *((volatile unsigned int*)(0x42C90868UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC3 *((volatile unsigned int*)(0x42C9086CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC4 *((volatile unsigned int*)(0x42C90870UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC5 *((volatile unsigned int*)(0x42C90874UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_SA *((volatile unsigned int*)(0x42C90878UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_AE *((volatile unsigned int*)(0x42C9087CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A0 *((volatile unsigned int*)(0x42C90880UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A1 *((volatile unsigned int*)(0x42C90884UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A2 *((volatile unsigned int*)(0x42C90888UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A3 *((volatile unsigned int*)(0x42C9088CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A4 *((volatile unsigned int*)(0x42C90890UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A5 *((volatile unsigned int*)(0x42C90894UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A6 *((volatile unsigned int*)(0x42C90898UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A7 *((volatile unsigned int*)(0x42C9089CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A8 *((volatile unsigned int*)(0x42C908A0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A9 *((volatile unsigned int*)(0x42C908A4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A10 *((volatile unsigned int*)(0x42C908A8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A11 *((volatile unsigned int*)(0x42C908ACUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A12 *((volatile unsigned int*)(0x42C908B0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A13 *((volatile unsigned int*)(0x42C908B4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A14 *((volatile unsigned int*)(0x42C908B8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A15 *((volatile unsigned int*)(0x42C908BCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A16 *((volatile unsigned int*)(0x42C908C0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A17 *((volatile unsigned int*)(0x42C908C4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A18 *((volatile unsigned int*)(0x42C908C8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A19 *((volatile unsigned int*)(0x42C908CCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A20 *((volatile unsigned int*)(0x42C908D0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A21 *((volatile unsigned int*)(0x42C908D4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A22 *((volatile unsigned int*)(0x42C908D8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A23 *((volatile unsigned int*)(0x42C908DCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A24 *((volatile unsigned int*)(0x42C908E0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A25 *((volatile unsigned int*)(0x42C908E4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A26 *((volatile unsigned int*)(0x42C908E8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A27 *((volatile unsigned int*)(0x42C908ECUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A28 *((volatile unsigned int*)(0x42C908F0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A29 *((volatile unsigned int*)(0x42C908F4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A30 *((volatile unsigned int*)(0x42C908F8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A31 *((volatile unsigned int*)(0x42C908FCUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A32 *((volatile unsigned int*)(0x42C90900UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A33 *((volatile unsigned int*)(0x42C90904UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A34 *((volatile unsigned int*)(0x42C90908UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A35 *((volatile unsigned int*)(0x42C9090CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A36 *((volatile unsigned int*)(0x42C90910UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A37 *((volatile unsigned int*)(0x42C90914UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A38 *((volatile unsigned int*)(0x42C90918UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A39 *((volatile unsigned int*)(0x42C9091CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A40 *((volatile unsigned int*)(0x42C90920UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A41 *((volatile unsigned int*)(0x42C90924UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A42 *((volatile unsigned int*)(0x42C90928UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A43 *((volatile unsigned int*)(0x42C9092CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A44 *((volatile unsigned int*)(0x42C90930UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A45 *((volatile unsigned int*)(0x42C90934UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A46 *((volatile unsigned int*)(0x42C90938UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A47 *((volatile unsigned int*)(0x42C9093CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC0 *((volatile unsigned int*)(0x42C90960UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC1 *((volatile unsigned int*)(0x42C90964UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC2 *((volatile unsigned int*)(0x42C90968UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC3 *((volatile unsigned int*)(0x42C9096CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC4 *((volatile unsigned int*)(0x42C90970UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC5 *((volatile unsigned int*)(0x42C90974UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_SA *((volatile unsigned int*)(0x42C90978UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_AE *((volatile unsigned int*)(0x42C9097CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A0 *((volatile unsigned int*)(0x42C90980UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A1 *((volatile unsigned int*)(0x42C90984UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A2 *((volatile unsigned int*)(0x42C90988UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A3 *((volatile unsigned int*)(0x42C9098CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A4 *((volatile unsigned int*)(0x42C90990UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A5 *((volatile unsigned int*)(0x42C90994UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A6 *((volatile unsigned int*)(0x42C90998UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A7 *((volatile unsigned int*)(0x42C9099CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A8 *((volatile unsigned int*)(0x42C909A0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A9 *((volatile unsigned int*)(0x42C909A4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A10 *((volatile unsigned int*)(0x42C909A8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A11 *((volatile unsigned int*)(0x42C909ACUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A12 *((volatile unsigned int*)(0x42C909B0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A13 *((volatile unsigned int*)(0x42C909B4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A14 *((volatile unsigned int*)(0x42C909B8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A15 *((volatile unsigned int*)(0x42C909BCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A16 *((volatile unsigned int*)(0x42C909C0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A17 *((volatile unsigned int*)(0x42C909C4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A18 *((volatile unsigned int*)(0x42C909C8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A19 *((volatile unsigned int*)(0x42C909CCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A20 *((volatile unsigned int*)(0x42C909D0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A21 *((volatile unsigned int*)(0x42C909D4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A22 *((volatile unsigned int*)(0x42C909D8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A23 *((volatile unsigned int*)(0x42C909DCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A24 *((volatile unsigned int*)(0x42C909E0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A25 *((volatile unsigned int*)(0x42C909E4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A26 *((volatile unsigned int*)(0x42C909E8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A27 *((volatile unsigned int*)(0x42C909ECUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A28 *((volatile unsigned int*)(0x42C909F0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A29 *((volatile unsigned int*)(0x42C909F4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A30 *((volatile unsigned int*)(0x42C909F8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A31 *((volatile unsigned int*)(0x42C909FCUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A32 *((volatile unsigned int*)(0x42C90A00UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A33 *((volatile unsigned int*)(0x42C90A04UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A34 *((volatile unsigned int*)(0x42C90A08UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A35 *((volatile unsigned int*)(0x42C90A0CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A36 *((volatile unsigned int*)(0x42C90A10UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A37 *((volatile unsigned int*)(0x42C90A14UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A38 *((volatile unsigned int*)(0x42C90A18UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A39 *((volatile unsigned int*)(0x42C90A1CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A40 *((volatile unsigned int*)(0x42C90A20UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A41 *((volatile unsigned int*)(0x42C90A24UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A42 *((volatile unsigned int*)(0x42C90A28UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A43 *((volatile unsigned int*)(0x42C90A2CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A44 *((volatile unsigned int*)(0x42C90A30UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A45 *((volatile unsigned int*)(0x42C90A34UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A46 *((volatile unsigned int*)(0x42C90A38UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A47 *((volatile unsigned int*)(0x42C90A3CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC0 *((volatile unsigned int*)(0x42C90A60UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC1 *((volatile unsigned int*)(0x42C90A64UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC2 *((volatile unsigned int*)(0x42C90A68UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC3 *((volatile unsigned int*)(0x42C90A6CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC4 *((volatile unsigned int*)(0x42C90A70UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC5 *((volatile unsigned int*)(0x42C90A74UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_SA *((volatile unsigned int*)(0x42C90A78UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_AE *((volatile unsigned int*)(0x42C90A7CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A0 *((volatile unsigned int*)(0x42C90A80UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A1 *((volatile unsigned int*)(0x42C90A84UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A2 *((volatile unsigned int*)(0x42C90A88UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A3 *((volatile unsigned int*)(0x42C90A8CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A4 *((volatile unsigned int*)(0x42C90A90UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A5 *((volatile unsigned int*)(0x42C90A94UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A6 *((volatile unsigned int*)(0x42C90A98UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A7 *((volatile unsigned int*)(0x42C90A9CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A8 *((volatile unsigned int*)(0x42C90AA0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A9 *((volatile unsigned int*)(0x42C90AA4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A10 *((volatile unsigned int*)(0x42C90AA8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A11 *((volatile unsigned int*)(0x42C90AACUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A12 *((volatile unsigned int*)(0x42C90AB0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A13 *((volatile unsigned int*)(0x42C90AB4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A14 *((volatile unsigned int*)(0x42C90AB8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A15 *((volatile unsigned int*)(0x42C90ABCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A16 *((volatile unsigned int*)(0x42C90AC0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A17 *((volatile unsigned int*)(0x42C90AC4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A18 *((volatile unsigned int*)(0x42C90AC8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A19 *((volatile unsigned int*)(0x42C90ACCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A20 *((volatile unsigned int*)(0x42C90AD0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A21 *((volatile unsigned int*)(0x42C90AD4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A22 *((volatile unsigned int*)(0x42C90AD8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A23 *((volatile unsigned int*)(0x42C90ADCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A24 *((volatile unsigned int*)(0x42C90AE0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A25 *((volatile unsigned int*)(0x42C90AE4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A26 *((volatile unsigned int*)(0x42C90AE8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A27 *((volatile unsigned int*)(0x42C90AECUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A28 *((volatile unsigned int*)(0x42C90AF0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A29 *((volatile unsigned int*)(0x42C90AF4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A30 *((volatile unsigned int*)(0x42C90AF8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A31 *((volatile unsigned int*)(0x42C90AFCUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A32 *((volatile unsigned int*)(0x42C90B00UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A33 *((volatile unsigned int*)(0x42C90B04UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A34 *((volatile unsigned int*)(0x42C90B08UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A35 *((volatile unsigned int*)(0x42C90B0CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A36 *((volatile unsigned int*)(0x42C90B10UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A37 *((volatile unsigned int*)(0x42C90B14UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A38 *((volatile unsigned int*)(0x42C90B18UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A39 *((volatile unsigned int*)(0x42C90B1CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A40 *((volatile unsigned int*)(0x42C90B20UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A41 *((volatile unsigned int*)(0x42C90B24UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A42 *((volatile unsigned int*)(0x42C90B28UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A43 *((volatile unsigned int*)(0x42C90B2CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A44 *((volatile unsigned int*)(0x42C90B30UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A45 *((volatile unsigned int*)(0x42C90B34UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A46 *((volatile unsigned int*)(0x42C90B38UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A47 *((volatile unsigned int*)(0x42C90B3CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC0 *((volatile unsigned int*)(0x42C90B60UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC1 *((volatile unsigned int*)(0x42C90B64UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC2 *((volatile unsigned int*)(0x42C90B68UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC3 *((volatile unsigned int*)(0x42C90B6CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC4 *((volatile unsigned int*)(0x42C90B70UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC5 *((volatile unsigned int*)(0x42C90B74UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_SA *((volatile unsigned int*)(0x42C90B78UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_AE *((volatile unsigned int*)(0x42C90B7CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A0 *((volatile unsigned int*)(0x42C90B80UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A1 *((volatile unsigned int*)(0x42C90B84UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A2 *((volatile unsigned int*)(0x42C90B88UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A3 *((volatile unsigned int*)(0x42C90B8CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A4 *((volatile unsigned int*)(0x42C90B90UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A5 *((volatile unsigned int*)(0x42C90B94UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A6 *((volatile unsigned int*)(0x42C90B98UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A7 *((volatile unsigned int*)(0x42C90B9CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A8 *((volatile unsigned int*)(0x42C90BA0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A9 *((volatile unsigned int*)(0x42C90BA4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A10 *((volatile unsigned int*)(0x42C90BA8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A11 *((volatile unsigned int*)(0x42C90BACUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A12 *((volatile unsigned int*)(0x42C90BB0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A13 *((volatile unsigned int*)(0x42C90BB4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A14 *((volatile unsigned int*)(0x42C90BB8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A15 *((volatile unsigned int*)(0x42C90BBCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A16 *((volatile unsigned int*)(0x42C90BC0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A17 *((volatile unsigned int*)(0x42C90BC4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A18 *((volatile unsigned int*)(0x42C90BC8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A19 *((volatile unsigned int*)(0x42C90BCCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A20 *((volatile unsigned int*)(0x42C90BD0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A21 *((volatile unsigned int*)(0x42C90BD4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A22 *((volatile unsigned int*)(0x42C90BD8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A23 *((volatile unsigned int*)(0x42C90BDCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A24 *((volatile unsigned int*)(0x42C90BE0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A25 *((volatile unsigned int*)(0x42C90BE4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A26 *((volatile unsigned int*)(0x42C90BE8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A27 *((volatile unsigned int*)(0x42C90BECUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A28 *((volatile unsigned int*)(0x42C90BF0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A29 *((volatile unsigned int*)(0x42C90BF4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A30 *((volatile unsigned int*)(0x42C90BF8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A31 *((volatile unsigned int*)(0x42C90BFCUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A32 *((volatile unsigned int*)(0x42C90C00UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A33 *((volatile unsigned int*)(0x42C90C04UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A34 *((volatile unsigned int*)(0x42C90C08UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A35 *((volatile unsigned int*)(0x42C90C0CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A36 *((volatile unsigned int*)(0x42C90C10UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A37 *((volatile unsigned int*)(0x42C90C14UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A38 *((volatile unsigned int*)(0x42C90C18UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A39 *((volatile unsigned int*)(0x42C90C1CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A40 *((volatile unsigned int*)(0x42C90C20UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A41 *((volatile unsigned int*)(0x42C90C24UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A42 *((volatile unsigned int*)(0x42C90C28UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A43 *((volatile unsigned int*)(0x42C90C2CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A44 *((volatile unsigned int*)(0x42C90C30UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A45 *((volatile unsigned int*)(0x42C90C34UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A46 *((volatile unsigned int*)(0x42C90C38UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A47 *((volatile unsigned int*)(0x42C90C3CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC0 *((volatile unsigned int*)(0x42C90C60UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC1 *((volatile unsigned int*)(0x42C90C64UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC2 *((volatile unsigned int*)(0x42C90C68UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC3 *((volatile unsigned int*)(0x42C90C6CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC4 *((volatile unsigned int*)(0x42C90C70UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC5 *((volatile unsigned int*)(0x42C90C74UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_SA *((volatile unsigned int*)(0x42C90C78UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_AE *((volatile unsigned int*)(0x42C90C7CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A0 *((volatile unsigned int*)(0x42C90C80UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A1 *((volatile unsigned int*)(0x42C90C84UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A2 *((volatile unsigned int*)(0x42C90C88UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A3 *((volatile unsigned int*)(0x42C90C8CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A4 *((volatile unsigned int*)(0x42C90C90UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A5 *((volatile unsigned int*)(0x42C90C94UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A6 *((volatile unsigned int*)(0x42C90C98UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A7 *((volatile unsigned int*)(0x42C90C9CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A8 *((volatile unsigned int*)(0x42C90CA0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A9 *((volatile unsigned int*)(0x42C90CA4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A10 *((volatile unsigned int*)(0x42C90CA8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A11 *((volatile unsigned int*)(0x42C90CACUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A12 *((volatile unsigned int*)(0x42C90CB0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A13 *((volatile unsigned int*)(0x42C90CB4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A14 *((volatile unsigned int*)(0x42C90CB8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A15 *((volatile unsigned int*)(0x42C90CBCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A16 *((volatile unsigned int*)(0x42C90CC0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A17 *((volatile unsigned int*)(0x42C90CC4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A18 *((volatile unsigned int*)(0x42C90CC8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A19 *((volatile unsigned int*)(0x42C90CCCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A20 *((volatile unsigned int*)(0x42C90CD0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A21 *((volatile unsigned int*)(0x42C90CD4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A22 *((volatile unsigned int*)(0x42C90CD8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A23 *((volatile unsigned int*)(0x42C90CDCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A24 *((volatile unsigned int*)(0x42C90CE0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A25 *((volatile unsigned int*)(0x42C90CE4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A26 *((volatile unsigned int*)(0x42C90CE8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A27 *((volatile unsigned int*)(0x42C90CECUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A28 *((volatile unsigned int*)(0x42C90CF0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A29 *((volatile unsigned int*)(0x42C90CF4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A30 *((volatile unsigned int*)(0x42C90CF8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A31 *((volatile unsigned int*)(0x42C90CFCUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A32 *((volatile unsigned int*)(0x42C90D00UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A33 *((volatile unsigned int*)(0x42C90D04UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A34 *((volatile unsigned int*)(0x42C90D08UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A35 *((volatile unsigned int*)(0x42C90D0CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A36 *((volatile unsigned int*)(0x42C90D10UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A37 *((volatile unsigned int*)(0x42C90D14UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A38 *((volatile unsigned int*)(0x42C90D18UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A39 *((volatile unsigned int*)(0x42C90D1CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A40 *((volatile unsigned int*)(0x42C90D20UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A41 *((volatile unsigned int*)(0x42C90D24UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A42 *((volatile unsigned int*)(0x42C90D28UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A43 *((volatile unsigned int*)(0x42C90D2CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A44 *((volatile unsigned int*)(0x42C90D30UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A45 *((volatile unsigned int*)(0x42C90D34UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A46 *((volatile unsigned int*)(0x42C90D38UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A47 *((volatile unsigned int*)(0x42C90D3CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC0 *((volatile unsigned int*)(0x42C90D60UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC1 *((volatile unsigned int*)(0x42C90D64UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC2 *((volatile unsigned int*)(0x42C90D68UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC3 *((volatile unsigned int*)(0x42C90D6CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC4 *((volatile unsigned int*)(0x42C90D70UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC5 *((volatile unsigned int*)(0x42C90D74UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_SA *((volatile unsigned int*)(0x42C90D78UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_AE *((volatile unsigned int*)(0x42C90D7CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A0 *((volatile unsigned int*)(0x42C90D80UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A1 *((volatile unsigned int*)(0x42C90D84UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A2 *((volatile unsigned int*)(0x42C90D88UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A3 *((volatile unsigned int*)(0x42C90D8CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A4 *((volatile unsigned int*)(0x42C90D90UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A5 *((volatile unsigned int*)(0x42C90D94UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A6 *((volatile unsigned int*)(0x42C90D98UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A7 *((volatile unsigned int*)(0x42C90D9CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A8 *((volatile unsigned int*)(0x42C90DA0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A9 *((volatile unsigned int*)(0x42C90DA4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A10 *((volatile unsigned int*)(0x42C90DA8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A11 *((volatile unsigned int*)(0x42C90DACUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A12 *((volatile unsigned int*)(0x42C90DB0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A13 *((volatile unsigned int*)(0x42C90DB4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A14 *((volatile unsigned int*)(0x42C90DB8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A15 *((volatile unsigned int*)(0x42C90DBCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A16 *((volatile unsigned int*)(0x42C90DC0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A17 *((volatile unsigned int*)(0x42C90DC4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A18 *((volatile unsigned int*)(0x42C90DC8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A19 *((volatile unsigned int*)(0x42C90DCCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A20 *((volatile unsigned int*)(0x42C90DD0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A21 *((volatile unsigned int*)(0x42C90DD4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A22 *((volatile unsigned int*)(0x42C90DD8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A23 *((volatile unsigned int*)(0x42C90DDCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A24 *((volatile unsigned int*)(0x42C90DE0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A25 *((volatile unsigned int*)(0x42C90DE4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A26 *((volatile unsigned int*)(0x42C90DE8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A27 *((volatile unsigned int*)(0x42C90DECUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A28 *((volatile unsigned int*)(0x42C90DF0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A29 *((volatile unsigned int*)(0x42C90DF4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A30 *((volatile unsigned int*)(0x42C90DF8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A31 *((volatile unsigned int*)(0x42C90DFCUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A32 *((volatile unsigned int*)(0x42C90E00UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A33 *((volatile unsigned int*)(0x42C90E04UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A34 *((volatile unsigned int*)(0x42C90E08UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A35 *((volatile unsigned int*)(0x42C90E0CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A36 *((volatile unsigned int*)(0x42C90E10UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A37 *((volatile unsigned int*)(0x42C90E14UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A38 *((volatile unsigned int*)(0x42C90E18UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A39 *((volatile unsigned int*)(0x42C90E1CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A40 *((volatile unsigned int*)(0x42C90E20UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A41 *((volatile unsigned int*)(0x42C90E24UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A42 *((volatile unsigned int*)(0x42C90E28UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A43 *((volatile unsigned int*)(0x42C90E2CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A44 *((volatile unsigned int*)(0x42C90E30UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A45 *((volatile unsigned int*)(0x42C90E34UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A46 *((volatile unsigned int*)(0x42C90E38UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A47 *((volatile unsigned int*)(0x42C90E3CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC0 *((volatile unsigned int*)(0x42C90E60UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC1 *((volatile unsigned int*)(0x42C90E64UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC2 *((volatile unsigned int*)(0x42C90E68UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC3 *((volatile unsigned int*)(0x42C90E6CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC4 *((volatile unsigned int*)(0x42C90E70UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC5 *((volatile unsigned int*)(0x42C90E74UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_SA *((volatile unsigned int*)(0x42C90E78UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_AE *((volatile unsigned int*)(0x42C90E7CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A0 *((volatile unsigned int*)(0x42C90E80UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A1 *((volatile unsigned int*)(0x42C90E84UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A2 *((volatile unsigned int*)(0x42C90E88UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A3 *((volatile unsigned int*)(0x42C90E8CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A4 *((volatile unsigned int*)(0x42C90E90UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A5 *((volatile unsigned int*)(0x42C90E94UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A6 *((volatile unsigned int*)(0x42C90E98UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A7 *((volatile unsigned int*)(0x42C90E9CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A8 *((volatile unsigned int*)(0x42C90EA0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A9 *((volatile unsigned int*)(0x42C90EA4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A10 *((volatile unsigned int*)(0x42C90EA8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A11 *((volatile unsigned int*)(0x42C90EACUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A12 *((volatile unsigned int*)(0x42C90EB0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A13 *((volatile unsigned int*)(0x42C90EB4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A14 *((volatile unsigned int*)(0x42C90EB8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A15 *((volatile unsigned int*)(0x42C90EBCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A16 *((volatile unsigned int*)(0x42C90EC0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A17 *((volatile unsigned int*)(0x42C90EC4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A18 *((volatile unsigned int*)(0x42C90EC8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A19 *((volatile unsigned int*)(0x42C90ECCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A20 *((volatile unsigned int*)(0x42C90ED0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A21 *((volatile unsigned int*)(0x42C90ED4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A22 *((volatile unsigned int*)(0x42C90ED8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A23 *((volatile unsigned int*)(0x42C90EDCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A24 *((volatile unsigned int*)(0x42C90EE0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A25 *((volatile unsigned int*)(0x42C90EE4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A26 *((volatile unsigned int*)(0x42C90EE8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A27 *((volatile unsigned int*)(0x42C90EECUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A28 *((volatile unsigned int*)(0x42C90EF0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A29 *((volatile unsigned int*)(0x42C90EF4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A30 *((volatile unsigned int*)(0x42C90EF8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A31 *((volatile unsigned int*)(0x42C90EFCUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A32 *((volatile unsigned int*)(0x42C90F00UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A33 *((volatile unsigned int*)(0x42C90F04UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A34 *((volatile unsigned int*)(0x42C90F08UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A35 *((volatile unsigned int*)(0x42C90F0CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A36 *((volatile unsigned int*)(0x42C90F10UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A37 *((volatile unsigned int*)(0x42C90F14UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A38 *((volatile unsigned int*)(0x42C90F18UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A39 *((volatile unsigned int*)(0x42C90F1CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A40 *((volatile unsigned int*)(0x42C90F20UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A41 *((volatile unsigned int*)(0x42C90F24UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A42 *((volatile unsigned int*)(0x42C90F28UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A43 *((volatile unsigned int*)(0x42C90F2CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A44 *((volatile unsigned int*)(0x42C90F30UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A45 *((volatile unsigned int*)(0x42C90F34UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A46 *((volatile unsigned int*)(0x42C90F38UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A47 *((volatile unsigned int*)(0x42C90F3CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC0 *((volatile unsigned int*)(0x42C90F60UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC1 *((volatile unsigned int*)(0x42C90F64UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC2 *((volatile unsigned int*)(0x42C90F68UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC3 *((volatile unsigned int*)(0x42C90F6CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC4 *((volatile unsigned int*)(0x42C90F70UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC5 *((volatile unsigned int*)(0x42C90F74UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_SA *((volatile unsigned int*)(0x42C90F78UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_AE *((volatile unsigned int*)(0x42C90F7CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A0 *((volatile unsigned int*)(0x42C90F80UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A1 *((volatile unsigned int*)(0x42C90F84UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A2 *((volatile unsigned int*)(0x42C90F88UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A3 *((volatile unsigned int*)(0x42C90F8CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A4 *((volatile unsigned int*)(0x42C90F90UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A5 *((volatile unsigned int*)(0x42C90F94UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A6 *((volatile unsigned int*)(0x42C90F98UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A7 *((volatile unsigned int*)(0x42C90F9CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A8 *((volatile unsigned int*)(0x42C90FA0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A9 *((volatile unsigned int*)(0x42C90FA4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A10 *((volatile unsigned int*)(0x42C90FA8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A11 *((volatile unsigned int*)(0x42C90FACUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A12 *((volatile unsigned int*)(0x42C90FB0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A13 *((volatile unsigned int*)(0x42C90FB4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A14 *((volatile unsigned int*)(0x42C90FB8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A15 *((volatile unsigned int*)(0x42C90FBCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A16 *((volatile unsigned int*)(0x42C90FC0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A17 *((volatile unsigned int*)(0x42C90FC4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A18 *((volatile unsigned int*)(0x42C90FC8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A19 *((volatile unsigned int*)(0x42C90FCCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A20 *((volatile unsigned int*)(0x42C90FD0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A21 *((volatile unsigned int*)(0x42C90FD4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A22 *((volatile unsigned int*)(0x42C90FD8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A23 *((volatile unsigned int*)(0x42C90FDCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A24 *((volatile unsigned int*)(0x42C90FE0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A25 *((volatile unsigned int*)(0x42C90FE4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A26 *((volatile unsigned int*)(0x42C90FE8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A27 *((volatile unsigned int*)(0x42C90FECUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A28 *((volatile unsigned int*)(0x42C90FF0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A29 *((volatile unsigned int*)(0x42C90FF4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A30 *((volatile unsigned int*)(0x42C90FF8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A31 *((volatile unsigned int*)(0x42C90FFCUL)) +#define bFM3_ETHERNET_MAC0_BMR_SWR *((volatile unsigned int*)(0x42CA0000UL)) +#define bFM3_ETHERNET_MAC0_BMR_DA *((volatile unsigned int*)(0x42CA0004UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL0 *((volatile unsigned int*)(0x42CA0008UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL1 *((volatile unsigned int*)(0x42CA000CUL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL2 *((volatile unsigned int*)(0x42CA0010UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL3 *((volatile unsigned int*)(0x42CA0014UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL4 *((volatile unsigned int*)(0x42CA0018UL)) +#define bFM3_ETHERNET_MAC0_BMR_ATDS *((volatile unsigned int*)(0x42CA001CUL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL0 *((volatile unsigned int*)(0x42CA0020UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL1 *((volatile unsigned int*)(0x42CA0024UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL2 *((volatile unsigned int*)(0x42CA0028UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL3 *((volatile unsigned int*)(0x42CA002CUL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL4 *((volatile unsigned int*)(0x42CA0030UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL5 *((volatile unsigned int*)(0x42CA0034UL)) +#define bFM3_ETHERNET_MAC0_BMR_PR0 *((volatile unsigned int*)(0x42CA0038UL)) +#define bFM3_ETHERNET_MAC0_BMR_PR1 *((volatile unsigned int*)(0x42CA003CUL)) +#define bFM3_ETHERNET_MAC0_BMR_FB *((volatile unsigned int*)(0x42CA0040UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL0 *((volatile unsigned int*)(0x42CA0044UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL1 *((volatile unsigned int*)(0x42CA0048UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL2 *((volatile unsigned int*)(0x42CA004CUL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL3 *((volatile unsigned int*)(0x42CA0050UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL4 *((volatile unsigned int*)(0x42CA0054UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL5 *((volatile unsigned int*)(0x42CA0058UL)) +#define bFM3_ETHERNET_MAC0_BMR_USP *((volatile unsigned int*)(0x42CA005CUL)) +#define bFM3_ETHERNET_MAC0_BMR_8XPBL *((volatile unsigned int*)(0x42CA0060UL)) +#define bFM3_ETHERNET_MAC0_BMR_AAL *((volatile unsigned int*)(0x42CA0064UL)) +#define bFM3_ETHERNET_MAC0_BMR_MB *((volatile unsigned int*)(0x42CA0068UL)) +#define bFM3_ETHERNET_MAC0_BMR_TXPR *((volatile unsigned int*)(0x42CA006CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD0 *((volatile unsigned int*)(0x42CA0080UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD1 *((volatile unsigned int*)(0x42CA0084UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD2 *((volatile unsigned int*)(0x42CA0088UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD3 *((volatile unsigned int*)(0x42CA008CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD4 *((volatile unsigned int*)(0x42CA0090UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD5 *((volatile unsigned int*)(0x42CA0094UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD6 *((volatile unsigned int*)(0x42CA0098UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD7 *((volatile unsigned int*)(0x42CA009CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD8 *((volatile unsigned int*)(0x42CA00A0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD9 *((volatile unsigned int*)(0x42CA00A4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD10 *((volatile unsigned int*)(0x42CA00A8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD11 *((volatile unsigned int*)(0x42CA00ACUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD12 *((volatile unsigned int*)(0x42CA00B0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD13 *((volatile unsigned int*)(0x42CA00B4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD14 *((volatile unsigned int*)(0x42CA00B8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD15 *((volatile unsigned int*)(0x42CA00BCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD16 *((volatile unsigned int*)(0x42CA00C0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD17 *((volatile unsigned int*)(0x42CA00C4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD18 *((volatile unsigned int*)(0x42CA00C8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD19 *((volatile unsigned int*)(0x42CA00CCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD20 *((volatile unsigned int*)(0x42CA00D0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD21 *((volatile unsigned int*)(0x42CA00D4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD22 *((volatile unsigned int*)(0x42CA00D8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD23 *((volatile unsigned int*)(0x42CA00DCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD24 *((volatile unsigned int*)(0x42CA00E0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD25 *((volatile unsigned int*)(0x42CA00E4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD26 *((volatile unsigned int*)(0x42CA00E8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD27 *((volatile unsigned int*)(0x42CA00ECUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD28 *((volatile unsigned int*)(0x42CA00F0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD29 *((volatile unsigned int*)(0x42CA00F4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD30 *((volatile unsigned int*)(0x42CA00F8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD31 *((volatile unsigned int*)(0x42CA00FCUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD0 *((volatile unsigned int*)(0x42CA0100UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD1 *((volatile unsigned int*)(0x42CA0104UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD2 *((volatile unsigned int*)(0x42CA0108UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD3 *((volatile unsigned int*)(0x42CA010CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD4 *((volatile unsigned int*)(0x42CA0110UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD5 *((volatile unsigned int*)(0x42CA0114UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD6 *((volatile unsigned int*)(0x42CA0118UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD7 *((volatile unsigned int*)(0x42CA011CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD8 *((volatile unsigned int*)(0x42CA0120UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD9 *((volatile unsigned int*)(0x42CA0124UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD10 *((volatile unsigned int*)(0x42CA0128UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD11 *((volatile unsigned int*)(0x42CA012CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD12 *((volatile unsigned int*)(0x42CA0130UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD13 *((volatile unsigned int*)(0x42CA0134UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD14 *((volatile unsigned int*)(0x42CA0138UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD15 *((volatile unsigned int*)(0x42CA013CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD16 *((volatile unsigned int*)(0x42CA0140UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD17 *((volatile unsigned int*)(0x42CA0144UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD18 *((volatile unsigned int*)(0x42CA0148UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD19 *((volatile unsigned int*)(0x42CA014CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD20 *((volatile unsigned int*)(0x42CA0150UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD21 *((volatile unsigned int*)(0x42CA0154UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD22 *((volatile unsigned int*)(0x42CA0158UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD23 *((volatile unsigned int*)(0x42CA015CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD24 *((volatile unsigned int*)(0x42CA0160UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD25 *((volatile unsigned int*)(0x42CA0164UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD26 *((volatile unsigned int*)(0x42CA0168UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD27 *((volatile unsigned int*)(0x42CA016CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD28 *((volatile unsigned int*)(0x42CA0170UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD29 *((volatile unsigned int*)(0x42CA0174UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD30 *((volatile unsigned int*)(0x42CA0178UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD31 *((volatile unsigned int*)(0x42CA017CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL2 *((volatile unsigned int*)(0x42CA0188UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL3 *((volatile unsigned int*)(0x42CA018CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL4 *((volatile unsigned int*)(0x42CA0190UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL5 *((volatile unsigned int*)(0x42CA0194UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL6 *((volatile unsigned int*)(0x42CA0198UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL7 *((volatile unsigned int*)(0x42CA019CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL8 *((volatile unsigned int*)(0x42CA01A0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL9 *((volatile unsigned int*)(0x42CA01A4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL10 *((volatile unsigned int*)(0x42CA01A8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL11 *((volatile unsigned int*)(0x42CA01ACUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL12 *((volatile unsigned int*)(0x42CA01B0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL13 *((volatile unsigned int*)(0x42CA01B4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL14 *((volatile unsigned int*)(0x42CA01B8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL15 *((volatile unsigned int*)(0x42CA01BCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL16 *((volatile unsigned int*)(0x42CA01C0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL17 *((volatile unsigned int*)(0x42CA01C4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL18 *((volatile unsigned int*)(0x42CA01C8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL19 *((volatile unsigned int*)(0x42CA01CCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL20 *((volatile unsigned int*)(0x42CA01D0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL21 *((volatile unsigned int*)(0x42CA01D4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL22 *((volatile unsigned int*)(0x42CA01D8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL23 *((volatile unsigned int*)(0x42CA01DCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL24 *((volatile unsigned int*)(0x42CA01E0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL25 *((volatile unsigned int*)(0x42CA01E4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL26 *((volatile unsigned int*)(0x42CA01E8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL27 *((volatile unsigned int*)(0x42CA01ECUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL28 *((volatile unsigned int*)(0x42CA01F0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL29 *((volatile unsigned int*)(0x42CA01F4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL30 *((volatile unsigned int*)(0x42CA01F8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL31 *((volatile unsigned int*)(0x42CA01FCUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL2 *((volatile unsigned int*)(0x42CA0208UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL3 *((volatile unsigned int*)(0x42CA020CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL4 *((volatile unsigned int*)(0x42CA0210UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL5 *((volatile unsigned int*)(0x42CA0214UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL6 *((volatile unsigned int*)(0x42CA0218UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL7 *((volatile unsigned int*)(0x42CA021CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL8 *((volatile unsigned int*)(0x42CA0220UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL9 *((volatile unsigned int*)(0x42CA0224UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL10 *((volatile unsigned int*)(0x42CA0228UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL11 *((volatile unsigned int*)(0x42CA022CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL12 *((volatile unsigned int*)(0x42CA0230UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL13 *((volatile unsigned int*)(0x42CA0234UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL14 *((volatile unsigned int*)(0x42CA0238UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL15 *((volatile unsigned int*)(0x42CA023CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL16 *((volatile unsigned int*)(0x42CA0240UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL17 *((volatile unsigned int*)(0x42CA0244UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL18 *((volatile unsigned int*)(0x42CA0248UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL19 *((volatile unsigned int*)(0x42CA024CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL20 *((volatile unsigned int*)(0x42CA0250UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL21 *((volatile unsigned int*)(0x42CA0254UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL22 *((volatile unsigned int*)(0x42CA0258UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL23 *((volatile unsigned int*)(0x42CA025CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL24 *((volatile unsigned int*)(0x42CA0260UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL25 *((volatile unsigned int*)(0x42CA0264UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL26 *((volatile unsigned int*)(0x42CA0268UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL27 *((volatile unsigned int*)(0x42CA026CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL28 *((volatile unsigned int*)(0x42CA0270UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL29 *((volatile unsigned int*)(0x42CA0274UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL30 *((volatile unsigned int*)(0x42CA0278UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL31 *((volatile unsigned int*)(0x42CA027CUL)) +#define bFM3_ETHERNET_MAC0_SR_TI *((volatile unsigned int*)(0x42CA0280UL)) +#define bFM3_ETHERNET_MAC0_SR_TPS *((volatile unsigned int*)(0x42CA0284UL)) +#define bFM3_ETHERNET_MAC0_SR_TU *((volatile unsigned int*)(0x42CA0288UL)) +#define bFM3_ETHERNET_MAC0_SR_TJT *((volatile unsigned int*)(0x42CA028CUL)) +#define bFM3_ETHERNET_MAC0_SR_OVF *((volatile unsigned int*)(0x42CA0290UL)) +#define bFM3_ETHERNET_MAC0_SR_UNF *((volatile unsigned int*)(0x42CA0294UL)) +#define bFM3_ETHERNET_MAC0_SR_RI *((volatile unsigned int*)(0x42CA0298UL)) +#define bFM3_ETHERNET_MAC0_SR_RU *((volatile unsigned int*)(0x42CA029CUL)) +#define bFM3_ETHERNET_MAC0_SR_RPS *((volatile unsigned int*)(0x42CA02A0UL)) +#define bFM3_ETHERNET_MAC0_SR_RWT *((volatile unsigned int*)(0x42CA02A4UL)) +#define bFM3_ETHERNET_MAC0_SR_ETI *((volatile unsigned int*)(0x42CA02A8UL)) +#define bFM3_ETHERNET_MAC0_SR_FBI *((volatile unsigned int*)(0x42CA02B4UL)) +#define bFM3_ETHERNET_MAC0_SR_ERI *((volatile unsigned int*)(0x42CA02B8UL)) +#define bFM3_ETHERNET_MAC0_SR_AIS *((volatile unsigned int*)(0x42CA02BCUL)) +#define bFM3_ETHERNET_MAC0_SR_NIS *((volatile unsigned int*)(0x42CA02C0UL)) +#define bFM3_ETHERNET_MAC0_SR_RS0 *((volatile unsigned int*)(0x42CA02C4UL)) +#define bFM3_ETHERNET_MAC0_SR_RS1 *((volatile unsigned int*)(0x42CA02C8UL)) +#define bFM3_ETHERNET_MAC0_SR_RS2 *((volatile unsigned int*)(0x42CA02CCUL)) +#define bFM3_ETHERNET_MAC0_SR_TS0 *((volatile unsigned int*)(0x42CA02D0UL)) +#define bFM3_ETHERNET_MAC0_SR_TS1 *((volatile unsigned int*)(0x42CA02D4UL)) +#define bFM3_ETHERNET_MAC0_SR_TS2 *((volatile unsigned int*)(0x42CA02D8UL)) +#define bFM3_ETHERNET_MAC0_SR_EB0 *((volatile unsigned int*)(0x42CA02DCUL)) +#define bFM3_ETHERNET_MAC0_SR_EB1 *((volatile unsigned int*)(0x42CA02E0UL)) +#define bFM3_ETHERNET_MAC0_SR_EB2 *((volatile unsigned int*)(0x42CA02E4UL)) +#define bFM3_ETHERNET_MAC0_SR_GLI *((volatile unsigned int*)(0x42CA02E8UL)) +#define bFM3_ETHERNET_MAC0_SR_GMI *((volatile unsigned int*)(0x42CA02ECUL)) +#define bFM3_ETHERNET_MAC0_SR_GPI *((volatile unsigned int*)(0x42CA02F0UL)) +#define bFM3_ETHERNET_MAC0_SR_TTI *((volatile unsigned int*)(0x42CA02F4UL)) +#define bFM3_ETHERNET_MAC0_SR_GLPII *((volatile unsigned int*)(0x42CA02F8UL)) +#define bFM3_ETHERNET_MAC0_OMR_SR *((volatile unsigned int*)(0x42CA0304UL)) +#define bFM3_ETHERNET_MAC0_OMR_OSF *((volatile unsigned int*)(0x42CA0308UL)) +#define bFM3_ETHERNET_MAC0_OMR_RTC0 *((volatile unsigned int*)(0x42CA030CUL)) +#define bFM3_ETHERNET_MAC0_OMR_RTC1 *((volatile unsigned int*)(0x42CA0310UL)) +#define bFM3_ETHERNET_MAC0_OMR_FUF *((volatile unsigned int*)(0x42CA0318UL)) +#define bFM3_ETHERNET_MAC0_OMR_FEF *((volatile unsigned int*)(0x42CA031CUL)) +#define bFM3_ETHERNET_MAC0_OMR_ST *((volatile unsigned int*)(0x42CA0334UL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC0 *((volatile unsigned int*)(0x42CA0338UL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC1 *((volatile unsigned int*)(0x42CA033CUL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC2 *((volatile unsigned int*)(0x42CA0340UL)) +#define bFM3_ETHERNET_MAC0_OMR_FTF *((volatile unsigned int*)(0x42CA0350UL)) +#define bFM3_ETHERNET_MAC0_OMR_TSF *((volatile unsigned int*)(0x42CA0354UL)) +#define bFM3_ETHERNET_MAC0_OMR_DFF *((volatile unsigned int*)(0x42CA0360UL)) +#define bFM3_ETHERNET_MAC0_OMR_RSF *((volatile unsigned int*)(0x42CA0364UL)) +#define bFM3_ETHERNET_MAC0_OMR_DT *((volatile unsigned int*)(0x42CA0368UL)) +#define bFM3_ETHERNET_MAC0_IER_TIE *((volatile unsigned int*)(0x42CA0380UL)) +#define bFM3_ETHERNET_MAC0_IER_TSE *((volatile unsigned int*)(0x42CA0384UL)) +#define bFM3_ETHERNET_MAC0_IER_TUE *((volatile unsigned int*)(0x42CA0388UL)) +#define bFM3_ETHERNET_MAC0_IER_TJE *((volatile unsigned int*)(0x42CA038CUL)) +#define bFM3_ETHERNET_MAC0_IER_OVE *((volatile unsigned int*)(0x42CA0390UL)) +#define bFM3_ETHERNET_MAC0_IER_UNE *((volatile unsigned int*)(0x42CA0394UL)) +#define bFM3_ETHERNET_MAC0_IER_RIE *((volatile unsigned int*)(0x42CA0398UL)) +#define bFM3_ETHERNET_MAC0_IER_RUE *((volatile unsigned int*)(0x42CA039CUL)) +#define bFM3_ETHERNET_MAC0_IER_RSE *((volatile unsigned int*)(0x42CA03A0UL)) +#define bFM3_ETHERNET_MAC0_IER_RWE *((volatile unsigned int*)(0x42CA03A4UL)) +#define bFM3_ETHERNET_MAC0_IER_ETE *((volatile unsigned int*)(0x42CA03A8UL)) +#define bFM3_ETHERNET_MAC0_IER_FBE *((volatile unsigned int*)(0x42CA03B4UL)) +#define bFM3_ETHERNET_MAC0_IER_ERE *((volatile unsigned int*)(0x42CA03B8UL)) +#define bFM3_ETHERNET_MAC0_IER_AIE *((volatile unsigned int*)(0x42CA03BCUL)) +#define bFM3_ETHERNET_MAC0_IER_NIE *((volatile unsigned int*)(0x42CA03C0UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42CA0400UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42CA0404UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42CA0408UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42CA040CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42CA0410UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42CA0414UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42CA0418UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42CA041CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42CA0420UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42CA0424UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42CA0428UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42CA042CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42CA0430UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42CA0434UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42CA0438UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42CA043CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH *((volatile unsigned int*)(0x42CA0440UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42CA0444UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42CA0448UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42CA044CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42CA0450UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42CA0454UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42CA0458UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42CA045CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42CA0460UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42CA0464UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42CA0468UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42CA046CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF *((volatile unsigned int*)(0x42CA0470UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0 *((volatile unsigned int*)(0x42CA0480UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1 *((volatile unsigned int*)(0x42CA0484UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2 *((volatile unsigned int*)(0x42CA0488UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3 *((volatile unsigned int*)(0x42CA048CUL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4 *((volatile unsigned int*)(0x42CA0490UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5 *((volatile unsigned int*)(0x42CA0494UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6 *((volatile unsigned int*)(0x42CA0498UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7 *((volatile unsigned int*)(0x42CA049CUL)) +#define bFM3_ETHERNET_MAC0_AHBSR_AHBS *((volatile unsigned int*)(0x42CA0580UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42CA0900UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42CA0904UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42CA0908UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42CA090CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42CA0910UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42CA0914UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42CA0918UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42CA091CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42CA0920UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42CA0924UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42CA0928UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42CA092CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42CA0930UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42CA0934UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42CA0938UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42CA093CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42CA0940UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42CA0944UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42CA0948UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42CA094CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42CA0950UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42CA0954UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42CA0958UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42CA095CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42CA0960UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42CA0964UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42CA0968UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42CA096CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42CA0970UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42CA0974UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42CA0978UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42CA097CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42CA0980UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42CA0984UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42CA0988UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42CA098CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42CA0990UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42CA0994UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42CA0998UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42CA099CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42CA09A0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42CA09A4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42CA09A8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42CA09ACUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42CA09B0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42CA09B4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42CA09B8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42CA09BCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42CA09C0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42CA09C4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42CA09C8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42CA09CCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42CA09D0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42CA09D4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42CA09D8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42CA09DCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42CA09E0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42CA09E4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42CA09E8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42CA09ECUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42CA09F0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42CA09F4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42CA09F8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42CA09FCUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42CA0A00UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42CA0A04UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42CA0A08UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42CA0A0CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42CA0A10UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42CA0A14UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42CA0A18UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42CA0A1CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42CA0A20UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42CA0A24UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42CA0A28UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42CA0A2CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42CA0A30UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42CA0A34UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42CA0A38UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42CA0A3CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42CA0A40UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42CA0A44UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42CA0A48UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42CA0A4CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42CA0A50UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42CA0A54UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42CA0A58UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42CA0A5CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42CA0A60UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42CA0A64UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42CA0A68UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42CA0A6CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42CA0A70UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42CA0A74UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42CA0A78UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42CA0A7CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42CA0A80UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42CA0A84UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42CA0A88UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42CA0A8CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42CA0A90UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42CA0A94UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42CA0A98UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42CA0A9CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42CA0AA0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42CA0AA4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42CA0AA8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42CA0AACUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42CA0AB0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42CA0AB4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42CA0AB8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42CA0ABCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42CA0AC0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42CA0AC4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42CA0AC8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42CA0ACCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42CA0AD0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42CA0AD4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42CA0AD8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42CA0ADCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42CA0AE0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42CA0AE4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42CA0AE8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42CA0AECUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42CA0AF0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42CA0AF4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42CA0AF8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42CA0AFCUL)) + +/* ETHERNET-MAC-CONTROL registers */ +#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE *((volatile unsigned int*)(0x42CC0000UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0 *((volatile unsigned int*)(0x42CC0020UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1 *((volatile unsigned int*)(0x42CC0024UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL *((volatile unsigned int*)(0x42CC0070UL)) +#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0 *((volatile unsigned int*)(0x42CC0100UL)) +#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1 *((volatile unsigned int*)(0x42CC0104UL)) + +/* ETHERNET-MAC1 registers*/ +#define bFM3_ETHERNET_MAC1_MCR_RE *((volatile unsigned int*)(0x42CE0008UL)) +#define bFM3_ETHERNET_MAC1_MCR_TE *((volatile unsigned int*)(0x42CE000CUL)) +#define bFM3_ETHERNET_MAC1_MCR_DC *((volatile unsigned int*)(0x42CE0010UL)) +#define bFM3_ETHERNET_MAC1_MCR_BL0 *((volatile unsigned int*)(0x42CE0014UL)) +#define bFM3_ETHERNET_MAC1_MCR_BL1 *((volatile unsigned int*)(0x42CE0018UL)) +#define bFM3_ETHERNET_MAC1_MCR_ACS *((volatile unsigned int*)(0x42CE001CUL)) +#define bFM3_ETHERNET_MAC1_MCR_LUD *((volatile unsigned int*)(0x42CE0020UL)) +#define bFM3_ETHERNET_MAC1_MCR_DR *((volatile unsigned int*)(0x42CE0024UL)) +#define bFM3_ETHERNET_MAC1_MCR_IPC *((volatile unsigned int*)(0x42CE0028UL)) +#define bFM3_ETHERNET_MAC1_MCR_DM *((volatile unsigned int*)(0x42CE002CUL)) +#define bFM3_ETHERNET_MAC1_MCR_LM *((volatile unsigned int*)(0x42CE0030UL)) +#define bFM3_ETHERNET_MAC1_MCR_DO *((volatile unsigned int*)(0x42CE0034UL)) +#define bFM3_ETHERNET_MAC1_MCR_FES *((volatile unsigned int*)(0x42CE0038UL)) +#define bFM3_ETHERNET_MAC1_MCR_PS *((volatile unsigned int*)(0x42CE003CUL)) +#define bFM3_ETHERNET_MAC1_MCR_DCRS *((volatile unsigned int*)(0x42CE0040UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG0 *((volatile unsigned int*)(0x42CE0044UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG1 *((volatile unsigned int*)(0x42CE0048UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG2 *((volatile unsigned int*)(0x42CE004CUL)) +#define bFM3_ETHERNET_MAC1_MCR_JE *((volatile unsigned int*)(0x42CE0050UL)) +#define bFM3_ETHERNET_MAC1_MCR_BE *((volatile unsigned int*)(0x42CE0054UL)) +#define bFM3_ETHERNET_MAC1_MCR_JD *((volatile unsigned int*)(0x42CE0058UL)) +#define bFM3_ETHERNET_MAC1_MCR_WD *((volatile unsigned int*)(0x42CE005CUL)) +#define bFM3_ETHERNET_MAC1_MCR_TC *((volatile unsigned int*)(0x42CE0060UL)) +#define bFM3_ETHERNET_MAC1_MCR_CST *((volatile unsigned int*)(0x42CE0064UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PR *((volatile unsigned int*)(0x42CE0080UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HUC *((volatile unsigned int*)(0x42CE0084UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HMC *((volatile unsigned int*)(0x42CE0088UL)) +#define bFM3_ETHERNET_MAC1_MFFR_DAIF *((volatile unsigned int*)(0x42CE008CUL)) +#define bFM3_ETHERNET_MAC1_MFFR_PM *((volatile unsigned int*)(0x42CE0090UL)) +#define bFM3_ETHERNET_MAC1_MFFR_DB *((volatile unsigned int*)(0x42CE0094UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PCF0 *((volatile unsigned int*)(0x42CE0098UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PCF1 *((volatile unsigned int*)(0x42CE009CUL)) +#define bFM3_ETHERNET_MAC1_MFFR_SAIF *((volatile unsigned int*)(0x42CE00A0UL)) +#define bFM3_ETHERNET_MAC1_MFFR_SAF *((volatile unsigned int*)(0x42CE00A4UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HPF *((volatile unsigned int*)(0x42CE00A8UL)) +#define bFM3_ETHERNET_MAC1_MFFR_RA *((volatile unsigned int*)(0x42CE00FCUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH0 *((volatile unsigned int*)(0x42CE0100UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH1 *((volatile unsigned int*)(0x42CE0104UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH2 *((volatile unsigned int*)(0x42CE0108UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH3 *((volatile unsigned int*)(0x42CE010CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH4 *((volatile unsigned int*)(0x42CE0110UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH5 *((volatile unsigned int*)(0x42CE0114UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH6 *((volatile unsigned int*)(0x42CE0118UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH7 *((volatile unsigned int*)(0x42CE011CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH8 *((volatile unsigned int*)(0x42CE0120UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH9 *((volatile unsigned int*)(0x42CE0124UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH10 *((volatile unsigned int*)(0x42CE0128UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH11 *((volatile unsigned int*)(0x42CE012CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH12 *((volatile unsigned int*)(0x42CE0130UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH13 *((volatile unsigned int*)(0x42CE0134UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH14 *((volatile unsigned int*)(0x42CE0138UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH15 *((volatile unsigned int*)(0x42CE013CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH16 *((volatile unsigned int*)(0x42CE0140UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH17 *((volatile unsigned int*)(0x42CE0144UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH18 *((volatile unsigned int*)(0x42CE0148UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH19 *((volatile unsigned int*)(0x42CE014CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH20 *((volatile unsigned int*)(0x42CE0150UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH21 *((volatile unsigned int*)(0x42CE0154UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH22 *((volatile unsigned int*)(0x42CE0158UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH23 *((volatile unsigned int*)(0x42CE015CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH24 *((volatile unsigned int*)(0x42CE0160UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH25 *((volatile unsigned int*)(0x42CE0164UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH26 *((volatile unsigned int*)(0x42CE0168UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH27 *((volatile unsigned int*)(0x42CE016CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH28 *((volatile unsigned int*)(0x42CE0170UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH29 *((volatile unsigned int*)(0x42CE0174UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH30 *((volatile unsigned int*)(0x42CE0178UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH31 *((volatile unsigned int*)(0x42CE017CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL0 *((volatile unsigned int*)(0x42CE0180UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL1 *((volatile unsigned int*)(0x42CE0184UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL2 *((volatile unsigned int*)(0x42CE0188UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL3 *((volatile unsigned int*)(0x42CE018CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL4 *((volatile unsigned int*)(0x42CE0190UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL5 *((volatile unsigned int*)(0x42CE0194UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL6 *((volatile unsigned int*)(0x42CE0198UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL7 *((volatile unsigned int*)(0x42CE019CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL8 *((volatile unsigned int*)(0x42CE01A0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL9 *((volatile unsigned int*)(0x42CE01A4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL10 *((volatile unsigned int*)(0x42CE01A8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL11 *((volatile unsigned int*)(0x42CE01ACUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL12 *((volatile unsigned int*)(0x42CE01B0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL13 *((volatile unsigned int*)(0x42CE01B4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL14 *((volatile unsigned int*)(0x42CE01B8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL15 *((volatile unsigned int*)(0x42CE01BCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL16 *((volatile unsigned int*)(0x42CE01C0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL17 *((volatile unsigned int*)(0x42CE01C4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL18 *((volatile unsigned int*)(0x42CE01C8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL19 *((volatile unsigned int*)(0x42CE01CCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL20 *((volatile unsigned int*)(0x42CE01D0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL21 *((volatile unsigned int*)(0x42CE01D4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL22 *((volatile unsigned int*)(0x42CE01D8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL23 *((volatile unsigned int*)(0x42CE01DCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL24 *((volatile unsigned int*)(0x42CE01E0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL25 *((volatile unsigned int*)(0x42CE01E4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL26 *((volatile unsigned int*)(0x42CE01E8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL27 *((volatile unsigned int*)(0x42CE01ECUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL28 *((volatile unsigned int*)(0x42CE01F0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL29 *((volatile unsigned int*)(0x42CE01F4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL30 *((volatile unsigned int*)(0x42CE01F8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL31 *((volatile unsigned int*)(0x42CE01FCUL)) +#define bFM3_ETHERNET_MAC1_GAR_GB *((volatile unsigned int*)(0x42CE0200UL)) +#define bFM3_ETHERNET_MAC1_GAR_GW *((volatile unsigned int*)(0x42CE0204UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR0 *((volatile unsigned int*)(0x42CE0208UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR1 *((volatile unsigned int*)(0x42CE020CUL)) +#define bFM3_ETHERNET_MAC1_GAR_CR2 *((volatile unsigned int*)(0x42CE0210UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR3 *((volatile unsigned int*)(0x42CE0214UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR0 *((volatile unsigned int*)(0x42CE0218UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR1 *((volatile unsigned int*)(0x42CE021CUL)) +#define bFM3_ETHERNET_MAC1_GAR_GR2 *((volatile unsigned int*)(0x42CE0220UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR3 *((volatile unsigned int*)(0x42CE0224UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR4 *((volatile unsigned int*)(0x42CE0228UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA0 *((volatile unsigned int*)(0x42CE022CUL)) +#define bFM3_ETHERNET_MAC1_GAR_PA1 *((volatile unsigned int*)(0x42CE0230UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA2 *((volatile unsigned int*)(0x42CE0234UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA3 *((volatile unsigned int*)(0x42CE0238UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA4 *((volatile unsigned int*)(0x42CE023CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD0 *((volatile unsigned int*)(0x42CE0280UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD1 *((volatile unsigned int*)(0x42CE0284UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD2 *((volatile unsigned int*)(0x42CE0288UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD3 *((volatile unsigned int*)(0x42CE028CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD4 *((volatile unsigned int*)(0x42CE0290UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD5 *((volatile unsigned int*)(0x42CE0294UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD6 *((volatile unsigned int*)(0x42CE0298UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD7 *((volatile unsigned int*)(0x42CE029CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD8 *((volatile unsigned int*)(0x42CE02A0UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD9 *((volatile unsigned int*)(0x42CE02A4UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD10 *((volatile unsigned int*)(0x42CE02A8UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD11 *((volatile unsigned int*)(0x42CE02ACUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD12 *((volatile unsigned int*)(0x42CE02B0UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD13 *((volatile unsigned int*)(0x42CE02B4UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD14 *((volatile unsigned int*)(0x42CE02B8UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD15 *((volatile unsigned int*)(0x42CE02BCUL)) +#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA *((volatile unsigned int*)(0x42CE0300UL)) +#define bFM3_ETHERNET_MAC1_FCR_TFE *((volatile unsigned int*)(0x42CE0304UL)) +#define bFM3_ETHERNET_MAC1_FCR_RFE *((volatile unsigned int*)(0x42CE0308UL)) +#define bFM3_ETHERNET_MAC1_FCR_UP *((volatile unsigned int*)(0x42CE030CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PLT0 *((volatile unsigned int*)(0x42CE0310UL)) +#define bFM3_ETHERNET_MAC1_FCR_PLT1 *((volatile unsigned int*)(0x42CE0314UL)) +#define bFM3_ETHERNET_MAC1_FCR_DZPQ *((volatile unsigned int*)(0x42CE031CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT0 *((volatile unsigned int*)(0x42CE0340UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT1 *((volatile unsigned int*)(0x42CE0344UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT2 *((volatile unsigned int*)(0x42CE0348UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT3 *((volatile unsigned int*)(0x42CE034CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT4 *((volatile unsigned int*)(0x42CE0350UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT5 *((volatile unsigned int*)(0x42CE0354UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT6 *((volatile unsigned int*)(0x42CE0358UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT7 *((volatile unsigned int*)(0x42CE035CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT8 *((volatile unsigned int*)(0x42CE0360UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT9 *((volatile unsigned int*)(0x42CE0364UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT10 *((volatile unsigned int*)(0x42CE0368UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT11 *((volatile unsigned int*)(0x42CE036CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT12 *((volatile unsigned int*)(0x42CE0370UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT13 *((volatile unsigned int*)(0x42CE0374UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT14 *((volatile unsigned int*)(0x42CE0378UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT15 *((volatile unsigned int*)(0x42CE037CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL0 *((volatile unsigned int*)(0x42CE0380UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL1 *((volatile unsigned int*)(0x42CE0384UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL2 *((volatile unsigned int*)(0x42CE0388UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL3 *((volatile unsigned int*)(0x42CE038CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL4 *((volatile unsigned int*)(0x42CE0390UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL5 *((volatile unsigned int*)(0x42CE0394UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL6 *((volatile unsigned int*)(0x42CE0398UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL7 *((volatile unsigned int*)(0x42CE039CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL8 *((volatile unsigned int*)(0x42CE03A0UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL9 *((volatile unsigned int*)(0x42CE03A4UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL10 *((volatile unsigned int*)(0x42CE03A8UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL11 *((volatile unsigned int*)(0x42CE03ACUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL12 *((volatile unsigned int*)(0x42CE03B0UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL13 *((volatile unsigned int*)(0x42CE03B4UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL14 *((volatile unsigned int*)(0x42CE03B8UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL15 *((volatile unsigned int*)(0x42CE03BCUL)) +#define bFM3_ETHERNET_MAC1_VTR_ETV *((volatile unsigned int*)(0x42CE03C0UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42CE0500UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42CE0504UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42CE0508UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42CE050CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42CE0510UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42CE0514UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42CE0518UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42CE051CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42CE0520UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42CE0524UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42CE0528UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42CE052CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42CE0530UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42CE0534UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42CE0538UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42CE053CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42CE0540UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42CE0544UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42CE0548UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42CE054CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42CE0550UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42CE0554UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42CE0558UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42CE055CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42CE0560UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42CE0564UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42CE0568UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42CE056CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42CE0570UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42CE0574UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42CE0578UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42CE057CUL)) +#define bFM3_ETHERNET_MAC1_PMTR_PD *((volatile unsigned int*)(0x42CE0580UL)) +#define bFM3_ETHERNET_MAC1_PMTR_MPE *((volatile unsigned int*)(0x42CE0584UL)) +#define bFM3_ETHERNET_MAC1_PMTR_WFE *((volatile unsigned int*)(0x42CE0588UL)) +#define bFM3_ETHERNET_MAC1_PMTR_MPR *((volatile unsigned int*)(0x42CE0594UL)) +#define bFM3_ETHERNET_MAC1_PMTR_WPR *((volatile unsigned int*)(0x42CE0598UL)) +#define bFM3_ETHERNET_MAC1_PMTR_GU *((volatile unsigned int*)(0x42CE05A4UL)) +#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR *((volatile unsigned int*)(0x42CE05FCUL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN *((volatile unsigned int*)(0x42CE0600UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX *((volatile unsigned int*)(0x42CE0604UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN *((volatile unsigned int*)(0x42CE0608UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX *((volatile unsigned int*)(0x42CE060CUL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST *((volatile unsigned int*)(0x42CE0620UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST *((volatile unsigned int*)(0x42CE0624UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN *((volatile unsigned int*)(0x42CE0640UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_PLS *((volatile unsigned int*)(0x42CE0644UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN *((volatile unsigned int*)(0x42CE0648UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA *((volatile unsigned int*)(0x42CE064CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT0 *((volatile unsigned int*)(0x42CE0680UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT1 *((volatile unsigned int*)(0x42CE0684UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT2 *((volatile unsigned int*)(0x42CE0688UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT3 *((volatile unsigned int*)(0x42CE068CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT4 *((volatile unsigned int*)(0x42CE0690UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT5 *((volatile unsigned int*)(0x42CE0694UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT6 *((volatile unsigned int*)(0x42CE0698UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT7 *((volatile unsigned int*)(0x42CE069CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT8 *((volatile unsigned int*)(0x42CE06A0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT9 *((volatile unsigned int*)(0x42CE06A4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT10 *((volatile unsigned int*)(0x42CE06A8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT11 *((volatile unsigned int*)(0x42CE06ACUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT12 *((volatile unsigned int*)(0x42CE06B0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT13 *((volatile unsigned int*)(0x42CE06B4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT14 *((volatile unsigned int*)(0x42CE06B8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT15 *((volatile unsigned int*)(0x42CE06BCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT0 *((volatile unsigned int*)(0x42CE06C0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT1 *((volatile unsigned int*)(0x42CE06C4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT2 *((volatile unsigned int*)(0x42CE06C8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT3 *((volatile unsigned int*)(0x42CE06CCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT4 *((volatile unsigned int*)(0x42CE06D0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT5 *((volatile unsigned int*)(0x42CE06D4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT6 *((volatile unsigned int*)(0x42CE06D8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT7 *((volatile unsigned int*)(0x42CE06DCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT8 *((volatile unsigned int*)(0x42CE06E0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT9 *((volatile unsigned int*)(0x42CE06E4UL)) +#define bFM3_ETHERNET_MAC1_ISR_RGIS *((volatile unsigned int*)(0x42CE0700UL)) +#define bFM3_ETHERNET_MAC1_ISR_PIS *((volatile unsigned int*)(0x42CE070CUL)) +#define bFM3_ETHERNET_MAC1_ISR_MIS *((volatile unsigned int*)(0x42CE0710UL)) +#define bFM3_ETHERNET_MAC1_ISR_RIS *((volatile unsigned int*)(0x42CE0714UL)) +#define bFM3_ETHERNET_MAC1_ISR_TIS *((volatile unsigned int*)(0x42CE0718UL)) +#define bFM3_ETHERNET_MAC1_ISR_COIS *((volatile unsigned int*)(0x42CE071CUL)) +#define bFM3_ETHERNET_MAC1_ISR_TSIS *((volatile unsigned int*)(0x42CE0724UL)) +#define bFM3_ETHERNET_MAC1_ISR_LPIIS *((volatile unsigned int*)(0x42CE0728UL)) +#define bFM3_ETHERNET_MAC1_IMR_RGIM *((volatile unsigned int*)(0x42CE0780UL)) +#define bFM3_ETHERNET_MAC1_IMR_PIM *((volatile unsigned int*)(0x42CE078CUL)) +#define bFM3_ETHERNET_MAC1_IMR_TSIM *((volatile unsigned int*)(0x42CE0794UL)) +#define bFM3_ETHERNET_MAC1_IMR_LPIIM *((volatile unsigned int*)(0x42CE0798UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A32 *((volatile unsigned int*)(0x42CE0800UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A33 *((volatile unsigned int*)(0x42CE0804UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A34 *((volatile unsigned int*)(0x42CE0808UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A35 *((volatile unsigned int*)(0x42CE080CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A36 *((volatile unsigned int*)(0x42CE0810UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A37 *((volatile unsigned int*)(0x42CE0814UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A38 *((volatile unsigned int*)(0x42CE0818UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A39 *((volatile unsigned int*)(0x42CE081CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A40 *((volatile unsigned int*)(0x42CE0820UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A41 *((volatile unsigned int*)(0x42CE0824UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A42 *((volatile unsigned int*)(0x42CE0828UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A43 *((volatile unsigned int*)(0x42CE082CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A44 *((volatile unsigned int*)(0x42CE0830UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A45 *((volatile unsigned int*)(0x42CE0834UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A46 *((volatile unsigned int*)(0x42CE0838UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A47 *((volatile unsigned int*)(0x42CE083CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_MO *((volatile unsigned int*)(0x42CE087CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A0 *((volatile unsigned int*)(0x42CE0880UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A1 *((volatile unsigned int*)(0x42CE0884UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A2 *((volatile unsigned int*)(0x42CE0888UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A3 *((volatile unsigned int*)(0x42CE088CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A4 *((volatile unsigned int*)(0x42CE0890UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A5 *((volatile unsigned int*)(0x42CE0894UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A6 *((volatile unsigned int*)(0x42CE0898UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A7 *((volatile unsigned int*)(0x42CE089CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A8 *((volatile unsigned int*)(0x42CE08A0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A9 *((volatile unsigned int*)(0x42CE08A4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A10 *((volatile unsigned int*)(0x42CE08A8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A11 *((volatile unsigned int*)(0x42CE08ACUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A12 *((volatile unsigned int*)(0x42CE08B0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A13 *((volatile unsigned int*)(0x42CE08B4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A14 *((volatile unsigned int*)(0x42CE08B8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A15 *((volatile unsigned int*)(0x42CE08BCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A16 *((volatile unsigned int*)(0x42CE08C0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A17 *((volatile unsigned int*)(0x42CE08C4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A18 *((volatile unsigned int*)(0x42CE08C8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A19 *((volatile unsigned int*)(0x42CE08CCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A20 *((volatile unsigned int*)(0x42CE08D0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A21 *((volatile unsigned int*)(0x42CE08D4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A22 *((volatile unsigned int*)(0x42CE08D8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A23 *((volatile unsigned int*)(0x42CE08DCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A24 *((volatile unsigned int*)(0x42CE08E0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A25 *((volatile unsigned int*)(0x42CE08E4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A26 *((volatile unsigned int*)(0x42CE08E8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A27 *((volatile unsigned int*)(0x42CE08ECUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A28 *((volatile unsigned int*)(0x42CE08F0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A29 *((volatile unsigned int*)(0x42CE08F4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A30 *((volatile unsigned int*)(0x42CE08F8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A31 *((volatile unsigned int*)(0x42CE08FCUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A32 *((volatile unsigned int*)(0x42CE0900UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A33 *((volatile unsigned int*)(0x42CE0904UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A34 *((volatile unsigned int*)(0x42CE0908UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A35 *((volatile unsigned int*)(0x42CE090CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A36 *((volatile unsigned int*)(0x42CE0910UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A37 *((volatile unsigned int*)(0x42CE0914UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A38 *((volatile unsigned int*)(0x42CE0918UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A39 *((volatile unsigned int*)(0x42CE091CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A40 *((volatile unsigned int*)(0x42CE0920UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A41 *((volatile unsigned int*)(0x42CE0924UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A42 *((volatile unsigned int*)(0x42CE0928UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A43 *((volatile unsigned int*)(0x42CE092CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A44 *((volatile unsigned int*)(0x42CE0930UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A45 *((volatile unsigned int*)(0x42CE0934UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A46 *((volatile unsigned int*)(0x42CE0938UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A47 *((volatile unsigned int*)(0x42CE093CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC0 *((volatile unsigned int*)(0x42CE0960UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC1 *((volatile unsigned int*)(0x42CE0964UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC2 *((volatile unsigned int*)(0x42CE0968UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC3 *((volatile unsigned int*)(0x42CE096CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC4 *((volatile unsigned int*)(0x42CE0970UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC5 *((volatile unsigned int*)(0x42CE0974UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_SA *((volatile unsigned int*)(0x42CE0978UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_AE *((volatile unsigned int*)(0x42CE097CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A0 *((volatile unsigned int*)(0x42CE0980UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A1 *((volatile unsigned int*)(0x42CE0984UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A2 *((volatile unsigned int*)(0x42CE0988UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A3 *((volatile unsigned int*)(0x42CE098CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A4 *((volatile unsigned int*)(0x42CE0990UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A5 *((volatile unsigned int*)(0x42CE0994UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A6 *((volatile unsigned int*)(0x42CE0998UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A7 *((volatile unsigned int*)(0x42CE099CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A8 *((volatile unsigned int*)(0x42CE09A0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A9 *((volatile unsigned int*)(0x42CE09A4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A10 *((volatile unsigned int*)(0x42CE09A8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A11 *((volatile unsigned int*)(0x42CE09ACUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A12 *((volatile unsigned int*)(0x42CE09B0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A13 *((volatile unsigned int*)(0x42CE09B4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A14 *((volatile unsigned int*)(0x42CE09B8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A15 *((volatile unsigned int*)(0x42CE09BCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A16 *((volatile unsigned int*)(0x42CE09C0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A17 *((volatile unsigned int*)(0x42CE09C4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A18 *((volatile unsigned int*)(0x42CE09C8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A19 *((volatile unsigned int*)(0x42CE09CCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A20 *((volatile unsigned int*)(0x42CE09D0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A21 *((volatile unsigned int*)(0x42CE09D4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A22 *((volatile unsigned int*)(0x42CE09D8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A23 *((volatile unsigned int*)(0x42CE09DCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A24 *((volatile unsigned int*)(0x42CE09E0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A25 *((volatile unsigned int*)(0x42CE09E4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A26 *((volatile unsigned int*)(0x42CE09E8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A27 *((volatile unsigned int*)(0x42CE09ECUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A28 *((volatile unsigned int*)(0x42CE09F0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A29 *((volatile unsigned int*)(0x42CE09F4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A30 *((volatile unsigned int*)(0x42CE09F8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A31 *((volatile unsigned int*)(0x42CE09FCUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A32 *((volatile unsigned int*)(0x42CE0A00UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A33 *((volatile unsigned int*)(0x42CE0A04UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A34 *((volatile unsigned int*)(0x42CE0A08UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A35 *((volatile unsigned int*)(0x42CE0A0CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A36 *((volatile unsigned int*)(0x42CE0A10UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A37 *((volatile unsigned int*)(0x42CE0A14UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A38 *((volatile unsigned int*)(0x42CE0A18UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A39 *((volatile unsigned int*)(0x42CE0A1CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A40 *((volatile unsigned int*)(0x42CE0A20UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A41 *((volatile unsigned int*)(0x42CE0A24UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A42 *((volatile unsigned int*)(0x42CE0A28UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A43 *((volatile unsigned int*)(0x42CE0A2CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A44 *((volatile unsigned int*)(0x42CE0A30UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A45 *((volatile unsigned int*)(0x42CE0A34UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A46 *((volatile unsigned int*)(0x42CE0A38UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A47 *((volatile unsigned int*)(0x42CE0A3CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC0 *((volatile unsigned int*)(0x42CE0A60UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC1 *((volatile unsigned int*)(0x42CE0A64UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC2 *((volatile unsigned int*)(0x42CE0A68UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC3 *((volatile unsigned int*)(0x42CE0A6CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC4 *((volatile unsigned int*)(0x42CE0A70UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC5 *((volatile unsigned int*)(0x42CE0A74UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_SA *((volatile unsigned int*)(0x42CE0A78UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_AE *((volatile unsigned int*)(0x42CE0A7CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A0 *((volatile unsigned int*)(0x42CE0A80UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A1 *((volatile unsigned int*)(0x42CE0A84UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A2 *((volatile unsigned int*)(0x42CE0A88UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A3 *((volatile unsigned int*)(0x42CE0A8CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A4 *((volatile unsigned int*)(0x42CE0A90UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A5 *((volatile unsigned int*)(0x42CE0A94UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A6 *((volatile unsigned int*)(0x42CE0A98UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A7 *((volatile unsigned int*)(0x42CE0A9CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A8 *((volatile unsigned int*)(0x42CE0AA0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A9 *((volatile unsigned int*)(0x42CE0AA4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A10 *((volatile unsigned int*)(0x42CE0AA8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A11 *((volatile unsigned int*)(0x42CE0AACUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A12 *((volatile unsigned int*)(0x42CE0AB0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A13 *((volatile unsigned int*)(0x42CE0AB4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A14 *((volatile unsigned int*)(0x42CE0AB8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A15 *((volatile unsigned int*)(0x42CE0ABCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A16 *((volatile unsigned int*)(0x42CE0AC0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A17 *((volatile unsigned int*)(0x42CE0AC4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A18 *((volatile unsigned int*)(0x42CE0AC8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A19 *((volatile unsigned int*)(0x42CE0ACCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A20 *((volatile unsigned int*)(0x42CE0AD0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A21 *((volatile unsigned int*)(0x42CE0AD4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A22 *((volatile unsigned int*)(0x42CE0AD8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A23 *((volatile unsigned int*)(0x42CE0ADCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A24 *((volatile unsigned int*)(0x42CE0AE0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A25 *((volatile unsigned int*)(0x42CE0AE4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A26 *((volatile unsigned int*)(0x42CE0AE8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A27 *((volatile unsigned int*)(0x42CE0AECUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A28 *((volatile unsigned int*)(0x42CE0AF0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A29 *((volatile unsigned int*)(0x42CE0AF4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A30 *((volatile unsigned int*)(0x42CE0AF8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A31 *((volatile unsigned int*)(0x42CE0AFCUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A32 *((volatile unsigned int*)(0x42CE0B00UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A33 *((volatile unsigned int*)(0x42CE0B04UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A34 *((volatile unsigned int*)(0x42CE0B08UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A35 *((volatile unsigned int*)(0x42CE0B0CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A36 *((volatile unsigned int*)(0x42CE0B10UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A37 *((volatile unsigned int*)(0x42CE0B14UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A38 *((volatile unsigned int*)(0x42CE0B18UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A39 *((volatile unsigned int*)(0x42CE0B1CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A40 *((volatile unsigned int*)(0x42CE0B20UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A41 *((volatile unsigned int*)(0x42CE0B24UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A42 *((volatile unsigned int*)(0x42CE0B28UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A43 *((volatile unsigned int*)(0x42CE0B2CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A44 *((volatile unsigned int*)(0x42CE0B30UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A45 *((volatile unsigned int*)(0x42CE0B34UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A46 *((volatile unsigned int*)(0x42CE0B38UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A47 *((volatile unsigned int*)(0x42CE0B3CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC0 *((volatile unsigned int*)(0x42CE0B60UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC1 *((volatile unsigned int*)(0x42CE0B64UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC2 *((volatile unsigned int*)(0x42CE0B68UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC3 *((volatile unsigned int*)(0x42CE0B6CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC4 *((volatile unsigned int*)(0x42CE0B70UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC5 *((volatile unsigned int*)(0x42CE0B74UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_SA *((volatile unsigned int*)(0x42CE0B78UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_AE *((volatile unsigned int*)(0x42CE0B7CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A0 *((volatile unsigned int*)(0x42CE0B80UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A1 *((volatile unsigned int*)(0x42CE0B84UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A2 *((volatile unsigned int*)(0x42CE0B88UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A3 *((volatile unsigned int*)(0x42CE0B8CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A4 *((volatile unsigned int*)(0x42CE0B90UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A5 *((volatile unsigned int*)(0x42CE0B94UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A6 *((volatile unsigned int*)(0x42CE0B98UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A7 *((volatile unsigned int*)(0x42CE0B9CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A8 *((volatile unsigned int*)(0x42CE0BA0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A9 *((volatile unsigned int*)(0x42CE0BA4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A10 *((volatile unsigned int*)(0x42CE0BA8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A11 *((volatile unsigned int*)(0x42CE0BACUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A12 *((volatile unsigned int*)(0x42CE0BB0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A13 *((volatile unsigned int*)(0x42CE0BB4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A14 *((volatile unsigned int*)(0x42CE0BB8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A15 *((volatile unsigned int*)(0x42CE0BBCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A16 *((volatile unsigned int*)(0x42CE0BC0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A17 *((volatile unsigned int*)(0x42CE0BC4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A18 *((volatile unsigned int*)(0x42CE0BC8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A19 *((volatile unsigned int*)(0x42CE0BCCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A20 *((volatile unsigned int*)(0x42CE0BD0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A21 *((volatile unsigned int*)(0x42CE0BD4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A22 *((volatile unsigned int*)(0x42CE0BD8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A23 *((volatile unsigned int*)(0x42CE0BDCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A24 *((volatile unsigned int*)(0x42CE0BE0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A25 *((volatile unsigned int*)(0x42CE0BE4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A26 *((volatile unsigned int*)(0x42CE0BE8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A27 *((volatile unsigned int*)(0x42CE0BECUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A28 *((volatile unsigned int*)(0x42CE0BF0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A29 *((volatile unsigned int*)(0x42CE0BF4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A30 *((volatile unsigned int*)(0x42CE0BF8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A31 *((volatile unsigned int*)(0x42CE0BFCUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A32 *((volatile unsigned int*)(0x42CE0C00UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A33 *((volatile unsigned int*)(0x42CE0C04UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A34 *((volatile unsigned int*)(0x42CE0C08UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A35 *((volatile unsigned int*)(0x42CE0C0CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A36 *((volatile unsigned int*)(0x42CE0C10UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A37 *((volatile unsigned int*)(0x42CE0C14UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A38 *((volatile unsigned int*)(0x42CE0C18UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A39 *((volatile unsigned int*)(0x42CE0C1CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A40 *((volatile unsigned int*)(0x42CE0C20UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A41 *((volatile unsigned int*)(0x42CE0C24UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A42 *((volatile unsigned int*)(0x42CE0C28UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A43 *((volatile unsigned int*)(0x42CE0C2CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A44 *((volatile unsigned int*)(0x42CE0C30UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A45 *((volatile unsigned int*)(0x42CE0C34UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A46 *((volatile unsigned int*)(0x42CE0C38UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A47 *((volatile unsigned int*)(0x42CE0C3CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC0 *((volatile unsigned int*)(0x42CE0C60UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC1 *((volatile unsigned int*)(0x42CE0C64UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC2 *((volatile unsigned int*)(0x42CE0C68UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC3 *((volatile unsigned int*)(0x42CE0C6CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC4 *((volatile unsigned int*)(0x42CE0C70UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC5 *((volatile unsigned int*)(0x42CE0C74UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_SA *((volatile unsigned int*)(0x42CE0C78UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_AE *((volatile unsigned int*)(0x42CE0C7CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A0 *((volatile unsigned int*)(0x42CE0C80UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A1 *((volatile unsigned int*)(0x42CE0C84UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A2 *((volatile unsigned int*)(0x42CE0C88UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A3 *((volatile unsigned int*)(0x42CE0C8CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A4 *((volatile unsigned int*)(0x42CE0C90UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A5 *((volatile unsigned int*)(0x42CE0C94UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A6 *((volatile unsigned int*)(0x42CE0C98UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A7 *((volatile unsigned int*)(0x42CE0C9CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A8 *((volatile unsigned int*)(0x42CE0CA0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A9 *((volatile unsigned int*)(0x42CE0CA4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A10 *((volatile unsigned int*)(0x42CE0CA8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A11 *((volatile unsigned int*)(0x42CE0CACUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A12 *((volatile unsigned int*)(0x42CE0CB0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A13 *((volatile unsigned int*)(0x42CE0CB4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A14 *((volatile unsigned int*)(0x42CE0CB8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A15 *((volatile unsigned int*)(0x42CE0CBCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A16 *((volatile unsigned int*)(0x42CE0CC0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A17 *((volatile unsigned int*)(0x42CE0CC4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A18 *((volatile unsigned int*)(0x42CE0CC8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A19 *((volatile unsigned int*)(0x42CE0CCCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A20 *((volatile unsigned int*)(0x42CE0CD0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A21 *((volatile unsigned int*)(0x42CE0CD4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A22 *((volatile unsigned int*)(0x42CE0CD8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A23 *((volatile unsigned int*)(0x42CE0CDCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A24 *((volatile unsigned int*)(0x42CE0CE0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A25 *((volatile unsigned int*)(0x42CE0CE4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A26 *((volatile unsigned int*)(0x42CE0CE8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A27 *((volatile unsigned int*)(0x42CE0CECUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A28 *((volatile unsigned int*)(0x42CE0CF0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A29 *((volatile unsigned int*)(0x42CE0CF4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A30 *((volatile unsigned int*)(0x42CE0CF8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A31 *((volatile unsigned int*)(0x42CE0CFCUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A32 *((volatile unsigned int*)(0x42CE0D00UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A33 *((volatile unsigned int*)(0x42CE0D04UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A34 *((volatile unsigned int*)(0x42CE0D08UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A35 *((volatile unsigned int*)(0x42CE0D0CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A36 *((volatile unsigned int*)(0x42CE0D10UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A37 *((volatile unsigned int*)(0x42CE0D14UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A38 *((volatile unsigned int*)(0x42CE0D18UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A39 *((volatile unsigned int*)(0x42CE0D1CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A40 *((volatile unsigned int*)(0x42CE0D20UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A41 *((volatile unsigned int*)(0x42CE0D24UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A42 *((volatile unsigned int*)(0x42CE0D28UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A43 *((volatile unsigned int*)(0x42CE0D2CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A44 *((volatile unsigned int*)(0x42CE0D30UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A45 *((volatile unsigned int*)(0x42CE0D34UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A46 *((volatile unsigned int*)(0x42CE0D38UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A47 *((volatile unsigned int*)(0x42CE0D3CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC0 *((volatile unsigned int*)(0x42CE0D60UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC1 *((volatile unsigned int*)(0x42CE0D64UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC2 *((volatile unsigned int*)(0x42CE0D68UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC3 *((volatile unsigned int*)(0x42CE0D6CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC4 *((volatile unsigned int*)(0x42CE0D70UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC5 *((volatile unsigned int*)(0x42CE0D74UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_SA *((volatile unsigned int*)(0x42CE0D78UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_AE *((volatile unsigned int*)(0x42CE0D7CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A0 *((volatile unsigned int*)(0x42CE0D80UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A1 *((volatile unsigned int*)(0x42CE0D84UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A2 *((volatile unsigned int*)(0x42CE0D88UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A3 *((volatile unsigned int*)(0x42CE0D8CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A4 *((volatile unsigned int*)(0x42CE0D90UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A5 *((volatile unsigned int*)(0x42CE0D94UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A6 *((volatile unsigned int*)(0x42CE0D98UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A7 *((volatile unsigned int*)(0x42CE0D9CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A8 *((volatile unsigned int*)(0x42CE0DA0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A9 *((volatile unsigned int*)(0x42CE0DA4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A10 *((volatile unsigned int*)(0x42CE0DA8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A11 *((volatile unsigned int*)(0x42CE0DACUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A12 *((volatile unsigned int*)(0x42CE0DB0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A13 *((volatile unsigned int*)(0x42CE0DB4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A14 *((volatile unsigned int*)(0x42CE0DB8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A15 *((volatile unsigned int*)(0x42CE0DBCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A16 *((volatile unsigned int*)(0x42CE0DC0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A17 *((volatile unsigned int*)(0x42CE0DC4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A18 *((volatile unsigned int*)(0x42CE0DC8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A19 *((volatile unsigned int*)(0x42CE0DCCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A20 *((volatile unsigned int*)(0x42CE0DD0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A21 *((volatile unsigned int*)(0x42CE0DD4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A22 *((volatile unsigned int*)(0x42CE0DD8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A23 *((volatile unsigned int*)(0x42CE0DDCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A24 *((volatile unsigned int*)(0x42CE0DE0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A25 *((volatile unsigned int*)(0x42CE0DE4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A26 *((volatile unsigned int*)(0x42CE0DE8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A27 *((volatile unsigned int*)(0x42CE0DECUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A28 *((volatile unsigned int*)(0x42CE0DF0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A29 *((volatile unsigned int*)(0x42CE0DF4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A30 *((volatile unsigned int*)(0x42CE0DF8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A31 *((volatile unsigned int*)(0x42CE0DFCUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A32 *((volatile unsigned int*)(0x42CE0E00UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A33 *((volatile unsigned int*)(0x42CE0E04UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A34 *((volatile unsigned int*)(0x42CE0E08UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A35 *((volatile unsigned int*)(0x42CE0E0CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A36 *((volatile unsigned int*)(0x42CE0E10UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A37 *((volatile unsigned int*)(0x42CE0E14UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A38 *((volatile unsigned int*)(0x42CE0E18UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A39 *((volatile unsigned int*)(0x42CE0E1CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A40 *((volatile unsigned int*)(0x42CE0E20UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A41 *((volatile unsigned int*)(0x42CE0E24UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A42 *((volatile unsigned int*)(0x42CE0E28UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A43 *((volatile unsigned int*)(0x42CE0E2CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A44 *((volatile unsigned int*)(0x42CE0E30UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A45 *((volatile unsigned int*)(0x42CE0E34UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A46 *((volatile unsigned int*)(0x42CE0E38UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A47 *((volatile unsigned int*)(0x42CE0E3CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC0 *((volatile unsigned int*)(0x42CE0E60UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC1 *((volatile unsigned int*)(0x42CE0E64UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC2 *((volatile unsigned int*)(0x42CE0E68UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC3 *((volatile unsigned int*)(0x42CE0E6CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC4 *((volatile unsigned int*)(0x42CE0E70UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC5 *((volatile unsigned int*)(0x42CE0E74UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_SA *((volatile unsigned int*)(0x42CE0E78UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_AE *((volatile unsigned int*)(0x42CE0E7CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A0 *((volatile unsigned int*)(0x42CE0E80UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A1 *((volatile unsigned int*)(0x42CE0E84UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A2 *((volatile unsigned int*)(0x42CE0E88UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A3 *((volatile unsigned int*)(0x42CE0E8CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A4 *((volatile unsigned int*)(0x42CE0E90UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A5 *((volatile unsigned int*)(0x42CE0E94UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A6 *((volatile unsigned int*)(0x42CE0E98UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A7 *((volatile unsigned int*)(0x42CE0E9CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A8 *((volatile unsigned int*)(0x42CE0EA0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A9 *((volatile unsigned int*)(0x42CE0EA4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A10 *((volatile unsigned int*)(0x42CE0EA8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A11 *((volatile unsigned int*)(0x42CE0EACUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A12 *((volatile unsigned int*)(0x42CE0EB0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A13 *((volatile unsigned int*)(0x42CE0EB4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A14 *((volatile unsigned int*)(0x42CE0EB8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A15 *((volatile unsigned int*)(0x42CE0EBCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A16 *((volatile unsigned int*)(0x42CE0EC0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A17 *((volatile unsigned int*)(0x42CE0EC4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A18 *((volatile unsigned int*)(0x42CE0EC8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A19 *((volatile unsigned int*)(0x42CE0ECCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A20 *((volatile unsigned int*)(0x42CE0ED0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A21 *((volatile unsigned int*)(0x42CE0ED4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A22 *((volatile unsigned int*)(0x42CE0ED8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A23 *((volatile unsigned int*)(0x42CE0EDCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A24 *((volatile unsigned int*)(0x42CE0EE0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A25 *((volatile unsigned int*)(0x42CE0EE4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A26 *((volatile unsigned int*)(0x42CE0EE8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A27 *((volatile unsigned int*)(0x42CE0EECUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A28 *((volatile unsigned int*)(0x42CE0EF0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A29 *((volatile unsigned int*)(0x42CE0EF4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A30 *((volatile unsigned int*)(0x42CE0EF8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A31 *((volatile unsigned int*)(0x42CE0EFCUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A32 *((volatile unsigned int*)(0x42CE0F00UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A33 *((volatile unsigned int*)(0x42CE0F04UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A34 *((volatile unsigned int*)(0x42CE0F08UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A35 *((volatile unsigned int*)(0x42CE0F0CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A36 *((volatile unsigned int*)(0x42CE0F10UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A37 *((volatile unsigned int*)(0x42CE0F14UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A38 *((volatile unsigned int*)(0x42CE0F18UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A39 *((volatile unsigned int*)(0x42CE0F1CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A40 *((volatile unsigned int*)(0x42CE0F20UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A41 *((volatile unsigned int*)(0x42CE0F24UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A42 *((volatile unsigned int*)(0x42CE0F28UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A43 *((volatile unsigned int*)(0x42CE0F2CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A44 *((volatile unsigned int*)(0x42CE0F30UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A45 *((volatile unsigned int*)(0x42CE0F34UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A46 *((volatile unsigned int*)(0x42CE0F38UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A47 *((volatile unsigned int*)(0x42CE0F3CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC0 *((volatile unsigned int*)(0x42CE0F60UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC1 *((volatile unsigned int*)(0x42CE0F64UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC2 *((volatile unsigned int*)(0x42CE0F68UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC3 *((volatile unsigned int*)(0x42CE0F6CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC4 *((volatile unsigned int*)(0x42CE0F70UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC5 *((volatile unsigned int*)(0x42CE0F74UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_SA *((volatile unsigned int*)(0x42CE0F78UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_AE *((volatile unsigned int*)(0x42CE0F7CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A0 *((volatile unsigned int*)(0x42CE0F80UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A1 *((volatile unsigned int*)(0x42CE0F84UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A2 *((volatile unsigned int*)(0x42CE0F88UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A3 *((volatile unsigned int*)(0x42CE0F8CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A4 *((volatile unsigned int*)(0x42CE0F90UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A5 *((volatile unsigned int*)(0x42CE0F94UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A6 *((volatile unsigned int*)(0x42CE0F98UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A7 *((volatile unsigned int*)(0x42CE0F9CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A8 *((volatile unsigned int*)(0x42CE0FA0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A9 *((volatile unsigned int*)(0x42CE0FA4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A10 *((volatile unsigned int*)(0x42CE0FA8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A11 *((volatile unsigned int*)(0x42CE0FACUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A12 *((volatile unsigned int*)(0x42CE0FB0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A13 *((volatile unsigned int*)(0x42CE0FB4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A14 *((volatile unsigned int*)(0x42CE0FB8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A15 *((volatile unsigned int*)(0x42CE0FBCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A16 *((volatile unsigned int*)(0x42CE0FC0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A17 *((volatile unsigned int*)(0x42CE0FC4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A18 *((volatile unsigned int*)(0x42CE0FC8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A19 *((volatile unsigned int*)(0x42CE0FCCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A20 *((volatile unsigned int*)(0x42CE0FD0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A21 *((volatile unsigned int*)(0x42CE0FD4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A22 *((volatile unsigned int*)(0x42CE0FD8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A23 *((volatile unsigned int*)(0x42CE0FDCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A24 *((volatile unsigned int*)(0x42CE0FE0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A25 *((volatile unsigned int*)(0x42CE0FE4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A26 *((volatile unsigned int*)(0x42CE0FE8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A27 *((volatile unsigned int*)(0x42CE0FECUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A28 *((volatile unsigned int*)(0x42CE0FF0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A29 *((volatile unsigned int*)(0x42CE0FF4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A30 *((volatile unsigned int*)(0x42CE0FF8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A31 *((volatile unsigned int*)(0x42CE0FFCUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A32 *((volatile unsigned int*)(0x42CE1000UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A33 *((volatile unsigned int*)(0x42CE1004UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A34 *((volatile unsigned int*)(0x42CE1008UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A35 *((volatile unsigned int*)(0x42CE100CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A36 *((volatile unsigned int*)(0x42CE1010UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A37 *((volatile unsigned int*)(0x42CE1014UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A38 *((volatile unsigned int*)(0x42CE1018UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A39 *((volatile unsigned int*)(0x42CE101CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A40 *((volatile unsigned int*)(0x42CE1020UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A41 *((volatile unsigned int*)(0x42CE1024UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A42 *((volatile unsigned int*)(0x42CE1028UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A43 *((volatile unsigned int*)(0x42CE102CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A44 *((volatile unsigned int*)(0x42CE1030UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A45 *((volatile unsigned int*)(0x42CE1034UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A46 *((volatile unsigned int*)(0x42CE1038UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A47 *((volatile unsigned int*)(0x42CE103CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC0 *((volatile unsigned int*)(0x42CE1060UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC1 *((volatile unsigned int*)(0x42CE1064UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC2 *((volatile unsigned int*)(0x42CE1068UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC3 *((volatile unsigned int*)(0x42CE106CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC4 *((volatile unsigned int*)(0x42CE1070UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC5 *((volatile unsigned int*)(0x42CE1074UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_SA *((volatile unsigned int*)(0x42CE1078UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_AE *((volatile unsigned int*)(0x42CE107CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A0 *((volatile unsigned int*)(0x42CE1080UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A1 *((volatile unsigned int*)(0x42CE1084UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A2 *((volatile unsigned int*)(0x42CE1088UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A3 *((volatile unsigned int*)(0x42CE108CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A4 *((volatile unsigned int*)(0x42CE1090UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A5 *((volatile unsigned int*)(0x42CE1094UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A6 *((volatile unsigned int*)(0x42CE1098UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A7 *((volatile unsigned int*)(0x42CE109CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A8 *((volatile unsigned int*)(0x42CE10A0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A9 *((volatile unsigned int*)(0x42CE10A4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A10 *((volatile unsigned int*)(0x42CE10A8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A11 *((volatile unsigned int*)(0x42CE10ACUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A12 *((volatile unsigned int*)(0x42CE10B0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A13 *((volatile unsigned int*)(0x42CE10B4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A14 *((volatile unsigned int*)(0x42CE10B8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A15 *((volatile unsigned int*)(0x42CE10BCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A16 *((volatile unsigned int*)(0x42CE10C0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A17 *((volatile unsigned int*)(0x42CE10C4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A18 *((volatile unsigned int*)(0x42CE10C8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A19 *((volatile unsigned int*)(0x42CE10CCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A20 *((volatile unsigned int*)(0x42CE10D0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A21 *((volatile unsigned int*)(0x42CE10D4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A22 *((volatile unsigned int*)(0x42CE10D8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A23 *((volatile unsigned int*)(0x42CE10DCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A24 *((volatile unsigned int*)(0x42CE10E0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A25 *((volatile unsigned int*)(0x42CE10E4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A26 *((volatile unsigned int*)(0x42CE10E8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A27 *((volatile unsigned int*)(0x42CE10ECUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A28 *((volatile unsigned int*)(0x42CE10F0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A29 *((volatile unsigned int*)(0x42CE10F4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A30 *((volatile unsigned int*)(0x42CE10F8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A31 *((volatile unsigned int*)(0x42CE10FCUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A32 *((volatile unsigned int*)(0x42CE1100UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A33 *((volatile unsigned int*)(0x42CE1104UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A34 *((volatile unsigned int*)(0x42CE1108UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A35 *((volatile unsigned int*)(0x42CE110CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A36 *((volatile unsigned int*)(0x42CE1110UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A37 *((volatile unsigned int*)(0x42CE1114UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A38 *((volatile unsigned int*)(0x42CE1118UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A39 *((volatile unsigned int*)(0x42CE111CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A40 *((volatile unsigned int*)(0x42CE1120UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A41 *((volatile unsigned int*)(0x42CE1124UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A42 *((volatile unsigned int*)(0x42CE1128UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A43 *((volatile unsigned int*)(0x42CE112CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A44 *((volatile unsigned int*)(0x42CE1130UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A45 *((volatile unsigned int*)(0x42CE1134UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A46 *((volatile unsigned int*)(0x42CE1138UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A47 *((volatile unsigned int*)(0x42CE113CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC0 *((volatile unsigned int*)(0x42CE1160UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC1 *((volatile unsigned int*)(0x42CE1164UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC2 *((volatile unsigned int*)(0x42CE1168UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC3 *((volatile unsigned int*)(0x42CE116CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC4 *((volatile unsigned int*)(0x42CE1170UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC5 *((volatile unsigned int*)(0x42CE1174UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_SA *((volatile unsigned int*)(0x42CE1178UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_AE *((volatile unsigned int*)(0x42CE117CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A0 *((volatile unsigned int*)(0x42CE1180UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A1 *((volatile unsigned int*)(0x42CE1184UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A2 *((volatile unsigned int*)(0x42CE1188UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A3 *((volatile unsigned int*)(0x42CE118CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A4 *((volatile unsigned int*)(0x42CE1190UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A5 *((volatile unsigned int*)(0x42CE1194UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A6 *((volatile unsigned int*)(0x42CE1198UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A7 *((volatile unsigned int*)(0x42CE119CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A8 *((volatile unsigned int*)(0x42CE11A0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A9 *((volatile unsigned int*)(0x42CE11A4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A10 *((volatile unsigned int*)(0x42CE11A8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A11 *((volatile unsigned int*)(0x42CE11ACUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A12 *((volatile unsigned int*)(0x42CE11B0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A13 *((volatile unsigned int*)(0x42CE11B4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A14 *((volatile unsigned int*)(0x42CE11B8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A15 *((volatile unsigned int*)(0x42CE11BCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A16 *((volatile unsigned int*)(0x42CE11C0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A17 *((volatile unsigned int*)(0x42CE11C4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A18 *((volatile unsigned int*)(0x42CE11C8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A19 *((volatile unsigned int*)(0x42CE11CCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A20 *((volatile unsigned int*)(0x42CE11D0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A21 *((volatile unsigned int*)(0x42CE11D4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A22 *((volatile unsigned int*)(0x42CE11D8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A23 *((volatile unsigned int*)(0x42CE11DCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A24 *((volatile unsigned int*)(0x42CE11E0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A25 *((volatile unsigned int*)(0x42CE11E4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A26 *((volatile unsigned int*)(0x42CE11E8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A27 *((volatile unsigned int*)(0x42CE11ECUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A28 *((volatile unsigned int*)(0x42CE11F0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A29 *((volatile unsigned int*)(0x42CE11F4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A30 *((volatile unsigned int*)(0x42CE11F8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A31 *((volatile unsigned int*)(0x42CE11FCUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A32 *((volatile unsigned int*)(0x42CE1200UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A33 *((volatile unsigned int*)(0x42CE1204UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A34 *((volatile unsigned int*)(0x42CE1208UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A35 *((volatile unsigned int*)(0x42CE120CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A36 *((volatile unsigned int*)(0x42CE1210UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A37 *((volatile unsigned int*)(0x42CE1214UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A38 *((volatile unsigned int*)(0x42CE1218UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A39 *((volatile unsigned int*)(0x42CE121CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A40 *((volatile unsigned int*)(0x42CE1220UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A41 *((volatile unsigned int*)(0x42CE1224UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A42 *((volatile unsigned int*)(0x42CE1228UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A43 *((volatile unsigned int*)(0x42CE122CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A44 *((volatile unsigned int*)(0x42CE1230UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A45 *((volatile unsigned int*)(0x42CE1234UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A46 *((volatile unsigned int*)(0x42CE1238UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A47 *((volatile unsigned int*)(0x42CE123CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC0 *((volatile unsigned int*)(0x42CE1260UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC1 *((volatile unsigned int*)(0x42CE1264UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC2 *((volatile unsigned int*)(0x42CE1268UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC3 *((volatile unsigned int*)(0x42CE126CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC4 *((volatile unsigned int*)(0x42CE1270UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC5 *((volatile unsigned int*)(0x42CE1274UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_SA *((volatile unsigned int*)(0x42CE1278UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_AE *((volatile unsigned int*)(0x42CE127CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A0 *((volatile unsigned int*)(0x42CE1280UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A1 *((volatile unsigned int*)(0x42CE1284UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A2 *((volatile unsigned int*)(0x42CE1288UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A3 *((volatile unsigned int*)(0x42CE128CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A4 *((volatile unsigned int*)(0x42CE1290UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A5 *((volatile unsigned int*)(0x42CE1294UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A6 *((volatile unsigned int*)(0x42CE1298UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A7 *((volatile unsigned int*)(0x42CE129CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A8 *((volatile unsigned int*)(0x42CE12A0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A9 *((volatile unsigned int*)(0x42CE12A4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A10 *((volatile unsigned int*)(0x42CE12A8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A11 *((volatile unsigned int*)(0x42CE12ACUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A12 *((volatile unsigned int*)(0x42CE12B0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A13 *((volatile unsigned int*)(0x42CE12B4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A14 *((volatile unsigned int*)(0x42CE12B8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A15 *((volatile unsigned int*)(0x42CE12BCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A16 *((volatile unsigned int*)(0x42CE12C0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A17 *((volatile unsigned int*)(0x42CE12C4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A18 *((volatile unsigned int*)(0x42CE12C8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A19 *((volatile unsigned int*)(0x42CE12CCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A20 *((volatile unsigned int*)(0x42CE12D0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A21 *((volatile unsigned int*)(0x42CE12D4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A22 *((volatile unsigned int*)(0x42CE12D8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A23 *((volatile unsigned int*)(0x42CE12DCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A24 *((volatile unsigned int*)(0x42CE12E0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A25 *((volatile unsigned int*)(0x42CE12E4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A26 *((volatile unsigned int*)(0x42CE12E8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A27 *((volatile unsigned int*)(0x42CE12ECUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A28 *((volatile unsigned int*)(0x42CE12F0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A29 *((volatile unsigned int*)(0x42CE12F4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A30 *((volatile unsigned int*)(0x42CE12F8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A31 *((volatile unsigned int*)(0x42CE12FCUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A32 *((volatile unsigned int*)(0x42CE1300UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A33 *((volatile unsigned int*)(0x42CE1304UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A34 *((volatile unsigned int*)(0x42CE1308UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A35 *((volatile unsigned int*)(0x42CE130CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A36 *((volatile unsigned int*)(0x42CE1310UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A37 *((volatile unsigned int*)(0x42CE1314UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A38 *((volatile unsigned int*)(0x42CE1318UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A39 *((volatile unsigned int*)(0x42CE131CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A40 *((volatile unsigned int*)(0x42CE1320UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A41 *((volatile unsigned int*)(0x42CE1324UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A42 *((volatile unsigned int*)(0x42CE1328UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A43 *((volatile unsigned int*)(0x42CE132CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A44 *((volatile unsigned int*)(0x42CE1330UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A45 *((volatile unsigned int*)(0x42CE1334UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A46 *((volatile unsigned int*)(0x42CE1338UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A47 *((volatile unsigned int*)(0x42CE133CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC0 *((volatile unsigned int*)(0x42CE1360UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC1 *((volatile unsigned int*)(0x42CE1364UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC2 *((volatile unsigned int*)(0x42CE1368UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC3 *((volatile unsigned int*)(0x42CE136CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC4 *((volatile unsigned int*)(0x42CE1370UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC5 *((volatile unsigned int*)(0x42CE1374UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_SA *((volatile unsigned int*)(0x42CE1378UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_AE *((volatile unsigned int*)(0x42CE137CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A0 *((volatile unsigned int*)(0x42CE1380UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A1 *((volatile unsigned int*)(0x42CE1384UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A2 *((volatile unsigned int*)(0x42CE1388UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A3 *((volatile unsigned int*)(0x42CE138CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A4 *((volatile unsigned int*)(0x42CE1390UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A5 *((volatile unsigned int*)(0x42CE1394UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A6 *((volatile unsigned int*)(0x42CE1398UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A7 *((volatile unsigned int*)(0x42CE139CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A8 *((volatile unsigned int*)(0x42CE13A0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A9 *((volatile unsigned int*)(0x42CE13A4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A10 *((volatile unsigned int*)(0x42CE13A8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A11 *((volatile unsigned int*)(0x42CE13ACUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A12 *((volatile unsigned int*)(0x42CE13B0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A13 *((volatile unsigned int*)(0x42CE13B4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A14 *((volatile unsigned int*)(0x42CE13B8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A15 *((volatile unsigned int*)(0x42CE13BCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A16 *((volatile unsigned int*)(0x42CE13C0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A17 *((volatile unsigned int*)(0x42CE13C4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A18 *((volatile unsigned int*)(0x42CE13C8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A19 *((volatile unsigned int*)(0x42CE13CCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A20 *((volatile unsigned int*)(0x42CE13D0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A21 *((volatile unsigned int*)(0x42CE13D4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A22 *((volatile unsigned int*)(0x42CE13D8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A23 *((volatile unsigned int*)(0x42CE13DCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A24 *((volatile unsigned int*)(0x42CE13E0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A25 *((volatile unsigned int*)(0x42CE13E4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A26 *((volatile unsigned int*)(0x42CE13E8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A27 *((volatile unsigned int*)(0x42CE13ECUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A28 *((volatile unsigned int*)(0x42CE13F0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A29 *((volatile unsigned int*)(0x42CE13F4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A30 *((volatile unsigned int*)(0x42CE13F8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A31 *((volatile unsigned int*)(0x42CE13FCUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A32 *((volatile unsigned int*)(0x42CE1400UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A33 *((volatile unsigned int*)(0x42CE1404UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A34 *((volatile unsigned int*)(0x42CE1408UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A35 *((volatile unsigned int*)(0x42CE140CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A36 *((volatile unsigned int*)(0x42CE1410UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A37 *((volatile unsigned int*)(0x42CE1414UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A38 *((volatile unsigned int*)(0x42CE1418UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A39 *((volatile unsigned int*)(0x42CE141CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A40 *((volatile unsigned int*)(0x42CE1420UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A41 *((volatile unsigned int*)(0x42CE1424UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A42 *((volatile unsigned int*)(0x42CE1428UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A43 *((volatile unsigned int*)(0x42CE142CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A44 *((volatile unsigned int*)(0x42CE1430UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A45 *((volatile unsigned int*)(0x42CE1434UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A46 *((volatile unsigned int*)(0x42CE1438UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A47 *((volatile unsigned int*)(0x42CE143CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC0 *((volatile unsigned int*)(0x42CE1460UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC1 *((volatile unsigned int*)(0x42CE1464UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC2 *((volatile unsigned int*)(0x42CE1468UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC3 *((volatile unsigned int*)(0x42CE146CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC4 *((volatile unsigned int*)(0x42CE1470UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC5 *((volatile unsigned int*)(0x42CE1474UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_SA *((volatile unsigned int*)(0x42CE1478UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_AE *((volatile unsigned int*)(0x42CE147CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A0 *((volatile unsigned int*)(0x42CE1480UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A1 *((volatile unsigned int*)(0x42CE1484UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A2 *((volatile unsigned int*)(0x42CE1488UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A3 *((volatile unsigned int*)(0x42CE148CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A4 *((volatile unsigned int*)(0x42CE1490UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A5 *((volatile unsigned int*)(0x42CE1494UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A6 *((volatile unsigned int*)(0x42CE1498UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A7 *((volatile unsigned int*)(0x42CE149CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A8 *((volatile unsigned int*)(0x42CE14A0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A9 *((volatile unsigned int*)(0x42CE14A4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A10 *((volatile unsigned int*)(0x42CE14A8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A11 *((volatile unsigned int*)(0x42CE14ACUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A12 *((volatile unsigned int*)(0x42CE14B0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A13 *((volatile unsigned int*)(0x42CE14B4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A14 *((volatile unsigned int*)(0x42CE14B8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A15 *((volatile unsigned int*)(0x42CE14BCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A16 *((volatile unsigned int*)(0x42CE14C0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A17 *((volatile unsigned int*)(0x42CE14C4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A18 *((volatile unsigned int*)(0x42CE14C8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A19 *((volatile unsigned int*)(0x42CE14CCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A20 *((volatile unsigned int*)(0x42CE14D0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A21 *((volatile unsigned int*)(0x42CE14D4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A22 *((volatile unsigned int*)(0x42CE14D8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A23 *((volatile unsigned int*)(0x42CE14DCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A24 *((volatile unsigned int*)(0x42CE14E0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A25 *((volatile unsigned int*)(0x42CE14E4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A26 *((volatile unsigned int*)(0x42CE14E8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A27 *((volatile unsigned int*)(0x42CE14ECUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A28 *((volatile unsigned int*)(0x42CE14F0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A29 *((volatile unsigned int*)(0x42CE14F4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A30 *((volatile unsigned int*)(0x42CE14F8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A31 *((volatile unsigned int*)(0x42CE14FCUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A32 *((volatile unsigned int*)(0x42CE1500UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A33 *((volatile unsigned int*)(0x42CE1504UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A34 *((volatile unsigned int*)(0x42CE1508UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A35 *((volatile unsigned int*)(0x42CE150CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A36 *((volatile unsigned int*)(0x42CE1510UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A37 *((volatile unsigned int*)(0x42CE1514UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A38 *((volatile unsigned int*)(0x42CE1518UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A39 *((volatile unsigned int*)(0x42CE151CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A40 *((volatile unsigned int*)(0x42CE1520UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A41 *((volatile unsigned int*)(0x42CE1524UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A42 *((volatile unsigned int*)(0x42CE1528UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A43 *((volatile unsigned int*)(0x42CE152CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A44 *((volatile unsigned int*)(0x42CE1530UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A45 *((volatile unsigned int*)(0x42CE1534UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A46 *((volatile unsigned int*)(0x42CE1538UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A47 *((volatile unsigned int*)(0x42CE153CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC0 *((volatile unsigned int*)(0x42CE1560UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC1 *((volatile unsigned int*)(0x42CE1564UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC2 *((volatile unsigned int*)(0x42CE1568UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC3 *((volatile unsigned int*)(0x42CE156CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC4 *((volatile unsigned int*)(0x42CE1570UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC5 *((volatile unsigned int*)(0x42CE1574UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_SA *((volatile unsigned int*)(0x42CE1578UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_AE *((volatile unsigned int*)(0x42CE157CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A0 *((volatile unsigned int*)(0x42CE1580UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A1 *((volatile unsigned int*)(0x42CE1584UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A2 *((volatile unsigned int*)(0x42CE1588UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A3 *((volatile unsigned int*)(0x42CE158CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A4 *((volatile unsigned int*)(0x42CE1590UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A5 *((volatile unsigned int*)(0x42CE1594UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A6 *((volatile unsigned int*)(0x42CE1598UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A7 *((volatile unsigned int*)(0x42CE159CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A8 *((volatile unsigned int*)(0x42CE15A0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A9 *((volatile unsigned int*)(0x42CE15A4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A10 *((volatile unsigned int*)(0x42CE15A8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A11 *((volatile unsigned int*)(0x42CE15ACUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A12 *((volatile unsigned int*)(0x42CE15B0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A13 *((volatile unsigned int*)(0x42CE15B4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A14 *((volatile unsigned int*)(0x42CE15B8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A15 *((volatile unsigned int*)(0x42CE15BCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A16 *((volatile unsigned int*)(0x42CE15C0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A17 *((volatile unsigned int*)(0x42CE15C4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A18 *((volatile unsigned int*)(0x42CE15C8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A19 *((volatile unsigned int*)(0x42CE15CCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A20 *((volatile unsigned int*)(0x42CE15D0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A21 *((volatile unsigned int*)(0x42CE15D4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A22 *((volatile unsigned int*)(0x42CE15D8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A23 *((volatile unsigned int*)(0x42CE15DCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A24 *((volatile unsigned int*)(0x42CE15E0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A25 *((volatile unsigned int*)(0x42CE15E4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A26 *((volatile unsigned int*)(0x42CE15E8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A27 *((volatile unsigned int*)(0x42CE15ECUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A28 *((volatile unsigned int*)(0x42CE15F0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A29 *((volatile unsigned int*)(0x42CE15F4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A30 *((volatile unsigned int*)(0x42CE15F8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A31 *((volatile unsigned int*)(0x42CE15FCUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A32 *((volatile unsigned int*)(0x42CE1600UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A33 *((volatile unsigned int*)(0x42CE1604UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A34 *((volatile unsigned int*)(0x42CE1608UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A35 *((volatile unsigned int*)(0x42CE160CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A36 *((volatile unsigned int*)(0x42CE1610UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A37 *((volatile unsigned int*)(0x42CE1614UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A38 *((volatile unsigned int*)(0x42CE1618UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A39 *((volatile unsigned int*)(0x42CE161CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A40 *((volatile unsigned int*)(0x42CE1620UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A41 *((volatile unsigned int*)(0x42CE1624UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A42 *((volatile unsigned int*)(0x42CE1628UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A43 *((volatile unsigned int*)(0x42CE162CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A44 *((volatile unsigned int*)(0x42CE1630UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A45 *((volatile unsigned int*)(0x42CE1634UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A46 *((volatile unsigned int*)(0x42CE1638UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A47 *((volatile unsigned int*)(0x42CE163CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC0 *((volatile unsigned int*)(0x42CE1660UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC1 *((volatile unsigned int*)(0x42CE1664UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC2 *((volatile unsigned int*)(0x42CE1668UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC3 *((volatile unsigned int*)(0x42CE166CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC4 *((volatile unsigned int*)(0x42CE1670UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC5 *((volatile unsigned int*)(0x42CE1674UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_SA *((volatile unsigned int*)(0x42CE1678UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_AE *((volatile unsigned int*)(0x42CE167CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A0 *((volatile unsigned int*)(0x42CE1680UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A1 *((volatile unsigned int*)(0x42CE1684UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A2 *((volatile unsigned int*)(0x42CE1688UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A3 *((volatile unsigned int*)(0x42CE168CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A4 *((volatile unsigned int*)(0x42CE1690UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A5 *((volatile unsigned int*)(0x42CE1694UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A6 *((volatile unsigned int*)(0x42CE1698UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A7 *((volatile unsigned int*)(0x42CE169CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A8 *((volatile unsigned int*)(0x42CE16A0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A9 *((volatile unsigned int*)(0x42CE16A4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A10 *((volatile unsigned int*)(0x42CE16A8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A11 *((volatile unsigned int*)(0x42CE16ACUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A12 *((volatile unsigned int*)(0x42CE16B0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A13 *((volatile unsigned int*)(0x42CE16B4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A14 *((volatile unsigned int*)(0x42CE16B8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A15 *((volatile unsigned int*)(0x42CE16BCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A16 *((volatile unsigned int*)(0x42CE16C0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A17 *((volatile unsigned int*)(0x42CE16C4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A18 *((volatile unsigned int*)(0x42CE16C8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A19 *((volatile unsigned int*)(0x42CE16CCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A20 *((volatile unsigned int*)(0x42CE16D0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A21 *((volatile unsigned int*)(0x42CE16D4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A22 *((volatile unsigned int*)(0x42CE16D8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A23 *((volatile unsigned int*)(0x42CE16DCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A24 *((volatile unsigned int*)(0x42CE16E0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A25 *((volatile unsigned int*)(0x42CE16E4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A26 *((volatile unsigned int*)(0x42CE16E8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A27 *((volatile unsigned int*)(0x42CE16ECUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A28 *((volatile unsigned int*)(0x42CE16F0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A29 *((volatile unsigned int*)(0x42CE16F4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A30 *((volatile unsigned int*)(0x42CE16F8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A31 *((volatile unsigned int*)(0x42CE16FCUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A32 *((volatile unsigned int*)(0x42CE1700UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A33 *((volatile unsigned int*)(0x42CE1704UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A34 *((volatile unsigned int*)(0x42CE1708UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A35 *((volatile unsigned int*)(0x42CE170CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A36 *((volatile unsigned int*)(0x42CE1710UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A37 *((volatile unsigned int*)(0x42CE1714UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A38 *((volatile unsigned int*)(0x42CE1718UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A39 *((volatile unsigned int*)(0x42CE171CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A40 *((volatile unsigned int*)(0x42CE1720UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A41 *((volatile unsigned int*)(0x42CE1724UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A42 *((volatile unsigned int*)(0x42CE1728UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A43 *((volatile unsigned int*)(0x42CE172CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A44 *((volatile unsigned int*)(0x42CE1730UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A45 *((volatile unsigned int*)(0x42CE1734UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A46 *((volatile unsigned int*)(0x42CE1738UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A47 *((volatile unsigned int*)(0x42CE173CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC0 *((volatile unsigned int*)(0x42CE1760UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC1 *((volatile unsigned int*)(0x42CE1764UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC2 *((volatile unsigned int*)(0x42CE1768UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC3 *((volatile unsigned int*)(0x42CE176CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC4 *((volatile unsigned int*)(0x42CE1770UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC5 *((volatile unsigned int*)(0x42CE1774UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_SA *((volatile unsigned int*)(0x42CE1778UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_AE *((volatile unsigned int*)(0x42CE177CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A0 *((volatile unsigned int*)(0x42CE1780UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A1 *((volatile unsigned int*)(0x42CE1784UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A2 *((volatile unsigned int*)(0x42CE1788UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A3 *((volatile unsigned int*)(0x42CE178CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A4 *((volatile unsigned int*)(0x42CE1790UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A5 *((volatile unsigned int*)(0x42CE1794UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A6 *((volatile unsigned int*)(0x42CE1798UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A7 *((volatile unsigned int*)(0x42CE179CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A8 *((volatile unsigned int*)(0x42CE17A0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A9 *((volatile unsigned int*)(0x42CE17A4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A10 *((volatile unsigned int*)(0x42CE17A8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A11 *((volatile unsigned int*)(0x42CE17ACUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A12 *((volatile unsigned int*)(0x42CE17B0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A13 *((volatile unsigned int*)(0x42CE17B4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A14 *((volatile unsigned int*)(0x42CE17B8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A15 *((volatile unsigned int*)(0x42CE17BCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A16 *((volatile unsigned int*)(0x42CE17C0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A17 *((volatile unsigned int*)(0x42CE17C4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A18 *((volatile unsigned int*)(0x42CE17C8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A19 *((volatile unsigned int*)(0x42CE17CCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A20 *((volatile unsigned int*)(0x42CE17D0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A21 *((volatile unsigned int*)(0x42CE17D4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A22 *((volatile unsigned int*)(0x42CE17D8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A23 *((volatile unsigned int*)(0x42CE17DCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A24 *((volatile unsigned int*)(0x42CE17E0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A25 *((volatile unsigned int*)(0x42CE17E4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A26 *((volatile unsigned int*)(0x42CE17E8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A27 *((volatile unsigned int*)(0x42CE17ECUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A28 *((volatile unsigned int*)(0x42CE17F0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A29 *((volatile unsigned int*)(0x42CE17F4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A30 *((volatile unsigned int*)(0x42CE17F8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A31 *((volatile unsigned int*)(0x42CE17FCUL)) +#define bFM3_ETHERNET_MAC1_RGSR_LM *((volatile unsigned int*)(0x42CE1B00UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LSP0 *((volatile unsigned int*)(0x42CE1B04UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LSP1 *((volatile unsigned int*)(0x42CE1B08UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LS *((volatile unsigned int*)(0x42CE1B0CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSE *((volatile unsigned int*)(0x42CEE000UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TFCU *((volatile unsigned int*)(0x42CEE004UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSI *((volatile unsigned int*)(0x42CEE008UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSU *((volatile unsigned int*)(0x42CEE00CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TITE *((volatile unsigned int*)(0x42CEE010UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TARU *((volatile unsigned int*)(0x42CEE014UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSEA *((volatile unsigned int*)(0x42CEE020UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSDB *((volatile unsigned int*)(0x42CEE024UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSV2E *((volatile unsigned int*)(0x42CEE028UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TETSP *((volatile unsigned int*)(0x42CEE02CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E *((volatile unsigned int*)(0x42CEE030UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E *((volatile unsigned int*)(0x42CEE034UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TETSEM *((volatile unsigned int*)(0x42CEE038UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSMRM *((volatile unsigned int*)(0x42CEE03CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSPS0 *((volatile unsigned int*)(0x42CEE040UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSPS1 *((volatile unsigned int*)(0x42CEE044UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSENMF *((volatile unsigned int*)(0x42CEE048UL)) +#define bFM3_ETHERNET_MAC1_TSCR_ATSFC *((volatile unsigned int*)(0x42CEE060UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC0 *((volatile unsigned int*)(0x42CEE080UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC1 *((volatile unsigned int*)(0x42CEE084UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC2 *((volatile unsigned int*)(0x42CEE088UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC3 *((volatile unsigned int*)(0x42CEE08CUL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC4 *((volatile unsigned int*)(0x42CEE090UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC5 *((volatile unsigned int*)(0x42CEE094UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC6 *((volatile unsigned int*)(0x42CEE098UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC7 *((volatile unsigned int*)(0x42CEE09CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS0 *((volatile unsigned int*)(0x42CEE100UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS1 *((volatile unsigned int*)(0x42CEE104UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS2 *((volatile unsigned int*)(0x42CEE108UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS3 *((volatile unsigned int*)(0x42CEE10CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS4 *((volatile unsigned int*)(0x42CEE110UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS5 *((volatile unsigned int*)(0x42CEE114UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS6 *((volatile unsigned int*)(0x42CEE118UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS7 *((volatile unsigned int*)(0x42CEE11CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS8 *((volatile unsigned int*)(0x42CEE120UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS9 *((volatile unsigned int*)(0x42CEE124UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS10 *((volatile unsigned int*)(0x42CEE128UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS11 *((volatile unsigned int*)(0x42CEE12CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS12 *((volatile unsigned int*)(0x42CEE130UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS13 *((volatile unsigned int*)(0x42CEE134UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS14 *((volatile unsigned int*)(0x42CEE138UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS15 *((volatile unsigned int*)(0x42CEE13CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS16 *((volatile unsigned int*)(0x42CEE140UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS17 *((volatile unsigned int*)(0x42CEE144UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS18 *((volatile unsigned int*)(0x42CEE148UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS19 *((volatile unsigned int*)(0x42CEE14CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS20 *((volatile unsigned int*)(0x42CEE150UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS21 *((volatile unsigned int*)(0x42CEE154UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS22 *((volatile unsigned int*)(0x42CEE158UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS23 *((volatile unsigned int*)(0x42CEE15CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS24 *((volatile unsigned int*)(0x42CEE160UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS25 *((volatile unsigned int*)(0x42CEE164UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS26 *((volatile unsigned int*)(0x42CEE168UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS27 *((volatile unsigned int*)(0x42CEE16CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS28 *((volatile unsigned int*)(0x42CEE170UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS29 *((volatile unsigned int*)(0x42CEE174UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS30 *((volatile unsigned int*)(0x42CEE178UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS31 *((volatile unsigned int*)(0x42CEE17CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS0 *((volatile unsigned int*)(0x42CEE080UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS1 *((volatile unsigned int*)(0x42CEE084UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS2 *((volatile unsigned int*)(0x42CEE088UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS3 *((volatile unsigned int*)(0x42CEE08CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS4 *((volatile unsigned int*)(0x42CEE090UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS5 *((volatile unsigned int*)(0x42CEE094UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS6 *((volatile unsigned int*)(0x42CEE098UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS7 *((volatile unsigned int*)(0x42CEE09CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS8 *((volatile unsigned int*)(0x42CEE0A0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS9 *((volatile unsigned int*)(0x42CEE0A4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS10 *((volatile unsigned int*)(0x42CEE0A8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS11 *((volatile unsigned int*)(0x42CEE0ACUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS12 *((volatile unsigned int*)(0x42CEE0B0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS13 *((volatile unsigned int*)(0x42CEE0B4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS14 *((volatile unsigned int*)(0x42CEE0B8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS15 *((volatile unsigned int*)(0x42CEE0BCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS16 *((volatile unsigned int*)(0x42CEE0C0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS17 *((volatile unsigned int*)(0x42CEE0C4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS18 *((volatile unsigned int*)(0x42CEE0C8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS19 *((volatile unsigned int*)(0x42CEE0CCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS20 *((volatile unsigned int*)(0x42CEE0D0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS21 *((volatile unsigned int*)(0x42CEE0D4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS22 *((volatile unsigned int*)(0x42CEE0D8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS23 *((volatile unsigned int*)(0x42CEE0DCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS24 *((volatile unsigned int*)(0x42CEE0E0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS25 *((volatile unsigned int*)(0x42CEE0E4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS26 *((volatile unsigned int*)(0x42CEE0E8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS27 *((volatile unsigned int*)(0x42CEE0ECUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS28 *((volatile unsigned int*)(0x42CEE0F0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS29 *((volatile unsigned int*)(0x42CEE0F4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS30 *((volatile unsigned int*)(0x42CEE0F8UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS0 *((volatile unsigned int*)(0x42CEE200UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS1 *((volatile unsigned int*)(0x42CEE204UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS2 *((volatile unsigned int*)(0x42CEE208UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS3 *((volatile unsigned int*)(0x42CEE20CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS4 *((volatile unsigned int*)(0x42CEE210UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS5 *((volatile unsigned int*)(0x42CEE214UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS6 *((volatile unsigned int*)(0x42CEE218UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS7 *((volatile unsigned int*)(0x42CEE21CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS8 *((volatile unsigned int*)(0x42CEE220UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS9 *((volatile unsigned int*)(0x42CEE224UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS10 *((volatile unsigned int*)(0x42CEE228UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS11 *((volatile unsigned int*)(0x42CEE22CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS12 *((volatile unsigned int*)(0x42CEE230UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS13 *((volatile unsigned int*)(0x42CEE234UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS14 *((volatile unsigned int*)(0x42CEE238UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS15 *((volatile unsigned int*)(0x42CEE23CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS16 *((volatile unsigned int*)(0x42CEE240UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS17 *((volatile unsigned int*)(0x42CEE244UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS18 *((volatile unsigned int*)(0x42CEE248UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS19 *((volatile unsigned int*)(0x42CEE24CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS20 *((volatile unsigned int*)(0x42CEE250UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS21 *((volatile unsigned int*)(0x42CEE254UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS22 *((volatile unsigned int*)(0x42CEE258UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS23 *((volatile unsigned int*)(0x42CEE25CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS24 *((volatile unsigned int*)(0x42CEE260UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS25 *((volatile unsigned int*)(0x42CEE264UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS26 *((volatile unsigned int*)(0x42CEE268UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS27 *((volatile unsigned int*)(0x42CEE26CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS28 *((volatile unsigned int*)(0x42CEE270UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS29 *((volatile unsigned int*)(0x42CEE274UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS30 *((volatile unsigned int*)(0x42CEE278UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS31 *((volatile unsigned int*)(0x42CEE27CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS0 *((volatile unsigned int*)(0x42CEE280UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS1 *((volatile unsigned int*)(0x42CEE284UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS2 *((volatile unsigned int*)(0x42CEE288UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS3 *((volatile unsigned int*)(0x42CEE28CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS4 *((volatile unsigned int*)(0x42CEE290UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS5 *((volatile unsigned int*)(0x42CEE294UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS6 *((volatile unsigned int*)(0x42CEE298UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS7 *((volatile unsigned int*)(0x42CEE29CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS8 *((volatile unsigned int*)(0x42CEE2A0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS9 *((volatile unsigned int*)(0x42CEE2A4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS10 *((volatile unsigned int*)(0x42CEE2A8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS11 *((volatile unsigned int*)(0x42CEE2ACUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS12 *((volatile unsigned int*)(0x42CEE2B0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS13 *((volatile unsigned int*)(0x42CEE2B4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS14 *((volatile unsigned int*)(0x42CEE2B8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS15 *((volatile unsigned int*)(0x42CEE2BCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS16 *((volatile unsigned int*)(0x42CEE2C0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS17 *((volatile unsigned int*)(0x42CEE2C4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS18 *((volatile unsigned int*)(0x42CEE2C8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS19 *((volatile unsigned int*)(0x42CEE2CCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS20 *((volatile unsigned int*)(0x42CEE2D0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS21 *((volatile unsigned int*)(0x42CEE2D4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS22 *((volatile unsigned int*)(0x42CEE2D8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS23 *((volatile unsigned int*)(0x42CEE2DCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS24 *((volatile unsigned int*)(0x42CEE2E0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS25 *((volatile unsigned int*)(0x42CEE2E4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS26 *((volatile unsigned int*)(0x42CEE2E8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS27 *((volatile unsigned int*)(0x42CEE2ECUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS28 *((volatile unsigned int*)(0x42CEE2F0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS29 *((volatile unsigned int*)(0x42CEE2F4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS30 *((volatile unsigned int*)(0x42CEE2F8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB *((volatile unsigned int*)(0x42CEE2FCUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR0 *((volatile unsigned int*)(0x42CEE300UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR1 *((volatile unsigned int*)(0x42CEE304UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR2 *((volatile unsigned int*)(0x42CEE308UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR3 *((volatile unsigned int*)(0x42CEE30CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR4 *((volatile unsigned int*)(0x42CEE310UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR5 *((volatile unsigned int*)(0x42CEE314UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR6 *((volatile unsigned int*)(0x42CEE318UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR7 *((volatile unsigned int*)(0x42CEE31CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR8 *((volatile unsigned int*)(0x42CEE320UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR9 *((volatile unsigned int*)(0x42CEE324UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR10 *((volatile unsigned int*)(0x42CEE328UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR11 *((volatile unsigned int*)(0x42CEE32CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR12 *((volatile unsigned int*)(0x42CEE330UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR13 *((volatile unsigned int*)(0x42CEE334UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR14 *((volatile unsigned int*)(0x42CEE338UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR15 *((volatile unsigned int*)(0x42CEE33CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR16 *((volatile unsigned int*)(0x42CEE340UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR17 *((volatile unsigned int*)(0x42CEE344UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR18 *((volatile unsigned int*)(0x42CEE348UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR19 *((volatile unsigned int*)(0x42CEE34CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR20 *((volatile unsigned int*)(0x42CEE350UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR21 *((volatile unsigned int*)(0x42CEE354UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR22 *((volatile unsigned int*)(0x42CEE358UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR23 *((volatile unsigned int*)(0x42CEE35CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR24 *((volatile unsigned int*)(0x42CEE360UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR25 *((volatile unsigned int*)(0x42CEE364UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR26 *((volatile unsigned int*)(0x42CEE368UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR27 *((volatile unsigned int*)(0x42CEE36CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR28 *((volatile unsigned int*)(0x42CEE370UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR29 *((volatile unsigned int*)(0x42CEE374UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR30 *((volatile unsigned int*)(0x42CEE378UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR31 *((volatile unsigned int*)(0x42CEE37CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR0 *((volatile unsigned int*)(0x42CEE380UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR1 *((volatile unsigned int*)(0x42CEE384UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR2 *((volatile unsigned int*)(0x42CEE388UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR3 *((volatile unsigned int*)(0x42CEE38CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR4 *((volatile unsigned int*)(0x42CEE390UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR5 *((volatile unsigned int*)(0x42CEE394UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR6 *((volatile unsigned int*)(0x42CEE398UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR7 *((volatile unsigned int*)(0x42CEE39CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR8 *((volatile unsigned int*)(0x42CEE3A0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR9 *((volatile unsigned int*)(0x42CEE3A4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR10 *((volatile unsigned int*)(0x42CEE3A8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR11 *((volatile unsigned int*)(0x42CEE3ACUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR12 *((volatile unsigned int*)(0x42CEE3B0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR13 *((volatile unsigned int*)(0x42CEE3B4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR14 *((volatile unsigned int*)(0x42CEE3B8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR15 *((volatile unsigned int*)(0x42CEE3BCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR16 *((volatile unsigned int*)(0x42CEE3C0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR17 *((volatile unsigned int*)(0x42CEE3C4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR18 *((volatile unsigned int*)(0x42CEE3C8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR19 *((volatile unsigned int*)(0x42CEE3CCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR20 *((volatile unsigned int*)(0x42CEE3D0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR21 *((volatile unsigned int*)(0x42CEE3D4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR22 *((volatile unsigned int*)(0x42CEE3D8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR23 *((volatile unsigned int*)(0x42CEE3DCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR24 *((volatile unsigned int*)(0x42CEE3E0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR25 *((volatile unsigned int*)(0x42CEE3E4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR26 *((volatile unsigned int*)(0x42CEE3E8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR27 *((volatile unsigned int*)(0x42CEE3ECUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR28 *((volatile unsigned int*)(0x42CEE3F0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR29 *((volatile unsigned int*)(0x42CEE3F4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR30 *((volatile unsigned int*)(0x42CEE3F8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR31 *((volatile unsigned int*)(0x42CEE3FCUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR0 *((volatile unsigned int*)(0x42CEE400UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR1 *((volatile unsigned int*)(0x42CEE404UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR2 *((volatile unsigned int*)(0x42CEE408UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR3 *((volatile unsigned int*)(0x42CEE40CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR4 *((volatile unsigned int*)(0x42CEE410UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR5 *((volatile unsigned int*)(0x42CEE414UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR6 *((volatile unsigned int*)(0x42CEE418UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR7 *((volatile unsigned int*)(0x42CEE41CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR8 *((volatile unsigned int*)(0x42CEE420UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR9 *((volatile unsigned int*)(0x42CEE424UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR10 *((volatile unsigned int*)(0x42CEE428UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR11 *((volatile unsigned int*)(0x42CEE42CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR12 *((volatile unsigned int*)(0x42CEE430UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR13 *((volatile unsigned int*)(0x42CEE434UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR14 *((volatile unsigned int*)(0x42CEE438UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR15 *((volatile unsigned int*)(0x42CEE43CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR16 *((volatile unsigned int*)(0x42CEE440UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR17 *((volatile unsigned int*)(0x42CEE444UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR18 *((volatile unsigned int*)(0x42CEE448UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR19 *((volatile unsigned int*)(0x42CEE44CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR20 *((volatile unsigned int*)(0x42CEE450UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR21 *((volatile unsigned int*)(0x42CEE454UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR22 *((volatile unsigned int*)(0x42CEE458UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR23 *((volatile unsigned int*)(0x42CEE45CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR24 *((volatile unsigned int*)(0x42CEE460UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR25 *((volatile unsigned int*)(0x42CEE464UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR26 *((volatile unsigned int*)(0x42CEE468UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR27 *((volatile unsigned int*)(0x42CEE46CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR28 *((volatile unsigned int*)(0x42CEE470UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR29 *((volatile unsigned int*)(0x42CEE474UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR30 *((volatile unsigned int*)(0x42CEE478UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42CEE480UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42CEE484UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42CEE488UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42CEE48CUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42CEE490UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42CEE494UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42CEE498UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42CEE49CUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42CEE4A0UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42CEE4A4UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42CEE4A8UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42CEE4ACUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42CEE4B0UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42CEE4B4UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42CEE4B8UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42CEE4BCUL)) +#define bFM3_ETHERNET_MAC1_TSR_TSSOVF *((volatile unsigned int*)(0x42CEE500UL)) +#define bFM3_ETHERNET_MAC1_TSR_TSTART *((volatile unsigned int*)(0x42CEE504UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSTS *((volatile unsigned int*)(0x42CEE508UL)) +#define bFM3_ETHERNET_MAC1_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSSTM *((volatile unsigned int*)(0x42CEE560UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS0 *((volatile unsigned int*)(0x42CEE564UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS1 *((volatile unsigned int*)(0x42CEE568UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS2 *((volatile unsigned int*)(0x42CEE56CUL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42CEE580UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42CEE584UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42CEE588UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42CEE58CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN0 *((volatile unsigned int*)(0x42CEE600UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN1 *((volatile unsigned int*)(0x42CEE604UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN2 *((volatile unsigned int*)(0x42CEE608UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN3 *((volatile unsigned int*)(0x42CEE60CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN4 *((volatile unsigned int*)(0x42CEE610UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN5 *((volatile unsigned int*)(0x42CEE614UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN6 *((volatile unsigned int*)(0x42CEE618UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN7 *((volatile unsigned int*)(0x42CEE61CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN8 *((volatile unsigned int*)(0x42CEE620UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN9 *((volatile unsigned int*)(0x42CEE624UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN10 *((volatile unsigned int*)(0x42CEE628UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN11 *((volatile unsigned int*)(0x42CEE62CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN12 *((volatile unsigned int*)(0x42CEE630UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN13 *((volatile unsigned int*)(0x42CEE634UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN14 *((volatile unsigned int*)(0x42CEE638UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN15 *((volatile unsigned int*)(0x42CEE63CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN16 *((volatile unsigned int*)(0x42CEE640UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN17 *((volatile unsigned int*)(0x42CEE644UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN18 *((volatile unsigned int*)(0x42CEE648UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN19 *((volatile unsigned int*)(0x42CEE64CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN20 *((volatile unsigned int*)(0x42CEE650UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN21 *((volatile unsigned int*)(0x42CEE654UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN22 *((volatile unsigned int*)(0x42CEE658UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN23 *((volatile unsigned int*)(0x42CEE65CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN24 *((volatile unsigned int*)(0x42CEE660UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN25 *((volatile unsigned int*)(0x42CEE664UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN26 *((volatile unsigned int*)(0x42CEE668UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN27 *((volatile unsigned int*)(0x42CEE66CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN28 *((volatile unsigned int*)(0x42CEE670UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN29 *((volatile unsigned int*)(0x42CEE674UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN30 *((volatile unsigned int*)(0x42CEE678UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS0 *((volatile unsigned int*)(0x42CEE680UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS1 *((volatile unsigned int*)(0x42CEE684UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS2 *((volatile unsigned int*)(0x42CEE688UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS3 *((volatile unsigned int*)(0x42CEE68CUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS4 *((volatile unsigned int*)(0x42CEE690UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS5 *((volatile unsigned int*)(0x42CEE694UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS6 *((volatile unsigned int*)(0x42CEE698UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS7 *((volatile unsigned int*)(0x42CEE69CUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS8 *((volatile unsigned int*)(0x42CEE6A0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS9 *((volatile unsigned int*)(0x42CEE6A4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS10 *((volatile unsigned int*)(0x42CEE6A8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS11 *((volatile unsigned int*)(0x42CEE6ACUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS12 *((volatile unsigned int*)(0x42CEE6B0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS13 *((volatile unsigned int*)(0x42CEE6B4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS14 *((volatile unsigned int*)(0x42CEE6B8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS15 *((volatile unsigned int*)(0x42CEE6BCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS16 *((volatile unsigned int*)(0x42CEE6C0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS17 *((volatile unsigned int*)(0x42CEE6C4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS18 *((volatile unsigned int*)(0x42CEE6C8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS19 *((volatile unsigned int*)(0x42CEE6CCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS20 *((volatile unsigned int*)(0x42CEE6D0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS21 *((volatile unsigned int*)(0x42CEE6D4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS22 *((volatile unsigned int*)(0x42CEE6D8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS23 *((volatile unsigned int*)(0x42CEE6DCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS24 *((volatile unsigned int*)(0x42CEE6E0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS25 *((volatile unsigned int*)(0x42CEE6E4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS26 *((volatile unsigned int*)(0x42CEE6E8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS27 *((volatile unsigned int*)(0x42CEE6ECUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS28 *((volatile unsigned int*)(0x42CEE6F0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS29 *((volatile unsigned int*)(0x42CEE6F4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS30 *((volatile unsigned int*)(0x42CEE6F8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS31 *((volatile unsigned int*)(0x42CEE6FCUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A32 *((volatile unsigned int*)(0x42CF0000UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A33 *((volatile unsigned int*)(0x42CF0004UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A34 *((volatile unsigned int*)(0x42CF0008UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A35 *((volatile unsigned int*)(0x42CF000CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A36 *((volatile unsigned int*)(0x42CF0010UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A37 *((volatile unsigned int*)(0x42CF0014UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A38 *((volatile unsigned int*)(0x42CF0018UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A39 *((volatile unsigned int*)(0x42CF001CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A40 *((volatile unsigned int*)(0x42CF0020UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A41 *((volatile unsigned int*)(0x42CF0024UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A42 *((volatile unsigned int*)(0x42CF0028UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A43 *((volatile unsigned int*)(0x42CF002CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A44 *((volatile unsigned int*)(0x42CF0030UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A45 *((volatile unsigned int*)(0x42CF0034UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A46 *((volatile unsigned int*)(0x42CF0038UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A47 *((volatile unsigned int*)(0x42CF003CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC0 *((volatile unsigned int*)(0x42CF0060UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC1 *((volatile unsigned int*)(0x42CF0064UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC2 *((volatile unsigned int*)(0x42CF0068UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC3 *((volatile unsigned int*)(0x42CF006CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC4 *((volatile unsigned int*)(0x42CF0070UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC5 *((volatile unsigned int*)(0x42CF0074UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_SA *((volatile unsigned int*)(0x42CF0078UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_AE *((volatile unsigned int*)(0x42CF007CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A0 *((volatile unsigned int*)(0x42CF0080UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A1 *((volatile unsigned int*)(0x42CF0084UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A2 *((volatile unsigned int*)(0x42CF0088UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A3 *((volatile unsigned int*)(0x42CF008CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A4 *((volatile unsigned int*)(0x42CF0090UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A5 *((volatile unsigned int*)(0x42CF0094UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A6 *((volatile unsigned int*)(0x42CF0098UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A7 *((volatile unsigned int*)(0x42CF009CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A8 *((volatile unsigned int*)(0x42CF00A0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A9 *((volatile unsigned int*)(0x42CF00A4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A10 *((volatile unsigned int*)(0x42CF00A8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A11 *((volatile unsigned int*)(0x42CF00ACUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A12 *((volatile unsigned int*)(0x42CF00B0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A13 *((volatile unsigned int*)(0x42CF00B4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A14 *((volatile unsigned int*)(0x42CF00B8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A15 *((volatile unsigned int*)(0x42CF00BCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A16 *((volatile unsigned int*)(0x42CF00C0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A17 *((volatile unsigned int*)(0x42CF00C4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A18 *((volatile unsigned int*)(0x42CF00C8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A19 *((volatile unsigned int*)(0x42CF00CCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A20 *((volatile unsigned int*)(0x42CF00D0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A21 *((volatile unsigned int*)(0x42CF00D4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A22 *((volatile unsigned int*)(0x42CF00D8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A23 *((volatile unsigned int*)(0x42CF00DCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A24 *((volatile unsigned int*)(0x42CF00E0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A25 *((volatile unsigned int*)(0x42CF00E4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A26 *((volatile unsigned int*)(0x42CF00E8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A27 *((volatile unsigned int*)(0x42CF00ECUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A28 *((volatile unsigned int*)(0x42CF00F0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A29 *((volatile unsigned int*)(0x42CF00F4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A30 *((volatile unsigned int*)(0x42CF00F8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A31 *((volatile unsigned int*)(0x42CF00FCUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A32 *((volatile unsigned int*)(0x42CF0100UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A33 *((volatile unsigned int*)(0x42CF0104UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A34 *((volatile unsigned int*)(0x42CF0108UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A35 *((volatile unsigned int*)(0x42CF010CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A36 *((volatile unsigned int*)(0x42CF0110UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A37 *((volatile unsigned int*)(0x42CF0114UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A38 *((volatile unsigned int*)(0x42CF0118UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A39 *((volatile unsigned int*)(0x42CF011CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A40 *((volatile unsigned int*)(0x42CF0120UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A41 *((volatile unsigned int*)(0x42CF0124UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A42 *((volatile unsigned int*)(0x42CF0128UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A43 *((volatile unsigned int*)(0x42CF012CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A44 *((volatile unsigned int*)(0x42CF0130UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A45 *((volatile unsigned int*)(0x42CF0134UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A46 *((volatile unsigned int*)(0x42CF0138UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A47 *((volatile unsigned int*)(0x42CF013CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC0 *((volatile unsigned int*)(0x42CF0160UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC1 *((volatile unsigned int*)(0x42CF0164UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC2 *((volatile unsigned int*)(0x42CF0168UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC3 *((volatile unsigned int*)(0x42CF016CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC4 *((volatile unsigned int*)(0x42CF0170UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC5 *((volatile unsigned int*)(0x42CF0174UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_SA *((volatile unsigned int*)(0x42CF0178UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_AE *((volatile unsigned int*)(0x42CF017CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A0 *((volatile unsigned int*)(0x42CF0180UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A1 *((volatile unsigned int*)(0x42CF0184UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A2 *((volatile unsigned int*)(0x42CF0188UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A3 *((volatile unsigned int*)(0x42CF018CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A4 *((volatile unsigned int*)(0x42CF0190UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A5 *((volatile unsigned int*)(0x42CF0194UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A6 *((volatile unsigned int*)(0x42CF0198UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A7 *((volatile unsigned int*)(0x42CF019CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A8 *((volatile unsigned int*)(0x42CF01A0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A9 *((volatile unsigned int*)(0x42CF01A4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A10 *((volatile unsigned int*)(0x42CF01A8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A11 *((volatile unsigned int*)(0x42CF01ACUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A12 *((volatile unsigned int*)(0x42CF01B0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A13 *((volatile unsigned int*)(0x42CF01B4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A14 *((volatile unsigned int*)(0x42CF01B8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A15 *((volatile unsigned int*)(0x42CF01BCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A16 *((volatile unsigned int*)(0x42CF01C0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A17 *((volatile unsigned int*)(0x42CF01C4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A18 *((volatile unsigned int*)(0x42CF01C8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A19 *((volatile unsigned int*)(0x42CF01CCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A20 *((volatile unsigned int*)(0x42CF01D0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A21 *((volatile unsigned int*)(0x42CF01D4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A22 *((volatile unsigned int*)(0x42CF01D8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A23 *((volatile unsigned int*)(0x42CF01DCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A24 *((volatile unsigned int*)(0x42CF01E0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A25 *((volatile unsigned int*)(0x42CF01E4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A26 *((volatile unsigned int*)(0x42CF01E8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A27 *((volatile unsigned int*)(0x42CF01ECUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A28 *((volatile unsigned int*)(0x42CF01F0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A29 *((volatile unsigned int*)(0x42CF01F4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A30 *((volatile unsigned int*)(0x42CF01F8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A31 *((volatile unsigned int*)(0x42CF01FCUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A32 *((volatile unsigned int*)(0x42CF0200UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A33 *((volatile unsigned int*)(0x42CF0204UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A34 *((volatile unsigned int*)(0x42CF0208UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A35 *((volatile unsigned int*)(0x42CF020CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A36 *((volatile unsigned int*)(0x42CF0210UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A37 *((volatile unsigned int*)(0x42CF0214UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A38 *((volatile unsigned int*)(0x42CF0218UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A39 *((volatile unsigned int*)(0x42CF021CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A40 *((volatile unsigned int*)(0x42CF0220UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A41 *((volatile unsigned int*)(0x42CF0224UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A42 *((volatile unsigned int*)(0x42CF0228UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A43 *((volatile unsigned int*)(0x42CF022CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A44 *((volatile unsigned int*)(0x42CF0230UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A45 *((volatile unsigned int*)(0x42CF0234UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A46 *((volatile unsigned int*)(0x42CF0238UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A47 *((volatile unsigned int*)(0x42CF023CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC0 *((volatile unsigned int*)(0x42CF0260UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC1 *((volatile unsigned int*)(0x42CF0264UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC2 *((volatile unsigned int*)(0x42CF0268UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC3 *((volatile unsigned int*)(0x42CF026CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC4 *((volatile unsigned int*)(0x42CF0270UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC5 *((volatile unsigned int*)(0x42CF0274UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_SA *((volatile unsigned int*)(0x42CF0278UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_AE *((volatile unsigned int*)(0x42CF027CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A0 *((volatile unsigned int*)(0x42CF0280UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A1 *((volatile unsigned int*)(0x42CF0284UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A2 *((volatile unsigned int*)(0x42CF0288UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A3 *((volatile unsigned int*)(0x42CF028CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A4 *((volatile unsigned int*)(0x42CF0290UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A5 *((volatile unsigned int*)(0x42CF0294UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A6 *((volatile unsigned int*)(0x42CF0298UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A7 *((volatile unsigned int*)(0x42CF029CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A8 *((volatile unsigned int*)(0x42CF02A0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A9 *((volatile unsigned int*)(0x42CF02A4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A10 *((volatile unsigned int*)(0x42CF02A8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A11 *((volatile unsigned int*)(0x42CF02ACUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A12 *((volatile unsigned int*)(0x42CF02B0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A13 *((volatile unsigned int*)(0x42CF02B4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A14 *((volatile unsigned int*)(0x42CF02B8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A15 *((volatile unsigned int*)(0x42CF02BCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A16 *((volatile unsigned int*)(0x42CF02C0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A17 *((volatile unsigned int*)(0x42CF02C4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A18 *((volatile unsigned int*)(0x42CF02C8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A19 *((volatile unsigned int*)(0x42CF02CCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A20 *((volatile unsigned int*)(0x42CF02D0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A21 *((volatile unsigned int*)(0x42CF02D4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A22 *((volatile unsigned int*)(0x42CF02D8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A23 *((volatile unsigned int*)(0x42CF02DCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A24 *((volatile unsigned int*)(0x42CF02E0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A25 *((volatile unsigned int*)(0x42CF02E4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A26 *((volatile unsigned int*)(0x42CF02E8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A27 *((volatile unsigned int*)(0x42CF02ECUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A28 *((volatile unsigned int*)(0x42CF02F0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A29 *((volatile unsigned int*)(0x42CF02F4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A30 *((volatile unsigned int*)(0x42CF02F8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A31 *((volatile unsigned int*)(0x42CF02FCUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A32 *((volatile unsigned int*)(0x42CF0300UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A33 *((volatile unsigned int*)(0x42CF0304UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A34 *((volatile unsigned int*)(0x42CF0308UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A35 *((volatile unsigned int*)(0x42CF030CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A36 *((volatile unsigned int*)(0x42CF0310UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A37 *((volatile unsigned int*)(0x42CF0314UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A38 *((volatile unsigned int*)(0x42CF0318UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A39 *((volatile unsigned int*)(0x42CF031CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A40 *((volatile unsigned int*)(0x42CF0320UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A41 *((volatile unsigned int*)(0x42CF0324UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A42 *((volatile unsigned int*)(0x42CF0328UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A43 *((volatile unsigned int*)(0x42CF032CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A44 *((volatile unsigned int*)(0x42CF0330UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A45 *((volatile unsigned int*)(0x42CF0334UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A46 *((volatile unsigned int*)(0x42CF0338UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A47 *((volatile unsigned int*)(0x42CF033CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC0 *((volatile unsigned int*)(0x42CF0360UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC1 *((volatile unsigned int*)(0x42CF0364UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC2 *((volatile unsigned int*)(0x42CF0368UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC3 *((volatile unsigned int*)(0x42CF036CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC4 *((volatile unsigned int*)(0x42CF0370UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC5 *((volatile unsigned int*)(0x42CF0374UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_SA *((volatile unsigned int*)(0x42CF0378UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_AE *((volatile unsigned int*)(0x42CF037CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A0 *((volatile unsigned int*)(0x42CF0380UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A1 *((volatile unsigned int*)(0x42CF0384UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A2 *((volatile unsigned int*)(0x42CF0388UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A3 *((volatile unsigned int*)(0x42CF038CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A4 *((volatile unsigned int*)(0x42CF0390UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A5 *((volatile unsigned int*)(0x42CF0394UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A6 *((volatile unsigned int*)(0x42CF0398UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A7 *((volatile unsigned int*)(0x42CF039CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A8 *((volatile unsigned int*)(0x42CF03A0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A9 *((volatile unsigned int*)(0x42CF03A4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A10 *((volatile unsigned int*)(0x42CF03A8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A11 *((volatile unsigned int*)(0x42CF03ACUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A12 *((volatile unsigned int*)(0x42CF03B0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A13 *((volatile unsigned int*)(0x42CF03B4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A14 *((volatile unsigned int*)(0x42CF03B8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A15 *((volatile unsigned int*)(0x42CF03BCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A16 *((volatile unsigned int*)(0x42CF03C0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A17 *((volatile unsigned int*)(0x42CF03C4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A18 *((volatile unsigned int*)(0x42CF03C8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A19 *((volatile unsigned int*)(0x42CF03CCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A20 *((volatile unsigned int*)(0x42CF03D0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A21 *((volatile unsigned int*)(0x42CF03D4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A22 *((volatile unsigned int*)(0x42CF03D8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A23 *((volatile unsigned int*)(0x42CF03DCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A24 *((volatile unsigned int*)(0x42CF03E0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A25 *((volatile unsigned int*)(0x42CF03E4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A26 *((volatile unsigned int*)(0x42CF03E8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A27 *((volatile unsigned int*)(0x42CF03ECUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A28 *((volatile unsigned int*)(0x42CF03F0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A29 *((volatile unsigned int*)(0x42CF03F4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A30 *((volatile unsigned int*)(0x42CF03F8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A31 *((volatile unsigned int*)(0x42CF03FCUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A32 *((volatile unsigned int*)(0x42CF0400UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A33 *((volatile unsigned int*)(0x42CF0404UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A34 *((volatile unsigned int*)(0x42CF0408UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A35 *((volatile unsigned int*)(0x42CF040CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A36 *((volatile unsigned int*)(0x42CF0410UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A37 *((volatile unsigned int*)(0x42CF0414UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A38 *((volatile unsigned int*)(0x42CF0418UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A39 *((volatile unsigned int*)(0x42CF041CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A40 *((volatile unsigned int*)(0x42CF0420UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A41 *((volatile unsigned int*)(0x42CF0424UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A42 *((volatile unsigned int*)(0x42CF0428UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A43 *((volatile unsigned int*)(0x42CF042CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A44 *((volatile unsigned int*)(0x42CF0430UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A45 *((volatile unsigned int*)(0x42CF0434UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A46 *((volatile unsigned int*)(0x42CF0438UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A47 *((volatile unsigned int*)(0x42CF043CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC0 *((volatile unsigned int*)(0x42CF0460UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC1 *((volatile unsigned int*)(0x42CF0464UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC2 *((volatile unsigned int*)(0x42CF0468UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC3 *((volatile unsigned int*)(0x42CF046CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC4 *((volatile unsigned int*)(0x42CF0470UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC5 *((volatile unsigned int*)(0x42CF0474UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_SA *((volatile unsigned int*)(0x42CF0478UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_AE *((volatile unsigned int*)(0x42CF047CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A0 *((volatile unsigned int*)(0x42CF0480UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A1 *((volatile unsigned int*)(0x42CF0484UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A2 *((volatile unsigned int*)(0x42CF0488UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A3 *((volatile unsigned int*)(0x42CF048CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A4 *((volatile unsigned int*)(0x42CF0490UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A5 *((volatile unsigned int*)(0x42CF0494UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A6 *((volatile unsigned int*)(0x42CF0498UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A7 *((volatile unsigned int*)(0x42CF049CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A8 *((volatile unsigned int*)(0x42CF04A0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A9 *((volatile unsigned int*)(0x42CF04A4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A10 *((volatile unsigned int*)(0x42CF04A8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A11 *((volatile unsigned int*)(0x42CF04ACUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A12 *((volatile unsigned int*)(0x42CF04B0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A13 *((volatile unsigned int*)(0x42CF04B4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A14 *((volatile unsigned int*)(0x42CF04B8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A15 *((volatile unsigned int*)(0x42CF04BCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A16 *((volatile unsigned int*)(0x42CF04C0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A17 *((volatile unsigned int*)(0x42CF04C4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A18 *((volatile unsigned int*)(0x42CF04C8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A19 *((volatile unsigned int*)(0x42CF04CCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A20 *((volatile unsigned int*)(0x42CF04D0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A21 *((volatile unsigned int*)(0x42CF04D4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A22 *((volatile unsigned int*)(0x42CF04D8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A23 *((volatile unsigned int*)(0x42CF04DCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A24 *((volatile unsigned int*)(0x42CF04E0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A25 *((volatile unsigned int*)(0x42CF04E4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A26 *((volatile unsigned int*)(0x42CF04E8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A27 *((volatile unsigned int*)(0x42CF04ECUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A28 *((volatile unsigned int*)(0x42CF04F0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A29 *((volatile unsigned int*)(0x42CF04F4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A30 *((volatile unsigned int*)(0x42CF04F8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A31 *((volatile unsigned int*)(0x42CF04FCUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A32 *((volatile unsigned int*)(0x42CF0500UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A33 *((volatile unsigned int*)(0x42CF0504UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A34 *((volatile unsigned int*)(0x42CF0508UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A35 *((volatile unsigned int*)(0x42CF050CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A36 *((volatile unsigned int*)(0x42CF0510UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A37 *((volatile unsigned int*)(0x42CF0514UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A38 *((volatile unsigned int*)(0x42CF0518UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A39 *((volatile unsigned int*)(0x42CF051CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A40 *((volatile unsigned int*)(0x42CF0520UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A41 *((volatile unsigned int*)(0x42CF0524UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A42 *((volatile unsigned int*)(0x42CF0528UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A43 *((volatile unsigned int*)(0x42CF052CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A44 *((volatile unsigned int*)(0x42CF0530UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A45 *((volatile unsigned int*)(0x42CF0534UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A46 *((volatile unsigned int*)(0x42CF0538UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A47 *((volatile unsigned int*)(0x42CF053CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC0 *((volatile unsigned int*)(0x42CF0560UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC1 *((volatile unsigned int*)(0x42CF0564UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC2 *((volatile unsigned int*)(0x42CF0568UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC3 *((volatile unsigned int*)(0x42CF056CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC4 *((volatile unsigned int*)(0x42CF0570UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC5 *((volatile unsigned int*)(0x42CF0574UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_SA *((volatile unsigned int*)(0x42CF0578UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_AE *((volatile unsigned int*)(0x42CF057CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A0 *((volatile unsigned int*)(0x42CF0580UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A1 *((volatile unsigned int*)(0x42CF0584UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A2 *((volatile unsigned int*)(0x42CF0588UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A3 *((volatile unsigned int*)(0x42CF058CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A4 *((volatile unsigned int*)(0x42CF0590UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A5 *((volatile unsigned int*)(0x42CF0594UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A6 *((volatile unsigned int*)(0x42CF0598UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A7 *((volatile unsigned int*)(0x42CF059CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A8 *((volatile unsigned int*)(0x42CF05A0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A9 *((volatile unsigned int*)(0x42CF05A4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A10 *((volatile unsigned int*)(0x42CF05A8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A11 *((volatile unsigned int*)(0x42CF05ACUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A12 *((volatile unsigned int*)(0x42CF05B0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A13 *((volatile unsigned int*)(0x42CF05B4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A14 *((volatile unsigned int*)(0x42CF05B8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A15 *((volatile unsigned int*)(0x42CF05BCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A16 *((volatile unsigned int*)(0x42CF05C0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A17 *((volatile unsigned int*)(0x42CF05C4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A18 *((volatile unsigned int*)(0x42CF05C8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A19 *((volatile unsigned int*)(0x42CF05CCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A20 *((volatile unsigned int*)(0x42CF05D0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A21 *((volatile unsigned int*)(0x42CF05D4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A22 *((volatile unsigned int*)(0x42CF05D8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A23 *((volatile unsigned int*)(0x42CF05DCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A24 *((volatile unsigned int*)(0x42CF05E0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A25 *((volatile unsigned int*)(0x42CF05E4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A26 *((volatile unsigned int*)(0x42CF05E8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A27 *((volatile unsigned int*)(0x42CF05ECUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A28 *((volatile unsigned int*)(0x42CF05F0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A29 *((volatile unsigned int*)(0x42CF05F4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A30 *((volatile unsigned int*)(0x42CF05F8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A31 *((volatile unsigned int*)(0x42CF05FCUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A32 *((volatile unsigned int*)(0x42CF0600UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A33 *((volatile unsigned int*)(0x42CF0604UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A34 *((volatile unsigned int*)(0x42CF0608UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A35 *((volatile unsigned int*)(0x42CF060CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A36 *((volatile unsigned int*)(0x42CF0610UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A37 *((volatile unsigned int*)(0x42CF0614UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A38 *((volatile unsigned int*)(0x42CF0618UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A39 *((volatile unsigned int*)(0x42CF061CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A40 *((volatile unsigned int*)(0x42CF0620UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A41 *((volatile unsigned int*)(0x42CF0624UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A42 *((volatile unsigned int*)(0x42CF0628UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A43 *((volatile unsigned int*)(0x42CF062CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A44 *((volatile unsigned int*)(0x42CF0630UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A45 *((volatile unsigned int*)(0x42CF0634UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A46 *((volatile unsigned int*)(0x42CF0638UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A47 *((volatile unsigned int*)(0x42CF063CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC0 *((volatile unsigned int*)(0x42CF0660UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC1 *((volatile unsigned int*)(0x42CF0664UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC2 *((volatile unsigned int*)(0x42CF0668UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC3 *((volatile unsigned int*)(0x42CF066CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC4 *((volatile unsigned int*)(0x42CF0670UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC5 *((volatile unsigned int*)(0x42CF0674UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_SA *((volatile unsigned int*)(0x42CF0678UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_AE *((volatile unsigned int*)(0x42CF067CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A0 *((volatile unsigned int*)(0x42CF0680UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A1 *((volatile unsigned int*)(0x42CF0684UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A2 *((volatile unsigned int*)(0x42CF0688UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A3 *((volatile unsigned int*)(0x42CF068CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A4 *((volatile unsigned int*)(0x42CF0690UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A5 *((volatile unsigned int*)(0x42CF0694UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A6 *((volatile unsigned int*)(0x42CF0698UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A7 *((volatile unsigned int*)(0x42CF069CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A8 *((volatile unsigned int*)(0x42CF06A0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A9 *((volatile unsigned int*)(0x42CF06A4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A10 *((volatile unsigned int*)(0x42CF06A8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A11 *((volatile unsigned int*)(0x42CF06ACUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A12 *((volatile unsigned int*)(0x42CF06B0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A13 *((volatile unsigned int*)(0x42CF06B4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A14 *((volatile unsigned int*)(0x42CF06B8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A15 *((volatile unsigned int*)(0x42CF06BCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A16 *((volatile unsigned int*)(0x42CF06C0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A17 *((volatile unsigned int*)(0x42CF06C4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A18 *((volatile unsigned int*)(0x42CF06C8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A19 *((volatile unsigned int*)(0x42CF06CCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A20 *((volatile unsigned int*)(0x42CF06D0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A21 *((volatile unsigned int*)(0x42CF06D4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A22 *((volatile unsigned int*)(0x42CF06D8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A23 *((volatile unsigned int*)(0x42CF06DCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A24 *((volatile unsigned int*)(0x42CF06E0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A25 *((volatile unsigned int*)(0x42CF06E4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A26 *((volatile unsigned int*)(0x42CF06E8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A27 *((volatile unsigned int*)(0x42CF06ECUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A28 *((volatile unsigned int*)(0x42CF06F0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A29 *((volatile unsigned int*)(0x42CF06F4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A30 *((volatile unsigned int*)(0x42CF06F8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A31 *((volatile unsigned int*)(0x42CF06FCUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A32 *((volatile unsigned int*)(0x42CF0700UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A33 *((volatile unsigned int*)(0x42CF0704UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A34 *((volatile unsigned int*)(0x42CF0708UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A35 *((volatile unsigned int*)(0x42CF070CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A36 *((volatile unsigned int*)(0x42CF0710UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A37 *((volatile unsigned int*)(0x42CF0714UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A38 *((volatile unsigned int*)(0x42CF0718UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A39 *((volatile unsigned int*)(0x42CF071CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A40 *((volatile unsigned int*)(0x42CF0720UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A41 *((volatile unsigned int*)(0x42CF0724UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A42 *((volatile unsigned int*)(0x42CF0728UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A43 *((volatile unsigned int*)(0x42CF072CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A44 *((volatile unsigned int*)(0x42CF0730UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A45 *((volatile unsigned int*)(0x42CF0734UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A46 *((volatile unsigned int*)(0x42CF0738UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A47 *((volatile unsigned int*)(0x42CF073CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC0 *((volatile unsigned int*)(0x42CF0760UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC1 *((volatile unsigned int*)(0x42CF0764UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC2 *((volatile unsigned int*)(0x42CF0768UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC3 *((volatile unsigned int*)(0x42CF076CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC4 *((volatile unsigned int*)(0x42CF0770UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC5 *((volatile unsigned int*)(0x42CF0774UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_SA *((volatile unsigned int*)(0x42CF0778UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_AE *((volatile unsigned int*)(0x42CF077CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A0 *((volatile unsigned int*)(0x42CF0780UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A1 *((volatile unsigned int*)(0x42CF0784UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A2 *((volatile unsigned int*)(0x42CF0788UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A3 *((volatile unsigned int*)(0x42CF078CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A4 *((volatile unsigned int*)(0x42CF0790UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A5 *((volatile unsigned int*)(0x42CF0794UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A6 *((volatile unsigned int*)(0x42CF0798UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A7 *((volatile unsigned int*)(0x42CF079CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A8 *((volatile unsigned int*)(0x42CF07A0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A9 *((volatile unsigned int*)(0x42CF07A4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A10 *((volatile unsigned int*)(0x42CF07A8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A11 *((volatile unsigned int*)(0x42CF07ACUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A12 *((volatile unsigned int*)(0x42CF07B0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A13 *((volatile unsigned int*)(0x42CF07B4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A14 *((volatile unsigned int*)(0x42CF07B8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A15 *((volatile unsigned int*)(0x42CF07BCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A16 *((volatile unsigned int*)(0x42CF07C0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A17 *((volatile unsigned int*)(0x42CF07C4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A18 *((volatile unsigned int*)(0x42CF07C8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A19 *((volatile unsigned int*)(0x42CF07CCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A20 *((volatile unsigned int*)(0x42CF07D0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A21 *((volatile unsigned int*)(0x42CF07D4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A22 *((volatile unsigned int*)(0x42CF07D8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A23 *((volatile unsigned int*)(0x42CF07DCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A24 *((volatile unsigned int*)(0x42CF07E0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A25 *((volatile unsigned int*)(0x42CF07E4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A26 *((volatile unsigned int*)(0x42CF07E8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A27 *((volatile unsigned int*)(0x42CF07ECUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A28 *((volatile unsigned int*)(0x42CF07F0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A29 *((volatile unsigned int*)(0x42CF07F4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A30 *((volatile unsigned int*)(0x42CF07F8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A31 *((volatile unsigned int*)(0x42CF07FCUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A32 *((volatile unsigned int*)(0x42CF0800UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A33 *((volatile unsigned int*)(0x42CF0804UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A34 *((volatile unsigned int*)(0x42CF0808UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A35 *((volatile unsigned int*)(0x42CF080CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A36 *((volatile unsigned int*)(0x42CF0810UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A37 *((volatile unsigned int*)(0x42CF0814UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A38 *((volatile unsigned int*)(0x42CF0818UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A39 *((volatile unsigned int*)(0x42CF081CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A40 *((volatile unsigned int*)(0x42CF0820UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A41 *((volatile unsigned int*)(0x42CF0824UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A42 *((volatile unsigned int*)(0x42CF0828UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A43 *((volatile unsigned int*)(0x42CF082CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A44 *((volatile unsigned int*)(0x42CF0830UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A45 *((volatile unsigned int*)(0x42CF0834UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A46 *((volatile unsigned int*)(0x42CF0838UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A47 *((volatile unsigned int*)(0x42CF083CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC0 *((volatile unsigned int*)(0x42CF0860UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC1 *((volatile unsigned int*)(0x42CF0864UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC2 *((volatile unsigned int*)(0x42CF0868UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC3 *((volatile unsigned int*)(0x42CF086CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC4 *((volatile unsigned int*)(0x42CF0870UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC5 *((volatile unsigned int*)(0x42CF0874UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_SA *((volatile unsigned int*)(0x42CF0878UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_AE *((volatile unsigned int*)(0x42CF087CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A0 *((volatile unsigned int*)(0x42CF0880UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A1 *((volatile unsigned int*)(0x42CF0884UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A2 *((volatile unsigned int*)(0x42CF0888UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A3 *((volatile unsigned int*)(0x42CF088CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A4 *((volatile unsigned int*)(0x42CF0890UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A5 *((volatile unsigned int*)(0x42CF0894UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A6 *((volatile unsigned int*)(0x42CF0898UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A7 *((volatile unsigned int*)(0x42CF089CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A8 *((volatile unsigned int*)(0x42CF08A0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A9 *((volatile unsigned int*)(0x42CF08A4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A10 *((volatile unsigned int*)(0x42CF08A8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A11 *((volatile unsigned int*)(0x42CF08ACUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A12 *((volatile unsigned int*)(0x42CF08B0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A13 *((volatile unsigned int*)(0x42CF08B4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A14 *((volatile unsigned int*)(0x42CF08B8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A15 *((volatile unsigned int*)(0x42CF08BCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A16 *((volatile unsigned int*)(0x42CF08C0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A17 *((volatile unsigned int*)(0x42CF08C4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A18 *((volatile unsigned int*)(0x42CF08C8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A19 *((volatile unsigned int*)(0x42CF08CCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A20 *((volatile unsigned int*)(0x42CF08D0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A21 *((volatile unsigned int*)(0x42CF08D4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A22 *((volatile unsigned int*)(0x42CF08D8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A23 *((volatile unsigned int*)(0x42CF08DCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A24 *((volatile unsigned int*)(0x42CF08E0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A25 *((volatile unsigned int*)(0x42CF08E4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A26 *((volatile unsigned int*)(0x42CF08E8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A27 *((volatile unsigned int*)(0x42CF08ECUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A28 *((volatile unsigned int*)(0x42CF08F0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A29 *((volatile unsigned int*)(0x42CF08F4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A30 *((volatile unsigned int*)(0x42CF08F8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A31 *((volatile unsigned int*)(0x42CF08FCUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A32 *((volatile unsigned int*)(0x42CF0900UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A33 *((volatile unsigned int*)(0x42CF0904UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A34 *((volatile unsigned int*)(0x42CF0908UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A35 *((volatile unsigned int*)(0x42CF090CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A36 *((volatile unsigned int*)(0x42CF0910UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A37 *((volatile unsigned int*)(0x42CF0914UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A38 *((volatile unsigned int*)(0x42CF0918UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A39 *((volatile unsigned int*)(0x42CF091CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A40 *((volatile unsigned int*)(0x42CF0920UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A41 *((volatile unsigned int*)(0x42CF0924UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A42 *((volatile unsigned int*)(0x42CF0928UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A43 *((volatile unsigned int*)(0x42CF092CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A44 *((volatile unsigned int*)(0x42CF0930UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A45 *((volatile unsigned int*)(0x42CF0934UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A46 *((volatile unsigned int*)(0x42CF0938UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A47 *((volatile unsigned int*)(0x42CF093CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC0 *((volatile unsigned int*)(0x42CF0960UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC1 *((volatile unsigned int*)(0x42CF0964UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC2 *((volatile unsigned int*)(0x42CF0968UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC3 *((volatile unsigned int*)(0x42CF096CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC4 *((volatile unsigned int*)(0x42CF0970UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC5 *((volatile unsigned int*)(0x42CF0974UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_SA *((volatile unsigned int*)(0x42CF0978UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_AE *((volatile unsigned int*)(0x42CF097CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A0 *((volatile unsigned int*)(0x42CF0980UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A1 *((volatile unsigned int*)(0x42CF0984UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A2 *((volatile unsigned int*)(0x42CF0988UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A3 *((volatile unsigned int*)(0x42CF098CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A4 *((volatile unsigned int*)(0x42CF0990UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A5 *((volatile unsigned int*)(0x42CF0994UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A6 *((volatile unsigned int*)(0x42CF0998UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A7 *((volatile unsigned int*)(0x42CF099CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A8 *((volatile unsigned int*)(0x42CF09A0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A9 *((volatile unsigned int*)(0x42CF09A4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A10 *((volatile unsigned int*)(0x42CF09A8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A11 *((volatile unsigned int*)(0x42CF09ACUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A12 *((volatile unsigned int*)(0x42CF09B0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A13 *((volatile unsigned int*)(0x42CF09B4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A14 *((volatile unsigned int*)(0x42CF09B8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A15 *((volatile unsigned int*)(0x42CF09BCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A16 *((volatile unsigned int*)(0x42CF09C0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A17 *((volatile unsigned int*)(0x42CF09C4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A18 *((volatile unsigned int*)(0x42CF09C8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A19 *((volatile unsigned int*)(0x42CF09CCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A20 *((volatile unsigned int*)(0x42CF09D0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A21 *((volatile unsigned int*)(0x42CF09D4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A22 *((volatile unsigned int*)(0x42CF09D8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A23 *((volatile unsigned int*)(0x42CF09DCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A24 *((volatile unsigned int*)(0x42CF09E0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A25 *((volatile unsigned int*)(0x42CF09E4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A26 *((volatile unsigned int*)(0x42CF09E8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A27 *((volatile unsigned int*)(0x42CF09ECUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A28 *((volatile unsigned int*)(0x42CF09F0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A29 *((volatile unsigned int*)(0x42CF09F4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A30 *((volatile unsigned int*)(0x42CF09F8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A31 *((volatile unsigned int*)(0x42CF09FCUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A32 *((volatile unsigned int*)(0x42CF0A00UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A33 *((volatile unsigned int*)(0x42CF0A04UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A34 *((volatile unsigned int*)(0x42CF0A08UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A35 *((volatile unsigned int*)(0x42CF0A0CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A36 *((volatile unsigned int*)(0x42CF0A10UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A37 *((volatile unsigned int*)(0x42CF0A14UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A38 *((volatile unsigned int*)(0x42CF0A18UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A39 *((volatile unsigned int*)(0x42CF0A1CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A40 *((volatile unsigned int*)(0x42CF0A20UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A41 *((volatile unsigned int*)(0x42CF0A24UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A42 *((volatile unsigned int*)(0x42CF0A28UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A43 *((volatile unsigned int*)(0x42CF0A2CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A44 *((volatile unsigned int*)(0x42CF0A30UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A45 *((volatile unsigned int*)(0x42CF0A34UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A46 *((volatile unsigned int*)(0x42CF0A38UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A47 *((volatile unsigned int*)(0x42CF0A3CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC0 *((volatile unsigned int*)(0x42CF0A60UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC1 *((volatile unsigned int*)(0x42CF0A64UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC2 *((volatile unsigned int*)(0x42CF0A68UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC3 *((volatile unsigned int*)(0x42CF0A6CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC4 *((volatile unsigned int*)(0x42CF0A70UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC5 *((volatile unsigned int*)(0x42CF0A74UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_SA *((volatile unsigned int*)(0x42CF0A78UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_AE *((volatile unsigned int*)(0x42CF0A7CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A0 *((volatile unsigned int*)(0x42CF0A80UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A1 *((volatile unsigned int*)(0x42CF0A84UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A2 *((volatile unsigned int*)(0x42CF0A88UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A3 *((volatile unsigned int*)(0x42CF0A8CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A4 *((volatile unsigned int*)(0x42CF0A90UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A5 *((volatile unsigned int*)(0x42CF0A94UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A6 *((volatile unsigned int*)(0x42CF0A98UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A7 *((volatile unsigned int*)(0x42CF0A9CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A8 *((volatile unsigned int*)(0x42CF0AA0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A9 *((volatile unsigned int*)(0x42CF0AA4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A10 *((volatile unsigned int*)(0x42CF0AA8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A11 *((volatile unsigned int*)(0x42CF0AACUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A12 *((volatile unsigned int*)(0x42CF0AB0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A13 *((volatile unsigned int*)(0x42CF0AB4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A14 *((volatile unsigned int*)(0x42CF0AB8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A15 *((volatile unsigned int*)(0x42CF0ABCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A16 *((volatile unsigned int*)(0x42CF0AC0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A17 *((volatile unsigned int*)(0x42CF0AC4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A18 *((volatile unsigned int*)(0x42CF0AC8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A19 *((volatile unsigned int*)(0x42CF0ACCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A20 *((volatile unsigned int*)(0x42CF0AD0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A21 *((volatile unsigned int*)(0x42CF0AD4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A22 *((volatile unsigned int*)(0x42CF0AD8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A23 *((volatile unsigned int*)(0x42CF0ADCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A24 *((volatile unsigned int*)(0x42CF0AE0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A25 *((volatile unsigned int*)(0x42CF0AE4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A26 *((volatile unsigned int*)(0x42CF0AE8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A27 *((volatile unsigned int*)(0x42CF0AECUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A28 *((volatile unsigned int*)(0x42CF0AF0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A29 *((volatile unsigned int*)(0x42CF0AF4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A30 *((volatile unsigned int*)(0x42CF0AF8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A31 *((volatile unsigned int*)(0x42CF0AFCUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A32 *((volatile unsigned int*)(0x42CF0B00UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A33 *((volatile unsigned int*)(0x42CF0B04UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A34 *((volatile unsigned int*)(0x42CF0B08UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A35 *((volatile unsigned int*)(0x42CF0B0CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A36 *((volatile unsigned int*)(0x42CF0B10UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A37 *((volatile unsigned int*)(0x42CF0B14UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A38 *((volatile unsigned int*)(0x42CF0B18UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A39 *((volatile unsigned int*)(0x42CF0B1CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A40 *((volatile unsigned int*)(0x42CF0B20UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A41 *((volatile unsigned int*)(0x42CF0B24UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A42 *((volatile unsigned int*)(0x42CF0B28UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A43 *((volatile unsigned int*)(0x42CF0B2CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A44 *((volatile unsigned int*)(0x42CF0B30UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A45 *((volatile unsigned int*)(0x42CF0B34UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A46 *((volatile unsigned int*)(0x42CF0B38UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A47 *((volatile unsigned int*)(0x42CF0B3CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC0 *((volatile unsigned int*)(0x42CF0B60UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC1 *((volatile unsigned int*)(0x42CF0B64UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC2 *((volatile unsigned int*)(0x42CF0B68UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC3 *((volatile unsigned int*)(0x42CF0B6CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC4 *((volatile unsigned int*)(0x42CF0B70UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC5 *((volatile unsigned int*)(0x42CF0B74UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_SA *((volatile unsigned int*)(0x42CF0B78UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_AE *((volatile unsigned int*)(0x42CF0B7CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A0 *((volatile unsigned int*)(0x42CF0B80UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A1 *((volatile unsigned int*)(0x42CF0B84UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A2 *((volatile unsigned int*)(0x42CF0B88UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A3 *((volatile unsigned int*)(0x42CF0B8CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A4 *((volatile unsigned int*)(0x42CF0B90UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A5 *((volatile unsigned int*)(0x42CF0B94UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A6 *((volatile unsigned int*)(0x42CF0B98UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A7 *((volatile unsigned int*)(0x42CF0B9CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A8 *((volatile unsigned int*)(0x42CF0BA0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A9 *((volatile unsigned int*)(0x42CF0BA4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A10 *((volatile unsigned int*)(0x42CF0BA8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A11 *((volatile unsigned int*)(0x42CF0BACUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A12 *((volatile unsigned int*)(0x42CF0BB0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A13 *((volatile unsigned int*)(0x42CF0BB4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A14 *((volatile unsigned int*)(0x42CF0BB8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A15 *((volatile unsigned int*)(0x42CF0BBCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A16 *((volatile unsigned int*)(0x42CF0BC0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A17 *((volatile unsigned int*)(0x42CF0BC4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A18 *((volatile unsigned int*)(0x42CF0BC8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A19 *((volatile unsigned int*)(0x42CF0BCCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A20 *((volatile unsigned int*)(0x42CF0BD0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A21 *((volatile unsigned int*)(0x42CF0BD4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A22 *((volatile unsigned int*)(0x42CF0BD8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A23 *((volatile unsigned int*)(0x42CF0BDCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A24 *((volatile unsigned int*)(0x42CF0BE0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A25 *((volatile unsigned int*)(0x42CF0BE4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A26 *((volatile unsigned int*)(0x42CF0BE8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A27 *((volatile unsigned int*)(0x42CF0BECUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A28 *((volatile unsigned int*)(0x42CF0BF0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A29 *((volatile unsigned int*)(0x42CF0BF4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A30 *((volatile unsigned int*)(0x42CF0BF8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A31 *((volatile unsigned int*)(0x42CF0BFCUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A32 *((volatile unsigned int*)(0x42CF0C00UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A33 *((volatile unsigned int*)(0x42CF0C04UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A34 *((volatile unsigned int*)(0x42CF0C08UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A35 *((volatile unsigned int*)(0x42CF0C0CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A36 *((volatile unsigned int*)(0x42CF0C10UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A37 *((volatile unsigned int*)(0x42CF0C14UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A38 *((volatile unsigned int*)(0x42CF0C18UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A39 *((volatile unsigned int*)(0x42CF0C1CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A40 *((volatile unsigned int*)(0x42CF0C20UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A41 *((volatile unsigned int*)(0x42CF0C24UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A42 *((volatile unsigned int*)(0x42CF0C28UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A43 *((volatile unsigned int*)(0x42CF0C2CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A44 *((volatile unsigned int*)(0x42CF0C30UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A45 *((volatile unsigned int*)(0x42CF0C34UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A46 *((volatile unsigned int*)(0x42CF0C38UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A47 *((volatile unsigned int*)(0x42CF0C3CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC0 *((volatile unsigned int*)(0x42CF0C60UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC1 *((volatile unsigned int*)(0x42CF0C64UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC2 *((volatile unsigned int*)(0x42CF0C68UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC3 *((volatile unsigned int*)(0x42CF0C6CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC4 *((volatile unsigned int*)(0x42CF0C70UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC5 *((volatile unsigned int*)(0x42CF0C74UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_SA *((volatile unsigned int*)(0x42CF0C78UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_AE *((volatile unsigned int*)(0x42CF0C7CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A0 *((volatile unsigned int*)(0x42CF0C80UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A1 *((volatile unsigned int*)(0x42CF0C84UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A2 *((volatile unsigned int*)(0x42CF0C88UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A3 *((volatile unsigned int*)(0x42CF0C8CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A4 *((volatile unsigned int*)(0x42CF0C90UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A5 *((volatile unsigned int*)(0x42CF0C94UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A6 *((volatile unsigned int*)(0x42CF0C98UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A7 *((volatile unsigned int*)(0x42CF0C9CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A8 *((volatile unsigned int*)(0x42CF0CA0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A9 *((volatile unsigned int*)(0x42CF0CA4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A10 *((volatile unsigned int*)(0x42CF0CA8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A11 *((volatile unsigned int*)(0x42CF0CACUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A12 *((volatile unsigned int*)(0x42CF0CB0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A13 *((volatile unsigned int*)(0x42CF0CB4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A14 *((volatile unsigned int*)(0x42CF0CB8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A15 *((volatile unsigned int*)(0x42CF0CBCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A16 *((volatile unsigned int*)(0x42CF0CC0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A17 *((volatile unsigned int*)(0x42CF0CC4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A18 *((volatile unsigned int*)(0x42CF0CC8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A19 *((volatile unsigned int*)(0x42CF0CCCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A20 *((volatile unsigned int*)(0x42CF0CD0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A21 *((volatile unsigned int*)(0x42CF0CD4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A22 *((volatile unsigned int*)(0x42CF0CD8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A23 *((volatile unsigned int*)(0x42CF0CDCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A24 *((volatile unsigned int*)(0x42CF0CE0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A25 *((volatile unsigned int*)(0x42CF0CE4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A26 *((volatile unsigned int*)(0x42CF0CE8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A27 *((volatile unsigned int*)(0x42CF0CECUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A28 *((volatile unsigned int*)(0x42CF0CF0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A29 *((volatile unsigned int*)(0x42CF0CF4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A30 *((volatile unsigned int*)(0x42CF0CF8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A31 *((volatile unsigned int*)(0x42CF0CFCUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A32 *((volatile unsigned int*)(0x42CF0D00UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A33 *((volatile unsigned int*)(0x42CF0D04UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A34 *((volatile unsigned int*)(0x42CF0D08UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A35 *((volatile unsigned int*)(0x42CF0D0CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A36 *((volatile unsigned int*)(0x42CF0D10UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A37 *((volatile unsigned int*)(0x42CF0D14UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A38 *((volatile unsigned int*)(0x42CF0D18UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A39 *((volatile unsigned int*)(0x42CF0D1CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A40 *((volatile unsigned int*)(0x42CF0D20UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A41 *((volatile unsigned int*)(0x42CF0D24UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A42 *((volatile unsigned int*)(0x42CF0D28UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A43 *((volatile unsigned int*)(0x42CF0D2CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A44 *((volatile unsigned int*)(0x42CF0D30UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A45 *((volatile unsigned int*)(0x42CF0D34UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A46 *((volatile unsigned int*)(0x42CF0D38UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A47 *((volatile unsigned int*)(0x42CF0D3CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC0 *((volatile unsigned int*)(0x42CF0D60UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC1 *((volatile unsigned int*)(0x42CF0D64UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC2 *((volatile unsigned int*)(0x42CF0D68UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC3 *((volatile unsigned int*)(0x42CF0D6CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC4 *((volatile unsigned int*)(0x42CF0D70UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC5 *((volatile unsigned int*)(0x42CF0D74UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_SA *((volatile unsigned int*)(0x42CF0D78UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_AE *((volatile unsigned int*)(0x42CF0D7CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A0 *((volatile unsigned int*)(0x42CF0D80UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A1 *((volatile unsigned int*)(0x42CF0D84UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A2 *((volatile unsigned int*)(0x42CF0D88UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A3 *((volatile unsigned int*)(0x42CF0D8CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A4 *((volatile unsigned int*)(0x42CF0D90UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A5 *((volatile unsigned int*)(0x42CF0D94UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A6 *((volatile unsigned int*)(0x42CF0D98UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A7 *((volatile unsigned int*)(0x42CF0D9CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A8 *((volatile unsigned int*)(0x42CF0DA0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A9 *((volatile unsigned int*)(0x42CF0DA4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A10 *((volatile unsigned int*)(0x42CF0DA8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A11 *((volatile unsigned int*)(0x42CF0DACUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A12 *((volatile unsigned int*)(0x42CF0DB0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A13 *((volatile unsigned int*)(0x42CF0DB4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A14 *((volatile unsigned int*)(0x42CF0DB8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A15 *((volatile unsigned int*)(0x42CF0DBCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A16 *((volatile unsigned int*)(0x42CF0DC0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A17 *((volatile unsigned int*)(0x42CF0DC4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A18 *((volatile unsigned int*)(0x42CF0DC8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A19 *((volatile unsigned int*)(0x42CF0DCCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A20 *((volatile unsigned int*)(0x42CF0DD0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A21 *((volatile unsigned int*)(0x42CF0DD4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A22 *((volatile unsigned int*)(0x42CF0DD8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A23 *((volatile unsigned int*)(0x42CF0DDCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A24 *((volatile unsigned int*)(0x42CF0DE0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A25 *((volatile unsigned int*)(0x42CF0DE4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A26 *((volatile unsigned int*)(0x42CF0DE8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A27 *((volatile unsigned int*)(0x42CF0DECUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A28 *((volatile unsigned int*)(0x42CF0DF0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A29 *((volatile unsigned int*)(0x42CF0DF4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A30 *((volatile unsigned int*)(0x42CF0DF8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A31 *((volatile unsigned int*)(0x42CF0DFCUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A32 *((volatile unsigned int*)(0x42CF0E00UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A33 *((volatile unsigned int*)(0x42CF0E04UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A34 *((volatile unsigned int*)(0x42CF0E08UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A35 *((volatile unsigned int*)(0x42CF0E0CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A36 *((volatile unsigned int*)(0x42CF0E10UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A37 *((volatile unsigned int*)(0x42CF0E14UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A38 *((volatile unsigned int*)(0x42CF0E18UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A39 *((volatile unsigned int*)(0x42CF0E1CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A40 *((volatile unsigned int*)(0x42CF0E20UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A41 *((volatile unsigned int*)(0x42CF0E24UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A42 *((volatile unsigned int*)(0x42CF0E28UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A43 *((volatile unsigned int*)(0x42CF0E2CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A44 *((volatile unsigned int*)(0x42CF0E30UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A45 *((volatile unsigned int*)(0x42CF0E34UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A46 *((volatile unsigned int*)(0x42CF0E38UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A47 *((volatile unsigned int*)(0x42CF0E3CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC0 *((volatile unsigned int*)(0x42CF0E60UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC1 *((volatile unsigned int*)(0x42CF0E64UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC2 *((volatile unsigned int*)(0x42CF0E68UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC3 *((volatile unsigned int*)(0x42CF0E6CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC4 *((volatile unsigned int*)(0x42CF0E70UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC5 *((volatile unsigned int*)(0x42CF0E74UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_SA *((volatile unsigned int*)(0x42CF0E78UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_AE *((volatile unsigned int*)(0x42CF0E7CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A0 *((volatile unsigned int*)(0x42CF0E80UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A1 *((volatile unsigned int*)(0x42CF0E84UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A2 *((volatile unsigned int*)(0x42CF0E88UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A3 *((volatile unsigned int*)(0x42CF0E8CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A4 *((volatile unsigned int*)(0x42CF0E90UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A5 *((volatile unsigned int*)(0x42CF0E94UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A6 *((volatile unsigned int*)(0x42CF0E98UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A7 *((volatile unsigned int*)(0x42CF0E9CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A8 *((volatile unsigned int*)(0x42CF0EA0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A9 *((volatile unsigned int*)(0x42CF0EA4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A10 *((volatile unsigned int*)(0x42CF0EA8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A11 *((volatile unsigned int*)(0x42CF0EACUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A12 *((volatile unsigned int*)(0x42CF0EB0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A13 *((volatile unsigned int*)(0x42CF0EB4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A14 *((volatile unsigned int*)(0x42CF0EB8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A15 *((volatile unsigned int*)(0x42CF0EBCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A16 *((volatile unsigned int*)(0x42CF0EC0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A17 *((volatile unsigned int*)(0x42CF0EC4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A18 *((volatile unsigned int*)(0x42CF0EC8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A19 *((volatile unsigned int*)(0x42CF0ECCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A20 *((volatile unsigned int*)(0x42CF0ED0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A21 *((volatile unsigned int*)(0x42CF0ED4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A22 *((volatile unsigned int*)(0x42CF0ED8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A23 *((volatile unsigned int*)(0x42CF0EDCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A24 *((volatile unsigned int*)(0x42CF0EE0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A25 *((volatile unsigned int*)(0x42CF0EE4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A26 *((volatile unsigned int*)(0x42CF0EE8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A27 *((volatile unsigned int*)(0x42CF0EECUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A28 *((volatile unsigned int*)(0x42CF0EF0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A29 *((volatile unsigned int*)(0x42CF0EF4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A30 *((volatile unsigned int*)(0x42CF0EF8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A31 *((volatile unsigned int*)(0x42CF0EFCUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A32 *((volatile unsigned int*)(0x42CF0F00UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A33 *((volatile unsigned int*)(0x42CF0F04UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A34 *((volatile unsigned int*)(0x42CF0F08UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A35 *((volatile unsigned int*)(0x42CF0F0CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A36 *((volatile unsigned int*)(0x42CF0F10UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A37 *((volatile unsigned int*)(0x42CF0F14UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A38 *((volatile unsigned int*)(0x42CF0F18UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A39 *((volatile unsigned int*)(0x42CF0F1CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A40 *((volatile unsigned int*)(0x42CF0F20UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A41 *((volatile unsigned int*)(0x42CF0F24UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A42 *((volatile unsigned int*)(0x42CF0F28UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A43 *((volatile unsigned int*)(0x42CF0F2CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A44 *((volatile unsigned int*)(0x42CF0F30UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A45 *((volatile unsigned int*)(0x42CF0F34UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A46 *((volatile unsigned int*)(0x42CF0F38UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A47 *((volatile unsigned int*)(0x42CF0F3CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC0 *((volatile unsigned int*)(0x42CF0F60UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC1 *((volatile unsigned int*)(0x42CF0F64UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC2 *((volatile unsigned int*)(0x42CF0F68UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC3 *((volatile unsigned int*)(0x42CF0F6CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC4 *((volatile unsigned int*)(0x42CF0F70UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC5 *((volatile unsigned int*)(0x42CF0F74UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_SA *((volatile unsigned int*)(0x42CF0F78UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_AE *((volatile unsigned int*)(0x42CF0F7CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A0 *((volatile unsigned int*)(0x42CF0F80UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A1 *((volatile unsigned int*)(0x42CF0F84UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A2 *((volatile unsigned int*)(0x42CF0F88UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A3 *((volatile unsigned int*)(0x42CF0F8CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A4 *((volatile unsigned int*)(0x42CF0F90UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A5 *((volatile unsigned int*)(0x42CF0F94UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A6 *((volatile unsigned int*)(0x42CF0F98UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A7 *((volatile unsigned int*)(0x42CF0F9CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A8 *((volatile unsigned int*)(0x42CF0FA0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A9 *((volatile unsigned int*)(0x42CF0FA4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A10 *((volatile unsigned int*)(0x42CF0FA8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A11 *((volatile unsigned int*)(0x42CF0FACUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A12 *((volatile unsigned int*)(0x42CF0FB0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A13 *((volatile unsigned int*)(0x42CF0FB4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A14 *((volatile unsigned int*)(0x42CF0FB8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A15 *((volatile unsigned int*)(0x42CF0FBCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A16 *((volatile unsigned int*)(0x42CF0FC0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A17 *((volatile unsigned int*)(0x42CF0FC4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A18 *((volatile unsigned int*)(0x42CF0FC8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A19 *((volatile unsigned int*)(0x42CF0FCCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A20 *((volatile unsigned int*)(0x42CF0FD0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A21 *((volatile unsigned int*)(0x42CF0FD4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A22 *((volatile unsigned int*)(0x42CF0FD8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A23 *((volatile unsigned int*)(0x42CF0FDCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A24 *((volatile unsigned int*)(0x42CF0FE0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A25 *((volatile unsigned int*)(0x42CF0FE4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A26 *((volatile unsigned int*)(0x42CF0FE8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A27 *((volatile unsigned int*)(0x42CF0FECUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A28 *((volatile unsigned int*)(0x42CF0FF0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A29 *((volatile unsigned int*)(0x42CF0FF4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A30 *((volatile unsigned int*)(0x42CF0FF8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A31 *((volatile unsigned int*)(0x42CF0FFCUL)) +#define bFM3_ETHERNET_MAC1_BMR_SWR *((volatile unsigned int*)(0x42D00000UL)) +#define bFM3_ETHERNET_MAC1_BMR_DA *((volatile unsigned int*)(0x42D00004UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL0 *((volatile unsigned int*)(0x42D00008UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL1 *((volatile unsigned int*)(0x42D0000CUL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL2 *((volatile unsigned int*)(0x42D00010UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL3 *((volatile unsigned int*)(0x42D00014UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL4 *((volatile unsigned int*)(0x42D00018UL)) +#define bFM3_ETHERNET_MAC1_BMR_ATDS *((volatile unsigned int*)(0x42D0001CUL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL0 *((volatile unsigned int*)(0x42D00020UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL1 *((volatile unsigned int*)(0x42D00024UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL2 *((volatile unsigned int*)(0x42D00028UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL3 *((volatile unsigned int*)(0x42D0002CUL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL4 *((volatile unsigned int*)(0x42D00030UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL5 *((volatile unsigned int*)(0x42D00034UL)) +#define bFM3_ETHERNET_MAC1_BMR_PR0 *((volatile unsigned int*)(0x42D00038UL)) +#define bFM3_ETHERNET_MAC1_BMR_PR1 *((volatile unsigned int*)(0x42D0003CUL)) +#define bFM3_ETHERNET_MAC1_BMR_FB *((volatile unsigned int*)(0x42D00040UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL0 *((volatile unsigned int*)(0x42D00044UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL1 *((volatile unsigned int*)(0x42D00048UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL2 *((volatile unsigned int*)(0x42D0004CUL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL3 *((volatile unsigned int*)(0x42D00050UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL4 *((volatile unsigned int*)(0x42D00054UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL5 *((volatile unsigned int*)(0x42D00058UL)) +#define bFM3_ETHERNET_MAC1_BMR_USP *((volatile unsigned int*)(0x42D0005CUL)) +#define bFM3_ETHERNET_MAC1_BMR_8XPBL *((volatile unsigned int*)(0x42D00060UL)) +#define bFM3_ETHERNET_MAC1_BMR_AAL *((volatile unsigned int*)(0x42D00064UL)) +#define bFM3_ETHERNET_MAC1_BMR_MB *((volatile unsigned int*)(0x42D00068UL)) +#define bFM3_ETHERNET_MAC1_BMR_TXPR *((volatile unsigned int*)(0x42D0006CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD0 *((volatile unsigned int*)(0x42D00080UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD1 *((volatile unsigned int*)(0x42D00084UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD2 *((volatile unsigned int*)(0x42D00088UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD3 *((volatile unsigned int*)(0x42D0008CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD4 *((volatile unsigned int*)(0x42D00090UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD5 *((volatile unsigned int*)(0x42D00094UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD6 *((volatile unsigned int*)(0x42D00098UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD7 *((volatile unsigned int*)(0x42D0009CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD8 *((volatile unsigned int*)(0x42D000A0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD9 *((volatile unsigned int*)(0x42D000A4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD10 *((volatile unsigned int*)(0x42D000A8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD11 *((volatile unsigned int*)(0x42D000ACUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD12 *((volatile unsigned int*)(0x42D000B0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD13 *((volatile unsigned int*)(0x42D000B4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD14 *((volatile unsigned int*)(0x42D000B8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD15 *((volatile unsigned int*)(0x42D000BCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD16 *((volatile unsigned int*)(0x42D000C0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD17 *((volatile unsigned int*)(0x42D000C4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD18 *((volatile unsigned int*)(0x42D000C8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD19 *((volatile unsigned int*)(0x42D000CCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD20 *((volatile unsigned int*)(0x42D000D0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD21 *((volatile unsigned int*)(0x42D000D4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD22 *((volatile unsigned int*)(0x42D000D8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD23 *((volatile unsigned int*)(0x42D000DCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD24 *((volatile unsigned int*)(0x42D000E0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD25 *((volatile unsigned int*)(0x42D000E4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD26 *((volatile unsigned int*)(0x42D000E8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD27 *((volatile unsigned int*)(0x42D000ECUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD28 *((volatile unsigned int*)(0x42D000F0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD29 *((volatile unsigned int*)(0x42D000F4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD30 *((volatile unsigned int*)(0x42D000F8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD31 *((volatile unsigned int*)(0x42D000FCUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD0 *((volatile unsigned int*)(0x42D00100UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD1 *((volatile unsigned int*)(0x42D00104UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD2 *((volatile unsigned int*)(0x42D00108UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD3 *((volatile unsigned int*)(0x42D0010CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD4 *((volatile unsigned int*)(0x42D00110UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD5 *((volatile unsigned int*)(0x42D00114UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD6 *((volatile unsigned int*)(0x42D00118UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD7 *((volatile unsigned int*)(0x42D0011CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD8 *((volatile unsigned int*)(0x42D00120UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD9 *((volatile unsigned int*)(0x42D00124UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD10 *((volatile unsigned int*)(0x42D00128UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD11 *((volatile unsigned int*)(0x42D0012CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD12 *((volatile unsigned int*)(0x42D00130UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD13 *((volatile unsigned int*)(0x42D00134UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD14 *((volatile unsigned int*)(0x42D00138UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD15 *((volatile unsigned int*)(0x42D0013CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD16 *((volatile unsigned int*)(0x42D00140UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD17 *((volatile unsigned int*)(0x42D00144UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD18 *((volatile unsigned int*)(0x42D00148UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD19 *((volatile unsigned int*)(0x42D0014CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD20 *((volatile unsigned int*)(0x42D00150UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD21 *((volatile unsigned int*)(0x42D00154UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD22 *((volatile unsigned int*)(0x42D00158UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD23 *((volatile unsigned int*)(0x42D0015CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD24 *((volatile unsigned int*)(0x42D00160UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD25 *((volatile unsigned int*)(0x42D00164UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD26 *((volatile unsigned int*)(0x42D00168UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD27 *((volatile unsigned int*)(0x42D0016CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD28 *((volatile unsigned int*)(0x42D00170UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD29 *((volatile unsigned int*)(0x42D00174UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD30 *((volatile unsigned int*)(0x42D00178UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD31 *((volatile unsigned int*)(0x42D0017CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL2 *((volatile unsigned int*)(0x42D00188UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL3 *((volatile unsigned int*)(0x42D0018CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL4 *((volatile unsigned int*)(0x42D00190UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL5 *((volatile unsigned int*)(0x42D00194UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL6 *((volatile unsigned int*)(0x42D00198UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL7 *((volatile unsigned int*)(0x42D0019CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL8 *((volatile unsigned int*)(0x42D001A0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL9 *((volatile unsigned int*)(0x42D001A4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL10 *((volatile unsigned int*)(0x42D001A8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL11 *((volatile unsigned int*)(0x42D001ACUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL12 *((volatile unsigned int*)(0x42D001B0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL13 *((volatile unsigned int*)(0x42D001B4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL14 *((volatile unsigned int*)(0x42D001B8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL15 *((volatile unsigned int*)(0x42D001BCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL16 *((volatile unsigned int*)(0x42D001C0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL17 *((volatile unsigned int*)(0x42D001C4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL18 *((volatile unsigned int*)(0x42D001C8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL19 *((volatile unsigned int*)(0x42D001CCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL20 *((volatile unsigned int*)(0x42D001D0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL21 *((volatile unsigned int*)(0x42D001D4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL22 *((volatile unsigned int*)(0x42D001D8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL23 *((volatile unsigned int*)(0x42D001DCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL24 *((volatile unsigned int*)(0x42D001E0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL25 *((volatile unsigned int*)(0x42D001E4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL26 *((volatile unsigned int*)(0x42D001E8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL27 *((volatile unsigned int*)(0x42D001ECUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL28 *((volatile unsigned int*)(0x42D001F0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL29 *((volatile unsigned int*)(0x42D001F4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL30 *((volatile unsigned int*)(0x42D001F8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL31 *((volatile unsigned int*)(0x42D001FCUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL2 *((volatile unsigned int*)(0x42D00208UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL3 *((volatile unsigned int*)(0x42D0020CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL4 *((volatile unsigned int*)(0x42D00210UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL5 *((volatile unsigned int*)(0x42D00214UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL6 *((volatile unsigned int*)(0x42D00218UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL7 *((volatile unsigned int*)(0x42D0021CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL8 *((volatile unsigned int*)(0x42D00220UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL9 *((volatile unsigned int*)(0x42D00224UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL10 *((volatile unsigned int*)(0x42D00228UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL11 *((volatile unsigned int*)(0x42D0022CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL12 *((volatile unsigned int*)(0x42D00230UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL13 *((volatile unsigned int*)(0x42D00234UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL14 *((volatile unsigned int*)(0x42D00238UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL15 *((volatile unsigned int*)(0x42D0023CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL16 *((volatile unsigned int*)(0x42D00240UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL17 *((volatile unsigned int*)(0x42D00244UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL18 *((volatile unsigned int*)(0x42D00248UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL19 *((volatile unsigned int*)(0x42D0024CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL20 *((volatile unsigned int*)(0x42D00250UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL21 *((volatile unsigned int*)(0x42D00254UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL22 *((volatile unsigned int*)(0x42D00258UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL23 *((volatile unsigned int*)(0x42D0025CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL24 *((volatile unsigned int*)(0x42D00260UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL25 *((volatile unsigned int*)(0x42D00264UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL26 *((volatile unsigned int*)(0x42D00268UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL27 *((volatile unsigned int*)(0x42D0026CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL28 *((volatile unsigned int*)(0x42D00270UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL29 *((volatile unsigned int*)(0x42D00274UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL30 *((volatile unsigned int*)(0x42D00278UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL31 *((volatile unsigned int*)(0x42D0027CUL)) +#define bFM3_ETHERNET_MAC1_SR_TI *((volatile unsigned int*)(0x42D00280UL)) +#define bFM3_ETHERNET_MAC1_SR_TPS *((volatile unsigned int*)(0x42D00284UL)) +#define bFM3_ETHERNET_MAC1_SR_TU *((volatile unsigned int*)(0x42D00288UL)) +#define bFM3_ETHERNET_MAC1_SR_TJT *((volatile unsigned int*)(0x42D0028CUL)) +#define bFM3_ETHERNET_MAC1_SR_OVF *((volatile unsigned int*)(0x42D00290UL)) +#define bFM3_ETHERNET_MAC1_SR_UNF *((volatile unsigned int*)(0x42D00294UL)) +#define bFM3_ETHERNET_MAC1_SR_RI *((volatile unsigned int*)(0x42D00298UL)) +#define bFM3_ETHERNET_MAC1_SR_RU *((volatile unsigned int*)(0x42D0029CUL)) +#define bFM3_ETHERNET_MAC1_SR_RPS *((volatile unsigned int*)(0x42D002A0UL)) +#define bFM3_ETHERNET_MAC1_SR_RWT *((volatile unsigned int*)(0x42D002A4UL)) +#define bFM3_ETHERNET_MAC1_SR_ETI *((volatile unsigned int*)(0x42D002A8UL)) +#define bFM3_ETHERNET_MAC1_SR_FBI *((volatile unsigned int*)(0x42D002B4UL)) +#define bFM3_ETHERNET_MAC1_SR_ERI *((volatile unsigned int*)(0x42D002B8UL)) +#define bFM3_ETHERNET_MAC1_SR_AIS *((volatile unsigned int*)(0x42D002BCUL)) +#define bFM3_ETHERNET_MAC1_SR_NIS *((volatile unsigned int*)(0x42D002C0UL)) +#define bFM3_ETHERNET_MAC1_SR_RS0 *((volatile unsigned int*)(0x42D002C4UL)) +#define bFM3_ETHERNET_MAC1_SR_RS1 *((volatile unsigned int*)(0x42D002C8UL)) +#define bFM3_ETHERNET_MAC1_SR_RS2 *((volatile unsigned int*)(0x42D002CCUL)) +#define bFM3_ETHERNET_MAC1_SR_TS0 *((volatile unsigned int*)(0x42D002D0UL)) +#define bFM3_ETHERNET_MAC1_SR_TS1 *((volatile unsigned int*)(0x42D002D4UL)) +#define bFM3_ETHERNET_MAC1_SR_TS2 *((volatile unsigned int*)(0x42D002D8UL)) +#define bFM3_ETHERNET_MAC1_SR_EB0 *((volatile unsigned int*)(0x42D002DCUL)) +#define bFM3_ETHERNET_MAC1_SR_EB1 *((volatile unsigned int*)(0x42D002E0UL)) +#define bFM3_ETHERNET_MAC1_SR_EB2 *((volatile unsigned int*)(0x42D002E4UL)) +#define bFM3_ETHERNET_MAC1_SR_GLI *((volatile unsigned int*)(0x42D002E8UL)) +#define bFM3_ETHERNET_MAC1_SR_GMI *((volatile unsigned int*)(0x42D002ECUL)) +#define bFM3_ETHERNET_MAC1_SR_GPI *((volatile unsigned int*)(0x42D002F0UL)) +#define bFM3_ETHERNET_MAC1_SR_TTI *((volatile unsigned int*)(0x42D002F4UL)) +#define bFM3_ETHERNET_MAC1_SR_GLPII *((volatile unsigned int*)(0x42D002F8UL)) +#define bFM3_ETHERNET_MAC1_OMR_SR *((volatile unsigned int*)(0x42D00304UL)) +#define bFM3_ETHERNET_MAC1_OMR_OSF *((volatile unsigned int*)(0x42D00308UL)) +#define bFM3_ETHERNET_MAC1_OMR_RTC0 *((volatile unsigned int*)(0x42D0030CUL)) +#define bFM3_ETHERNET_MAC1_OMR_RTC1 *((volatile unsigned int*)(0x42D00310UL)) +#define bFM3_ETHERNET_MAC1_OMR_FUF *((volatile unsigned int*)(0x42D00318UL)) +#define bFM3_ETHERNET_MAC1_OMR_FEF *((volatile unsigned int*)(0x42D0031CUL)) +#define bFM3_ETHERNET_MAC1_OMR_ST *((volatile unsigned int*)(0x42D00334UL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC0 *((volatile unsigned int*)(0x42D00338UL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC1 *((volatile unsigned int*)(0x42D0033CUL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC2 *((volatile unsigned int*)(0x42D00340UL)) +#define bFM3_ETHERNET_MAC1_OMR_FTF *((volatile unsigned int*)(0x42D00350UL)) +#define bFM3_ETHERNET_MAC1_OMR_TSF *((volatile unsigned int*)(0x42D00354UL)) +#define bFM3_ETHERNET_MAC1_OMR_DFF *((volatile unsigned int*)(0x42D00360UL)) +#define bFM3_ETHERNET_MAC1_OMR_RSF *((volatile unsigned int*)(0x42D00364UL)) +#define bFM3_ETHERNET_MAC1_OMR_DT *((volatile unsigned int*)(0x42D00368UL)) +#define bFM3_ETHERNET_MAC1_IER_TIE *((volatile unsigned int*)(0x42D00380UL)) +#define bFM3_ETHERNET_MAC1_IER_TSE *((volatile unsigned int*)(0x42D00384UL)) +#define bFM3_ETHERNET_MAC1_IER_TUE *((volatile unsigned int*)(0x42D00388UL)) +#define bFM3_ETHERNET_MAC1_IER_TJE *((volatile unsigned int*)(0x42D0038CUL)) +#define bFM3_ETHERNET_MAC1_IER_OVE *((volatile unsigned int*)(0x42D00390UL)) +#define bFM3_ETHERNET_MAC1_IER_UNE *((volatile unsigned int*)(0x42D00394UL)) +#define bFM3_ETHERNET_MAC1_IER_RIE *((volatile unsigned int*)(0x42D00398UL)) +#define bFM3_ETHERNET_MAC1_IER_RUE *((volatile unsigned int*)(0x42D0039CUL)) +#define bFM3_ETHERNET_MAC1_IER_RSE *((volatile unsigned int*)(0x42D003A0UL)) +#define bFM3_ETHERNET_MAC1_IER_RWE *((volatile unsigned int*)(0x42D003A4UL)) +#define bFM3_ETHERNET_MAC1_IER_ETE *((volatile unsigned int*)(0x42D003A8UL)) +#define bFM3_ETHERNET_MAC1_IER_FBE *((volatile unsigned int*)(0x42D003B4UL)) +#define bFM3_ETHERNET_MAC1_IER_ERE *((volatile unsigned int*)(0x42D003B8UL)) +#define bFM3_ETHERNET_MAC1_IER_AIE *((volatile unsigned int*)(0x42D003BCUL)) +#define bFM3_ETHERNET_MAC1_IER_NIE *((volatile unsigned int*)(0x42D003C0UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42D00400UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42D00404UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42D00408UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42D0040CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42D00410UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42D00414UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42D00418UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42D0041CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42D00420UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42D00424UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42D00428UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42D0042CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42D00430UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42D00434UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42D00438UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42D0043CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH *((volatile unsigned int*)(0x42D00440UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42D00444UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42D00448UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42D0044CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42D00450UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42D00454UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42D00458UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42D0045CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42D00460UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42D00464UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42D00468UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42D0046CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF *((volatile unsigned int*)(0x42D00470UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0 *((volatile unsigned int*)(0x42D00480UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1 *((volatile unsigned int*)(0x42D00484UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2 *((volatile unsigned int*)(0x42D00488UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3 *((volatile unsigned int*)(0x42D0048CUL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4 *((volatile unsigned int*)(0x42D00490UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5 *((volatile unsigned int*)(0x42D00494UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6 *((volatile unsigned int*)(0x42D00498UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7 *((volatile unsigned int*)(0x42D0049CUL)) +#define bFM3_ETHERNET_MAC1_AHBSR_AHBS *((volatile unsigned int*)(0x42D00580UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42D00900UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42D00904UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42D00908UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42D0090CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42D00910UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42D00914UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42D00918UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42D0091CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42D00920UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42D00924UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42D00928UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42D0092CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42D00930UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42D00934UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42D00938UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42D0093CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42D00940UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42D00944UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42D00948UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42D0094CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42D00950UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42D00954UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42D00958UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42D0095CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42D00960UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42D00964UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42D00968UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42D0096CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42D00970UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42D00974UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42D00978UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42D0097CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42D00980UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42D00984UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42D00988UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42D0098CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42D00990UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42D00994UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42D00998UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42D0099CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42D009A0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42D009A4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42D009A8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42D009ACUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42D009B0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42D009B4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42D009B8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42D009BCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42D009C0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42D009C4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42D009C8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42D009CCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42D009D0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42D009D4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42D009D8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42D009DCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42D009E0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42D009E4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42D009E8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42D009ECUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42D009F0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42D009F4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42D009F8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42D009FCUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42D00A00UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42D00A04UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42D00A08UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42D00A0CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42D00A10UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42D00A14UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42D00A18UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42D00A1CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42D00A20UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42D00A24UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42D00A28UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42D00A2CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42D00A30UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42D00A34UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42D00A38UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42D00A3CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42D00A40UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42D00A44UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42D00A48UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42D00A4CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42D00A50UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42D00A54UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42D00A58UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42D00A5CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42D00A60UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42D00A64UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42D00A68UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42D00A6CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42D00A70UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42D00A74UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42D00A78UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42D00A7CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42D00A80UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42D00A84UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42D00A88UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42D00A8CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42D00A90UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42D00A94UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42D00A98UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42D00A9CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42D00AA0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42D00AA4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42D00AA8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42D00AACUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42D00AB0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42D00AB4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42D00AB8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42D00ABCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42D00AC0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42D00AC4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42D00AC8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42D00ACCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42D00AD0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42D00AD4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42D00AD8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42D00ADCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42D00AE0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42D00AE4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42D00AE8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42D00AECUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42D00AF0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42D00AF4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42D00AF8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42D00AFCUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9BF618S_H_ */ + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h new file mode 100644 index 0000000000..b75c77ba6b --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h @@ -0,0 +1,29338 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9B610T */ +/* Version V1.2 */ +/* Date 2012-02-23 */ +/* */ +/************************************************************************/ + +/****************************************************************************** + * History + * Date Ver Description + * 2011-08-04 1.0 Initial + * 2011-10-04 1.1 Added FBFCR register + * Removed the following bits from the bit fields + * - TMD bits of WFSAxx register in MFT + * - MD bits of PPGCx register in PPG + * - FMD bits of TMCR register in BT + * - MD bits of SMR register in MFS + * 2012-02-23 1.2 Added the following bits to the bit fields + * - TMD bits of WFSAxx register in MFT + * - MD bits of PPGCx register in PPG + * - FMD bits of TMCR register in BT + * - MD bits of SMR register in MFS + * + ******************************************************************************/ + +#ifndef _MB9B610T_H_ +#define _MB9B610T_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_31_IRQn = 5, /* External Interrupt Request ch.8 to ch.31 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM0_7_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + ETHER_MAC0_IRQn = 32, /* Ethernet MAC ch.0 */ + ETHER_MAC1_IRQn = 33, /* Ethernet MAC ch.1 */ + USB0F_IRQn = 34, /* USB Function ch.0 */ + USB0F_USB0H_IRQn = 35, /* USB Function ch.0 / USB Host ch.0 */ + USB1F_IRQn = 36, /* USB Function ch.1 */ + USB1F_USB1H_IRQn = 37, /* USB Function ch.1 / USB Host ch.1 */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45, /* DMAC ch.7 */ + BTIM8_15_IRQn = 46 /* Base Timer ch.8 to ch.15 */ + /* Reserved = 47 */ +} IRQn_Type; + + +#include +#include "system_mb9bf61x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Peripheral register bit fields + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash_IF_MODULE register bit fields */ +typedef struct stc_flash_if_faszr_field +{ + __IO uint32_t ASZ0 : 1; + __IO uint32_t ASZ1 : 1; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + __IO uint32_t RWT0 : 1; + __IO uint32_t RWT1 : 1; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY : 1; + __IO uint32_t HNG : 1; + __IO uint32_t EER : 1; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_fbfcr_field +{ + __IO uint32_t BE : 1; + __IO uint32_t BS : 1; +} stc_flash_if_fbfcr_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + __IO uint32_t TRMM0 : 1; + __IO uint32_t TRMM1 : 1; + __IO uint32_t TRMM2 : 1; + __IO uint32_t TRMM3 : 1; + __IO uint32_t TRMM4 : 1; + __IO uint32_t TRMM5 : 1; + __IO uint32_t TRMM6 : 1; + __IO uint32_t TRMM7 : 1; + __IO uint32_t TRMM8 : 1; + __IO uint32_t TRMM9 : 1; +} stc_flash_if_crtrmm_field_t; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock_Reset_MODULE register bit fields */ +typedef struct stc_crg_scm_ctl_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MOSCE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SOSCE : 1; + __IO uint8_t PLLE : 1; + __IO uint8_t RCS0 : 1; + __IO uint8_t RCS1 : 1; + __IO uint8_t RCS2 : 1; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + uint8_t RESERVED1 : 1; + __IO uint8_t MORDY : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t SORDY : 1; + __IO uint8_t PLRDY : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t RCM2 : 1; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint16_t PONR : 1; + __IO uint16_t INITX : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SWDT : 1; + __IO uint16_t HWDT : 1; + __IO uint16_t CSVR : 1; + __IO uint16_t FCSR : 1; + __IO uint16_t SRST : 1; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + __IO uint8_t BSR0 : 1; + __IO uint8_t BSR1 : 1; + __IO uint8_t BSR2 : 1; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + __IO uint8_t APBC00 : 1; + __IO uint8_t APBC01 : 1; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + __IO uint8_t APBC10 : 1; + __IO uint8_t APBC11 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC1RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC1EN : 1; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + __IO uint8_t APBC20 : 1; + __IO uint8_t APBC21 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t APBC2RST : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t APBC2EN : 1; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + __IO uint8_t SWDS0 : 1; + __IO uint8_t SWDS1 : 1; + uint8_t RESERVED1 : 5; + __IO uint8_t TESTB : 1; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + __IO uint8_t TTC0 : 1; + __IO uint8_t TTC1 : 1; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + __IO uint8_t MOWT0 : 1; + __IO uint8_t MOWT1 : 1; + __IO uint8_t MOWT2 : 1; + __IO uint8_t MOWT3 : 1; + __IO uint8_t SOWT0 : 1; + __IO uint8_t SOWT1 : 1; + __IO uint8_t SOWT2 : 1; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + __IO uint8_t POWT0 : 1; + __IO uint8_t POWT1 : 1; + __IO uint8_t POWT2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t PINC : 1; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + __IO uint8_t PLLM0 : 1; + __IO uint8_t PLLM1 : 1; + __IO uint8_t PLLM2 : 1; + __IO uint8_t PLLM3 : 1; + __IO uint8_t PLLK0 : 1; + __IO uint8_t PLLK1 : 1; + __IO uint8_t PLLK2 : 1; + __IO uint8_t PLLK3 : 1; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + __IO uint8_t PLLN0 : 1; + __IO uint8_t PLLN1 : 1; + __IO uint8_t PLLN2 : 1; + __IO uint8_t PLLN3 : 1; + __IO uint8_t PLLN4 : 1; + __IO uint8_t PLLN5 : 1; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + __IO uint16_t MCSVE : 1; + __IO uint16_t SCSVE : 1; + uint16_t RESERVED1 : 6; + __IO uint16_t FCSDE : 1; + __IO uint16_t FCSRE : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t FCD0 : 1; + __IO uint16_t FCD1 : 1; + __IO uint16_t FCD2 : 1; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint8_t MCMF : 1; + __IO uint8_t SCMF : 1; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + uint8_t RESERVED1 : 5; + __IO uint8_t DPSWBE : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t DPHWBE : 1; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint8_t MCSE : 1; + __IO uint8_t SCSE : 1; + __IO uint8_t PCSE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSE : 1; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint8_t MCSI : 1; + __IO uint8_t SCSI : 1; + __IO uint8_t PCSI : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSI : 1; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint8_t MCSC : 1; + __IO uint8_t SCSC : 1; + __IO uint8_t PCSC : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t FCSC : 1; +} stc_crg_int_clr_field_t; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* HWWDT_MODULE register bit fields */ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint8_t RIS : 1; +} stc_hwwdt_wdg_ris_field_t; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* SWWDT_MODULE register bit fields */ +typedef struct stc_swwdt_wdogcontrol_field +{ + __IO uint8_t INTEN : 1; + __IO uint8_t RESEN : 1; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint8_t RIS : 1; +} stc_swwdt_wdogris_field_t; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* DTIM_MODULE register bit fields */ +typedef struct stc_dtim_timer1control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer1control_field_t; + +typedef struct stc_dtim_timer1ris_field +{ + __IO uint32_t TIMER1RIS : 1; +} stc_dtim_timer1ris_field_t; + +typedef struct stc_dtim_timer1mis_field +{ + __IO uint32_t TIMER1MIS : 1; +} stc_dtim_timer1mis_field_t; + +typedef struct stc_dtim_timer2control_field +{ + __IO uint32_t ONESHOT : 1; + __IO uint32_t TIMERSIZE : 1; + __IO uint32_t TIMERPRE0 : 1; + __IO uint32_t TIMERPRE1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t INTENABLE : 1; + __IO uint32_t TIMERMODE : 1; + __IO uint32_t TIMEREN : 1; +} stc_dtim_timer2control_field_t; + +typedef struct stc_dtim_timer2ris_field +{ + __IO uint32_t TIMER2RIS : 1; +} stc_dtim_timer2ris_field_t; + +typedef struct stc_dtim_timer2mis_field +{ + __IO uint32_t TIMER2MIS : 1; +} stc_dtim_timer2mis_field_t; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* MFT_FRT_MODULE register bit fields */ +typedef struct stc_mft_frt_tcsa0_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsb0_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb0_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsb1_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb1_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + __IO uint16_t CLK0 : 1; + __IO uint16_t CLK1 : 1; + __IO uint16_t CLK2 : 1; + __IO uint16_t CLK3 : 1; + __IO uint16_t SCLR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BFE : 1; + __IO uint16_t ICRE : 1; + __IO uint16_t ICLR : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t IRQZE : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKE : 1; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsb2_field +{ + __IO uint16_t AD0E : 1; + __IO uint16_t AD1E : 1; + __IO uint16_t AD2E : 1; +} stc_mft_frt_tcsb2_field_t; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* MFT_OCU_MODULE register bit fields */ +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 : 1; + __IO uint8_t CST1 : 1; + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t IOE0 : 1; + __IO uint8_t IOE1 : 1; + __IO uint8_t IOP0 : 1; + __IO uint8_t IOP1 : 1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 : 1; + __IO uint8_t OTD1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST2 : 1; + __IO uint8_t CST3 : 1; + __IO uint8_t BDIS2 : 1; + __IO uint8_t BDIS3 : 1; + __IO uint8_t IOE2 : 1; + __IO uint8_t IOE3 : 1; + __IO uint8_t IOP2 : 1; + __IO uint8_t IOP3 : 1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD2 : 1; + __IO uint8_t OTD3 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS2 : 1; + __IO uint8_t BTS3 : 1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST4 : 1; + __IO uint8_t CST5 : 1; + __IO uint8_t BDIS4 : 1; + __IO uint8_t BDIS5 : 1; + __IO uint8_t IOE4 : 1; + __IO uint8_t IOE5 : 1; + __IO uint8_t IOP4 : 1; + __IO uint8_t IOP5 : 1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD4 : 1; + __IO uint8_t OTD5 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CMOD : 1; + __IO uint8_t BTS4 : 1; + __IO uint8_t BTS5 : 1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 : 1; + __IO uint8_t MOD1 : 1; + __IO uint8_t MOD2 : 1; + __IO uint8_t MOD3 : 1; + __IO uint8_t MOD4 : 1; + __IO uint8_t MOD5 : 1; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + __IO uint8_t FSO00 : 1; + __IO uint8_t FSO01 : 1; + __IO uint8_t FSO02 : 1; + __IO uint8_t FSO03 : 1; + __IO uint8_t FSO10 : 1; + __IO uint8_t FSO11 : 1; + __IO uint8_t FSO12 : 1; + __IO uint8_t FSO13 : 1; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + __IO uint8_t FSO20 : 1; + __IO uint8_t FSO21 : 1; + __IO uint8_t FSO22 : 1; + __IO uint8_t FSO23 : 1; + __IO uint8_t FSO30 : 1; + __IO uint8_t FSO31 : 1; + __IO uint8_t FSO32 : 1; + __IO uint8_t FSO33 : 1; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + __IO uint8_t FSO40 : 1; + __IO uint8_t FSO41 : 1; + __IO uint8_t FSO42 : 1; + __IO uint8_t FSO43 : 1; + __IO uint8_t FSO50 : 1; + __IO uint8_t FSO51 : 1; + __IO uint8_t FSO52 : 1; + __IO uint8_t FSO53 : 1; +} stc_mft_ocu_ocfs54_field_t; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* MFT_WFG_MODULE register bit fields */ +typedef struct stc_mft_wfg_wfsa10_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + __IO uint16_t DCK0 : 1; + __IO uint16_t DCK1 : 1; + __IO uint16_t DCK2 : 1; + __IO uint16_t TMD : 3; + __IO uint16_t GTEN0 : 1; + __IO uint16_t GTEN1 : 1; + __IO uint16_t PSEL0 : 1; + __IO uint16_t PSEL1 : 1; + __IO uint16_t PGEN0 : 1; + __IO uint16_t PGEN1 : 1; + __IO uint16_t DMOD : 1; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIF : 1; + __IO uint16_t DTIC : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t TMIF10 : 1; + __IO uint16_t TMIC10 : 1; + __IO uint16_t TMIE10 : 1; + __IO uint16_t TMIS10 : 1; + __IO uint16_t TMIF32 : 1; + __IO uint16_t TMIC32 : 1; + __IO uint16_t TMIE32 : 1; + __IO uint16_t TMIS32 : 1; + __IO uint16_t TMIF54 : 1; + __IO uint16_t TMIC54 : 1; + __IO uint16_t TMIE54 : 1; + __IO uint16_t TMIS54 : 1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + __IO uint16_t DTIE : 1; + __IO uint16_t NWS0 : 1; + __IO uint16_t NWS1 : 1; + __IO uint16_t NWS2 : 1; + __IO uint16_t SDTI : 1; +} stc_mft_wfg_nzcl_field_t; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* MFT_ICU_MODULE register bit fields */ +typedef struct stc_mft_icu_icfs10_field +{ + __IO uint8_t FSI00 : 1; + __IO uint8_t FSI01 : 1; + __IO uint8_t FSI02 : 1; + __IO uint8_t FSI03 : 1; + __IO uint8_t FSI10 : 1; + __IO uint8_t FSI11 : 1; + __IO uint8_t FSI12 : 1; + __IO uint8_t FSI13 : 1; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + __IO uint8_t FSI20 : 1; + __IO uint8_t FSI21 : 1; + __IO uint8_t FSI22 : 1; + __IO uint8_t FSI23 : 1; + __IO uint8_t FSI30 : 1; + __IO uint8_t FSI31 : 1; + __IO uint8_t FSI32 : 1; + __IO uint8_t FSI33 : 1; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + __IO uint8_t EG00 : 1; + __IO uint8_t EG01 : 1; + __IO uint8_t EG10 : 1; + __IO uint8_t EG11 : 1; + __IO uint8_t ICE0 : 1; + __IO uint8_t ICE1 : 1; + __IO uint8_t ICP0 : 1; + __IO uint8_t ICP1 : 1; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 : 1; + __IO uint8_t IEI1 : 1; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + __IO uint8_t EG20 : 1; + __IO uint8_t EG21 : 1; + __IO uint8_t EG30 : 1; + __IO uint8_t EG31 : 1; + __IO uint8_t ICE2 : 1; + __IO uint8_t ICE3 : 1; + __IO uint8_t ICP2 : 1; + __IO uint8_t ICP3 : 1; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI2 : 1; + __IO uint8_t IEI3 : 1; +} stc_mft_icu_icsb32_field_t; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* MFT_ADCMP_MODULE register bit fields */ +typedef struct stc_mft_adcmp_acsb_field +{ + __IO uint8_t BDIS0 : 1; + __IO uint8_t BDIS1 : 1; + __IO uint8_t BDIS2 : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BTS0 : 1; + __IO uint8_t BTS1 : 1; + __IO uint8_t BTS2 : 1; +} stc_mft_adcmp_acsb_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + __IO uint16_t CE00 : 1; + __IO uint16_t CE01 : 1; + __IO uint16_t CE10 : 1; + __IO uint16_t CE11 : 1; + __IO uint16_t CE20 : 1; + __IO uint16_t CE21 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SEL00 : 1; + __IO uint16_t SEL01 : 1; + __IO uint16_t SEL10 : 1; + __IO uint16_t SEL11 : 1; + __IO uint16_t SEL20 : 1; + __IO uint16_t SEL21 : 1; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_atsa_field +{ + __IO uint16_t AD0S0 : 1; + __IO uint16_t AD0S1 : 1; + __IO uint16_t AD1S0 : 1; + __IO uint16_t AD1S1 : 1; + __IO uint16_t AD2S0 : 1; + __IO uint16_t AD2S1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t AD0P0 : 1; + __IO uint16_t AD0P1 : 1; + __IO uint16_t AD1P0 : 1; + __IO uint16_t AD1P1 : 1; + __IO uint16_t AD2P0 : 1; + __IO uint16_t AD2P1 : 1; +} stc_mft_adcmp_atsa_field_t; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* MFT_PPG_MODULE register bit fields */ +typedef struct stc_mft_ppg_ttcr0_field +{ + __IO uint8_t STR0 : 1; + __IO uint8_t MONI0 : 1; + __IO uint8_t CS00 : 1; + __IO uint8_t CS01 : 1; + __IO uint8_t TRG0O : 1; + __IO uint8_t TRG2O : 1; + __IO uint8_t TRG4O : 1; + __IO uint8_t TRG6O : 1; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + __IO uint8_t STR1 : 1; + __IO uint8_t MONI1 : 1; + __IO uint8_t CS10 : 1; + __IO uint8_t CS11 : 1; + __IO uint8_t TRG1O : 1; + __IO uint8_t TRG3O : 1; + __IO uint8_t TRG5O : 1; + __IO uint8_t TRG7O : 1; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_ttcr2_field +{ + __IO uint8_t STR2 : 1; + __IO uint8_t MONI2 : 1; + __IO uint8_t CS20 : 1; + __IO uint8_t CS21 : 1; + __IO uint8_t TRG16O : 1; + __IO uint8_t TRG18O : 1; + __IO uint8_t TRG20O : 1; + __IO uint8_t TRG22O : 1; +} stc_mft_ppg_ttcr2_field_t; + +typedef struct stc_mft_ppg_trg_field +{ + __IO uint16_t PEN00 : 1; + __IO uint16_t PEN01 : 1; + __IO uint16_t PEN02 : 1; + __IO uint16_t PEN03 : 1; + __IO uint16_t PEN04 : 1; + __IO uint16_t PEN05 : 1; + __IO uint16_t PEN06 : 1; + __IO uint16_t PEN07 : 1; + __IO uint16_t PEN08 : 1; + __IO uint16_t PEN09 : 1; + __IO uint16_t PEN10 : 1; + __IO uint16_t PEN11 : 1; + __IO uint16_t PEN12 : 1; + __IO uint16_t PEN13 : 1; + __IO uint16_t PEN14 : 1; + __IO uint16_t PEN15 : 1; +} stc_mft_ppg_trg_field_t; + +typedef struct stc_mft_ppg_trg1_field +{ + __IO uint16_t PEN16 : 1; + __IO uint16_t PEN17 : 1; + __IO uint16_t PEN18 : 1; + __IO uint16_t PEN19 : 1; + __IO uint16_t PEN20 : 1; + __IO uint16_t PEN21 : 1; + __IO uint16_t PEN22 : 1; + __IO uint16_t PEN23 : 1; +} stc_mft_ppg_trg1_field_t; + +typedef struct stc_mft_ppg_revc_field +{ + __IO uint16_t REV00 : 1; + __IO uint16_t REV01 : 1; + __IO uint16_t REV02 : 1; + __IO uint16_t REV03 : 1; + __IO uint16_t REV04 : 1; + __IO uint16_t REV05 : 1; + __IO uint16_t REV06 : 1; + __IO uint16_t REV07 : 1; + __IO uint16_t REV08 : 1; + __IO uint16_t REV09 : 1; + __IO uint16_t REV10 : 1; + __IO uint16_t REV11 : 1; + __IO uint16_t REV12 : 1; + __IO uint16_t REV13 : 1; + __IO uint16_t REV14 : 1; + __IO uint16_t REV15 : 1; +} stc_mft_ppg_revc_field_t; + +typedef struct stc_mft_ppg_revc1_field +{ + __IO uint16_t REV16 : 1; + __IO uint16_t REV17 : 1; + __IO uint16_t REV18 : 1; + __IO uint16_t REV19 : 1; + __IO uint16_t REV20 : 1; + __IO uint16_t REV21 : 1; + __IO uint16_t REV22 : 1; + __IO uint16_t REV23 : 1; +} stc_mft_ppg_revc1_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 : 1; + __IO uint8_t STRG0 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE2 : 1; + __IO uint8_t STRG2 : 1; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 : 1; + __IO uint8_t STRG4 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE6 : 1; + __IO uint8_t STRG6 : 1; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 : 1; + __IO uint8_t STRG8 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE10 : 1; + __IO uint8_t STRG10 : 1; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 : 1; + __IO uint8_t STRG12 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE14 : 1; + __IO uint8_t STRG14 : 1; +} stc_mft_ppg_gatec12_field_t; + +typedef struct stc_mft_ppg_ppgc17_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc17_field_t; + +typedef struct stc_mft_ppg_ppgc16_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc16_field_t; + +typedef struct stc_mft_ppg_ppgc19_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc19_field_t; + +typedef struct stc_mft_ppg_ppgc18_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc18_field_t; + +typedef struct stc_mft_ppg_gatec16_field +{ + __IO uint8_t EDGE16 : 1; + __IO uint8_t STRG16 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE18 : 1; + __IO uint8_t STRG18 : 1; +} stc_mft_ppg_gatec16_field_t; + +typedef struct stc_mft_ppg_ppgc21_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc21_field_t; + +typedef struct stc_mft_ppg_ppgc20_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc20_field_t; + +typedef struct stc_mft_ppg_ppgc23_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc23_field_t; + +typedef struct stc_mft_ppg_ppgc22_field +{ + __IO uint8_t TTRG : 1; + __IO uint8_t MD : 2; + __IO uint8_t PCS0 : 1; + __IO uint8_t PCS1 : 1; + __IO uint8_t INTM : 1; + __IO uint8_t PUF : 1; + __IO uint8_t PIE : 1; +} stc_mft_ppg_ppgc22_field_t; + +typedef struct stc_mft_ppg_gatec20_field +{ + __IO uint8_t EDGE20 : 1; + __IO uint8_t STRG20 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t EDGE22 : 1; + __IO uint8_t STRG22 : 1; +} stc_mft_ppg_gatec20_field_t; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* BT_PPG_MODULE register bit fields */ +typedef struct stc_bt_ppg_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD : 3; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_ppg_tmcr2_field_t; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* BT_PWM_MODULE register bit fields */ +typedef struct stc_bt_pwm_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD : 3; + uint16_t RESERVED1 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t PMSK : 1; + __IO uint16_t RTGEN : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR : 1; + __IO uint8_t DTIR : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t UDIE : 1; + __IO uint8_t DTIE : 1; + __IO uint8_t TGIE : 1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwm_tmcr2_field_t; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* BT_RT_MODULE register bit fields */ +typedef struct stc_bt_rt_tmcr_field +{ + __IO uint16_t STRG : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + __IO uint16_t OSEL : 1; + __IO uint16_t FMD : 3; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TGIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t UDIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t TGIE : 1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_rt_tmcr2_field_t; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* BT_PWC_MODULE register bit fields */ +typedef struct stc_bt_pwc_tmcr_field +{ + uint16_t RESERVED1 : 1; + __IO uint16_t CTEN : 1; + __IO uint16_t MDSE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FMD : 3; + __IO uint16_t T32 : 1; + __IO uint16_t EGS0 : 1; + __IO uint16_t EGS1 : 1; + __IO uint16_t EGS2 : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t CKS0 : 1; + __IO uint16_t CKS1 : 1; + __IO uint16_t CKS2 : 1; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t EDIR : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t OVIE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t EDIE : 1; + __IO uint8_t ERR : 1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 : 1; +} stc_bt_pwc_tmcr2_field_t; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* BTIOSEL03_MODULE register bit fields */ +typedef struct stc_btiosel03_btsel0123_field +{ + __IO uint8_t SEL01_0 : 1; + __IO uint8_t SEL01_1 : 1; + __IO uint8_t SEL01_2 : 1; + __IO uint8_t SEL01_3 : 1; + __IO uint8_t SEL23_0 : 1; + __IO uint8_t SEL23_1 : 1; + __IO uint8_t SEL23_2 : 1; + __IO uint8_t SEL23_3 : 1; +} stc_btiosel03_btsel0123_field_t; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* BTIOSEL47_MODULE register bit fields */ +typedef struct stc_btiosel47_btsel4567_field +{ + __IO uint8_t SEL45_0 : 1; + __IO uint8_t SEL45_1 : 1; + __IO uint8_t SEL45_2 : 1; + __IO uint8_t SEL45_3 : 1; + __IO uint8_t SEL67_0 : 1; + __IO uint8_t SEL67_1 : 1; + __IO uint8_t SEL67_2 : 1; + __IO uint8_t SEL67_3 : 1; +} stc_btiosel47_btsel4567_field_t; + +/****************************************************************************** + * BTIOSEL811_MODULE + ******************************************************************************/ +/* BTIOSEL811_MODULE register bit fields */ +typedef struct stc_btiosel8b_btsel89ab_field +{ + __IO uint8_t SEL89_0 : 1; + __IO uint8_t SEL89_1 : 1; + __IO uint8_t SEL89_2 : 1; + __IO uint8_t SEL89_3 : 1; + __IO uint8_t SELAB_0 : 1; + __IO uint8_t SELAB_1 : 1; + __IO uint8_t SELAB_2 : 1; + __IO uint8_t SELAB_3 : 1; +} stc_btiosel8b_btsel89ab_field_t; + +/****************************************************************************** + * BTIOSEL1215_MODULE + ******************************************************************************/ +/* BTIOSEL1215_MODULE register bit fields */ +typedef struct stc_btioselcf_btselcdef_field +{ + __IO uint8_t SELCD_0 : 1; + __IO uint8_t SELCD_1 : 1; + __IO uint8_t SELCD_2 : 1; + __IO uint8_t SELCD_3 : 1; + __IO uint8_t SELEF_0 : 1; + __IO uint8_t SELEF_1 : 1; + __IO uint8_t SELEF_2 : 1; + __IO uint8_t SELEF_3 : 1; +} stc_btioselcf_btselcdef_field_t; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* SBSSR_MODULE register bit fields */ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSR0 : 1; + __IO uint16_t SSR1 : 1; + __IO uint16_t SSR2 : 1; + __IO uint16_t SSR3 : 1; + __IO uint16_t SSR4 : 1; + __IO uint16_t SSR5 : 1; + __IO uint16_t SSR6 : 1; + __IO uint16_t SSR7 : 1; + __IO uint16_t SSR8 : 1; + __IO uint16_t SSR9 : 1; + __IO uint16_t SSR10 : 1; + __IO uint16_t SSR11 : 1; + __IO uint16_t SSR12 : 1; + __IO uint16_t SSR13 : 1; + __IO uint16_t SSR14 : 1; + __IO uint16_t SSR15 : 1; +} stc_sbssr_btsssr_field_t; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* QPRC_MODULE register bit fields */ +typedef struct stc_qprc_qicr_field +{ + __IO uint16_t QPCMIE : 1; + __IO uint16_t QPCMF : 1; + __IO uint16_t QPRCMIE : 1; + __IO uint16_t QPRCMF : 1; + __IO uint16_t OUZIE : 1; + __IO uint16_t UFDF : 1; + __IO uint16_t OFDF : 1; + __IO uint16_t ZIIF : 1; + __IO uint16_t CDCIE : 1; + __IO uint16_t CDCF : 1; + __IO uint16_t DIRPC : 1; + __IO uint16_t DIROU : 1; + __IO uint16_t QPCNRCMIE : 1; + __IO uint16_t QPCNRCMF : 1; +} stc_qprc_qicr_field_t; + +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE : 1; + __IO uint8_t QPCMF : 1; + __IO uint8_t QPRCMIE : 1; + __IO uint8_t QPRCMF : 1; + __IO uint8_t OUZIE : 1; + __IO uint8_t UFDF : 1; + __IO uint8_t OFDF : 1; + __IO uint8_t ZIIF : 1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE : 1; + __IO uint8_t CDCF : 1; + __IO uint8_t DIRPC : 1; + __IO uint8_t DIROU : 1; + __IO uint8_t QPCNRCMIE : 1; + __IO uint8_t QPCNRCMF : 1; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + __IO uint16_t PCM0 : 1; + __IO uint16_t PCM1 : 1; + __IO uint16_t RCM0 : 1; + __IO uint16_t RCM1 : 1; + __IO uint16_t PSTP : 1; + __IO uint16_t CGSC : 1; + __IO uint16_t RSEL : 1; + __IO uint16_t SWAP : 1; + __IO uint16_t PCRM0 : 1; + __IO uint16_t PCRM1 : 1; + __IO uint16_t AES0 : 1; + __IO uint16_t AES1 : 1; + __IO uint16_t BES0 : 1; + __IO uint16_t BES1 : 1; + __IO uint16_t CGE0 : 1; + __IO uint16_t CGE1 : 1; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qcrl_field +{ + __IO uint8_t PCM0 : 1; + __IO uint8_t PCM1 : 1; + __IO uint8_t RCM0 : 1; + __IO uint8_t RCM1 : 1; + __IO uint8_t PSTP : 1; + __IO uint8_t CGSC : 1; + __IO uint8_t RSEL : 1; + __IO uint8_t SWAP : 1; +} stc_qprc_qcrl_field_t; + +typedef struct stc_qprc_qcrh_field +{ + __IO uint8_t PCRM0 : 1; + __IO uint8_t PCRM1 : 1; + __IO uint8_t AES0 : 1; + __IO uint8_t AES1 : 1; + __IO uint8_t BES0 : 1; + __IO uint8_t BES1 : 1; + __IO uint8_t CGE0 : 1; + __IO uint8_t CGE1 : 1; +} stc_qprc_qcrh_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD : 1; + __IO uint16_t ORNGF : 1; + __IO uint16_t ORNGIE : 1; +} stc_qprc_qecr_field_t; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* ADC12_MODULE register bit fields */ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS : 1; + __IO uint8_t PCS : 1; + __IO uint8_t PCNS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t FDAS : 1; + __IO uint8_t ADSTP : 1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE : 1; + __IO uint8_t CMPIE : 1; + __IO uint8_t PCIE : 1; + __IO uint8_t SCIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t CMPIF : 1; + __IO uint8_t PCIF : 1; + __IO uint8_t SCIF : 1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + __IO uint8_t SFS0 : 1; + __IO uint8_t SFS1 : 1; + __IO uint8_t SFS2 : 1; + __IO uint8_t SFS3 : 1; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR : 1; + __IO uint8_t SHEN : 1; + __IO uint8_t RPT : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t SFCLR : 1; + __IO uint8_t SOVR : 1; + __IO uint8_t SFUL : 1; + __IO uint8_t SEMP : 1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_field +{ + __IO uint32_t SC0 : 1; + __IO uint32_t SC1 : 1; + __IO uint32_t SC2 : 1; + __IO uint32_t SC3 : 1; + __IO uint32_t SC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t SD0 : 1; + __IO uint32_t SD1 : 1; + __IO uint32_t SD2 : 1; + __IO uint32_t SD3 : 1; + __IO uint32_t SD4 : 1; + __IO uint32_t SD5 : 1; + __IO uint32_t SD6 : 1; + __IO uint32_t SD7 : 1; + __IO uint32_t SD8 : 1; + __IO uint32_t SD9 : 1; + __IO uint32_t SD10 : 1; + __IO uint32_t SD11 : 1; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scfdl_field +{ + __IO uint16_t SC0 : 1; + __IO uint16_t SC1 : 1; + __IO uint16_t SC2 : 1; + __IO uint16_t SC3 : 1; + __IO uint16_t SC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t INVL : 1; +} stc_adc_scfdl_field_t; + +typedef struct stc_adc_scfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t SD0 : 1; + __IO uint16_t SD1 : 1; + __IO uint16_t SD2 : 1; + __IO uint16_t SD3 : 1; + __IO uint16_t SD4 : 1; + __IO uint16_t SD5 : 1; + __IO uint16_t SD6 : 1; + __IO uint16_t SD7 : 1; + __IO uint16_t SD8 : 1; + __IO uint16_t SD9 : 1; + __IO uint16_t SD10 : 1; + __IO uint16_t SD11 : 1; +} stc_adc_scfdh_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 : 1; + __IO uint16_t AN17 : 1; + __IO uint16_t AN18 : 1; + __IO uint16_t AN19 : 1; + __IO uint16_t AN20 : 1; + __IO uint16_t AN21 : 1; + __IO uint16_t AN22 : 1; + __IO uint16_t AN23 : 1; + __IO uint16_t AN24 : 1; + __IO uint16_t AN25 : 1; + __IO uint16_t AN26 : 1; + __IO uint16_t AN27 : 1; + __IO uint16_t AN28 : 1; + __IO uint16_t AN29 : 1; + __IO uint16_t AN30 : 1; + __IO uint16_t AN31 : 1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis2_field +{ + __IO uint8_t AN16 : 1; + __IO uint8_t AN17 : 1; + __IO uint8_t AN18 : 1; + __IO uint8_t AN19 : 1; + __IO uint8_t AN20 : 1; + __IO uint8_t AN21 : 1; + __IO uint8_t AN22 : 1; + __IO uint8_t AN23 : 1; +} stc_adc_scis2_field_t; + +typedef struct stc_adc_scis3_field +{ + __IO uint8_t AN24 : 1; + __IO uint8_t AN25 : 1; + __IO uint8_t AN26 : 1; + __IO uint8_t AN27 : 1; + __IO uint8_t AN28 : 1; + __IO uint8_t AN29 : 1; + __IO uint8_t AN30 : 1; + __IO uint8_t AN31 : 1; +} stc_adc_scis3_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 : 1; + __IO uint16_t AN1 : 1; + __IO uint16_t AN2 : 1; + __IO uint16_t AN3 : 1; + __IO uint16_t AN4 : 1; + __IO uint16_t AN5 : 1; + __IO uint16_t AN6 : 1; + __IO uint16_t AN7 : 1; + __IO uint16_t AN8 : 1; + __IO uint16_t AN9 : 1; + __IO uint16_t AN10 : 1; + __IO uint16_t AN11 : 1; + __IO uint16_t AN12 : 1; + __IO uint16_t AN13 : 1; + __IO uint16_t AN14 : 1; + __IO uint16_t AN15 : 1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_scis0_field +{ + __IO uint8_t AN0 : 1; + __IO uint8_t AN1 : 1; + __IO uint8_t AN2 : 1; + __IO uint8_t AN3 : 1; + __IO uint8_t AN4 : 1; + __IO uint8_t AN5 : 1; + __IO uint8_t AN6 : 1; + __IO uint8_t AN7 : 1; +} stc_adc_scis0_field_t; + +typedef struct stc_adc_scis1_field +{ + __IO uint8_t AN8 : 1; + __IO uint8_t AN9 : 1; + __IO uint8_t AN10 : 1; + __IO uint8_t AN11 : 1; + __IO uint8_t AN12 : 1; + __IO uint8_t AN13 : 1; + __IO uint8_t AN14 : 1; + __IO uint8_t AN15 : 1; +} stc_adc_scis1_field_t; + +typedef struct stc_adc_pfns_field +{ + __IO uint8_t PFS0 : 1; + __IO uint8_t PFS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t TEST0 : 1; + __IO uint8_t TEST1 : 1; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR : 1; + __IO uint8_t PHEN : 1; + __IO uint8_t PEEN : 1; + __IO uint8_t ESCE : 1; + __IO uint8_t PFCLR : 1; + __IO uint8_t POVR : 1; + __IO uint8_t PFUL : 1; + __IO uint8_t PEMP : 1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_field +{ + __IO uint32_t PC0 : 1; + __IO uint32_t PC1 : 1; + __IO uint32_t PC2 : 1; + __IO uint32_t PC3 : 1; + __IO uint32_t PC4 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t INVL : 1; + uint32_t RESERVED3 : 7; + __IO uint32_t PD0 : 1; + __IO uint32_t PD1 : 1; + __IO uint32_t PD2 : 1; + __IO uint32_t PD3 : 1; + __IO uint32_t PD4 : 1; + __IO uint32_t PD5 : 1; + __IO uint32_t PD6 : 1; + __IO uint32_t PD7 : 1; + __IO uint32_t PD8 : 1; + __IO uint32_t PD9 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcfdl_field +{ + __IO uint16_t PC0 : 1; + __IO uint16_t PC1 : 1; + __IO uint16_t PC2 : 1; + __IO uint16_t PC3 : 1; + __IO uint16_t PC4 : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t RS0 : 1; + __IO uint16_t RS1 : 1; + __IO uint16_t RS2 : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t INVL : 1; +} stc_adc_pcfdl_field_t; + +typedef struct stc_adc_pcfdh_field +{ + uint16_t RESERVED1 : 4; + __IO uint16_t PD0 : 1; + __IO uint16_t PD1 : 1; + __IO uint16_t PD2 : 1; + __IO uint16_t PD3 : 1; + __IO uint16_t PD4 : 1; + __IO uint16_t PD5 : 1; + __IO uint16_t PD6 : 1; + __IO uint16_t PD7 : 1; + __IO uint16_t PD8 : 1; + __IO uint16_t PD9 : 1; + __IO uint16_t PD10 : 1; + __IO uint16_t PD11 : 1; +} stc_adc_pcfdh_field_t; + +typedef struct stc_adc_pcis_field +{ + __IO uint8_t P1A0 : 1; + __IO uint8_t P1A1 : 1; + __IO uint8_t P1A2 : 1; + __IO uint8_t P2A0 : 1; + __IO uint8_t P2A1 : 1; + __IO uint8_t P2A2 : 1; + __IO uint8_t P2A3 : 1; + __IO uint8_t P2A4 : 1; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + __IO uint8_t CCH0 : 1; + __IO uint8_t CCH1 : 1; + __IO uint8_t CCH2 : 1; + __IO uint8_t CCH3 : 1; + __IO uint8_t CCH4 : 1; + __IO uint8_t CMD0 : 1; + __IO uint8_t CMD1 : 1; + __IO uint8_t CMPEN : 1; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + uint16_t RESERVED1 : 6; + __IO uint16_t CMAD2 : 1; + __IO uint16_t CMAD3 : 1; + __IO uint16_t CMAD4 : 1; + __IO uint16_t CMAD5 : 1; + __IO uint16_t CMAD6 : 1; + __IO uint16_t CMAD7 : 1; + __IO uint16_t CMAD8 : 1; + __IO uint16_t CMAD9 : 1; + __IO uint16_t CMAD10 : 1; + __IO uint16_t CMAD11 : 1; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 : 1; + __IO uint16_t TS17 : 1; + __IO uint16_t TS18 : 1; + __IO uint16_t TS19 : 1; + __IO uint16_t TS20 : 1; + __IO uint16_t TS21 : 1; + __IO uint16_t TS22 : 1; + __IO uint16_t TS23 : 1; + __IO uint16_t TS24 : 1; + __IO uint16_t TS25 : 1; + __IO uint16_t TS26 : 1; + __IO uint16_t TS27 : 1; + __IO uint16_t TS28 : 1; + __IO uint16_t TS29 : 1; + __IO uint16_t TS30 : 1; + __IO uint16_t TS31 : 1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss2_field +{ + __IO uint8_t TS16 : 1; + __IO uint8_t TS17 : 1; + __IO uint8_t TS18 : 1; + __IO uint8_t TS19 : 1; + __IO uint8_t TS20 : 1; + __IO uint8_t TS21 : 1; + __IO uint8_t TS22 : 1; + __IO uint8_t TS23 : 1; +} stc_adc_adss2_field_t; + +typedef struct stc_adc_adss3_field +{ + __IO uint8_t TS24 : 1; + __IO uint8_t TS25 : 1; + __IO uint8_t TS26 : 1; + __IO uint8_t TS27 : 1; + __IO uint8_t TS28 : 1; + __IO uint8_t TS29 : 1; + __IO uint8_t TS30 : 1; + __IO uint8_t TS31 : 1; +} stc_adc_adss3_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 : 1; + __IO uint16_t TS1 : 1; + __IO uint16_t TS2 : 1; + __IO uint16_t TS3 : 1; + __IO uint16_t TS4 : 1; + __IO uint16_t TS5 : 1; + __IO uint16_t TS6 : 1; + __IO uint16_t TS7 : 1; + __IO uint16_t TS8 : 1; + __IO uint16_t TS9 : 1; + __IO uint16_t TS10 : 1; + __IO uint16_t TS11 : 1; + __IO uint16_t TS12 : 1; + __IO uint16_t TS13 : 1; + __IO uint16_t TS14 : 1; + __IO uint16_t TS15 : 1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adss0_field +{ + __IO uint8_t TS0 : 1; + __IO uint8_t TS1 : 1; + __IO uint8_t TS2 : 1; + __IO uint8_t TS3 : 1; + __IO uint8_t TS4 : 1; + __IO uint8_t TS5 : 1; + __IO uint8_t TS6 : 1; + __IO uint8_t TS7 : 1; +} stc_adc_adss0_field_t; + +typedef struct stc_adc_adss1_field +{ + __IO uint8_t TS8 : 1; + __IO uint8_t TS9 : 1; + __IO uint8_t TS10 : 1; + __IO uint8_t TS11 : 1; + __IO uint8_t TS12 : 1; + __IO uint8_t TS13 : 1; + __IO uint8_t TS14 : 1; + __IO uint8_t TS15 : 1; +} stc_adc_adss1_field_t; + +typedef struct stc_adc_adst01_field +{ + __IO uint16_t ST10 : 1; + __IO uint16_t ST11 : 1; + __IO uint16_t ST12 : 1; + __IO uint16_t ST13 : 1; + __IO uint16_t ST14 : 1; + __IO uint16_t STX10 : 1; + __IO uint16_t STX11 : 1; + __IO uint16_t STX12 : 1; + __IO uint16_t ST00 : 1; + __IO uint16_t ST01 : 1; + __IO uint16_t ST02 : 1; + __IO uint16_t ST03 : 1; + __IO uint16_t ST04 : 1; + __IO uint16_t STX00 : 1; + __IO uint16_t STX01 : 1; + __IO uint16_t STX02 : 1; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adst1_field +{ + __IO uint8_t ST10 : 1; + __IO uint8_t ST11 : 1; + __IO uint8_t ST12 : 1; + __IO uint8_t ST13 : 1; + __IO uint8_t ST14 : 1; + __IO uint8_t STX10 : 1; + __IO uint8_t STX11 : 1; + __IO uint8_t STX12 : 1; +} stc_adc_adst1_field_t; + +typedef struct stc_adc_adst0_field +{ + __IO uint8_t ST00 : 1; + __IO uint8_t ST01 : 1; + __IO uint8_t ST02 : 1; + __IO uint8_t ST03 : 1; + __IO uint8_t ST04 : 1; + __IO uint8_t STX00 : 1; + __IO uint8_t STX01 : 1; + __IO uint8_t STX02 : 1; +} stc_adc_adst0_field_t; + +typedef struct stc_adc_adct_field +{ + __IO uint8_t CT0 : 1; + __IO uint8_t CT1 : 1; + __IO uint8_t CT2 : 1; + __IO uint8_t CT3 : 1; + __IO uint8_t CT4 : 1; + __IO uint8_t CT5 : 1; + __IO uint8_t CT6 : 1; + __IO uint8_t CT7 : 1; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + __IO uint8_t PRTSL0 : 1; + __IO uint8_t PRTSL1 : 1; + __IO uint8_t PRTSL2 : 1; + __IO uint8_t PRTSL3 : 1; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + __IO uint8_t SCTSL0 : 1; + __IO uint8_t SCTSL1 : 1; + __IO uint8_t SCTSL2 : 1; + __IO uint8_t SCTSL3 : 1; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + __IO uint8_t ENBL : 1; + __IO uint8_t READY : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t CYCLSL0 : 1; + __IO uint8_t CYCLSL1 : 1; +} stc_adc_adcen_field_t; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CRTRIM_MODULE register bit fields */ +typedef struct stc_crtrim_mcr_psr_field +{ + __IO uint8_t CSR0 : 1; + __IO uint8_t CSR1 : 1; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + __IO uint16_t TRD0 : 1; + __IO uint16_t TRD1 : 1; + __IO uint16_t TRD2 : 1; + __IO uint16_t TRD3 : 1; + __IO uint16_t TRD4 : 1; + __IO uint16_t TRD5 : 1; + __IO uint16_t TRD6 : 1; + __IO uint16_t TRD7 : 1; +} stc_crtrim_mcr_ftrm_field_t; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* EXTI_MODULE registEN bit fields */ +typedef struct stc_exti_enir_field +{ + __IO uint16_t EN0 : 1; + __IO uint16_t EN1 : 1; + __IO uint16_t EN2 : 1; + __IO uint16_t EN3 : 1; + __IO uint16_t EN4 : 1; + __IO uint16_t EN5 : 1; + __IO uint16_t EN6 : 1; + __IO uint16_t EN7 : 1; + __IO uint16_t EN8 : 1; + __IO uint16_t EN9 : 1; + __IO uint16_t EN10 : 1; + __IO uint16_t EN11 : 1; + __IO uint16_t EN12 : 1; + __IO uint16_t EN13 : 1; + __IO uint16_t EN14 : 1; + __IO uint16_t EN15 : 1; + __IO uint16_t EN16 : 1; + __IO uint16_t EN17 : 1; + __IO uint16_t EN18 : 1; + __IO uint16_t EN19 : 1; + __IO uint16_t EN20 : 1; + __IO uint16_t EN21 : 1; + __IO uint16_t EN22 : 1; + __IO uint16_t EN23 : 1; + __IO uint16_t EN24 : 1; + __IO uint16_t EN25 : 1; + __IO uint16_t EN26 : 1; + __IO uint16_t EN27 : 1; + __IO uint16_t EN28 : 1; + __IO uint16_t EN29 : 1; + __IO uint16_t EN30 : 1; + __IO uint16_t EN31 : 1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint16_t ER0 : 1; + __IO uint16_t ER1 : 1; + __IO uint16_t ER2 : 1; + __IO uint16_t ER3 : 1; + __IO uint16_t ER4 : 1; + __IO uint16_t ER5 : 1; + __IO uint16_t ER6 : 1; + __IO uint16_t ER7 : 1; + __IO uint16_t ER8 : 1; + __IO uint16_t ER9 : 1; + __IO uint16_t ER10 : 1; + __IO uint16_t ER11 : 1; + __IO uint16_t ER12 : 1; + __IO uint16_t ER13 : 1; + __IO uint16_t ER14 : 1; + __IO uint16_t ER15 : 1; + __IO uint16_t ER16 : 1; + __IO uint16_t ER17 : 1; + __IO uint16_t ER18 : 1; + __IO uint16_t ER19 : 1; + __IO uint16_t ER20 : 1; + __IO uint16_t ER21 : 1; + __IO uint16_t ER22 : 1; + __IO uint16_t ER23 : 1; + __IO uint16_t ER24 : 1; + __IO uint16_t ER25 : 1; + __IO uint16_t ER26 : 1; + __IO uint16_t ER27 : 1; + __IO uint16_t ER28 : 1; + __IO uint16_t ER29 : 1; + __IO uint16_t ER30 : 1; + __IO uint16_t ER31 : 1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint16_t ECL0 : 1; + __IO uint16_t ECL1 : 1; + __IO uint16_t ECL2 : 1; + __IO uint16_t ECL3 : 1; + __IO uint16_t ECL4 : 1; + __IO uint16_t ECL5 : 1; + __IO uint16_t ECL6 : 1; + __IO uint16_t ECL7 : 1; + __IO uint16_t ECL8 : 1; + __IO uint16_t ECL9 : 1; + __IO uint16_t ECL10 : 1; + __IO uint16_t ECL11 : 1; + __IO uint16_t ECL12 : 1; + __IO uint16_t ECL13 : 1; + __IO uint16_t ECL14 : 1; + __IO uint16_t ECL15 : 1; + __IO uint16_t ECL16 : 1; + __IO uint16_t ECL17 : 1; + __IO uint16_t ECL18 : 1; + __IO uint16_t ECL19 : 1; + __IO uint16_t ECL20 : 1; + __IO uint16_t ECL21 : 1; + __IO uint16_t ECL22 : 1; + __IO uint16_t ECL23 : 1; + __IO uint16_t ECL24 : 1; + __IO uint16_t ECL25 : 1; + __IO uint16_t ECL26 : 1; + __IO uint16_t ECL27 : 1; + __IO uint16_t ECL28 : 1; + __IO uint16_t ECL29 : 1; + __IO uint16_t ECL30 : 1; + __IO uint16_t ECL31 : 1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 : 1; + __IO uint32_t LB0 : 1; + __IO uint32_t LA1 : 1; + __IO uint32_t LB1 : 1; + __IO uint32_t LA2 : 1; + __IO uint32_t LB2 : 1; + __IO uint32_t LA3 : 1; + __IO uint32_t LB3 : 1; + __IO uint32_t LA4 : 1; + __IO uint32_t LB4 : 1; + __IO uint32_t LA5 : 1; + __IO uint32_t LB5 : 1; + __IO uint32_t LA6 : 1; + __IO uint32_t LB6 : 1; + __IO uint32_t LA7 : 1; + __IO uint32_t LB7 : 1; + __IO uint32_t LA8 : 1; + __IO uint32_t LB8 : 1; + __IO uint32_t LA9 : 1; + __IO uint32_t LB9 : 1; + __IO uint32_t LA10 : 1; + __IO uint32_t LB10 : 1; + __IO uint32_t LA11 : 1; + __IO uint32_t LB11 : 1; + __IO uint32_t LA12 : 1; + __IO uint32_t LB12 : 1; + __IO uint32_t LA13 : 1; + __IO uint32_t LB13 : 1; + __IO uint32_t LA14 : 1; + __IO uint32_t LB14 : 1; + __IO uint32_t LA15 : 1; + __IO uint32_t LB15 : 1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_elvr1_field +{ + __IO uint32_t LA16 : 1; + __IO uint32_t LB16 : 1; + __IO uint32_t LA17 : 1; + __IO uint32_t LB17 : 1; + __IO uint32_t LA18 : 1; + __IO uint32_t LB18 : 1; + __IO uint32_t LA19 : 1; + __IO uint32_t LB19 : 1; + __IO uint32_t LA20 : 1; + __IO uint32_t LB20 : 1; + __IO uint32_t LA21 : 1; + __IO uint32_t LB21 : 1; + __IO uint32_t LA22 : 1; + __IO uint32_t LB22 : 1; + __IO uint32_t LA23 : 1; + __IO uint32_t LB23 : 1; + __IO uint32_t LA24 : 1; + __IO uint32_t LB24 : 1; + __IO uint32_t LA25 : 1; + __IO uint32_t LB25 : 1; + __IO uint32_t LA26 : 1; + __IO uint32_t LB26 : 1; + __IO uint32_t LA27 : 1; + __IO uint32_t LB27 : 1; + __IO uint32_t LA28 : 1; + __IO uint32_t LB28 : 1; + __IO uint32_t LA29 : 1; + __IO uint32_t LB29 : 1; + __IO uint32_t LA30 : 1; + __IO uint32_t LB30 : 1; + __IO uint32_t LA31 : 1; + __IO uint32_t LB31 : 1; +} stc_exti_elvr1_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint8_t NR0 : 1; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint8_t NCL0 : 1; +} stc_exti_nmicl_field_t; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* INTREQ_MODULE register bit fields */ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t DRQSEL0 : 1; + __IO uint32_t DRQSEL1 : 1; + __IO uint32_t DRQSEL2 : 1; + __IO uint32_t DRQSEL3 : 1; + __IO uint32_t DRQSEL4 : 1; + __IO uint32_t DRQSEL5 : 1; + __IO uint32_t DRQSEL6 : 1; + __IO uint32_t DRQSEL7 : 1; + __IO uint32_t DRQSEL8 : 1; + __IO uint32_t DRQSEL9 : 1; + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; + __IO uint32_t DRQSEL15 : 1; + __IO uint32_t DRQSEL16 : 1; + __IO uint32_t DRQSEL17 : 1; + __IO uint32_t DRQSEL18 : 1; + __IO uint32_t DRQSEL19 : 1; + __IO uint32_t DRQSEL20 : 1; + __IO uint32_t DRQSEL21 : 1; + __IO uint32_t DRQSEL22 : 1; + __IO uint32_t DRQSEL23 : 1; + __IO uint32_t DRQSEL24 : 1; + __IO uint32_t DRQSEL25 : 1; + __IO uint32_t DRQSEL26 : 1; + __IO uint32_t DRQSEL27 : 1; + __IO uint32_t DRQSEL28 : 1; + __IO uint32_t DRQSEL29 : 1; + __IO uint32_t DRQSEL30 : 1; + __IO uint32_t DRQSEL31 : 1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_oddpks_field +{ + __IO uint8_t ODDPKS0 : 1; + __IO uint8_t ODDPKS1 : 1; + __IO uint8_t ODDPKS2 : 1; + __IO uint8_t ODDPKS3 : 1; + __IO uint8_t ODDPKS4 : 1; +} stc_intreq_oddpks_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI : 1; + __IO uint32_t HWINT : 1; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq00mon_field +{ + __IO uint32_t FCSINT : 1; +} stc_intreq_irq00mon_field_t; + +typedef struct stc_intreq_irq01mon_field +{ + __IO uint32_t SWWDTINT : 1; +} stc_intreq_irq01mon_field_t; + +typedef struct stc_intreq_irq02mon_field +{ + __IO uint32_t LVDINT : 1; +} stc_intreq_irq02mon_field_t; + +typedef struct stc_intreq_irq03mon_field +{ + __IO uint32_t WAVE0INT0 : 1; + __IO uint32_t WAVE0INT1 : 1; + __IO uint32_t WAVE0INT2 : 1; + __IO uint32_t WAVE0INT3 : 1; + __IO uint32_t WAVE1INT0 : 1; + __IO uint32_t WAVE1INT1 : 1; + __IO uint32_t WAVE1INT2 : 1; + __IO uint32_t WAVE1INT3 : 1; + __IO uint32_t WAVE2INT0 : 1; + __IO uint32_t WAVE2INT1 : 1; + __IO uint32_t WAVE2INT2 : 1; + __IO uint32_t WAVE2INT3 : 1; +} stc_intreq_irq03mon_field_t; + +typedef struct stc_intreq_irq04mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; +} stc_intreq_irq04mon_field_t; + +typedef struct stc_intreq_irq05mon_field +{ + __IO uint32_t EXTINT0 : 1; + __IO uint32_t EXTINT1 : 1; + __IO uint32_t EXTINT2 : 1; + __IO uint32_t EXTINT3 : 1; + __IO uint32_t EXTINT4 : 1; + __IO uint32_t EXTINT5 : 1; + __IO uint32_t EXTINT6 : 1; + __IO uint32_t EXTINT7 : 1; + __IO uint32_t EXTINT8 : 1; + __IO uint32_t EXTINT9 : 1; + __IO uint32_t EXTINT10 : 1; + __IO uint32_t EXTINT11 : 1; + __IO uint32_t EXTINT12 : 1; + __IO uint32_t EXTINT13 : 1; + __IO uint32_t EXTINT14 : 1; + __IO uint32_t EXTINT15 : 1; + __IO uint32_t EXTINT16 : 1; + __IO uint32_t EXTINT17 : 1; + __IO uint32_t EXTINT18 : 1; + __IO uint32_t EXTINT19 : 1; + __IO uint32_t EXTINT20 : 1; + __IO uint32_t EXTINT21 : 1; + __IO uint32_t EXTINT22 : 1; + __IO uint32_t EXTINT23 : 1; +} stc_intreq_irq05mon_field_t; + +typedef struct stc_intreq_irq06mon_field +{ + __IO uint32_t TIMINT1 : 1; + __IO uint32_t TIMINT2 : 1; + __IO uint32_t QUD0INT0 : 1; + __IO uint32_t QUD0INT1 : 1; + __IO uint32_t QUD0INT2 : 1; + __IO uint32_t QUD0INT3 : 1; + __IO uint32_t QUD0INT4 : 1; + __IO uint32_t QUD0INT5 : 1; + __IO uint32_t QUD1INT0 : 1; + __IO uint32_t QUD1INT1 : 1; + __IO uint32_t QUD1INT2 : 1; + __IO uint32_t QUD1INT3 : 1; + __IO uint32_t QUD1INT4 : 1; + __IO uint32_t QUD1INT5 : 1; + __IO uint32_t QUD2INT0 : 1; + __IO uint32_t QUD2INT1 : 1; + __IO uint32_t QUD2INT2 : 1; + __IO uint32_t QUD2INT3 : 1; + __IO uint32_t QUD2INT4 : 1; + __IO uint32_t QUD2INT5 : 1; +} stc_intreq_irq06mon_field_t; + +typedef struct stc_intreq_irq07mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq07mon_field_t; + +typedef struct stc_intreq_irq08mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq08mon_field_t; + +typedef struct stc_intreq_irq09mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq09mon_field_t; + +typedef struct stc_intreq_irq10mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq10mon_field_t; + +typedef struct stc_intreq_irq11mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq11mon_field_t; + +typedef struct stc_intreq_irq12mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq12mon_field_t; + +typedef struct stc_intreq_irq13mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq13mon_field_t; + +typedef struct stc_intreq_irq14mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq14mon_field_t; + +typedef struct stc_intreq_irq15mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq15mon_field_t; + +typedef struct stc_intreq_irq16mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq16mon_field_t; + +typedef struct stc_intreq_irq17mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq17mon_field_t; + +typedef struct stc_intreq_irq18mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq18mon_field_t; + +typedef struct stc_intreq_irq19mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq19mon_field_t; + +typedef struct stc_intreq_irq20mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq20mon_field_t; + +typedef struct stc_intreq_irq21mon_field +{ + __IO uint32_t FMSINT : 1; +} stc_intreq_irq21mon_field_t; + +typedef struct stc_intreq_irq22mon_field +{ + __IO uint32_t MFSINT0 : 1; + __IO uint32_t MFSINT1 : 1; +} stc_intreq_irq22mon_field_t; + +typedef struct stc_intreq_irq23mon_field +{ + __IO uint32_t PPGINT0 : 1; + __IO uint32_t PPGINT1 : 1; + __IO uint32_t PPGINT2 : 1; + __IO uint32_t PPGINT3 : 1; + __IO uint32_t PPGINT4 : 1; + __IO uint32_t PPGINT5 : 1; + __IO uint32_t PPGINT6 : 1; + __IO uint32_t PPGINT7 : 1; + __IO uint32_t PPGINT8 : 1; +} stc_intreq_irq23mon_field_t; + +typedef struct stc_intreq_irq24mon_field +{ + __IO uint32_t MOSCINT : 1; + __IO uint32_t SOSCINT : 1; + __IO uint32_t MPLLINT : 1; + __IO uint32_t UPLLINT : 1; + __IO uint32_t WCINT : 1; +} stc_intreq_irq24mon_field_t; + +typedef struct stc_intreq_irq25mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq25mon_field_t; + +typedef struct stc_intreq_irq26mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq26mon_field_t; + +typedef struct stc_intreq_irq27mon_field +{ + __IO uint32_t ADCINT0 : 1; + __IO uint32_t ADCINT1 : 1; + __IO uint32_t ADCINT2 : 1; + __IO uint32_t ADCINT3 : 1; +} stc_intreq_irq27mon_field_t; + +typedef struct stc_intreq_irq28mon_field +{ + __IO uint32_t FRT0INT0 : 1; + __IO uint32_t FRT0INT1 : 1; + __IO uint32_t FRT0INT2 : 1; + __IO uint32_t FRT0INT3 : 1; + __IO uint32_t FRT0INT4 : 1; + __IO uint32_t FRT0INT5 : 1; + __IO uint32_t FRT1INT0 : 1; + __IO uint32_t FRT1INT1 : 1; + __IO uint32_t FRT1INT2 : 1; + __IO uint32_t FRT1INT3 : 1; + __IO uint32_t FRT1INT4 : 1; + __IO uint32_t FRT1INT5 : 1; + __IO uint32_t FRT2INT0 : 1; + __IO uint32_t FRT2INT1 : 1; + __IO uint32_t FRT2INT2 : 1; + __IO uint32_t FRT2INT3 : 1; + __IO uint32_t FRT2INT4 : 1; + __IO uint32_t FRT2INT5 : 1; +} stc_intreq_irq28mon_field_t; + +typedef struct stc_intreq_irq29mon_field +{ + __IO uint32_t ICU0INT0 : 1; + __IO uint32_t ICU0INT1 : 1; + __IO uint32_t ICU0INT2 : 1; + __IO uint32_t ICU0INT3 : 1; + __IO uint32_t ICU1INT0 : 1; + __IO uint32_t ICU1INT1 : 1; + __IO uint32_t ICU1INT2 : 1; + __IO uint32_t ICU1INT3 : 1; + __IO uint32_t ICU2INT0 : 1; + __IO uint32_t ICU2INT1 : 1; + __IO uint32_t ICU2INT2 : 1; + __IO uint32_t ICU2INT3 : 1; +} stc_intreq_irq29mon_field_t; + +typedef struct stc_intreq_irq30mon_field +{ + __IO uint32_t OCU0INT0 : 1; + __IO uint32_t OCU0INT1 : 1; + __IO uint32_t OCU0INT2 : 1; + __IO uint32_t OCU0INT3 : 1; + __IO uint32_t OCU0INT4 : 1; + __IO uint32_t OCU0INT5 : 1; + __IO uint32_t OCU1INT0 : 1; + __IO uint32_t OCU1INT1 : 1; + __IO uint32_t OCU1INT2 : 1; + __IO uint32_t OCU1INT3 : 1; + __IO uint32_t OCU1INT4 : 1; + __IO uint32_t OCU1INT5 : 1; + __IO uint32_t OCU2INT0 : 1; + __IO uint32_t OCU2INT1 : 1; + __IO uint32_t OCU2INT2 : 1; + __IO uint32_t OCU2INT3 : 1; + __IO uint32_t OCU2INT4 : 1; + __IO uint32_t OCU2INT5 : 1; +} stc_intreq_irq30mon_field_t; + +typedef struct stc_intreq_irq31mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; + __IO uint32_t BTINT8 : 1; + __IO uint32_t BTINT9 : 1; + __IO uint32_t BTINT10 : 1; + __IO uint32_t BTINT11 : 1; + __IO uint32_t BTINT12 : 1; + __IO uint32_t BTINT13 : 1; + __IO uint32_t BTINT14 : 1; + __IO uint32_t BTINT15 : 1; +} stc_intreq_irq31mon_field_t; + +typedef struct stc_intreq_irq32mon_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t MAC0SBD : 1; + __IO uint32_t MAC0PMI : 1; + __IO uint32_t MAC0LPI : 1; +} stc_intreq_irq32mon_field_t; + +typedef struct stc_intreq_irq33mon_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t MAC1SBD : 1; + __IO uint32_t MAC1PMI : 1; +} stc_intreq_irq33mon_field_t; + +typedef struct stc_intreq_irq34mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; +} stc_intreq_irq34mon_field_t; + +typedef struct stc_intreq_irq35mon_field +{ + __IO uint32_t USB0INT0 : 1; + __IO uint32_t USB0INT1 : 1; + __IO uint32_t USB0INT2 : 1; + __IO uint32_t USB0INT3 : 1; + __IO uint32_t USB0INT4 : 1; + __IO uint32_t USB0INT5 : 1; +} stc_intreq_irq35mon_field_t; + +typedef struct stc_intreq_irq36mon_field +{ + __IO uint32_t USB1INT0 : 1; + __IO uint32_t USB1INT1 : 1; + __IO uint32_t USB1INT2 : 1; + __IO uint32_t USB1INT3 : 1; + __IO uint32_t USB1INT4 : 1; +} stc_intreq_irq36mon_field_t; + +typedef struct stc_intreq_irq37mon_field +{ + __IO uint32_t USB1INT0 : 1; + __IO uint32_t USB1INT1 : 1; + __IO uint32_t USB1INT2 : 1; + __IO uint32_t USB1INT3 : 1; + __IO uint32_t USB1INT4 : 1; + __IO uint32_t USB1INT5 : 1; +} stc_intreq_irq37mon_field_t; + +typedef struct stc_intreq_irq38mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq38mon_field_t; + +typedef struct stc_intreq_irq39mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq39mon_field_t; + +typedef struct stc_intreq_irq40mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq40mon_field_t; + +typedef struct stc_intreq_irq41mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq41mon_field_t; + +typedef struct stc_intreq_irq42mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq42mon_field_t; + +typedef struct stc_intreq_irq43mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq43mon_field_t; + +typedef struct stc_intreq_irq44mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq44mon_field_t; + +typedef struct stc_intreq_irq45mon_field +{ + __IO uint32_t DMAINT : 1; +} stc_intreq_irq45mon_field_t; + +typedef struct stc_intreq_irq46mon_field +{ + __IO uint32_t BTINT0 : 1; + __IO uint32_t BTINT1 : 1; + __IO uint32_t BTINT2 : 1; + __IO uint32_t BTINT3 : 1; + __IO uint32_t BTINT4 : 1; + __IO uint32_t BTINT5 : 1; + __IO uint32_t BTINT6 : 1; + __IO uint32_t BTINT7 : 1; + __IO uint32_t BTINT8 : 1; + __IO uint32_t BTINT9 : 1; + __IO uint32_t BTINT10 : 1; + __IO uint32_t BTINT11 : 1; + __IO uint32_t BTINT12 : 1; + __IO uint32_t BTINT13 : 1; + __IO uint32_t BTINT14 : 1; + __IO uint32_t BTINT15 : 1; +} stc_intreq_irq46mon_field_t; + +typedef struct stc_intreq_drqsel1_field +{ + __IO uint32_t DRQSEL10 : 1; + __IO uint32_t DRQSEL11 : 1; + __IO uint32_t DRQSEL12 : 1; + __IO uint32_t DRQSEL13 : 1; + __IO uint32_t DRQSEL14 : 1; +} stc_intreq_drqsel1_field_t; + +typedef struct stc_intreq_dqesel_field +{ + __IO uint32_t ESEL100 : 1; + __IO uint32_t ESEL101 : 1; + __IO uint32_t ESEL102 : 1; + __IO uint32_t ESEL103 : 1; + __IO uint32_t ESEL110 : 1; + __IO uint32_t ESEL111 : 1; + __IO uint32_t ESEL112 : 1; + __IO uint32_t ESEL113 : 1; + __IO uint32_t ESEL240 : 1; + __IO uint32_t ESEL241 : 1; + __IO uint32_t ESEL242 : 1; + __IO uint32_t ESEL243 : 1; + __IO uint32_t ESEL250 : 1; + __IO uint32_t ESEL251 : 1; + __IO uint32_t ESEL252 : 1; + __IO uint32_t ESEL253 : 1; + __IO uint32_t ESEL260 : 1; + __IO uint32_t ESEL261 : 1; + __IO uint32_t ESEL262 : 1; + __IO uint32_t ESEL263 : 1; + __IO uint32_t ESEL270 : 1; + __IO uint32_t ESEL271 : 1; + __IO uint32_t ESEL272 : 1; + __IO uint32_t ESEL273 : 1; + __IO uint32_t ESEL300 : 1; + __IO uint32_t ESEL301 : 1; + __IO uint32_t ESEL302 : 1; + __IO uint32_t ESEL303 : 1; + __IO uint32_t ESEL310 : 1; + __IO uint32_t ESEL311 : 1; + __IO uint32_t ESEL312 : 1; + __IO uint32_t ESEL313 : 1; +} stc_intreq_dqesel_field_t; + +typedef struct stc_intreq_oddpks1_field +{ + __IO uint8_t ODDPKS10 : 1; + __IO uint8_t ODDPKS11 : 1; + __IO uint8_t ODDPKS12 : 1; + __IO uint8_t ODDPKS13 : 1; + __IO uint8_t ODDPKS14 : 1; +} stc_intreq_oddpks1_field_t; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* GPIO_MODULE register bit fields */ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_pfr5_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfr8_field_t; + +typedef struct stc_gpio_pfr9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pfr9_field_t; + +typedef struct stc_gpio_pfra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pfra_field_t; + +typedef struct stc_gpio_pfrb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_pfrb_field_t; + +typedef struct stc_gpio_pfrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pfrc_field_t; + +typedef struct stc_gpio_pfrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfrd_field_t; + +typedef struct stc_gpio_pfre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pfre_field_t; + +typedef struct stc_gpio_pfrf_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pfrf_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_pcr5_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_pcr9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pcr9_field_t; + +typedef struct stc_gpio_pcra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pcra_field_t; + +typedef struct stc_gpio_pcrb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_pcrb_field_t; + +typedef struct stc_gpio_pcrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pcrc_field_t; + +typedef struct stc_gpio_pcrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pcrd_field_t; + +typedef struct stc_gpio_pcre_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pcre_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_ddr5_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_ddr9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_ddr9_field_t; + +typedef struct stc_gpio_ddra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_ddra_field_t; + +typedef struct stc_gpio_ddrb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_ddrb_field_t; + +typedef struct stc_gpio_ddrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_ddrc_field_t; + +typedef struct stc_gpio_ddrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddrd_field_t; + +typedef struct stc_gpio_ddre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_ddre_field_t; + +typedef struct stc_gpio_ddrf_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_ddrf_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_pdir5_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdir9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdir9_field_t; + +typedef struct stc_gpio_pdira_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdira_field_t; + +typedef struct stc_gpio_pdirb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_pdirb_field_t; + +typedef struct stc_gpio_pdirc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdirc_field_t; + +typedef struct stc_gpio_pdird_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdird_field_t; + +typedef struct stc_gpio_pdire_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdire_field_t; + +typedef struct stc_gpio_pdirf_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pdirf_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_pdor5_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_pdor9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdor9_field_t; + +typedef struct stc_gpio_pdora_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pdora_field_t; + +typedef struct stc_gpio_pdorb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_pdorb_field_t; + +typedef struct stc_gpio_pdorc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pdorc_field_t; + +typedef struct stc_gpio_pdord_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdord_field_t; + +typedef struct stc_gpio_pdore_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pdore_field_t; + +typedef struct stc_gpio_pdorf_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pdorf_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN0 : 1; + __IO uint32_t AN1 : 1; + __IO uint32_t AN2 : 1; + __IO uint32_t AN3 : 1; + __IO uint32_t AN4 : 1; + __IO uint32_t AN5 : 1; + __IO uint32_t AN6 : 1; + __IO uint32_t AN7 : 1; + __IO uint32_t AN8 : 1; + __IO uint32_t AN9 : 1; + __IO uint32_t AN10 : 1; + __IO uint32_t AN11 : 1; + __IO uint32_t AN12 : 1; + __IO uint32_t AN13 : 1; + __IO uint32_t AN14 : 1; + __IO uint32_t AN15 : 1; + __IO uint32_t AN16 : 1; + __IO uint32_t AN17 : 1; + __IO uint32_t AN18 : 1; + __IO uint32_t AN19 : 1; + __IO uint32_t AN20 : 1; + __IO uint32_t AN21 : 1; + __IO uint32_t AN22 : 1; + __IO uint32_t AN23 : 1; + __IO uint32_t AN24 : 1; + __IO uint32_t AN25 : 1; + __IO uint32_t AN26 : 1; + __IO uint32_t AN27 : 1; + __IO uint32_t AN28 : 1; + __IO uint32_t AN29 : 1; + __IO uint32_t AN30 : 1; + __IO uint32_t AN31 : 1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + __IO uint32_t SUBXC : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MAINXC : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t USB0C : 1; + __IO uint32_t USB1C : 1; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + __IO uint32_t NMIS : 1; + __IO uint32_t CROUTE0 : 1; + __IO uint32_t CROUTE1 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SUBOUTE0 : 1; + __IO uint32_t SUBOUTE1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t USBP0E : 1; + uint32_t RESERVED3 : 3; + __IO uint32_t USBP1E : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t JTAGEN0B : 1; + __IO uint32_t JTAGEN1S : 1; + uint32_t RESERVED5 : 6; + __IO uint32_t TRC0E : 1; + __IO uint32_t TRC1E : 1; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + __IO uint32_t RTO00E0 : 1; + __IO uint32_t RTO00E1 : 1; + __IO uint32_t RTO01E0 : 1; + __IO uint32_t RTO01E1 : 1; + __IO uint32_t RTO02E0 : 1; + __IO uint32_t RTO02E1 : 1; + __IO uint32_t RTO03E0 : 1; + __IO uint32_t RTO03E1 : 1; + __IO uint32_t RTO04E0 : 1; + __IO uint32_t RTO04E1 : 1; + __IO uint32_t RTO05E0 : 1; + __IO uint32_t RTO05E1 : 1; + __IO uint32_t DTTI0C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI0S0 : 1; + __IO uint32_t DTTI0S1 : 1; + __IO uint32_t FRCK0S0 : 1; + __IO uint32_t FRCK0S1 : 1; + __IO uint32_t IC00S0 : 1; + __IO uint32_t IC00S1 : 1; + __IO uint32_t IC00S2 : 1; + __IO uint32_t IC01S0 : 1; + __IO uint32_t IC01S1 : 1; + __IO uint32_t IC01S2 : 1; + __IO uint32_t IC02S0 : 1; + __IO uint32_t IC02S1 : 1; + __IO uint32_t IC02S2 : 1; + __IO uint32_t IC03S0 : 1; + __IO uint32_t IC03S1 : 1; + __IO uint32_t IC03S2 : 1; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + __IO uint32_t RTO10E0 : 1; + __IO uint32_t RTO10E1 : 1; + __IO uint32_t RTO11E0 : 1; + __IO uint32_t RTO11E1 : 1; + __IO uint32_t RTO12E0 : 1; + __IO uint32_t RTO12E1 : 1; + __IO uint32_t RTO13E0 : 1; + __IO uint32_t RTO13E1 : 1; + __IO uint32_t RTO14E0 : 1; + __IO uint32_t RTO14E1 : 1; + __IO uint32_t RTO15E0 : 1; + __IO uint32_t RTO15E1 : 1; + __IO uint32_t DTTI1C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI1S0 : 1; + __IO uint32_t DTTI1S1 : 1; + __IO uint32_t FRCK1S0 : 1; + __IO uint32_t FRCK1S1 : 1; + __IO uint32_t IC10S0 : 1; + __IO uint32_t IC10S1 : 1; + __IO uint32_t IC10S2 : 1; + __IO uint32_t IC11S0 : 1; + __IO uint32_t IC11S1 : 1; + __IO uint32_t IC11S2 : 1; + __IO uint32_t IC12S0 : 1; + __IO uint32_t IC12S1 : 1; + __IO uint32_t IC12S2 : 1; + __IO uint32_t IC13S0 : 1; + __IO uint32_t IC13S1 : 1; + __IO uint32_t IC13S2 : 1; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr03_field +{ + __IO uint32_t RTO20E0 : 1; + __IO uint32_t RTO20E1 : 1; + __IO uint32_t RTO21E0 : 1; + __IO uint32_t RTO21E1 : 1; + __IO uint32_t RTO22E0 : 1; + __IO uint32_t RTO22E1 : 1; + __IO uint32_t RTO23E0 : 1; + __IO uint32_t RTO23E1 : 1; + __IO uint32_t RTO24E0 : 1; + __IO uint32_t RTO24E1 : 1; + __IO uint32_t RTO25E0 : 1; + __IO uint32_t RTO25E1 : 1; + __IO uint32_t DTTI2C : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTTI2S0 : 1; + __IO uint32_t DTTI2S1 : 1; + __IO uint32_t FRCK2S0 : 1; + __IO uint32_t FRCK2S1 : 1; + __IO uint32_t IC20S0 : 1; + __IO uint32_t IC20S1 : 1; + __IO uint32_t IC20S2 : 1; + __IO uint32_t IC21S0 : 1; + __IO uint32_t IC21S1 : 1; + __IO uint32_t IC21S2 : 1; + __IO uint32_t IC22S0 : 1; + __IO uint32_t IC22S1 : 1; + __IO uint32_t IC22S2 : 1; + __IO uint32_t IC23S0 : 1; + __IO uint32_t IC23S1 : 1; + __IO uint32_t IC23S2 : 1; +} stc_gpio_epfr03_field_t; + +typedef struct stc_gpio_epfr04_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA0E0 : 1; + __IO uint32_t TIOA0E1 : 1; + __IO uint32_t TIOB0S0 : 1; + __IO uint32_t TIOB0S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA1S0 : 1; + __IO uint32_t TIOA1S1 : 1; + __IO uint32_t TIOA1E0 : 1; + __IO uint32_t TIOA1E1 : 1; + __IO uint32_t TIOB1S0 : 1; + __IO uint32_t TIOB1S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA2E0 : 1; + __IO uint32_t TIOA2E1 : 1; + __IO uint32_t TIOB2S0 : 1; + __IO uint32_t TIOB2S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA3S0 : 1; + __IO uint32_t TIOA3S1 : 1; + __IO uint32_t TIOA3E0 : 1; + __IO uint32_t TIOA3E1 : 1; + __IO uint32_t TIOB3S0 : 1; + __IO uint32_t TIOB3S1 : 1; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA4E0 : 1; + __IO uint32_t TIOA4E1 : 1; + __IO uint32_t TIOB4S0 : 1; + __IO uint32_t TIOB4S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA5S0 : 1; + __IO uint32_t TIOA5S1 : 1; + __IO uint32_t TIOA5E0 : 1; + __IO uint32_t TIOA5E1 : 1; + __IO uint32_t TIOB5S0 : 1; + __IO uint32_t TIOB5S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA6E0 : 1; + __IO uint32_t TIOA6E1 : 1; + __IO uint32_t TIOB6S0 : 1; + __IO uint32_t TIOB6S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA7S0 : 1; + __IO uint32_t TIOA7S1 : 1; + __IO uint32_t TIOA7E0 : 1; + __IO uint32_t TIOA7E1 : 1; + __IO uint32_t TIOB7S0 : 1; + __IO uint32_t TIOB7S1 : 1; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + __IO uint32_t EINT00S0 : 1; + __IO uint32_t EINT00S1 : 1; + __IO uint32_t EINT01S0 : 1; + __IO uint32_t EINT01S1 : 1; + __IO uint32_t EINT02S0 : 1; + __IO uint32_t EINT02S1 : 1; + __IO uint32_t EINT03S0 : 1; + __IO uint32_t EINT03S1 : 1; + __IO uint32_t EINT04S0 : 1; + __IO uint32_t EINT04S1 : 1; + __IO uint32_t EINT05S0 : 1; + __IO uint32_t EINT05S1 : 1; + __IO uint32_t EINT06S0 : 1; + __IO uint32_t EINT06S1 : 1; + __IO uint32_t EINT07S0 : 1; + __IO uint32_t EINT07S1 : 1; + __IO uint32_t EINT08S0 : 1; + __IO uint32_t EINT08S1 : 1; + __IO uint32_t EINT09S0 : 1; + __IO uint32_t EINT09S1 : 1; + __IO uint32_t EINT10S0 : 1; + __IO uint32_t EINT10S1 : 1; + __IO uint32_t EINT11S0 : 1; + __IO uint32_t EINT11S1 : 1; + __IO uint32_t EINT12S0 : 1; + __IO uint32_t EINT12S1 : 1; + __IO uint32_t EINT13S0 : 1; + __IO uint32_t EINT13S1 : 1; + __IO uint32_t EINT14S0 : 1; + __IO uint32_t EINT14S1 : 1; + __IO uint32_t EINT15S0 : 1; + __IO uint32_t EINT15S1 : 1; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + uint32_t RESERVED1 : 4; + __IO uint32_t SIN0S0 : 1; + __IO uint32_t SIN0S1 : 1; + __IO uint32_t SOT0B0 : 1; + __IO uint32_t SOT0B1 : 1; + __IO uint32_t SCK0B0 : 1; + __IO uint32_t SCK0B1 : 1; + __IO uint32_t SIN1S0 : 1; + __IO uint32_t SIN1S1 : 1; + __IO uint32_t SOT1B0 : 1; + __IO uint32_t SOT1B1 : 1; + __IO uint32_t SCK1B0 : 1; + __IO uint32_t SCK1B1 : 1; + __IO uint32_t SIN2S0 : 1; + __IO uint32_t SIN2S1 : 1; + __IO uint32_t SOT2B0 : 1; + __IO uint32_t SOT2B1 : 1; + __IO uint32_t SCK2B0 : 1; + __IO uint32_t SCK2B1 : 1; + __IO uint32_t SIN3S0 : 1; + __IO uint32_t SIN3S1 : 1; + __IO uint32_t SOT3B0 : 1; + __IO uint32_t SOT3B1 : 1; + __IO uint32_t SCK3B0 : 1; + __IO uint32_t SCK3B1 : 1; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + __IO uint32_t RTS4E0 : 1; + __IO uint32_t RTS4E1 : 1; + __IO uint32_t CTS4S0 : 1; + __IO uint32_t CTS4S1 : 1; + __IO uint32_t SIN4S0 : 1; + __IO uint32_t SIN4S1 : 1; + __IO uint32_t SOT4B0 : 1; + __IO uint32_t SOT4B1 : 1; + __IO uint32_t SCK4B0 : 1; + __IO uint32_t SCK4B1 : 1; + __IO uint32_t SIN5S0 : 1; + __IO uint32_t SIN5S1 : 1; + __IO uint32_t SOT5B0 : 1; + __IO uint32_t SOT5B1 : 1; + __IO uint32_t SCK5B0 : 1; + __IO uint32_t SCK5B1 : 1; + __IO uint32_t SIN6S0 : 1; + __IO uint32_t SIN6S1 : 1; + __IO uint32_t SOT6B0 : 1; + __IO uint32_t SOT6B1 : 1; + __IO uint32_t SCK6B0 : 1; + __IO uint32_t SCK6B1 : 1; + __IO uint32_t SIN7S0 : 1; + __IO uint32_t SIN7S1 : 1; + __IO uint32_t SOT7B0 : 1; + __IO uint32_t SOT7B1 : 1; + __IO uint32_t SCK7B0 : 1; + __IO uint32_t SCK7B1 : 1; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + __IO uint32_t QAIN0S0 : 1; + __IO uint32_t QAIN0S1 : 1; + __IO uint32_t QBIN0S0 : 1; + __IO uint32_t QBIN0S1 : 1; + __IO uint32_t QZIN0S0 : 1; + __IO uint32_t QZIN0S1 : 1; + __IO uint32_t QAIN1S0 : 1; + __IO uint32_t QAIN1S1 : 1; + __IO uint32_t QBIN1S0 : 1; + __IO uint32_t QBIN1S1 : 1; + __IO uint32_t QZIN1S0 : 1; + __IO uint32_t QZIN1S1 : 1; + __IO uint32_t ADTRG0S0 : 1; + __IO uint32_t ADTRG0S1 : 1; + __IO uint32_t ADTRG0S2 : 1; + __IO uint32_t ADTRG0S3 : 1; + __IO uint32_t ADTRG1S0 : 1; + __IO uint32_t ADTRG1S1 : 1; + __IO uint32_t ADTRG1S2 : 1; + __IO uint32_t ADTRG1S3 : 1; + __IO uint32_t ADTRG2S0 : 1; + __IO uint32_t ADTRG2S1 : 1; + __IO uint32_t ADTRG2S2 : 1; + __IO uint32_t ADTRG2S3 : 1; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB : 1; + __IO uint32_t UEDTHB : 1; + __IO uint32_t UECLKE : 1; + __IO uint32_t UEWEXE : 1; + __IO uint32_t UEDQME : 1; + __IO uint32_t UEOEXE : 1; + __IO uint32_t UEFLSE : 1; + __IO uint32_t UECS1E : 1; + __IO uint32_t UECS2E : 1; + __IO uint32_t UECS3E : 1; + __IO uint32_t UECS4E : 1; + __IO uint32_t UECS5E : 1; + __IO uint32_t UECS6E : 1; + __IO uint32_t UECS7E : 1; + __IO uint32_t UEAOOE : 1; + __IO uint32_t UEA08E : 1; + __IO uint32_t UEA09E : 1; + __IO uint32_t UEA10E : 1; + __IO uint32_t UEA11E : 1; + __IO uint32_t UEA12E : 1; + __IO uint32_t UEA13E : 1; + __IO uint32_t UEA14E : 1; + __IO uint32_t UEA15E : 1; + __IO uint32_t UEA16E : 1; + __IO uint32_t UEA17E : 1; + __IO uint32_t UEA18E : 1; + __IO uint32_t UEA19E : 1; + __IO uint32_t UEA20E : 1; + __IO uint32_t UEA21E : 1; + __IO uint32_t UEA22E : 1; + __IO uint32_t UEA23E : 1; + __IO uint32_t UEA24E : 1; +} stc_gpio_epfr10_field_t; + +typedef struct stc_gpio_epfr11_field +{ + __IO uint32_t UEALEE : 1; + __IO uint32_t UECS0E : 1; + __IO uint32_t UEA01E : 1; + __IO uint32_t UEA02E : 1; + __IO uint32_t UEA03E : 1; + __IO uint32_t UEA04E : 1; + __IO uint32_t UEA05E : 1; + __IO uint32_t UEA06E : 1; + __IO uint32_t UEA07E : 1; + __IO uint32_t UED00B : 1; + __IO uint32_t UED01B : 1; + __IO uint32_t UED02B : 1; + __IO uint32_t UED03B : 1; + __IO uint32_t UED04B : 1; + __IO uint32_t UED05B : 1; + __IO uint32_t UED06B : 1; + __IO uint32_t UED07B : 1; + __IO uint32_t UED08B : 1; + __IO uint32_t UED09B : 1; + __IO uint32_t UED10B : 1; + __IO uint32_t UED11B : 1; + __IO uint32_t UED12B : 1; + __IO uint32_t UED13B : 1; + __IO uint32_t UED14B : 1; + __IO uint32_t UED15B : 1; + __IO uint32_t UERLC : 1; +} stc_gpio_epfr11_field_t; + +typedef struct stc_gpio_epfr12_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA8E0 : 1; + __IO uint32_t TIOA8E1 : 1; + __IO uint32_t TIOB8S0 : 1; + __IO uint32_t TIOB8S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA9S0 : 1; + __IO uint32_t TIOA9S1 : 1; + __IO uint32_t TIOA9E0 : 1; + __IO uint32_t TIOA9E1 : 1; + __IO uint32_t TIOB9S0 : 1; + __IO uint32_t TIOB9S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA10E0 : 1; + __IO uint32_t TIOA10E1 : 1; + __IO uint32_t TIOB10S0 : 1; + __IO uint32_t TIOB10S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA11S0 : 1; + __IO uint32_t TIOA11S1 : 1; + __IO uint32_t TIOA11E0 : 1; + __IO uint32_t TIOA11E1 : 1; + __IO uint32_t TIOB11S0 : 1; + __IO uint32_t TIOB11S1 : 1; +} stc_gpio_epfr12_field_t; + +typedef struct stc_gpio_epfr13_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t TIOA12E0 : 1; + __IO uint32_t TIOA12E1 : 1; + __IO uint32_t TIOB12S0 : 1; + __IO uint32_t TIOB12S1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t TIOA13S0 : 1; + __IO uint32_t TIOA13S1 : 1; + __IO uint32_t TIOA13E0 : 1; + __IO uint32_t TIOA13E1 : 1; + __IO uint32_t TIOB13S0 : 1; + __IO uint32_t TIOB13S1 : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t TIOA14E0 : 1; + __IO uint32_t TIOA14E1 : 1; + __IO uint32_t TIOB14S0 : 1; + __IO uint32_t TIOB14S1 : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t TIOA15S0 : 1; + __IO uint32_t TIOA15S1 : 1; + __IO uint32_t TIOA15E0 : 1; + __IO uint32_t TIOA15E1 : 1; + __IO uint32_t TIOB15S0 : 1; + __IO uint32_t TIOB15S1 : 1; +} stc_gpio_epfr13_field_t; + +typedef struct stc_gpio_epfr14_field +{ + __IO uint32_t QAIN2S0 : 1; + __IO uint32_t QAIN2S1 : 1; + __IO uint32_t QBIN2S0 : 1; + __IO uint32_t QBIN2S1 : 1; + __IO uint32_t QZIN2S0 : 1; + __IO uint32_t QZIN2S1 : 1; + uint32_t RESERVED1 : 12; + __IO uint32_t E_TD0E : 1; + __IO uint32_t E_TD1E : 1; + __IO uint32_t E_TE0E : 1; + __IO uint32_t E_TE1E : 1; + __IO uint32_t E_MC0E : 1; + __IO uint32_t E_MC1B : 1; + __IO uint32_t E_MD0B : 1; + __IO uint32_t E_MD1B : 1; + __IO uint32_t E_CKE : 1; + __IO uint32_t E_PSE : 1; + __IO uint32_t E_SPLC0 : 1; + __IO uint32_t E_SPLC1 : 1; +} stc_gpio_epfr14_field_t; + +typedef struct stc_gpio_epfr15_field +{ + __IO uint32_t EINT16S0 : 1; + __IO uint32_t EINT16S1 : 1; + __IO uint32_t EINT17S0 : 1; + __IO uint32_t EINT17S1 : 1; + __IO uint32_t EINT18S0 : 1; + __IO uint32_t EINT18S1 : 1; + __IO uint32_t EINT19S0 : 1; + __IO uint32_t EINT19S1 : 1; + __IO uint32_t EINT20S0 : 1; + __IO uint32_t EINT20S1 : 1; + __IO uint32_t EINT21S0 : 1; + __IO uint32_t EINT21S1 : 1; + __IO uint32_t EINT22S0 : 1; + __IO uint32_t EINT22S1 : 1; + __IO uint32_t EINT23S0 : 1; + __IO uint32_t EINT23S1 : 1; + __IO uint32_t EINT24S0 : 1; + __IO uint32_t EINT24S1 : 1; + __IO uint32_t EINT25S0 : 1; + __IO uint32_t EINT25S1 : 1; + __IO uint32_t EINT26S0 : 1; + __IO uint32_t EINT26S1 : 1; + __IO uint32_t EINT27S0 : 1; + __IO uint32_t EINT27S1 : 1; + __IO uint32_t EINT28S0 : 1; + __IO uint32_t EINT28S1 : 1; + __IO uint32_t EINT29S0 : 1; + __IO uint32_t EINT29S1 : 1; + __IO uint32_t EINT30S0 : 1; + __IO uint32_t EINT30S1 : 1; + __IO uint32_t EINT31S0 : 1; + __IO uint32_t EINT31S1 : 1; +} stc_gpio_epfr15_field_t; + +typedef struct stc_gpio_pzr0_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pzr0_field_t; + +typedef struct stc_gpio_pzr1_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzr1_field_t; + +typedef struct stc_gpio_pzr2_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; +} stc_gpio_pzr2_field_t; + +typedef struct stc_gpio_pzr3_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzr3_field_t; + +typedef struct stc_gpio_pzr4_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; +} stc_gpio_pzr4_field_t; + +typedef struct stc_gpio_pzr5_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; +} stc_gpio_pzr5_field_t; + +typedef struct stc_gpio_pzr6_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; +} stc_gpio_pzr6_field_t; + +typedef struct stc_gpio_pzr7_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzr7_field_t; + +typedef struct stc_gpio_pzr8_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzr8_field_t; + +typedef struct stc_gpio_pzr9_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pzr9_field_t; + +typedef struct stc_gpio_pzra_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; +} stc_gpio_pzra_field_t; + +typedef struct stc_gpio_pzrb_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; +} stc_gpio_pzrb_field_t; + +typedef struct stc_gpio_pzrc_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; + __IO uint32_t P7 : 1; + __IO uint32_t P8 : 1; + __IO uint32_t P9 : 1; + __IO uint32_t PA : 1; + __IO uint32_t PB : 1; + __IO uint32_t PC : 1; + __IO uint32_t PD : 1; + __IO uint32_t PE : 1; + __IO uint32_t PF : 1; +} stc_gpio_pzrc_field_t; + +typedef struct stc_gpio_pzrd_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzrd_field_t; + +typedef struct stc_gpio_pzre_field +{ + __IO uint32_t P0 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; +} stc_gpio_pzre_field_t; + +typedef struct stc_gpio_pzrf_field +{ + __IO uint32_t P0 : 1; + __IO uint32_t P1 : 1; + __IO uint32_t P2 : 1; + __IO uint32_t P3 : 1; + __IO uint32_t P4 : 1; + __IO uint32_t P5 : 1; + __IO uint32_t P6 : 1; +} stc_gpio_pzrf_field_t; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* LVD_MODULE register bit fields */ +typedef struct stc_lvd_lvd_ctl_field +{ + uint8_t RESERVED1 : 2; + __IO uint8_t SVHI0 : 1; + __IO uint8_t SVHI1 : 1; + __IO uint8_t SVHI2 : 1; + __IO uint8_t SVHI3 : 1; + uint8_t RESERVED2 : 1; + __IO uint8_t LVDIE : 1; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIR : 1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDCL : 1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t LVDIRDY : 1; +} stc_lvd_lvd_str2_field_t; + +/****************************************************************************** + * USB Ethernet CLK + ******************************************************************************/ +/* USB ETHERNET CLK register bit fields */ +typedef struct stc_usbethernetclk_uccr_field +{ + __IO uint8_t UCEN0 : 1; + __IO uint8_t UCSEL0 : 1; + __IO uint8_t UCSEL1 : 1; + __IO uint8_t UCEN1 : 1; + __IO uint8_t ECEN : 1; + __IO uint8_t ECSEL0 : 1; + __IO uint8_t ECSEL1 : 1; +} stc_usbethernetclk_uccr_field_t; + +typedef struct stc_usbethernetclk_upcr1_field +{ + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; +} stc_usbethernetclk_upcr1_field_t; + +typedef struct stc_usbethernetclk_upcr2_field +{ + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; +} stc_usbethernetclk_upcr2_field_t; + +typedef struct stc_usbethernetclk_upcr3_field +{ + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; +} stc_usbethernetclk_upcr3_field_t; + +typedef struct stc_usbethernetclk_upcr4_field +{ + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; +} stc_usbethernetclk_upcr4_field_t; + +typedef struct stc_usbethernetclk_up_str_field +{ + __IO uint8_t UPRDY : 1; +} stc_usbethernetclk_up_str_field_t; + +typedef struct stc_usbethernetclk_upint_enr_field +{ + __IO uint8_t UPCSE : 1; +} stc_usbethernetclk_upint_enr_field_t; + +typedef struct stc_usbethernetclk_upint_clr_field +{ + __IO uint8_t UPCSC : 1; +} stc_usbethernetclk_upint_clr_field_t; + +typedef struct stc_usbethernetclk_upint_str_field +{ + __IO uint8_t UPCSI : 1; +} stc_usbethernetclk_upint_str_field_t; + +typedef struct stc_usbethernetclk_upcr5_field +{ + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; +} stc_usbethernetclk_upcr5_field_t; + +typedef struct stc_usbethernetclk_upcr6_field +{ + __IO uint8_t UBSR0 : 1; + __IO uint8_t UBSR1 : 1; + __IO uint8_t UBSR2 : 1; + __IO uint8_t UBSR3 : 1; +} stc_usbethernetclk_upcr6_field_t; + +typedef struct stc_usbethernetclk_upcr7_field +{ + __IO uint8_t EPLLEN : 1; +} stc_usbethernetclk_upcr7_field_t; + +typedef struct stc_usbethernetclk_usben0_field +{ + __IO uint8_t USBEN0 : 1; +} stc_usbethernetclk_usben0_field_t; + +typedef struct stc_usbethernetclk_usben1_field +{ + __IO uint8_t USBEN1 : 1; +} stc_usbethernetclk_usben1_field_t; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* MFS03_UART_MODULE register bit fields */ +typedef struct stc_mfs03_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs03_uart_smr_field_t; + +typedef struct stc_mfs03_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs03_uart_scr_field_t; + +typedef struct stc_mfs03_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs03_uart_escr_field_t; + +typedef struct stc_mfs03_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_uart_ssr_field_t; + +typedef struct stc_mfs03_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_rdr_field_t; + +typedef struct stc_mfs03_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs03_uart_tdr_field_t; + +typedef struct stc_mfs03_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_uart_bgr_field_t; + +typedef struct stc_mfs03_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_uart_bgr1_field_t; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* MFS03_CSIO_MODULE register bit fields */ +typedef struct stc_mfs03_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs03_csio_smr_field_t; + +typedef struct stc_mfs03_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_csio_scr_field_t; + +typedef struct stc_mfs03_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs03_csio_escr_field_t; + +typedef struct stc_mfs03_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs03_csio_ssr_field_t; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* MFS03_LIN_MODULE register bit fields */ +typedef struct stc_mfs03_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs03_lin_smr_field_t; + +typedef struct stc_mfs03_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs03_lin_scr_field_t; + +typedef struct stc_mfs03_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs03_lin_escr_field_t; + +typedef struct stc_mfs03_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs03_lin_ssr_field_t; + +typedef struct stc_mfs03_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs03_lin_bgr_field_t; + +typedef struct stc_mfs03_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs03_lin_bgr1_field_t; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* MFS03_I2C_MODULE register bit fields */ +typedef struct stc_mfs03_i2c_smr_field +{ + uint8_t RESERVED1 : 2; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs03_i2c_smr_field_t; + +typedef struct stc_mfs03_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs03_i2c_ibcr_field_t; + +typedef struct stc_mfs03_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs03_i2c_ibsr_field_t; + +typedef struct stc_mfs03_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs03_i2c_ssr_field_t; + +typedef struct stc_mfs03_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs03_i2c_isba_field_t; + +typedef struct stc_mfs03_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs03_i2c_ismk_field_t; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* MFS47_UART_MODULE register bit fields */ +typedef struct stc_mfs47_uart_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs47_uart_smr_field_t; + +typedef struct stc_mfs47_uart_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t UPCL : 1; +} stc_mfs47_uart_scr_field_t; + +typedef struct stc_mfs47_uart_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t P : 1; + __IO uint8_t PEN : 1; + __IO uint8_t INV : 1; + __IO uint8_t ESBL : 1; + __IO uint8_t FLWEN : 1; +} stc_mfs47_uart_escr_field_t; + +typedef struct stc_mfs47_uart_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t PE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_uart_ssr_field_t; + +typedef struct stc_mfs47_uart_rdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_rdr_field_t; + +typedef struct stc_mfs47_uart_tdr_field +{ + uint16_t RESERVED1 : 8; + __IO uint16_t AD : 1; +} stc_mfs47_uart_tdr_field_t; + +typedef struct stc_mfs47_uart_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_uart_bgr_field_t; + +typedef struct stc_mfs47_uart_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_uart_bgr1_field_t; + +typedef struct stc_mfs47_uart_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_uart_fcr_field_t; + +typedef struct stc_mfs47_uart_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_uart_fcr0_field_t; + +typedef struct stc_mfs47_uart_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_uart_fcr1_field_t; + +typedef struct stc_mfs47_uart_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_uart_fbyte_field_t; + +typedef struct stc_mfs47_uart_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_uart_fbyte1_field_t; + +typedef struct stc_mfs47_uart_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_uart_fbyte2_field_t; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* MFS47_CSIO_MODULE register bit fields */ +typedef struct stc_mfs47_csio_smr_field +{ + __IO uint8_t SOE : 1; + __IO uint8_t SCKE : 1; + __IO uint8_t BDS : 1; + __IO uint8_t SCINV : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs47_csio_smr_field_t; + +typedef struct stc_mfs47_csio_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t SPI : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_csio_scr_field_t; + +typedef struct stc_mfs47_csio_escr_field +{ + __IO uint8_t L0 : 1; + __IO uint8_t L1 : 1; + __IO uint8_t L2 : 1; + __IO uint8_t WT0 : 1; + __IO uint8_t WT1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SOP : 1; +} stc_mfs47_csio_escr_field_t; + +typedef struct stc_mfs47_csio_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t REC : 1; +} stc_mfs47_csio_ssr_field_t; + +typedef struct stc_mfs47_csio_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_csio_fcr_field_t; + +typedef struct stc_mfs47_csio_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_csio_fcr0_field_t; + +typedef struct stc_mfs47_csio_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_csio_fcr1_field_t; + +typedef struct stc_mfs47_csio_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_csio_fbyte_field_t; + +typedef struct stc_mfs47_csio_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_csio_fbyte1_field_t; + +typedef struct stc_mfs47_csio_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_csio_fbyte2_field_t; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* MFS47_LIN_MODULE register bit fields */ +typedef struct stc_mfs47_lin_smr_field +{ + __IO uint8_t SOE : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t SBL : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs47_lin_smr_field_t; + +typedef struct stc_mfs47_lin_scr_field +{ + __IO uint8_t TXE : 1; + __IO uint8_t RXE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t LBR : 1; + __IO uint8_t MS : 1; + __IO uint8_t UPCL : 1; +} stc_mfs47_lin_scr_field_t; + +typedef struct stc_mfs47_lin_escr_field +{ + __IO uint8_t DEL0 : 1; + __IO uint8_t DEL1 : 1; + __IO uint8_t LBL0 : 1; + __IO uint8_t LBL1 : 1; + __IO uint8_t LBIE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t ESBL : 1; +} stc_mfs47_lin_escr_field_t; + +typedef struct stc_mfs47_lin_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t FRE : 1; + __IO uint8_t LBD : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t REC : 1; +} stc_mfs47_lin_ssr_field_t; + +typedef struct stc_mfs47_lin_bgr_field +{ + uint16_t RESERVED1 : 15; + __IO uint16_t EXT : 1; +} stc_mfs47_lin_bgr_field_t; + +typedef struct stc_mfs47_lin_bgr1_field +{ + uint8_t RESERVED1 : 7; + __IO uint8_t EXT : 1; +} stc_mfs47_lin_bgr1_field_t; + +typedef struct stc_mfs47_lin_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_lin_fcr_field_t; + +typedef struct stc_mfs47_lin_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_lin_fcr0_field_t; + +typedef struct stc_mfs47_lin_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_lin_fcr1_field_t; + +typedef struct stc_mfs47_lin_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_lin_fbyte_field_t; + +typedef struct stc_mfs47_lin_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_lin_fbyte1_field_t; + +typedef struct stc_mfs47_lin_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_lin_fbyte2_field_t; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* MFS47_I2C_MODULE register bit fields */ +typedef struct stc_mfs47_i2c_smr_field +{ + uint8_t RESERVED1 : 2; + __IO uint8_t TIE : 1; + __IO uint8_t RIE : 1; + __IO uint8_t WUCR : 1; + __IO uint8_t MD : 3; +} stc_mfs47_i2c_smr_field_t; + +typedef struct stc_mfs47_i2c_ibcr_field +{ + __IO uint8_t INT : 1; + __IO uint8_t BER : 1; + __IO uint8_t INTE : 1; + __IO uint8_t CNDE : 1; + __IO uint8_t WSEL : 1; + __IO uint8_t ACKE : 1; + __IO uint8_t SCC : 1; + __IO uint8_t MSS : 1; +} stc_mfs47_i2c_ibcr_field_t; + +typedef struct stc_mfs47_i2c_ibsr_field +{ + __IO uint8_t BB : 1; + __IO uint8_t SPC : 1; + __IO uint8_t RSC : 1; + __IO uint8_t AL : 1; + __IO uint8_t TRX : 1; + __IO uint8_t RSA : 1; + __IO uint8_t RACK : 1; + __IO uint8_t FBT : 1; +} stc_mfs47_i2c_ibsr_field_t; + +typedef struct stc_mfs47_i2c_ssr_field +{ + __IO uint8_t TBI : 1; + __IO uint8_t TDRE : 1; + __IO uint8_t RDRF : 1; + __IO uint8_t ORE : 1; + __IO uint8_t TBIE : 1; + __IO uint8_t DMA : 1; + __IO uint8_t TSET : 1; + __IO uint8_t REC : 1; +} stc_mfs47_i2c_ssr_field_t; + +typedef struct stc_mfs47_i2c_isba_field +{ + __IO uint8_t SA0 : 1; + __IO uint8_t SA1 : 1; + __IO uint8_t SA2 : 1; + __IO uint8_t SA3 : 1; + __IO uint8_t SA4 : 1; + __IO uint8_t SA5 : 1; + __IO uint8_t SA6 : 1; + __IO uint8_t SAEN : 1; +} stc_mfs47_i2c_isba_field_t; + +typedef struct stc_mfs47_i2c_ismk_field +{ + __IO uint8_t SM0 : 1; + __IO uint8_t SM1 : 1; + __IO uint8_t SM2 : 1; + __IO uint8_t SM3 : 1; + __IO uint8_t SM4 : 1; + __IO uint8_t SM5 : 1; + __IO uint8_t SM6 : 1; + __IO uint8_t EN : 1; +} stc_mfs47_i2c_ismk_field_t; + +typedef struct stc_mfs47_i2c_fcr_field +{ + __IO uint16_t FE1 : 1; + __IO uint16_t FE2 : 1; + __IO uint16_t FCL1 : 1; + __IO uint16_t FCL2 : 1; + __IO uint16_t FSET : 1; + __IO uint16_t FLD : 1; + __IO uint16_t FLST : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t FSEL : 1; + __IO uint16_t FTIE : 1; + __IO uint16_t FDRQ : 1; + __IO uint16_t FRIE : 1; + __IO uint16_t FLSTE : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t FTST0 : 1; + __IO uint16_t FTST1 : 1; +} stc_mfs47_i2c_fcr_field_t; + +typedef struct stc_mfs47_i2c_fcr0_field +{ + __IO uint8_t FE1 : 1; + __IO uint8_t FE2 : 1; + __IO uint8_t FCL1 : 1; + __IO uint8_t FCL2 : 1; + __IO uint8_t FSET : 1; + __IO uint8_t FLD : 1; + __IO uint8_t FLST : 1; +} stc_mfs47_i2c_fcr0_field_t; + +typedef struct stc_mfs47_i2c_fcr1_field +{ + __IO uint8_t FSEL : 1; + __IO uint8_t FTIE : 1; + __IO uint8_t FDRQ : 1; + __IO uint8_t FRIE : 1; + __IO uint8_t FLSTE : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t FTST0 : 1; + __IO uint8_t FTST1 : 1; +} stc_mfs47_i2c_fcr1_field_t; + +typedef struct stc_mfs47_i2c_fbyte_field +{ + __IO uint16_t FD0 : 1; + __IO uint16_t FD1 : 1; + __IO uint16_t FD2 : 1; + __IO uint16_t FD3 : 1; + __IO uint16_t FD4 : 1; + __IO uint16_t FD5 : 1; + __IO uint16_t FD6 : 1; + __IO uint16_t FD7 : 1; + __IO uint16_t FD8 : 1; + __IO uint16_t FD9 : 1; + __IO uint16_t FD10 : 1; + __IO uint16_t FD11 : 1; + __IO uint16_t FD12 : 1; + __IO uint16_t FD13 : 1; + __IO uint16_t FD14 : 1; + __IO uint16_t FD15 : 1; +} stc_mfs47_i2c_fbyte_field_t; + +typedef struct stc_mfs47_i2c_fbyte1_field +{ + __IO uint8_t FD0 : 1; + __IO uint8_t FD1 : 1; + __IO uint8_t FD2 : 1; + __IO uint8_t FD3 : 1; + __IO uint8_t FD4 : 1; + __IO uint8_t FD5 : 1; + __IO uint8_t FD6 : 1; + __IO uint8_t FD7 : 1; +} stc_mfs47_i2c_fbyte1_field_t; + +typedef struct stc_mfs47_i2c_fbyte2_field +{ + __IO uint8_t FD8 : 1; + __IO uint8_t FD9 : 1; + __IO uint8_t FD10 : 1; + __IO uint8_t FD11 : 1; + __IO uint8_t FD12 : 1; + __IO uint8_t FD13 : 1; + __IO uint8_t FD14 : 1; + __IO uint8_t FD15 : 1; +} stc_mfs47_i2c_fbyte2_field_t; + +/****************************************************************************** + * MFS_NFC_MODULE + ******************************************************************************/ +/* MFS_NFC_MODULE register bit fields */ +typedef struct stc_mfs_nfc_i2cdnf_field +{ + __IO uint16_t I2CDNF00 : 1; + __IO uint16_t I2CDNF01 : 1; + __IO uint16_t I2CDNF10 : 1; + __IO uint16_t I2CDNF11 : 1; + __IO uint16_t I2CDNF20 : 1; + __IO uint16_t I2CDNF21 : 1; + __IO uint16_t I2CDNF30 : 1; + __IO uint16_t I2CDNF31 : 1; + __IO uint16_t I2CDNF40 : 1; + __IO uint16_t I2CDNF41 : 1; + __IO uint16_t I2CDNF50 : 1; + __IO uint16_t I2CDNF51 : 1; + __IO uint16_t I2CDNF60 : 1; + __IO uint16_t I2CDNF61 : 1; + __IO uint16_t I2CDNF70 : 1; + __IO uint16_t I2CDNF71 : 1; +} stc_mfs_nfc_i2cdnf_field_t; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC_MODULE register bit fields */ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT : 1; + __IO uint8_t CRC32 : 1; + __IO uint8_t LTLEND : 1; + __IO uint8_t LSBFST : 1; + __IO uint8_t CRCLTE : 1; + __IO uint8_t CRCLSF : 1; + __IO uint8_t FXOR : 1; +} stc_crc_crccr_field_t; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* WC_MODULE register bit fields */ +typedef struct stc_wc_wcrd_field +{ + __IO uint8_t CTR0 : 1; + __IO uint8_t CTR1 : 1; + __IO uint8_t CTR2 : 1; + __IO uint8_t CTR3 : 1; + __IO uint8_t CTR4 : 1; + __IO uint8_t CTR5 : 1; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + __IO uint8_t RLC0 : 1; + __IO uint8_t RLC1 : 1; + __IO uint8_t RLC2 : 1; + __IO uint8_t RLC3 : 1; + __IO uint8_t RLC4 : 1; + __IO uint8_t RLC5 : 1; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + __IO uint8_t WCIF : 1; + __IO uint8_t WCIE : 1; + __IO uint8_t CS0 : 1; + __IO uint8_t CS1 : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t WCOP : 1; + __IO uint8_t WCEN : 1; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + __IO uint16_t SEL_IN : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t SEL_OUT : 1; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN : 1; + __IO uint8_t CLK_EN_R : 1; +} stc_wc_clk_en_field_t; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* EXBUS_MODULE register bit fields */ +typedef struct stc_exbus_mode0_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode0_field_t; + +typedef struct stc_exbus_mode1_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode1_field_t; + +typedef struct stc_exbus_mode2_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode2_field_t; + +typedef struct stc_exbus_mode3_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode3_field_t; + +typedef struct stc_exbus_mode4_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode4_field_t; + +typedef struct stc_exbus_mode5_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode5_field_t; + +typedef struct stc_exbus_mode6_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode6_field_t; + +typedef struct stc_exbus_mode7_field +{ + __IO uint32_t WDTH0 : 1; + __IO uint32_t WDTH1 : 1; + __IO uint32_t RBMON : 1; + __IO uint32_t WEOFF : 1; + __IO uint32_t NAND : 1; + __IO uint32_t PAGE : 1; + __IO uint32_t RDY : 1; + __IO uint32_t SHRTDOUT : 1; + __IO uint32_t MPXMODE : 1; + __IO uint32_t ALEINV : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t MPXDOFF : 1; + __IO uint32_t MPXCSOF : 1; + __IO uint32_t MOEXEUP : 1; +} stc_exbus_mode7_field_t; + +typedef struct stc_exbus_tim0_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim0_field_t; + +typedef struct stc_exbus_tim1_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim1_field_t; + +typedef struct stc_exbus_tim2_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim2_field_t; + +typedef struct stc_exbus_tim3_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim3_field_t; + +typedef struct stc_exbus_tim4_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim4_field_t; + +typedef struct stc_exbus_tim5_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim5_field_t; + +typedef struct stc_exbus_tim6_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim6_field_t; + +typedef struct stc_exbus_tim7_field +{ + __IO uint32_t RACC0 : 1; + __IO uint32_t RACC1 : 1; + __IO uint32_t RACC2 : 1; + __IO uint32_t RACC3 : 1; + __IO uint32_t RADC0 : 1; + __IO uint32_t RADC1 : 1; + __IO uint32_t RADC2 : 1; + __IO uint32_t RADC3 : 1; + __IO uint32_t FRADC0 : 1; + __IO uint32_t FRADC1 : 1; + __IO uint32_t FRADC2 : 1; + __IO uint32_t FRADC3 : 1; + __IO uint32_t RIDLC0 : 1; + __IO uint32_t RIDLC1 : 1; + __IO uint32_t RIDLC2 : 1; + __IO uint32_t RIDLC3 : 1; + __IO uint32_t WACC0 : 1; + __IO uint32_t WACC1 : 1; + __IO uint32_t WACC2 : 1; + __IO uint32_t WACC3 : 1; + __IO uint32_t WADC0 : 1; + __IO uint32_t WADC1 : 1; + __IO uint32_t WADC2 : 1; + __IO uint32_t WADC3 : 1; + __IO uint32_t WWEC0 : 1; + __IO uint32_t WWEC1 : 1; + __IO uint32_t WWEC2 : 1; + __IO uint32_t WWEC3 : 1; + __IO uint32_t WIDLC0 : 1; + __IO uint32_t WIDLC1 : 1; + __IO uint32_t WIDLC2 : 1; + __IO uint32_t WIDLC3 : 1; +} stc_exbus_tim7_field_t; + +typedef struct stc_exbus_area0_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area0_field_t; + +typedef struct stc_exbus_area1_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area1_field_t; + +typedef struct stc_exbus_area2_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area2_field_t; + +typedef struct stc_exbus_area3_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area3_field_t; + +typedef struct stc_exbus_area4_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area4_field_t; + +typedef struct stc_exbus_area5_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area5_field_t; + +typedef struct stc_exbus_area6_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area6_field_t; + +typedef struct stc_exbus_area7_field +{ + __IO uint32_t ADDR0 : 1; + __IO uint32_t ADDR1 : 1; + __IO uint32_t ADDR2 : 1; + __IO uint32_t ADDR3 : 1; + __IO uint32_t ADDR4 : 1; + __IO uint32_t ADDR5 : 1; + __IO uint32_t ADDR6 : 1; + __IO uint32_t ADDR7 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MASK0 : 1; + __IO uint32_t MASK1 : 1; + __IO uint32_t MASK2 : 1; + __IO uint32_t MASK3 : 1; + __IO uint32_t MASK4 : 1; + __IO uint32_t MASK5 : 1; + __IO uint32_t MASK6 : 1; +} stc_exbus_area7_field_t; + +typedef struct stc_exbus_atim0_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim0_field_t; + +typedef struct stc_exbus_atim1_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim1_field_t; + +typedef struct stc_exbus_atim2_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim2_field_t; + +typedef struct stc_exbus_atim3_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim3_field_t; + +typedef struct stc_exbus_atim4_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim4_field_t; + +typedef struct stc_exbus_atim5_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim5_field_t; + +typedef struct stc_exbus_atim6_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim6_field_t; + +typedef struct stc_exbus_atim7_field +{ + __IO uint16_t ALC0 : 1; + __IO uint16_t ALC1 : 1; + __IO uint16_t ALC2 : 1; + __IO uint16_t ALC3 : 1; + __IO uint16_t ALES0 : 1; + __IO uint16_t ALES1 : 1; + __IO uint16_t ALES2 : 1; + __IO uint16_t ALES3 : 1; + __IO uint16_t ALEW0 : 1; + __IO uint16_t ALEW1 : 1; + __IO uint16_t ALEW2 : 1; + __IO uint16_t ALEW3 : 1; +} stc_exbus_atim7_field_t; + +typedef struct stc_exbus_dclkr_field +{ + __IO uint8_t MDIV0 : 1; + __IO uint8_t MDIV1 : 1; + __IO uint8_t MDIV2 : 1; + __IO uint8_t MDIV3 : 1; + __IO uint8_t MCLKON : 1; +} stc_exbus_dclkr_field_t; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB_MODULE register bit fields */ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST : 1; + __IO uint16_t URST : 1; + __IO uint16_t SOFIRE : 1; + __IO uint16_t DIRE : 1; + __IO uint16_t CNNIRE : 1; + __IO uint16_t CMPIRE : 1; + __IO uint16_t URIRE : 1; + __IO uint16_t RWKIRE : 1; + __IO uint16_t RETRY : 1; + __IO uint16_t CANCEL : 1; + __IO uint16_t SOFSTEP : 1; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hcnt0_field +{ + __IO uint8_t HOST : 1; + __IO uint8_t URST : 1; + __IO uint8_t SOFIRE : 1; + __IO uint8_t DIRE : 1; + __IO uint8_t CNNIRE : 1; + __IO uint8_t CMPIRE : 1; + __IO uint8_t URIRE : 1; + __IO uint8_t RWKIRE : 1; +} stc_usb_hcnt0_field_t; + +typedef struct stc_usb_hcnt1_field +{ + __IO uint8_t RETRY : 1; + __IO uint8_t CANCEL : 1; + __IO uint8_t SOFSTEP : 1; +} stc_usb_hcnt1_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ : 1; + __IO uint8_t DIRQ : 1; + __IO uint8_t CNNIRQ : 1; + __IO uint8_t CMPIRQ : 1; + __IO uint8_t URIRQ : 1; + __IO uint8_t RWKIRQ : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TCAN : 1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + __IO uint8_t HS0 : 1; + __IO uint8_t HS1 : 1; + __IO uint8_t STUFF : 1; + __IO uint8_t TGERR : 1; + __IO uint8_t CRC : 1; + __IO uint8_t TOUT : 1; + __IO uint8_t RERR : 1; + __IO uint8_t LSTOF : 1; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT : 1; + __IO uint8_t TMODE : 1; + __IO uint8_t SUSP : 1; + __IO uint8_t SOFBUSY : 1; + __IO uint8_t CLKSEL : 1; + __IO uint8_t ALIVE : 1; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + __IO uint8_t FRAMECOMP0 : 1; + __IO uint8_t FRAMECOMP1 : 1; + __IO uint8_t FRAMECOMP2 : 1; + __IO uint8_t FRAMECOMP3 : 1; + __IO uint8_t FRAMECOMP4 : 1; + __IO uint8_t FRAMECOMP5 : 1; + __IO uint8_t FRAMECOMP6 : 1; + __IO uint8_t FRAMECOMP7 : 1; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + __IO uint16_t RTIMER0 : 1; + __IO uint16_t RTIMER1 : 1; + __IO uint16_t RTIMER2 : 1; + __IO uint16_t RTIMER3 : 1; + __IO uint16_t RTIMER4 : 1; + __IO uint16_t RTIMER5 : 1; + __IO uint16_t RTIMER6 : 1; + __IO uint16_t RTIMER7 : 1; + __IO uint16_t RTIMER8 : 1; + __IO uint16_t RTIMER9 : 1; + __IO uint16_t RTIMER10 : 1; + __IO uint16_t RTIMER11 : 1; + __IO uint16_t RTIMER12 : 1; + __IO uint16_t RTIMER13 : 1; + __IO uint16_t RTIMER14 : 1; + __IO uint16_t RTIMER15 : 1; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer0_field +{ + __IO uint8_t RTIMER00 : 1; + __IO uint8_t RTIMER01 : 1; + __IO uint8_t RTIMER02 : 1; + __IO uint8_t RTIMER03 : 1; + __IO uint8_t RTIMER04 : 1; + __IO uint8_t RTIMER05 : 1; + __IO uint8_t RTIMER06 : 1; + __IO uint8_t RTIMER07 : 1; +} stc_usb_hrtimer0_field_t; + +typedef struct stc_usb_hrtimer1_field +{ + __IO uint8_t RTIMER10 : 1; + __IO uint8_t RTIMER11 : 1; + __IO uint8_t RTIMER12 : 1; + __IO uint8_t RTIMER13 : 1; + __IO uint8_t RTIMER14 : 1; + __IO uint8_t RTIMER15 : 1; + __IO uint8_t RTIMER16 : 1; + __IO uint8_t RTIMER17 : 1; +} stc_usb_hrtimer1_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + __IO uint8_t RTIMER20 : 1; + __IO uint8_t RTIMER21 : 1; + __IO uint8_t RTIMER22 : 1; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + __IO uint8_t ADDRESS0 : 1; + __IO uint8_t ADDRESS1 : 1; + __IO uint8_t ADDRESS2 : 1; + __IO uint8_t ADDRESS3 : 1; + __IO uint8_t ADDRESS4 : 1; + __IO uint8_t ADDRESS5 : 1; + __IO uint8_t ADDRESS6 : 1; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + __IO uint16_t EOF0 : 1; + __IO uint16_t EOF1 : 1; + __IO uint16_t EOF2 : 1; + __IO uint16_t EOF3 : 1; + __IO uint16_t EOF4 : 1; + __IO uint16_t EOF5 : 1; + __IO uint16_t EOF6 : 1; + __IO uint16_t EOF7 : 1; + __IO uint16_t EOF8 : 1; + __IO uint16_t EOF9 : 1; + __IO uint16_t EOF10 : 1; + __IO uint16_t EOF11 : 1; + __IO uint16_t EOF12 : 1; + __IO uint16_t EOF13 : 1; + __IO uint16_t EOF14 : 1; + __IO uint16_t EOF15 : 1; +} stc_usb_heof_field_t; + +typedef struct stc_usb_heof0_field +{ + __IO uint8_t EOF00 : 1; + __IO uint8_t EOF01 : 1; + __IO uint8_t EOF02 : 1; + __IO uint8_t EOF03 : 1; + __IO uint8_t EOF04 : 1; + __IO uint8_t EOF05 : 1; + __IO uint8_t EOF06 : 1; + __IO uint8_t EOF07 : 1; +} stc_usb_heof0_field_t; + +typedef struct stc_usb_heof1_field +{ + __IO uint8_t EOF10 : 1; + __IO uint8_t EOF11 : 1; + __IO uint8_t EOF12 : 1; + __IO uint8_t EOF13 : 1; + __IO uint8_t EOF14 : 1; + __IO uint8_t EOF15 : 1; +} stc_usb_heof1_field_t; + +typedef struct stc_usb_hframe_field +{ + __IO uint16_t FRAME0 : 1; + __IO uint16_t FRAME1 : 1; + __IO uint16_t FRAME2 : 1; + __IO uint16_t FRAME3 : 1; + __IO uint16_t FRAME4 : 1; + __IO uint16_t FRAME5 : 1; + __IO uint16_t FRAME6 : 1; + __IO uint16_t FRAME7 : 1; + __IO uint16_t FRAME8 : 1; + __IO uint16_t FRAME9 : 1; + __IO uint16_t FRAME10 : 1; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_hframe0_field +{ + __IO uint8_t FRAME00 : 1; + __IO uint8_t FRAME01 : 1; + __IO uint8_t FRAME02 : 1; + __IO uint8_t FRAME03 : 1; + __IO uint8_t FRAME04 : 1; + __IO uint8_t FRAME05 : 1; + __IO uint8_t FRAME06 : 1; + __IO uint8_t FRAME07 : 1; +} stc_usb_hframe0_field_t; + +typedef struct stc_usb_hframe1_field +{ + __IO uint8_t FRAME10 : 1; + __IO uint8_t FRAME11 : 1; + __IO uint8_t FRAME12 : 1; + __IO uint8_t FRAME13 : 1; +} stc_usb_hframe1_field_t; + +typedef struct stc_usb_htoken_field +{ + __IO uint8_t ENDPT0 : 1; + __IO uint8_t ENDPT1 : 1; + __IO uint8_t ENDPT2 : 1; + __IO uint8_t ENDPT3 : 1; + __IO uint8_t TKNEN0 : 1; + __IO uint8_t TKNEN1 : 1; + __IO uint8_t TKNEN2 : 1; + __IO uint8_t TGGL : 1; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC : 1; + __IO uint16_t RFBK : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t STALCLREN : 1; + __IO uint16_t USTP : 1; + __IO uint16_t HCONX : 1; + __IO uint16_t RESUM : 1; + __IO uint16_t RST : 1; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + __IO uint16_t PKS00 : 1; + __IO uint16_t PKS01 : 1; + __IO uint16_t PKS02 : 1; + __IO uint16_t PKS03 : 1; + __IO uint16_t PKS04 : 1; + __IO uint16_t PKS05 : 1; + __IO uint16_t PKS06 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + __IO uint16_t PKS10 : 1; + __IO uint16_t PKS11 : 1; + __IO uint16_t PKS12 : 1; + __IO uint16_t PKS13 : 1; + __IO uint16_t PKS14 : 1; + __IO uint16_t PKS15 : 1; + __IO uint16_t PKS16 : 1; + __IO uint16_t PKS17 : 1; + __IO uint16_t PKS18 : 1; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + __IO uint16_t PKS20 : 1; + __IO uint16_t PKS21 : 1; + __IO uint16_t PKS22 : 1; + __IO uint16_t PKS23 : 1; + __IO uint16_t PKS24 : 1; + __IO uint16_t PKS25 : 1; + __IO uint16_t PKS26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + __IO uint16_t PKS30 : 1; + __IO uint16_t PKS31 : 1; + __IO uint16_t PKS32 : 1; + __IO uint16_t PKS33 : 1; + __IO uint16_t PKS34 : 1; + __IO uint16_t PKS35 : 1; + __IO uint16_t PKS36 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + __IO uint16_t PKS40 : 1; + __IO uint16_t PKS41 : 1; + __IO uint16_t PKS42 : 1; + __IO uint16_t PKS43 : 1; + __IO uint16_t PKS44 : 1; + __IO uint16_t PKS45 : 1; + __IO uint16_t PKS46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + __IO uint16_t PKS50 : 1; + __IO uint16_t PKS51 : 1; + __IO uint16_t PKS52 : 1; + __IO uint16_t PKS53 : 1; + __IO uint16_t PKS54 : 1; + __IO uint16_t PKS55 : 1; + __IO uint16_t PKS56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + __IO uint16_t TMSP0 : 1; + __IO uint16_t TMSP1 : 1; + __IO uint16_t TMSP2 : 1; + __IO uint16_t TMSP3 : 1; + __IO uint16_t TMSP4 : 1; + __IO uint16_t TMSP5 : 1; + __IO uint16_t TMSP6 : 1; + __IO uint16_t TMSP7 : 1; + __IO uint16_t TMSP8 : 1; + __IO uint16_t TMSP9 : 1; + __IO uint16_t TMSP10 : 1; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF : 1; + __IO uint8_t SETP : 1; + __IO uint8_t WKUP : 1; + __IO uint8_t BRST : 1; + __IO uint8_t SOF : 1; + __IO uint8_t SUSP : 1; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE : 1; + __IO uint8_t CONFN : 1; + __IO uint8_t WKUPIE : 1; + __IO uint8_t BRSTIE : 1; + __IO uint8_t SOFIE : 1; + __IO uint8_t SUSPIE : 1; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + uint16_t RESERVED1 : 10; + __IO uint16_t DRQI : 1; + uint16_t RESERVED2 : 3; + __IO uint16_t DRQIIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + __IO uint16_t SIZE0 : 1; + __IO uint16_t SIZE1 : 1; + __IO uint16_t SIZE2 : 1; + __IO uint16_t SIZE3 : 1; + __IO uint16_t SIZE4 : 1; + __IO uint16_t SIZE5 : 1; + __IO uint16_t SIZE6 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQO : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQOIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + __IO uint16_t SIZE10 : 1; + __IO uint16_t SIZE11 : 1; + __IO uint16_t SIZE12 : 1; + __IO uint16_t SIZE13 : 1; + __IO uint16_t SIZE14 : 1; + __IO uint16_t SIZE15 : 1; + __IO uint16_t SIZE16 : 1; + __IO uint16_t SIZE17 : 1; + __IO uint16_t SIZE18 : 1; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + __IO uint16_t SIZE20 : 1; + __IO uint16_t SIZE21 : 1; + __IO uint16_t SIZE22 : 1; + __IO uint16_t SIZE23 : 1; + __IO uint16_t SIZE24 : 1; + __IO uint16_t SIZE25 : 1; + __IO uint16_t SIZE26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep4s_field +{ + __IO uint16_t SIZE40 : 1; + __IO uint16_t SIZE41 : 1; + __IO uint16_t SIZE42 : 1; + __IO uint16_t SIZE43 : 1; + __IO uint16_t SIZE44 : 1; + __IO uint16_t SIZE45 : 1; + __IO uint16_t SIZE46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + __IO uint16_t SIZE50 : 1; + __IO uint16_t SIZE51 : 1; + __IO uint16_t SIZE52 : 1; + __IO uint16_t SIZE53 : 1; + __IO uint16_t SIZE54 : 1; + __IO uint16_t SIZE55 : 1; + __IO uint16_t SIZE56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usb_ep5s_field_t; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMAC_MODULE register bit fields */ +typedef struct stc_dmac_dmacr_field +{ + uint32_t RESERVED1 : 24; + __IO uint32_t DH0 : 1; + __IO uint32_t DH1 : 1; + __IO uint32_t DH2 : 1; + __IO uint32_t DH3 : 1; + __IO uint32_t PR : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t DS : 1; + __IO uint32_t DE : 1; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + __IO uint32_t TC0 : 1; + __IO uint32_t TC1 : 1; + __IO uint32_t TC2 : 1; + __IO uint32_t TC3 : 1; + __IO uint32_t TC4 : 1; + __IO uint32_t TC5 : 1; + __IO uint32_t TC6 : 1; + __IO uint32_t TC7 : 1; + __IO uint32_t TC8 : 1; + __IO uint32_t TC9 : 1; + __IO uint32_t TC10 : 1; + __IO uint32_t TC11 : 1; + __IO uint32_t TC12 : 1; + __IO uint32_t TC13 : 1; + __IO uint32_t TC14 : 1; + __IO uint32_t TC15 : 1; + __IO uint32_t BC0 : 1; + __IO uint32_t BC1 : 1; + __IO uint32_t BC2 : 1; + __IO uint32_t BC3 : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t IS0 : 1; + __IO uint32_t IS1 : 1; + __IO uint32_t IS2 : 1; + __IO uint32_t IS3 : 1; + __IO uint32_t IS4 : 1; + __IO uint32_t IS5 : 1; + __IO uint32_t ST : 1; + __IO uint32_t PB : 1; + __IO uint32_t EB : 1; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + __IO uint32_t EM : 1; + uint32_t RESERVED1 : 15; + __IO uint32_t SS0 : 1; + __IO uint32_t SS1 : 1; + __IO uint32_t SS2 : 1; + __IO uint32_t CI : 1; + __IO uint32_t EI : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t TW0 : 1; + __IO uint32_t TW1 : 1; + __IO uint32_t MS0 : 1; + __IO uint32_t MS1 : 1; +} stc_dmac_dmacb7_field_t; + +/****************************************************************************** + * ETHERNET_MAC_MODULE + ******************************************************************************/ +/* ETHERNET_MAC_MODULE register bit fields */ +typedef struct stc_ethernet_mac_mcr_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t DC : 1; + __IO uint32_t BL0 : 1; + __IO uint32_t BL1 : 1; + __IO uint32_t ACS : 1; + __IO uint32_t LUD : 1; + __IO uint32_t DR : 1; + __IO uint32_t IPC : 1; + __IO uint32_t DM : 1; + __IO uint32_t LM : 1; + __IO uint32_t DO : 1; + __IO uint32_t FES : 1; + __IO uint32_t PS : 1; + __IO uint32_t DCRS : 1; + __IO uint32_t IFG0 : 1; + __IO uint32_t IFG1 : 1; + __IO uint32_t IFG2 : 1; + __IO uint32_t JE : 1; + __IO uint32_t BE : 1; + __IO uint32_t JD : 1; + __IO uint32_t WD : 1; + __IO uint32_t TC : 1; + __IO uint32_t CST : 1; +} stc_ethernet_mac_mcr_field_t; + +typedef struct stc_ethernet_mac_mffr_field +{ + __IO uint32_t PR : 1; + __IO uint32_t HUC : 1; + __IO uint32_t HMC : 1; + __IO uint32_t DAIF : 1; + __IO uint32_t PM : 1; + __IO uint32_t DB : 1; + __IO uint32_t PCF0 : 1; + __IO uint32_t PCF1 : 1; + __IO uint32_t SAIF : 1; + __IO uint32_t SAF : 1; + __IO uint32_t HPF : 1; + uint32_t RESERVED1 :20; + __IO uint32_t RA : 1; +} stc_ethernet_mac_mffr_field_t; + +typedef struct stc_ethernet_mac_mhtrh_field +{ + __IO uint32_t HTH0 : 1; + __IO uint32_t HTH1 : 1; + __IO uint32_t HTH2 : 1; + __IO uint32_t HTH3 : 1; + __IO uint32_t HTH4 : 1; + __IO uint32_t HTH5 : 1; + __IO uint32_t HTH6 : 1; + __IO uint32_t HTH7 : 1; + __IO uint32_t HTH8 : 1; + __IO uint32_t HTH9 : 1; + __IO uint32_t HTH10 : 1; + __IO uint32_t HTH11 : 1; + __IO uint32_t HTH12 : 1; + __IO uint32_t HTH13 : 1; + __IO uint32_t HTH14 : 1; + __IO uint32_t HTH15 : 1; + __IO uint32_t HTH16 : 1; + __IO uint32_t HTH17 : 1; + __IO uint32_t HTH18 : 1; + __IO uint32_t HTH19 : 1; + __IO uint32_t HTH20 : 1; + __IO uint32_t HTH21 : 1; + __IO uint32_t HTH22 : 1; + __IO uint32_t HTH23 : 1; + __IO uint32_t HTH24 : 1; + __IO uint32_t HTH25 : 1; + __IO uint32_t HTH26 : 1; + __IO uint32_t HTH27 : 1; + __IO uint32_t HTH28 : 1; + __IO uint32_t HTH29 : 1; + __IO uint32_t HTH30 : 1; + __IO uint32_t HTH31 : 1; +} stc_ethernet_mac_mhtrh_field_t; + +typedef struct stc_ethernet_mac_mhtrl_field +{ + __IO uint32_t HTL0 : 1; + __IO uint32_t HTL1 : 1; + __IO uint32_t HTL2 : 1; + __IO uint32_t HTL3 : 1; + __IO uint32_t HTL4 : 1; + __IO uint32_t HTL5 : 1; + __IO uint32_t HTL6 : 1; + __IO uint32_t HTL7 : 1; + __IO uint32_t HTL8 : 1; + __IO uint32_t HTL9 : 1; + __IO uint32_t HTL10 : 1; + __IO uint32_t HTL11 : 1; + __IO uint32_t HTL12 : 1; + __IO uint32_t HTL13 : 1; + __IO uint32_t HTL14 : 1; + __IO uint32_t HTL15 : 1; + __IO uint32_t HTL16 : 1; + __IO uint32_t HTL17 : 1; + __IO uint32_t HTL18 : 1; + __IO uint32_t HTL19 : 1; + __IO uint32_t HTL20 : 1; + __IO uint32_t HTL21 : 1; + __IO uint32_t HTL22 : 1; + __IO uint32_t HTL23 : 1; + __IO uint32_t HTL24 : 1; + __IO uint32_t HTL25 : 1; + __IO uint32_t HTL26 : 1; + __IO uint32_t HTL27 : 1; + __IO uint32_t HTL28 : 1; + __IO uint32_t HTL29 : 1; + __IO uint32_t HTL30 : 1; + __IO uint32_t HTL31 : 1; +} stc_ethernet_mac_mhtrl_field_t; + +typedef struct stc_ethernet_mac_gar_field +{ + __IO uint32_t GB : 1; + __IO uint32_t GW : 1; + __IO uint32_t CR0 : 1; + __IO uint32_t CR1 : 1; + __IO uint32_t CR2 : 1; + __IO uint32_t CR3 : 1; + __IO uint32_t GR0 : 1; + __IO uint32_t GR1 : 1; + __IO uint32_t GR2 : 1; + __IO uint32_t GR3 : 1; + __IO uint32_t GR4 : 1; + __IO uint32_t PA0 : 1; + __IO uint32_t PA1 : 1; + __IO uint32_t PA2 : 1; + __IO uint32_t PA3 : 1; + __IO uint32_t PA4 : 1; +} stc_ethernet_mac_gar_field_t; + +typedef struct stc_ethernet_mac_gdr_field +{ + __IO uint32_t GD0 : 1; + __IO uint32_t GD1 : 1; + __IO uint32_t GD2 : 1; + __IO uint32_t GD3 : 1; + __IO uint32_t GD4 : 1; + __IO uint32_t GD5 : 1; + __IO uint32_t GD6 : 1; + __IO uint32_t GD7 : 1; + __IO uint32_t GD8 : 1; + __IO uint32_t GD9 : 1; + __IO uint32_t GD10 : 1; + __IO uint32_t GD11 : 1; + __IO uint32_t GD12 : 1; + __IO uint32_t GD13 : 1; + __IO uint32_t GD14 : 1; + __IO uint32_t GD15 : 1; +} stc_ethernet_mac_gdr_field_t; + +typedef struct stc_ethernet_mac_fcr_field +{ + __IO uint32_t FCB_BPA : 1; + __IO uint32_t TFE : 1; + __IO uint32_t RFE : 1; + __IO uint32_t UP : 1; + __IO uint32_t PLT0 : 1; + __IO uint32_t PLT1 : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t DZPQ : 1; + uint32_t RESERVED2 : 8; + __IO uint32_t PT0 : 1; + __IO uint32_t PT1 : 1; + __IO uint32_t PT2 : 1; + __IO uint32_t PT3 : 1; + __IO uint32_t PT4 : 1; + __IO uint32_t PT5 : 1; + __IO uint32_t PT6 : 1; + __IO uint32_t PT7 : 1; + __IO uint32_t PT8 : 1; + __IO uint32_t PT9 : 1; + __IO uint32_t PT10 : 1; + __IO uint32_t PT11 : 1; + __IO uint32_t PT12 : 1; + __IO uint32_t PT13 : 1; + __IO uint32_t PT14 : 1; + __IO uint32_t PT15 : 1; +} stc_ethernet_mac_fcr_field_t; + +typedef struct stc_ethernet_mac_vtr_field +{ + __IO uint32_t VL0 : 1; + __IO uint32_t VL1 : 1; + __IO uint32_t VL2 : 1; + __IO uint32_t VL3 : 1; + __IO uint32_t VL4 : 1; + __IO uint32_t VL5 : 1; + __IO uint32_t VL6 : 1; + __IO uint32_t VL7 : 1; + __IO uint32_t VL8 : 1; + __IO uint32_t VL9 : 1; + __IO uint32_t VL10 : 1; + __IO uint32_t VL11 : 1; + __IO uint32_t VL12 : 1; + __IO uint32_t VL13 : 1; + __IO uint32_t VL14 : 1; + __IO uint32_t VL15 : 1; + __IO uint32_t ETV : 1; +} stc_ethernet_mac_vtr_field_t; + +typedef struct stc_ethernet_mac_rwffr_field +{ + __IO uint32_t RWFFR0 : 1; + __IO uint32_t RWFFR1 : 1; + __IO uint32_t RWFFR2 : 1; + __IO uint32_t RWFFR3 : 1; + __IO uint32_t RWFFR4 : 1; + __IO uint32_t RWFFR5 : 1; + __IO uint32_t RWFFR6 : 1; + __IO uint32_t RWFFR7 : 1; + __IO uint32_t RWFFR8 : 1; + __IO uint32_t RWFFR9 : 1; + __IO uint32_t RWFFR10 : 1; + __IO uint32_t RWFFR11 : 1; + __IO uint32_t RWFFR12 : 1; + __IO uint32_t RWFFR13 : 1; + __IO uint32_t RWFFR14 : 1; + __IO uint32_t RWFFR15 : 1; + __IO uint32_t RWFFR16 : 1; + __IO uint32_t RWFFR17 : 1; + __IO uint32_t RWFFR18 : 1; + __IO uint32_t RWFFR19 : 1; + __IO uint32_t RWFFR20 : 1; + __IO uint32_t RWFFR21 : 1; + __IO uint32_t RWFFR22 : 1; + __IO uint32_t RWFFR23 : 1; + __IO uint32_t RWFFR24 : 1; + __IO uint32_t RWFFR25 : 1; + __IO uint32_t RWFFR26 : 1; + __IO uint32_t RWFFR27 : 1; + __IO uint32_t RWFFR28 : 1; + __IO uint32_t RWFFR29 : 1; + __IO uint32_t RWFFR30 : 1; + __IO uint32_t RWFFR31 : 1; +} stc_ethernet_mac_rwffr_field_t; + +typedef struct stc_ethernet_mac_pmtr_field +{ + __IO uint32_t PD : 1; + __IO uint32_t MPE : 1; + __IO uint32_t WFE : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t MPR : 1; + __IO uint32_t WPR : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t GU : 1; + uint32_t RESERVED3 :21; + __IO uint32_t RWFFRPR : 1; +} stc_ethernet_mac_pmtr_field_t; + +typedef struct stc_ethernet_mac_lpicsr_field +{ + __IO uint32_t TLPIEN : 1; + __IO uint32_t TLPIEX : 1; + __IO uint32_t RLPIEN : 1; + __IO uint32_t RLPIEX : 1; + uint32_t RESERVED1 : 4; + __IO uint32_t TLPIST : 1; + __IO uint32_t RLPIST : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t LPIEN : 1; + __IO uint32_t PLS : 1; + __IO uint32_t PLSEN : 1; + __IO uint32_t LPITXA : 1; +} stc_ethernet_mac_lpicsr_field_t; + +typedef struct stc_ethernet_mac_lpitcr_field +{ + __IO uint32_t TWT0 : 1; + __IO uint32_t TWT1 : 1; + __IO uint32_t TWT2 : 1; + __IO uint32_t TWT3 : 1; + __IO uint32_t TWT4 : 1; + __IO uint32_t TWT5 : 1; + __IO uint32_t TWT6 : 1; + __IO uint32_t TWT7 : 1; + __IO uint32_t TWT8 : 1; + __IO uint32_t TWT9 : 1; + __IO uint32_t TWT10 : 1; + __IO uint32_t TWT11 : 1; + __IO uint32_t TWT12 : 1; + __IO uint32_t TWT13 : 1; + __IO uint32_t TWT14 : 1; + __IO uint32_t TWT15 : 1; + __IO uint32_t LIT0 : 1; + __IO uint32_t LIT1 : 1; + __IO uint32_t LIT2 : 1; + __IO uint32_t LIT3 : 1; + __IO uint32_t LIT4 : 1; + __IO uint32_t LIT5 : 1; + __IO uint32_t LIT6 : 1; + __IO uint32_t LIT7 : 1; + __IO uint32_t LIT8 : 1; + __IO uint32_t LIT9 : 1; +} stc_ethernet_mac_lpitcr_field_t; + +typedef struct stc_ethernet_mac_isr_field +{ + __IO uint32_t RGIS : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t PIS : 1; + __IO uint32_t MIS : 1; + __IO uint32_t RIS : 1; + __IO uint32_t TIS : 1; + __IO uint32_t COIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TSIS : 1; + __IO uint32_t LPIIS : 1; +} stc_ethernet_mac_isr_field_t; + +typedef struct stc_ethernet_mac_imr_field +{ + __IO uint32_t RGIM : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t PIM : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t TSIM : 1; + __IO uint32_t LPIIM : 1; +} stc_ethernet_mac_imr_field_t; + +typedef struct stc_ethernet_mac_mar0h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 :15; + __IO uint32_t MO : 1; +} stc_ethernet_mac_mar0h_field_t; + +typedef struct stc_ethernet_mac_mar0l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar0l_field_t; + +typedef struct stc_ethernet_mac_mar1h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar1h_field_t; + +typedef struct stc_ethernet_mac_mar1l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar1l_field_t; + +typedef struct stc_ethernet_mac_mar2h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar2h_field_t; + +typedef struct stc_ethernet_mac_mar2l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar2l_field_t; + +typedef struct stc_ethernet_mac_mar3h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar3h_field_t; + +typedef struct stc_ethernet_mac_mar3l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar3l_field_t; + +typedef struct stc_ethernet_mac_mar4h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar4h_field_t; + +typedef struct stc_ethernet_mac_mar4l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar4l_field_t; + +typedef struct stc_ethernet_mac_mar5h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar5h_field_t; + +typedef struct stc_ethernet_mac_mar5l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar5l_field_t; + +typedef struct stc_ethernet_mac_mar6h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar6h_field_t; + +typedef struct stc_ethernet_mac_mar6l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar6l_field_t; + +typedef struct stc_ethernet_mac_mar7h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar7h_field_t; + +typedef struct stc_ethernet_mac_mar7l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar7l_field_t; + +typedef struct stc_ethernet_mac_mar8h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar8h_field_t; + +typedef struct stc_ethernet_mac_mar8l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar8l_field_t; + +typedef struct stc_ethernet_mac_mar9h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar9h_field_t; + +typedef struct stc_ethernet_mac_mar9l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar9l_field_t; + +typedef struct stc_ethernet_mac_mar10h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar10h_field_t; + +typedef struct stc_ethernet_mac_mar10l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar10l_field_t; + +typedef struct stc_ethernet_mac_mar11h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar11h_field_t; + +typedef struct stc_ethernet_mac_mar11l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar11l_field_t; + +typedef struct stc_ethernet_mac_mar12h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar12h_field_t; + +typedef struct stc_ethernet_mac_mar12l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar12l_field_t; + +typedef struct stc_ethernet_mac_mar13h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar13h_field_t; + +typedef struct stc_ethernet_mac_mar13l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar13l_field_t; + +typedef struct stc_ethernet_mac_mar14h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar14h_field_t; + +typedef struct stc_ethernet_mac_mar14l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar14l_field_t; + +typedef struct stc_ethernet_mac_mar15h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar15h_field_t; + +typedef struct stc_ethernet_mac_mar15l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar15l_field_t; + +typedef struct stc_ethernet_mac_rgsr_field +{ + __IO uint32_t LM : 1; + __IO uint32_t LSP0 : 1; + __IO uint32_t LSP1 : 1; + __IO uint32_t LS : 1; +} stc_ethernet_mac_rgsr_field_t; + +typedef struct stc_ethernet_mac_tscr_field +{ + __IO uint32_t TSE : 1; + __IO uint32_t TFCU : 1; + __IO uint32_t TSI : 1; + __IO uint32_t TSU : 1; + __IO uint32_t TITE : 1; + __IO uint32_t TARU : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t TSEA : 1; + __IO uint32_t TSDB : 1; + __IO uint32_t TSV2E : 1; + __IO uint32_t TETSP : 1; + __IO uint32_t TSIP6E : 1; + __IO uint32_t TSIP4E : 1; + __IO uint32_t TETSEM : 1; + __IO uint32_t TSMRM : 1; + __IO uint32_t TSPS0 : 1; + __IO uint32_t TSPS1 : 1; + __IO uint32_t TSENMF : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t ATSFC : 1; +} stc_ethernet_mac_tscr_field_t; + +typedef struct stc_ethernet_mac_ssir_field +{ + __IO uint32_t SSINC0 : 1; + __IO uint32_t SSINC1 : 1; + __IO uint32_t SSINC2 : 1; + __IO uint32_t SSINC3 : 1; + __IO uint32_t SSINC4 : 1; + __IO uint32_t SSINC5 : 1; + __IO uint32_t SSINC6 : 1; + __IO uint32_t SSINC7 : 1; +} stc_ethernet_mac_ssir_field_t; + +typedef struct stc_ethernet_mac_stsr_field +{ + __IO uint32_t TSS0 : 1; + __IO uint32_t TSS1 : 1; + __IO uint32_t TSS2 : 1; + __IO uint32_t TSS3 : 1; + __IO uint32_t TSS4 : 1; + __IO uint32_t TSS5 : 1; + __IO uint32_t TSS6 : 1; + __IO uint32_t TSS7 : 1; + __IO uint32_t TSS8 : 1; + __IO uint32_t TSS9 : 1; + __IO uint32_t TSS10 : 1; + __IO uint32_t TSS11 : 1; + __IO uint32_t TSS12 : 1; + __IO uint32_t TSS13 : 1; + __IO uint32_t TSS14 : 1; + __IO uint32_t TSS15 : 1; + __IO uint32_t TSS16 : 1; + __IO uint32_t TSS17 : 1; + __IO uint32_t TSS18 : 1; + __IO uint32_t TSS19 : 1; + __IO uint32_t TSS20 : 1; + __IO uint32_t TSS21 : 1; + __IO uint32_t TSS22 : 1; + __IO uint32_t TSS23 : 1; + __IO uint32_t TSS24 : 1; + __IO uint32_t TSS25 : 1; + __IO uint32_t TSS26 : 1; + __IO uint32_t TSS27 : 1; + __IO uint32_t TSS28 : 1; + __IO uint32_t TSS29 : 1; + __IO uint32_t TSS30 : 1; + __IO uint32_t TSS31 : 1; +} stc_ethernet_mac_stsr_field_t; + +typedef struct stc_ethernet_mac_stnr_field +{ + __IO uint32_t TSSS0 : 1; + __IO uint32_t TSSS1 : 1; + __IO uint32_t TSSS2 : 1; + __IO uint32_t TSSS3 : 1; + __IO uint32_t TSSS4 : 1; + __IO uint32_t TSSS5 : 1; + __IO uint32_t TSSS6 : 1; + __IO uint32_t TSSS7 : 1; + __IO uint32_t TSSS8 : 1; + __IO uint32_t TSSS9 : 1; + __IO uint32_t TSSS10 : 1; + __IO uint32_t TSSS11 : 1; + __IO uint32_t TSSS12 : 1; + __IO uint32_t TSSS13 : 1; + __IO uint32_t TSSS14 : 1; + __IO uint32_t TSSS15 : 1; + __IO uint32_t TSSS16 : 1; + __IO uint32_t TSSS17 : 1; + __IO uint32_t TSSS18 : 1; + __IO uint32_t TSSS19 : 1; + __IO uint32_t TSSS20 : 1; + __IO uint32_t TSSS21 : 1; + __IO uint32_t TSSS22 : 1; + __IO uint32_t TSSS23 : 1; + __IO uint32_t TSSS24 : 1; + __IO uint32_t TSSS25 : 1; + __IO uint32_t TSSS26 : 1; + __IO uint32_t TSSS27 : 1; + __IO uint32_t TSSS28 : 1; + __IO uint32_t TSSS29 : 1; + __IO uint32_t TSSS30 : 1; +} stc_ethernet_mac_stnr_field_t; + +typedef struct stc_ethernet_mac_stsur_field +{ + __IO uint32_t TSS0 : 1; + __IO uint32_t TSS1 : 1; + __IO uint32_t TSS2 : 1; + __IO uint32_t TSS3 : 1; + __IO uint32_t TSS4 : 1; + __IO uint32_t TSS5 : 1; + __IO uint32_t TSS6 : 1; + __IO uint32_t TSS7 : 1; + __IO uint32_t TSS8 : 1; + __IO uint32_t TSS9 : 1; + __IO uint32_t TSS10 : 1; + __IO uint32_t TSS11 : 1; + __IO uint32_t TSS12 : 1; + __IO uint32_t TSS13 : 1; + __IO uint32_t TSS14 : 1; + __IO uint32_t TSS15 : 1; + __IO uint32_t TSS16 : 1; + __IO uint32_t TSS17 : 1; + __IO uint32_t TSS18 : 1; + __IO uint32_t TSS19 : 1; + __IO uint32_t TSS20 : 1; + __IO uint32_t TSS21 : 1; + __IO uint32_t TSS22 : 1; + __IO uint32_t TSS23 : 1; + __IO uint32_t TSS24 : 1; + __IO uint32_t TSS25 : 1; + __IO uint32_t TSS26 : 1; + __IO uint32_t TSS27 : 1; + __IO uint32_t TSS28 : 1; + __IO uint32_t TSS29 : 1; + __IO uint32_t TSS30 : 1; + __IO uint32_t TSS31 : 1; +} stc_ethernet_mac_stsur_field_t; + +typedef struct stc_ethernet_mac_stnur_field +{ + __IO uint32_t TSSS0 : 1; + __IO uint32_t TSSS1 : 1; + __IO uint32_t TSSS2 : 1; + __IO uint32_t TSSS3 : 1; + __IO uint32_t TSSS4 : 1; + __IO uint32_t TSSS5 : 1; + __IO uint32_t TSSS6 : 1; + __IO uint32_t TSSS7 : 1; + __IO uint32_t TSSS8 : 1; + __IO uint32_t TSSS9 : 1; + __IO uint32_t TSSS10 : 1; + __IO uint32_t TSSS11 : 1; + __IO uint32_t TSSS12 : 1; + __IO uint32_t TSSS13 : 1; + __IO uint32_t TSSS14 : 1; + __IO uint32_t TSSS15 : 1; + __IO uint32_t TSSS16 : 1; + __IO uint32_t TSSS17 : 1; + __IO uint32_t TSSS18 : 1; + __IO uint32_t TSSS19 : 1; + __IO uint32_t TSSS20 : 1; + __IO uint32_t TSSS21 : 1; + __IO uint32_t TSSS22 : 1; + __IO uint32_t TSSS23 : 1; + __IO uint32_t TSSS24 : 1; + __IO uint32_t TSSS25 : 1; + __IO uint32_t TSSS26 : 1; + __IO uint32_t TSSS27 : 1; + __IO uint32_t TSSS28 : 1; + __IO uint32_t TSSS29 : 1; + __IO uint32_t TSSS30 : 1; + __IO uint32_t ADDSUB : 1; +} stc_ethernet_mac_stnur_field_t; + +typedef struct stc_ethernet_mac_tsar_field +{ + __IO uint32_t TSAR0 : 1; + __IO uint32_t TSAR1 : 1; + __IO uint32_t TSAR2 : 1; + __IO uint32_t TSAR3 : 1; + __IO uint32_t TSAR4 : 1; + __IO uint32_t TSAR5 : 1; + __IO uint32_t TSAR6 : 1; + __IO uint32_t TSAR7 : 1; + __IO uint32_t TSAR8 : 1; + __IO uint32_t TSAR9 : 1; + __IO uint32_t TSAR10 : 1; + __IO uint32_t TSAR11 : 1; + __IO uint32_t TSAR12 : 1; + __IO uint32_t TSAR13 : 1; + __IO uint32_t TSAR14 : 1; + __IO uint32_t TSAR15 : 1; + __IO uint32_t TSAR16 : 1; + __IO uint32_t TSAR17 : 1; + __IO uint32_t TSAR18 : 1; + __IO uint32_t TSAR19 : 1; + __IO uint32_t TSAR20 : 1; + __IO uint32_t TSAR21 : 1; + __IO uint32_t TSAR22 : 1; + __IO uint32_t TSAR23 : 1; + __IO uint32_t TSAR24 : 1; + __IO uint32_t TSAR25 : 1; + __IO uint32_t TSAR26 : 1; + __IO uint32_t TSAR27 : 1; + __IO uint32_t TSAR28 : 1; + __IO uint32_t TSAR29 : 1; + __IO uint32_t TSAR30 : 1; + __IO uint32_t TSAR31 : 1; +} stc_ethernet_mac_tsar_field_t; + +typedef struct stc_ethernet_mac_ttsr_field +{ + __IO uint32_t TSTR0 : 1; + __IO uint32_t TSTR1 : 1; + __IO uint32_t TSTR2 : 1; + __IO uint32_t TSTR3 : 1; + __IO uint32_t TSTR4 : 1; + __IO uint32_t TSTR5 : 1; + __IO uint32_t TSTR6 : 1; + __IO uint32_t TSTR7 : 1; + __IO uint32_t TSTR8 : 1; + __IO uint32_t TSTR9 : 1; + __IO uint32_t TSTR10 : 1; + __IO uint32_t TSTR11 : 1; + __IO uint32_t TSTR12 : 1; + __IO uint32_t TSTR13 : 1; + __IO uint32_t TSTR14 : 1; + __IO uint32_t TSTR15 : 1; + __IO uint32_t TSTR16 : 1; + __IO uint32_t TSTR17 : 1; + __IO uint32_t TSTR18 : 1; + __IO uint32_t TSTR19 : 1; + __IO uint32_t TSTR20 : 1; + __IO uint32_t TSTR21 : 1; + __IO uint32_t TSTR22 : 1; + __IO uint32_t TSTR23 : 1; + __IO uint32_t TSTR24 : 1; + __IO uint32_t TSTR25 : 1; + __IO uint32_t TSTR26 : 1; + __IO uint32_t TSTR27 : 1; + __IO uint32_t TSTR28 : 1; + __IO uint32_t TSTR29 : 1; + __IO uint32_t TSTR30 : 1; + __IO uint32_t TSTR31 : 1; +} stc_ethernet_mac_ttsr_field_t; + +typedef struct stc_ethernet_mac_ttnr_field +{ + __IO uint32_t TSTR0 : 1; + __IO uint32_t TSTR1 : 1; + __IO uint32_t TSTR2 : 1; + __IO uint32_t TSTR3 : 1; + __IO uint32_t TSTR4 : 1; + __IO uint32_t TSTR5 : 1; + __IO uint32_t TSTR6 : 1; + __IO uint32_t TSTR7 : 1; + __IO uint32_t TSTR8 : 1; + __IO uint32_t TSTR9 : 1; + __IO uint32_t TSTR10 : 1; + __IO uint32_t TSTR11 : 1; + __IO uint32_t TSTR12 : 1; + __IO uint32_t TSTR13 : 1; + __IO uint32_t TSTR14 : 1; + __IO uint32_t TSTR15 : 1; + __IO uint32_t TSTR16 : 1; + __IO uint32_t TSTR17 : 1; + __IO uint32_t TSTR18 : 1; + __IO uint32_t TSTR19 : 1; + __IO uint32_t TSTR20 : 1; + __IO uint32_t TSTR21 : 1; + __IO uint32_t TSTR22 : 1; + __IO uint32_t TSTR23 : 1; + __IO uint32_t TSTR24 : 1; + __IO uint32_t TSTR25 : 1; + __IO uint32_t TSTR26 : 1; + __IO uint32_t TSTR27 : 1; + __IO uint32_t TSTR28 : 1; + __IO uint32_t TSTR29 : 1; + __IO uint32_t TSTR30 : 1; +} stc_ethernet_mac_ttnr_field_t; + +typedef struct stc_ethernet_mac_sthwsr_field +{ + __IO uint32_t TSHWR0 : 1; + __IO uint32_t TSHWR1 : 1; + __IO uint32_t TSHWR2 : 1; + __IO uint32_t TSHWR3 : 1; + __IO uint32_t TSHWR4 : 1; + __IO uint32_t TSHWR5 : 1; + __IO uint32_t TSHWR6 : 1; + __IO uint32_t TSHWR7 : 1; + __IO uint32_t TSHWR8 : 1; + __IO uint32_t TSHWR9 : 1; + __IO uint32_t TSHWR10 : 1; + __IO uint32_t TSHWR11 : 1; + __IO uint32_t TSHWR12 : 1; + __IO uint32_t TSHWR13 : 1; + __IO uint32_t TSHWR14 : 1; + __IO uint32_t TSHWR15 : 1; +} stc_ethernet_mac_sthwsr_field_t; + +typedef struct stc_ethernet_mac_tsr_field +{ + __IO uint32_t TSSOVF : 1; + __IO uint32_t TSTART : 1; + __IO uint32_t ATSTS : 1; + __IO uint32_t TRGTER : 1; + uint32_t RESERVED1 :20; + __IO uint32_t ATSSTM : 1; + __IO uint32_t ATSNS0 : 1; + __IO uint32_t ATSNS1 : 1; + __IO uint32_t ATSNS2 : 1; +} stc_ethernet_mac_tsr_field_t; + +typedef struct stc_ethernet_mac_ppscr_field +{ + __IO uint32_t PPSCTRL0 : 1; + __IO uint32_t PPSCTRL1 : 1; + __IO uint32_t PPSCTRL2 : 1; + __IO uint32_t PPSCTRL3 : 1; +} stc_ethernet_mac_ppscr_field_t; + +typedef struct stc_ethernet_mac_atnr_field +{ + __IO uint32_t ATN0 : 1; + __IO uint32_t ATN1 : 1; + __IO uint32_t ATN2 : 1; + __IO uint32_t ATN3 : 1; + __IO uint32_t ATN4 : 1; + __IO uint32_t ATN5 : 1; + __IO uint32_t ATN6 : 1; + __IO uint32_t ATN7 : 1; + __IO uint32_t ATN8 : 1; + __IO uint32_t ATN9 : 1; + __IO uint32_t ATN10 : 1; + __IO uint32_t ATN11 : 1; + __IO uint32_t ATN12 : 1; + __IO uint32_t ATN13 : 1; + __IO uint32_t ATN14 : 1; + __IO uint32_t ATN15 : 1; + __IO uint32_t ATN16 : 1; + __IO uint32_t ATN17 : 1; + __IO uint32_t ATN18 : 1; + __IO uint32_t ATN19 : 1; + __IO uint32_t ATN20 : 1; + __IO uint32_t ATN21 : 1; + __IO uint32_t ATN22 : 1; + __IO uint32_t ATN23 : 1; + __IO uint32_t ATN24 : 1; + __IO uint32_t ATN25 : 1; + __IO uint32_t ATN26 : 1; + __IO uint32_t ATN27 : 1; + __IO uint32_t ATN28 : 1; + __IO uint32_t ATN29 : 1; + __IO uint32_t ATN30 : 1; +} stc_ethernet_mac_atnr_field_t; + +typedef struct stc_ethernet_mac_atsr_field +{ + __IO uint32_t ATS0 : 1; + __IO uint32_t ATS1 : 1; + __IO uint32_t ATS2 : 1; + __IO uint32_t ATS3 : 1; + __IO uint32_t ATS4 : 1; + __IO uint32_t ATS5 : 1; + __IO uint32_t ATS6 : 1; + __IO uint32_t ATS7 : 1; + __IO uint32_t ATS8 : 1; + __IO uint32_t ATS9 : 1; + __IO uint32_t ATS10 : 1; + __IO uint32_t ATS11 : 1; + __IO uint32_t ATS12 : 1; + __IO uint32_t ATS13 : 1; + __IO uint32_t ATS14 : 1; + __IO uint32_t ATS15 : 1; + __IO uint32_t ATS16 : 1; + __IO uint32_t ATS17 : 1; + __IO uint32_t ATS18 : 1; + __IO uint32_t ATS19 : 1; + __IO uint32_t ATS20 : 1; + __IO uint32_t ATS21 : 1; + __IO uint32_t ATS22 : 1; + __IO uint32_t ATS23 : 1; + __IO uint32_t ATS24 : 1; + __IO uint32_t ATS25 : 1; + __IO uint32_t ATS26 : 1; + __IO uint32_t ATS27 : 1; + __IO uint32_t ATS28 : 1; + __IO uint32_t ATS29 : 1; + __IO uint32_t ATS30 : 1; + __IO uint32_t ATS31 : 1; +} stc_ethernet_mac_atsr_field_t; + +typedef struct stc_ethernet_mac_mar16h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar16h_field_t; + +typedef struct stc_ethernet_mac_mar16l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar16l_field_t; + +typedef struct stc_ethernet_mac_mar17h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar17h_field_t; + +typedef struct stc_ethernet_mac_mar17l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar17l_field_t; + +typedef struct stc_ethernet_mac_mar18h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar18h_field_t; + +typedef struct stc_ethernet_mac_mar18l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar18l_field_t; + +typedef struct stc_ethernet_mac_mar19h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar19h_field_t; + +typedef struct stc_ethernet_mac_mar19l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar19l_field_t; + +typedef struct stc_ethernet_mac_mar20h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar20h_field_t; + +typedef struct stc_ethernet_mac_mar20l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar20l_field_t; + +typedef struct stc_ethernet_mac_mar21h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar21h_field_t; + +typedef struct stc_ethernet_mac_mar21l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar21l_field_t; + +typedef struct stc_ethernet_mac_mar22h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar22h_field_t; + +typedef struct stc_ethernet_mac_mar22l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar22l_field_t; + +typedef struct stc_ethernet_mac_mar23h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar23h_field_t; + +typedef struct stc_ethernet_mac_mar23l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar23l_field_t; + +typedef struct stc_ethernet_mac_mar24h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar24h_field_t; + +typedef struct stc_ethernet_mac_mar24l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar24l_field_t; + +typedef struct stc_ethernet_mac_mar25h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar25h_field_t; + +typedef struct stc_ethernet_mac_mar25l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar25l_field_t; + +typedef struct stc_ethernet_mac_mar26h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar26h_field_t; + +typedef struct stc_ethernet_mac_mar26l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar26l_field_t; + +typedef struct stc_ethernet_mac_mar27h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar27h_field_t; + +typedef struct stc_ethernet_mac_mar27l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar27l_field_t; + +typedef struct stc_ethernet_mac_mar28h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar28h_field_t; + +typedef struct stc_ethernet_mac_mar28l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar28l_field_t; + +typedef struct stc_ethernet_mac_mar29h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar29h_field_t; + +typedef struct stc_ethernet_mac_mar29l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar29l_field_t; + +typedef struct stc_ethernet_mac_mar30h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar30h_field_t; + +typedef struct stc_ethernet_mac_mar30l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar30l_field_t; + +typedef struct stc_ethernet_mac_mar31h_field +{ + __IO uint32_t A32 : 1; + __IO uint32_t A33 : 1; + __IO uint32_t A34 : 1; + __IO uint32_t A35 : 1; + __IO uint32_t A36 : 1; + __IO uint32_t A37 : 1; + __IO uint32_t A38 : 1; + __IO uint32_t A39 : 1; + __IO uint32_t A40 : 1; + __IO uint32_t A41 : 1; + __IO uint32_t A42 : 1; + __IO uint32_t A43 : 1; + __IO uint32_t A44 : 1; + __IO uint32_t A45 : 1; + __IO uint32_t A46 : 1; + __IO uint32_t A47 : 1; + uint32_t RESERVED1 : 8; + __IO uint32_t MBC0 : 1; + __IO uint32_t MBC1 : 1; + __IO uint32_t MBC2 : 1; + __IO uint32_t MBC3 : 1; + __IO uint32_t MBC4 : 1; + __IO uint32_t MBC5 : 1; + __IO uint32_t SA : 1; + __IO uint32_t AE : 1; +} stc_ethernet_mac_mar31h_field_t; + +typedef struct stc_ethernet_mac_mar31l_field +{ + __IO uint32_t A0 : 1; + __IO uint32_t A1 : 1; + __IO uint32_t A2 : 1; + __IO uint32_t A3 : 1; + __IO uint32_t A4 : 1; + __IO uint32_t A5 : 1; + __IO uint32_t A6 : 1; + __IO uint32_t A7 : 1; + __IO uint32_t A8 : 1; + __IO uint32_t A9 : 1; + __IO uint32_t A10 : 1; + __IO uint32_t A11 : 1; + __IO uint32_t A12 : 1; + __IO uint32_t A13 : 1; + __IO uint32_t A14 : 1; + __IO uint32_t A15 : 1; + __IO uint32_t A16 : 1; + __IO uint32_t A17 : 1; + __IO uint32_t A18 : 1; + __IO uint32_t A19 : 1; + __IO uint32_t A20 : 1; + __IO uint32_t A21 : 1; + __IO uint32_t A22 : 1; + __IO uint32_t A23 : 1; + __IO uint32_t A24 : 1; + __IO uint32_t A25 : 1; + __IO uint32_t A26 : 1; + __IO uint32_t A27 : 1; + __IO uint32_t A28 : 1; + __IO uint32_t A29 : 1; + __IO uint32_t A30 : 1; + __IO uint32_t A31 : 1; +} stc_ethernet_mac_mar31l_field_t; + +typedef struct stc_ethernet_mac_bmr_field +{ + __IO uint32_t SWR : 1; + __IO uint32_t DA : 1; + __IO uint32_t DSL0 : 1; + __IO uint32_t DSL1 : 1; + __IO uint32_t DSL2 : 1; + __IO uint32_t DSL3 : 1; + __IO uint32_t DSL4 : 1; + __IO uint32_t ATDS : 1; + __IO uint32_t PBL0 : 1; + __IO uint32_t PBL1 : 1; + __IO uint32_t PBL2 : 1; + __IO uint32_t PBL3 : 1; + __IO uint32_t PBL4 : 1; + __IO uint32_t PBL5 : 1; + __IO uint32_t PR0 : 1; + __IO uint32_t PR1 : 1; + __IO uint32_t FB : 1; + __IO uint32_t RPBL0 : 1; + __IO uint32_t RPBL1 : 1; + __IO uint32_t RPBL2 : 1; + __IO uint32_t RPBL3 : 1; + __IO uint32_t RPBL4 : 1; + __IO uint32_t RPBL5 : 1; + __IO uint32_t USP : 1; + __IO uint32_t _8XPBL : 1; + __IO uint32_t AAL : 1; + __IO uint32_t MB : 1; + __IO uint32_t TXPR : 1; +} stc_ethernet_mac_bmr_field_t; + +typedef struct stc_ethernet_mac_tpdr_field +{ + __IO uint32_t TPD0 : 1; + __IO uint32_t TPD1 : 1; + __IO uint32_t TPD2 : 1; + __IO uint32_t TPD3 : 1; + __IO uint32_t TPD4 : 1; + __IO uint32_t TPD5 : 1; + __IO uint32_t TPD6 : 1; + __IO uint32_t TPD7 : 1; + __IO uint32_t TPD8 : 1; + __IO uint32_t TPD9 : 1; + __IO uint32_t TPD10 : 1; + __IO uint32_t TPD11 : 1; + __IO uint32_t TPD12 : 1; + __IO uint32_t TPD13 : 1; + __IO uint32_t TPD14 : 1; + __IO uint32_t TPD15 : 1; + __IO uint32_t TPD16 : 1; + __IO uint32_t TPD17 : 1; + __IO uint32_t TPD18 : 1; + __IO uint32_t TPD19 : 1; + __IO uint32_t TPD20 : 1; + __IO uint32_t TPD21 : 1; + __IO uint32_t TPD22 : 1; + __IO uint32_t TPD23 : 1; + __IO uint32_t TPD24 : 1; + __IO uint32_t TPD25 : 1; + __IO uint32_t TPD26 : 1; + __IO uint32_t TPD27 : 1; + __IO uint32_t TPD28 : 1; + __IO uint32_t TPD29 : 1; + __IO uint32_t TPD30 : 1; + __IO uint32_t TPD31 : 1; +} stc_ethernet_mac_tpdr_field_t; + +typedef struct stc_ethernet_mac_rpdr_field +{ + __IO uint32_t RPD0 : 1; + __IO uint32_t RPD1 : 1; + __IO uint32_t RPD2 : 1; + __IO uint32_t RPD3 : 1; + __IO uint32_t RPD4 : 1; + __IO uint32_t RPD5 : 1; + __IO uint32_t RPD6 : 1; + __IO uint32_t RPD7 : 1; + __IO uint32_t RPD8 : 1; + __IO uint32_t RPD9 : 1; + __IO uint32_t RPD10 : 1; + __IO uint32_t RPD11 : 1; + __IO uint32_t RPD12 : 1; + __IO uint32_t RPD13 : 1; + __IO uint32_t RPD14 : 1; + __IO uint32_t RPD15 : 1; + __IO uint32_t RPD16 : 1; + __IO uint32_t RPD17 : 1; + __IO uint32_t RPD18 : 1; + __IO uint32_t RPD19 : 1; + __IO uint32_t RPD20 : 1; + __IO uint32_t RPD21 : 1; + __IO uint32_t RPD22 : 1; + __IO uint32_t RPD23 : 1; + __IO uint32_t RPD24 : 1; + __IO uint32_t RPD25 : 1; + __IO uint32_t RPD26 : 1; + __IO uint32_t RPD27 : 1; + __IO uint32_t RPD28 : 1; + __IO uint32_t RPD29 : 1; + __IO uint32_t RPD30 : 1; + __IO uint32_t RPD31 : 1; +} stc_ethernet_mac_rpdr_field_t; + +typedef struct stc_ethernet_mac_rdlar_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t SRL2 : 1; + __IO uint32_t SRL3 : 1; + __IO uint32_t SRL4 : 1; + __IO uint32_t SRL5 : 1; + __IO uint32_t SRL6 : 1; + __IO uint32_t SRL7 : 1; + __IO uint32_t SRL8 : 1; + __IO uint32_t SRL9 : 1; + __IO uint32_t SRL10 : 1; + __IO uint32_t SRL11 : 1; + __IO uint32_t SRL12 : 1; + __IO uint32_t SRL13 : 1; + __IO uint32_t SRL14 : 1; + __IO uint32_t SRL15 : 1; + __IO uint32_t SRL16 : 1; + __IO uint32_t SRL17 : 1; + __IO uint32_t SRL18 : 1; + __IO uint32_t SRL19 : 1; + __IO uint32_t SRL20 : 1; + __IO uint32_t SRL21 : 1; + __IO uint32_t SRL22 : 1; + __IO uint32_t SRL23 : 1; + __IO uint32_t SRL24 : 1; + __IO uint32_t SRL25 : 1; + __IO uint32_t SRL26 : 1; + __IO uint32_t SRL27 : 1; + __IO uint32_t SRL28 : 1; + __IO uint32_t SRL29 : 1; + __IO uint32_t SRL30 : 1; + __IO uint32_t SRL31 : 1; +} stc_ethernet_mac_rdlar_field_t; + +typedef struct stc_ethernet_mac_tdlar_field +{ + uint32_t RESERVED1 : 2; + __IO uint32_t STL2 : 1; + __IO uint32_t STL3 : 1; + __IO uint32_t STL4 : 1; + __IO uint32_t STL5 : 1; + __IO uint32_t STL6 : 1; + __IO uint32_t STL7 : 1; + __IO uint32_t STL8 : 1; + __IO uint32_t STL9 : 1; + __IO uint32_t STL10 : 1; + __IO uint32_t STL11 : 1; + __IO uint32_t STL12 : 1; + __IO uint32_t STL13 : 1; + __IO uint32_t STL14 : 1; + __IO uint32_t STL15 : 1; + __IO uint32_t STL16 : 1; + __IO uint32_t STL17 : 1; + __IO uint32_t STL18 : 1; + __IO uint32_t STL19 : 1; + __IO uint32_t STL20 : 1; + __IO uint32_t STL21 : 1; + __IO uint32_t STL22 : 1; + __IO uint32_t STL23 : 1; + __IO uint32_t STL24 : 1; + __IO uint32_t STL25 : 1; + __IO uint32_t STL26 : 1; + __IO uint32_t STL27 : 1; + __IO uint32_t STL28 : 1; + __IO uint32_t STL29 : 1; + __IO uint32_t STL30 : 1; + __IO uint32_t STL31 : 1; +} stc_ethernet_mac_tdlar_field_t; + +typedef struct stc_ethernet_mac_sr_field +{ + __IO uint32_t TI : 1; + __IO uint32_t TPS : 1; + __IO uint32_t TU : 1; + __IO uint32_t TJT : 1; + __IO uint32_t OVF : 1; + __IO uint32_t UNF : 1; + __IO uint32_t RI : 1; + __IO uint32_t RU : 1; + __IO uint32_t RPS : 1; + __IO uint32_t RWT : 1; + __IO uint32_t ETI : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t FBI : 1; + __IO uint32_t ERI : 1; + __IO uint32_t AIS : 1; + __IO uint32_t NIS : 1; + __IO uint32_t RS0 : 1; + __IO uint32_t RS1 : 1; + __IO uint32_t RS2 : 1; + __IO uint32_t TS0 : 1; + __IO uint32_t TS1 : 1; + __IO uint32_t TS2 : 1; + __IO uint32_t EB0 : 1; + __IO uint32_t EB1 : 1; + __IO uint32_t EB2 : 1; + __IO uint32_t GLI : 1; + __IO uint32_t GMI : 1; + __IO uint32_t GPI : 1; + __IO uint32_t TTI : 1; + __IO uint32_t GLPII : 1; +} stc_ethernet_mac_sr_field_t; + +typedef struct stc_ethernet_mac_omr_field +{ + uint32_t RESERVED1 : 1; + __IO uint32_t SR : 1; + __IO uint32_t OSF : 1; + __IO uint32_t RTC0 : 1; + __IO uint32_t RTC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t FUF : 1; + __IO uint32_t FEF : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t ST : 1; + __IO uint32_t TTC0 : 1; + __IO uint32_t TTC1 : 1; + __IO uint32_t TTC2 : 1; + uint32_t RESERVED4 : 3; + __IO uint32_t FTF : 1; + __IO uint32_t TSF : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t DFF : 1; + __IO uint32_t RSF : 1; + __IO uint32_t DT : 1; +} stc_ethernet_mac_omr_field_t; + +typedef struct stc_ethernet_mac_ier_field +{ + __IO uint32_t TIE : 1; + __IO uint32_t TSE : 1; + __IO uint32_t TUE : 1; + __IO uint32_t TJE : 1; + __IO uint32_t OVE : 1; + __IO uint32_t UNE : 1; + __IO uint32_t RIE : 1; + __IO uint32_t RUE : 1; + __IO uint32_t RSE : 1; + __IO uint32_t RWE : 1; + __IO uint32_t ETE : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t FBE : 1; + __IO uint32_t ERE : 1; + __IO uint32_t AIE : 1; + __IO uint32_t NIE : 1; +} stc_ethernet_mac_ier_field_t; + +typedef struct stc_ethernet_mac_mfbocr_field +{ + __IO uint32_t NMFH0 : 1; + __IO uint32_t NMFH1 : 1; + __IO uint32_t NMFH2 : 1; + __IO uint32_t NMFH3 : 1; + __IO uint32_t NMFH4 : 1; + __IO uint32_t NMFH5 : 1; + __IO uint32_t NMFH6 : 1; + __IO uint32_t NMFH7 : 1; + __IO uint32_t NMFH8 : 1; + __IO uint32_t NMFH9 : 1; + __IO uint32_t NMFH10 : 1; + __IO uint32_t NMFH11 : 1; + __IO uint32_t NMFH12 : 1; + __IO uint32_t NMFH13 : 1; + __IO uint32_t NMFH14 : 1; + __IO uint32_t NMFH15 : 1; + __IO uint32_t ONMFH : 1; + __IO uint32_t NMFF0 : 1; + __IO uint32_t NMFF1 : 1; + __IO uint32_t NMFF2 : 1; + __IO uint32_t NMFF3 : 1; + __IO uint32_t NMFF4 : 1; + __IO uint32_t NMFF5 : 1; + __IO uint32_t NMFF6 : 1; + __IO uint32_t NMFF7 : 1; + __IO uint32_t NMFF8 : 1; + __IO uint32_t NMFF9 : 1; + __IO uint32_t NMFF10 : 1; + __IO uint32_t ONMFF : 1; +} stc_ethernet_mac_mfbocr_field_t; + +typedef struct stc_ethernet_mac_riwtr_field +{ + __IO uint32_t RIWT0 : 1; + __IO uint32_t RIWT1 : 1; + __IO uint32_t RIWT2 : 1; + __IO uint32_t RIWT3 : 1; + __IO uint32_t RIWT4 : 1; + __IO uint32_t RIWT5 : 1; + __IO uint32_t RIWT6 : 1; + __IO uint32_t RIWT7 : 1; +} stc_ethernet_mac_riwtr_field_t; + +typedef struct stc_ethernet_mac_ahbsr_field +{ + __IO uint32_t AHBS : 1; +} stc_ethernet_mac_ahbsr_field_t; + +typedef struct stc_ethernet_mac_chtdr_field +{ + __IO uint32_t HTDAP0 : 1; + __IO uint32_t HTDAP1 : 1; + __IO uint32_t HTDAP2 : 1; + __IO uint32_t HTDAP3 : 1; + __IO uint32_t HTDAP4 : 1; + __IO uint32_t HTDAP5 : 1; + __IO uint32_t HTDAP6 : 1; + __IO uint32_t HTDAP7 : 1; + __IO uint32_t HTDAP8 : 1; + __IO uint32_t HTDAP9 : 1; + __IO uint32_t HTDAP10 : 1; + __IO uint32_t HTDAP11 : 1; + __IO uint32_t HTDAP12 : 1; + __IO uint32_t HTDAP13 : 1; + __IO uint32_t HTDAP14 : 1; + __IO uint32_t HTDAP15 : 1; + __IO uint32_t HTDAP16 : 1; + __IO uint32_t HTDAP17 : 1; + __IO uint32_t HTDAP18 : 1; + __IO uint32_t HTDAP19 : 1; + __IO uint32_t HTDAP20 : 1; + __IO uint32_t HTDAP21 : 1; + __IO uint32_t HTDAP22 : 1; + __IO uint32_t HTDAP23 : 1; + __IO uint32_t HTDAP24 : 1; + __IO uint32_t HTDAP25 : 1; + __IO uint32_t HTDAP26 : 1; + __IO uint32_t HTDAP27 : 1; + __IO uint32_t HTDAP28 : 1; + __IO uint32_t HTDAP29 : 1; + __IO uint32_t HTDAP30 : 1; + __IO uint32_t HTDAP31 : 1; +} stc_ethernet_mac_chtdr_field_t; + +typedef struct stc_ethernet_mac_chrdr_field +{ + __IO uint32_t HRDAP0 : 1; + __IO uint32_t HRDAP1 : 1; + __IO uint32_t HRDAP2 : 1; + __IO uint32_t HRDAP3 : 1; + __IO uint32_t HRDAP4 : 1; + __IO uint32_t HRDAP5 : 1; + __IO uint32_t HRDAP6 : 1; + __IO uint32_t HRDAP7 : 1; + __IO uint32_t HRDAP8 : 1; + __IO uint32_t HRDAP9 : 1; + __IO uint32_t HRDAP10 : 1; + __IO uint32_t HRDAP11 : 1; + __IO uint32_t HRDAP12 : 1; + __IO uint32_t HRDAP13 : 1; + __IO uint32_t HRDAP14 : 1; + __IO uint32_t HRDAP15 : 1; + __IO uint32_t HRDAP16 : 1; + __IO uint32_t HRDAP17 : 1; + __IO uint32_t HRDAP18 : 1; + __IO uint32_t HRDAP19 : 1; + __IO uint32_t HRDAP20 : 1; + __IO uint32_t HRDAP21 : 1; + __IO uint32_t HRDAP22 : 1; + __IO uint32_t HRDAP23 : 1; + __IO uint32_t HRDAP24 : 1; + __IO uint32_t HRDAP25 : 1; + __IO uint32_t HRDAP26 : 1; + __IO uint32_t HRDAP27 : 1; + __IO uint32_t HRDAP28 : 1; + __IO uint32_t HRDAP29 : 1; + __IO uint32_t HRDAP30 : 1; + __IO uint32_t HRDAP31 : 1; +} stc_ethernet_mac_chrdr_field_t; + +typedef struct stc_ethernet_mac_chtbar_field +{ + __IO uint32_t HTBAR0 : 1; + __IO uint32_t HTBAR1 : 1; + __IO uint32_t HTBAR2 : 1; + __IO uint32_t HTBAR3 : 1; + __IO uint32_t HTBAR4 : 1; + __IO uint32_t HTBAR5 : 1; + __IO uint32_t HTBAR6 : 1; + __IO uint32_t HTBAR7 : 1; + __IO uint32_t HTBAR8 : 1; + __IO uint32_t HTBAR9 : 1; + __IO uint32_t HTBAR10 : 1; + __IO uint32_t HTBAR11 : 1; + __IO uint32_t HTBAR12 : 1; + __IO uint32_t HTBAR13 : 1; + __IO uint32_t HTBAR14 : 1; + __IO uint32_t HTBAR15 : 1; + __IO uint32_t HTBAR16 : 1; + __IO uint32_t HTBAR17 : 1; + __IO uint32_t HTBAR18 : 1; + __IO uint32_t HTBAR19 : 1; + __IO uint32_t HTBAR20 : 1; + __IO uint32_t HTBAR21 : 1; + __IO uint32_t HTBAR22 : 1; + __IO uint32_t HTBAR23 : 1; + __IO uint32_t HTBAR24 : 1; + __IO uint32_t HTBAR25 : 1; + __IO uint32_t HTBAR26 : 1; + __IO uint32_t HTBAR27 : 1; + __IO uint32_t HTBAR28 : 1; + __IO uint32_t HTBAR29 : 1; + __IO uint32_t HTBAR30 : 1; + __IO uint32_t HTBAR31 : 1; +} stc_ethernet_mac_chtbar_field_t; + +typedef struct stc_ethernet_mac_chrbar_field +{ + __IO uint32_t HRBAR0 : 1; + __IO uint32_t HRBAR1 : 1; + __IO uint32_t HRBAR2 : 1; + __IO uint32_t HRBAR3 : 1; + __IO uint32_t HRBAR4 : 1; + __IO uint32_t HRBAR5 : 1; + __IO uint32_t HRBAR6 : 1; + __IO uint32_t HRBAR7 : 1; + __IO uint32_t HRBAR8 : 1; + __IO uint32_t HRBAR9 : 1; + __IO uint32_t HRBAR10 : 1; + __IO uint32_t HRBAR11 : 1; + __IO uint32_t HRBAR12 : 1; + __IO uint32_t HRBAR13 : 1; + __IO uint32_t HRBAR14 : 1; + __IO uint32_t HRBAR15 : 1; + __IO uint32_t HRBAR16 : 1; + __IO uint32_t HRBAR17 : 1; + __IO uint32_t HRBAR18 : 1; + __IO uint32_t HRBAR19 : 1; + __IO uint32_t HRBAR20 : 1; + __IO uint32_t HRBAR21 : 1; + __IO uint32_t HRBAR22 : 1; + __IO uint32_t HRBAR23 : 1; + __IO uint32_t HRBAR24 : 1; + __IO uint32_t HRBAR25 : 1; + __IO uint32_t HRBAR26 : 1; + __IO uint32_t HRBAR27 : 1; + __IO uint32_t HRBAR28 : 1; + __IO uint32_t HRBAR29 : 1; + __IO uint32_t HRBAR30 : 1; + __IO uint32_t HRBAR31 : 1; +} stc_ethernet_mac_chrbar_field_t; + +/* ETHERNET_CONTROL_MODULE register bit fields */ +typedef struct stc_ethernet_control_eth_mode_field +{ + __IO uint32_t IFMODE : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t RST0 : 1; + __IO uint32_t RST1 : 1; + uint32_t RESERVED2 :18; + __IO uint32_t ASZPPSSEL : 1; +} stc_ethernet_control_eth_mode_field_t; + +typedef struct stc_ethernet_control_eth_clkg_field +{ + __IO uint32_t MACEN0 : 1; + __IO uint32_t MACEN1 : 1; +} stc_ethernet_control_eth_clkg_field_t; + +/****************************************************************************** + * Peripheral register structures + ******************************************************************************/ + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + }; + uint8_t RESERVED0[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + }; + union { + __IO uint32_t FBFCR; + stc_flash_if_fbfcr_field_t FBFCR_f; + }; + uint8_t RESERVED1[232]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + }; +}FM3_FLASH_IF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + union { + __IO uint8_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + }; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + union { + __IO uint16_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + }; + uint8_t RESERVED7[7]; + union { + __IO uint8_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + }; + uint8_t RESERVED8[7]; + union { + __IO uint8_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint16_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint8_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + }; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + union { + __IO uint8_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + }; + uint8_t RESERVED18[11]; + union { + __IO uint8_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + }; + uint8_t RESERVED19[3]; + union { + __IO uint8_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + }; + uint8_t RESERVED20[3]; + union { + __IO uint8_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + }; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + union { + __IO uint8_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + }; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + union { + __IO uint8_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + }; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + union { + __IO uint8_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + union { + __IO uint8_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + }; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + union { + __IO uint32_t TIMER1CONTROL; + stc_dtim_timer1control_field_t TIMER1CONTROL_f; + }; + __IO uint32_t TIMER1INTCLR; + union { + __IO uint32_t TIMER1RIS; + stc_dtim_timer1ris_field_t TIMER1RIS_f; + }; + union { + __IO uint32_t TIMER1MIS; + stc_dtim_timer1mis_field_t TIMER1MIS_f; + }; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + union { + __IO uint32_t TIMER2CONTROL; + stc_dtim_timer2control_field_t TIMER2CONTROL_f; + }; + __IO uint32_t TIMER2INTCLR; + union { + __IO uint32_t TIMER2RIS; + stc_dtim_timer2ris_field_t TIMER2RIS_f; + }; + union { + __IO uint32_t TIMER2MIS; + stc_dtim_timer2mis_field_t TIMER2MIS_f; + }; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t TCSB0; + stc_mft_frt_tcsb0_field_t TCSB0_f; + }; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t TCSB1; + stc_mft_frt_tcsb1_field_t TCSB1_f; + }; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t TCSB2; + stc_mft_frt_tcsb2_field_t TCSB2_f; + }; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + uint8_t RESERVED9[50]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + }; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + union { + __IO uint8_t ACSB; + stc_mft_adcmp_acsb_field_t ACSB_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ATSA; + stc_mft_adcmp_atsa_field_t ATSA_f; + }; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[12]; + union { + __IO uint8_t TTCR2; + stc_mft_ppg_ttcr2_field_t TTCR2_f; + }; + uint8_t RESERVED11[7]; + __IO uint8_t COMP8; + uint8_t RESERVED12[2]; + __IO uint8_t COMP10; + uint8_t RESERVED13[4]; + __IO uint8_t COMP12; + uint8_t RESERVED14[2]; + __IO uint8_t COMP14; + uint8_t RESERVED15[171]; + union { + __IO uint16_t TRG; + stc_mft_ppg_trg_field_t TRG_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t REVC; + stc_mft_ppg_revc_field_t REVC_f; + }; + uint8_t RESERVED17[58]; + union { + __IO uint16_t TRG1; + stc_mft_ppg_trg1_field_t TRG1_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t REVC1; + stc_mft_ppg_revc1_field_t REVC1_f; + }; + uint8_t RESERVED19[186]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + uint8_t RESERVED20[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + uint8_t RESERVED26[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + uint8_t RESERVED27[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED32[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + uint8_t RESERVED33[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + uint8_t RESERVED34[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED39[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + uint8_t RESERVED40[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + uint8_t RESERVED41[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + uint8_t RESERVED42[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED43[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED44[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED45[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED46[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; + uint8_t RESERVED47[39]; + union { + __IO uint8_t PPGC17; + stc_mft_ppg_ppgc17_field_t PPGC17_f; + }; + union { + __IO uint8_t PPGC16; + stc_mft_ppg_ppgc16_field_t PPGC16_f; + }; + uint8_t RESERVED48[2]; + union { + __IO uint8_t PPGC19; + stc_mft_ppg_ppgc19_field_t PPGC19_f; + }; + union { + __IO uint8_t PPGC18; + stc_mft_ppg_ppgc18_field_t PPGC18_f; + }; + uint8_t RESERVED49[2]; + union { + __IO uint16_t PRL16; + struct { + __IO uint8_t PRLL16; + __IO uint8_t PRLH16; + }; + }; + uint8_t RESERVED50[2]; + union { + __IO uint16_t PRL17; + struct { + __IO uint8_t PRLL17; + __IO uint8_t PRLH17; + }; + }; + uint8_t RESERVED51[2]; + union { + __IO uint16_t PRL18; + struct { + __IO uint8_t PRLL18; + __IO uint8_t PRLH18; + }; + }; + uint8_t RESERVED52[2]; + union { + __IO uint16_t PRL19; + struct { + __IO uint8_t PRLL19; + __IO uint8_t PRLH19; + }; + }; + uint8_t RESERVED53[2]; + union { + __IO uint8_t GATEC16; + stc_mft_ppg_gatec16_field_t GATEC16_f; + }; + uint8_t RESERVED54[39]; + union { + __IO uint8_t PPGC21; + stc_mft_ppg_ppgc21_field_t PPGC21_f; + }; + union { + __IO uint8_t PPGC20; + stc_mft_ppg_ppgc20_field_t PPGC20_f; + }; + uint8_t RESERVED55[2]; + union { + __IO uint8_t PPGC23; + stc_mft_ppg_ppgc23_field_t PPGC23_f; + }; + union { + __IO uint8_t PPGC22; + stc_mft_ppg_ppgc22_field_t PPGC22_f; + }; + uint8_t RESERVED56[2]; + union { + __IO uint16_t PRL20; + struct { + __IO uint8_t PRLL20; + __IO uint8_t PRLH20; + }; + }; + uint8_t RESERVED57[2]; + union { + __IO uint16_t PRL21; + struct { + __IO uint8_t PRLL21; + __IO uint8_t PRLH21; + }; + }; + uint8_t RESERVED58[2]; + union { + __IO uint16_t PRL22; + struct { + __IO uint8_t PRLL22; + __IO uint8_t PRLH22; + }; + }; + uint8_t RESERVED59[2]; + union { + __IO uint16_t PRL23; + struct { + __IO uint8_t PRLL23; + __IO uint8_t PRLH23; + }; + }; + uint8_t RESERVED60[2]; + union { + __IO uint8_t GATEC20; + stc_mft_ppg_gatec20_field_t GATEC20_f; + }; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * BTIOSEL8B_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 8 - channel 11 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSEL89AB; + stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; + }; +}FM3_BTIOSEL8B_TypeDef; + +/****************************************************************************** + * BTIOSELCF_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 12 - channel 15 registers */ +typedef struct +{ + uint8_t RESERVED0; + union { + __IO uint8_t BTSELCDEF; + stc_btioselcf_btselcdef_field_t BTSELCDEF_f; + }; +}FM3_BTIOSELCF_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + }; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t QICR; + stc_qprc_qicr_field_t QICR_f; + }; + struct { + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + }; + struct { + union { + __IO uint8_t QCRL; + stc_qprc_qcrl_field_t QCRL_f; + }; + union { + __IO uint8_t QCRH; + stc_qprc_qcrh_field_t QCRH_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + }; + uint8_t RESERVED7[30]; + __IO uint16_t QRCRR; + __IO uint16_t QPCRR; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + }; + struct { + union { + __IO uint16_t SCFDL; + stc_adc_scfdl_field_t SCFDL_f; + }; + union { + __IO uint16_t SCFDH; + stc_adc_scfdh_field_t SCFDH_f; + }; + }; + }; + union { + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + }; + struct { + union { + __IO uint8_t SCIS2; + stc_adc_scis2_field_t SCIS2_f; + }; + union { + __IO uint8_t SCIS3; + stc_adc_scis3_field_t SCIS3_f; + }; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + }; + struct { + union { + __IO uint8_t SCIS0; + stc_adc_scis0_field_t SCIS0_f; + }; + union { + __IO uint8_t SCIS1; + stc_adc_scis1_field_t SCIS1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + }; + struct { + union { + __IO uint16_t PCFDL; + stc_adc_pcfdl_field_t PCFDL_f; + }; + union { + __IO uint16_t PCFDH; + stc_adc_pcfdh_field_t PCFDH_f; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + uint8_t RESERVED6; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + }; + union { + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + }; + struct { + union { + __IO uint8_t ADSS2; + stc_adc_adss2_field_t ADSS2_f; + }; + union { + __IO uint8_t ADSS3; + stc_adc_adss3_field_t ADSS3_f; + }; + }; + }; + uint8_t RESERVED7[2]; + union { + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + }; + struct { + union { + __IO uint8_t ADSS0; + stc_adc_adss0_field_t ADSS0_f; + }; + union { + __IO uint8_t ADSS1; + stc_adc_adss1_field_t ADSS1_f; + }; + }; + }; + uint8_t RESERVED8[2]; + union { + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + }; + struct { + union { + __IO uint8_t ADST1; + stc_adc_adst1_field_t ADST1_f; + }; + union { + __IO uint8_t ADST0; + stc_adc_adst0_field_t ADST0_f; + }; + }; + }; + uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint8_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + }; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint16_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + }; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + union { + __IO uint32_t ENIR; + stc_exti_enir_field_t ENIR_f; + }; + union { + __IO uint32_t EIRR; + stc_exti_eirr_field_t EIRR_f; + }; + union { + __IO uint32_t EICL; + stc_exti_eicl_field_t EICL_f; + }; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + }; + union { + __IO uint32_t ELVR1; + stc_exti_elvr1_field_t ELVR1_f; + }; + union { + __IO uint8_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + }; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + }; + uint8_t RESERVED0[7]; + union { + __IO uint8_t ODDPKS; + stc_intreq_oddpks_field_t ODDPKS_f; + }; + uint8_t RESERVED1[4]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + }; + union { + __IO uint32_t IRQ00MON; + stc_intreq_irq00mon_field_t IRQ00MON_f; + }; + union { + __IO uint32_t IRQ01MON; + stc_intreq_irq01mon_field_t IRQ01MON_f; + }; + union { + __IO uint32_t IRQ02MON; + stc_intreq_irq02mon_field_t IRQ02MON_f; + }; + union { + __IO uint32_t IRQ03MON; + stc_intreq_irq03mon_field_t IRQ03MON_f; + }; + union { + __IO uint32_t IRQ04MON; + stc_intreq_irq04mon_field_t IRQ04MON_f; + }; + union { + __IO uint32_t IRQ05MON; + stc_intreq_irq05mon_field_t IRQ05MON_f; + }; + union { + __IO uint32_t IRQ06MON; + stc_intreq_irq06mon_field_t IRQ06MON_f; + }; + union { + __IO uint32_t IRQ07MON; + stc_intreq_irq07mon_field_t IRQ07MON_f; + }; + union { + __IO uint32_t IRQ08MON; + stc_intreq_irq08mon_field_t IRQ08MON_f; + }; + union { + __IO uint32_t IRQ09MON; + stc_intreq_irq09mon_field_t IRQ09MON_f; + }; + union { + __IO uint32_t IRQ10MON; + stc_intreq_irq10mon_field_t IRQ10MON_f; + }; + union { + __IO uint32_t IRQ11MON; + stc_intreq_irq11mon_field_t IRQ11MON_f; + }; + union { + __IO uint32_t IRQ12MON; + stc_intreq_irq12mon_field_t IRQ12MON_f; + }; + union { + __IO uint32_t IRQ13MON; + stc_intreq_irq13mon_field_t IRQ13MON_f; + }; + union { + __IO uint32_t IRQ14MON; + stc_intreq_irq14mon_field_t IRQ14MON_f; + }; + union { + __IO uint32_t IRQ15MON; + stc_intreq_irq15mon_field_t IRQ15MON_f; + }; + union { + __IO uint32_t IRQ16MON; + stc_intreq_irq16mon_field_t IRQ16MON_f; + }; + union { + __IO uint32_t IRQ17MON; + stc_intreq_irq17mon_field_t IRQ17MON_f; + }; + union { + __IO uint32_t IRQ18MON; + stc_intreq_irq18mon_field_t IRQ18MON_f; + }; + union { + __IO uint32_t IRQ19MON; + stc_intreq_irq19mon_field_t IRQ19MON_f; + }; + union { + __IO uint32_t IRQ20MON; + stc_intreq_irq20mon_field_t IRQ20MON_f; + }; + union { + __IO uint32_t IRQ21MON; + stc_intreq_irq21mon_field_t IRQ21MON_f; + }; + union { + __IO uint32_t IRQ22MON; + stc_intreq_irq22mon_field_t IRQ22MON_f; + }; + union { + __IO uint32_t IRQ23MON; + stc_intreq_irq23mon_field_t IRQ23MON_f; + }; + union { + __IO uint32_t IRQ24MON; + stc_intreq_irq24mon_field_t IRQ24MON_f; + }; + union { + __IO uint32_t IRQ25MON; + stc_intreq_irq25mon_field_t IRQ25MON_f; + }; + union { + __IO uint32_t IRQ26MON; + stc_intreq_irq26mon_field_t IRQ26MON_f; + }; + union { + __IO uint32_t IRQ27MON; + stc_intreq_irq27mon_field_t IRQ27MON_f; + }; + union { + __IO uint32_t IRQ28MON; + stc_intreq_irq28mon_field_t IRQ28MON_f; + }; + union { + __IO uint32_t IRQ29MON; + stc_intreq_irq29mon_field_t IRQ29MON_f; + }; + union { + __IO uint32_t IRQ30MON; + stc_intreq_irq30mon_field_t IRQ30MON_f; + }; + union { + __IO uint32_t IRQ31MON; + stc_intreq_irq31mon_field_t IRQ31MON_f; + }; + union { + __IO uint32_t IRQ32MON; + stc_intreq_irq32mon_field_t IRQ32MON_f; + }; + union { + __IO uint32_t IRQ33MON; + stc_intreq_irq33mon_field_t IRQ33MON_f; + }; + union { + __IO uint32_t IRQ34MON; + stc_intreq_irq34mon_field_t IRQ34MON_f; + }; + union { + __IO uint32_t IRQ35MON; + stc_intreq_irq35mon_field_t IRQ35MON_f; + }; + union { + __IO uint32_t IRQ36MON; + stc_intreq_irq36mon_field_t IRQ36MON_f; + }; + union { + __IO uint32_t IRQ37MON; + stc_intreq_irq37mon_field_t IRQ37MON_f; + }; + union { + __IO uint32_t IRQ38MON; + stc_intreq_irq38mon_field_t IRQ38MON_f; + }; + union { + __IO uint32_t IRQ39MON; + stc_intreq_irq39mon_field_t IRQ39MON_f; + }; + union { + __IO uint32_t IRQ40MON; + stc_intreq_irq40mon_field_t IRQ40MON_f; + }; + union { + __IO uint32_t IRQ41MON; + stc_intreq_irq41mon_field_t IRQ41MON_f; + }; + union { + __IO uint32_t IRQ42MON; + stc_intreq_irq42mon_field_t IRQ42MON_f; + }; + union { + __IO uint32_t IRQ43MON; + stc_intreq_irq43mon_field_t IRQ43MON_f; + }; + union { + __IO uint32_t IRQ44MON; + stc_intreq_irq44mon_field_t IRQ44MON_f; + }; + union { + __IO uint32_t IRQ45MON; + stc_intreq_irq45mon_field_t IRQ45MON_f; + }; + union { + __IO uint32_t IRQ46MON; + stc_intreq_irq46mon_field_t IRQ46MON_f; + }; + __IO uint32_t IRQ47MON; + uint8_t RESERVED2[300]; + union { + __IO uint32_t DRQSEL1; + stc_intreq_drqsel1_field_t DRQSEL1_f; + }; + union { + __IO uint32_t DQESEL; + stc_intreq_dqesel_field_t DQESEL_f; + }; + uint8_t RESERVED3[7]; + union { + __IO uint8_t ODDPKS1; + stc_intreq_oddpks1_field_t ODDPKS1_f; + }; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + }; + union { + __IO uint32_t PFR5; + stc_gpio_pfr5_field_t PFR5_f; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + }; + union { + __IO uint32_t PFR9; + stc_gpio_pfr9_field_t PFR9_f; + }; + union { + __IO uint32_t PFRA; + stc_gpio_pfra_field_t PFRA_f; + }; + union { + __IO uint32_t PFRB; + stc_gpio_pfrb_field_t PFRB_f; + }; + union { + __IO uint32_t PFRC; + stc_gpio_pfrc_field_t PFRC_f; + }; + union { + __IO uint32_t PFRD; + stc_gpio_pfrd_field_t PFRD_f; + }; + union { + __IO uint32_t PFRE; + stc_gpio_pfre_field_t PFRE_f; + }; + union { + __IO uint32_t PFRF; + stc_gpio_pfrf_field_t PFRF_f; + }; + uint8_t RESERVED0[192]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + }; + union { + __IO uint32_t PCR5; + stc_gpio_pcr5_field_t PCR5_f; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + }; + __IO uint32_t PCR8; + union { + __IO uint32_t PCR9; + stc_gpio_pcr9_field_t PCR9_f; + }; + union { + __IO uint32_t PCRA; + stc_gpio_pcra_field_t PCRA_f; + }; + union { + __IO uint32_t PCRB; + stc_gpio_pcrb_field_t PCRB_f; + }; + union { + __IO uint32_t PCRC; + stc_gpio_pcrc_field_t PCRC_f; + }; + union { + __IO uint32_t PCRD; + stc_gpio_pcrd_field_t PCRD_f; + }; + union { + __IO uint32_t PCRE; + stc_gpio_pcre_field_t PCRE_f; + }; + __IO uint32_t PCRF; + uint8_t RESERVED1[192]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + }; + union { + __IO uint32_t DDR5; + stc_gpio_ddr5_field_t DDR5_f; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + }; + union { + __IO uint32_t DDR9; + stc_gpio_ddr9_field_t DDR9_f; + }; + union { + __IO uint32_t DDRA; + stc_gpio_ddra_field_t DDRA_f; + }; + union { + __IO uint32_t DDRB; + stc_gpio_ddrb_field_t DDRB_f; + }; + union { + __IO uint32_t DDRC; + stc_gpio_ddrc_field_t DDRC_f; + }; + union { + __IO uint32_t DDRD; + stc_gpio_ddrd_field_t DDRD_f; + }; + union { + __IO uint32_t DDRE; + stc_gpio_ddre_field_t DDRE_f; + }; + union { + __IO uint32_t DDRF; + stc_gpio_ddrf_field_t DDRF_f; + }; + uint8_t RESERVED2[192]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + }; + union { + __IO uint32_t PDIR5; + stc_gpio_pdir5_field_t PDIR5_f; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + }; + union { + __IO uint32_t PDIR9; + stc_gpio_pdir9_field_t PDIR9_f; + }; + union { + __IO uint32_t PDIRA; + stc_gpio_pdira_field_t PDIRA_f; + }; + union { + __IO uint32_t PDIRB; + stc_gpio_pdirb_field_t PDIRB_f; + }; + union { + __IO uint32_t PDIRC; + stc_gpio_pdirc_field_t PDIRC_f; + }; + union { + __IO uint32_t PDIRD; + stc_gpio_pdird_field_t PDIRD_f; + }; + union { + __IO uint32_t PDIRE; + stc_gpio_pdire_field_t PDIRE_f; + }; + union { + __IO uint32_t PDIRF; + stc_gpio_pdirf_field_t PDIRF_f; + }; + uint8_t RESERVED3[192]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + }; + union { + __IO uint32_t PDOR5; + stc_gpio_pdor5_field_t PDOR5_f; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + }; + union { + __IO uint32_t PDOR9; + stc_gpio_pdor9_field_t PDOR9_f; + }; + union { + __IO uint32_t PDORA; + stc_gpio_pdora_field_t PDORA_f; + }; + union { + __IO uint32_t PDORB; + stc_gpio_pdorb_field_t PDORB_f; + }; + union { + __IO uint32_t PDORC; + stc_gpio_pdorc_field_t PDORC_f; + }; + union { + __IO uint32_t PDORD; + stc_gpio_pdord_field_t PDORD_f; + }; + union { + __IO uint32_t PDORE; + stc_gpio_pdore_field_t PDORE_f; + }; + union { + __IO uint32_t PDORF; + stc_gpio_pdorf_field_t PDORF_f; + }; + uint8_t RESERVED4[192]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + }; + uint8_t RESERVED5[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + }; + uint8_t RESERVED6[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + }; + union { + __IO uint32_t EPFR03; + stc_gpio_epfr03_field_t EPFR03_f; + }; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + }; + union { + __IO uint32_t EPFR11; + stc_gpio_epfr11_field_t EPFR11_f; + }; + union { + __IO uint32_t EPFR12; + stc_gpio_epfr12_field_t EPFR12_f; + }; + union { + __IO uint32_t EPFR13; + stc_gpio_epfr13_field_t EPFR13_f; + }; + union { + __IO uint32_t EPFR14; + stc_gpio_epfr14_field_t EPFR14_f; + }; + union { + __IO uint32_t EPFR15; + stc_gpio_epfr15_field_t EPFR15_f; + }; + uint8_t RESERVED7[192]; + union { + __IO uint32_t PZR0; + stc_gpio_pzr0_field_t PZR0_f; + }; + union { + __IO uint32_t PZR1; + stc_gpio_pzr1_field_t PZR1_f; + }; + union { + __IO uint32_t PZR2; + stc_gpio_pzr2_field_t PZR2_f; + }; + union { + __IO uint32_t PZR3; + stc_gpio_pzr3_field_t PZR3_f; + }; + union { + __IO uint32_t PZR4; + stc_gpio_pzr4_field_t PZR4_f; + }; + union { + __IO uint32_t PZR5; + stc_gpio_pzr5_field_t PZR5_f; + }; + union { + __IO uint32_t PZR6; + stc_gpio_pzr6_field_t PZR6_f; + }; + union { + __IO uint32_t PZR7; + stc_gpio_pzr7_field_t PZR7_f; + }; + union { + __IO uint32_t PZR8; + stc_gpio_pzr8_field_t PZR8_f; + }; + union { + __IO uint32_t PZR9; + stc_gpio_pzr9_field_t PZR9_f; + }; + union { + __IO uint32_t PZRA; + stc_gpio_pzra_field_t PZRA_f; + }; + union { + __IO uint32_t PZRB; + stc_gpio_pzrb_field_t PZRB_f; + }; + union { + __IO uint32_t PZRC; + stc_gpio_pzrc_field_t PZRC_f; + }; + union { + __IO uint32_t PZRD; + stc_gpio_pzrd_field_t PZRD_f; + }; + union { + __IO uint32_t PZRE; + stc_gpio_pzre_field_t PZRE_f; + }; + union { + __IO uint32_t PZRF; + stc_gpio_pzrf_field_t PZRF_f; + }; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBETHERNETCLK + ******************************************************************************/ +/* USB Ethernet clock registers */ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbethernetclk_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbethernetclk_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbethernetclk_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbethernetclk_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbethernetclk_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbethernetclk_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbethernetclk_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbethernetclk_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t UPCR6; + stc_usbethernetclk_upcr6_field_t UPCR6_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t UPCR7; + stc_usbethernetclk_upcr7_field_t UPCR7_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t USBEN0; + stc_usbethernetclk_usben0_field_t USBEN0_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t USBEN1; + stc_usbethernetclk_usben1_field_t USBEN1_f; + }; +}FM3_USBETHERNETCLK_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs03_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs03_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_uart_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs03_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs03_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs03_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs03_lin_bgr1_field_t BGR1_f; + }; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs03_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs03_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs03_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs03_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs03_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs03_i2c_ismk_field_t ISMK_f; + }; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_uart_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_uart_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + union { + __IO uint16_t RDR; + stc_mfs47_uart_rdr_field_t RDR_f; + }; + union { + __IO uint16_t TDR; + stc_mfs47_uart_tdr_field_t TDR_f; + }; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_uart_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_uart_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_uart_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_uart_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_uart_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_uart_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_uart_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_uart_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_csio_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_csio_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_csio_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_csio_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_csio_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_csio_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_csio_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_csio_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs47_lin_scr_field_t SCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs47_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_lin_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t BGR; + stc_mfs47_lin_bgr_field_t BGR_f; + }; + struct { + __IO uint8_t BGR0; + union { + __IO uint8_t BGR1; + stc_mfs47_lin_bgr1_field_t BGR1_f; + }; + }; + }; + uint8_t RESERVED3[6]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_lin_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_lin_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_lin_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_lin_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_lin_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_lin_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs47_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs47_i2c_ibcr_field_t IBCR_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t IBSR; + stc_mfs47_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs47_i2c_ssr_field_t SSR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs47_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs47_i2c_ismk_field_t ISMK_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t FCR; + stc_mfs47_i2c_fcr_field_t FCR_f; + }; + struct { + union { + __IO uint8_t FCR0; + stc_mfs47_i2c_fcr0_field_t FCR0_f; + }; + union { + __IO uint8_t FCR1; + stc_mfs47_i2c_fcr1_field_t FCR1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t FBYTE; + stc_mfs47_i2c_fbyte_field_t FBYTE_f; + }; + struct { + union { + __IO uint8_t FBYTE1; + stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; + }; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * MFS_NFC_MODULE + ******************************************************************************/ +/* MFS_NFC_MODULE register bit fields */ +typedef struct +{ + union { + __IO uint16_t I2CDNF; + stc_mfs_nfc_i2cdnf_field_t I2CDNF_f; + }; +}FM3_MFS_NFC_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode0_field_t MODE0_f; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode1_field_t MODE1_f; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode2_field_t MODE2_f; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode3_field_t MODE3_f; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode4_field_t MODE4_f; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode5_field_t MODE5_f; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode6_field_t MODE6_f; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode7_field_t MODE7_f; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim0_field_t TIM0_f; + }; + union { + __IO uint32_t TIM1; + stc_exbus_tim1_field_t TIM1_f; + }; + union { + __IO uint32_t TIM2; + stc_exbus_tim2_field_t TIM2_f; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim3_field_t TIM3_f; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim4_field_t TIM4_f; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim5_field_t TIM5_f; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim6_field_t TIM6_f; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim7_field_t TIM7_f; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area0_field_t AREA0_f; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area1_field_t AREA1_f; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area2_field_t AREA2_f; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area3_field_t AREA3_f; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area4_field_t AREA4_f; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area5_field_t AREA5_f; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area6_field_t AREA6_f; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area7_field_t AREA7_f; + }; + union { + __IO uint16_t ATIM0; + stc_exbus_atim0_field_t ATIM0_f; + }; + uint8_t RESERVED0[2]; + union { + __IO uint16_t ATIM1; + stc_exbus_atim1_field_t ATIM1_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint16_t ATIM2; + stc_exbus_atim2_field_t ATIM2_f; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t ATIM3; + stc_exbus_atim3_field_t ATIM3_f; + }; + uint8_t RESERVED3[2]; + union { + __IO uint16_t ATIM4; + stc_exbus_atim4_field_t ATIM4_f; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t ATIM5; + stc_exbus_atim5_field_t ATIM5_f; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t ATIM6; + stc_exbus_atim6_field_t ATIM6_f; + }; + uint8_t RESERVED6[2]; + union { + __IO uint16_t ATIM7; + stc_exbus_atim7_field_t ATIM7_f; + }; + uint8_t RESERVED7[642]; + union { + __IO uint8_t DCLKR; + stc_exbus_dclkr_field_t DCLKR_f; + }; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + }; + struct { + union { + __IO uint8_t HCNT0; + stc_usb_hcnt0_field_t HCNT0_f; + }; + union { + __IO uint8_t HCNT1; + stc_usb_hcnt1_field_t HCNT1_f; + }; + }; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + }; + struct { + union { + __IO uint8_t HRTIMER0; + stc_usb_hrtimer0_field_t HRTIMER0_f; + }; + union { + __IO uint8_t HRTIMER1; + stc_usb_hrtimer1_field_t HRTIMER1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + }; + struct { + union { + __IO uint8_t HEOF0; + stc_usb_heof0_field_t HEOF0_f; + }; + union { + __IO uint8_t HEOF1; + stc_usb_heof1_field_t HEOF1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + }; + struct { + union { + __IO uint8_t HFRAME0; + stc_usb_hframe0_field_t HFRAME0_f; + }; + union { + __IO uint8_t HFRAME1; + stc_usb_hframe1_field_t HFRAME1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + }; + uint8_t RESERVED19[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + }; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + }; + uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + }; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + }; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + }; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + }; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + }; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + }; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + }; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + }; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * ETHERNET_MAC_MODULE + ******************************************************************************/ +/* ETHERNET-MAC registers */ +typedef struct +{ + union { + __IO uint32_t MCR; + stc_ethernet_mac_mcr_field_t MCR_f; + }; + union { + __IO uint32_t MFFR; + stc_ethernet_mac_mffr_field_t MFFR_f; + }; + union { + __IO uint32_t MHTRH; + stc_ethernet_mac_mhtrh_field_t MHTRH_f; + }; + union { + __IO uint32_t MHTRL; + stc_ethernet_mac_mhtrl_field_t MHTRL_f; + }; + union { + __IO uint32_t GAR; + stc_ethernet_mac_gar_field_t GAR_f; + }; + union { + __IO uint32_t GDR; + stc_ethernet_mac_gdr_field_t GDR_f; + }; + union { + __IO uint32_t FCR; + stc_ethernet_mac_fcr_field_t FCR_f; + }; + union { + __IO uint32_t VTR; + stc_ethernet_mac_vtr_field_t VTR_f; + }; + uint8_t RESERVED0[8]; + union { + __IO uint32_t RWFFR; + stc_ethernet_mac_rwffr_field_t RWFFR_f; + }; + union { + __IO uint32_t PMTR; + stc_ethernet_mac_pmtr_field_t PMTR_f; + }; + union { + __IO uint32_t LPICSR; + stc_ethernet_mac_lpicsr_field_t LPICSR_f; + }; + union { + __IO uint32_t LPITCR; + stc_ethernet_mac_lpitcr_field_t LPITCR_f; + }; + union { + __IO uint32_t ISR; + stc_ethernet_mac_isr_field_t ISR_f; + }; + union { + __IO uint32_t IMR; + stc_ethernet_mac_imr_field_t IMR_f; + }; + union { + __IO uint32_t MAR0H; + stc_ethernet_mac_mar0h_field_t MAR0H_f; + }; + union { + __IO uint32_t MAR0L; + stc_ethernet_mac_mar0l_field_t MAR0L_f; + }; + union { + __IO uint32_t MAR1H; + stc_ethernet_mac_mar1h_field_t MAR1H_f; + }; + union { + __IO uint32_t MAR1L; + stc_ethernet_mac_mar1l_field_t MAR1L_f; + }; + union { + __IO uint32_t MAR2H; + stc_ethernet_mac_mar2h_field_t MAR2H_f; + }; + union { + __IO uint32_t MAR2L; + stc_ethernet_mac_mar2l_field_t MAR2L_f; + }; + union { + __IO uint32_t MAR3H; + stc_ethernet_mac_mar3h_field_t MAR3H_f; + }; + union { + __IO uint32_t MAR3L; + stc_ethernet_mac_mar3l_field_t MAR3L_f; + }; + union { + __IO uint32_t MAR4H; + stc_ethernet_mac_mar4h_field_t MAR4H_f; + }; + union { + __IO uint32_t MAR4L; + stc_ethernet_mac_mar4l_field_t MAR4L_f; + }; + union { + __IO uint32_t MAR5H; + stc_ethernet_mac_mar5h_field_t MAR5H_f; + }; + union { + __IO uint32_t MAR5L; + stc_ethernet_mac_mar5l_field_t MAR5L_f; + }; + union { + __IO uint32_t MAR6H; + stc_ethernet_mac_mar6h_field_t MAR6H_f; + }; + union { + __IO uint32_t MAR6L; + stc_ethernet_mac_mar6l_field_t MAR6L_f; + }; + union { + __IO uint32_t MAR7H; + stc_ethernet_mac_mar7h_field_t MAR7H_f; + }; + union { + __IO uint32_t MAR7L; + stc_ethernet_mac_mar7l_field_t MAR7L_f; + }; + union { + __IO uint32_t MAR8H; + stc_ethernet_mac_mar8h_field_t MAR8H_f; + }; + union { + __IO uint32_t MAR8L; + stc_ethernet_mac_mar8l_field_t MAR8L_f; + }; + union { + __IO uint32_t MAR9H; + stc_ethernet_mac_mar9h_field_t MAR9H_f; + }; + union { + __IO uint32_t MAR9L; + stc_ethernet_mac_mar9l_field_t MAR9L_f; + }; + union { + __IO uint32_t MAR10H; + stc_ethernet_mac_mar10h_field_t MAR10H_f; + }; + union { + __IO uint32_t MAR10L; + stc_ethernet_mac_mar10l_field_t MAR10L_f; + }; + union { + __IO uint32_t MAR11H; + stc_ethernet_mac_mar11h_field_t MAR11H_f; + }; + union { + __IO uint32_t MAR11L; + stc_ethernet_mac_mar11l_field_t MAR11L_f; + }; + union { + __IO uint32_t MAR12H; + stc_ethernet_mac_mar12h_field_t MAR12H_f; + }; + union { + __IO uint32_t MAR12L; + stc_ethernet_mac_mar12l_field_t MAR12L_f; + }; + union { + __IO uint32_t MAR13H; + stc_ethernet_mac_mar13h_field_t MAR13H_f; + }; + union { + __IO uint32_t MAR13L; + stc_ethernet_mac_mar13l_field_t MAR13L_f; + }; + union { + __IO uint32_t MAR14H; + stc_ethernet_mac_mar14h_field_t MAR14H_f; + }; + union { + __IO uint32_t MAR14L; + stc_ethernet_mac_mar14l_field_t MAR14L_f; + }; + union { + __IO uint32_t MAR15H; + stc_ethernet_mac_mar15h_field_t MAR15H_f; + }; + union { + __IO uint32_t MAR15L; + stc_ethernet_mac_mar15l_field_t MAR15L_f; + }; + uint8_t RESERVED1[24]; + union { + __IO uint32_t RGSR; + stc_ethernet_mac_rgsr_field_t RGSR_f; + }; + uint8_t RESERVED2[36]; + __IO uint32_t mmc_cntl; + __IO uint32_t mmc_intr_rx; + __IO uint32_t mmc_intr_tx; + __IO uint32_t mmc_intr_mask_rx; + __IO uint32_t mmc_intr_mask_tx; + __IO uint32_t txoctetcount_gb; + __IO uint32_t txframecount_gb; + __IO uint32_t txbroadcastframes_g; + __IO uint32_t txmulticastframes_g; + __IO uint32_t tx64octets_gb; + __IO uint32_t tx65to127octets_gb; + __IO uint32_t tx128to255octets_gb; + __IO uint32_t tx256to511octets_gb; + __IO uint32_t tx512to1023octets_gb; + __IO uint32_t tx1024tomaxoctets_gb; + __IO uint32_t txunicastframes_gb; + __IO uint32_t txmulticastframes_gb; + __IO uint32_t txbroadcastframes_gb; + __IO uint32_t txunderflowerror; + __IO uint32_t txsinglecol_g; + __IO uint32_t txmulticol_g; + __IO uint32_t txdeferred; + __IO uint32_t txlatecol; + __IO uint32_t txexesscol; + __IO uint32_t txcarriererror; + __IO uint32_t txoctetcount_g; + __IO uint32_t txframecount_g; + __IO uint32_t txexecessdef_g; + __IO uint32_t txpauseframes; + __IO uint32_t txvlanframes_g; + uint8_t RESERVED3[8]; + __IO uint32_t rxframecount_gb; + __IO uint32_t rxoctetcount_gb; + __IO uint32_t rxoctetcount_g; + __IO uint32_t rxbroadcastframes_g; + __IO uint32_t rxmulticastframes_g; + __IO uint32_t rxcrcerror; + __IO uint32_t rxallignmenterror; + __IO uint32_t rxrunterror; + __IO uint32_t rxjabbererror; + __IO uint32_t rxundersize_g; + __IO uint32_t rxoversize_g; + __IO uint32_t rx64octets_gb; + __IO uint32_t rx65to127octets_gb; + __IO uint32_t rx128to255octets_gb; + __IO uint32_t rx256to511octets_gb; + __IO uint32_t rx512to1023octets_gb; + __IO uint32_t rx1024tomaxoctets_gb; + __IO uint32_t rxunicastframes_g; + __IO uint32_t rxlengtherror; + __IO uint32_t rxoutofrangetype; + __IO uint32_t rxpauseframes; + __IO uint32_t rxfifooverflow; + __IO uint32_t rxvlanframes_gb; + __IO uint32_t rxwatchdogerror; + uint8_t RESERVED4[32]; + __IO uint32_t mmc_ipc_intr_mask_rx; + uint8_t RESERVED5[4]; + __IO uint32_t mmc_ipc_intr_rx; + uint8_t RESERVED6[4]; + __IO uint32_t rxipv4_gd_frms; + __IO uint32_t rxipv4_hdrerr_frms; + __IO uint32_t rxipv4_nopay_frms; + __IO uint32_t rxipv4_frag_frms; + __IO uint32_t rxipv4_udsbl_frms; + __IO uint32_t rxipv6_gd_frms; + __IO uint32_t rxipv6_hdrerr_frms; + __IO uint32_t rxipv6_nopay_frms; + __IO uint32_t rxudp_gd_frms; + __IO uint32_t rxudp_err_frms; + __IO uint32_t rxtcp_gd_frms; + __IO uint32_t rxtcp_err_frms; + __IO uint32_t rxicmp_gd_frms; + __IO uint32_t rxicmp_err_frms; + uint8_t RESERVED7[8]; + __IO uint32_t rxipv4_gd_octets; + __IO uint32_t rxipv4_hdrerr_octets; + __IO uint32_t rxipv4_nopay_octets; + __IO uint32_t rxipv4_frag_octets; + __IO uint32_t rxipv4_udsbl_octets; + __IO uint32_t rxipv6_gd_octets; + __IO uint32_t rxipv6_hdrerr_octets; + __IO uint32_t rxipv6_nopay_octets; + __IO uint32_t rxudp_gd_octets; + __IO uint32_t rxudp_err_octets; + __IO uint32_t rxtcp_gd_octets; + __IO uint32_t rxtcp_err_octets; + __IO uint32_t rxicmp_gd_octets; + __IO uint32_t rxicmp_err_octets; + uint8_t RESERVED8[1144]; + union { + __IO uint32_t TSCR; + stc_ethernet_mac_tscr_field_t TSCR_f; + }; + union { + __IO uint32_t SSIR; + stc_ethernet_mac_ssir_field_t SSIR_f; + }; + union { + __IO uint32_t STSR; + stc_ethernet_mac_stsr_field_t STSR_f; + }; + union { + __IO uint32_t STNR; + stc_ethernet_mac_stnr_field_t STNR_f; + }; + union { + __IO uint32_t STSUR; + stc_ethernet_mac_stsur_field_t STSUR_f; + }; + union { + __IO uint32_t STNUR; + stc_ethernet_mac_stnur_field_t STNUR_f; + }; + union { + __IO uint32_t TSAR; + stc_ethernet_mac_tsar_field_t TSAR_f; + }; + union { + __IO uint32_t TTSR; + stc_ethernet_mac_ttsr_field_t TTSR_f; + }; + union { + __IO uint32_t TTNR; + stc_ethernet_mac_ttnr_field_t TTNR_f; + }; + union { + __IO uint32_t STHWSR; + stc_ethernet_mac_sthwsr_field_t STHWSR_f; + }; + union { + __IO uint32_t TSR; + stc_ethernet_mac_tsr_field_t TSR_f; + }; + union { + __IO uint32_t PPSCR; + stc_ethernet_mac_ppscr_field_t PPSCR_f; + }; + union { + __IO uint32_t ATNR; + stc_ethernet_mac_atnr_field_t ATNR_f; + }; + union { + __IO uint32_t ATSR; + stc_ethernet_mac_atsr_field_t ATSR_f; + }; + uint8_t RESERVED9[200]; + union { + __IO uint32_t MAR16H; + stc_ethernet_mac_mar16h_field_t MAR16H_f; + }; + union { + __IO uint32_t MAR16L; + stc_ethernet_mac_mar16l_field_t MAR16L_f; + }; + union { + __IO uint32_t MAR17H; + stc_ethernet_mac_mar17h_field_t MAR17H_f; + }; + union { + __IO uint32_t MAR17L; + stc_ethernet_mac_mar17l_field_t MAR17L_f; + }; + union { + __IO uint32_t MAR18H; + stc_ethernet_mac_mar18h_field_t MAR18H_f; + }; + union { + __IO uint32_t MAR18L; + stc_ethernet_mac_mar18l_field_t MAR18L_f; + }; + union { + __IO uint32_t MAR19H; + stc_ethernet_mac_mar19h_field_t MAR19H_f; + }; + union { + __IO uint32_t MAR19L; + stc_ethernet_mac_mar19l_field_t MAR19L_f; + }; + union { + __IO uint32_t MAR20H; + stc_ethernet_mac_mar20h_field_t MAR20H_f; + }; + union { + __IO uint32_t MAR20L; + stc_ethernet_mac_mar20l_field_t MAR20L_f; + }; + union { + __IO uint32_t MAR21H; + stc_ethernet_mac_mar21h_field_t MAR21H_f; + }; + union { + __IO uint32_t MAR21L; + stc_ethernet_mac_mar21l_field_t MAR21L_f; + }; + union { + __IO uint32_t MAR22H; + stc_ethernet_mac_mar22h_field_t MAR22H_f; + }; + union { + __IO uint32_t MAR22L; + stc_ethernet_mac_mar22l_field_t MAR22L_f; + }; + union { + __IO uint32_t MAR23H; + stc_ethernet_mac_mar23h_field_t MAR23H_f; + }; + union { + __IO uint32_t MAR23L; + stc_ethernet_mac_mar23l_field_t MAR23L_f; + }; + union { + __IO uint32_t MAR24H; + stc_ethernet_mac_mar24h_field_t MAR24H_f; + }; + union { + __IO uint32_t MAR24L; + stc_ethernet_mac_mar24l_field_t MAR24L_f; + }; + union { + __IO uint32_t MAR25H; + stc_ethernet_mac_mar25h_field_t MAR25H_f; + }; + union { + __IO uint32_t MAR25L; + stc_ethernet_mac_mar25l_field_t MAR25L_f; + }; + union { + __IO uint32_t MAR26H; + stc_ethernet_mac_mar26h_field_t MAR26H_f; + }; + union { + __IO uint32_t MAR26L; + stc_ethernet_mac_mar26l_field_t MAR26L_f; + }; + union { + __IO uint32_t MAR27H; + stc_ethernet_mac_mar27h_field_t MAR27H_f; + }; + union { + __IO uint32_t MAR27L; + stc_ethernet_mac_mar27l_field_t MAR27L_f; + }; + union { + __IO uint32_t MAR28H; + stc_ethernet_mac_mar28h_field_t MAR28H_f; + }; + union { + __IO uint32_t MAR28L; + stc_ethernet_mac_mar28l_field_t MAR28L_f; + }; + union { + __IO uint32_t MAR29H; + stc_ethernet_mac_mar29h_field_t MAR29H_f; + }; + union { + __IO uint32_t MAR29L; + stc_ethernet_mac_mar29l_field_t MAR29L_f; + }; + union { + __IO uint32_t MAR30H; + stc_ethernet_mac_mar30h_field_t MAR30H_f; + }; + union { + __IO uint32_t MAR30L; + stc_ethernet_mac_mar30l_field_t MAR30L_f; + }; + union { + __IO uint32_t MAR31H; + stc_ethernet_mac_mar31h_field_t MAR31H_f; + }; + union { + __IO uint32_t MAR31L; + stc_ethernet_mac_mar31l_field_t MAR31L_f; + }; + uint8_t RESERVED10[1920]; + union { + __IO uint32_t BMR; + stc_ethernet_mac_bmr_field_t BMR_f; + }; + union { + __IO uint32_t TPDR; + stc_ethernet_mac_tpdr_field_t TPDR_f; + }; + union { + __IO uint32_t RPDR; + stc_ethernet_mac_rpdr_field_t RPDR_f; + }; + union { + __IO uint32_t RDLAR; + stc_ethernet_mac_rdlar_field_t RDLAR_f; + }; + union { + __IO uint32_t TDLAR; + stc_ethernet_mac_tdlar_field_t TDLAR_f; + }; + union { + __IO uint32_t SR; + stc_ethernet_mac_sr_field_t SR_f; + }; + union { + __IO uint32_t OMR; + stc_ethernet_mac_omr_field_t OMR_f; + }; + union { + __IO uint32_t IER; + stc_ethernet_mac_ier_field_t IER_f; + }; + union { + __IO uint32_t MFBOCR; + stc_ethernet_mac_mfbocr_field_t MFBOCR_f; + }; + union { + __IO uint32_t RIWTR; + stc_ethernet_mac_riwtr_field_t RIWTR_f; + }; + uint8_t RESERVED11[4]; + union { + __IO uint32_t AHBSR; + stc_ethernet_mac_ahbsr_field_t AHBSR_f; + }; + uint8_t RESERVED12[24]; + union { + __IO uint32_t CHTDR; + stc_ethernet_mac_chtdr_field_t CHTDR_f; + }; + union { + __IO uint32_t CHRDR; + stc_ethernet_mac_chrdr_field_t CHRDR_f; + }; + union { + __IO uint32_t CHTBAR; + stc_ethernet_mac_chtbar_field_t CHTBAR_f; + }; + union { + __IO uint32_t CHRBAR; + stc_ethernet_mac_chrbar_field_t CHRBAR_f; + }; +}FM3_ETHERNET_MAC_TypeDef; + +/* ETHERNET-CONTROL registers */ +typedef struct +{ + union { + __IO uint32_t ETH_MODE; + stc_ethernet_control_eth_mode_field_t ETH_MODE_f; + }; + uint8_t RESERVED1[4]; + union { + __IO uint32_t ETH_CLKG; + stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f; + }; +}FM3_ETHERNET_CONTROL_TypeDef; + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT2_FRT_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Free Running Timer registers */ +#define FM3_MFT2_OCU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ +#define FM3_MFT2_WFG_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT2_ICU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ +#define FM3_MFT2_ADCMP_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_BT8_PPG_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ +#define FM3_BT8_PWM_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ +#define FM3_BT8_RT_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ +#define FM3_BT8_PWC_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ +#define FM3_BT9_PPG_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ +#define FM3_BT9_PWM_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ +#define FM3_BT9_RT_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ +#define FM3_BT9_PWC_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ +#define FM3_BT10_PPG_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ +#define FM3_BT10_PWM_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ +#define FM3_BT10_RT_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ +#define FM3_BT10_PWC_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ +#define FM3_BT11_PPG_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ +#define FM3_BT11_PWM_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ +#define FM3_BT11_RT_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ +#define FM3_BT11_PWC_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ +#define FM3_BT12_PPG_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ +#define FM3_BT12_PWM_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ +#define FM3_BT12_RT_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ +#define FM3_BT12_PWC_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ +#define FM3_BT13_PPG_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ +#define FM3_BT13_PWM_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ +#define FM3_BT13_RT_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ +#define FM3_BT13_PWC_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ +#define FM3_BT14_PPG_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ +#define FM3_BT14_PWM_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ +#define FM3_BT14_RT_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ +#define FM3_BT14_PWC_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ +#define FM3_BT15_PPG_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ +#define FM3_BT15_PWM_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ +#define FM3_BT15_RT_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ +#define FM3_BT15_PWC_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ +#define FM3_BTIOSEL8B_BASE (FM3_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ +#define FM3_BTIOSELCF_BASE (FM3_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_QPRC2_BASE (FM3_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_MFS_NFC_BASE (FM3_PERIPH_BASE + 0x38800UL) /* MFS Noise Filter Control register */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_USB1_BASE (FM3_PERIPH_BASE + 0x52100UL) /* USB channel 1 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_ETHERNET_MAC0_BASE (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers */ +#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers */ +#define FM3_ETHERNET_MAC1_BASE (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT2_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE) +#define FM3_MFT2_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE) +#define FM3_MFT2_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE) +#define FM3_MFT2_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE) +#define FM3_MFT2_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_BT8_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE) +#define FM3_BT8_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE) +#define FM3_BT8_RT ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE) +#define FM3_BT8_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE) +#define FM3_BT9_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE) +#define FM3_BT9_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE) +#define FM3_BT9_RT ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE) +#define FM3_BT9_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE) +#define FM3_BT10_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE) +#define FM3_BT10_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE) +#define FM3_BT10_RT ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE) +#define FM3_BT10_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE) +#define FM3_BT11_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE) +#define FM3_BT11_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE) +#define FM3_BT11_RT ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE) +#define FM3_BT11_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE) +#define FM3_BT12_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE) +#define FM3_BT12_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE) +#define FM3_BT12_RT ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE) +#define FM3_BT12_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE) +#define FM3_BT13_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE) +#define FM3_BT13_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE) +#define FM3_BT13_RT ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE) +#define FM3_BT13_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE) +#define FM3_BT14_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE) +#define FM3_BT14_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE) +#define FM3_BT14_RT ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE) +#define FM3_BT14_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE) +#define FM3_BT15_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE) +#define FM3_BT15_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE) +#define FM3_BT15_RT ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE) +#define FM3_BT15_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE) +#define FM3_BTIOSEL8B ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE) +#define FM3_BTIOSELCF ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_QPRC2 ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_MFS_NFC ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_USB1 ((FM3_USB_TypeDef *)FM3_USB1_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_ETHERNET_MAC0 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE) +#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_SET_TypeDef *)FM3_ETHERNET_SET_BASE) +#define FM3_ETHERNET_MAC1 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_FBFCR_BE *((volatile unsigned int*)(0x42000280UL)) +#define bFM3_FLASH_IF_FBFCR_BS *((volatile unsigned int*)(0x42000284UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMER1RIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMER1MIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMER2RIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMER2MIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer unit 2 Free Running Timer registers */ +#define bFM3_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42440600UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42440604UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42440608UL)) +#define bFM3_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244060CUL)) +#define bFM3_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42440610UL)) +#define bFM3_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42440614UL)) +#define bFM3_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42440618UL)) +#define bFM3_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244061CUL)) +#define bFM3_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42440620UL)) +#define bFM3_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42440624UL)) +#define bFM3_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42440634UL)) +#define bFM3_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42440638UL)) +#define bFM3_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244063CUL)) +#define bFM3_MFT2_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42440680UL)) +#define bFM3_MFT2_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42440684UL)) +#define bFM3_MFT2_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42440688UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42440800UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42440804UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42440808UL)) +#define bFM3_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4244080CUL)) +#define bFM3_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42440810UL)) +#define bFM3_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42440814UL)) +#define bFM3_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42440818UL)) +#define bFM3_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4244081CUL)) +#define bFM3_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42440820UL)) +#define bFM3_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42440824UL)) +#define bFM3_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42440834UL)) +#define bFM3_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42440838UL)) +#define bFM3_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4244083CUL)) +#define bFM3_MFT2_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42440880UL)) +#define bFM3_MFT2_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42440884UL)) +#define bFM3_MFT2_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42440888UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42440A00UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42440A04UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42440A08UL)) +#define bFM3_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42440A0CUL)) +#define bFM3_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42440A10UL)) +#define bFM3_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42440A14UL)) +#define bFM3_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42440A18UL)) +#define bFM3_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42440A1CUL)) +#define bFM3_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42440A20UL)) +#define bFM3_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42440A24UL)) +#define bFM3_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42440A34UL)) +#define bFM3_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42440A38UL)) +#define bFM3_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42440A3CUL)) +#define bFM3_MFT2_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42440A80UL)) +#define bFM3_MFT2_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42440A84UL)) +#define bFM3_MFT2_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42440A88UL)) + +/* Multifunction Timer unit 2 Output Compare Unit registers */ +#define bFM3_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42440300UL)) +#define bFM3_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42440304UL)) +#define bFM3_MFT2_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42440308UL)) +#define bFM3_MFT2_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4244030CUL)) +#define bFM3_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42440310UL)) +#define bFM3_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42440314UL)) +#define bFM3_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42440318UL)) +#define bFM3_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244031CUL)) +#define bFM3_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42440320UL)) +#define bFM3_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42440324UL)) +#define bFM3_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42440330UL)) +#define bFM3_MFT2_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42440334UL)) +#define bFM3_MFT2_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42440338UL)) +#define bFM3_MFT2_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42440380UL)) +#define bFM3_MFT2_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42440384UL)) +#define bFM3_MFT2_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42440388UL)) +#define bFM3_MFT2_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4244038CUL)) +#define bFM3_MFT2_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42440390UL)) +#define bFM3_MFT2_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42440394UL)) +#define bFM3_MFT2_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42440398UL)) +#define bFM3_MFT2_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4244039CUL)) +#define bFM3_MFT2_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424403A0UL)) +#define bFM3_MFT2_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424403A4UL)) +#define bFM3_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424403B0UL)) +#define bFM3_MFT2_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424403B4UL)) +#define bFM3_MFT2_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424403B8UL)) +#define bFM3_MFT2_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42440400UL)) +#define bFM3_MFT2_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42440404UL)) +#define bFM3_MFT2_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42440408UL)) +#define bFM3_MFT2_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4244040CUL)) +#define bFM3_MFT2_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42440410UL)) +#define bFM3_MFT2_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42440414UL)) +#define bFM3_MFT2_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42440418UL)) +#define bFM3_MFT2_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4244041CUL)) +#define bFM3_MFT2_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42440420UL)) +#define bFM3_MFT2_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42440424UL)) +#define bFM3_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42440430UL)) +#define bFM3_MFT2_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42440434UL)) +#define bFM3_MFT2_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42440438UL)) +#define bFM3_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424404A0UL)) +#define bFM3_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424404A4UL)) +#define bFM3_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424404A8UL)) +#define bFM3_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424404ACUL)) +#define bFM3_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424404B0UL)) +#define bFM3_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424404B4UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42440B00UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42440B04UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42440B08UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42440B0CUL)) +#define bFM3_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42440B10UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42440B14UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42440B18UL)) +#define bFM3_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42440B1CUL)) +#define bFM3_MFT2_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42440B20UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42440B24UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42440B28UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42440B2CUL)) +#define bFM3_MFT2_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42440B30UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42440B34UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42440B38UL)) +#define bFM3_MFT2_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42440B3CUL)) +#define bFM3_MFT2_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42440B80UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42440B84UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42440B88UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42440B8CUL)) +#define bFM3_MFT2_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42440B90UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42440B94UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42440B98UL)) +#define bFM3_MFT2_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42440B9CUL)) + +/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42441180UL)) +#define bFM3_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42441184UL)) +#define bFM3_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42441188UL)) +#define bFM3_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42441198UL)) +#define bFM3_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244119CUL)) +#define bFM3_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424411A0UL)) +#define bFM3_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424411A4UL)) +#define bFM3_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424411A8UL)) +#define bFM3_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424411ACUL)) +#define bFM3_MFT2_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424411B0UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42441200UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42441204UL)) +#define bFM3_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42441208UL)) +#define bFM3_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42441218UL)) +#define bFM3_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244121CUL)) +#define bFM3_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42441220UL)) +#define bFM3_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42441224UL)) +#define bFM3_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42441228UL)) +#define bFM3_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244122CUL)) +#define bFM3_MFT2_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42441230UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42441280UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42441284UL)) +#define bFM3_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42441288UL)) +#define bFM3_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42441298UL)) +#define bFM3_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244129CUL)) +#define bFM3_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424412A0UL)) +#define bFM3_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424412A4UL)) +#define bFM3_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424412A8UL)) +#define bFM3_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424412ACUL)) +#define bFM3_MFT2_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424412B0UL)) +#define bFM3_MFT2_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42441300UL)) +#define bFM3_MFT2_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42441304UL)) +#define bFM3_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42441310UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42441314UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42441318UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244131CUL)) +#define bFM3_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42441320UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42441324UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42441328UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244132CUL)) +#define bFM3_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42441330UL)) +#define bFM3_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42441334UL)) +#define bFM3_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42441338UL)) +#define bFM3_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244133CUL)) +#define bFM3_MFT2_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42441380UL)) +#define bFM3_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42441384UL)) +#define bFM3_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42441388UL)) +#define bFM3_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244138CUL)) +#define bFM3_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42441390UL)) + +/* Multifunction Timer unit 2 Input Capture Unit registers */ +#define bFM3_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42440C00UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42440C04UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42440C08UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42440C0CUL)) +#define bFM3_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42440C10UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42440C14UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42440C18UL)) +#define bFM3_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42440C1CUL)) +#define bFM3_MFT2_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42440C20UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42440C24UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42440C28UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42440C2CUL)) +#define bFM3_MFT2_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42440C30UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42440C34UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42440C38UL)) +#define bFM3_MFT2_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42440C3CUL)) +#define bFM3_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42440F00UL)) +#define bFM3_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42440F04UL)) +#define bFM3_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42440F08UL)) +#define bFM3_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42440F0CUL)) +#define bFM3_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42440F10UL)) +#define bFM3_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42440F14UL)) +#define bFM3_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42440F18UL)) +#define bFM3_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42440F1CUL)) +#define bFM3_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42440F20UL)) +#define bFM3_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42440F24UL)) +#define bFM3_MFT2_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42440F80UL)) +#define bFM3_MFT2_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42440F84UL)) +#define bFM3_MFT2_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42440F88UL)) +#define bFM3_MFT2_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42440F8CUL)) +#define bFM3_MFT2_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42440F90UL)) +#define bFM3_MFT2_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42440F94UL)) +#define bFM3_MFT2_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42440F98UL)) +#define bFM3_MFT2_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42440F9CUL)) +#define bFM3_MFT2_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42440FA0UL)) +#define bFM3_MFT2_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42440FA4UL)) + +/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ +#define bFM3_MFT2_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42441700UL)) +#define bFM3_MFT2_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42441704UL)) +#define bFM3_MFT2_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42441708UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42441710UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42441714UL)) +#define bFM3_MFT2_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42441718UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42441780UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42441784UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42441788UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4244178CUL)) +#define bFM3_MFT2_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42441790UL)) +#define bFM3_MFT2_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42441794UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424417A0UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424417A4UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424417A8UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424417ACUL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424417B0UL)) +#define bFM3_MFT2_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424417B4UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42441800UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42441804UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42441808UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4244180CUL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42441810UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42441814UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42441820UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42441824UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42441828UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4244182CUL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42441830UL)) +#define bFM3_MFT2_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42441834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) +#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) +#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) +#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) +#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) +#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) +#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) +#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) +#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) +#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) +#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) +#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) +#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) +#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) +#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) +#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) +#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) +#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) +#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) +#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) +#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) +#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) +#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) +#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) +#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) +#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) +#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) +#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) +#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) +#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) +#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) +#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) +#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) +#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) +#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) +#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) +#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) +#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) +#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) +#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) +#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) +#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) +#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) +#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) +#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) +#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) +#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) +#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) +#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) +#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) +#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) +#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) +#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) +#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) +#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) +#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) +#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) +#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) +#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) +#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) +#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) +#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) +#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) +#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) +#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) +#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) +#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) +#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) +#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) +#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) +#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) +#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) +#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) +#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) +#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) +#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) +#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) +#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) +#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Base Timer 8 PPG registers */ +#define bFM3_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM3_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWM registers */ +#define bFM3_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) +#define bFM3_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) +#define bFM3_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) +#define bFM3_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 RT registers */ +#define bFM3_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) +#define bFM3_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) +#define bFM3_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM3_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 8 PWC registers */ +#define bFM3_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) +#define bFM3_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) +#define bFM3_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) +#define bFM3_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) +#define bFM3_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) +#define bFM3_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) +#define bFM3_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) +#define bFM3_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) +#define bFM3_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) +#define bFM3_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) +#define bFM3_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) +#define bFM3_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) +#define bFM3_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) +#define bFM3_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) +#define bFM3_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) + +/* Base Timer 9 PPG registers */ +#define bFM3_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM3_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWM registers */ +#define bFM3_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) +#define bFM3_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) +#define bFM3_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) +#define bFM3_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 RT registers */ +#define bFM3_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) +#define bFM3_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) +#define bFM3_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM3_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 9 PWC registers */ +#define bFM3_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) +#define bFM3_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) +#define bFM3_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) +#define bFM3_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) +#define bFM3_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) +#define bFM3_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) +#define bFM3_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) +#define bFM3_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) +#define bFM3_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) +#define bFM3_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) +#define bFM3_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) +#define bFM3_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) +#define bFM3_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) +#define bFM3_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) +#define bFM3_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) + +/* Base Timer 10 PPG registers */ +#define bFM3_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM3_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWM registers */ +#define bFM3_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) +#define bFM3_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) +#define bFM3_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) +#define bFM3_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 RT registers */ +#define bFM3_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) +#define bFM3_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) +#define bFM3_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM3_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 10 PWC registers */ +#define bFM3_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) +#define bFM3_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) +#define bFM3_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) +#define bFM3_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) +#define bFM3_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) +#define bFM3_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) +#define bFM3_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) +#define bFM3_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) +#define bFM3_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) +#define bFM3_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) +#define bFM3_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) +#define bFM3_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) +#define bFM3_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) +#define bFM3_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) +#define bFM3_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) + +/* Base Timer 11 PPG registers */ +#define bFM3_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM3_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWM registers */ +#define bFM3_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) +#define bFM3_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) +#define bFM3_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) +#define bFM3_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 RT registers */ +#define bFM3_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) +#define bFM3_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) +#define bFM3_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM3_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 11 PWC registers */ +#define bFM3_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) +#define bFM3_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) +#define bFM3_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) +#define bFM3_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) +#define bFM3_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) +#define bFM3_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) +#define bFM3_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) +#define bFM3_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) +#define bFM3_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) +#define bFM3_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) +#define bFM3_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) +#define bFM3_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) +#define bFM3_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) +#define bFM3_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) +#define bFM3_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) + +/* Base Timer 12 PPG registers */ +#define bFM3_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM3_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWM registers */ +#define bFM3_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) +#define bFM3_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) +#define bFM3_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) +#define bFM3_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 RT registers */ +#define bFM3_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) +#define bFM3_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) +#define bFM3_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM3_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 12 PWC registers */ +#define bFM3_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) +#define bFM3_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) +#define bFM3_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) +#define bFM3_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) +#define bFM3_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) +#define bFM3_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) +#define bFM3_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) +#define bFM3_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) +#define bFM3_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) +#define bFM3_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) +#define bFM3_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) +#define bFM3_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) +#define bFM3_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) +#define bFM3_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) +#define bFM3_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) + +/* Base Timer 13 PPG registers */ +#define bFM3_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM3_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWM registers */ +#define bFM3_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) +#define bFM3_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) +#define bFM3_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) +#define bFM3_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 RT registers */ +#define bFM3_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) +#define bFM3_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) +#define bFM3_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM3_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 13 PWC registers */ +#define bFM3_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) +#define bFM3_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) +#define bFM3_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) +#define bFM3_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) +#define bFM3_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) +#define bFM3_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) +#define bFM3_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) +#define bFM3_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) +#define bFM3_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) +#define bFM3_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) +#define bFM3_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) +#define bFM3_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) +#define bFM3_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) +#define bFM3_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) +#define bFM3_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) + +/* Base Timer 14 PPG registers */ +#define bFM3_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM3_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWM registers */ +#define bFM3_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) +#define bFM3_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) +#define bFM3_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) +#define bFM3_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 RT registers */ +#define bFM3_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) +#define bFM3_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) +#define bFM3_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM3_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 14 PWC registers */ +#define bFM3_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) +#define bFM3_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) +#define bFM3_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) +#define bFM3_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) +#define bFM3_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) +#define bFM3_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) +#define bFM3_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) +#define bFM3_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) +#define bFM3_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) +#define bFM3_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) +#define bFM3_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) +#define bFM3_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) +#define bFM3_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) +#define bFM3_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) +#define bFM3_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) + +/* Base Timer 15 PPG registers */ +#define bFM3_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM3_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWM registers */ +#define bFM3_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) +#define bFM3_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) +#define bFM3_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) +#define bFM3_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 RT registers */ +#define bFM3_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) +#define bFM3_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) +#define bFM3_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM3_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer 15 PWC registers */ +#define bFM3_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) +#define bFM3_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) +#define bFM3_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) +#define bFM3_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) +#define bFM3_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) +#define bFM3_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) +#define bFM3_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) +#define bFM3_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) +#define bFM3_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) +#define bFM3_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) +#define bFM3_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) +#define bFM3_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) +#define bFM3_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) +#define bFM3_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) +#define bFM3_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) + +/* Base Timer I/O selector channel 8 - channel 11 registers */ +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) +#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) + +/* Base Timer I/O selector channel 12 - channel 15 registers */ +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) +#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* Quad position and revolution counter channel 2 registers */ +#define bFM3_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM3_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM3_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM3_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM3_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM3_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM3_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM3_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM3_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM3_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM3_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM3_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM3_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM3_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM3_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) +#define bFM3_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) +#define bFM3_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) +#define bFM3_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) +#define bFM3_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) +#define bFM3_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) +#define bFM3_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) +#define bFM3_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) +#define bFM3_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) +#define bFM3_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) +#define bFM3_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) +#define bFM3_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) +#define bFM3_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) +#define bFM3_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) +#define bFM3_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM3_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM3_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM3_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM3_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM3_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM3_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM3_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM3_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM3_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM3_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM3_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM3_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM3_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM3_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM3_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM3_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) +#define bFM3_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) +#define bFM3_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) +#define bFM3_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) +#define bFM3_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) +#define bFM3_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) +#define bFM3_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) +#define bFM3_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) +#define bFM3_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) +#define bFM3_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) +#define bFM3_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) +#define bFM3_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) +#define bFM3_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) +#define bFM3_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) +#define bFM3_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) +#define bFM3_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) +#define bFM3_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) +#define bFM3_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) +#define bFM3_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) +#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) +#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) +#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) +#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) +#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) +#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) +#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) +#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) +#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) +#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) +#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) +#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) +#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) +#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) +#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) +#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) +#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) +#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) +#define bFM3_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) +#define bFM3_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) +#define bFM3_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) +#define bFM3_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) +#define bFM3_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) +#define bFM3_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) +#define bFM3_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) +#define bFM3_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) +#define bFM3_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) +#define bFM3_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) +#define bFM3_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) +#define bFM3_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) +#define bFM3_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) +#define bFM3_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) +#define bFM3_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) +#define bFM3_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) +#define bFM3_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) +#define bFM3_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) +#define bFM3_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) +#define bFM3_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) +#define bFM3_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) +#define bFM3_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) +#define bFM3_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) +#define bFM3_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) +#define bFM3_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) +#define bFM3_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) +#define bFM3_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) +#define bFM3_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) +#define bFM3_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) +#define bFM3_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) +#define bFM3_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) +#define bFM3_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) +#define bFM3_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) +#define bFM3_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) +#define bFM3_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) +#define bFM3_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) +#define bFM3_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) +#define bFM3_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) +#define bFM3_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) +#define bFM3_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) +#define bFM3_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) +#define bFM3_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) +#define bFM3_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) +#define bFM3_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) +#define bFM3_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_ELVR_LA16 *((volatile unsigned int*)(0x42600200UL)) +#define bFM3_EXTI_ELVR_LB16 *((volatile unsigned int*)(0x42600204UL)) +#define bFM3_EXTI_ELVR_LA17 *((volatile unsigned int*)(0x42600208UL)) +#define bFM3_EXTI_ELVR_LB17 *((volatile unsigned int*)(0x4260020CUL)) +#define bFM3_EXTI_ELVR_LA18 *((volatile unsigned int*)(0x42600210UL)) +#define bFM3_EXTI_ELVR_LB18 *((volatile unsigned int*)(0x42600214UL)) +#define bFM3_EXTI_ELVR_LA19 *((volatile unsigned int*)(0x42600218UL)) +#define bFM3_EXTI_ELVR_LB19 *((volatile unsigned int*)(0x4260021CUL)) +#define bFM3_EXTI_ELVR_LA20 *((volatile unsigned int*)(0x42600220UL)) +#define bFM3_EXTI_ELVR_LB20 *((volatile unsigned int*)(0x42600224UL)) +#define bFM3_EXTI_ELVR_LA21 *((volatile unsigned int*)(0x42600228UL)) +#define bFM3_EXTI_ELVR_LB21 *((volatile unsigned int*)(0x4260022CUL)) +#define bFM3_EXTI_ELVR_LA22 *((volatile unsigned int*)(0x42600230UL)) +#define bFM3_EXTI_ELVR_LB22 *((volatile unsigned int*)(0x42600234UL)) +#define bFM3_EXTI_ELVR_LA23 *((volatile unsigned int*)(0x42600238UL)) +#define bFM3_EXTI_ELVR_LB23 *((volatile unsigned int*)(0x4260023CUL)) +#define bFM3_EXTI_ELVR_LA24 *((volatile unsigned int*)(0x42600240UL)) +#define bFM3_EXTI_ELVR_LB24 *((volatile unsigned int*)(0x42600244UL)) +#define bFM3_EXTI_ELVR_LA25 *((volatile unsigned int*)(0x42600248UL)) +#define bFM3_EXTI_ELVR_LB25 *((volatile unsigned int*)(0x4260024CUL)) +#define bFM3_EXTI_ELVR_LA26 *((volatile unsigned int*)(0x42600250UL)) +#define bFM3_EXTI_ELVR_LB26 *((volatile unsigned int*)(0x42600254UL)) +#define bFM3_EXTI_ELVR_LA27 *((volatile unsigned int*)(0x42600258UL)) +#define bFM3_EXTI_ELVR_LB27 *((volatile unsigned int*)(0x4260025CUL)) +#define bFM3_EXTI_ELVR_LA28 *((volatile unsigned int*)(0x42600260UL)) +#define bFM3_EXTI_ELVR_LB28 *((volatile unsigned int*)(0x42600264UL)) +#define bFM3_EXTI_ELVR_LA29 *((volatile unsigned int*)(0x42600268UL)) +#define bFM3_EXTI_ELVR_LB29 *((volatile unsigned int*)(0x4260026CUL)) +#define bFM3_EXTI_ELVR_LA30 *((volatile unsigned int*)(0x42600270UL)) +#define bFM3_EXTI_ELVR_LB30 *((volatile unsigned int*)(0x42600274UL)) +#define bFM3_EXTI_ELVR_LA31 *((volatile unsigned int*)(0x42600278UL)) +#define bFM3_EXTI_ELVR_LB31 *((volatile unsigned int*)(0x4260027CUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned char*)(0x42620160UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned char*)(0x42620164UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned char*)(0x42620168UL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned char*)(0x4262016CUL)) +#define bFM3_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned char*)(0x42620170UL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT0 *((volatile unsigned int*)(0x42620420UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT1 *((volatile unsigned int*)(0x42620424UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT2 *((volatile unsigned int*)(0x42620428UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE2INT3 *((volatile unsigned int*)(0x4262042CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT8 *((volatile unsigned int*)(0x42620520UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT9 *((volatile unsigned int*)(0x42620524UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT10 *((volatile unsigned int*)(0x42620528UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT11 *((volatile unsigned int*)(0x4262052CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT12 *((volatile unsigned int*)(0x42620530UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT13 *((volatile unsigned int*)(0x42620534UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT14 *((volatile unsigned int*)(0x42620538UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT15 *((volatile unsigned int*)(0x4262053CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT16 *((volatile unsigned int*)(0x42620540UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT17 *((volatile unsigned int*)(0x42620544UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT18 *((volatile unsigned int*)(0x42620548UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT19 *((volatile unsigned int*)(0x4262054CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT20 *((volatile unsigned int*)(0x42620550UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT21 *((volatile unsigned int*)(0x42620554UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT22 *((volatile unsigned int*)(0x42620558UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT23 *((volatile unsigned int*)(0x4262055CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT2 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT0 *((volatile unsigned int*)(0x426205B8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT1 *((volatile unsigned int*)(0x426205BCUL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT2 *((volatile unsigned int*)(0x426205C0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT3 *((volatile unsigned int*)(0x426205C4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT4 *((volatile unsigned int*)(0x426205C8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD2INT5 *((volatile unsigned int*)(0x426205CCUL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT6 *((volatile unsigned int*)(0x42620E18UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT7 *((volatile unsigned int*)(0x42620E1CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT8 *((volatile unsigned int*)(0x42620E20UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT0 *((volatile unsigned int*)(0x426210B0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT1 *((volatile unsigned int*)(0x426210B4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT2 *((volatile unsigned int*)(0x426210B8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT3 *((volatile unsigned int*)(0x426210BCUL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT4 *((volatile unsigned int*)(0x426210C0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT2INT5 *((volatile unsigned int*)(0x426210C4UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT0 *((volatile unsigned int*)(0x42621120UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT1 *((volatile unsigned int*)(0x42621124UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT2 *((volatile unsigned int*)(0x42621128UL)) +#define bFM3_INTREQ_IRQ29MON_ICU2INT3 *((volatile unsigned int*)(0x4262112CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT0 *((volatile unsigned int*)(0x426211B0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT1 *((volatile unsigned int*)(0x426211B4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT2 *((volatile unsigned int*)(0x426211B8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT3 *((volatile unsigned int*)(0x426211BCUL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT4 *((volatile unsigned int*)(0x426211C0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU2INT5 *((volatile unsigned int*)(0x426211C4UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_MAC0SBD *((volatile unsigned int*)(0x42621284UL)) +#define bFM3_INTREQ_IRQ32MON_MAC0PMI *((volatile unsigned int*)(0x42621288UL)) +#define bFM3_INTREQ_IRQ32MON_MAC0LPI *((volatile unsigned int*)(0x4262128CUL)) +#define bFM3_INTREQ_IRQ33MON_MAC1SBD *((volatile unsigned int*)(0x42621304UL)) +#define bFM3_INTREQ_IRQ33MON_MAC1PMI *((volatile unsigned int*)(0x42621308UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT0 *((volatile unsigned int*)(0x42621480UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT1 *((volatile unsigned int*)(0x42621484UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT2 *((volatile unsigned int*)(0x42621488UL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT3 *((volatile unsigned int*)(0x4262148CUL)) +#define bFM3_INTREQ_IRQ36MON_USB1INT4 *((volatile unsigned int*)(0x42621490UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT0 *((volatile unsigned int*)(0x42621500UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT1 *((volatile unsigned int*)(0x42621504UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT2 *((volatile unsigned int*)(0x42621508UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT3 *((volatile unsigned int*)(0x4262150CUL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT4 *((volatile unsigned int*)(0x42621510UL)) +#define bFM3_INTREQ_IRQ37MON_USB1INT5 *((volatile unsigned int*)(0x42621514UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT0 *((volatile unsigned int*)(0x42621980UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT1 *((volatile unsigned int*)(0x42621984UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT2 *((volatile unsigned int*)(0x42621988UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT3 *((volatile unsigned int*)(0x4262198CUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT4 *((volatile unsigned int*)(0x42621990UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT5 *((volatile unsigned int*)(0x42621994UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT6 *((volatile unsigned int*)(0x42621998UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT7 *((volatile unsigned int*)(0x4262199CUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT8 *((volatile unsigned int*)(0x426219A0UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT9 *((volatile unsigned int*)(0x426219A4UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT10 *((volatile unsigned int*)(0x426219A8UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT11 *((volatile unsigned int*)(0x426219ACUL)) +#define bFM3_INTREQ_IRQ46MON_BTINT12 *((volatile unsigned int*)(0x426219B0UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT13 *((volatile unsigned int*)(0x426219B4UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT14 *((volatile unsigned int*)(0x426219B8UL)) +#define bFM3_INTREQ_IRQ46MON_BTINT15 *((volatile unsigned int*)(0x426219BCUL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL10 *((volatile unsigned int*)(0x42624000UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL11 *((volatile unsigned int*)(0x42624004UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL12 *((volatile unsigned int*)(0x42624008UL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL13 *((volatile unsigned int*)(0x4262400CUL)) +#define bFM3_INTREQ_DRQSEL1_DRQSEL14 *((volatile unsigned int*)(0x42624010UL)) +#define bFM3_INTREQ_DQESEL_ESEL100 *((volatile unsigned int*)(0x42624080UL)) +#define bFM3_INTREQ_DQESEL_ESEL101 *((volatile unsigned int*)(0x42624084UL)) +#define bFM3_INTREQ_DQESEL_ESEL102 *((volatile unsigned int*)(0x42624088UL)) +#define bFM3_INTREQ_DQESEL_ESEL103 *((volatile unsigned int*)(0x4262408CUL)) +#define bFM3_INTREQ_DQESEL_ESEL110 *((volatile unsigned int*)(0x42624090UL)) +#define bFM3_INTREQ_DQESEL_ESEL111 *((volatile unsigned int*)(0x42624094UL)) +#define bFM3_INTREQ_DQESEL_ESEL112 *((volatile unsigned int*)(0x42624098UL)) +#define bFM3_INTREQ_DQESEL_ESEL113 *((volatile unsigned int*)(0x4262409CUL)) +#define bFM3_INTREQ_DQESEL_ESEL240 *((volatile unsigned int*)(0x426240A0UL)) +#define bFM3_INTREQ_DQESEL_ESEL241 *((volatile unsigned int*)(0x426240A4UL)) +#define bFM3_INTREQ_DQESEL_ESEL242 *((volatile unsigned int*)(0x426240A8UL)) +#define bFM3_INTREQ_DQESEL_ESEL243 *((volatile unsigned int*)(0x426240ACUL)) +#define bFM3_INTREQ_DQESEL_ESEL250 *((volatile unsigned int*)(0x426240B0UL)) +#define bFM3_INTREQ_DQESEL_ESEL251 *((volatile unsigned int*)(0x426240B4UL)) +#define bFM3_INTREQ_DQESEL_ESEL252 *((volatile unsigned int*)(0x426240B8UL)) +#define bFM3_INTREQ_DQESEL_ESEL253 *((volatile unsigned int*)(0x426240BCUL)) +#define bFM3_INTREQ_DQESEL_ESEL260 *((volatile unsigned int*)(0x426240C0UL)) +#define bFM3_INTREQ_DQESEL_ESEL261 *((volatile unsigned int*)(0x426240C4UL)) +#define bFM3_INTREQ_DQESEL_ESEL262 *((volatile unsigned int*)(0x426240C8UL)) +#define bFM3_INTREQ_DQESEL_ESEL263 *((volatile unsigned int*)(0x426240CCUL)) +#define bFM3_INTREQ_DQESEL_ESEL270 *((volatile unsigned int*)(0x426240D0UL)) +#define bFM3_INTREQ_DQESEL_ESEL271 *((volatile unsigned int*)(0x426240D4UL)) +#define bFM3_INTREQ_DQESEL_ESEL272 *((volatile unsigned int*)(0x426240D8UL)) +#define bFM3_INTREQ_DQESEL_ESEL273 *((volatile unsigned int*)(0x426240DCUL)) +#define bFM3_INTREQ_DQESEL_ESEL300 *((volatile unsigned int*)(0x426240E0UL)) +#define bFM3_INTREQ_DQESEL_ESEL301 *((volatile unsigned int*)(0x426240E4UL)) +#define bFM3_INTREQ_DQESEL_ESEL302 *((volatile unsigned int*)(0x426240E8UL)) +#define bFM3_INTREQ_DQESEL_ESEL303 *((volatile unsigned int*)(0x426240ECUL)) +#define bFM3_INTREQ_DQESEL_ESEL310 *((volatile unsigned int*)(0x426240F0UL)) +#define bFM3_INTREQ_DQESEL_ESEL311 *((volatile unsigned int*)(0x426240F4UL)) +#define bFM3_INTREQ_DQESEL_ESEL312 *((volatile unsigned int*)(0x426240F8UL)) +#define bFM3_INTREQ_DQESEL_ESEL313 *((volatile unsigned int*)(0x426240FCUL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS10 *((volatile unsigned char*)(0x426241E0UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS11 *((volatile unsigned char*)(0x426241E4UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS12 *((volatile unsigned char*)(0x426241E8UL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS13 *((volatile unsigned char*)(0x426241ECUL)) +#define bFM3_INTREQ_ODDPKS1_ODDPKS14 *((volatile unsigned char*)(0x426241F0UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR2_P9 *((volatile unsigned int*)(0x42660124UL)) +#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR5_PC *((volatile unsigned int*)(0x426602B0UL)) +#define bFM3_GPIO_PFR5_PD *((volatile unsigned int*)(0x426602B4UL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR7_P5 *((volatile unsigned int*)(0x42660394UL)) +#define bFM3_GPIO_PFR7_P6 *((volatile unsigned int*)(0x42660398UL)) +#define bFM3_GPIO_PFR7_P7 *((volatile unsigned int*)(0x4266039CUL)) +#define bFM3_GPIO_PFR7_P8 *((volatile unsigned int*)(0x426603A0UL)) +#define bFM3_GPIO_PFR7_P9 *((volatile unsigned int*)(0x426603A4UL)) +#define bFM3_GPIO_PFR7_PA *((volatile unsigned int*)(0x426603A8UL)) +#define bFM3_GPIO_PFR7_PB *((volatile unsigned int*)(0x426603ACUL)) +#define bFM3_GPIO_PFR7_PC *((volatile unsigned int*)(0x426603B0UL)) +#define bFM3_GPIO_PFR7_PD *((volatile unsigned int*)(0x426603B4UL)) +#define bFM3_GPIO_PFR7_PE *((volatile unsigned int*)(0x426603B8UL)) +#define bFM3_GPIO_PFR7_PF *((volatile unsigned int*)(0x426603BCUL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PFR8_P2 *((volatile unsigned int*)(0x42660408UL)) +#define bFM3_GPIO_PFR8_P3 *((volatile unsigned int*)(0x4266040CUL)) +#define bFM3_GPIO_PFR9_P0 *((volatile unsigned int*)(0x42660480UL)) +#define bFM3_GPIO_PFR9_P1 *((volatile unsigned int*)(0x42660484UL)) +#define bFM3_GPIO_PFR9_P2 *((volatile unsigned int*)(0x42660488UL)) +#define bFM3_GPIO_PFR9_P3 *((volatile unsigned int*)(0x4266048CUL)) +#define bFM3_GPIO_PFR9_P4 *((volatile unsigned int*)(0x42660490UL)) +#define bFM3_GPIO_PFR9_P5 *((volatile unsigned int*)(0x42660494UL)) +#define bFM3_GPIO_PFRA_P0 *((volatile unsigned int*)(0x42660500UL)) +#define bFM3_GPIO_PFRA_P1 *((volatile unsigned int*)(0x42660504UL)) +#define bFM3_GPIO_PFRA_P2 *((volatile unsigned int*)(0x42660508UL)) +#define bFM3_GPIO_PFRA_P3 *((volatile unsigned int*)(0x4266050CUL)) +#define bFM3_GPIO_PFRA_P4 *((volatile unsigned int*)(0x42660510UL)) +#define bFM3_GPIO_PFRA_P5 *((volatile unsigned int*)(0x42660514UL)) +#define bFM3_GPIO_PFRB_P0 *((volatile unsigned int*)(0x42660580UL)) +#define bFM3_GPIO_PFRB_P1 *((volatile unsigned int*)(0x42660584UL)) +#define bFM3_GPIO_PFRB_P2 *((volatile unsigned int*)(0x42660588UL)) +#define bFM3_GPIO_PFRB_P3 *((volatile unsigned int*)(0x4266058CUL)) +#define bFM3_GPIO_PFRB_P4 *((volatile unsigned int*)(0x42660590UL)) +#define bFM3_GPIO_PFRB_P5 *((volatile unsigned int*)(0x42660594UL)) +#define bFM3_GPIO_PFRB_P6 *((volatile unsigned int*)(0x42660598UL)) +#define bFM3_GPIO_PFRB_P7 *((volatile unsigned int*)(0x4266059CUL)) +#define bFM3_GPIO_PFRC_P0 *((volatile unsigned int*)(0x42660600UL)) +#define bFM3_GPIO_PFRC_P1 *((volatile unsigned int*)(0x42660604UL)) +#define bFM3_GPIO_PFRC_P2 *((volatile unsigned int*)(0x42660608UL)) +#define bFM3_GPIO_PFRC_P3 *((volatile unsigned int*)(0x4266060CUL)) +#define bFM3_GPIO_PFRC_P4 *((volatile unsigned int*)(0x42660610UL)) +#define bFM3_GPIO_PFRC_P5 *((volatile unsigned int*)(0x42660614UL)) +#define bFM3_GPIO_PFRC_P6 *((volatile unsigned int*)(0x42660618UL)) +#define bFM3_GPIO_PFRC_P7 *((volatile unsigned int*)(0x4266061CUL)) +#define bFM3_GPIO_PFRC_P8 *((volatile unsigned int*)(0x42660620UL)) +#define bFM3_GPIO_PFRC_P9 *((volatile unsigned int*)(0x42660624UL)) +#define bFM3_GPIO_PFRC_PA *((volatile unsigned int*)(0x42660628UL)) +#define bFM3_GPIO_PFRC_PB *((volatile unsigned int*)(0x4266062CUL)) +#define bFM3_GPIO_PFRC_PC *((volatile unsigned int*)(0x42660630UL)) +#define bFM3_GPIO_PFRC_PD *((volatile unsigned int*)(0x42660634UL)) +#define bFM3_GPIO_PFRC_PE *((volatile unsigned int*)(0x42660638UL)) +#define bFM3_GPIO_PFRC_PF *((volatile unsigned int*)(0x4266063CUL)) +#define bFM3_GPIO_PFRD_P0 *((volatile unsigned int*)(0x42660680UL)) +#define bFM3_GPIO_PFRD_P1 *((volatile unsigned int*)(0x42660684UL)) +#define bFM3_GPIO_PFRD_P2 *((volatile unsigned int*)(0x42660688UL)) +#define bFM3_GPIO_PFRD_P3 *((volatile unsigned int*)(0x4266068CUL)) +#define bFM3_GPIO_PFRE_P0 *((volatile unsigned int*)(0x42660700UL)) +#define bFM3_GPIO_PFRE_P2 *((volatile unsigned int*)(0x42660708UL)) +#define bFM3_GPIO_PFRE_P3 *((volatile unsigned int*)(0x4266070CUL)) +#define bFM3_GPIO_PFRF_P0 *((volatile unsigned int*)(0x42660780UL)) +#define bFM3_GPIO_PFRF_P1 *((volatile unsigned int*)(0x42660784UL)) +#define bFM3_GPIO_PFRF_P2 *((volatile unsigned int*)(0x42660788UL)) +#define bFM3_GPIO_PFRF_P3 *((volatile unsigned int*)(0x4266078CUL)) +#define bFM3_GPIO_PFRF_P4 *((volatile unsigned int*)(0x42660790UL)) +#define bFM3_GPIO_PFRF_P5 *((volatile unsigned int*)(0x42660794UL)) +#define bFM3_GPIO_PFRF_P6 *((volatile unsigned int*)(0x42660798UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR2_P9 *((volatile unsigned int*)(0x42662124UL)) +#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) +#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) +#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) +#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) +#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) +#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR5_PC *((volatile unsigned int*)(0x426622B0UL)) +#define bFM3_GPIO_PCR5_PD *((volatile unsigned int*)(0x426622B4UL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_PCR7_P5 *((volatile unsigned int*)(0x42662394UL)) +#define bFM3_GPIO_PCR7_P6 *((volatile unsigned int*)(0x42662398UL)) +#define bFM3_GPIO_PCR7_P7 *((volatile unsigned int*)(0x4266239CUL)) +#define bFM3_GPIO_PCR7_P8 *((volatile unsigned int*)(0x426623A0UL)) +#define bFM3_GPIO_PCR7_P9 *((volatile unsigned int*)(0x426623A4UL)) +#define bFM3_GPIO_PCR7_PA *((volatile unsigned int*)(0x426623A8UL)) +#define bFM3_GPIO_PCR7_PB *((volatile unsigned int*)(0x426623ACUL)) +#define bFM3_GPIO_PCR7_PC *((volatile unsigned int*)(0x426623B0UL)) +#define bFM3_GPIO_PCR7_PD *((volatile unsigned int*)(0x426623B4UL)) +#define bFM3_GPIO_PCR7_PE *((volatile unsigned int*)(0x426623B8UL)) +#define bFM3_GPIO_PCR7_PF *((volatile unsigned int*)(0x426623BCUL)) +#define bFM3_GPIO_PCR9_P0 *((volatile unsigned int*)(0x42662480UL)) +#define bFM3_GPIO_PCR9_P1 *((volatile unsigned int*)(0x42662484UL)) +#define bFM3_GPIO_PCR9_P2 *((volatile unsigned int*)(0x42662488UL)) +#define bFM3_GPIO_PCR9_P3 *((volatile unsigned int*)(0x4266248CUL)) +#define bFM3_GPIO_PCR9_P4 *((volatile unsigned int*)(0x42662490UL)) +#define bFM3_GPIO_PCR9_P5 *((volatile unsigned int*)(0x42662494UL)) +#define bFM3_GPIO_PCRA_P0 *((volatile unsigned int*)(0x42662500UL)) +#define bFM3_GPIO_PCRA_P1 *((volatile unsigned int*)(0x42662504UL)) +#define bFM3_GPIO_PCRA_P2 *((volatile unsigned int*)(0x42662508UL)) +#define bFM3_GPIO_PCRA_P3 *((volatile unsigned int*)(0x4266250CUL)) +#define bFM3_GPIO_PCRA_P4 *((volatile unsigned int*)(0x42662510UL)) +#define bFM3_GPIO_PCRA_P5 *((volatile unsigned int*)(0x42662514UL)) +#define bFM3_GPIO_PCRB_P0 *((volatile unsigned int*)(0x42662580UL)) +#define bFM3_GPIO_PCRB_P1 *((volatile unsigned int*)(0x42662584UL)) +#define bFM3_GPIO_PCRB_P2 *((volatile unsigned int*)(0x42662588UL)) +#define bFM3_GPIO_PCRB_P3 *((volatile unsigned int*)(0x4266258CUL)) +#define bFM3_GPIO_PCRB_P4 *((volatile unsigned int*)(0x42662590UL)) +#define bFM3_GPIO_PCRB_P5 *((volatile unsigned int*)(0x42662594UL)) +#define bFM3_GPIO_PCRB_P6 *((volatile unsigned int*)(0x42662598UL)) +#define bFM3_GPIO_PCRB_P7 *((volatile unsigned int*)(0x4266259CUL)) +#define bFM3_GPIO_PCRC_P0 *((volatile unsigned int*)(0x42662600UL)) +#define bFM3_GPIO_PCRC_P1 *((volatile unsigned int*)(0x42662604UL)) +#define bFM3_GPIO_PCRC_P2 *((volatile unsigned int*)(0x42662608UL)) +#define bFM3_GPIO_PCRC_P3 *((volatile unsigned int*)(0x4266260CUL)) +#define bFM3_GPIO_PCRC_P4 *((volatile unsigned int*)(0x42662610UL)) +#define bFM3_GPIO_PCRC_P5 *((volatile unsigned int*)(0x42662614UL)) +#define bFM3_GPIO_PCRC_P6 *((volatile unsigned int*)(0x42662618UL)) +#define bFM3_GPIO_PCRC_P7 *((volatile unsigned int*)(0x4266261CUL)) +#define bFM3_GPIO_PCRC_P8 *((volatile unsigned int*)(0x42662620UL)) +#define bFM3_GPIO_PCRC_P9 *((volatile unsigned int*)(0x42662624UL)) +#define bFM3_GPIO_PCRC_PA *((volatile unsigned int*)(0x42662628UL)) +#define bFM3_GPIO_PCRC_PB *((volatile unsigned int*)(0x4266262CUL)) +#define bFM3_GPIO_PCRC_PC *((volatile unsigned int*)(0x42662630UL)) +#define bFM3_GPIO_PCRC_PD *((volatile unsigned int*)(0x42662634UL)) +#define bFM3_GPIO_PCRC_PE *((volatile unsigned int*)(0x42662638UL)) +#define bFM3_GPIO_PCRC_PF *((volatile unsigned int*)(0x4266263CUL)) +#define bFM3_GPIO_PCRD_P0 *((volatile unsigned int*)(0x42662680UL)) +#define bFM3_GPIO_PCRD_P1 *((volatile unsigned int*)(0x42662684UL)) +#define bFM3_GPIO_PCRD_P2 *((volatile unsigned int*)(0x42662688UL)) +#define bFM3_GPIO_PCRD_P3 *((volatile unsigned int*)(0x4266268CUL)) +#define bFM3_GPIO_PCRE_P2 *((volatile unsigned int*)(0x42662708UL)) +#define bFM3_GPIO_PCRE_P3 *((volatile unsigned int*)(0x4266270CUL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR2_P9 *((volatile unsigned int*)(0x42664124UL)) +#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) +#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) +#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) +#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) +#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) +#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR5_PC *((volatile unsigned int*)(0x426642B0UL)) +#define bFM3_GPIO_DDR5_PD *((volatile unsigned int*)(0x426642B4UL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR7_P5 *((volatile unsigned int*)(0x42664394UL)) +#define bFM3_GPIO_DDR7_P6 *((volatile unsigned int*)(0x42664398UL)) +#define bFM3_GPIO_DDR7_P7 *((volatile unsigned int*)(0x4266439CUL)) +#define bFM3_GPIO_DDR7_P8 *((volatile unsigned int*)(0x426643A0UL)) +#define bFM3_GPIO_DDR7_P9 *((volatile unsigned int*)(0x426643A4UL)) +#define bFM3_GPIO_DDR7_PA *((volatile unsigned int*)(0x426643A8UL)) +#define bFM3_GPIO_DDR7_PB *((volatile unsigned int*)(0x426643ACUL)) +#define bFM3_GPIO_DDR7_PC *((volatile unsigned int*)(0x426643B0UL)) +#define bFM3_GPIO_DDR7_PD *((volatile unsigned int*)(0x426643B4UL)) +#define bFM3_GPIO_DDR7_PE *((volatile unsigned int*)(0x426643B8UL)) +#define bFM3_GPIO_DDR7_PF *((volatile unsigned int*)(0x426643BCUL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_DDR8_P2 *((volatile unsigned int*)(0x42664408UL)) +#define bFM3_GPIO_DDR8_P3 *((volatile unsigned int*)(0x4266440CUL)) +#define bFM3_GPIO_DDR9_P0 *((volatile unsigned int*)(0x42664480UL)) +#define bFM3_GPIO_DDR9_P1 *((volatile unsigned int*)(0x42664484UL)) +#define bFM3_GPIO_DDR9_P2 *((volatile unsigned int*)(0x42664488UL)) +#define bFM3_GPIO_DDR9_P3 *((volatile unsigned int*)(0x4266448CUL)) +#define bFM3_GPIO_DDR9_P4 *((volatile unsigned int*)(0x42664490UL)) +#define bFM3_GPIO_DDR9_P5 *((volatile unsigned int*)(0x42664494UL)) +#define bFM3_GPIO_DDRA_P0 *((volatile unsigned int*)(0x42664500UL)) +#define bFM3_GPIO_DDRA_P1 *((volatile unsigned int*)(0x42664504UL)) +#define bFM3_GPIO_DDRA_P2 *((volatile unsigned int*)(0x42664508UL)) +#define bFM3_GPIO_DDRA_P3 *((volatile unsigned int*)(0x4266450CUL)) +#define bFM3_GPIO_DDRA_P4 *((volatile unsigned int*)(0x42664510UL)) +#define bFM3_GPIO_DDRA_P5 *((volatile unsigned int*)(0x42664514UL)) +#define bFM3_GPIO_DDRB_P0 *((volatile unsigned int*)(0x42664580UL)) +#define bFM3_GPIO_DDRB_P1 *((volatile unsigned int*)(0x42664584UL)) +#define bFM3_GPIO_DDRB_P2 *((volatile unsigned int*)(0x42664588UL)) +#define bFM3_GPIO_DDRB_P3 *((volatile unsigned int*)(0x4266458CUL)) +#define bFM3_GPIO_DDRB_P4 *((volatile unsigned int*)(0x42664590UL)) +#define bFM3_GPIO_DDRB_P5 *((volatile unsigned int*)(0x42664594UL)) +#define bFM3_GPIO_DDRB_P6 *((volatile unsigned int*)(0x42664598UL)) +#define bFM3_GPIO_DDRB_P7 *((volatile unsigned int*)(0x4266459CUL)) +#define bFM3_GPIO_DDRC_P0 *((volatile unsigned int*)(0x42664600UL)) +#define bFM3_GPIO_DDRC_P1 *((volatile unsigned int*)(0x42664604UL)) +#define bFM3_GPIO_DDRC_P2 *((volatile unsigned int*)(0x42664608UL)) +#define bFM3_GPIO_DDRC_P3 *((volatile unsigned int*)(0x4266460CUL)) +#define bFM3_GPIO_DDRC_P4 *((volatile unsigned int*)(0x42664610UL)) +#define bFM3_GPIO_DDRC_P5 *((volatile unsigned int*)(0x42664614UL)) +#define bFM3_GPIO_DDRC_P6 *((volatile unsigned int*)(0x42664618UL)) +#define bFM3_GPIO_DDRC_P7 *((volatile unsigned int*)(0x4266461CUL)) +#define bFM3_GPIO_DDRC_P8 *((volatile unsigned int*)(0x42664620UL)) +#define bFM3_GPIO_DDRC_P9 *((volatile unsigned int*)(0x42664624UL)) +#define bFM3_GPIO_DDRC_PA *((volatile unsigned int*)(0x42664628UL)) +#define bFM3_GPIO_DDRC_PB *((volatile unsigned int*)(0x4266462CUL)) +#define bFM3_GPIO_DDRC_PC *((volatile unsigned int*)(0x42664630UL)) +#define bFM3_GPIO_DDRC_PD *((volatile unsigned int*)(0x42664634UL)) +#define bFM3_GPIO_DDRC_PE *((volatile unsigned int*)(0x42664638UL)) +#define bFM3_GPIO_DDRC_PF *((volatile unsigned int*)(0x4266463CUL)) +#define bFM3_GPIO_DDRD_P0 *((volatile unsigned int*)(0x42664680UL)) +#define bFM3_GPIO_DDRD_P1 *((volatile unsigned int*)(0x42664684UL)) +#define bFM3_GPIO_DDRD_P2 *((volatile unsigned int*)(0x42664688UL)) +#define bFM3_GPIO_DDRD_P3 *((volatile unsigned int*)(0x4266468CUL)) +#define bFM3_GPIO_DDRE_P0 *((volatile unsigned int*)(0x42664700UL)) +#define bFM3_GPIO_DDRE_P2 *((volatile unsigned int*)(0x42664708UL)) +#define bFM3_GPIO_DDRE_P3 *((volatile unsigned int*)(0x4266470CUL)) +#define bFM3_GPIO_DDRF_P0 *((volatile unsigned int*)(0x42664780UL)) +#define bFM3_GPIO_DDRF_P1 *((volatile unsigned int*)(0x42664784UL)) +#define bFM3_GPIO_DDRF_P2 *((volatile unsigned int*)(0x42664788UL)) +#define bFM3_GPIO_DDRF_P3 *((volatile unsigned int*)(0x4266478CUL)) +#define bFM3_GPIO_DDRF_P4 *((volatile unsigned int*)(0x42664790UL)) +#define bFM3_GPIO_DDRF_P5 *((volatile unsigned int*)(0x42664794UL)) +#define bFM3_GPIO_DDRF_P6 *((volatile unsigned int*)(0x42664798UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR2_P9 *((volatile unsigned int*)(0x42666124UL)) +#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) +#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) +#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) +#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) +#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) +#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR5_PC *((volatile unsigned int*)(0x426662B0UL)) +#define bFM3_GPIO_PDIR5_PD *((volatile unsigned int*)(0x426662B4UL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR7_P5 *((volatile unsigned int*)(0x42666394UL)) +#define bFM3_GPIO_PDIR7_P6 *((volatile unsigned int*)(0x42666398UL)) +#define bFM3_GPIO_PDIR7_P7 *((volatile unsigned int*)(0x4266639CUL)) +#define bFM3_GPIO_PDIR7_P8 *((volatile unsigned int*)(0x426663A0UL)) +#define bFM3_GPIO_PDIR7_P9 *((volatile unsigned int*)(0x426663A4UL)) +#define bFM3_GPIO_PDIR7_PA *((volatile unsigned int*)(0x426663A8UL)) +#define bFM3_GPIO_PDIR7_PB *((volatile unsigned int*)(0x426663ACUL)) +#define bFM3_GPIO_PDIR7_PC *((volatile unsigned int*)(0x426663B0UL)) +#define bFM3_GPIO_PDIR7_PD *((volatile unsigned int*)(0x426663B4UL)) +#define bFM3_GPIO_PDIR7_PE *((volatile unsigned int*)(0x426663B8UL)) +#define bFM3_GPIO_PDIR7_PF *((volatile unsigned int*)(0x426663BCUL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDIR8_P2 *((volatile unsigned int*)(0x42666408UL)) +#define bFM3_GPIO_PDIR8_P3 *((volatile unsigned int*)(0x4266640CUL)) +#define bFM3_GPIO_PDIR9_P0 *((volatile unsigned int*)(0x42666480UL)) +#define bFM3_GPIO_PDIR9_P1 *((volatile unsigned int*)(0x42666484UL)) +#define bFM3_GPIO_PDIR9_P2 *((volatile unsigned int*)(0x42666488UL)) +#define bFM3_GPIO_PDIR9_P3 *((volatile unsigned int*)(0x4266648CUL)) +#define bFM3_GPIO_PDIR9_P4 *((volatile unsigned int*)(0x42666490UL)) +#define bFM3_GPIO_PDIR9_P5 *((volatile unsigned int*)(0x42666494UL)) +#define bFM3_GPIO_PDIRA_P0 *((volatile unsigned int*)(0x42666500UL)) +#define bFM3_GPIO_PDIRA_P1 *((volatile unsigned int*)(0x42666504UL)) +#define bFM3_GPIO_PDIRA_P2 *((volatile unsigned int*)(0x42666508UL)) +#define bFM3_GPIO_PDIRA_P3 *((volatile unsigned int*)(0x4266650CUL)) +#define bFM3_GPIO_PDIRA_P4 *((volatile unsigned int*)(0x42666510UL)) +#define bFM3_GPIO_PDIRA_P5 *((volatile unsigned int*)(0x42666514UL)) +#define bFM3_GPIO_PDIRB_P0 *((volatile unsigned int*)(0x42666580UL)) +#define bFM3_GPIO_PDIRB_P1 *((volatile unsigned int*)(0x42666584UL)) +#define bFM3_GPIO_PDIRB_P2 *((volatile unsigned int*)(0x42666588UL)) +#define bFM3_GPIO_PDIRB_P3 *((volatile unsigned int*)(0x4266658CUL)) +#define bFM3_GPIO_PDIRB_P4 *((volatile unsigned int*)(0x42666590UL)) +#define bFM3_GPIO_PDIRB_P5 *((volatile unsigned int*)(0x42666594UL)) +#define bFM3_GPIO_PDIRB_P6 *((volatile unsigned int*)(0x42666598UL)) +#define bFM3_GPIO_PDIRB_P7 *((volatile unsigned int*)(0x4266659CUL)) +#define bFM3_GPIO_PDIRC_P0 *((volatile unsigned int*)(0x42666600UL)) +#define bFM3_GPIO_PDIRC_P1 *((volatile unsigned int*)(0x42666604UL)) +#define bFM3_GPIO_PDIRC_P2 *((volatile unsigned int*)(0x42666608UL)) +#define bFM3_GPIO_PDIRC_P3 *((volatile unsigned int*)(0x4266660CUL)) +#define bFM3_GPIO_PDIRC_P4 *((volatile unsigned int*)(0x42666610UL)) +#define bFM3_GPIO_PDIRC_P5 *((volatile unsigned int*)(0x42666614UL)) +#define bFM3_GPIO_PDIRC_P6 *((volatile unsigned int*)(0x42666618UL)) +#define bFM3_GPIO_PDIRC_P7 *((volatile unsigned int*)(0x4266661CUL)) +#define bFM3_GPIO_PDIRC_P8 *((volatile unsigned int*)(0x42666620UL)) +#define bFM3_GPIO_PDIRC_P9 *((volatile unsigned int*)(0x42666624UL)) +#define bFM3_GPIO_PDIRC_PA *((volatile unsigned int*)(0x42666628UL)) +#define bFM3_GPIO_PDIRC_PB *((volatile unsigned int*)(0x4266662CUL)) +#define bFM3_GPIO_PDIRC_PC *((volatile unsigned int*)(0x42666630UL)) +#define bFM3_GPIO_PDIRC_PD *((volatile unsigned int*)(0x42666634UL)) +#define bFM3_GPIO_PDIRC_PE *((volatile unsigned int*)(0x42666638UL)) +#define bFM3_GPIO_PDIRC_PF *((volatile unsigned int*)(0x4266663CUL)) +#define bFM3_GPIO_PDIRD_P0 *((volatile unsigned int*)(0x42666680UL)) +#define bFM3_GPIO_PDIRD_P1 *((volatile unsigned int*)(0x42666684UL)) +#define bFM3_GPIO_PDIRD_P2 *((volatile unsigned int*)(0x42666688UL)) +#define bFM3_GPIO_PDIRD_P3 *((volatile unsigned int*)(0x4266668CUL)) +#define bFM3_GPIO_PDIRE_P0 *((volatile unsigned int*)(0x42666700UL)) +#define bFM3_GPIO_PDIRE_P2 *((volatile unsigned int*)(0x42666708UL)) +#define bFM3_GPIO_PDIRE_P3 *((volatile unsigned int*)(0x4266670CUL)) +#define bFM3_GPIO_PDIRF_P0 *((volatile unsigned int*)(0x42666780UL)) +#define bFM3_GPIO_PDIRF_P1 *((volatile unsigned int*)(0x42666784UL)) +#define bFM3_GPIO_PDIRF_P2 *((volatile unsigned int*)(0x42666788UL)) +#define bFM3_GPIO_PDIRF_P3 *((volatile unsigned int*)(0x4266678CUL)) +#define bFM3_GPIO_PDIRF_P4 *((volatile unsigned int*)(0x42666790UL)) +#define bFM3_GPIO_PDIRF_P5 *((volatile unsigned int*)(0x42666794UL)) +#define bFM3_GPIO_PDIRF_P6 *((volatile unsigned int*)(0x42666798UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR2_P9 *((volatile unsigned int*)(0x42668124UL)) +#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) +#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) +#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) +#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) +#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) +#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR5_PC *((volatile unsigned int*)(0x426682B0UL)) +#define bFM3_GPIO_PDOR5_PD *((volatile unsigned int*)(0x426682B4UL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR7_P5 *((volatile unsigned int*)(0x42668394UL)) +#define bFM3_GPIO_PDOR7_P6 *((volatile unsigned int*)(0x42668398UL)) +#define bFM3_GPIO_PDOR7_P7 *((volatile unsigned int*)(0x4266839CUL)) +#define bFM3_GPIO_PDOR7_P8 *((volatile unsigned int*)(0x426683A0UL)) +#define bFM3_GPIO_PDOR7_P9 *((volatile unsigned int*)(0x426683A4UL)) +#define bFM3_GPIO_PDOR7_PA *((volatile unsigned int*)(0x426683A8UL)) +#define bFM3_GPIO_PDOR7_PB *((volatile unsigned int*)(0x426683ACUL)) +#define bFM3_GPIO_PDOR7_PC *((volatile unsigned int*)(0x426683B0UL)) +#define bFM3_GPIO_PDOR7_PD *((volatile unsigned int*)(0x426683B4UL)) +#define bFM3_GPIO_PDOR7_PE *((volatile unsigned int*)(0x426683B8UL)) +#define bFM3_GPIO_PDOR7_PF *((volatile unsigned int*)(0x426683BCUL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_PDOR8_P2 *((volatile unsigned int*)(0x42668408UL)) +#define bFM3_GPIO_PDOR8_P3 *((volatile unsigned int*)(0x4266840CUL)) +#define bFM3_GPIO_PDOR9_P0 *((volatile unsigned int*)(0x42668480UL)) +#define bFM3_GPIO_PDOR9_P1 *((volatile unsigned int*)(0x42668484UL)) +#define bFM3_GPIO_PDOR9_P2 *((volatile unsigned int*)(0x42668488UL)) +#define bFM3_GPIO_PDOR9_P3 *((volatile unsigned int*)(0x4266848CUL)) +#define bFM3_GPIO_PDOR9_P4 *((volatile unsigned int*)(0x42668490UL)) +#define bFM3_GPIO_PDOR9_P5 *((volatile unsigned int*)(0x42668494UL)) +#define bFM3_GPIO_PDORA_P0 *((volatile unsigned int*)(0x42668500UL)) +#define bFM3_GPIO_PDORA_P1 *((volatile unsigned int*)(0x42668504UL)) +#define bFM3_GPIO_PDORA_P2 *((volatile unsigned int*)(0x42668508UL)) +#define bFM3_GPIO_PDORA_P3 *((volatile unsigned int*)(0x4266850CUL)) +#define bFM3_GPIO_PDORA_P4 *((volatile unsigned int*)(0x42668510UL)) +#define bFM3_GPIO_PDORA_P5 *((volatile unsigned int*)(0x42668514UL)) +#define bFM3_GPIO_PDORB_P0 *((volatile unsigned int*)(0x42668580UL)) +#define bFM3_GPIO_PDORB_P1 *((volatile unsigned int*)(0x42668584UL)) +#define bFM3_GPIO_PDORB_P2 *((volatile unsigned int*)(0x42668588UL)) +#define bFM3_GPIO_PDORB_P3 *((volatile unsigned int*)(0x4266858CUL)) +#define bFM3_GPIO_PDORB_P4 *((volatile unsigned int*)(0x42668590UL)) +#define bFM3_GPIO_PDORB_P5 *((volatile unsigned int*)(0x42668594UL)) +#define bFM3_GPIO_PDORB_P6 *((volatile unsigned int*)(0x42668598UL)) +#define bFM3_GPIO_PDORB_P7 *((volatile unsigned int*)(0x4266859CUL)) +#define bFM3_GPIO_PDORC_P0 *((volatile unsigned int*)(0x42668600UL)) +#define bFM3_GPIO_PDORC_P1 *((volatile unsigned int*)(0x42668604UL)) +#define bFM3_GPIO_PDORC_P2 *((volatile unsigned int*)(0x42668608UL)) +#define bFM3_GPIO_PDORC_P3 *((volatile unsigned int*)(0x4266860CUL)) +#define bFM3_GPIO_PDORC_P4 *((volatile unsigned int*)(0x42668610UL)) +#define bFM3_GPIO_PDORC_P5 *((volatile unsigned int*)(0x42668614UL)) +#define bFM3_GPIO_PDORC_P6 *((volatile unsigned int*)(0x42668618UL)) +#define bFM3_GPIO_PDORC_P7 *((volatile unsigned int*)(0x4266861CUL)) +#define bFM3_GPIO_PDORC_P8 *((volatile unsigned int*)(0x42668620UL)) +#define bFM3_GPIO_PDORC_P9 *((volatile unsigned int*)(0x42668624UL)) +#define bFM3_GPIO_PDORC_PA *((volatile unsigned int*)(0x42668628UL)) +#define bFM3_GPIO_PDORC_PB *((volatile unsigned int*)(0x4266862CUL)) +#define bFM3_GPIO_PDORC_PC *((volatile unsigned int*)(0x42668630UL)) +#define bFM3_GPIO_PDORC_PD *((volatile unsigned int*)(0x42668634UL)) +#define bFM3_GPIO_PDORC_PE *((volatile unsigned int*)(0x42668638UL)) +#define bFM3_GPIO_PDORC_PF *((volatile unsigned int*)(0x4266863CUL)) +#define bFM3_GPIO_PDORD_P0 *((volatile unsigned int*)(0x42668680UL)) +#define bFM3_GPIO_PDORD_P1 *((volatile unsigned int*)(0x42668684UL)) +#define bFM3_GPIO_PDORD_P2 *((volatile unsigned int*)(0x42668688UL)) +#define bFM3_GPIO_PDORD_P3 *((volatile unsigned int*)(0x4266868CUL)) +#define bFM3_GPIO_PDORE_P0 *((volatile unsigned int*)(0x42668700UL)) +#define bFM3_GPIO_PDORE_P2 *((volatile unsigned int*)(0x42668708UL)) +#define bFM3_GPIO_PDORE_P3 *((volatile unsigned int*)(0x4266870CUL)) +#define bFM3_GPIO_PDORF_P0 *((volatile unsigned int*)(0x42668780UL)) +#define bFM3_GPIO_PDORF_P1 *((volatile unsigned int*)(0x42668784UL)) +#define bFM3_GPIO_PDORF_P2 *((volatile unsigned int*)(0x42668788UL)) +#define bFM3_GPIO_PDORF_P3 *((volatile unsigned int*)(0x4266878CUL)) +#define bFM3_GPIO_PDORF_P4 *((volatile unsigned int*)(0x42668790UL)) +#define bFM3_GPIO_PDORF_P5 *((volatile unsigned int*)(0x42668794UL)) +#define bFM3_GPIO_PDORF_P6 *((volatile unsigned int*)(0x42668798UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_AN10 *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_AN11 *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_AN12 *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AN13 *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_AN14 *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_AN15 *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_ADE_AN16 *((volatile unsigned int*)(0x4266A040UL)) +#define bFM3_GPIO_ADE_AN17 *((volatile unsigned int*)(0x4266A044UL)) +#define bFM3_GPIO_ADE_AN18 *((volatile unsigned int*)(0x4266A048UL)) +#define bFM3_GPIO_ADE_AN19 *((volatile unsigned int*)(0x4266A04CUL)) +#define bFM3_GPIO_ADE_AN20 *((volatile unsigned int*)(0x4266A050UL)) +#define bFM3_GPIO_ADE_AN21 *((volatile unsigned int*)(0x4266A054UL)) +#define bFM3_GPIO_ADE_AN22 *((volatile unsigned int*)(0x4266A058UL)) +#define bFM3_GPIO_ADE_AN23 *((volatile unsigned int*)(0x4266A05CUL)) +#define bFM3_GPIO_ADE_AN24 *((volatile unsigned int*)(0x4266A060UL)) +#define bFM3_GPIO_ADE_AN25 *((volatile unsigned int*)(0x4266A064UL)) +#define bFM3_GPIO_ADE_AN26 *((volatile unsigned int*)(0x4266A068UL)) +#define bFM3_GPIO_ADE_AN27 *((volatile unsigned int*)(0x4266A06CUL)) +#define bFM3_GPIO_ADE_AN28 *((volatile unsigned int*)(0x4266A070UL)) +#define bFM3_GPIO_ADE_AN29 *((volatile unsigned int*)(0x4266A074UL)) +#define bFM3_GPIO_ADE_AN30 *((volatile unsigned int*)(0x4266A078UL)) +#define bFM3_GPIO_ADE_AN31 *((volatile unsigned int*)(0x4266A07CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_MAINXC *((volatile unsigned int*)(0x4266B008UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x4266B014UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x4266C008UL)) +#define bFM3_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x4266C018UL)) +#define bFM3_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x4266C01CUL)) +#define bFM3_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x4266C034UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x4266C180UL)) +#define bFM3_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x4266C184UL)) +#define bFM3_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x4266C188UL)) +#define bFM3_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x4266C18CUL)) +#define bFM3_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x4266C190UL)) +#define bFM3_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x4266C194UL)) +#define bFM3_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x4266C198UL)) +#define bFM3_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x4266C19CUL)) +#define bFM3_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x4266C1A0UL)) +#define bFM3_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x4266C1A4UL)) +#define bFM3_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x4266C1A8UL)) +#define bFM3_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x4266C1ACUL)) +#define bFM3_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x4266C1B0UL)) +#define bFM3_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x4266C1C0UL)) +#define bFM3_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x4266C1C4UL)) +#define bFM3_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x4266C1C8UL)) +#define bFM3_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x4266C1CCUL)) +#define bFM3_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x4266C1D0UL)) +#define bFM3_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x4266C1D4UL)) +#define bFM3_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x4266C1D8UL)) +#define bFM3_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x4266C1DCUL)) +#define bFM3_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x4266C1E0UL)) +#define bFM3_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x4266C1E4UL)) +#define bFM3_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x4266C1E8UL)) +#define bFM3_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x4266C1ECUL)) +#define bFM3_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x4266C1F0UL)) +#define bFM3_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x4266C1F4UL)) +#define bFM3_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x4266C1F8UL)) +#define bFM3_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x4266C1FCUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) +#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) +#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) +#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) +#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) +#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) +#define bFM3_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x4266C580UL)) +#define bFM3_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x4266C584UL)) +#define bFM3_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x4266C588UL)) +#define bFM3_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x4266C58CUL)) +#define bFM3_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x4266C590UL)) +#define bFM3_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x4266C594UL)) +#define bFM3_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x4266C598UL)) +#define bFM3_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x4266C59CUL)) +#define bFM3_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x4266C5A0UL)) +#define bFM3_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x4266C5A4UL)) +#define bFM3_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x4266C5A8UL)) +#define bFM3_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x4266C5ACUL)) +#define bFM3_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x4266C5B0UL)) +#define bFM3_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x4266C5B4UL)) +#define bFM3_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x4266C5B8UL)) +#define bFM3_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x4266C5BCUL)) +#define bFM3_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x4266C5C0UL)) +#define bFM3_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x4266C5C4UL)) +#define bFM3_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x4266C5C8UL)) +#define bFM3_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x4266C5CCUL)) +#define bFM3_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x4266C5D0UL)) +#define bFM3_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x4266C5D4UL)) +#define bFM3_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x4266C5D8UL)) +#define bFM3_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x4266C5DCUL)) +#define bFM3_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x4266C5E0UL)) +#define bFM3_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x4266C5E4UL)) +#define bFM3_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x4266C608UL)) +#define bFM3_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x4266C60CUL)) +#define bFM3_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x4266C610UL)) +#define bFM3_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x4266C614UL)) +#define bFM3_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x4266C620UL)) +#define bFM3_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x4266C624UL)) +#define bFM3_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x4266C628UL)) +#define bFM3_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x4266C62CUL)) +#define bFM3_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x4266C630UL)) +#define bFM3_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x4266C634UL)) +#define bFM3_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x4266C648UL)) +#define bFM3_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x4266C64CUL)) +#define bFM3_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x4266C650UL)) +#define bFM3_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x4266C654UL)) +#define bFM3_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x4266C660UL)) +#define bFM3_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x4266C664UL)) +#define bFM3_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x4266C668UL)) +#define bFM3_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x4266C66CUL)) +#define bFM3_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x4266C670UL)) +#define bFM3_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x4266C674UL)) +#define bFM3_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x4266C688UL)) +#define bFM3_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x4266C68CUL)) +#define bFM3_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x4266C690UL)) +#define bFM3_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x4266C694UL)) +#define bFM3_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x4266C6A0UL)) +#define bFM3_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x4266C6A4UL)) +#define bFM3_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x4266C6A8UL)) +#define bFM3_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x4266C6ACUL)) +#define bFM3_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x4266C6B0UL)) +#define bFM3_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x4266C6B4UL)) +#define bFM3_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x4266C6C8UL)) +#define bFM3_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x4266C6CCUL)) +#define bFM3_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x4266C6D0UL)) +#define bFM3_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x4266C6D4UL)) +#define bFM3_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x4266C6E0UL)) +#define bFM3_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x4266C6E4UL)) +#define bFM3_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x4266C6E8UL)) +#define bFM3_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x4266C6ECUL)) +#define bFM3_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x4266C6F0UL)) +#define bFM3_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x4266C6F4UL)) +#define bFM3_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x4266C700UL)) +#define bFM3_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x4266C704UL)) +#define bFM3_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x4266C708UL)) +#define bFM3_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x4266C70CUL)) +#define bFM3_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x4266C710UL)) +#define bFM3_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x4266C714UL)) +#define bFM3_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x4266C748UL)) +#define bFM3_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x4266C74CUL)) +#define bFM3_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x4266C750UL)) +#define bFM3_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x4266C754UL)) +#define bFM3_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x4266C758UL)) +#define bFM3_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x4266C75CUL)) +#define bFM3_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x4266C760UL)) +#define bFM3_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x4266C764UL)) +#define bFM3_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x4266C768UL)) +#define bFM3_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x4266C76CUL)) +#define bFM3_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x4266C770UL)) +#define bFM3_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x4266C774UL)) +#define bFM3_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x4266C780UL)) +#define bFM3_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x4266C784UL)) +#define bFM3_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x4266C788UL)) +#define bFM3_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x4266C78CUL)) +#define bFM3_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x4266C790UL)) +#define bFM3_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x4266C794UL)) +#define bFM3_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x4266C798UL)) +#define bFM3_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x4266C79CUL)) +#define bFM3_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x4266C7A0UL)) +#define bFM3_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x4266C7A4UL)) +#define bFM3_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x4266C7A8UL)) +#define bFM3_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x4266C7ACUL)) +#define bFM3_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x4266C7B0UL)) +#define bFM3_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x4266C7B4UL)) +#define bFM3_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x4266C7B8UL)) +#define bFM3_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x4266C7BCUL)) +#define bFM3_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x4266C7C0UL)) +#define bFM3_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x4266C7C4UL)) +#define bFM3_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x4266C7C8UL)) +#define bFM3_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x4266C7CCUL)) +#define bFM3_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x4266C7D0UL)) +#define bFM3_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x4266C7D4UL)) +#define bFM3_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x4266C7D8UL)) +#define bFM3_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x4266C7DCUL)) +#define bFM3_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x4266C7E0UL)) +#define bFM3_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x4266C7E4UL)) +#define bFM3_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x4266C7E8UL)) +#define bFM3_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x4266C7ECUL)) +#define bFM3_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x4266C7F0UL)) +#define bFM3_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x4266C7F4UL)) +#define bFM3_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x4266C7F8UL)) +#define bFM3_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x4266C7FCUL)) +#define bFM3_GPIO_PZR0_P0 *((volatile unsigned int*)(0x4266E000UL)) +#define bFM3_GPIO_PZR0_P1 *((volatile unsigned int*)(0x4266E004UL)) +#define bFM3_GPIO_PZR0_P2 *((volatile unsigned int*)(0x4266E008UL)) +#define bFM3_GPIO_PZR0_P3 *((volatile unsigned int*)(0x4266E00CUL)) +#define bFM3_GPIO_PZR0_P4 *((volatile unsigned int*)(0x4266E010UL)) +#define bFM3_GPIO_PZR0_P5 *((volatile unsigned int*)(0x4266E014UL)) +#define bFM3_GPIO_PZR0_P6 *((volatile unsigned int*)(0x4266E018UL)) +#define bFM3_GPIO_PZR0_P7 *((volatile unsigned int*)(0x4266E01CUL)) +#define bFM3_GPIO_PZR0_P8 *((volatile unsigned int*)(0x4266E020UL)) +#define bFM3_GPIO_PZR0_P9 *((volatile unsigned int*)(0x4266E024UL)) +#define bFM3_GPIO_PZR1_P0 *((volatile unsigned int*)(0x4266E080UL)) +#define bFM3_GPIO_PZR1_P1 *((volatile unsigned int*)(0x4266E084UL)) +#define bFM3_GPIO_PZR1_P2 *((volatile unsigned int*)(0x4266E088UL)) +#define bFM3_GPIO_PZR1_P3 *((volatile unsigned int*)(0x4266E08CUL)) +#define bFM3_GPIO_PZR1_P4 *((volatile unsigned int*)(0x4266E090UL)) +#define bFM3_GPIO_PZR1_P5 *((volatile unsigned int*)(0x4266E094UL)) +#define bFM3_GPIO_PZR1_P6 *((volatile unsigned int*)(0x4266E098UL)) +#define bFM3_GPIO_PZR1_P7 *((volatile unsigned int*)(0x4266E09CUL)) +#define bFM3_GPIO_PZR1_P8 *((volatile unsigned int*)(0x4266E0A0UL)) +#define bFM3_GPIO_PZR1_P9 *((volatile unsigned int*)(0x4266E0A4UL)) +#define bFM3_GPIO_PZR1_PA *((volatile unsigned int*)(0x4266E0A8UL)) +#define bFM3_GPIO_PZR1_PB *((volatile unsigned int*)(0x4266E0ACUL)) +#define bFM3_GPIO_PZR1_PC *((volatile unsigned int*)(0x4266E0B0UL)) +#define bFM3_GPIO_PZR1_PD *((volatile unsigned int*)(0x4266E0B4UL)) +#define bFM3_GPIO_PZR1_PE *((volatile unsigned int*)(0x4266E0B8UL)) +#define bFM3_GPIO_PZR1_PF *((volatile unsigned int*)(0x4266E0BCUL)) +#define bFM3_GPIO_PZR2_P0 *((volatile unsigned int*)(0x4266E100UL)) +#define bFM3_GPIO_PZR2_P1 *((volatile unsigned int*)(0x4266E104UL)) +#define bFM3_GPIO_PZR2_P2 *((volatile unsigned int*)(0x4266E108UL)) +#define bFM3_GPIO_PZR2_P3 *((volatile unsigned int*)(0x4266E10CUL)) +#define bFM3_GPIO_PZR2_P4 *((volatile unsigned int*)(0x4266E110UL)) +#define bFM3_GPIO_PZR2_P5 *((volatile unsigned int*)(0x4266E114UL)) +#define bFM3_GPIO_PZR2_P6 *((volatile unsigned int*)(0x4266E118UL)) +#define bFM3_GPIO_PZR2_P7 *((volatile unsigned int*)(0x4266E11CUL)) +#define bFM3_GPIO_PZR2_P8 *((volatile unsigned int*)(0x4266E120UL)) +#define bFM3_GPIO_PZR2_P9 *((volatile unsigned int*)(0x4266E124UL)) +#define bFM3_GPIO_PZR3_P0 *((volatile unsigned int*)(0x4266E180UL)) +#define bFM3_GPIO_PZR3_P1 *((volatile unsigned int*)(0x4266E184UL)) +#define bFM3_GPIO_PZR3_P2 *((volatile unsigned int*)(0x4266E188UL)) +#define bFM3_GPIO_PZR3_P3 *((volatile unsigned int*)(0x4266E18CUL)) +#define bFM3_GPIO_PZR3_P4 *((volatile unsigned int*)(0x4266E190UL)) +#define bFM3_GPIO_PZR3_P5 *((volatile unsigned int*)(0x4266E194UL)) +#define bFM3_GPIO_PZR3_P6 *((volatile unsigned int*)(0x4266E198UL)) +#define bFM3_GPIO_PZR3_P7 *((volatile unsigned int*)(0x4266E19CUL)) +#define bFM3_GPIO_PZR3_P8 *((volatile unsigned int*)(0x4266E1A0UL)) +#define bFM3_GPIO_PZR3_P9 *((volatile unsigned int*)(0x4266E1A4UL)) +#define bFM3_GPIO_PZR3_PA *((volatile unsigned int*)(0x4266E1A8UL)) +#define bFM3_GPIO_PZR3_PB *((volatile unsigned int*)(0x4266E1ACUL)) +#define bFM3_GPIO_PZR3_PC *((volatile unsigned int*)(0x4266E1B0UL)) +#define bFM3_GPIO_PZR3_PD *((volatile unsigned int*)(0x4266E1B4UL)) +#define bFM3_GPIO_PZR3_PE *((volatile unsigned int*)(0x4266E1B8UL)) +#define bFM3_GPIO_PZR3_PF *((volatile unsigned int*)(0x4266E1BCUL)) +#define bFM3_GPIO_PZR4_P0 *((volatile unsigned int*)(0x4266E200UL)) +#define bFM3_GPIO_PZR4_P1 *((volatile unsigned int*)(0x4266E204UL)) +#define bFM3_GPIO_PZR4_P2 *((volatile unsigned int*)(0x4266E208UL)) +#define bFM3_GPIO_PZR4_P3 *((volatile unsigned int*)(0x4266E20CUL)) +#define bFM3_GPIO_PZR4_P4 *((volatile unsigned int*)(0x4266E210UL)) +#define bFM3_GPIO_PZR4_P5 *((volatile unsigned int*)(0x4266E214UL)) +#define bFM3_GPIO_PZR4_P6 *((volatile unsigned int*)(0x4266E218UL)) +#define bFM3_GPIO_PZR4_P7 *((volatile unsigned int*)(0x4266E21CUL)) +#define bFM3_GPIO_PZR4_P8 *((volatile unsigned int*)(0x4266E220UL)) +#define bFM3_GPIO_PZR4_P9 *((volatile unsigned int*)(0x4266E224UL)) +#define bFM3_GPIO_PZR4_PA *((volatile unsigned int*)(0x4266E228UL)) +#define bFM3_GPIO_PZR4_PB *((volatile unsigned int*)(0x4266E22CUL)) +#define bFM3_GPIO_PZR4_PC *((volatile unsigned int*)(0x4266E230UL)) +#define bFM3_GPIO_PZR4_PD *((volatile unsigned int*)(0x4266E234UL)) +#define bFM3_GPIO_PZR4_PE *((volatile unsigned int*)(0x4266E238UL)) +#define bFM3_GPIO_PZR5_P0 *((volatile unsigned int*)(0x4266E280UL)) +#define bFM3_GPIO_PZR5_P1 *((volatile unsigned int*)(0x4266E284UL)) +#define bFM3_GPIO_PZR5_P2 *((volatile unsigned int*)(0x4266E288UL)) +#define bFM3_GPIO_PZR5_P3 *((volatile unsigned int*)(0x4266E28CUL)) +#define bFM3_GPIO_PZR5_P4 *((volatile unsigned int*)(0x4266E290UL)) +#define bFM3_GPIO_PZR5_P5 *((volatile unsigned int*)(0x4266E294UL)) +#define bFM3_GPIO_PZR5_P6 *((volatile unsigned int*)(0x4266E298UL)) +#define bFM3_GPIO_PZR5_P7 *((volatile unsigned int*)(0x4266E29CUL)) +#define bFM3_GPIO_PZR5_P8 *((volatile unsigned int*)(0x4266E2A0UL)) +#define bFM3_GPIO_PZR5_P9 *((volatile unsigned int*)(0x4266E2A4UL)) +#define bFM3_GPIO_PZR5_PA *((volatile unsigned int*)(0x4266E2A8UL)) +#define bFM3_GPIO_PZR5_PB *((volatile unsigned int*)(0x4266E2ACUL)) +#define bFM3_GPIO_PZR5_PC *((volatile unsigned int*)(0x4266E2B0UL)) +#define bFM3_GPIO_PZR5_PD *((volatile unsigned int*)(0x4266E2B4UL)) +#define bFM3_GPIO_PZR6_P0 *((volatile unsigned int*)(0x4266E300UL)) +#define bFM3_GPIO_PZR6_P1 *((volatile unsigned int*)(0x4266E304UL)) +#define bFM3_GPIO_PZR6_P2 *((volatile unsigned int*)(0x4266E308UL)) +#define bFM3_GPIO_PZR7_P0 *((volatile unsigned int*)(0x4266E380UL)) +#define bFM3_GPIO_PZR7_P1 *((volatile unsigned int*)(0x4266E384UL)) +#define bFM3_GPIO_PZR7_P2 *((volatile unsigned int*)(0x4266E388UL)) +#define bFM3_GPIO_PZR7_P3 *((volatile unsigned int*)(0x4266E38CUL)) +#define bFM3_GPIO_PZR7_P4 *((volatile unsigned int*)(0x4266E390UL)) +#define bFM3_GPIO_PZR7_P5 *((volatile unsigned int*)(0x4266E394UL)) +#define bFM3_GPIO_PZR7_P6 *((volatile unsigned int*)(0x4266E398UL)) +#define bFM3_GPIO_PZR7_P7 *((volatile unsigned int*)(0x4266E39CUL)) +#define bFM3_GPIO_PZR7_P8 *((volatile unsigned int*)(0x4266E3A0UL)) +#define bFM3_GPIO_PZR7_P9 *((volatile unsigned int*)(0x4266E3A4UL)) +#define bFM3_GPIO_PZR7_PA *((volatile unsigned int*)(0x4266E3A8UL)) +#define bFM3_GPIO_PZR7_PB *((volatile unsigned int*)(0x4266E3ACUL)) +#define bFM3_GPIO_PZR7_PC *((volatile unsigned int*)(0x4266E3B0UL)) +#define bFM3_GPIO_PZR7_PD *((volatile unsigned int*)(0x4266E3B4UL)) +#define bFM3_GPIO_PZR7_PE *((volatile unsigned int*)(0x4266E3B8UL)) +#define bFM3_GPIO_PZR7_PF *((volatile unsigned int*)(0x4266E3BCUL)) +#define bFM3_GPIO_PZR8_P0 *((volatile unsigned int*)(0x4266E400UL)) +#define bFM3_GPIO_PZR8_P1 *((volatile unsigned int*)(0x4266E404UL)) +#define bFM3_GPIO_PZR8_P2 *((volatile unsigned int*)(0x4266E408UL)) +#define bFM3_GPIO_PZR8_P3 *((volatile unsigned int*)(0x4266E40CUL)) +#define bFM3_GPIO_PZR9_P0 *((volatile unsigned int*)(0x4266E480UL)) +#define bFM3_GPIO_PZR9_P1 *((volatile unsigned int*)(0x4266E484UL)) +#define bFM3_GPIO_PZR9_P2 *((volatile unsigned int*)(0x4266E488UL)) +#define bFM3_GPIO_PZR9_P3 *((volatile unsigned int*)(0x4266E48CUL)) +#define bFM3_GPIO_PZR9_P4 *((volatile unsigned int*)(0x4266E490UL)) +#define bFM3_GPIO_PZR9_P5 *((volatile unsigned int*)(0x4266E494UL)) +#define bFM3_GPIO_PZRA_P0 *((volatile unsigned int*)(0x4266E500UL)) +#define bFM3_GPIO_PZRA_P1 *((volatile unsigned int*)(0x4266E504UL)) +#define bFM3_GPIO_PZRA_P2 *((volatile unsigned int*)(0x4266E508UL)) +#define bFM3_GPIO_PZRA_P3 *((volatile unsigned int*)(0x4266E50CUL)) +#define bFM3_GPIO_PZRA_P4 *((volatile unsigned int*)(0x4266E510UL)) +#define bFM3_GPIO_PZRA_P5 *((volatile unsigned int*)(0x4266E514UL)) +#define bFM3_GPIO_PZRB_P0 *((volatile unsigned int*)(0x4266E580UL)) +#define bFM3_GPIO_PZRB_P1 *((volatile unsigned int*)(0x4266E584UL)) +#define bFM3_GPIO_PZRB_P2 *((volatile unsigned int*)(0x4266E588UL)) +#define bFM3_GPIO_PZRB_P3 *((volatile unsigned int*)(0x4266E58CUL)) +#define bFM3_GPIO_PZRB_P4 *((volatile unsigned int*)(0x4266E590UL)) +#define bFM3_GPIO_PZRB_P5 *((volatile unsigned int*)(0x4266E594UL)) +#define bFM3_GPIO_PZRB_P6 *((volatile unsigned int*)(0x4266E598UL)) +#define bFM3_GPIO_PZRB_P7 *((volatile unsigned int*)(0x4266E59CUL)) +#define bFM3_GPIO_PZRC_P0 *((volatile unsigned int*)(0x4266E600UL)) +#define bFM3_GPIO_PZRC_P1 *((volatile unsigned int*)(0x4266E604UL)) +#define bFM3_GPIO_PZRC_P2 *((volatile unsigned int*)(0x4266E608UL)) +#define bFM3_GPIO_PZRC_P3 *((volatile unsigned int*)(0x4266E60CUL)) +#define bFM3_GPIO_PZRC_P4 *((volatile unsigned int*)(0x4266E610UL)) +#define bFM3_GPIO_PZRC_P5 *((volatile unsigned int*)(0x4266E614UL)) +#define bFM3_GPIO_PZRC_P6 *((volatile unsigned int*)(0x4266E618UL)) +#define bFM3_GPIO_PZRC_P7 *((volatile unsigned int*)(0x4266E61CUL)) +#define bFM3_GPIO_PZRC_P8 *((volatile unsigned int*)(0x4266E620UL)) +#define bFM3_GPIO_PZRC_P9 *((volatile unsigned int*)(0x4266E624UL)) +#define bFM3_GPIO_PZRC_PA *((volatile unsigned int*)(0x4266E628UL)) +#define bFM3_GPIO_PZRC_PB *((volatile unsigned int*)(0x4266E62CUL)) +#define bFM3_GPIO_PZRC_PC *((volatile unsigned int*)(0x4266E630UL)) +#define bFM3_GPIO_PZRC_PD *((volatile unsigned int*)(0x4266E634UL)) +#define bFM3_GPIO_PZRC_PE *((volatile unsigned int*)(0x4266E638UL)) +#define bFM3_GPIO_PZRC_PF *((volatile unsigned int*)(0x4266E63CUL)) +#define bFM3_GPIO_PZRD_P0 *((volatile unsigned int*)(0x4266E680UL)) +#define bFM3_GPIO_PZRD_P1 *((volatile unsigned int*)(0x4266E684UL)) +#define bFM3_GPIO_PZRD_P2 *((volatile unsigned int*)(0x4266E688UL)) +#define bFM3_GPIO_PZRD_P3 *((volatile unsigned int*)(0x4266E68CUL)) +#define bFM3_GPIO_PZRE_P0 *((volatile unsigned int*)(0x4266E700UL)) +#define bFM3_GPIO_PZRE_P2 *((volatile unsigned int*)(0x4266E708UL)) +#define bFM3_GPIO_PZRE_P3 *((volatile unsigned int*)(0x4266E70CUL)) +#define bFM3_GPIO_PZRF_P0 *((volatile unsigned int*)(0x4266E780UL)) +#define bFM3_GPIO_PZRF_P1 *((volatile unsigned int*)(0x4266E784UL)) +#define bFM3_GPIO_PZRF_P2 *((volatile unsigned int*)(0x4266E788UL)) +#define bFM3_GPIO_PZRF_P3 *((volatile unsigned int*)(0x4266E78CUL)) +#define bFM3_GPIO_PZRF_P4 *((volatile unsigned int*)(0x4266E790UL)) +#define bFM3_GPIO_PZRF_P5 *((volatile unsigned int*)(0x4266E794UL)) +#define bFM3_GPIO_PZRF_P6 *((volatile unsigned int*)(0x4266E798UL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBETHERNETCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) +#define bFM3_USBETHERNETCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) +#define bFM3_USBETHERNETCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) +#define bFM3_USBETHERNETCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) +#define bFM3_USBETHERNETCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) +#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBETHERNETCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) +#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) +#define bFM3_USBETHERNETCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) +#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) +#define bFM3_USBETHERNETCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) +#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) +#define bFM3_USBETHERNETCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) +#define bFM3_USBETHERNETCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* MFS Noise Filter Control registers */ +#define bFM3_MFS_NFC_I2CDNF_I2CDNF00 *((volatile unsigned int*)(0x42710000UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF01 *((volatile unsigned int*)(0x42710004UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF10 *((volatile unsigned int*)(0x42710008UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF11 *((volatile unsigned int*)(0x4271000CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF20 *((volatile unsigned int*)(0x42710010UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF21 *((volatile unsigned int*)(0x42710014UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF30 *((volatile unsigned int*)(0x42710018UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF31 *((volatile unsigned int*)(0x4271001CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF40 *((volatile unsigned int*)(0x42710020UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF41 *((volatile unsigned int*)(0x42710024UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF50 *((volatile unsigned int*)(0x42710028UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF51 *((volatile unsigned int*)(0x4271002CUL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF60 *((volatile unsigned int*)(0x42710030UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF61 *((volatile unsigned int*)(0x42710034UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF70 *((volatile unsigned int*)(0x42710038UL)) +#define bFM3_MFS_NFC_I2CDNF_I2CDNF71 *((volatile unsigned int*)(0x4271003CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_RDY *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE0_SHRTDOUT *((volatile unsigned int*)(0x427E001CUL)) +#define bFM3_EXBUS_MODE0_MPXMODE *((volatile unsigned int*)(0x427E0020UL)) +#define bFM3_EXBUS_MODE0_ALEINV *((volatile unsigned int*)(0x427E0024UL)) +#define bFM3_EXBUS_MODE0_MPXDOFF *((volatile unsigned int*)(0x427E002CUL)) +#define bFM3_EXBUS_MODE0_MPXCSOF *((volatile unsigned int*)(0x427E0030UL)) +#define bFM3_EXBUS_MODE0_MOEXEUP *((volatile unsigned int*)(0x427E0034UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_RDY *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE1_SHRTDOUT *((volatile unsigned int*)(0x427E009CUL)) +#define bFM3_EXBUS_MODE1_MPXMODE *((volatile unsigned int*)(0x427E00A0UL)) +#define bFM3_EXBUS_MODE1_ALEINV *((volatile unsigned int*)(0x427E00A4UL)) +#define bFM3_EXBUS_MODE1_MPXDOFF *((volatile unsigned int*)(0x427E00ACUL)) +#define bFM3_EXBUS_MODE1_MPXCSOF *((volatile unsigned int*)(0x427E00B0UL)) +#define bFM3_EXBUS_MODE1_MOEXEUP *((volatile unsigned int*)(0x427E00B4UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_RDY *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE2_SHRTDOUT *((volatile unsigned int*)(0x427E011CUL)) +#define bFM3_EXBUS_MODE2_MPXMODE *((volatile unsigned int*)(0x427E0120UL)) +#define bFM3_EXBUS_MODE2_ALEINV *((volatile unsigned int*)(0x427E0124UL)) +#define bFM3_EXBUS_MODE2_MPXDOFF *((volatile unsigned int*)(0x427E012CUL)) +#define bFM3_EXBUS_MODE2_MPXCSOF *((volatile unsigned int*)(0x427E0130UL)) +#define bFM3_EXBUS_MODE2_MOEXEUP *((volatile unsigned int*)(0x427E0134UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_RDY *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE3_SHRTDOUT *((volatile unsigned int*)(0x427E019CUL)) +#define bFM3_EXBUS_MODE3_MPXMODE *((volatile unsigned int*)(0x427E01A0UL)) +#define bFM3_EXBUS_MODE3_ALEINV *((volatile unsigned int*)(0x427E01A4UL)) +#define bFM3_EXBUS_MODE3_MPXDOFF *((volatile unsigned int*)(0x427E01ACUL)) +#define bFM3_EXBUS_MODE3_MPXCSOF *((volatile unsigned int*)(0x427E01B0UL)) +#define bFM3_EXBUS_MODE3_MOEXEUP *((volatile unsigned int*)(0x427E01B4UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_RDY *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE4_SHRTDOUT *((volatile unsigned int*)(0x427E021CUL)) +#define bFM3_EXBUS_MODE4_MPXMODE *((volatile unsigned int*)(0x427E0220UL)) +#define bFM3_EXBUS_MODE4_ALEINV *((volatile unsigned int*)(0x427E0224UL)) +#define bFM3_EXBUS_MODE4_MPXDOFF *((volatile unsigned int*)(0x427E022CUL)) +#define bFM3_EXBUS_MODE4_MPXCSOF *((volatile unsigned int*)(0x427E0230UL)) +#define bFM3_EXBUS_MODE4_MOEXEUP *((volatile unsigned int*)(0x427E0234UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_RDY *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE5_SHRTDOUT *((volatile unsigned int*)(0x427E029CUL)) +#define bFM3_EXBUS_MODE5_MPXMODE *((volatile unsigned int*)(0x427E02A0UL)) +#define bFM3_EXBUS_MODE5_ALEINV *((volatile unsigned int*)(0x427E02A4UL)) +#define bFM3_EXBUS_MODE5_MPXDOFF *((volatile unsigned int*)(0x427E02ACUL)) +#define bFM3_EXBUS_MODE5_MPXCSOF *((volatile unsigned int*)(0x427E02B0UL)) +#define bFM3_EXBUS_MODE5_MOEXEUP *((volatile unsigned int*)(0x427E02B4UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_RDY *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE6_SHRTDOUT *((volatile unsigned int*)(0x427E031CUL)) +#define bFM3_EXBUS_MODE6_MPXMODE *((volatile unsigned int*)(0x427E0320UL)) +#define bFM3_EXBUS_MODE6_ALEINV *((volatile unsigned int*)(0x427E0324UL)) +#define bFM3_EXBUS_MODE6_MPXDOFF *((volatile unsigned int*)(0x427E032CUL)) +#define bFM3_EXBUS_MODE6_MPXCSOF *((volatile unsigned int*)(0x427E0330UL)) +#define bFM3_EXBUS_MODE6_MOEXEUP *((volatile unsigned int*)(0x427E0334UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_RDY *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_MODE7_SHRTDOUT *((volatile unsigned int*)(0x427E039CUL)) +#define bFM3_EXBUS_MODE7_MPXMODE *((volatile unsigned int*)(0x427E03A0UL)) +#define bFM3_EXBUS_MODE7_ALEINV *((volatile unsigned int*)(0x427E03A4UL)) +#define bFM3_EXBUS_MODE7_MPXDOFF *((volatile unsigned int*)(0x427E03ACUL)) +#define bFM3_EXBUS_MODE7_MPXCSOF *((volatile unsigned int*)(0x427E03B0UL)) +#define bFM3_EXBUS_MODE7_MOEXEUP *((volatile unsigned int*)(0x427E03B4UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) +#define bFM3_EXBUS_ATIM0_ALC0 *((volatile unsigned int*)(0x427E0C00UL)) +#define bFM3_EXBUS_ATIM0_ALC1 *((volatile unsigned int*)(0x427E0C04UL)) +#define bFM3_EXBUS_ATIM0_ALC2 *((volatile unsigned int*)(0x427E0C08UL)) +#define bFM3_EXBUS_ATIM0_ALC3 *((volatile unsigned int*)(0x427E0C0CUL)) +#define bFM3_EXBUS_ATIM0_ALES0 *((volatile unsigned int*)(0x427E0C10UL)) +#define bFM3_EXBUS_ATIM0_ALES1 *((volatile unsigned int*)(0x427E0C14UL)) +#define bFM3_EXBUS_ATIM0_ALES2 *((volatile unsigned int*)(0x427E0C18UL)) +#define bFM3_EXBUS_ATIM0_ALES3 *((volatile unsigned int*)(0x427E0C1CUL)) +#define bFM3_EXBUS_ATIM0_ALEW0 *((volatile unsigned int*)(0x427E0C20UL)) +#define bFM3_EXBUS_ATIM0_ALEW1 *((volatile unsigned int*)(0x427E0C24UL)) +#define bFM3_EXBUS_ATIM0_ALEW2 *((volatile unsigned int*)(0x427E0C28UL)) +#define bFM3_EXBUS_ATIM0_ALEW3 *((volatile unsigned int*)(0x427E0C2CUL)) +#define bFM3_EXBUS_ATIM1_ALC0 *((volatile unsigned int*)(0x427E0C80UL)) +#define bFM3_EXBUS_ATIM1_ALC1 *((volatile unsigned int*)(0x427E0C84UL)) +#define bFM3_EXBUS_ATIM1_ALC2 *((volatile unsigned int*)(0x427E0C88UL)) +#define bFM3_EXBUS_ATIM1_ALC3 *((volatile unsigned int*)(0x427E0C8CUL)) +#define bFM3_EXBUS_ATIM1_ALES0 *((volatile unsigned int*)(0x427E0C90UL)) +#define bFM3_EXBUS_ATIM1_ALES1 *((volatile unsigned int*)(0x427E0C94UL)) +#define bFM3_EXBUS_ATIM1_ALES2 *((volatile unsigned int*)(0x427E0C98UL)) +#define bFM3_EXBUS_ATIM1_ALES3 *((volatile unsigned int*)(0x427E0C9CUL)) +#define bFM3_EXBUS_ATIM1_ALEW0 *((volatile unsigned int*)(0x427E0CA0UL)) +#define bFM3_EXBUS_ATIM1_ALEW1 *((volatile unsigned int*)(0x427E0CA4UL)) +#define bFM3_EXBUS_ATIM1_ALEW2 *((volatile unsigned int*)(0x427E0CA8UL)) +#define bFM3_EXBUS_ATIM1_ALEW3 *((volatile unsigned int*)(0x427E0CACUL)) +#define bFM3_EXBUS_ATIM2_ALC0 *((volatile unsigned int*)(0x427E0D00UL)) +#define bFM3_EXBUS_ATIM2_ALC1 *((volatile unsigned int*)(0x427E0D04UL)) +#define bFM3_EXBUS_ATIM2_ALC2 *((volatile unsigned int*)(0x427E0D08UL)) +#define bFM3_EXBUS_ATIM2_ALC3 *((volatile unsigned int*)(0x427E0D0CUL)) +#define bFM3_EXBUS_ATIM2_ALES0 *((volatile unsigned int*)(0x427E0D10UL)) +#define bFM3_EXBUS_ATIM2_ALES1 *((volatile unsigned int*)(0x427E0D14UL)) +#define bFM3_EXBUS_ATIM2_ALES2 *((volatile unsigned int*)(0x427E0D18UL)) +#define bFM3_EXBUS_ATIM2_ALES3 *((volatile unsigned int*)(0x427E0D1CUL)) +#define bFM3_EXBUS_ATIM2_ALEW0 *((volatile unsigned int*)(0x427E0D20UL)) +#define bFM3_EXBUS_ATIM2_ALEW1 *((volatile unsigned int*)(0x427E0D24UL)) +#define bFM3_EXBUS_ATIM2_ALEW2 *((volatile unsigned int*)(0x427E0D28UL)) +#define bFM3_EXBUS_ATIM2_ALEW3 *((volatile unsigned int*)(0x427E0D2CUL)) +#define bFM3_EXBUS_ATIM3_ALC0 *((volatile unsigned int*)(0x427E0D80UL)) +#define bFM3_EXBUS_ATIM3_ALC1 *((volatile unsigned int*)(0x427E0D84UL)) +#define bFM3_EXBUS_ATIM3_ALC2 *((volatile unsigned int*)(0x427E0D88UL)) +#define bFM3_EXBUS_ATIM3_ALC3 *((volatile unsigned int*)(0x427E0D8CUL)) +#define bFM3_EXBUS_ATIM3_ALES0 *((volatile unsigned int*)(0x427E0D90UL)) +#define bFM3_EXBUS_ATIM3_ALES1 *((volatile unsigned int*)(0x427E0D94UL)) +#define bFM3_EXBUS_ATIM3_ALES2 *((volatile unsigned int*)(0x427E0D98UL)) +#define bFM3_EXBUS_ATIM3_ALES3 *((volatile unsigned int*)(0x427E0D9CUL)) +#define bFM3_EXBUS_ATIM3_ALEW0 *((volatile unsigned int*)(0x427E0DA0UL)) +#define bFM3_EXBUS_ATIM3_ALEW1 *((volatile unsigned int*)(0x427E0DA4UL)) +#define bFM3_EXBUS_ATIM3_ALEW2 *((volatile unsigned int*)(0x427E0DA8UL)) +#define bFM3_EXBUS_ATIM3_ALEW3 *((volatile unsigned int*)(0x427E0DACUL)) +#define bFM3_EXBUS_ATIM4_ALC0 *((volatile unsigned int*)(0x427E0E00UL)) +#define bFM3_EXBUS_ATIM4_ALC1 *((volatile unsigned int*)(0x427E0E04UL)) +#define bFM3_EXBUS_ATIM4_ALC2 *((volatile unsigned int*)(0x427E0E08UL)) +#define bFM3_EXBUS_ATIM4_ALC3 *((volatile unsigned int*)(0x427E0E0CUL)) +#define bFM3_EXBUS_ATIM4_ALES0 *((volatile unsigned int*)(0x427E0E10UL)) +#define bFM3_EXBUS_ATIM4_ALES1 *((volatile unsigned int*)(0x427E0E14UL)) +#define bFM3_EXBUS_ATIM4_ALES2 *((volatile unsigned int*)(0x427E0E18UL)) +#define bFM3_EXBUS_ATIM4_ALES3 *((volatile unsigned int*)(0x427E0E1CUL)) +#define bFM3_EXBUS_ATIM4_ALEW0 *((volatile unsigned int*)(0x427E0E20UL)) +#define bFM3_EXBUS_ATIM4_ALEW1 *((volatile unsigned int*)(0x427E0E24UL)) +#define bFM3_EXBUS_ATIM4_ALEW2 *((volatile unsigned int*)(0x427E0E28UL)) +#define bFM3_EXBUS_ATIM4_ALEW3 *((volatile unsigned int*)(0x427E0E2CUL)) +#define bFM3_EXBUS_ATIM5_ALC0 *((volatile unsigned int*)(0x427E0E80UL)) +#define bFM3_EXBUS_ATIM5_ALC1 *((volatile unsigned int*)(0x427E0E84UL)) +#define bFM3_EXBUS_ATIM5_ALC2 *((volatile unsigned int*)(0x427E0E88UL)) +#define bFM3_EXBUS_ATIM5_ALC3 *((volatile unsigned int*)(0x427E0E8CUL)) +#define bFM3_EXBUS_ATIM5_ALES0 *((volatile unsigned int*)(0x427E0E90UL)) +#define bFM3_EXBUS_ATIM5_ALES1 *((volatile unsigned int*)(0x427E0E94UL)) +#define bFM3_EXBUS_ATIM5_ALES2 *((volatile unsigned int*)(0x427E0E98UL)) +#define bFM3_EXBUS_ATIM5_ALES3 *((volatile unsigned int*)(0x427E0E9CUL)) +#define bFM3_EXBUS_ATIM5_ALEW0 *((volatile unsigned int*)(0x427E0EA0UL)) +#define bFM3_EXBUS_ATIM5_ALEW1 *((volatile unsigned int*)(0x427E0EA4UL)) +#define bFM3_EXBUS_ATIM5_ALEW2 *((volatile unsigned int*)(0x427E0EA8UL)) +#define bFM3_EXBUS_ATIM5_ALEW3 *((volatile unsigned int*)(0x427E0EACUL)) +#define bFM3_EXBUS_ATIM6_ALC0 *((volatile unsigned int*)(0x427E0F00UL)) +#define bFM3_EXBUS_ATIM6_ALC1 *((volatile unsigned int*)(0x427E0F04UL)) +#define bFM3_EXBUS_ATIM6_ALC2 *((volatile unsigned int*)(0x427E0F08UL)) +#define bFM3_EXBUS_ATIM6_ALC3 *((volatile unsigned int*)(0x427E0F0CUL)) +#define bFM3_EXBUS_ATIM6_ALES0 *((volatile unsigned int*)(0x427E0F10UL)) +#define bFM3_EXBUS_ATIM6_ALES1 *((volatile unsigned int*)(0x427E0F14UL)) +#define bFM3_EXBUS_ATIM6_ALES2 *((volatile unsigned int*)(0x427E0F18UL)) +#define bFM3_EXBUS_ATIM6_ALES3 *((volatile unsigned int*)(0x427E0F1CUL)) +#define bFM3_EXBUS_ATIM6_ALEW0 *((volatile unsigned int*)(0x427E0F20UL)) +#define bFM3_EXBUS_ATIM6_ALEW1 *((volatile unsigned int*)(0x427E0F24UL)) +#define bFM3_EXBUS_ATIM6_ALEW2 *((volatile unsigned int*)(0x427E0F28UL)) +#define bFM3_EXBUS_ATIM6_ALEW3 *((volatile unsigned int*)(0x427E0F2CUL)) +#define bFM3_EXBUS_ATIM7_ALC0 *((volatile unsigned int*)(0x427E0F80UL)) +#define bFM3_EXBUS_ATIM7_ALC1 *((volatile unsigned int*)(0x427E0F84UL)) +#define bFM3_EXBUS_ATIM7_ALC2 *((volatile unsigned int*)(0x427E0F88UL)) +#define bFM3_EXBUS_ATIM7_ALC3 *((volatile unsigned int*)(0x427E0F8CUL)) +#define bFM3_EXBUS_ATIM7_ALES0 *((volatile unsigned int*)(0x427E0F90UL)) +#define bFM3_EXBUS_ATIM7_ALES1 *((volatile unsigned int*)(0x427E0F94UL)) +#define bFM3_EXBUS_ATIM7_ALES2 *((volatile unsigned int*)(0x427E0F98UL)) +#define bFM3_EXBUS_ATIM7_ALES3 *((volatile unsigned int*)(0x427E0F9CUL)) +#define bFM3_EXBUS_ATIM7_ALEW0 *((volatile unsigned int*)(0x427E0FA0UL)) +#define bFM3_EXBUS_ATIM7_ALEW1 *((volatile unsigned int*)(0x427E0FA4UL)) +#define bFM3_EXBUS_ATIM7_ALEW2 *((volatile unsigned int*)(0x427E0FA8UL)) +#define bFM3_EXBUS_ATIM7_ALEW3 *((volatile unsigned int*)(0x427E0FACUL)) +#define bFM3_EXBUS_DCLKR_MDIV0 *((volatile unsigned int*)(0x427E6000UL)) +#define bFM3_EXBUS_DCLKR_MDIV1 *((volatile unsigned int*)(0x427E6004UL)) +#define bFM3_EXBUS_DCLKR_MDIV2 *((volatile unsigned int*)(0x427E6008UL)) +#define bFM3_EXBUS_DCLKR_MDIV3 *((volatile unsigned int*)(0x427E600CUL)) +#define bFM3_EXBUS_DCLKR_MCLKON *((volatile unsigned int*)(0x427E6010UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* USB channel 1 registers */ +#define bFM3_USB1_HCNT_HOST *((volatile unsigned int*)(0x42A42000UL)) +#define bFM3_USB1_HCNT_URST *((volatile unsigned int*)(0x42A42004UL)) +#define bFM3_USB1_HCNT_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) +#define bFM3_USB1_HCNT_DIRE *((volatile unsigned int*)(0x42A4200CUL)) +#define bFM3_USB1_HCNT_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) +#define bFM3_USB1_HCNT_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) +#define bFM3_USB1_HCNT_URIRE *((volatile unsigned int*)(0x42A42018UL)) +#define bFM3_USB1_HCNT_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) +#define bFM3_USB1_HCNT_RETRY *((volatile unsigned int*)(0x42A42020UL)) +#define bFM3_USB1_HCNT_CANCEL *((volatile unsigned int*)(0x42A42024UL)) +#define bFM3_USB1_HCNT_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) +#define bFM3_USB1_HCNT0_HOST *((volatile unsigned int*)(0x42A42000UL)) +#define bFM3_USB1_HCNT0_URST *((volatile unsigned int*)(0x42A42004UL)) +#define bFM3_USB1_HCNT0_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) +#define bFM3_USB1_HCNT0_DIRE *((volatile unsigned int*)(0x42A4200CUL)) +#define bFM3_USB1_HCNT0_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) +#define bFM3_USB1_HCNT0_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) +#define bFM3_USB1_HCNT0_URIRE *((volatile unsigned int*)(0x42A42018UL)) +#define bFM3_USB1_HCNT0_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) +#define bFM3_USB1_HCNT1_RETRY *((volatile unsigned int*)(0x42A42020UL)) +#define bFM3_USB1_HCNT1_CANCEL *((volatile unsigned int*)(0x42A42024UL)) +#define bFM3_USB1_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) +#define bFM3_USB1_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42A42080UL)) +#define bFM3_USB1_HIRQ_DIRQ *((volatile unsigned int*)(0x42A42084UL)) +#define bFM3_USB1_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42A42088UL)) +#define bFM3_USB1_HIRQ_CMPIRQ *((volatile unsigned int*)(0x42A4208CUL)) +#define bFM3_USB1_HIRQ_URIRQ *((volatile unsigned int*)(0x42A42090UL)) +#define bFM3_USB1_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42A42094UL)) +#define bFM3_USB1_HIRQ_TCAN *((volatile unsigned int*)(0x42A4209CUL)) +#define bFM3_USB1_HERR_HS0 *((volatile unsigned int*)(0x42A420A0UL)) +#define bFM3_USB1_HERR_HS1 *((volatile unsigned int*)(0x42A420A4UL)) +#define bFM3_USB1_HERR_STUFF *((volatile unsigned int*)(0x42A420A8UL)) +#define bFM3_USB1_HERR_TGERR *((volatile unsigned int*)(0x42A420ACUL)) +#define bFM3_USB1_HERR_CRC *((volatile unsigned int*)(0x42A420B0UL)) +#define bFM3_USB1_HERR_TOUT *((volatile unsigned int*)(0x42A420B4UL)) +#define bFM3_USB1_HERR_RERR *((volatile unsigned int*)(0x42A420B8UL)) +#define bFM3_USB1_HERR_LSTOF *((volatile unsigned int*)(0x42A420BCUL)) +#define bFM3_USB1_HSTATE_CSTAT *((volatile unsigned int*)(0x42A42100UL)) +#define bFM3_USB1_HSTATE_TMODE *((volatile unsigned int*)(0x42A42104UL)) +#define bFM3_USB1_HSTATE_SUSP *((volatile unsigned int*)(0x42A42108UL)) +#define bFM3_USB1_HSTATE_SOFBUSY *((volatile unsigned int*)(0x42A4210CUL)) +#define bFM3_USB1_HSTATE_CLKSEL *((volatile unsigned int*)(0x42A42110UL)) +#define bFM3_USB1_HSTATE_ALIVE *((volatile unsigned int*)(0x42A42114UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42A42120UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42A42124UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42A42128UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x42A4212CUL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42A42130UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42A42134UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42A42138UL)) +#define bFM3_USB1_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x42A4213CUL)) +#define bFM3_USB1_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42A42180UL)) +#define bFM3_USB1_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42A42184UL)) +#define bFM3_USB1_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42A42188UL)) +#define bFM3_USB1_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x42A4218CUL)) +#define bFM3_USB1_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42A42190UL)) +#define bFM3_USB1_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42A42194UL)) +#define bFM3_USB1_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42A42198UL)) +#define bFM3_USB1_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x42A4219CUL)) +#define bFM3_USB1_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x42A421A0UL)) +#define bFM3_USB1_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x42A421A4UL)) +#define bFM3_USB1_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x42A421A8UL)) +#define bFM3_USB1_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x42A421ACUL)) +#define bFM3_USB1_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x42A421B0UL)) +#define bFM3_USB1_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x42A421B4UL)) +#define bFM3_USB1_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x42A421B8UL)) +#define bFM3_USB1_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x42A421BCUL)) +#define bFM3_USB1_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42A42180UL)) +#define bFM3_USB1_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42A42184UL)) +#define bFM3_USB1_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42A42188UL)) +#define bFM3_USB1_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x42A4218CUL)) +#define bFM3_USB1_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42A42190UL)) +#define bFM3_USB1_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42A42194UL)) +#define bFM3_USB1_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42A42198UL)) +#define bFM3_USB1_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x42A4219CUL)) +#define bFM3_USB1_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x42A421A0UL)) +#define bFM3_USB1_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x42A421A4UL)) +#define bFM3_USB1_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x42A421A8UL)) +#define bFM3_USB1_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x42A421ACUL)) +#define bFM3_USB1_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x42A421B0UL)) +#define bFM3_USB1_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x42A421B4UL)) +#define bFM3_USB1_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x42A421B8UL)) +#define bFM3_USB1_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x42A421BCUL)) +#define bFM3_USB1_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42A42200UL)) +#define bFM3_USB1_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42A42204UL)) +#define bFM3_USB1_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42A42208UL)) +#define bFM3_USB1_HADR_ADDRESS0 *((volatile unsigned int*)(0x42A42220UL)) +#define bFM3_USB1_HADR_ADDRESS1 *((volatile unsigned int*)(0x42A42224UL)) +#define bFM3_USB1_HADR_ADDRESS2 *((volatile unsigned int*)(0x42A42228UL)) +#define bFM3_USB1_HADR_ADDRESS3 *((volatile unsigned int*)(0x42A4222CUL)) +#define bFM3_USB1_HADR_ADDRESS4 *((volatile unsigned int*)(0x42A42230UL)) +#define bFM3_USB1_HADR_ADDRESS5 *((volatile unsigned int*)(0x42A42234UL)) +#define bFM3_USB1_HADR_ADDRESS6 *((volatile unsigned int*)(0x42A42238UL)) +#define bFM3_USB1_HEOF_EOF0 *((volatile unsigned int*)(0x42A42280UL)) +#define bFM3_USB1_HEOF_EOF1 *((volatile unsigned int*)(0x42A42284UL)) +#define bFM3_USB1_HEOF_EOF2 *((volatile unsigned int*)(0x42A42288UL)) +#define bFM3_USB1_HEOF_EOF3 *((volatile unsigned int*)(0x42A4228CUL)) +#define bFM3_USB1_HEOF_EOF4 *((volatile unsigned int*)(0x42A42290UL)) +#define bFM3_USB1_HEOF_EOF5 *((volatile unsigned int*)(0x42A42294UL)) +#define bFM3_USB1_HEOF_EOF6 *((volatile unsigned int*)(0x42A42298UL)) +#define bFM3_USB1_HEOF_EOF7 *((volatile unsigned int*)(0x42A4229CUL)) +#define bFM3_USB1_HEOF_EOF8 *((volatile unsigned int*)(0x42A422A0UL)) +#define bFM3_USB1_HEOF_EOF9 *((volatile unsigned int*)(0x42A422A4UL)) +#define bFM3_USB1_HEOF_EOF10 *((volatile unsigned int*)(0x42A422A8UL)) +#define bFM3_USB1_HEOF_EOF11 *((volatile unsigned int*)(0x42A422ACUL)) +#define bFM3_USB1_HEOF_EOF12 *((volatile unsigned int*)(0x42A422B0UL)) +#define bFM3_USB1_HEOF_EOF13 *((volatile unsigned int*)(0x42A422B4UL)) +#define bFM3_USB1_HEOF_EOF14 *((volatile unsigned int*)(0x42A422B8UL)) +#define bFM3_USB1_HEOF_EOF15 *((volatile unsigned int*)(0x42A422BCUL)) +#define bFM3_USB1_HEOF0_EOF00 *((volatile unsigned int*)(0x42A42280UL)) +#define bFM3_USB1_HEOF0_EOF01 *((volatile unsigned int*)(0x42A42284UL)) +#define bFM3_USB1_HEOF0_EOF02 *((volatile unsigned int*)(0x42A42288UL)) +#define bFM3_USB1_HEOF0_EOF03 *((volatile unsigned int*)(0x42A4228CUL)) +#define bFM3_USB1_HEOF0_EOF04 *((volatile unsigned int*)(0x42A42290UL)) +#define bFM3_USB1_HEOF0_EOF05 *((volatile unsigned int*)(0x42A42294UL)) +#define bFM3_USB1_HEOF0_EOF06 *((volatile unsigned int*)(0x42A42298UL)) +#define bFM3_USB1_HEOF0_EOF07 *((volatile unsigned int*)(0x42A4229CUL)) +#define bFM3_USB1_HEOF1_EOF10 *((volatile unsigned int*)(0x42A422A0UL)) +#define bFM3_USB1_HEOF1_EOF11 *((volatile unsigned int*)(0x42A422A4UL)) +#define bFM3_USB1_HEOF1_EOF12 *((volatile unsigned int*)(0x42A422A8UL)) +#define bFM3_USB1_HEOF1_EOF13 *((volatile unsigned int*)(0x42A422ACUL)) +#define bFM3_USB1_HEOF1_EOF14 *((volatile unsigned int*)(0x42A422B0UL)) +#define bFM3_USB1_HEOF1_EOF15 *((volatile unsigned int*)(0x42A422B4UL)) +#define bFM3_USB1_HFRAME_FRAME0 *((volatile unsigned int*)(0x42A42300UL)) +#define bFM3_USB1_HFRAME_FRAME1 *((volatile unsigned int*)(0x42A42304UL)) +#define bFM3_USB1_HFRAME_FRAME2 *((volatile unsigned int*)(0x42A42308UL)) +#define bFM3_USB1_HFRAME_FRAME3 *((volatile unsigned int*)(0x42A4230CUL)) +#define bFM3_USB1_HFRAME_FRAME4 *((volatile unsigned int*)(0x42A42310UL)) +#define bFM3_USB1_HFRAME_FRAME5 *((volatile unsigned int*)(0x42A42314UL)) +#define bFM3_USB1_HFRAME_FRAME6 *((volatile unsigned int*)(0x42A42318UL)) +#define bFM3_USB1_HFRAME_FRAME7 *((volatile unsigned int*)(0x42A4231CUL)) +#define bFM3_USB1_HFRAME_FRAME8 *((volatile unsigned int*)(0x42A42320UL)) +#define bFM3_USB1_HFRAME_FRAME9 *((volatile unsigned int*)(0x42A42324UL)) +#define bFM3_USB1_HFRAME_FRAME10 *((volatile unsigned int*)(0x42A42328UL)) +#define bFM3_USB1_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42A42300UL)) +#define bFM3_USB1_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42A42304UL)) +#define bFM3_USB1_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42A42308UL)) +#define bFM3_USB1_HFRAME0_FRAME03 *((volatile unsigned int*)(0x42A4230CUL)) +#define bFM3_USB1_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42A42310UL)) +#define bFM3_USB1_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42A42314UL)) +#define bFM3_USB1_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42A42318UL)) +#define bFM3_USB1_HFRAME0_FRAME07 *((volatile unsigned int*)(0x42A4231CUL)) +#define bFM3_USB1_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42A42320UL)) +#define bFM3_USB1_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42A42324UL)) +#define bFM3_USB1_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42A42328UL)) +#define bFM3_USB1_HFRAME1_FRAME13 *((volatile unsigned int*)(0x42A4232CUL)) +#define bFM3_USB1_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42A42380UL)) +#define bFM3_USB1_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42A42384UL)) +#define bFM3_USB1_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42A42388UL)) +#define bFM3_USB1_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x42A4238CUL)) +#define bFM3_USB1_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42A42390UL)) +#define bFM3_USB1_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42A42394UL)) +#define bFM3_USB1_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42A42398UL)) +#define bFM3_USB1_HTOKEN_TGGL *((volatile unsigned int*)(0x42A4239CUL)) +#define bFM3_USB1_UDCC_PWC *((volatile unsigned int*)(0x42A42400UL)) +#define bFM3_USB1_UDCC_RFBK *((volatile unsigned int*)(0x42A42404UL)) +#define bFM3_USB1_UDCC_STALCLREN *((volatile unsigned int*)(0x42A4240CUL)) +#define bFM3_USB1_UDCC_USTP *((volatile unsigned int*)(0x42A42410UL)) +#define bFM3_USB1_UDCC_HCONX *((volatile unsigned int*)(0x42A42414UL)) +#define bFM3_USB1_UDCC_RESUM *((volatile unsigned int*)(0x42A42418UL)) +#define bFM3_USB1_UDCC_RST *((volatile unsigned int*)(0x42A4241CUL)) +#define bFM3_USB1_EP0C_PKS00 *((volatile unsigned int*)(0x42A42480UL)) +#define bFM3_USB1_EP0C_PKS01 *((volatile unsigned int*)(0x42A42484UL)) +#define bFM3_USB1_EP0C_PKS02 *((volatile unsigned int*)(0x42A42488UL)) +#define bFM3_USB1_EP0C_PKS03 *((volatile unsigned int*)(0x42A4248CUL)) +#define bFM3_USB1_EP0C_PKS04 *((volatile unsigned int*)(0x42A42490UL)) +#define bFM3_USB1_EP0C_PKS05 *((volatile unsigned int*)(0x42A42494UL)) +#define bFM3_USB1_EP0C_PKS06 *((volatile unsigned int*)(0x42A42498UL)) +#define bFM3_USB1_EP0C_STAL *((volatile unsigned int*)(0x42A424A4UL)) +#define bFM3_USB1_EP1C_PKS10 *((volatile unsigned int*)(0x42A42500UL)) +#define bFM3_USB1_EP1C_PKS11 *((volatile unsigned int*)(0x42A42504UL)) +#define bFM3_USB1_EP1C_PKS12 *((volatile unsigned int*)(0x42A42508UL)) +#define bFM3_USB1_EP1C_PKS13 *((volatile unsigned int*)(0x42A4250CUL)) +#define bFM3_USB1_EP1C_PKS14 *((volatile unsigned int*)(0x42A42510UL)) +#define bFM3_USB1_EP1C_PKS15 *((volatile unsigned int*)(0x42A42514UL)) +#define bFM3_USB1_EP1C_PKS16 *((volatile unsigned int*)(0x42A42518UL)) +#define bFM3_USB1_EP1C_PKS17 *((volatile unsigned int*)(0x42A4251CUL)) +#define bFM3_USB1_EP1C_PKS18 *((volatile unsigned int*)(0x42A42520UL)) +#define bFM3_USB1_EP1C_STAL *((volatile unsigned int*)(0x42A42524UL)) +#define bFM3_USB1_EP1C_NULE *((volatile unsigned int*)(0x42A42528UL)) +#define bFM3_USB1_EP1C_DMAE *((volatile unsigned int*)(0x42A4252CUL)) +#define bFM3_USB1_EP1C_DIR *((volatile unsigned int*)(0x42A42530UL)) +#define bFM3_USB1_EP1C_TYPE0 *((volatile unsigned int*)(0x42A42534UL)) +#define bFM3_USB1_EP1C_TYPE1 *((volatile unsigned int*)(0x42A42538UL)) +#define bFM3_USB1_EP1C_EPEN *((volatile unsigned int*)(0x42A4253CUL)) +#define bFM3_USB1_EP2C_PKS20 *((volatile unsigned int*)(0x42A42580UL)) +#define bFM3_USB1_EP2C_PKS21 *((volatile unsigned int*)(0x42A42584UL)) +#define bFM3_USB1_EP2C_PKS22 *((volatile unsigned int*)(0x42A42588UL)) +#define bFM3_USB1_EP2C_PKS23 *((volatile unsigned int*)(0x42A4258CUL)) +#define bFM3_USB1_EP2C_PKS24 *((volatile unsigned int*)(0x42A42590UL)) +#define bFM3_USB1_EP2C_PKS25 *((volatile unsigned int*)(0x42A42594UL)) +#define bFM3_USB1_EP2C_PKS26 *((volatile unsigned int*)(0x42A42598UL)) +#define bFM3_USB1_EP2C_STAL *((volatile unsigned int*)(0x42A425A4UL)) +#define bFM3_USB1_EP2C_NULE *((volatile unsigned int*)(0x42A425A8UL)) +#define bFM3_USB1_EP2C_DMAE *((volatile unsigned int*)(0x42A425ACUL)) +#define bFM3_USB1_EP2C_DIR *((volatile unsigned int*)(0x42A425B0UL)) +#define bFM3_USB1_EP2C_TYPE0 *((volatile unsigned int*)(0x42A425B4UL)) +#define bFM3_USB1_EP2C_TYPE1 *((volatile unsigned int*)(0x42A425B8UL)) +#define bFM3_USB1_EP2C_EPEN *((volatile unsigned int*)(0x42A425BCUL)) +#define bFM3_USB1_EP3C_PKS30 *((volatile unsigned int*)(0x42A42600UL)) +#define bFM3_USB1_EP3C_PKS31 *((volatile unsigned int*)(0x42A42604UL)) +#define bFM3_USB1_EP3C_PKS32 *((volatile unsigned int*)(0x42A42608UL)) +#define bFM3_USB1_EP3C_PKS33 *((volatile unsigned int*)(0x42A4260CUL)) +#define bFM3_USB1_EP3C_PKS34 *((volatile unsigned int*)(0x42A42610UL)) +#define bFM3_USB1_EP3C_PKS35 *((volatile unsigned int*)(0x42A42614UL)) +#define bFM3_USB1_EP3C_PKS36 *((volatile unsigned int*)(0x42A42618UL)) +#define bFM3_USB1_EP3C_STAL *((volatile unsigned int*)(0x42A42624UL)) +#define bFM3_USB1_EP3C_NULE *((volatile unsigned int*)(0x42A42628UL)) +#define bFM3_USB1_EP3C_DMAE *((volatile unsigned int*)(0x42A4262CUL)) +#define bFM3_USB1_EP3C_DIR *((volatile unsigned int*)(0x42A42630UL)) +#define bFM3_USB1_EP3C_TYPE0 *((volatile unsigned int*)(0x42A42634UL)) +#define bFM3_USB1_EP3C_TYPE1 *((volatile unsigned int*)(0x42A42638UL)) +#define bFM3_USB1_EP3C_EPEN *((volatile unsigned int*)(0x42A4263CUL)) +#define bFM3_USB1_EP4C_PKS40 *((volatile unsigned int*)(0x42A42680UL)) +#define bFM3_USB1_EP4C_PKS41 *((volatile unsigned int*)(0x42A42684UL)) +#define bFM3_USB1_EP4C_PKS42 *((volatile unsigned int*)(0x42A42688UL)) +#define bFM3_USB1_EP4C_PKS43 *((volatile unsigned int*)(0x42A4268CUL)) +#define bFM3_USB1_EP4C_PKS44 *((volatile unsigned int*)(0x42A42690UL)) +#define bFM3_USB1_EP4C_PKS45 *((volatile unsigned int*)(0x42A42694UL)) +#define bFM3_USB1_EP4C_PKS46 *((volatile unsigned int*)(0x42A42698UL)) +#define bFM3_USB1_EP4C_STAL *((volatile unsigned int*)(0x42A426A4UL)) +#define bFM3_USB1_EP4C_NULE *((volatile unsigned int*)(0x42A426A8UL)) +#define bFM3_USB1_EP4C_DMAE *((volatile unsigned int*)(0x42A426ACUL)) +#define bFM3_USB1_EP4C_DIR *((volatile unsigned int*)(0x42A426B0UL)) +#define bFM3_USB1_EP4C_TYPE0 *((volatile unsigned int*)(0x42A426B4UL)) +#define bFM3_USB1_EP4C_TYPE1 *((volatile unsigned int*)(0x42A426B8UL)) +#define bFM3_USB1_EP4C_EPEN *((volatile unsigned int*)(0x42A426BCUL)) +#define bFM3_USB1_EP5C_PKS50 *((volatile unsigned int*)(0x42A42700UL)) +#define bFM3_USB1_EP5C_PKS51 *((volatile unsigned int*)(0x42A42704UL)) +#define bFM3_USB1_EP5C_PKS52 *((volatile unsigned int*)(0x42A42708UL)) +#define bFM3_USB1_EP5C_PKS53 *((volatile unsigned int*)(0x42A4270CUL)) +#define bFM3_USB1_EP5C_PKS54 *((volatile unsigned int*)(0x42A42710UL)) +#define bFM3_USB1_EP5C_PKS55 *((volatile unsigned int*)(0x42A42714UL)) +#define bFM3_USB1_EP5C_PKS56 *((volatile unsigned int*)(0x42A42718UL)) +#define bFM3_USB1_EP5C_STAL *((volatile unsigned int*)(0x42A42724UL)) +#define bFM3_USB1_EP5C_NULE *((volatile unsigned int*)(0x42A42728UL)) +#define bFM3_USB1_EP5C_DMAE *((volatile unsigned int*)(0x42A4272CUL)) +#define bFM3_USB1_EP5C_DIR *((volatile unsigned int*)(0x42A42730UL)) +#define bFM3_USB1_EP5C_TYPE0 *((volatile unsigned int*)(0x42A42734UL)) +#define bFM3_USB1_EP5C_TYPE1 *((volatile unsigned int*)(0x42A42738UL)) +#define bFM3_USB1_EP5C_EPEN *((volatile unsigned int*)(0x42A4273CUL)) +#define bFM3_USB1_TMSP_TMSP0 *((volatile unsigned int*)(0x42A42780UL)) +#define bFM3_USB1_TMSP_TMSP1 *((volatile unsigned int*)(0x42A42784UL)) +#define bFM3_USB1_TMSP_TMSP2 *((volatile unsigned int*)(0x42A42788UL)) +#define bFM3_USB1_TMSP_TMSP3 *((volatile unsigned int*)(0x42A4278CUL)) +#define bFM3_USB1_TMSP_TMSP4 *((volatile unsigned int*)(0x42A42790UL)) +#define bFM3_USB1_TMSP_TMSP5 *((volatile unsigned int*)(0x42A42794UL)) +#define bFM3_USB1_TMSP_TMSP6 *((volatile unsigned int*)(0x42A42798UL)) +#define bFM3_USB1_TMSP_TMSP7 *((volatile unsigned int*)(0x42A4279CUL)) +#define bFM3_USB1_TMSP_TMSP8 *((volatile unsigned int*)(0x42A427A0UL)) +#define bFM3_USB1_TMSP_TMSP9 *((volatile unsigned int*)(0x42A427A4UL)) +#define bFM3_USB1_TMSP_TMSP10 *((volatile unsigned int*)(0x42A427A8UL)) +#define bFM3_USB1_UDCS_CONF *((volatile unsigned int*)(0x42A42800UL)) +#define bFM3_USB1_UDCS_SETP *((volatile unsigned int*)(0x42A42804UL)) +#define bFM3_USB1_UDCS_WKUP *((volatile unsigned int*)(0x42A42808UL)) +#define bFM3_USB1_UDCS_BRST *((volatile unsigned int*)(0x42A4280CUL)) +#define bFM3_USB1_UDCS_SOF *((volatile unsigned int*)(0x42A42810UL)) +#define bFM3_USB1_UDCS_SUSP *((volatile unsigned int*)(0x42A42814UL)) +#define bFM3_USB1_UDCIE_CONFIE *((volatile unsigned int*)(0x42A42820UL)) +#define bFM3_USB1_UDCIE_CONFN *((volatile unsigned int*)(0x42A42824UL)) +#define bFM3_USB1_UDCIE_WKUPIE *((volatile unsigned int*)(0x42A42828UL)) +#define bFM3_USB1_UDCIE_BRSTIE *((volatile unsigned int*)(0x42A4282CUL)) +#define bFM3_USB1_UDCIE_SOFIE *((volatile unsigned int*)(0x42A42830UL)) +#define bFM3_USB1_UDCIE_SUSPIE *((volatile unsigned int*)(0x42A42834UL)) +#define bFM3_USB1_EP0IS_DRQI *((volatile unsigned int*)(0x42A428A8UL)) +#define bFM3_USB1_EP0IS_DRQIIE *((volatile unsigned int*)(0x42A428B8UL)) +#define bFM3_USB1_EP0IS_BFINI *((volatile unsigned int*)(0x42A428BCUL)) +#define bFM3_USB1_EP0OS_SIZE0 *((volatile unsigned int*)(0x42A42900UL)) +#define bFM3_USB1_EP0OS_SIZE1 *((volatile unsigned int*)(0x42A42904UL)) +#define bFM3_USB1_EP0OS_SIZE2 *((volatile unsigned int*)(0x42A42908UL)) +#define bFM3_USB1_EP0OS_SIZE3 *((volatile unsigned int*)(0x42A4290CUL)) +#define bFM3_USB1_EP0OS_SIZE4 *((volatile unsigned int*)(0x42A42910UL)) +#define bFM3_USB1_EP0OS_SIZE5 *((volatile unsigned int*)(0x42A42914UL)) +#define bFM3_USB1_EP0OS_SIZE6 *((volatile unsigned int*)(0x42A42918UL)) +#define bFM3_USB1_EP0OS_SPK *((volatile unsigned int*)(0x42A42924UL)) +#define bFM3_USB1_EP0OS_DRQO *((volatile unsigned int*)(0x42A42928UL)) +#define bFM3_USB1_EP0OS_SPKIE *((volatile unsigned int*)(0x42A42934UL)) +#define bFM3_USB1_EP0OS_DRQOIE *((volatile unsigned int*)(0x42A42938UL)) +#define bFM3_USB1_EP0OS_BFINI *((volatile unsigned int*)(0x42A4293CUL)) +#define bFM3_USB1_EP1S_SIZE10 *((volatile unsigned int*)(0x42A42980UL)) +#define bFM3_USB1_EP1S_SIZE11 *((volatile unsigned int*)(0x42A42984UL)) +#define bFM3_USB1_EP1S_SIZE12 *((volatile unsigned int*)(0x42A42988UL)) +#define bFM3_USB1_EP1S_SIZE13 *((volatile unsigned int*)(0x42A4298CUL)) +#define bFM3_USB1_EP1S_SIZE14 *((volatile unsigned int*)(0x42A42990UL)) +#define bFM3_USB1_EP1S_SIZE15 *((volatile unsigned int*)(0x42A42994UL)) +#define bFM3_USB1_EP1S_SIZE16 *((volatile unsigned int*)(0x42A42998UL)) +#define bFM3_USB1_EP1S_SIZE17 *((volatile unsigned int*)(0x42A4299CUL)) +#define bFM3_USB1_EP1S_SIZE18 *((volatile unsigned int*)(0x42A429A0UL)) +#define bFM3_USB1_EP1S_SPK *((volatile unsigned int*)(0x42A429A4UL)) +#define bFM3_USB1_EP1S_DRQ *((volatile unsigned int*)(0x42A429A8UL)) +#define bFM3_USB1_EP1S_BUSY *((volatile unsigned int*)(0x42A429ACUL)) +#define bFM3_USB1_EP1S_SPKIE *((volatile unsigned int*)(0x42A429B4UL)) +#define bFM3_USB1_EP1S_DRQIE *((volatile unsigned int*)(0x42A429B8UL)) +#define bFM3_USB1_EP1S_BFINI *((volatile unsigned int*)(0x42A429BCUL)) +#define bFM3_USB1_EP2S_SIZE20 *((volatile unsigned int*)(0x42A42A00UL)) +#define bFM3_USB1_EP2S_SIZE21 *((volatile unsigned int*)(0x42A42A04UL)) +#define bFM3_USB1_EP2S_SIZE22 *((volatile unsigned int*)(0x42A42A08UL)) +#define bFM3_USB1_EP2S_SIZE23 *((volatile unsigned int*)(0x42A42A0CUL)) +#define bFM3_USB1_EP2S_SIZE24 *((volatile unsigned int*)(0x42A42A10UL)) +#define bFM3_USB1_EP2S_SIZE25 *((volatile unsigned int*)(0x42A42A14UL)) +#define bFM3_USB1_EP2S_SIZE26 *((volatile unsigned int*)(0x42A42A18UL)) +#define bFM3_USB1_EP2S_SPK *((volatile unsigned int*)(0x42A42A24UL)) +#define bFM3_USB1_EP2S_DRQ *((volatile unsigned int*)(0x42A42A28UL)) +#define bFM3_USB1_EP2S_BUSY *((volatile unsigned int*)(0x42A42A2CUL)) +#define bFM3_USB1_EP2S_SPKIE *((volatile unsigned int*)(0x42A42A34UL)) +#define bFM3_USB1_EP2S_DRQIE *((volatile unsigned int*)(0x42A42A38UL)) +#define bFM3_USB1_EP2S_BFINI *((volatile unsigned int*)(0x42A42A3CUL)) +#define bFM3_USB1_EP3S_SIZE30 *((volatile unsigned int*)(0x42A42A80UL)) +#define bFM3_USB1_EP3S_SIZE31 *((volatile unsigned int*)(0x42A42A84UL)) +#define bFM3_USB1_EP3S_SIZE32 *((volatile unsigned int*)(0x42A42A88UL)) +#define bFM3_USB1_EP3S_SIZE33 *((volatile unsigned int*)(0x42A42A8CUL)) +#define bFM3_USB1_EP3S_SIZE34 *((volatile unsigned int*)(0x42A42A90UL)) +#define bFM3_USB1_EP3S_SIZE35 *((volatile unsigned int*)(0x42A42A94UL)) +#define bFM3_USB1_EP3S_SIZE36 *((volatile unsigned int*)(0x42A42A98UL)) +#define bFM3_USB1_EP3S_SPK *((volatile unsigned int*)(0x42A42AA4UL)) +#define bFM3_USB1_EP3S_DRQ *((volatile unsigned int*)(0x42A42AA8UL)) +#define bFM3_USB1_EP3S_BUSY *((volatile unsigned int*)(0x42A42AACUL)) +#define bFM3_USB1_EP3S_SPKIE *((volatile unsigned int*)(0x42A42AB4UL)) +#define bFM3_USB1_EP3S_DRQIE *((volatile unsigned int*)(0x42A42AB8UL)) +#define bFM3_USB1_EP3S_BFINI *((volatile unsigned int*)(0x42A42ABCUL)) +#define bFM3_USB1_EP4S_SIZE40 *((volatile unsigned int*)(0x42A42B00UL)) +#define bFM3_USB1_EP4S_SIZE41 *((volatile unsigned int*)(0x42A42B04UL)) +#define bFM3_USB1_EP4S_SIZE42 *((volatile unsigned int*)(0x42A42B08UL)) +#define bFM3_USB1_EP4S_SIZE43 *((volatile unsigned int*)(0x42A42B0CUL)) +#define bFM3_USB1_EP4S_SIZE44 *((volatile unsigned int*)(0x42A42B10UL)) +#define bFM3_USB1_EP4S_SIZE45 *((volatile unsigned int*)(0x42A42B14UL)) +#define bFM3_USB1_EP4S_SIZE46 *((volatile unsigned int*)(0x42A42B18UL)) +#define bFM3_USB1_EP4S_SPK *((volatile unsigned int*)(0x42A42B24UL)) +#define bFM3_USB1_EP4S_DRQ *((volatile unsigned int*)(0x42A42B28UL)) +#define bFM3_USB1_EP4S_BUSY *((volatile unsigned int*)(0x42A42B2CUL)) +#define bFM3_USB1_EP4S_SPKIE *((volatile unsigned int*)(0x42A42B34UL)) +#define bFM3_USB1_EP4S_DRQIE *((volatile unsigned int*)(0x42A42B38UL)) +#define bFM3_USB1_EP4S_BFINI *((volatile unsigned int*)(0x42A42B3CUL)) +#define bFM3_USB1_EP5S_SIZE50 *((volatile unsigned int*)(0x42A42B80UL)) +#define bFM3_USB1_EP5S_SIZE51 *((volatile unsigned int*)(0x42A42B84UL)) +#define bFM3_USB1_EP5S_SIZE52 *((volatile unsigned int*)(0x42A42B88UL)) +#define bFM3_USB1_EP5S_SIZE53 *((volatile unsigned int*)(0x42A42B8CUL)) +#define bFM3_USB1_EP5S_SIZE54 *((volatile unsigned int*)(0x42A42B90UL)) +#define bFM3_USB1_EP5S_SIZE55 *((volatile unsigned int*)(0x42A42B94UL)) +#define bFM3_USB1_EP5S_SIZE56 *((volatile unsigned int*)(0x42A42B98UL)) +#define bFM3_USB1_EP5S_SPK *((volatile unsigned int*)(0x42A42BA4UL)) +#define bFM3_USB1_EP5S_DRQ *((volatile unsigned int*)(0x42A42BA8UL)) +#define bFM3_USB1_EP5S_BUSY *((volatile unsigned int*)(0x42A42BACUL)) +#define bFM3_USB1_EP5S_SPKIE *((volatile unsigned int*)(0x42A42BB4UL)) +#define bFM3_USB1_EP5S_DRQIE *((volatile unsigned int*)(0x42A42BB8UL)) +#define bFM3_USB1_EP5S_BFINI *((volatile unsigned int*)(0x42A42BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* ETHERNET-MAC0 registers*/ +#define bFM3_ETHERNET_MAC0_MCR_RE *((volatile unsigned int*)(0x42C80008UL)) +#define bFM3_ETHERNET_MAC0_MCR_TE *((volatile unsigned int*)(0x42C8000CUL)) +#define bFM3_ETHERNET_MAC0_MCR_DC *((volatile unsigned int*)(0x42C80010UL)) +#define bFM3_ETHERNET_MAC0_MCR_BL0 *((volatile unsigned int*)(0x42C80014UL)) +#define bFM3_ETHERNET_MAC0_MCR_BL1 *((volatile unsigned int*)(0x42C80018UL)) +#define bFM3_ETHERNET_MAC0_MCR_ACS *((volatile unsigned int*)(0x42C8001CUL)) +#define bFM3_ETHERNET_MAC0_MCR_LUD *((volatile unsigned int*)(0x42C80020UL)) +#define bFM3_ETHERNET_MAC0_MCR_DR *((volatile unsigned int*)(0x42C80024UL)) +#define bFM3_ETHERNET_MAC0_MCR_IPC *((volatile unsigned int*)(0x42C80028UL)) +#define bFM3_ETHERNET_MAC0_MCR_DM *((volatile unsigned int*)(0x42C8002CUL)) +#define bFM3_ETHERNET_MAC0_MCR_LM *((volatile unsigned int*)(0x42C80030UL)) +#define bFM3_ETHERNET_MAC0_MCR_DO *((volatile unsigned int*)(0x42C80034UL)) +#define bFM3_ETHERNET_MAC0_MCR_FES *((volatile unsigned int*)(0x42C80038UL)) +#define bFM3_ETHERNET_MAC0_MCR_PS *((volatile unsigned int*)(0x42C8003CUL)) +#define bFM3_ETHERNET_MAC0_MCR_DCRS *((volatile unsigned int*)(0x42C80040UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG0 *((volatile unsigned int*)(0x42C80044UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG1 *((volatile unsigned int*)(0x42C80048UL)) +#define bFM3_ETHERNET_MAC0_MCR_IFG2 *((volatile unsigned int*)(0x42C8004CUL)) +#define bFM3_ETHERNET_MAC0_MCR_JE *((volatile unsigned int*)(0x42C80050UL)) +#define bFM3_ETHERNET_MAC0_MCR_BE *((volatile unsigned int*)(0x42C80054UL)) +#define bFM3_ETHERNET_MAC0_MCR_JD *((volatile unsigned int*)(0x42C80058UL)) +#define bFM3_ETHERNET_MAC0_MCR_WD *((volatile unsigned int*)(0x42C8005CUL)) +#define bFM3_ETHERNET_MAC0_MCR_TC *((volatile unsigned int*)(0x42C80060UL)) +#define bFM3_ETHERNET_MAC0_MCR_CST *((volatile unsigned int*)(0x42C80064UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PR *((volatile unsigned int*)(0x42C80080UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HUC *((volatile unsigned int*)(0x42C80084UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HMC *((volatile unsigned int*)(0x42C80088UL)) +#define bFM3_ETHERNET_MAC0_MFFR_DAIF *((volatile unsigned int*)(0x42C8008CUL)) +#define bFM3_ETHERNET_MAC0_MFFR_PM *((volatile unsigned int*)(0x42C80090UL)) +#define bFM3_ETHERNET_MAC0_MFFR_DB *((volatile unsigned int*)(0x42C80094UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PCF0 *((volatile unsigned int*)(0x42C80098UL)) +#define bFM3_ETHERNET_MAC0_MFFR_PCF1 *((volatile unsigned int*)(0x42C8009CUL)) +#define bFM3_ETHERNET_MAC0_MFFR_SAIF *((volatile unsigned int*)(0x42C800A0UL)) +#define bFM3_ETHERNET_MAC0_MFFR_SAF *((volatile unsigned int*)(0x42C800A4UL)) +#define bFM3_ETHERNET_MAC0_MFFR_HPF *((volatile unsigned int*)(0x42C800A8UL)) +#define bFM3_ETHERNET_MAC0_MFFR_RA *((volatile unsigned int*)(0x42C800FCUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH0 *((volatile unsigned int*)(0x42C80100UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH1 *((volatile unsigned int*)(0x42C80104UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH2 *((volatile unsigned int*)(0x42C80108UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH3 *((volatile unsigned int*)(0x42C8010CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH4 *((volatile unsigned int*)(0x42C80110UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH5 *((volatile unsigned int*)(0x42C80114UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH6 *((volatile unsigned int*)(0x42C80118UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH7 *((volatile unsigned int*)(0x42C8011CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH8 *((volatile unsigned int*)(0x42C80120UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH9 *((volatile unsigned int*)(0x42C80124UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH10 *((volatile unsigned int*)(0x42C80128UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH11 *((volatile unsigned int*)(0x42C8012CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH12 *((volatile unsigned int*)(0x42C80130UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH13 *((volatile unsigned int*)(0x42C80134UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH14 *((volatile unsigned int*)(0x42C80138UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH15 *((volatile unsigned int*)(0x42C8013CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH16 *((volatile unsigned int*)(0x42C80140UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH17 *((volatile unsigned int*)(0x42C80144UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH18 *((volatile unsigned int*)(0x42C80148UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH19 *((volatile unsigned int*)(0x42C8014CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH20 *((volatile unsigned int*)(0x42C80150UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH21 *((volatile unsigned int*)(0x42C80154UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH22 *((volatile unsigned int*)(0x42C80158UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH23 *((volatile unsigned int*)(0x42C8015CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH24 *((volatile unsigned int*)(0x42C80160UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH25 *((volatile unsigned int*)(0x42C80164UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH26 *((volatile unsigned int*)(0x42C80168UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH27 *((volatile unsigned int*)(0x42C8016CUL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH28 *((volatile unsigned int*)(0x42C80170UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH29 *((volatile unsigned int*)(0x42C80174UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH30 *((volatile unsigned int*)(0x42C80178UL)) +#define bFM3_ETHERNET_MAC0_MHTRH_HTH31 *((volatile unsigned int*)(0x42C8017CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL0 *((volatile unsigned int*)(0x42C80180UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL1 *((volatile unsigned int*)(0x42C80184UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL2 *((volatile unsigned int*)(0x42C80188UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL3 *((volatile unsigned int*)(0x42C8018CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL4 *((volatile unsigned int*)(0x42C80190UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL5 *((volatile unsigned int*)(0x42C80194UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL6 *((volatile unsigned int*)(0x42C80198UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL7 *((volatile unsigned int*)(0x42C8019CUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL8 *((volatile unsigned int*)(0x42C801A0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL9 *((volatile unsigned int*)(0x42C801A4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL10 *((volatile unsigned int*)(0x42C801A8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL11 *((volatile unsigned int*)(0x42C801ACUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL12 *((volatile unsigned int*)(0x42C801B0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL13 *((volatile unsigned int*)(0x42C801B4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL14 *((volatile unsigned int*)(0x42C801B8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL15 *((volatile unsigned int*)(0x42C801BCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL16 *((volatile unsigned int*)(0x42C801C0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL17 *((volatile unsigned int*)(0x42C801C4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL18 *((volatile unsigned int*)(0x42C801C8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL19 *((volatile unsigned int*)(0x42C801CCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL20 *((volatile unsigned int*)(0x42C801D0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL21 *((volatile unsigned int*)(0x42C801D4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL22 *((volatile unsigned int*)(0x42C801D8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL23 *((volatile unsigned int*)(0x42C801DCUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL24 *((volatile unsigned int*)(0x42C801E0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL25 *((volatile unsigned int*)(0x42C801E4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL26 *((volatile unsigned int*)(0x42C801E8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL27 *((volatile unsigned int*)(0x42C801ECUL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL28 *((volatile unsigned int*)(0x42C801F0UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL29 *((volatile unsigned int*)(0x42C801F4UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL30 *((volatile unsigned int*)(0x42C801F8UL)) +#define bFM3_ETHERNET_MAC0_MHTRL_HTL31 *((volatile unsigned int*)(0x42C801FCUL)) +#define bFM3_ETHERNET_MAC0_GAR_GB *((volatile unsigned int*)(0x42C80200UL)) +#define bFM3_ETHERNET_MAC0_GAR_GW *((volatile unsigned int*)(0x42C80204UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR0 *((volatile unsigned int*)(0x42C80208UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR1 *((volatile unsigned int*)(0x42C8020CUL)) +#define bFM3_ETHERNET_MAC0_GAR_CR2 *((volatile unsigned int*)(0x42C80210UL)) +#define bFM3_ETHERNET_MAC0_GAR_CR3 *((volatile unsigned int*)(0x42C80214UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR0 *((volatile unsigned int*)(0x42C80218UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR1 *((volatile unsigned int*)(0x42C8021CUL)) +#define bFM3_ETHERNET_MAC0_GAR_GR2 *((volatile unsigned int*)(0x42C80220UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR3 *((volatile unsigned int*)(0x42C80224UL)) +#define bFM3_ETHERNET_MAC0_GAR_GR4 *((volatile unsigned int*)(0x42C80228UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA0 *((volatile unsigned int*)(0x42C8022CUL)) +#define bFM3_ETHERNET_MAC0_GAR_PA1 *((volatile unsigned int*)(0x42C80230UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA2 *((volatile unsigned int*)(0x42C80234UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA3 *((volatile unsigned int*)(0x42C80238UL)) +#define bFM3_ETHERNET_MAC0_GAR_PA4 *((volatile unsigned int*)(0x42C8023CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD0 *((volatile unsigned int*)(0x42C80280UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD1 *((volatile unsigned int*)(0x42C80284UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD2 *((volatile unsigned int*)(0x42C80288UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD3 *((volatile unsigned int*)(0x42C8028CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD4 *((volatile unsigned int*)(0x42C80290UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD5 *((volatile unsigned int*)(0x42C80294UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD6 *((volatile unsigned int*)(0x42C80298UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD7 *((volatile unsigned int*)(0x42C8029CUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD8 *((volatile unsigned int*)(0x42C802A0UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD9 *((volatile unsigned int*)(0x42C802A4UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD10 *((volatile unsigned int*)(0x42C802A8UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD11 *((volatile unsigned int*)(0x42C802ACUL)) +#define bFM3_ETHERNET_MAC0_GDR_GD12 *((volatile unsigned int*)(0x42C802B0UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD13 *((volatile unsigned int*)(0x42C802B4UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD14 *((volatile unsigned int*)(0x42C802B8UL)) +#define bFM3_ETHERNET_MAC0_GDR_GD15 *((volatile unsigned int*)(0x42C802BCUL)) +#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA *((volatile unsigned int*)(0x42C80300UL)) +#define bFM3_ETHERNET_MAC0_FCR_TFE *((volatile unsigned int*)(0x42C80304UL)) +#define bFM3_ETHERNET_MAC0_FCR_RFE *((volatile unsigned int*)(0x42C80308UL)) +#define bFM3_ETHERNET_MAC0_FCR_UP *((volatile unsigned int*)(0x42C8030CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PLT0 *((volatile unsigned int*)(0x42C80310UL)) +#define bFM3_ETHERNET_MAC0_FCR_PLT1 *((volatile unsigned int*)(0x42C80314UL)) +#define bFM3_ETHERNET_MAC0_FCR_DZPQ *((volatile unsigned int*)(0x42C8031CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT0 *((volatile unsigned int*)(0x42C80340UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT1 *((volatile unsigned int*)(0x42C80344UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT2 *((volatile unsigned int*)(0x42C80348UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT3 *((volatile unsigned int*)(0x42C8034CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT4 *((volatile unsigned int*)(0x42C80350UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT5 *((volatile unsigned int*)(0x42C80354UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT6 *((volatile unsigned int*)(0x42C80358UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT7 *((volatile unsigned int*)(0x42C8035CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT8 *((volatile unsigned int*)(0x42C80360UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT9 *((volatile unsigned int*)(0x42C80364UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT10 *((volatile unsigned int*)(0x42C80368UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT11 *((volatile unsigned int*)(0x42C8036CUL)) +#define bFM3_ETHERNET_MAC0_FCR_PT12 *((volatile unsigned int*)(0x42C80370UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT13 *((volatile unsigned int*)(0x42C80374UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT14 *((volatile unsigned int*)(0x42C80378UL)) +#define bFM3_ETHERNET_MAC0_FCR_PT15 *((volatile unsigned int*)(0x42C8037CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL0 *((volatile unsigned int*)(0x42C80380UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL1 *((volatile unsigned int*)(0x42C80384UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL2 *((volatile unsigned int*)(0x42C80388UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL3 *((volatile unsigned int*)(0x42C8038CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL4 *((volatile unsigned int*)(0x42C80390UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL5 *((volatile unsigned int*)(0x42C80394UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL6 *((volatile unsigned int*)(0x42C80398UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL7 *((volatile unsigned int*)(0x42C8039CUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL8 *((volatile unsigned int*)(0x42C803A0UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL9 *((volatile unsigned int*)(0x42C803A4UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL10 *((volatile unsigned int*)(0x42C803A8UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL11 *((volatile unsigned int*)(0x42C803ACUL)) +#define bFM3_ETHERNET_MAC0_VTR_VL12 *((volatile unsigned int*)(0x42C803B0UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL13 *((volatile unsigned int*)(0x42C803B4UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL14 *((volatile unsigned int*)(0x42C803B8UL)) +#define bFM3_ETHERNET_MAC0_VTR_VL15 *((volatile unsigned int*)(0x42C803BCUL)) +#define bFM3_ETHERNET_MAC0_VTR_ETV *((volatile unsigned int*)(0x42C803C0UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42C80500UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42C80504UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42C80508UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42C8050CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42C80510UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42C80514UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42C80518UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42C8051CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42C80520UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42C80524UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42C80528UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42C8052CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42C80530UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42C80534UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42C80538UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42C8053CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42C80540UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42C80544UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42C80548UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42C8054CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42C80550UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42C80554UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42C80558UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42C8055CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42C80560UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42C80564UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42C80568UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42C8056CUL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42C80570UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42C80574UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42C80578UL)) +#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42C8057CUL)) +#define bFM3_ETHERNET_MAC0_PMTR_PD *((volatile unsigned int*)(0x42C80580UL)) +#define bFM3_ETHERNET_MAC0_PMTR_MPE *((volatile unsigned int*)(0x42C80584UL)) +#define bFM3_ETHERNET_MAC0_PMTR_WFE *((volatile unsigned int*)(0x42C80588UL)) +#define bFM3_ETHERNET_MAC0_PMTR_MPR *((volatile unsigned int*)(0x42C80594UL)) +#define bFM3_ETHERNET_MAC0_PMTR_WPR *((volatile unsigned int*)(0x42C80598UL)) +#define bFM3_ETHERNET_MAC0_PMTR_GU *((volatile unsigned int*)(0x42C805A4UL)) +#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR *((volatile unsigned int*)(0x42C805FCUL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN *((volatile unsigned int*)(0x42C80600UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX *((volatile unsigned int*)(0x42C80604UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN *((volatile unsigned int*)(0x42C80608UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX *((volatile unsigned int*)(0x42C8060CUL)) +#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST *((volatile unsigned int*)(0x42C80620UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST *((volatile unsigned int*)(0x42C80624UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN *((volatile unsigned int*)(0x42C80640UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_PLS *((volatile unsigned int*)(0x42C80644UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN *((volatile unsigned int*)(0x42C80648UL)) +#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA *((volatile unsigned int*)(0x42C8064CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT0 *((volatile unsigned int*)(0x42C80680UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT1 *((volatile unsigned int*)(0x42C80684UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT2 *((volatile unsigned int*)(0x42C80688UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT3 *((volatile unsigned int*)(0x42C8068CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT4 *((volatile unsigned int*)(0x42C80690UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT5 *((volatile unsigned int*)(0x42C80694UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT6 *((volatile unsigned int*)(0x42C80698UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT7 *((volatile unsigned int*)(0x42C8069CUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT8 *((volatile unsigned int*)(0x42C806A0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT9 *((volatile unsigned int*)(0x42C806A4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT10 *((volatile unsigned int*)(0x42C806A8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT11 *((volatile unsigned int*)(0x42C806ACUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT12 *((volatile unsigned int*)(0x42C806B0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT13 *((volatile unsigned int*)(0x42C806B4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT14 *((volatile unsigned int*)(0x42C806B8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_TWT15 *((volatile unsigned int*)(0x42C806BCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT0 *((volatile unsigned int*)(0x42C806C0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT1 *((volatile unsigned int*)(0x42C806C4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT2 *((volatile unsigned int*)(0x42C806C8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT3 *((volatile unsigned int*)(0x42C806CCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT4 *((volatile unsigned int*)(0x42C806D0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT5 *((volatile unsigned int*)(0x42C806D4UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT6 *((volatile unsigned int*)(0x42C806D8UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT7 *((volatile unsigned int*)(0x42C806DCUL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT8 *((volatile unsigned int*)(0x42C806E0UL)) +#define bFM3_ETHERNET_MAC0_LPITCR_LIT9 *((volatile unsigned int*)(0x42C806E4UL)) +#define bFM3_ETHERNET_MAC0_ISR_RGIS *((volatile unsigned int*)(0x42C80700UL)) +#define bFM3_ETHERNET_MAC0_ISR_PIS *((volatile unsigned int*)(0x42C8070CUL)) +#define bFM3_ETHERNET_MAC0_ISR_MIS *((volatile unsigned int*)(0x42C80710UL)) +#define bFM3_ETHERNET_MAC0_ISR_RIS *((volatile unsigned int*)(0x42C80714UL)) +#define bFM3_ETHERNET_MAC0_ISR_TIS *((volatile unsigned int*)(0x42C80718UL)) +#define bFM3_ETHERNET_MAC0_ISR_COIS *((volatile unsigned int*)(0x42C8071CUL)) +#define bFM3_ETHERNET_MAC0_ISR_TSIS *((volatile unsigned int*)(0x42C80724UL)) +#define bFM3_ETHERNET_MAC0_ISR_LPIIS *((volatile unsigned int*)(0x42C80728UL)) +#define bFM3_ETHERNET_MAC0_IMR_RGIM *((volatile unsigned int*)(0x42C80780UL)) +#define bFM3_ETHERNET_MAC0_IMR_PIM *((volatile unsigned int*)(0x42C8078CUL)) +#define bFM3_ETHERNET_MAC0_IMR_TSIM *((volatile unsigned int*)(0x42C80794UL)) +#define bFM3_ETHERNET_MAC0_IMR_LPIIM *((volatile unsigned int*)(0x42C80798UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A32 *((volatile unsigned int*)(0x42C80800UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A33 *((volatile unsigned int*)(0x42C80804UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A34 *((volatile unsigned int*)(0x42C80808UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A35 *((volatile unsigned int*)(0x42C8080CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A36 *((volatile unsigned int*)(0x42C80810UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A37 *((volatile unsigned int*)(0x42C80814UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A38 *((volatile unsigned int*)(0x42C80818UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A39 *((volatile unsigned int*)(0x42C8081CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A40 *((volatile unsigned int*)(0x42C80820UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A41 *((volatile unsigned int*)(0x42C80824UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A42 *((volatile unsigned int*)(0x42C80828UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A43 *((volatile unsigned int*)(0x42C8082CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A44 *((volatile unsigned int*)(0x42C80830UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A45 *((volatile unsigned int*)(0x42C80834UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A46 *((volatile unsigned int*)(0x42C80838UL)) +#define bFM3_ETHERNET_MAC0_MAR0H_A47 *((volatile unsigned int*)(0x42C8083CUL)) +#define bFM3_ETHERNET_MAC0_MAR0H_MO *((volatile unsigned int*)(0x42C8087CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A0 *((volatile unsigned int*)(0x42C80880UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A1 *((volatile unsigned int*)(0x42C80884UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A2 *((volatile unsigned int*)(0x42C80888UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A3 *((volatile unsigned int*)(0x42C8088CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A4 *((volatile unsigned int*)(0x42C80890UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A5 *((volatile unsigned int*)(0x42C80894UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A6 *((volatile unsigned int*)(0x42C80898UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A7 *((volatile unsigned int*)(0x42C8089CUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A8 *((volatile unsigned int*)(0x42C808A0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A9 *((volatile unsigned int*)(0x42C808A4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A10 *((volatile unsigned int*)(0x42C808A8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A11 *((volatile unsigned int*)(0x42C808ACUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A12 *((volatile unsigned int*)(0x42C808B0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A13 *((volatile unsigned int*)(0x42C808B4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A14 *((volatile unsigned int*)(0x42C808B8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A15 *((volatile unsigned int*)(0x42C808BCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A16 *((volatile unsigned int*)(0x42C808C0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A17 *((volatile unsigned int*)(0x42C808C4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A18 *((volatile unsigned int*)(0x42C808C8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A19 *((volatile unsigned int*)(0x42C808CCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A20 *((volatile unsigned int*)(0x42C808D0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A21 *((volatile unsigned int*)(0x42C808D4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A22 *((volatile unsigned int*)(0x42C808D8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A23 *((volatile unsigned int*)(0x42C808DCUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A24 *((volatile unsigned int*)(0x42C808E0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A25 *((volatile unsigned int*)(0x42C808E4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A26 *((volatile unsigned int*)(0x42C808E8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A27 *((volatile unsigned int*)(0x42C808ECUL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A28 *((volatile unsigned int*)(0x42C808F0UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A29 *((volatile unsigned int*)(0x42C808F4UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A30 *((volatile unsigned int*)(0x42C808F8UL)) +#define bFM3_ETHERNET_MAC0_MAR0L_A31 *((volatile unsigned int*)(0x42C808FCUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A32 *((volatile unsigned int*)(0x42C80900UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A33 *((volatile unsigned int*)(0x42C80904UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A34 *((volatile unsigned int*)(0x42C80908UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A35 *((volatile unsigned int*)(0x42C8090CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A36 *((volatile unsigned int*)(0x42C80910UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A37 *((volatile unsigned int*)(0x42C80914UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A38 *((volatile unsigned int*)(0x42C80918UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A39 *((volatile unsigned int*)(0x42C8091CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A40 *((volatile unsigned int*)(0x42C80920UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A41 *((volatile unsigned int*)(0x42C80924UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A42 *((volatile unsigned int*)(0x42C80928UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A43 *((volatile unsigned int*)(0x42C8092CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A44 *((volatile unsigned int*)(0x42C80930UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A45 *((volatile unsigned int*)(0x42C80934UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A46 *((volatile unsigned int*)(0x42C80938UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_A47 *((volatile unsigned int*)(0x42C8093CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC0 *((volatile unsigned int*)(0x42C80960UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC1 *((volatile unsigned int*)(0x42C80964UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC2 *((volatile unsigned int*)(0x42C80968UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC3 *((volatile unsigned int*)(0x42C8096CUL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC4 *((volatile unsigned int*)(0x42C80970UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_MBC5 *((volatile unsigned int*)(0x42C80974UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_SA *((volatile unsigned int*)(0x42C80978UL)) +#define bFM3_ETHERNET_MAC0_MAR1H_AE *((volatile unsigned int*)(0x42C8097CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A0 *((volatile unsigned int*)(0x42C80980UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A1 *((volatile unsigned int*)(0x42C80984UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A2 *((volatile unsigned int*)(0x42C80988UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A3 *((volatile unsigned int*)(0x42C8098CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A4 *((volatile unsigned int*)(0x42C80990UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A5 *((volatile unsigned int*)(0x42C80994UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A6 *((volatile unsigned int*)(0x42C80998UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A7 *((volatile unsigned int*)(0x42C8099CUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A8 *((volatile unsigned int*)(0x42C809A0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A9 *((volatile unsigned int*)(0x42C809A4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A10 *((volatile unsigned int*)(0x42C809A8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A11 *((volatile unsigned int*)(0x42C809ACUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A12 *((volatile unsigned int*)(0x42C809B0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A13 *((volatile unsigned int*)(0x42C809B4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A14 *((volatile unsigned int*)(0x42C809B8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A15 *((volatile unsigned int*)(0x42C809BCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A16 *((volatile unsigned int*)(0x42C809C0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A17 *((volatile unsigned int*)(0x42C809C4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A18 *((volatile unsigned int*)(0x42C809C8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A19 *((volatile unsigned int*)(0x42C809CCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A20 *((volatile unsigned int*)(0x42C809D0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A21 *((volatile unsigned int*)(0x42C809D4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A22 *((volatile unsigned int*)(0x42C809D8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A23 *((volatile unsigned int*)(0x42C809DCUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A24 *((volatile unsigned int*)(0x42C809E0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A25 *((volatile unsigned int*)(0x42C809E4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A26 *((volatile unsigned int*)(0x42C809E8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A27 *((volatile unsigned int*)(0x42C809ECUL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A28 *((volatile unsigned int*)(0x42C809F0UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A29 *((volatile unsigned int*)(0x42C809F4UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A30 *((volatile unsigned int*)(0x42C809F8UL)) +#define bFM3_ETHERNET_MAC0_MAR1L_A31 *((volatile unsigned int*)(0x42C809FCUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A32 *((volatile unsigned int*)(0x42C80A00UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A33 *((volatile unsigned int*)(0x42C80A04UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A34 *((volatile unsigned int*)(0x42C80A08UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A35 *((volatile unsigned int*)(0x42C80A0CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A36 *((volatile unsigned int*)(0x42C80A10UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A37 *((volatile unsigned int*)(0x42C80A14UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A38 *((volatile unsigned int*)(0x42C80A18UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A39 *((volatile unsigned int*)(0x42C80A1CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A40 *((volatile unsigned int*)(0x42C80A20UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A41 *((volatile unsigned int*)(0x42C80A24UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A42 *((volatile unsigned int*)(0x42C80A28UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A43 *((volatile unsigned int*)(0x42C80A2CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A44 *((volatile unsigned int*)(0x42C80A30UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A45 *((volatile unsigned int*)(0x42C80A34UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A46 *((volatile unsigned int*)(0x42C80A38UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_A47 *((volatile unsigned int*)(0x42C80A3CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC0 *((volatile unsigned int*)(0x42C80A60UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC1 *((volatile unsigned int*)(0x42C80A64UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC2 *((volatile unsigned int*)(0x42C80A68UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC3 *((volatile unsigned int*)(0x42C80A6CUL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC4 *((volatile unsigned int*)(0x42C80A70UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_MBC5 *((volatile unsigned int*)(0x42C80A74UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_SA *((volatile unsigned int*)(0x42C80A78UL)) +#define bFM3_ETHERNET_MAC0_MAR2H_AE *((volatile unsigned int*)(0x42C80A7CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A0 *((volatile unsigned int*)(0x42C80A80UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A1 *((volatile unsigned int*)(0x42C80A84UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A2 *((volatile unsigned int*)(0x42C80A88UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A3 *((volatile unsigned int*)(0x42C80A8CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A4 *((volatile unsigned int*)(0x42C80A90UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A5 *((volatile unsigned int*)(0x42C80A94UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A6 *((volatile unsigned int*)(0x42C80A98UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A7 *((volatile unsigned int*)(0x42C80A9CUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A8 *((volatile unsigned int*)(0x42C80AA0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A9 *((volatile unsigned int*)(0x42C80AA4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A10 *((volatile unsigned int*)(0x42C80AA8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A11 *((volatile unsigned int*)(0x42C80AACUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A12 *((volatile unsigned int*)(0x42C80AB0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A13 *((volatile unsigned int*)(0x42C80AB4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A14 *((volatile unsigned int*)(0x42C80AB8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A15 *((volatile unsigned int*)(0x42C80ABCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A16 *((volatile unsigned int*)(0x42C80AC0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A17 *((volatile unsigned int*)(0x42C80AC4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A18 *((volatile unsigned int*)(0x42C80AC8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A19 *((volatile unsigned int*)(0x42C80ACCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A20 *((volatile unsigned int*)(0x42C80AD0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A21 *((volatile unsigned int*)(0x42C80AD4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A22 *((volatile unsigned int*)(0x42C80AD8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A23 *((volatile unsigned int*)(0x42C80ADCUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A24 *((volatile unsigned int*)(0x42C80AE0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A25 *((volatile unsigned int*)(0x42C80AE4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A26 *((volatile unsigned int*)(0x42C80AE8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A27 *((volatile unsigned int*)(0x42C80AECUL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A28 *((volatile unsigned int*)(0x42C80AF0UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A29 *((volatile unsigned int*)(0x42C80AF4UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A30 *((volatile unsigned int*)(0x42C80AF8UL)) +#define bFM3_ETHERNET_MAC0_MAR2L_A31 *((volatile unsigned int*)(0x42C80AFCUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A32 *((volatile unsigned int*)(0x42C80B00UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A33 *((volatile unsigned int*)(0x42C80B04UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A34 *((volatile unsigned int*)(0x42C80B08UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A35 *((volatile unsigned int*)(0x42C80B0CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A36 *((volatile unsigned int*)(0x42C80B10UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A37 *((volatile unsigned int*)(0x42C80B14UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A38 *((volatile unsigned int*)(0x42C80B18UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A39 *((volatile unsigned int*)(0x42C80B1CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A40 *((volatile unsigned int*)(0x42C80B20UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A41 *((volatile unsigned int*)(0x42C80B24UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A42 *((volatile unsigned int*)(0x42C80B28UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A43 *((volatile unsigned int*)(0x42C80B2CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A44 *((volatile unsigned int*)(0x42C80B30UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A45 *((volatile unsigned int*)(0x42C80B34UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A46 *((volatile unsigned int*)(0x42C80B38UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_A47 *((volatile unsigned int*)(0x42C80B3CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC0 *((volatile unsigned int*)(0x42C80B60UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC1 *((volatile unsigned int*)(0x42C80B64UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC2 *((volatile unsigned int*)(0x42C80B68UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC3 *((volatile unsigned int*)(0x42C80B6CUL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC4 *((volatile unsigned int*)(0x42C80B70UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_MBC5 *((volatile unsigned int*)(0x42C80B74UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_SA *((volatile unsigned int*)(0x42C80B78UL)) +#define bFM3_ETHERNET_MAC0_MAR3H_AE *((volatile unsigned int*)(0x42C80B7CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A0 *((volatile unsigned int*)(0x42C80B80UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A1 *((volatile unsigned int*)(0x42C80B84UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A2 *((volatile unsigned int*)(0x42C80B88UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A3 *((volatile unsigned int*)(0x42C80B8CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A4 *((volatile unsigned int*)(0x42C80B90UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A5 *((volatile unsigned int*)(0x42C80B94UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A6 *((volatile unsigned int*)(0x42C80B98UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A7 *((volatile unsigned int*)(0x42C80B9CUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A8 *((volatile unsigned int*)(0x42C80BA0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A9 *((volatile unsigned int*)(0x42C80BA4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A10 *((volatile unsigned int*)(0x42C80BA8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A11 *((volatile unsigned int*)(0x42C80BACUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A12 *((volatile unsigned int*)(0x42C80BB0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A13 *((volatile unsigned int*)(0x42C80BB4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A14 *((volatile unsigned int*)(0x42C80BB8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A15 *((volatile unsigned int*)(0x42C80BBCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A16 *((volatile unsigned int*)(0x42C80BC0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A17 *((volatile unsigned int*)(0x42C80BC4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A18 *((volatile unsigned int*)(0x42C80BC8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A19 *((volatile unsigned int*)(0x42C80BCCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A20 *((volatile unsigned int*)(0x42C80BD0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A21 *((volatile unsigned int*)(0x42C80BD4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A22 *((volatile unsigned int*)(0x42C80BD8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A23 *((volatile unsigned int*)(0x42C80BDCUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A24 *((volatile unsigned int*)(0x42C80BE0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A25 *((volatile unsigned int*)(0x42C80BE4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A26 *((volatile unsigned int*)(0x42C80BE8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A27 *((volatile unsigned int*)(0x42C80BECUL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A28 *((volatile unsigned int*)(0x42C80BF0UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A29 *((volatile unsigned int*)(0x42C80BF4UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A30 *((volatile unsigned int*)(0x42C80BF8UL)) +#define bFM3_ETHERNET_MAC0_MAR3L_A31 *((volatile unsigned int*)(0x42C80BFCUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A32 *((volatile unsigned int*)(0x42C80C00UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A33 *((volatile unsigned int*)(0x42C80C04UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A34 *((volatile unsigned int*)(0x42C80C08UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A35 *((volatile unsigned int*)(0x42C80C0CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A36 *((volatile unsigned int*)(0x42C80C10UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A37 *((volatile unsigned int*)(0x42C80C14UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A38 *((volatile unsigned int*)(0x42C80C18UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A39 *((volatile unsigned int*)(0x42C80C1CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A40 *((volatile unsigned int*)(0x42C80C20UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A41 *((volatile unsigned int*)(0x42C80C24UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A42 *((volatile unsigned int*)(0x42C80C28UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A43 *((volatile unsigned int*)(0x42C80C2CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A44 *((volatile unsigned int*)(0x42C80C30UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A45 *((volatile unsigned int*)(0x42C80C34UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A46 *((volatile unsigned int*)(0x42C80C38UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_A47 *((volatile unsigned int*)(0x42C80C3CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC0 *((volatile unsigned int*)(0x42C80C60UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC1 *((volatile unsigned int*)(0x42C80C64UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC2 *((volatile unsigned int*)(0x42C80C68UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC3 *((volatile unsigned int*)(0x42C80C6CUL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC4 *((volatile unsigned int*)(0x42C80C70UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_MBC5 *((volatile unsigned int*)(0x42C80C74UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_SA *((volatile unsigned int*)(0x42C80C78UL)) +#define bFM3_ETHERNET_MAC0_MAR4H_AE *((volatile unsigned int*)(0x42C80C7CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A0 *((volatile unsigned int*)(0x42C80C80UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A1 *((volatile unsigned int*)(0x42C80C84UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A2 *((volatile unsigned int*)(0x42C80C88UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A3 *((volatile unsigned int*)(0x42C80C8CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A4 *((volatile unsigned int*)(0x42C80C90UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A5 *((volatile unsigned int*)(0x42C80C94UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A6 *((volatile unsigned int*)(0x42C80C98UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A7 *((volatile unsigned int*)(0x42C80C9CUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A8 *((volatile unsigned int*)(0x42C80CA0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A9 *((volatile unsigned int*)(0x42C80CA4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A10 *((volatile unsigned int*)(0x42C80CA8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A11 *((volatile unsigned int*)(0x42C80CACUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A12 *((volatile unsigned int*)(0x42C80CB0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A13 *((volatile unsigned int*)(0x42C80CB4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A14 *((volatile unsigned int*)(0x42C80CB8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A15 *((volatile unsigned int*)(0x42C80CBCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A16 *((volatile unsigned int*)(0x42C80CC0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A17 *((volatile unsigned int*)(0x42C80CC4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A18 *((volatile unsigned int*)(0x42C80CC8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A19 *((volatile unsigned int*)(0x42C80CCCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A20 *((volatile unsigned int*)(0x42C80CD0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A21 *((volatile unsigned int*)(0x42C80CD4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A22 *((volatile unsigned int*)(0x42C80CD8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A23 *((volatile unsigned int*)(0x42C80CDCUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A24 *((volatile unsigned int*)(0x42C80CE0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A25 *((volatile unsigned int*)(0x42C80CE4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A26 *((volatile unsigned int*)(0x42C80CE8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A27 *((volatile unsigned int*)(0x42C80CECUL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A28 *((volatile unsigned int*)(0x42C80CF0UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A29 *((volatile unsigned int*)(0x42C80CF4UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A30 *((volatile unsigned int*)(0x42C80CF8UL)) +#define bFM3_ETHERNET_MAC0_MAR4L_A31 *((volatile unsigned int*)(0x42C80CFCUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A32 *((volatile unsigned int*)(0x42C80D00UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A33 *((volatile unsigned int*)(0x42C80D04UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A34 *((volatile unsigned int*)(0x42C80D08UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A35 *((volatile unsigned int*)(0x42C80D0CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A36 *((volatile unsigned int*)(0x42C80D10UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A37 *((volatile unsigned int*)(0x42C80D14UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A38 *((volatile unsigned int*)(0x42C80D18UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A39 *((volatile unsigned int*)(0x42C80D1CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A40 *((volatile unsigned int*)(0x42C80D20UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A41 *((volatile unsigned int*)(0x42C80D24UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A42 *((volatile unsigned int*)(0x42C80D28UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A43 *((volatile unsigned int*)(0x42C80D2CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A44 *((volatile unsigned int*)(0x42C80D30UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A45 *((volatile unsigned int*)(0x42C80D34UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A46 *((volatile unsigned int*)(0x42C80D38UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_A47 *((volatile unsigned int*)(0x42C80D3CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC0 *((volatile unsigned int*)(0x42C80D60UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC1 *((volatile unsigned int*)(0x42C80D64UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC2 *((volatile unsigned int*)(0x42C80D68UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC3 *((volatile unsigned int*)(0x42C80D6CUL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC4 *((volatile unsigned int*)(0x42C80D70UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_MBC5 *((volatile unsigned int*)(0x42C80D74UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_SA *((volatile unsigned int*)(0x42C80D78UL)) +#define bFM3_ETHERNET_MAC0_MAR5H_AE *((volatile unsigned int*)(0x42C80D7CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A0 *((volatile unsigned int*)(0x42C80D80UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A1 *((volatile unsigned int*)(0x42C80D84UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A2 *((volatile unsigned int*)(0x42C80D88UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A3 *((volatile unsigned int*)(0x42C80D8CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A4 *((volatile unsigned int*)(0x42C80D90UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A5 *((volatile unsigned int*)(0x42C80D94UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A6 *((volatile unsigned int*)(0x42C80D98UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A7 *((volatile unsigned int*)(0x42C80D9CUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A8 *((volatile unsigned int*)(0x42C80DA0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A9 *((volatile unsigned int*)(0x42C80DA4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A10 *((volatile unsigned int*)(0x42C80DA8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A11 *((volatile unsigned int*)(0x42C80DACUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A12 *((volatile unsigned int*)(0x42C80DB0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A13 *((volatile unsigned int*)(0x42C80DB4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A14 *((volatile unsigned int*)(0x42C80DB8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A15 *((volatile unsigned int*)(0x42C80DBCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A16 *((volatile unsigned int*)(0x42C80DC0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A17 *((volatile unsigned int*)(0x42C80DC4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A18 *((volatile unsigned int*)(0x42C80DC8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A19 *((volatile unsigned int*)(0x42C80DCCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A20 *((volatile unsigned int*)(0x42C80DD0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A21 *((volatile unsigned int*)(0x42C80DD4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A22 *((volatile unsigned int*)(0x42C80DD8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A23 *((volatile unsigned int*)(0x42C80DDCUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A24 *((volatile unsigned int*)(0x42C80DE0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A25 *((volatile unsigned int*)(0x42C80DE4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A26 *((volatile unsigned int*)(0x42C80DE8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A27 *((volatile unsigned int*)(0x42C80DECUL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A28 *((volatile unsigned int*)(0x42C80DF0UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A29 *((volatile unsigned int*)(0x42C80DF4UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A30 *((volatile unsigned int*)(0x42C80DF8UL)) +#define bFM3_ETHERNET_MAC0_MAR5L_A31 *((volatile unsigned int*)(0x42C80DFCUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A32 *((volatile unsigned int*)(0x42C80E00UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A33 *((volatile unsigned int*)(0x42C80E04UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A34 *((volatile unsigned int*)(0x42C80E08UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A35 *((volatile unsigned int*)(0x42C80E0CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A36 *((volatile unsigned int*)(0x42C80E10UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A37 *((volatile unsigned int*)(0x42C80E14UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A38 *((volatile unsigned int*)(0x42C80E18UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A39 *((volatile unsigned int*)(0x42C80E1CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A40 *((volatile unsigned int*)(0x42C80E20UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A41 *((volatile unsigned int*)(0x42C80E24UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A42 *((volatile unsigned int*)(0x42C80E28UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A43 *((volatile unsigned int*)(0x42C80E2CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A44 *((volatile unsigned int*)(0x42C80E30UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A45 *((volatile unsigned int*)(0x42C80E34UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A46 *((volatile unsigned int*)(0x42C80E38UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_A47 *((volatile unsigned int*)(0x42C80E3CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC0 *((volatile unsigned int*)(0x42C80E60UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC1 *((volatile unsigned int*)(0x42C80E64UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC2 *((volatile unsigned int*)(0x42C80E68UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC3 *((volatile unsigned int*)(0x42C80E6CUL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC4 *((volatile unsigned int*)(0x42C80E70UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_MBC5 *((volatile unsigned int*)(0x42C80E74UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_SA *((volatile unsigned int*)(0x42C80E78UL)) +#define bFM3_ETHERNET_MAC0_MAR6H_AE *((volatile unsigned int*)(0x42C80E7CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A0 *((volatile unsigned int*)(0x42C80E80UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A1 *((volatile unsigned int*)(0x42C80E84UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A2 *((volatile unsigned int*)(0x42C80E88UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A3 *((volatile unsigned int*)(0x42C80E8CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A4 *((volatile unsigned int*)(0x42C80E90UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A5 *((volatile unsigned int*)(0x42C80E94UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A6 *((volatile unsigned int*)(0x42C80E98UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A7 *((volatile unsigned int*)(0x42C80E9CUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A8 *((volatile unsigned int*)(0x42C80EA0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A9 *((volatile unsigned int*)(0x42C80EA4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A10 *((volatile unsigned int*)(0x42C80EA8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A11 *((volatile unsigned int*)(0x42C80EACUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A12 *((volatile unsigned int*)(0x42C80EB0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A13 *((volatile unsigned int*)(0x42C80EB4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A14 *((volatile unsigned int*)(0x42C80EB8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A15 *((volatile unsigned int*)(0x42C80EBCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A16 *((volatile unsigned int*)(0x42C80EC0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A17 *((volatile unsigned int*)(0x42C80EC4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A18 *((volatile unsigned int*)(0x42C80EC8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A19 *((volatile unsigned int*)(0x42C80ECCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A20 *((volatile unsigned int*)(0x42C80ED0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A21 *((volatile unsigned int*)(0x42C80ED4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A22 *((volatile unsigned int*)(0x42C80ED8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A23 *((volatile unsigned int*)(0x42C80EDCUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A24 *((volatile unsigned int*)(0x42C80EE0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A25 *((volatile unsigned int*)(0x42C80EE4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A26 *((volatile unsigned int*)(0x42C80EE8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A27 *((volatile unsigned int*)(0x42C80EECUL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A28 *((volatile unsigned int*)(0x42C80EF0UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A29 *((volatile unsigned int*)(0x42C80EF4UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A30 *((volatile unsigned int*)(0x42C80EF8UL)) +#define bFM3_ETHERNET_MAC0_MAR6L_A31 *((volatile unsigned int*)(0x42C80EFCUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A32 *((volatile unsigned int*)(0x42C80F00UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A33 *((volatile unsigned int*)(0x42C80F04UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A34 *((volatile unsigned int*)(0x42C80F08UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A35 *((volatile unsigned int*)(0x42C80F0CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A36 *((volatile unsigned int*)(0x42C80F10UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A37 *((volatile unsigned int*)(0x42C80F14UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A38 *((volatile unsigned int*)(0x42C80F18UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A39 *((volatile unsigned int*)(0x42C80F1CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A40 *((volatile unsigned int*)(0x42C80F20UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A41 *((volatile unsigned int*)(0x42C80F24UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A42 *((volatile unsigned int*)(0x42C80F28UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A43 *((volatile unsigned int*)(0x42C80F2CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A44 *((volatile unsigned int*)(0x42C80F30UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A45 *((volatile unsigned int*)(0x42C80F34UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A46 *((volatile unsigned int*)(0x42C80F38UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_A47 *((volatile unsigned int*)(0x42C80F3CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC0 *((volatile unsigned int*)(0x42C80F60UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC1 *((volatile unsigned int*)(0x42C80F64UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC2 *((volatile unsigned int*)(0x42C80F68UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC3 *((volatile unsigned int*)(0x42C80F6CUL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC4 *((volatile unsigned int*)(0x42C80F70UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_MBC5 *((volatile unsigned int*)(0x42C80F74UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_SA *((volatile unsigned int*)(0x42C80F78UL)) +#define bFM3_ETHERNET_MAC0_MAR7H_AE *((volatile unsigned int*)(0x42C80F7CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A0 *((volatile unsigned int*)(0x42C80F80UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A1 *((volatile unsigned int*)(0x42C80F84UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A2 *((volatile unsigned int*)(0x42C80F88UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A3 *((volatile unsigned int*)(0x42C80F8CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A4 *((volatile unsigned int*)(0x42C80F90UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A5 *((volatile unsigned int*)(0x42C80F94UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A6 *((volatile unsigned int*)(0x42C80F98UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A7 *((volatile unsigned int*)(0x42C80F9CUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A8 *((volatile unsigned int*)(0x42C80FA0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A9 *((volatile unsigned int*)(0x42C80FA4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A10 *((volatile unsigned int*)(0x42C80FA8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A11 *((volatile unsigned int*)(0x42C80FACUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A12 *((volatile unsigned int*)(0x42C80FB0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A13 *((volatile unsigned int*)(0x42C80FB4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A14 *((volatile unsigned int*)(0x42C80FB8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A15 *((volatile unsigned int*)(0x42C80FBCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A16 *((volatile unsigned int*)(0x42C80FC0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A17 *((volatile unsigned int*)(0x42C80FC4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A18 *((volatile unsigned int*)(0x42C80FC8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A19 *((volatile unsigned int*)(0x42C80FCCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A20 *((volatile unsigned int*)(0x42C80FD0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A21 *((volatile unsigned int*)(0x42C80FD4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A22 *((volatile unsigned int*)(0x42C80FD8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A23 *((volatile unsigned int*)(0x42C80FDCUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A24 *((volatile unsigned int*)(0x42C80FE0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A25 *((volatile unsigned int*)(0x42C80FE4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A26 *((volatile unsigned int*)(0x42C80FE8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A27 *((volatile unsigned int*)(0x42C80FECUL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A28 *((volatile unsigned int*)(0x42C80FF0UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A29 *((volatile unsigned int*)(0x42C80FF4UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A30 *((volatile unsigned int*)(0x42C80FF8UL)) +#define bFM3_ETHERNET_MAC0_MAR7L_A31 *((volatile unsigned int*)(0x42C80FFCUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A32 *((volatile unsigned int*)(0x42C81000UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A33 *((volatile unsigned int*)(0x42C81004UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A34 *((volatile unsigned int*)(0x42C81008UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A35 *((volatile unsigned int*)(0x42C8100CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A36 *((volatile unsigned int*)(0x42C81010UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A37 *((volatile unsigned int*)(0x42C81014UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A38 *((volatile unsigned int*)(0x42C81018UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A39 *((volatile unsigned int*)(0x42C8101CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A40 *((volatile unsigned int*)(0x42C81020UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A41 *((volatile unsigned int*)(0x42C81024UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A42 *((volatile unsigned int*)(0x42C81028UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A43 *((volatile unsigned int*)(0x42C8102CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A44 *((volatile unsigned int*)(0x42C81030UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A45 *((volatile unsigned int*)(0x42C81034UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A46 *((volatile unsigned int*)(0x42C81038UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_A47 *((volatile unsigned int*)(0x42C8103CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC0 *((volatile unsigned int*)(0x42C81060UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC1 *((volatile unsigned int*)(0x42C81064UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC2 *((volatile unsigned int*)(0x42C81068UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC3 *((volatile unsigned int*)(0x42C8106CUL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC4 *((volatile unsigned int*)(0x42C81070UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_MBC5 *((volatile unsigned int*)(0x42C81074UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_SA *((volatile unsigned int*)(0x42C81078UL)) +#define bFM3_ETHERNET_MAC0_MAR8H_AE *((volatile unsigned int*)(0x42C8107CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A0 *((volatile unsigned int*)(0x42C81080UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A1 *((volatile unsigned int*)(0x42C81084UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A2 *((volatile unsigned int*)(0x42C81088UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A3 *((volatile unsigned int*)(0x42C8108CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A4 *((volatile unsigned int*)(0x42C81090UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A5 *((volatile unsigned int*)(0x42C81094UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A6 *((volatile unsigned int*)(0x42C81098UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A7 *((volatile unsigned int*)(0x42C8109CUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A8 *((volatile unsigned int*)(0x42C810A0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A9 *((volatile unsigned int*)(0x42C810A4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A10 *((volatile unsigned int*)(0x42C810A8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A11 *((volatile unsigned int*)(0x42C810ACUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A12 *((volatile unsigned int*)(0x42C810B0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A13 *((volatile unsigned int*)(0x42C810B4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A14 *((volatile unsigned int*)(0x42C810B8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A15 *((volatile unsigned int*)(0x42C810BCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A16 *((volatile unsigned int*)(0x42C810C0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A17 *((volatile unsigned int*)(0x42C810C4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A18 *((volatile unsigned int*)(0x42C810C8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A19 *((volatile unsigned int*)(0x42C810CCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A20 *((volatile unsigned int*)(0x42C810D0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A21 *((volatile unsigned int*)(0x42C810D4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A22 *((volatile unsigned int*)(0x42C810D8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A23 *((volatile unsigned int*)(0x42C810DCUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A24 *((volatile unsigned int*)(0x42C810E0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A25 *((volatile unsigned int*)(0x42C810E4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A26 *((volatile unsigned int*)(0x42C810E8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A27 *((volatile unsigned int*)(0x42C810ECUL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A28 *((volatile unsigned int*)(0x42C810F0UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A29 *((volatile unsigned int*)(0x42C810F4UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A30 *((volatile unsigned int*)(0x42C810F8UL)) +#define bFM3_ETHERNET_MAC0_MAR8L_A31 *((volatile unsigned int*)(0x42C810FCUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A32 *((volatile unsigned int*)(0x42C81100UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A33 *((volatile unsigned int*)(0x42C81104UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A34 *((volatile unsigned int*)(0x42C81108UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A35 *((volatile unsigned int*)(0x42C8110CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A36 *((volatile unsigned int*)(0x42C81110UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A37 *((volatile unsigned int*)(0x42C81114UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A38 *((volatile unsigned int*)(0x42C81118UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A39 *((volatile unsigned int*)(0x42C8111CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A40 *((volatile unsigned int*)(0x42C81120UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A41 *((volatile unsigned int*)(0x42C81124UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A42 *((volatile unsigned int*)(0x42C81128UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A43 *((volatile unsigned int*)(0x42C8112CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A44 *((volatile unsigned int*)(0x42C81130UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A45 *((volatile unsigned int*)(0x42C81134UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A46 *((volatile unsigned int*)(0x42C81138UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_A47 *((volatile unsigned int*)(0x42C8113CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC0 *((volatile unsigned int*)(0x42C81160UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC1 *((volatile unsigned int*)(0x42C81164UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC2 *((volatile unsigned int*)(0x42C81168UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC3 *((volatile unsigned int*)(0x42C8116CUL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC4 *((volatile unsigned int*)(0x42C81170UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_MBC5 *((volatile unsigned int*)(0x42C81174UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_SA *((volatile unsigned int*)(0x42C81178UL)) +#define bFM3_ETHERNET_MAC0_MAR9H_AE *((volatile unsigned int*)(0x42C8117CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A0 *((volatile unsigned int*)(0x42C81180UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A1 *((volatile unsigned int*)(0x42C81184UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A2 *((volatile unsigned int*)(0x42C81188UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A3 *((volatile unsigned int*)(0x42C8118CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A4 *((volatile unsigned int*)(0x42C81190UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A5 *((volatile unsigned int*)(0x42C81194UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A6 *((volatile unsigned int*)(0x42C81198UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A7 *((volatile unsigned int*)(0x42C8119CUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A8 *((volatile unsigned int*)(0x42C811A0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A9 *((volatile unsigned int*)(0x42C811A4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A10 *((volatile unsigned int*)(0x42C811A8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A11 *((volatile unsigned int*)(0x42C811ACUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A12 *((volatile unsigned int*)(0x42C811B0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A13 *((volatile unsigned int*)(0x42C811B4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A14 *((volatile unsigned int*)(0x42C811B8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A15 *((volatile unsigned int*)(0x42C811BCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A16 *((volatile unsigned int*)(0x42C811C0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A17 *((volatile unsigned int*)(0x42C811C4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A18 *((volatile unsigned int*)(0x42C811C8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A19 *((volatile unsigned int*)(0x42C811CCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A20 *((volatile unsigned int*)(0x42C811D0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A21 *((volatile unsigned int*)(0x42C811D4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A22 *((volatile unsigned int*)(0x42C811D8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A23 *((volatile unsigned int*)(0x42C811DCUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A24 *((volatile unsigned int*)(0x42C811E0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A25 *((volatile unsigned int*)(0x42C811E4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A26 *((volatile unsigned int*)(0x42C811E8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A27 *((volatile unsigned int*)(0x42C811ECUL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A28 *((volatile unsigned int*)(0x42C811F0UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A29 *((volatile unsigned int*)(0x42C811F4UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A30 *((volatile unsigned int*)(0x42C811F8UL)) +#define bFM3_ETHERNET_MAC0_MAR9L_A31 *((volatile unsigned int*)(0x42C811FCUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A32 *((volatile unsigned int*)(0x42C81200UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A33 *((volatile unsigned int*)(0x42C81204UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A34 *((volatile unsigned int*)(0x42C81208UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A35 *((volatile unsigned int*)(0x42C8120CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A36 *((volatile unsigned int*)(0x42C81210UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A37 *((volatile unsigned int*)(0x42C81214UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A38 *((volatile unsigned int*)(0x42C81218UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A39 *((volatile unsigned int*)(0x42C8121CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A40 *((volatile unsigned int*)(0x42C81220UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A41 *((volatile unsigned int*)(0x42C81224UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A42 *((volatile unsigned int*)(0x42C81228UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A43 *((volatile unsigned int*)(0x42C8122CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A44 *((volatile unsigned int*)(0x42C81230UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A45 *((volatile unsigned int*)(0x42C81234UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A46 *((volatile unsigned int*)(0x42C81238UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_A47 *((volatile unsigned int*)(0x42C8123CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC0 *((volatile unsigned int*)(0x42C81260UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC1 *((volatile unsigned int*)(0x42C81264UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC2 *((volatile unsigned int*)(0x42C81268UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC3 *((volatile unsigned int*)(0x42C8126CUL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC4 *((volatile unsigned int*)(0x42C81270UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_MBC5 *((volatile unsigned int*)(0x42C81274UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_SA *((volatile unsigned int*)(0x42C81278UL)) +#define bFM3_ETHERNET_MAC0_MAR10H_AE *((volatile unsigned int*)(0x42C8127CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A0 *((volatile unsigned int*)(0x42C81280UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A1 *((volatile unsigned int*)(0x42C81284UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A2 *((volatile unsigned int*)(0x42C81288UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A3 *((volatile unsigned int*)(0x42C8128CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A4 *((volatile unsigned int*)(0x42C81290UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A5 *((volatile unsigned int*)(0x42C81294UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A6 *((volatile unsigned int*)(0x42C81298UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A7 *((volatile unsigned int*)(0x42C8129CUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A8 *((volatile unsigned int*)(0x42C812A0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A9 *((volatile unsigned int*)(0x42C812A4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A10 *((volatile unsigned int*)(0x42C812A8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A11 *((volatile unsigned int*)(0x42C812ACUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A12 *((volatile unsigned int*)(0x42C812B0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A13 *((volatile unsigned int*)(0x42C812B4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A14 *((volatile unsigned int*)(0x42C812B8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A15 *((volatile unsigned int*)(0x42C812BCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A16 *((volatile unsigned int*)(0x42C812C0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A17 *((volatile unsigned int*)(0x42C812C4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A18 *((volatile unsigned int*)(0x42C812C8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A19 *((volatile unsigned int*)(0x42C812CCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A20 *((volatile unsigned int*)(0x42C812D0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A21 *((volatile unsigned int*)(0x42C812D4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A22 *((volatile unsigned int*)(0x42C812D8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A23 *((volatile unsigned int*)(0x42C812DCUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A24 *((volatile unsigned int*)(0x42C812E0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A25 *((volatile unsigned int*)(0x42C812E4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A26 *((volatile unsigned int*)(0x42C812E8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A27 *((volatile unsigned int*)(0x42C812ECUL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A28 *((volatile unsigned int*)(0x42C812F0UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A29 *((volatile unsigned int*)(0x42C812F4UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A30 *((volatile unsigned int*)(0x42C812F8UL)) +#define bFM3_ETHERNET_MAC0_MAR10L_A31 *((volatile unsigned int*)(0x42C812FCUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A32 *((volatile unsigned int*)(0x42C81300UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A33 *((volatile unsigned int*)(0x42C81304UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A34 *((volatile unsigned int*)(0x42C81308UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A35 *((volatile unsigned int*)(0x42C8130CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A36 *((volatile unsigned int*)(0x42C81310UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A37 *((volatile unsigned int*)(0x42C81314UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A38 *((volatile unsigned int*)(0x42C81318UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A39 *((volatile unsigned int*)(0x42C8131CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A40 *((volatile unsigned int*)(0x42C81320UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A41 *((volatile unsigned int*)(0x42C81324UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A42 *((volatile unsigned int*)(0x42C81328UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A43 *((volatile unsigned int*)(0x42C8132CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A44 *((volatile unsigned int*)(0x42C81330UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A45 *((volatile unsigned int*)(0x42C81334UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A46 *((volatile unsigned int*)(0x42C81338UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_A47 *((volatile unsigned int*)(0x42C8133CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC0 *((volatile unsigned int*)(0x42C81360UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC1 *((volatile unsigned int*)(0x42C81364UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC2 *((volatile unsigned int*)(0x42C81368UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC3 *((volatile unsigned int*)(0x42C8136CUL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC4 *((volatile unsigned int*)(0x42C81370UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_MBC5 *((volatile unsigned int*)(0x42C81374UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_SA *((volatile unsigned int*)(0x42C81378UL)) +#define bFM3_ETHERNET_MAC0_MAR11H_AE *((volatile unsigned int*)(0x42C8137CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A0 *((volatile unsigned int*)(0x42C81380UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A1 *((volatile unsigned int*)(0x42C81384UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A2 *((volatile unsigned int*)(0x42C81388UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A3 *((volatile unsigned int*)(0x42C8138CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A4 *((volatile unsigned int*)(0x42C81390UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A5 *((volatile unsigned int*)(0x42C81394UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A6 *((volatile unsigned int*)(0x42C81398UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A7 *((volatile unsigned int*)(0x42C8139CUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A8 *((volatile unsigned int*)(0x42C813A0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A9 *((volatile unsigned int*)(0x42C813A4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A10 *((volatile unsigned int*)(0x42C813A8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A11 *((volatile unsigned int*)(0x42C813ACUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A12 *((volatile unsigned int*)(0x42C813B0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A13 *((volatile unsigned int*)(0x42C813B4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A14 *((volatile unsigned int*)(0x42C813B8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A15 *((volatile unsigned int*)(0x42C813BCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A16 *((volatile unsigned int*)(0x42C813C0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A17 *((volatile unsigned int*)(0x42C813C4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A18 *((volatile unsigned int*)(0x42C813C8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A19 *((volatile unsigned int*)(0x42C813CCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A20 *((volatile unsigned int*)(0x42C813D0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A21 *((volatile unsigned int*)(0x42C813D4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A22 *((volatile unsigned int*)(0x42C813D8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A23 *((volatile unsigned int*)(0x42C813DCUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A24 *((volatile unsigned int*)(0x42C813E0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A25 *((volatile unsigned int*)(0x42C813E4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A26 *((volatile unsigned int*)(0x42C813E8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A27 *((volatile unsigned int*)(0x42C813ECUL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A28 *((volatile unsigned int*)(0x42C813F0UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A29 *((volatile unsigned int*)(0x42C813F4UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A30 *((volatile unsigned int*)(0x42C813F8UL)) +#define bFM3_ETHERNET_MAC0_MAR11L_A31 *((volatile unsigned int*)(0x42C813FCUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A32 *((volatile unsigned int*)(0x42C81400UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A33 *((volatile unsigned int*)(0x42C81404UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A34 *((volatile unsigned int*)(0x42C81408UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A35 *((volatile unsigned int*)(0x42C8140CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A36 *((volatile unsigned int*)(0x42C81410UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A37 *((volatile unsigned int*)(0x42C81414UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A38 *((volatile unsigned int*)(0x42C81418UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A39 *((volatile unsigned int*)(0x42C8141CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A40 *((volatile unsigned int*)(0x42C81420UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A41 *((volatile unsigned int*)(0x42C81424UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A42 *((volatile unsigned int*)(0x42C81428UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A43 *((volatile unsigned int*)(0x42C8142CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A44 *((volatile unsigned int*)(0x42C81430UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A45 *((volatile unsigned int*)(0x42C81434UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A46 *((volatile unsigned int*)(0x42C81438UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_A47 *((volatile unsigned int*)(0x42C8143CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC0 *((volatile unsigned int*)(0x42C81460UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC1 *((volatile unsigned int*)(0x42C81464UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC2 *((volatile unsigned int*)(0x42C81468UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC3 *((volatile unsigned int*)(0x42C8146CUL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC4 *((volatile unsigned int*)(0x42C81470UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_MBC5 *((volatile unsigned int*)(0x42C81474UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_SA *((volatile unsigned int*)(0x42C81478UL)) +#define bFM3_ETHERNET_MAC0_MAR12H_AE *((volatile unsigned int*)(0x42C8147CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A0 *((volatile unsigned int*)(0x42C81480UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A1 *((volatile unsigned int*)(0x42C81484UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A2 *((volatile unsigned int*)(0x42C81488UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A3 *((volatile unsigned int*)(0x42C8148CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A4 *((volatile unsigned int*)(0x42C81490UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A5 *((volatile unsigned int*)(0x42C81494UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A6 *((volatile unsigned int*)(0x42C81498UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A7 *((volatile unsigned int*)(0x42C8149CUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A8 *((volatile unsigned int*)(0x42C814A0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A9 *((volatile unsigned int*)(0x42C814A4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A10 *((volatile unsigned int*)(0x42C814A8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A11 *((volatile unsigned int*)(0x42C814ACUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A12 *((volatile unsigned int*)(0x42C814B0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A13 *((volatile unsigned int*)(0x42C814B4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A14 *((volatile unsigned int*)(0x42C814B8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A15 *((volatile unsigned int*)(0x42C814BCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A16 *((volatile unsigned int*)(0x42C814C0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A17 *((volatile unsigned int*)(0x42C814C4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A18 *((volatile unsigned int*)(0x42C814C8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A19 *((volatile unsigned int*)(0x42C814CCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A20 *((volatile unsigned int*)(0x42C814D0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A21 *((volatile unsigned int*)(0x42C814D4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A22 *((volatile unsigned int*)(0x42C814D8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A23 *((volatile unsigned int*)(0x42C814DCUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A24 *((volatile unsigned int*)(0x42C814E0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A25 *((volatile unsigned int*)(0x42C814E4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A26 *((volatile unsigned int*)(0x42C814E8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A27 *((volatile unsigned int*)(0x42C814ECUL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A28 *((volatile unsigned int*)(0x42C814F0UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A29 *((volatile unsigned int*)(0x42C814F4UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A30 *((volatile unsigned int*)(0x42C814F8UL)) +#define bFM3_ETHERNET_MAC0_MAR12L_A31 *((volatile unsigned int*)(0x42C814FCUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A32 *((volatile unsigned int*)(0x42C81500UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A33 *((volatile unsigned int*)(0x42C81504UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A34 *((volatile unsigned int*)(0x42C81508UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A35 *((volatile unsigned int*)(0x42C8150CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A36 *((volatile unsigned int*)(0x42C81510UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A37 *((volatile unsigned int*)(0x42C81514UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A38 *((volatile unsigned int*)(0x42C81518UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A39 *((volatile unsigned int*)(0x42C8151CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A40 *((volatile unsigned int*)(0x42C81520UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A41 *((volatile unsigned int*)(0x42C81524UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A42 *((volatile unsigned int*)(0x42C81528UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A43 *((volatile unsigned int*)(0x42C8152CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A44 *((volatile unsigned int*)(0x42C81530UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A45 *((volatile unsigned int*)(0x42C81534UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A46 *((volatile unsigned int*)(0x42C81538UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_A47 *((volatile unsigned int*)(0x42C8153CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC0 *((volatile unsigned int*)(0x42C81560UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC1 *((volatile unsigned int*)(0x42C81564UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC2 *((volatile unsigned int*)(0x42C81568UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC3 *((volatile unsigned int*)(0x42C8156CUL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC4 *((volatile unsigned int*)(0x42C81570UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_MBC5 *((volatile unsigned int*)(0x42C81574UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_SA *((volatile unsigned int*)(0x42C81578UL)) +#define bFM3_ETHERNET_MAC0_MAR13H_AE *((volatile unsigned int*)(0x42C8157CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A0 *((volatile unsigned int*)(0x42C81580UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A1 *((volatile unsigned int*)(0x42C81584UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A2 *((volatile unsigned int*)(0x42C81588UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A3 *((volatile unsigned int*)(0x42C8158CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A4 *((volatile unsigned int*)(0x42C81590UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A5 *((volatile unsigned int*)(0x42C81594UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A6 *((volatile unsigned int*)(0x42C81598UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A7 *((volatile unsigned int*)(0x42C8159CUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A8 *((volatile unsigned int*)(0x42C815A0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A9 *((volatile unsigned int*)(0x42C815A4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A10 *((volatile unsigned int*)(0x42C815A8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A11 *((volatile unsigned int*)(0x42C815ACUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A12 *((volatile unsigned int*)(0x42C815B0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A13 *((volatile unsigned int*)(0x42C815B4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A14 *((volatile unsigned int*)(0x42C815B8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A15 *((volatile unsigned int*)(0x42C815BCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A16 *((volatile unsigned int*)(0x42C815C0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A17 *((volatile unsigned int*)(0x42C815C4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A18 *((volatile unsigned int*)(0x42C815C8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A19 *((volatile unsigned int*)(0x42C815CCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A20 *((volatile unsigned int*)(0x42C815D0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A21 *((volatile unsigned int*)(0x42C815D4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A22 *((volatile unsigned int*)(0x42C815D8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A23 *((volatile unsigned int*)(0x42C815DCUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A24 *((volatile unsigned int*)(0x42C815E0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A25 *((volatile unsigned int*)(0x42C815E4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A26 *((volatile unsigned int*)(0x42C815E8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A27 *((volatile unsigned int*)(0x42C815ECUL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A28 *((volatile unsigned int*)(0x42C815F0UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A29 *((volatile unsigned int*)(0x42C815F4UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A30 *((volatile unsigned int*)(0x42C815F8UL)) +#define bFM3_ETHERNET_MAC0_MAR13L_A31 *((volatile unsigned int*)(0x42C815FCUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A32 *((volatile unsigned int*)(0x42C81600UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A33 *((volatile unsigned int*)(0x42C81604UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A34 *((volatile unsigned int*)(0x42C81608UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A35 *((volatile unsigned int*)(0x42C8160CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A36 *((volatile unsigned int*)(0x42C81610UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A37 *((volatile unsigned int*)(0x42C81614UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A38 *((volatile unsigned int*)(0x42C81618UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A39 *((volatile unsigned int*)(0x42C8161CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A40 *((volatile unsigned int*)(0x42C81620UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A41 *((volatile unsigned int*)(0x42C81624UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A42 *((volatile unsigned int*)(0x42C81628UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A43 *((volatile unsigned int*)(0x42C8162CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A44 *((volatile unsigned int*)(0x42C81630UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A45 *((volatile unsigned int*)(0x42C81634UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A46 *((volatile unsigned int*)(0x42C81638UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_A47 *((volatile unsigned int*)(0x42C8163CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC0 *((volatile unsigned int*)(0x42C81660UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC1 *((volatile unsigned int*)(0x42C81664UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC2 *((volatile unsigned int*)(0x42C81668UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC3 *((volatile unsigned int*)(0x42C8166CUL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC4 *((volatile unsigned int*)(0x42C81670UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_MBC5 *((volatile unsigned int*)(0x42C81674UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_SA *((volatile unsigned int*)(0x42C81678UL)) +#define bFM3_ETHERNET_MAC0_MAR14H_AE *((volatile unsigned int*)(0x42C8167CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A0 *((volatile unsigned int*)(0x42C81680UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A1 *((volatile unsigned int*)(0x42C81684UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A2 *((volatile unsigned int*)(0x42C81688UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A3 *((volatile unsigned int*)(0x42C8168CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A4 *((volatile unsigned int*)(0x42C81690UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A5 *((volatile unsigned int*)(0x42C81694UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A6 *((volatile unsigned int*)(0x42C81698UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A7 *((volatile unsigned int*)(0x42C8169CUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A8 *((volatile unsigned int*)(0x42C816A0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A9 *((volatile unsigned int*)(0x42C816A4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A10 *((volatile unsigned int*)(0x42C816A8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A11 *((volatile unsigned int*)(0x42C816ACUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A12 *((volatile unsigned int*)(0x42C816B0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A13 *((volatile unsigned int*)(0x42C816B4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A14 *((volatile unsigned int*)(0x42C816B8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A15 *((volatile unsigned int*)(0x42C816BCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A16 *((volatile unsigned int*)(0x42C816C0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A17 *((volatile unsigned int*)(0x42C816C4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A18 *((volatile unsigned int*)(0x42C816C8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A19 *((volatile unsigned int*)(0x42C816CCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A20 *((volatile unsigned int*)(0x42C816D0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A21 *((volatile unsigned int*)(0x42C816D4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A22 *((volatile unsigned int*)(0x42C816D8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A23 *((volatile unsigned int*)(0x42C816DCUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A24 *((volatile unsigned int*)(0x42C816E0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A25 *((volatile unsigned int*)(0x42C816E4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A26 *((volatile unsigned int*)(0x42C816E8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A27 *((volatile unsigned int*)(0x42C816ECUL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A28 *((volatile unsigned int*)(0x42C816F0UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A29 *((volatile unsigned int*)(0x42C816F4UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A30 *((volatile unsigned int*)(0x42C816F8UL)) +#define bFM3_ETHERNET_MAC0_MAR14L_A31 *((volatile unsigned int*)(0x42C816FCUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A32 *((volatile unsigned int*)(0x42C81700UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A33 *((volatile unsigned int*)(0x42C81704UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A34 *((volatile unsigned int*)(0x42C81708UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A35 *((volatile unsigned int*)(0x42C8170CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A36 *((volatile unsigned int*)(0x42C81710UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A37 *((volatile unsigned int*)(0x42C81714UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A38 *((volatile unsigned int*)(0x42C81718UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A39 *((volatile unsigned int*)(0x42C8171CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A40 *((volatile unsigned int*)(0x42C81720UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A41 *((volatile unsigned int*)(0x42C81724UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A42 *((volatile unsigned int*)(0x42C81728UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A43 *((volatile unsigned int*)(0x42C8172CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A44 *((volatile unsigned int*)(0x42C81730UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A45 *((volatile unsigned int*)(0x42C81734UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A46 *((volatile unsigned int*)(0x42C81738UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_A47 *((volatile unsigned int*)(0x42C8173CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC0 *((volatile unsigned int*)(0x42C81760UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC1 *((volatile unsigned int*)(0x42C81764UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC2 *((volatile unsigned int*)(0x42C81768UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC3 *((volatile unsigned int*)(0x42C8176CUL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC4 *((volatile unsigned int*)(0x42C81770UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_MBC5 *((volatile unsigned int*)(0x42C81774UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_SA *((volatile unsigned int*)(0x42C81778UL)) +#define bFM3_ETHERNET_MAC0_MAR15H_AE *((volatile unsigned int*)(0x42C8177CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A0 *((volatile unsigned int*)(0x42C81780UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A1 *((volatile unsigned int*)(0x42C81784UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A2 *((volatile unsigned int*)(0x42C81788UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A3 *((volatile unsigned int*)(0x42C8178CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A4 *((volatile unsigned int*)(0x42C81790UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A5 *((volatile unsigned int*)(0x42C81794UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A6 *((volatile unsigned int*)(0x42C81798UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A7 *((volatile unsigned int*)(0x42C8179CUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A8 *((volatile unsigned int*)(0x42C817A0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A9 *((volatile unsigned int*)(0x42C817A4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A10 *((volatile unsigned int*)(0x42C817A8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A11 *((volatile unsigned int*)(0x42C817ACUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A12 *((volatile unsigned int*)(0x42C817B0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A13 *((volatile unsigned int*)(0x42C817B4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A14 *((volatile unsigned int*)(0x42C817B8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A15 *((volatile unsigned int*)(0x42C817BCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A16 *((volatile unsigned int*)(0x42C817C0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A17 *((volatile unsigned int*)(0x42C817C4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A18 *((volatile unsigned int*)(0x42C817C8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A19 *((volatile unsigned int*)(0x42C817CCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A20 *((volatile unsigned int*)(0x42C817D0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A21 *((volatile unsigned int*)(0x42C817D4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A22 *((volatile unsigned int*)(0x42C817D8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A23 *((volatile unsigned int*)(0x42C817DCUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A24 *((volatile unsigned int*)(0x42C817E0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A25 *((volatile unsigned int*)(0x42C817E4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A26 *((volatile unsigned int*)(0x42C817E8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A27 *((volatile unsigned int*)(0x42C817ECUL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A28 *((volatile unsigned int*)(0x42C817F0UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A29 *((volatile unsigned int*)(0x42C817F4UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A30 *((volatile unsigned int*)(0x42C817F8UL)) +#define bFM3_ETHERNET_MAC0_MAR15L_A31 *((volatile unsigned int*)(0x42C817FCUL)) +#define bFM3_ETHERNET_MAC0_RGSR_LM *((volatile unsigned int*)(0x42C81B00UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LSP0 *((volatile unsigned int*)(0x42C81B04UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LSP1 *((volatile unsigned int*)(0x42C81B08UL)) +#define bFM3_ETHERNET_MAC0_RGSR_LS *((volatile unsigned int*)(0x42C81B0CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSE *((volatile unsigned int*)(0x42C8E000UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TFCU *((volatile unsigned int*)(0x42C8E004UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSI *((volatile unsigned int*)(0x42C8E008UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSU *((volatile unsigned int*)(0x42C8E00CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TITE *((volatile unsigned int*)(0x42C8E010UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TARU *((volatile unsigned int*)(0x42C8E014UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSEA *((volatile unsigned int*)(0x42C8E020UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSDB *((volatile unsigned int*)(0x42C8E024UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSV2E *((volatile unsigned int*)(0x42C8E028UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TETSP *((volatile unsigned int*)(0x42C8E02CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E *((volatile unsigned int*)(0x42C8E030UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E *((volatile unsigned int*)(0x42C8E034UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TETSEM *((volatile unsigned int*)(0x42C8E038UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSMRM *((volatile unsigned int*)(0x42C8E03CUL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSPS0 *((volatile unsigned int*)(0x42C8E040UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSPS1 *((volatile unsigned int*)(0x42C8E044UL)) +#define bFM3_ETHERNET_MAC0_TSCR_TSENMF *((volatile unsigned int*)(0x42C8E048UL)) +#define bFM3_ETHERNET_MAC0_TSCR_ATSFC *((volatile unsigned int*)(0x42C8E060UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC0 *((volatile unsigned int*)(0x42C8E080UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC1 *((volatile unsigned int*)(0x42C8E084UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC2 *((volatile unsigned int*)(0x42C8E088UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC3 *((volatile unsigned int*)(0x42C8E08CUL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC4 *((volatile unsigned int*)(0x42C8E090UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC5 *((volatile unsigned int*)(0x42C8E094UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC6 *((volatile unsigned int*)(0x42C8E098UL)) +#define bFM3_ETHERNET_MAC0_SSIR_SSINC7 *((volatile unsigned int*)(0x42C8E09CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS0 *((volatile unsigned int*)(0x42C8E100UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS1 *((volatile unsigned int*)(0x42C8E104UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS2 *((volatile unsigned int*)(0x42C8E108UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS3 *((volatile unsigned int*)(0x42C8E10CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS4 *((volatile unsigned int*)(0x42C8E110UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS5 *((volatile unsigned int*)(0x42C8E114UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS6 *((volatile unsigned int*)(0x42C8E118UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS7 *((volatile unsigned int*)(0x42C8E11CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS8 *((volatile unsigned int*)(0x42C8E120UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS9 *((volatile unsigned int*)(0x42C8E124UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS10 *((volatile unsigned int*)(0x42C8E128UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS11 *((volatile unsigned int*)(0x42C8E12CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS12 *((volatile unsigned int*)(0x42C8E130UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS13 *((volatile unsigned int*)(0x42C8E134UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS14 *((volatile unsigned int*)(0x42C8E138UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS15 *((volatile unsigned int*)(0x42C8E13CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS16 *((volatile unsigned int*)(0x42C8E140UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS17 *((volatile unsigned int*)(0x42C8E144UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS18 *((volatile unsigned int*)(0x42C8E148UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS19 *((volatile unsigned int*)(0x42C8E14CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS20 *((volatile unsigned int*)(0x42C8E150UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS21 *((volatile unsigned int*)(0x42C8E154UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS22 *((volatile unsigned int*)(0x42C8E158UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS23 *((volatile unsigned int*)(0x42C8E15CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS24 *((volatile unsigned int*)(0x42C8E160UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS25 *((volatile unsigned int*)(0x42C8E164UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS26 *((volatile unsigned int*)(0x42C8E168UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS27 *((volatile unsigned int*)(0x42C8E16CUL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS28 *((volatile unsigned int*)(0x42C8E170UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS29 *((volatile unsigned int*)(0x42C8E174UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS30 *((volatile unsigned int*)(0x42C8E178UL)) +#define bFM3_ETHERNET_MAC0_STSR_TSS31 *((volatile unsigned int*)(0x42C8E17CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS0 *((volatile unsigned int*)(0x42C8E080UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS1 *((volatile unsigned int*)(0x42C8E084UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS2 *((volatile unsigned int*)(0x42C8E088UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS3 *((volatile unsigned int*)(0x42C8E08CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS4 *((volatile unsigned int*)(0x42C8E090UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS5 *((volatile unsigned int*)(0x42C8E094UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS6 *((volatile unsigned int*)(0x42C8E098UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS7 *((volatile unsigned int*)(0x42C8E09CUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS8 *((volatile unsigned int*)(0x42C8E0A0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS9 *((volatile unsigned int*)(0x42C8E0A4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS10 *((volatile unsigned int*)(0x42C8E0A8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS11 *((volatile unsigned int*)(0x42C8E0ACUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS12 *((volatile unsigned int*)(0x42C8E0B0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS13 *((volatile unsigned int*)(0x42C8E0B4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS14 *((volatile unsigned int*)(0x42C8E0B8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS15 *((volatile unsigned int*)(0x42C8E0BCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS16 *((volatile unsigned int*)(0x42C8E0C0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS17 *((volatile unsigned int*)(0x42C8E0C4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS18 *((volatile unsigned int*)(0x42C8E0C8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS19 *((volatile unsigned int*)(0x42C8E0CCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS20 *((volatile unsigned int*)(0x42C8E0D0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS21 *((volatile unsigned int*)(0x42C8E0D4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS22 *((volatile unsigned int*)(0x42C8E0D8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS23 *((volatile unsigned int*)(0x42C8E0DCUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS24 *((volatile unsigned int*)(0x42C8E0E0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS25 *((volatile unsigned int*)(0x42C8E0E4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS26 *((volatile unsigned int*)(0x42C8E0E8UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS27 *((volatile unsigned int*)(0x42C8E0ECUL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS28 *((volatile unsigned int*)(0x42C8E0F0UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS29 *((volatile unsigned int*)(0x42C8E0F4UL)) +#define bFM3_ETHERNET_MAC0_STNR_TSSS30 *((volatile unsigned int*)(0x42C8E0F8UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS0 *((volatile unsigned int*)(0x42C8E200UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS1 *((volatile unsigned int*)(0x42C8E204UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS2 *((volatile unsigned int*)(0x42C8E208UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS3 *((volatile unsigned int*)(0x42C8E20CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS4 *((volatile unsigned int*)(0x42C8E210UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS5 *((volatile unsigned int*)(0x42C8E214UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS6 *((volatile unsigned int*)(0x42C8E218UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS7 *((volatile unsigned int*)(0x42C8E21CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS8 *((volatile unsigned int*)(0x42C8E220UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS9 *((volatile unsigned int*)(0x42C8E224UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS10 *((volatile unsigned int*)(0x42C8E228UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS11 *((volatile unsigned int*)(0x42C8E22CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS12 *((volatile unsigned int*)(0x42C8E230UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS13 *((volatile unsigned int*)(0x42C8E234UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS14 *((volatile unsigned int*)(0x42C8E238UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS15 *((volatile unsigned int*)(0x42C8E23CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS16 *((volatile unsigned int*)(0x42C8E240UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS17 *((volatile unsigned int*)(0x42C8E244UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS18 *((volatile unsigned int*)(0x42C8E248UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS19 *((volatile unsigned int*)(0x42C8E24CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS20 *((volatile unsigned int*)(0x42C8E250UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS21 *((volatile unsigned int*)(0x42C8E254UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS22 *((volatile unsigned int*)(0x42C8E258UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS23 *((volatile unsigned int*)(0x42C8E25CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS24 *((volatile unsigned int*)(0x42C8E260UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS25 *((volatile unsigned int*)(0x42C8E264UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS26 *((volatile unsigned int*)(0x42C8E268UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS27 *((volatile unsigned int*)(0x42C8E26CUL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS28 *((volatile unsigned int*)(0x42C8E270UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS29 *((volatile unsigned int*)(0x42C8E274UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS30 *((volatile unsigned int*)(0x42C8E278UL)) +#define bFM3_ETHERNET_MAC0_STSUR_TSS31 *((volatile unsigned int*)(0x42C8E27CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS0 *((volatile unsigned int*)(0x42C8E280UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS1 *((volatile unsigned int*)(0x42C8E284UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS2 *((volatile unsigned int*)(0x42C8E288UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS3 *((volatile unsigned int*)(0x42C8E28CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS4 *((volatile unsigned int*)(0x42C8E290UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS5 *((volatile unsigned int*)(0x42C8E294UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS6 *((volatile unsigned int*)(0x42C8E298UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS7 *((volatile unsigned int*)(0x42C8E29CUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS8 *((volatile unsigned int*)(0x42C8E2A0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS9 *((volatile unsigned int*)(0x42C8E2A4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS10 *((volatile unsigned int*)(0x42C8E2A8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS11 *((volatile unsigned int*)(0x42C8E2ACUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS12 *((volatile unsigned int*)(0x42C8E2B0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS13 *((volatile unsigned int*)(0x42C8E2B4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS14 *((volatile unsigned int*)(0x42C8E2B8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS15 *((volatile unsigned int*)(0x42C8E2BCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS16 *((volatile unsigned int*)(0x42C8E2C0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS17 *((volatile unsigned int*)(0x42C8E2C4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS18 *((volatile unsigned int*)(0x42C8E2C8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS19 *((volatile unsigned int*)(0x42C8E2CCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS20 *((volatile unsigned int*)(0x42C8E2D0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS21 *((volatile unsigned int*)(0x42C8E2D4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS22 *((volatile unsigned int*)(0x42C8E2D8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS23 *((volatile unsigned int*)(0x42C8E2DCUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS24 *((volatile unsigned int*)(0x42C8E2E0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS25 *((volatile unsigned int*)(0x42C8E2E4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS26 *((volatile unsigned int*)(0x42C8E2E8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS27 *((volatile unsigned int*)(0x42C8E2ECUL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS28 *((volatile unsigned int*)(0x42C8E2F0UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS29 *((volatile unsigned int*)(0x42C8E2F4UL)) +#define bFM3_ETHERNET_MAC0_STNUR_TSSS30 *((volatile unsigned int*)(0x42C8E2F8UL)) +#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB *((volatile unsigned int*)(0x42C8E2FCUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR0 *((volatile unsigned int*)(0x42C8E300UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR1 *((volatile unsigned int*)(0x42C8E304UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR2 *((volatile unsigned int*)(0x42C8E308UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR3 *((volatile unsigned int*)(0x42C8E30CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR4 *((volatile unsigned int*)(0x42C8E310UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR5 *((volatile unsigned int*)(0x42C8E314UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR6 *((volatile unsigned int*)(0x42C8E318UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR7 *((volatile unsigned int*)(0x42C8E31CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR8 *((volatile unsigned int*)(0x42C8E320UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR9 *((volatile unsigned int*)(0x42C8E324UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR10 *((volatile unsigned int*)(0x42C8E328UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR11 *((volatile unsigned int*)(0x42C8E32CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR12 *((volatile unsigned int*)(0x42C8E330UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR13 *((volatile unsigned int*)(0x42C8E334UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR14 *((volatile unsigned int*)(0x42C8E338UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR15 *((volatile unsigned int*)(0x42C8E33CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR16 *((volatile unsigned int*)(0x42C8E340UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR17 *((volatile unsigned int*)(0x42C8E344UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR18 *((volatile unsigned int*)(0x42C8E348UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR19 *((volatile unsigned int*)(0x42C8E34CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR20 *((volatile unsigned int*)(0x42C8E350UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR21 *((volatile unsigned int*)(0x42C8E354UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR22 *((volatile unsigned int*)(0x42C8E358UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR23 *((volatile unsigned int*)(0x42C8E35CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR24 *((volatile unsigned int*)(0x42C8E360UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR25 *((volatile unsigned int*)(0x42C8E364UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR26 *((volatile unsigned int*)(0x42C8E368UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR27 *((volatile unsigned int*)(0x42C8E36CUL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR28 *((volatile unsigned int*)(0x42C8E370UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR29 *((volatile unsigned int*)(0x42C8E374UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR30 *((volatile unsigned int*)(0x42C8E378UL)) +#define bFM3_ETHERNET_MAC0_TSAR_TSAR31 *((volatile unsigned int*)(0x42C8E37CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR0 *((volatile unsigned int*)(0x42C8E380UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR1 *((volatile unsigned int*)(0x42C8E384UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR2 *((volatile unsigned int*)(0x42C8E388UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR3 *((volatile unsigned int*)(0x42C8E38CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR4 *((volatile unsigned int*)(0x42C8E390UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR5 *((volatile unsigned int*)(0x42C8E394UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR6 *((volatile unsigned int*)(0x42C8E398UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR7 *((volatile unsigned int*)(0x42C8E39CUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR8 *((volatile unsigned int*)(0x42C8E3A0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR9 *((volatile unsigned int*)(0x42C8E3A4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR10 *((volatile unsigned int*)(0x42C8E3A8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR11 *((volatile unsigned int*)(0x42C8E3ACUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR12 *((volatile unsigned int*)(0x42C8E3B0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR13 *((volatile unsigned int*)(0x42C8E3B4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR14 *((volatile unsigned int*)(0x42C8E3B8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR15 *((volatile unsigned int*)(0x42C8E3BCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR16 *((volatile unsigned int*)(0x42C8E3C0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR17 *((volatile unsigned int*)(0x42C8E3C4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR18 *((volatile unsigned int*)(0x42C8E3C8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR19 *((volatile unsigned int*)(0x42C8E3CCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR20 *((volatile unsigned int*)(0x42C8E3D0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR21 *((volatile unsigned int*)(0x42C8E3D4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR22 *((volatile unsigned int*)(0x42C8E3D8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR23 *((volatile unsigned int*)(0x42C8E3DCUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR24 *((volatile unsigned int*)(0x42C8E3E0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR25 *((volatile unsigned int*)(0x42C8E3E4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR26 *((volatile unsigned int*)(0x42C8E3E8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR27 *((volatile unsigned int*)(0x42C8E3ECUL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR28 *((volatile unsigned int*)(0x42C8E3F0UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR29 *((volatile unsigned int*)(0x42C8E3F4UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR30 *((volatile unsigned int*)(0x42C8E3F8UL)) +#define bFM3_ETHERNET_MAC0_TTSR_TSTR31 *((volatile unsigned int*)(0x42C8E3FCUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR0 *((volatile unsigned int*)(0x42C8E400UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR1 *((volatile unsigned int*)(0x42C8E404UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR2 *((volatile unsigned int*)(0x42C8E408UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR3 *((volatile unsigned int*)(0x42C8E40CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR4 *((volatile unsigned int*)(0x42C8E410UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR5 *((volatile unsigned int*)(0x42C8E414UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR6 *((volatile unsigned int*)(0x42C8E418UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR7 *((volatile unsigned int*)(0x42C8E41CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR8 *((volatile unsigned int*)(0x42C8E420UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR9 *((volatile unsigned int*)(0x42C8E424UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR10 *((volatile unsigned int*)(0x42C8E428UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR11 *((volatile unsigned int*)(0x42C8E42CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR12 *((volatile unsigned int*)(0x42C8E430UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR13 *((volatile unsigned int*)(0x42C8E434UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR14 *((volatile unsigned int*)(0x42C8E438UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR15 *((volatile unsigned int*)(0x42C8E43CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR16 *((volatile unsigned int*)(0x42C8E440UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR17 *((volatile unsigned int*)(0x42C8E444UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR18 *((volatile unsigned int*)(0x42C8E448UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR19 *((volatile unsigned int*)(0x42C8E44CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR20 *((volatile unsigned int*)(0x42C8E450UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR21 *((volatile unsigned int*)(0x42C8E454UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR22 *((volatile unsigned int*)(0x42C8E458UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR23 *((volatile unsigned int*)(0x42C8E45CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR24 *((volatile unsigned int*)(0x42C8E460UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR25 *((volatile unsigned int*)(0x42C8E464UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR26 *((volatile unsigned int*)(0x42C8E468UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR27 *((volatile unsigned int*)(0x42C8E46CUL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR28 *((volatile unsigned int*)(0x42C8E470UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR29 *((volatile unsigned int*)(0x42C8E474UL)) +#define bFM3_ETHERNET_MAC0_TTNR_TSTR30 *((volatile unsigned int*)(0x42C8E478UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42C8E480UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42C8E484UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42C8E488UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42C8E48CUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42C8E490UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42C8E494UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42C8E498UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42C8E49CUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42C8E4A0UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42C8E4A4UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42C8E4A8UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42C8E4ACUL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42C8E4B0UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42C8E4B4UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42C8E4B8UL)) +#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42C8E4BCUL)) +#define bFM3_ETHERNET_MAC0_TSR_TSSOVF *((volatile unsigned int*)(0x42C8E500UL)) +#define bFM3_ETHERNET_MAC0_TSR_TSTART *((volatile unsigned int*)(0x42C8E504UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSTS *((volatile unsigned int*)(0x42C8E508UL)) +#define bFM3_ETHERNET_MAC0_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSSTM *((volatile unsigned int*)(0x42C8E560UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS0 *((volatile unsigned int*)(0x42C8E564UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS1 *((volatile unsigned int*)(0x42C8E568UL)) +#define bFM3_ETHERNET_MAC0_TSR_ATSNS2 *((volatile unsigned int*)(0x42C8E56CUL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42C8E580UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42C8E584UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42C8E588UL)) +#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42C8E58CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN0 *((volatile unsigned int*)(0x42C8E600UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN1 *((volatile unsigned int*)(0x42C8E604UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN2 *((volatile unsigned int*)(0x42C8E608UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN3 *((volatile unsigned int*)(0x42C8E60CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN4 *((volatile unsigned int*)(0x42C8E610UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN5 *((volatile unsigned int*)(0x42C8E614UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN6 *((volatile unsigned int*)(0x42C8E618UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN7 *((volatile unsigned int*)(0x42C8E61CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN8 *((volatile unsigned int*)(0x42C8E620UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN9 *((volatile unsigned int*)(0x42C8E624UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN10 *((volatile unsigned int*)(0x42C8E628UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN11 *((volatile unsigned int*)(0x42C8E62CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN12 *((volatile unsigned int*)(0x42C8E630UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN13 *((volatile unsigned int*)(0x42C8E634UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN14 *((volatile unsigned int*)(0x42C8E638UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN15 *((volatile unsigned int*)(0x42C8E63CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN16 *((volatile unsigned int*)(0x42C8E640UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN17 *((volatile unsigned int*)(0x42C8E644UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN18 *((volatile unsigned int*)(0x42C8E648UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN19 *((volatile unsigned int*)(0x42C8E64CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN20 *((volatile unsigned int*)(0x42C8E650UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN21 *((volatile unsigned int*)(0x42C8E654UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN22 *((volatile unsigned int*)(0x42C8E658UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN23 *((volatile unsigned int*)(0x42C8E65CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN24 *((volatile unsigned int*)(0x42C8E660UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN25 *((volatile unsigned int*)(0x42C8E664UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN26 *((volatile unsigned int*)(0x42C8E668UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN27 *((volatile unsigned int*)(0x42C8E66CUL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN28 *((volatile unsigned int*)(0x42C8E670UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN29 *((volatile unsigned int*)(0x42C8E674UL)) +#define bFM3_ETHERNET_MAC0_ATNR_ATN30 *((volatile unsigned int*)(0x42C8E678UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS0 *((volatile unsigned int*)(0x42C8E680UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS1 *((volatile unsigned int*)(0x42C8E684UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS2 *((volatile unsigned int*)(0x42C8E688UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS3 *((volatile unsigned int*)(0x42C8E68CUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS4 *((volatile unsigned int*)(0x42C8E690UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS5 *((volatile unsigned int*)(0x42C8E694UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS6 *((volatile unsigned int*)(0x42C8E698UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS7 *((volatile unsigned int*)(0x42C8E69CUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS8 *((volatile unsigned int*)(0x42C8E6A0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS9 *((volatile unsigned int*)(0x42C8E6A4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS10 *((volatile unsigned int*)(0x42C8E6A8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS11 *((volatile unsigned int*)(0x42C8E6ACUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS12 *((volatile unsigned int*)(0x42C8E6B0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS13 *((volatile unsigned int*)(0x42C8E6B4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS14 *((volatile unsigned int*)(0x42C8E6B8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS15 *((volatile unsigned int*)(0x42C8E6BCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS16 *((volatile unsigned int*)(0x42C8E6C0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS17 *((volatile unsigned int*)(0x42C8E6C4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS18 *((volatile unsigned int*)(0x42C8E6C8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS19 *((volatile unsigned int*)(0x42C8E6CCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS20 *((volatile unsigned int*)(0x42C8E6D0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS21 *((volatile unsigned int*)(0x42C8E6D4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS22 *((volatile unsigned int*)(0x42C8E6D8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS23 *((volatile unsigned int*)(0x42C8E6DCUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS24 *((volatile unsigned int*)(0x42C8E6E0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS25 *((volatile unsigned int*)(0x42C8E6E4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS26 *((volatile unsigned int*)(0x42C8E6E8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS27 *((volatile unsigned int*)(0x42C8E6ECUL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS28 *((volatile unsigned int*)(0x42C8E6F0UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS29 *((volatile unsigned int*)(0x42C8E6F4UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS30 *((volatile unsigned int*)(0x42C8E6F8UL)) +#define bFM3_ETHERNET_MAC0_ATSR_ATS31 *((volatile unsigned int*)(0x42C8E6FCUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A32 *((volatile unsigned int*)(0x42C90000UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A33 *((volatile unsigned int*)(0x42C90004UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A34 *((volatile unsigned int*)(0x42C90008UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A35 *((volatile unsigned int*)(0x42C9000CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A36 *((volatile unsigned int*)(0x42C90010UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A37 *((volatile unsigned int*)(0x42C90014UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A38 *((volatile unsigned int*)(0x42C90018UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A39 *((volatile unsigned int*)(0x42C9001CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A40 *((volatile unsigned int*)(0x42C90020UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A41 *((volatile unsigned int*)(0x42C90024UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A42 *((volatile unsigned int*)(0x42C90028UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A43 *((volatile unsigned int*)(0x42C9002CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A44 *((volatile unsigned int*)(0x42C90030UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A45 *((volatile unsigned int*)(0x42C90034UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A46 *((volatile unsigned int*)(0x42C90038UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_A47 *((volatile unsigned int*)(0x42C9003CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC0 *((volatile unsigned int*)(0x42C90060UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC1 *((volatile unsigned int*)(0x42C90064UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC2 *((volatile unsigned int*)(0x42C90068UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC3 *((volatile unsigned int*)(0x42C9006CUL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC4 *((volatile unsigned int*)(0x42C90070UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_MBC5 *((volatile unsigned int*)(0x42C90074UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_SA *((volatile unsigned int*)(0x42C90078UL)) +#define bFM3_ETHERNET_MAC0_MAR16H_AE *((volatile unsigned int*)(0x42C9007CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A0 *((volatile unsigned int*)(0x42C90080UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A1 *((volatile unsigned int*)(0x42C90084UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A2 *((volatile unsigned int*)(0x42C90088UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A3 *((volatile unsigned int*)(0x42C9008CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A4 *((volatile unsigned int*)(0x42C90090UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A5 *((volatile unsigned int*)(0x42C90094UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A6 *((volatile unsigned int*)(0x42C90098UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A7 *((volatile unsigned int*)(0x42C9009CUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A8 *((volatile unsigned int*)(0x42C900A0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A9 *((volatile unsigned int*)(0x42C900A4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A10 *((volatile unsigned int*)(0x42C900A8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A11 *((volatile unsigned int*)(0x42C900ACUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A12 *((volatile unsigned int*)(0x42C900B0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A13 *((volatile unsigned int*)(0x42C900B4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A14 *((volatile unsigned int*)(0x42C900B8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A15 *((volatile unsigned int*)(0x42C900BCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A16 *((volatile unsigned int*)(0x42C900C0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A17 *((volatile unsigned int*)(0x42C900C4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A18 *((volatile unsigned int*)(0x42C900C8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A19 *((volatile unsigned int*)(0x42C900CCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A20 *((volatile unsigned int*)(0x42C900D0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A21 *((volatile unsigned int*)(0x42C900D4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A22 *((volatile unsigned int*)(0x42C900D8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A23 *((volatile unsigned int*)(0x42C900DCUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A24 *((volatile unsigned int*)(0x42C900E0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A25 *((volatile unsigned int*)(0x42C900E4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A26 *((volatile unsigned int*)(0x42C900E8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A27 *((volatile unsigned int*)(0x42C900ECUL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A28 *((volatile unsigned int*)(0x42C900F0UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A29 *((volatile unsigned int*)(0x42C900F4UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A30 *((volatile unsigned int*)(0x42C900F8UL)) +#define bFM3_ETHERNET_MAC0_MAR16L_A31 *((volatile unsigned int*)(0x42C900FCUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A32 *((volatile unsigned int*)(0x42C90100UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A33 *((volatile unsigned int*)(0x42C90104UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A34 *((volatile unsigned int*)(0x42C90108UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A35 *((volatile unsigned int*)(0x42C9010CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A36 *((volatile unsigned int*)(0x42C90110UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A37 *((volatile unsigned int*)(0x42C90114UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A38 *((volatile unsigned int*)(0x42C90118UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A39 *((volatile unsigned int*)(0x42C9011CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A40 *((volatile unsigned int*)(0x42C90120UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A41 *((volatile unsigned int*)(0x42C90124UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A42 *((volatile unsigned int*)(0x42C90128UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A43 *((volatile unsigned int*)(0x42C9012CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A44 *((volatile unsigned int*)(0x42C90130UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A45 *((volatile unsigned int*)(0x42C90134UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A46 *((volatile unsigned int*)(0x42C90138UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_A47 *((volatile unsigned int*)(0x42C9013CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC0 *((volatile unsigned int*)(0x42C90160UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC1 *((volatile unsigned int*)(0x42C90164UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC2 *((volatile unsigned int*)(0x42C90168UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC3 *((volatile unsigned int*)(0x42C9016CUL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC4 *((volatile unsigned int*)(0x42C90170UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_MBC5 *((volatile unsigned int*)(0x42C90174UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_SA *((volatile unsigned int*)(0x42C90178UL)) +#define bFM3_ETHERNET_MAC0_MAR17H_AE *((volatile unsigned int*)(0x42C9017CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A0 *((volatile unsigned int*)(0x42C90180UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A1 *((volatile unsigned int*)(0x42C90184UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A2 *((volatile unsigned int*)(0x42C90188UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A3 *((volatile unsigned int*)(0x42C9018CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A4 *((volatile unsigned int*)(0x42C90190UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A5 *((volatile unsigned int*)(0x42C90194UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A6 *((volatile unsigned int*)(0x42C90198UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A7 *((volatile unsigned int*)(0x42C9019CUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A8 *((volatile unsigned int*)(0x42C901A0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A9 *((volatile unsigned int*)(0x42C901A4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A10 *((volatile unsigned int*)(0x42C901A8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A11 *((volatile unsigned int*)(0x42C901ACUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A12 *((volatile unsigned int*)(0x42C901B0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A13 *((volatile unsigned int*)(0x42C901B4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A14 *((volatile unsigned int*)(0x42C901B8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A15 *((volatile unsigned int*)(0x42C901BCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A16 *((volatile unsigned int*)(0x42C901C0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A17 *((volatile unsigned int*)(0x42C901C4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A18 *((volatile unsigned int*)(0x42C901C8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A19 *((volatile unsigned int*)(0x42C901CCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A20 *((volatile unsigned int*)(0x42C901D0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A21 *((volatile unsigned int*)(0x42C901D4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A22 *((volatile unsigned int*)(0x42C901D8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A23 *((volatile unsigned int*)(0x42C901DCUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A24 *((volatile unsigned int*)(0x42C901E0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A25 *((volatile unsigned int*)(0x42C901E4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A26 *((volatile unsigned int*)(0x42C901E8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A27 *((volatile unsigned int*)(0x42C901ECUL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A28 *((volatile unsigned int*)(0x42C901F0UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A29 *((volatile unsigned int*)(0x42C901F4UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A30 *((volatile unsigned int*)(0x42C901F8UL)) +#define bFM3_ETHERNET_MAC0_MAR17L_A31 *((volatile unsigned int*)(0x42C901FCUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A32 *((volatile unsigned int*)(0x42C90200UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A33 *((volatile unsigned int*)(0x42C90204UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A34 *((volatile unsigned int*)(0x42C90208UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A35 *((volatile unsigned int*)(0x42C9020CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A36 *((volatile unsigned int*)(0x42C90210UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A37 *((volatile unsigned int*)(0x42C90214UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A38 *((volatile unsigned int*)(0x42C90218UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A39 *((volatile unsigned int*)(0x42C9021CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A40 *((volatile unsigned int*)(0x42C90220UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A41 *((volatile unsigned int*)(0x42C90224UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A42 *((volatile unsigned int*)(0x42C90228UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A43 *((volatile unsigned int*)(0x42C9022CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A44 *((volatile unsigned int*)(0x42C90230UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A45 *((volatile unsigned int*)(0x42C90234UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A46 *((volatile unsigned int*)(0x42C90238UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_A47 *((volatile unsigned int*)(0x42C9023CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC0 *((volatile unsigned int*)(0x42C90260UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC1 *((volatile unsigned int*)(0x42C90264UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC2 *((volatile unsigned int*)(0x42C90268UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC3 *((volatile unsigned int*)(0x42C9026CUL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC4 *((volatile unsigned int*)(0x42C90270UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_MBC5 *((volatile unsigned int*)(0x42C90274UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_SA *((volatile unsigned int*)(0x42C90278UL)) +#define bFM3_ETHERNET_MAC0_MAR18H_AE *((volatile unsigned int*)(0x42C9027CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A0 *((volatile unsigned int*)(0x42C90280UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A1 *((volatile unsigned int*)(0x42C90284UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A2 *((volatile unsigned int*)(0x42C90288UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A3 *((volatile unsigned int*)(0x42C9028CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A4 *((volatile unsigned int*)(0x42C90290UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A5 *((volatile unsigned int*)(0x42C90294UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A6 *((volatile unsigned int*)(0x42C90298UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A7 *((volatile unsigned int*)(0x42C9029CUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A8 *((volatile unsigned int*)(0x42C902A0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A9 *((volatile unsigned int*)(0x42C902A4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A10 *((volatile unsigned int*)(0x42C902A8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A11 *((volatile unsigned int*)(0x42C902ACUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A12 *((volatile unsigned int*)(0x42C902B0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A13 *((volatile unsigned int*)(0x42C902B4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A14 *((volatile unsigned int*)(0x42C902B8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A15 *((volatile unsigned int*)(0x42C902BCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A16 *((volatile unsigned int*)(0x42C902C0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A17 *((volatile unsigned int*)(0x42C902C4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A18 *((volatile unsigned int*)(0x42C902C8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A19 *((volatile unsigned int*)(0x42C902CCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A20 *((volatile unsigned int*)(0x42C902D0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A21 *((volatile unsigned int*)(0x42C902D4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A22 *((volatile unsigned int*)(0x42C902D8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A23 *((volatile unsigned int*)(0x42C902DCUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A24 *((volatile unsigned int*)(0x42C902E0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A25 *((volatile unsigned int*)(0x42C902E4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A26 *((volatile unsigned int*)(0x42C902E8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A27 *((volatile unsigned int*)(0x42C902ECUL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A28 *((volatile unsigned int*)(0x42C902F0UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A29 *((volatile unsigned int*)(0x42C902F4UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A30 *((volatile unsigned int*)(0x42C902F8UL)) +#define bFM3_ETHERNET_MAC0_MAR18L_A31 *((volatile unsigned int*)(0x42C902FCUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A32 *((volatile unsigned int*)(0x42C90300UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A33 *((volatile unsigned int*)(0x42C90304UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A34 *((volatile unsigned int*)(0x42C90308UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A35 *((volatile unsigned int*)(0x42C9030CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A36 *((volatile unsigned int*)(0x42C90310UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A37 *((volatile unsigned int*)(0x42C90314UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A38 *((volatile unsigned int*)(0x42C90318UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A39 *((volatile unsigned int*)(0x42C9031CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A40 *((volatile unsigned int*)(0x42C90320UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A41 *((volatile unsigned int*)(0x42C90324UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A42 *((volatile unsigned int*)(0x42C90328UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A43 *((volatile unsigned int*)(0x42C9032CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A44 *((volatile unsigned int*)(0x42C90330UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A45 *((volatile unsigned int*)(0x42C90334UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A46 *((volatile unsigned int*)(0x42C90338UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_A47 *((volatile unsigned int*)(0x42C9033CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC0 *((volatile unsigned int*)(0x42C90360UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC1 *((volatile unsigned int*)(0x42C90364UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC2 *((volatile unsigned int*)(0x42C90368UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC3 *((volatile unsigned int*)(0x42C9036CUL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC4 *((volatile unsigned int*)(0x42C90370UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_MBC5 *((volatile unsigned int*)(0x42C90374UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_SA *((volatile unsigned int*)(0x42C90378UL)) +#define bFM3_ETHERNET_MAC0_MAR19H_AE *((volatile unsigned int*)(0x42C9037CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A0 *((volatile unsigned int*)(0x42C90380UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A1 *((volatile unsigned int*)(0x42C90384UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A2 *((volatile unsigned int*)(0x42C90388UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A3 *((volatile unsigned int*)(0x42C9038CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A4 *((volatile unsigned int*)(0x42C90390UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A5 *((volatile unsigned int*)(0x42C90394UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A6 *((volatile unsigned int*)(0x42C90398UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A7 *((volatile unsigned int*)(0x42C9039CUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A8 *((volatile unsigned int*)(0x42C903A0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A9 *((volatile unsigned int*)(0x42C903A4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A10 *((volatile unsigned int*)(0x42C903A8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A11 *((volatile unsigned int*)(0x42C903ACUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A12 *((volatile unsigned int*)(0x42C903B0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A13 *((volatile unsigned int*)(0x42C903B4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A14 *((volatile unsigned int*)(0x42C903B8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A15 *((volatile unsigned int*)(0x42C903BCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A16 *((volatile unsigned int*)(0x42C903C0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A17 *((volatile unsigned int*)(0x42C903C4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A18 *((volatile unsigned int*)(0x42C903C8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A19 *((volatile unsigned int*)(0x42C903CCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A20 *((volatile unsigned int*)(0x42C903D0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A21 *((volatile unsigned int*)(0x42C903D4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A22 *((volatile unsigned int*)(0x42C903D8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A23 *((volatile unsigned int*)(0x42C903DCUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A24 *((volatile unsigned int*)(0x42C903E0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A25 *((volatile unsigned int*)(0x42C903E4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A26 *((volatile unsigned int*)(0x42C903E8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A27 *((volatile unsigned int*)(0x42C903ECUL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A28 *((volatile unsigned int*)(0x42C903F0UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A29 *((volatile unsigned int*)(0x42C903F4UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A30 *((volatile unsigned int*)(0x42C903F8UL)) +#define bFM3_ETHERNET_MAC0_MAR19L_A31 *((volatile unsigned int*)(0x42C903FCUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A32 *((volatile unsigned int*)(0x42C90400UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A33 *((volatile unsigned int*)(0x42C90404UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A34 *((volatile unsigned int*)(0x42C90408UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A35 *((volatile unsigned int*)(0x42C9040CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A36 *((volatile unsigned int*)(0x42C90410UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A37 *((volatile unsigned int*)(0x42C90414UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A38 *((volatile unsigned int*)(0x42C90418UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A39 *((volatile unsigned int*)(0x42C9041CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A40 *((volatile unsigned int*)(0x42C90420UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A41 *((volatile unsigned int*)(0x42C90424UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A42 *((volatile unsigned int*)(0x42C90428UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A43 *((volatile unsigned int*)(0x42C9042CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A44 *((volatile unsigned int*)(0x42C90430UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A45 *((volatile unsigned int*)(0x42C90434UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A46 *((volatile unsigned int*)(0x42C90438UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_A47 *((volatile unsigned int*)(0x42C9043CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC0 *((volatile unsigned int*)(0x42C90460UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC1 *((volatile unsigned int*)(0x42C90464UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC2 *((volatile unsigned int*)(0x42C90468UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC3 *((volatile unsigned int*)(0x42C9046CUL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC4 *((volatile unsigned int*)(0x42C90470UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_MBC5 *((volatile unsigned int*)(0x42C90474UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_SA *((volatile unsigned int*)(0x42C90478UL)) +#define bFM3_ETHERNET_MAC0_MAR20H_AE *((volatile unsigned int*)(0x42C9047CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A0 *((volatile unsigned int*)(0x42C90480UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A1 *((volatile unsigned int*)(0x42C90484UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A2 *((volatile unsigned int*)(0x42C90488UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A3 *((volatile unsigned int*)(0x42C9048CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A4 *((volatile unsigned int*)(0x42C90490UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A5 *((volatile unsigned int*)(0x42C90494UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A6 *((volatile unsigned int*)(0x42C90498UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A7 *((volatile unsigned int*)(0x42C9049CUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A8 *((volatile unsigned int*)(0x42C904A0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A9 *((volatile unsigned int*)(0x42C904A4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A10 *((volatile unsigned int*)(0x42C904A8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A11 *((volatile unsigned int*)(0x42C904ACUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A12 *((volatile unsigned int*)(0x42C904B0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A13 *((volatile unsigned int*)(0x42C904B4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A14 *((volatile unsigned int*)(0x42C904B8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A15 *((volatile unsigned int*)(0x42C904BCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A16 *((volatile unsigned int*)(0x42C904C0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A17 *((volatile unsigned int*)(0x42C904C4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A18 *((volatile unsigned int*)(0x42C904C8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A19 *((volatile unsigned int*)(0x42C904CCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A20 *((volatile unsigned int*)(0x42C904D0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A21 *((volatile unsigned int*)(0x42C904D4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A22 *((volatile unsigned int*)(0x42C904D8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A23 *((volatile unsigned int*)(0x42C904DCUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A24 *((volatile unsigned int*)(0x42C904E0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A25 *((volatile unsigned int*)(0x42C904E4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A26 *((volatile unsigned int*)(0x42C904E8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A27 *((volatile unsigned int*)(0x42C904ECUL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A28 *((volatile unsigned int*)(0x42C904F0UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A29 *((volatile unsigned int*)(0x42C904F4UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A30 *((volatile unsigned int*)(0x42C904F8UL)) +#define bFM3_ETHERNET_MAC0_MAR20L_A31 *((volatile unsigned int*)(0x42C904FCUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A32 *((volatile unsigned int*)(0x42C90500UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A33 *((volatile unsigned int*)(0x42C90504UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A34 *((volatile unsigned int*)(0x42C90508UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A35 *((volatile unsigned int*)(0x42C9050CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A36 *((volatile unsigned int*)(0x42C90510UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A37 *((volatile unsigned int*)(0x42C90514UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A38 *((volatile unsigned int*)(0x42C90518UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A39 *((volatile unsigned int*)(0x42C9051CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A40 *((volatile unsigned int*)(0x42C90520UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A41 *((volatile unsigned int*)(0x42C90524UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A42 *((volatile unsigned int*)(0x42C90528UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A43 *((volatile unsigned int*)(0x42C9052CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A44 *((volatile unsigned int*)(0x42C90530UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A45 *((volatile unsigned int*)(0x42C90534UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A46 *((volatile unsigned int*)(0x42C90538UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_A47 *((volatile unsigned int*)(0x42C9053CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC0 *((volatile unsigned int*)(0x42C90560UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC1 *((volatile unsigned int*)(0x42C90564UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC2 *((volatile unsigned int*)(0x42C90568UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC3 *((volatile unsigned int*)(0x42C9056CUL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC4 *((volatile unsigned int*)(0x42C90570UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_MBC5 *((volatile unsigned int*)(0x42C90574UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_SA *((volatile unsigned int*)(0x42C90578UL)) +#define bFM3_ETHERNET_MAC0_MAR21H_AE *((volatile unsigned int*)(0x42C9057CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A0 *((volatile unsigned int*)(0x42C90580UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A1 *((volatile unsigned int*)(0x42C90584UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A2 *((volatile unsigned int*)(0x42C90588UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A3 *((volatile unsigned int*)(0x42C9058CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A4 *((volatile unsigned int*)(0x42C90590UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A5 *((volatile unsigned int*)(0x42C90594UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A6 *((volatile unsigned int*)(0x42C90598UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A7 *((volatile unsigned int*)(0x42C9059CUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A8 *((volatile unsigned int*)(0x42C905A0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A9 *((volatile unsigned int*)(0x42C905A4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A10 *((volatile unsigned int*)(0x42C905A8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A11 *((volatile unsigned int*)(0x42C905ACUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A12 *((volatile unsigned int*)(0x42C905B0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A13 *((volatile unsigned int*)(0x42C905B4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A14 *((volatile unsigned int*)(0x42C905B8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A15 *((volatile unsigned int*)(0x42C905BCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A16 *((volatile unsigned int*)(0x42C905C0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A17 *((volatile unsigned int*)(0x42C905C4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A18 *((volatile unsigned int*)(0x42C905C8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A19 *((volatile unsigned int*)(0x42C905CCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A20 *((volatile unsigned int*)(0x42C905D0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A21 *((volatile unsigned int*)(0x42C905D4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A22 *((volatile unsigned int*)(0x42C905D8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A23 *((volatile unsigned int*)(0x42C905DCUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A24 *((volatile unsigned int*)(0x42C905E0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A25 *((volatile unsigned int*)(0x42C905E4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A26 *((volatile unsigned int*)(0x42C905E8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A27 *((volatile unsigned int*)(0x42C905ECUL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A28 *((volatile unsigned int*)(0x42C905F0UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A29 *((volatile unsigned int*)(0x42C905F4UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A30 *((volatile unsigned int*)(0x42C905F8UL)) +#define bFM3_ETHERNET_MAC0_MAR21L_A31 *((volatile unsigned int*)(0x42C905FCUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A32 *((volatile unsigned int*)(0x42C90600UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A33 *((volatile unsigned int*)(0x42C90604UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A34 *((volatile unsigned int*)(0x42C90608UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A35 *((volatile unsigned int*)(0x42C9060CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A36 *((volatile unsigned int*)(0x42C90610UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A37 *((volatile unsigned int*)(0x42C90614UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A38 *((volatile unsigned int*)(0x42C90618UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A39 *((volatile unsigned int*)(0x42C9061CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A40 *((volatile unsigned int*)(0x42C90620UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A41 *((volatile unsigned int*)(0x42C90624UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A42 *((volatile unsigned int*)(0x42C90628UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A43 *((volatile unsigned int*)(0x42C9062CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A44 *((volatile unsigned int*)(0x42C90630UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A45 *((volatile unsigned int*)(0x42C90634UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A46 *((volatile unsigned int*)(0x42C90638UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_A47 *((volatile unsigned int*)(0x42C9063CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC0 *((volatile unsigned int*)(0x42C90660UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC1 *((volatile unsigned int*)(0x42C90664UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC2 *((volatile unsigned int*)(0x42C90668UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC3 *((volatile unsigned int*)(0x42C9066CUL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC4 *((volatile unsigned int*)(0x42C90670UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_MBC5 *((volatile unsigned int*)(0x42C90674UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_SA *((volatile unsigned int*)(0x42C90678UL)) +#define bFM3_ETHERNET_MAC0_MAR22H_AE *((volatile unsigned int*)(0x42C9067CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A0 *((volatile unsigned int*)(0x42C90680UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A1 *((volatile unsigned int*)(0x42C90684UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A2 *((volatile unsigned int*)(0x42C90688UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A3 *((volatile unsigned int*)(0x42C9068CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A4 *((volatile unsigned int*)(0x42C90690UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A5 *((volatile unsigned int*)(0x42C90694UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A6 *((volatile unsigned int*)(0x42C90698UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A7 *((volatile unsigned int*)(0x42C9069CUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A8 *((volatile unsigned int*)(0x42C906A0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A9 *((volatile unsigned int*)(0x42C906A4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A10 *((volatile unsigned int*)(0x42C906A8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A11 *((volatile unsigned int*)(0x42C906ACUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A12 *((volatile unsigned int*)(0x42C906B0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A13 *((volatile unsigned int*)(0x42C906B4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A14 *((volatile unsigned int*)(0x42C906B8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A15 *((volatile unsigned int*)(0x42C906BCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A16 *((volatile unsigned int*)(0x42C906C0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A17 *((volatile unsigned int*)(0x42C906C4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A18 *((volatile unsigned int*)(0x42C906C8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A19 *((volatile unsigned int*)(0x42C906CCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A20 *((volatile unsigned int*)(0x42C906D0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A21 *((volatile unsigned int*)(0x42C906D4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A22 *((volatile unsigned int*)(0x42C906D8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A23 *((volatile unsigned int*)(0x42C906DCUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A24 *((volatile unsigned int*)(0x42C906E0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A25 *((volatile unsigned int*)(0x42C906E4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A26 *((volatile unsigned int*)(0x42C906E8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A27 *((volatile unsigned int*)(0x42C906ECUL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A28 *((volatile unsigned int*)(0x42C906F0UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A29 *((volatile unsigned int*)(0x42C906F4UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A30 *((volatile unsigned int*)(0x42C906F8UL)) +#define bFM3_ETHERNET_MAC0_MAR22L_A31 *((volatile unsigned int*)(0x42C906FCUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A32 *((volatile unsigned int*)(0x42C90700UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A33 *((volatile unsigned int*)(0x42C90704UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A34 *((volatile unsigned int*)(0x42C90708UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A35 *((volatile unsigned int*)(0x42C9070CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A36 *((volatile unsigned int*)(0x42C90710UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A37 *((volatile unsigned int*)(0x42C90714UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A38 *((volatile unsigned int*)(0x42C90718UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A39 *((volatile unsigned int*)(0x42C9071CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A40 *((volatile unsigned int*)(0x42C90720UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A41 *((volatile unsigned int*)(0x42C90724UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A42 *((volatile unsigned int*)(0x42C90728UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A43 *((volatile unsigned int*)(0x42C9072CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A44 *((volatile unsigned int*)(0x42C90730UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A45 *((volatile unsigned int*)(0x42C90734UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A46 *((volatile unsigned int*)(0x42C90738UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_A47 *((volatile unsigned int*)(0x42C9073CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC0 *((volatile unsigned int*)(0x42C90760UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC1 *((volatile unsigned int*)(0x42C90764UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC2 *((volatile unsigned int*)(0x42C90768UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC3 *((volatile unsigned int*)(0x42C9076CUL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC4 *((volatile unsigned int*)(0x42C90770UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_MBC5 *((volatile unsigned int*)(0x42C90774UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_SA *((volatile unsigned int*)(0x42C90778UL)) +#define bFM3_ETHERNET_MAC0_MAR23H_AE *((volatile unsigned int*)(0x42C9077CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A0 *((volatile unsigned int*)(0x42C90780UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A1 *((volatile unsigned int*)(0x42C90784UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A2 *((volatile unsigned int*)(0x42C90788UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A3 *((volatile unsigned int*)(0x42C9078CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A4 *((volatile unsigned int*)(0x42C90790UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A5 *((volatile unsigned int*)(0x42C90794UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A6 *((volatile unsigned int*)(0x42C90798UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A7 *((volatile unsigned int*)(0x42C9079CUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A8 *((volatile unsigned int*)(0x42C907A0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A9 *((volatile unsigned int*)(0x42C907A4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A10 *((volatile unsigned int*)(0x42C907A8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A11 *((volatile unsigned int*)(0x42C907ACUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A12 *((volatile unsigned int*)(0x42C907B0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A13 *((volatile unsigned int*)(0x42C907B4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A14 *((volatile unsigned int*)(0x42C907B8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A15 *((volatile unsigned int*)(0x42C907BCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A16 *((volatile unsigned int*)(0x42C907C0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A17 *((volatile unsigned int*)(0x42C907C4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A18 *((volatile unsigned int*)(0x42C907C8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A19 *((volatile unsigned int*)(0x42C907CCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A20 *((volatile unsigned int*)(0x42C907D0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A21 *((volatile unsigned int*)(0x42C907D4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A22 *((volatile unsigned int*)(0x42C907D8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A23 *((volatile unsigned int*)(0x42C907DCUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A24 *((volatile unsigned int*)(0x42C907E0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A25 *((volatile unsigned int*)(0x42C907E4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A26 *((volatile unsigned int*)(0x42C907E8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A27 *((volatile unsigned int*)(0x42C907ECUL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A28 *((volatile unsigned int*)(0x42C907F0UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A29 *((volatile unsigned int*)(0x42C907F4UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A30 *((volatile unsigned int*)(0x42C907F8UL)) +#define bFM3_ETHERNET_MAC0_MAR23L_A31 *((volatile unsigned int*)(0x42C907FCUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A32 *((volatile unsigned int*)(0x42C90800UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A33 *((volatile unsigned int*)(0x42C90804UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A34 *((volatile unsigned int*)(0x42C90808UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A35 *((volatile unsigned int*)(0x42C9080CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A36 *((volatile unsigned int*)(0x42C90810UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A37 *((volatile unsigned int*)(0x42C90814UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A38 *((volatile unsigned int*)(0x42C90818UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A39 *((volatile unsigned int*)(0x42C9081CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A40 *((volatile unsigned int*)(0x42C90820UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A41 *((volatile unsigned int*)(0x42C90824UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A42 *((volatile unsigned int*)(0x42C90828UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A43 *((volatile unsigned int*)(0x42C9082CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A44 *((volatile unsigned int*)(0x42C90830UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A45 *((volatile unsigned int*)(0x42C90834UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A46 *((volatile unsigned int*)(0x42C90838UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_A47 *((volatile unsigned int*)(0x42C9083CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC0 *((volatile unsigned int*)(0x42C90860UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC1 *((volatile unsigned int*)(0x42C90864UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC2 *((volatile unsigned int*)(0x42C90868UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC3 *((volatile unsigned int*)(0x42C9086CUL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC4 *((volatile unsigned int*)(0x42C90870UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_MBC5 *((volatile unsigned int*)(0x42C90874UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_SA *((volatile unsigned int*)(0x42C90878UL)) +#define bFM3_ETHERNET_MAC0_MAR24H_AE *((volatile unsigned int*)(0x42C9087CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A0 *((volatile unsigned int*)(0x42C90880UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A1 *((volatile unsigned int*)(0x42C90884UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A2 *((volatile unsigned int*)(0x42C90888UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A3 *((volatile unsigned int*)(0x42C9088CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A4 *((volatile unsigned int*)(0x42C90890UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A5 *((volatile unsigned int*)(0x42C90894UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A6 *((volatile unsigned int*)(0x42C90898UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A7 *((volatile unsigned int*)(0x42C9089CUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A8 *((volatile unsigned int*)(0x42C908A0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A9 *((volatile unsigned int*)(0x42C908A4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A10 *((volatile unsigned int*)(0x42C908A8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A11 *((volatile unsigned int*)(0x42C908ACUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A12 *((volatile unsigned int*)(0x42C908B0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A13 *((volatile unsigned int*)(0x42C908B4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A14 *((volatile unsigned int*)(0x42C908B8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A15 *((volatile unsigned int*)(0x42C908BCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A16 *((volatile unsigned int*)(0x42C908C0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A17 *((volatile unsigned int*)(0x42C908C4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A18 *((volatile unsigned int*)(0x42C908C8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A19 *((volatile unsigned int*)(0x42C908CCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A20 *((volatile unsigned int*)(0x42C908D0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A21 *((volatile unsigned int*)(0x42C908D4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A22 *((volatile unsigned int*)(0x42C908D8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A23 *((volatile unsigned int*)(0x42C908DCUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A24 *((volatile unsigned int*)(0x42C908E0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A25 *((volatile unsigned int*)(0x42C908E4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A26 *((volatile unsigned int*)(0x42C908E8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A27 *((volatile unsigned int*)(0x42C908ECUL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A28 *((volatile unsigned int*)(0x42C908F0UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A29 *((volatile unsigned int*)(0x42C908F4UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A30 *((volatile unsigned int*)(0x42C908F8UL)) +#define bFM3_ETHERNET_MAC0_MAR24L_A31 *((volatile unsigned int*)(0x42C908FCUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A32 *((volatile unsigned int*)(0x42C90900UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A33 *((volatile unsigned int*)(0x42C90904UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A34 *((volatile unsigned int*)(0x42C90908UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A35 *((volatile unsigned int*)(0x42C9090CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A36 *((volatile unsigned int*)(0x42C90910UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A37 *((volatile unsigned int*)(0x42C90914UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A38 *((volatile unsigned int*)(0x42C90918UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A39 *((volatile unsigned int*)(0x42C9091CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A40 *((volatile unsigned int*)(0x42C90920UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A41 *((volatile unsigned int*)(0x42C90924UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A42 *((volatile unsigned int*)(0x42C90928UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A43 *((volatile unsigned int*)(0x42C9092CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A44 *((volatile unsigned int*)(0x42C90930UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A45 *((volatile unsigned int*)(0x42C90934UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A46 *((volatile unsigned int*)(0x42C90938UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_A47 *((volatile unsigned int*)(0x42C9093CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC0 *((volatile unsigned int*)(0x42C90960UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC1 *((volatile unsigned int*)(0x42C90964UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC2 *((volatile unsigned int*)(0x42C90968UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC3 *((volatile unsigned int*)(0x42C9096CUL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC4 *((volatile unsigned int*)(0x42C90970UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_MBC5 *((volatile unsigned int*)(0x42C90974UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_SA *((volatile unsigned int*)(0x42C90978UL)) +#define bFM3_ETHERNET_MAC0_MAR25H_AE *((volatile unsigned int*)(0x42C9097CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A0 *((volatile unsigned int*)(0x42C90980UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A1 *((volatile unsigned int*)(0x42C90984UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A2 *((volatile unsigned int*)(0x42C90988UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A3 *((volatile unsigned int*)(0x42C9098CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A4 *((volatile unsigned int*)(0x42C90990UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A5 *((volatile unsigned int*)(0x42C90994UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A6 *((volatile unsigned int*)(0x42C90998UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A7 *((volatile unsigned int*)(0x42C9099CUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A8 *((volatile unsigned int*)(0x42C909A0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A9 *((volatile unsigned int*)(0x42C909A4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A10 *((volatile unsigned int*)(0x42C909A8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A11 *((volatile unsigned int*)(0x42C909ACUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A12 *((volatile unsigned int*)(0x42C909B0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A13 *((volatile unsigned int*)(0x42C909B4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A14 *((volatile unsigned int*)(0x42C909B8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A15 *((volatile unsigned int*)(0x42C909BCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A16 *((volatile unsigned int*)(0x42C909C0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A17 *((volatile unsigned int*)(0x42C909C4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A18 *((volatile unsigned int*)(0x42C909C8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A19 *((volatile unsigned int*)(0x42C909CCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A20 *((volatile unsigned int*)(0x42C909D0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A21 *((volatile unsigned int*)(0x42C909D4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A22 *((volatile unsigned int*)(0x42C909D8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A23 *((volatile unsigned int*)(0x42C909DCUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A24 *((volatile unsigned int*)(0x42C909E0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A25 *((volatile unsigned int*)(0x42C909E4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A26 *((volatile unsigned int*)(0x42C909E8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A27 *((volatile unsigned int*)(0x42C909ECUL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A28 *((volatile unsigned int*)(0x42C909F0UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A29 *((volatile unsigned int*)(0x42C909F4UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A30 *((volatile unsigned int*)(0x42C909F8UL)) +#define bFM3_ETHERNET_MAC0_MAR25L_A31 *((volatile unsigned int*)(0x42C909FCUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A32 *((volatile unsigned int*)(0x42C90A00UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A33 *((volatile unsigned int*)(0x42C90A04UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A34 *((volatile unsigned int*)(0x42C90A08UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A35 *((volatile unsigned int*)(0x42C90A0CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A36 *((volatile unsigned int*)(0x42C90A10UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A37 *((volatile unsigned int*)(0x42C90A14UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A38 *((volatile unsigned int*)(0x42C90A18UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A39 *((volatile unsigned int*)(0x42C90A1CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A40 *((volatile unsigned int*)(0x42C90A20UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A41 *((volatile unsigned int*)(0x42C90A24UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A42 *((volatile unsigned int*)(0x42C90A28UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A43 *((volatile unsigned int*)(0x42C90A2CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A44 *((volatile unsigned int*)(0x42C90A30UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A45 *((volatile unsigned int*)(0x42C90A34UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A46 *((volatile unsigned int*)(0x42C90A38UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_A47 *((volatile unsigned int*)(0x42C90A3CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC0 *((volatile unsigned int*)(0x42C90A60UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC1 *((volatile unsigned int*)(0x42C90A64UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC2 *((volatile unsigned int*)(0x42C90A68UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC3 *((volatile unsigned int*)(0x42C90A6CUL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC4 *((volatile unsigned int*)(0x42C90A70UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_MBC5 *((volatile unsigned int*)(0x42C90A74UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_SA *((volatile unsigned int*)(0x42C90A78UL)) +#define bFM3_ETHERNET_MAC0_MAR26H_AE *((volatile unsigned int*)(0x42C90A7CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A0 *((volatile unsigned int*)(0x42C90A80UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A1 *((volatile unsigned int*)(0x42C90A84UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A2 *((volatile unsigned int*)(0x42C90A88UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A3 *((volatile unsigned int*)(0x42C90A8CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A4 *((volatile unsigned int*)(0x42C90A90UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A5 *((volatile unsigned int*)(0x42C90A94UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A6 *((volatile unsigned int*)(0x42C90A98UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A7 *((volatile unsigned int*)(0x42C90A9CUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A8 *((volatile unsigned int*)(0x42C90AA0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A9 *((volatile unsigned int*)(0x42C90AA4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A10 *((volatile unsigned int*)(0x42C90AA8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A11 *((volatile unsigned int*)(0x42C90AACUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A12 *((volatile unsigned int*)(0x42C90AB0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A13 *((volatile unsigned int*)(0x42C90AB4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A14 *((volatile unsigned int*)(0x42C90AB8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A15 *((volatile unsigned int*)(0x42C90ABCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A16 *((volatile unsigned int*)(0x42C90AC0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A17 *((volatile unsigned int*)(0x42C90AC4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A18 *((volatile unsigned int*)(0x42C90AC8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A19 *((volatile unsigned int*)(0x42C90ACCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A20 *((volatile unsigned int*)(0x42C90AD0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A21 *((volatile unsigned int*)(0x42C90AD4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A22 *((volatile unsigned int*)(0x42C90AD8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A23 *((volatile unsigned int*)(0x42C90ADCUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A24 *((volatile unsigned int*)(0x42C90AE0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A25 *((volatile unsigned int*)(0x42C90AE4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A26 *((volatile unsigned int*)(0x42C90AE8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A27 *((volatile unsigned int*)(0x42C90AECUL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A28 *((volatile unsigned int*)(0x42C90AF0UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A29 *((volatile unsigned int*)(0x42C90AF4UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A30 *((volatile unsigned int*)(0x42C90AF8UL)) +#define bFM3_ETHERNET_MAC0_MAR26L_A31 *((volatile unsigned int*)(0x42C90AFCUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A32 *((volatile unsigned int*)(0x42C90B00UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A33 *((volatile unsigned int*)(0x42C90B04UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A34 *((volatile unsigned int*)(0x42C90B08UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A35 *((volatile unsigned int*)(0x42C90B0CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A36 *((volatile unsigned int*)(0x42C90B10UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A37 *((volatile unsigned int*)(0x42C90B14UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A38 *((volatile unsigned int*)(0x42C90B18UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A39 *((volatile unsigned int*)(0x42C90B1CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A40 *((volatile unsigned int*)(0x42C90B20UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A41 *((volatile unsigned int*)(0x42C90B24UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A42 *((volatile unsigned int*)(0x42C90B28UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A43 *((volatile unsigned int*)(0x42C90B2CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A44 *((volatile unsigned int*)(0x42C90B30UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A45 *((volatile unsigned int*)(0x42C90B34UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A46 *((volatile unsigned int*)(0x42C90B38UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_A47 *((volatile unsigned int*)(0x42C90B3CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC0 *((volatile unsigned int*)(0x42C90B60UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC1 *((volatile unsigned int*)(0x42C90B64UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC2 *((volatile unsigned int*)(0x42C90B68UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC3 *((volatile unsigned int*)(0x42C90B6CUL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC4 *((volatile unsigned int*)(0x42C90B70UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_MBC5 *((volatile unsigned int*)(0x42C90B74UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_SA *((volatile unsigned int*)(0x42C90B78UL)) +#define bFM3_ETHERNET_MAC0_MAR27H_AE *((volatile unsigned int*)(0x42C90B7CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A0 *((volatile unsigned int*)(0x42C90B80UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A1 *((volatile unsigned int*)(0x42C90B84UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A2 *((volatile unsigned int*)(0x42C90B88UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A3 *((volatile unsigned int*)(0x42C90B8CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A4 *((volatile unsigned int*)(0x42C90B90UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A5 *((volatile unsigned int*)(0x42C90B94UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A6 *((volatile unsigned int*)(0x42C90B98UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A7 *((volatile unsigned int*)(0x42C90B9CUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A8 *((volatile unsigned int*)(0x42C90BA0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A9 *((volatile unsigned int*)(0x42C90BA4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A10 *((volatile unsigned int*)(0x42C90BA8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A11 *((volatile unsigned int*)(0x42C90BACUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A12 *((volatile unsigned int*)(0x42C90BB0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A13 *((volatile unsigned int*)(0x42C90BB4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A14 *((volatile unsigned int*)(0x42C90BB8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A15 *((volatile unsigned int*)(0x42C90BBCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A16 *((volatile unsigned int*)(0x42C90BC0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A17 *((volatile unsigned int*)(0x42C90BC4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A18 *((volatile unsigned int*)(0x42C90BC8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A19 *((volatile unsigned int*)(0x42C90BCCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A20 *((volatile unsigned int*)(0x42C90BD0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A21 *((volatile unsigned int*)(0x42C90BD4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A22 *((volatile unsigned int*)(0x42C90BD8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A23 *((volatile unsigned int*)(0x42C90BDCUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A24 *((volatile unsigned int*)(0x42C90BE0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A25 *((volatile unsigned int*)(0x42C90BE4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A26 *((volatile unsigned int*)(0x42C90BE8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A27 *((volatile unsigned int*)(0x42C90BECUL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A28 *((volatile unsigned int*)(0x42C90BF0UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A29 *((volatile unsigned int*)(0x42C90BF4UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A30 *((volatile unsigned int*)(0x42C90BF8UL)) +#define bFM3_ETHERNET_MAC0_MAR27L_A31 *((volatile unsigned int*)(0x42C90BFCUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A32 *((volatile unsigned int*)(0x42C90C00UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A33 *((volatile unsigned int*)(0x42C90C04UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A34 *((volatile unsigned int*)(0x42C90C08UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A35 *((volatile unsigned int*)(0x42C90C0CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A36 *((volatile unsigned int*)(0x42C90C10UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A37 *((volatile unsigned int*)(0x42C90C14UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A38 *((volatile unsigned int*)(0x42C90C18UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A39 *((volatile unsigned int*)(0x42C90C1CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A40 *((volatile unsigned int*)(0x42C90C20UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A41 *((volatile unsigned int*)(0x42C90C24UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A42 *((volatile unsigned int*)(0x42C90C28UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A43 *((volatile unsigned int*)(0x42C90C2CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A44 *((volatile unsigned int*)(0x42C90C30UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A45 *((volatile unsigned int*)(0x42C90C34UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A46 *((volatile unsigned int*)(0x42C90C38UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_A47 *((volatile unsigned int*)(0x42C90C3CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC0 *((volatile unsigned int*)(0x42C90C60UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC1 *((volatile unsigned int*)(0x42C90C64UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC2 *((volatile unsigned int*)(0x42C90C68UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC3 *((volatile unsigned int*)(0x42C90C6CUL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC4 *((volatile unsigned int*)(0x42C90C70UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_MBC5 *((volatile unsigned int*)(0x42C90C74UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_SA *((volatile unsigned int*)(0x42C90C78UL)) +#define bFM3_ETHERNET_MAC0_MAR28H_AE *((volatile unsigned int*)(0x42C90C7CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A0 *((volatile unsigned int*)(0x42C90C80UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A1 *((volatile unsigned int*)(0x42C90C84UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A2 *((volatile unsigned int*)(0x42C90C88UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A3 *((volatile unsigned int*)(0x42C90C8CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A4 *((volatile unsigned int*)(0x42C90C90UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A5 *((volatile unsigned int*)(0x42C90C94UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A6 *((volatile unsigned int*)(0x42C90C98UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A7 *((volatile unsigned int*)(0x42C90C9CUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A8 *((volatile unsigned int*)(0x42C90CA0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A9 *((volatile unsigned int*)(0x42C90CA4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A10 *((volatile unsigned int*)(0x42C90CA8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A11 *((volatile unsigned int*)(0x42C90CACUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A12 *((volatile unsigned int*)(0x42C90CB0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A13 *((volatile unsigned int*)(0x42C90CB4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A14 *((volatile unsigned int*)(0x42C90CB8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A15 *((volatile unsigned int*)(0x42C90CBCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A16 *((volatile unsigned int*)(0x42C90CC0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A17 *((volatile unsigned int*)(0x42C90CC4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A18 *((volatile unsigned int*)(0x42C90CC8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A19 *((volatile unsigned int*)(0x42C90CCCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A20 *((volatile unsigned int*)(0x42C90CD0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A21 *((volatile unsigned int*)(0x42C90CD4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A22 *((volatile unsigned int*)(0x42C90CD8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A23 *((volatile unsigned int*)(0x42C90CDCUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A24 *((volatile unsigned int*)(0x42C90CE0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A25 *((volatile unsigned int*)(0x42C90CE4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A26 *((volatile unsigned int*)(0x42C90CE8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A27 *((volatile unsigned int*)(0x42C90CECUL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A28 *((volatile unsigned int*)(0x42C90CF0UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A29 *((volatile unsigned int*)(0x42C90CF4UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A30 *((volatile unsigned int*)(0x42C90CF8UL)) +#define bFM3_ETHERNET_MAC0_MAR28L_A31 *((volatile unsigned int*)(0x42C90CFCUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A32 *((volatile unsigned int*)(0x42C90D00UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A33 *((volatile unsigned int*)(0x42C90D04UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A34 *((volatile unsigned int*)(0x42C90D08UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A35 *((volatile unsigned int*)(0x42C90D0CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A36 *((volatile unsigned int*)(0x42C90D10UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A37 *((volatile unsigned int*)(0x42C90D14UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A38 *((volatile unsigned int*)(0x42C90D18UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A39 *((volatile unsigned int*)(0x42C90D1CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A40 *((volatile unsigned int*)(0x42C90D20UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A41 *((volatile unsigned int*)(0x42C90D24UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A42 *((volatile unsigned int*)(0x42C90D28UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A43 *((volatile unsigned int*)(0x42C90D2CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A44 *((volatile unsigned int*)(0x42C90D30UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A45 *((volatile unsigned int*)(0x42C90D34UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A46 *((volatile unsigned int*)(0x42C90D38UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_A47 *((volatile unsigned int*)(0x42C90D3CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC0 *((volatile unsigned int*)(0x42C90D60UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC1 *((volatile unsigned int*)(0x42C90D64UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC2 *((volatile unsigned int*)(0x42C90D68UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC3 *((volatile unsigned int*)(0x42C90D6CUL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC4 *((volatile unsigned int*)(0x42C90D70UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_MBC5 *((volatile unsigned int*)(0x42C90D74UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_SA *((volatile unsigned int*)(0x42C90D78UL)) +#define bFM3_ETHERNET_MAC0_MAR29H_AE *((volatile unsigned int*)(0x42C90D7CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A0 *((volatile unsigned int*)(0x42C90D80UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A1 *((volatile unsigned int*)(0x42C90D84UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A2 *((volatile unsigned int*)(0x42C90D88UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A3 *((volatile unsigned int*)(0x42C90D8CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A4 *((volatile unsigned int*)(0x42C90D90UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A5 *((volatile unsigned int*)(0x42C90D94UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A6 *((volatile unsigned int*)(0x42C90D98UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A7 *((volatile unsigned int*)(0x42C90D9CUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A8 *((volatile unsigned int*)(0x42C90DA0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A9 *((volatile unsigned int*)(0x42C90DA4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A10 *((volatile unsigned int*)(0x42C90DA8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A11 *((volatile unsigned int*)(0x42C90DACUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A12 *((volatile unsigned int*)(0x42C90DB0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A13 *((volatile unsigned int*)(0x42C90DB4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A14 *((volatile unsigned int*)(0x42C90DB8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A15 *((volatile unsigned int*)(0x42C90DBCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A16 *((volatile unsigned int*)(0x42C90DC0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A17 *((volatile unsigned int*)(0x42C90DC4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A18 *((volatile unsigned int*)(0x42C90DC8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A19 *((volatile unsigned int*)(0x42C90DCCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A20 *((volatile unsigned int*)(0x42C90DD0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A21 *((volatile unsigned int*)(0x42C90DD4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A22 *((volatile unsigned int*)(0x42C90DD8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A23 *((volatile unsigned int*)(0x42C90DDCUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A24 *((volatile unsigned int*)(0x42C90DE0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A25 *((volatile unsigned int*)(0x42C90DE4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A26 *((volatile unsigned int*)(0x42C90DE8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A27 *((volatile unsigned int*)(0x42C90DECUL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A28 *((volatile unsigned int*)(0x42C90DF0UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A29 *((volatile unsigned int*)(0x42C90DF4UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A30 *((volatile unsigned int*)(0x42C90DF8UL)) +#define bFM3_ETHERNET_MAC0_MAR29L_A31 *((volatile unsigned int*)(0x42C90DFCUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A32 *((volatile unsigned int*)(0x42C90E00UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A33 *((volatile unsigned int*)(0x42C90E04UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A34 *((volatile unsigned int*)(0x42C90E08UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A35 *((volatile unsigned int*)(0x42C90E0CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A36 *((volatile unsigned int*)(0x42C90E10UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A37 *((volatile unsigned int*)(0x42C90E14UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A38 *((volatile unsigned int*)(0x42C90E18UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A39 *((volatile unsigned int*)(0x42C90E1CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A40 *((volatile unsigned int*)(0x42C90E20UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A41 *((volatile unsigned int*)(0x42C90E24UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A42 *((volatile unsigned int*)(0x42C90E28UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A43 *((volatile unsigned int*)(0x42C90E2CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A44 *((volatile unsigned int*)(0x42C90E30UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A45 *((volatile unsigned int*)(0x42C90E34UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A46 *((volatile unsigned int*)(0x42C90E38UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_A47 *((volatile unsigned int*)(0x42C90E3CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC0 *((volatile unsigned int*)(0x42C90E60UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC1 *((volatile unsigned int*)(0x42C90E64UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC2 *((volatile unsigned int*)(0x42C90E68UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC3 *((volatile unsigned int*)(0x42C90E6CUL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC4 *((volatile unsigned int*)(0x42C90E70UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_MBC5 *((volatile unsigned int*)(0x42C90E74UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_SA *((volatile unsigned int*)(0x42C90E78UL)) +#define bFM3_ETHERNET_MAC0_MAR30H_AE *((volatile unsigned int*)(0x42C90E7CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A0 *((volatile unsigned int*)(0x42C90E80UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A1 *((volatile unsigned int*)(0x42C90E84UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A2 *((volatile unsigned int*)(0x42C90E88UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A3 *((volatile unsigned int*)(0x42C90E8CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A4 *((volatile unsigned int*)(0x42C90E90UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A5 *((volatile unsigned int*)(0x42C90E94UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A6 *((volatile unsigned int*)(0x42C90E98UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A7 *((volatile unsigned int*)(0x42C90E9CUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A8 *((volatile unsigned int*)(0x42C90EA0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A9 *((volatile unsigned int*)(0x42C90EA4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A10 *((volatile unsigned int*)(0x42C90EA8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A11 *((volatile unsigned int*)(0x42C90EACUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A12 *((volatile unsigned int*)(0x42C90EB0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A13 *((volatile unsigned int*)(0x42C90EB4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A14 *((volatile unsigned int*)(0x42C90EB8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A15 *((volatile unsigned int*)(0x42C90EBCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A16 *((volatile unsigned int*)(0x42C90EC0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A17 *((volatile unsigned int*)(0x42C90EC4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A18 *((volatile unsigned int*)(0x42C90EC8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A19 *((volatile unsigned int*)(0x42C90ECCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A20 *((volatile unsigned int*)(0x42C90ED0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A21 *((volatile unsigned int*)(0x42C90ED4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A22 *((volatile unsigned int*)(0x42C90ED8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A23 *((volatile unsigned int*)(0x42C90EDCUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A24 *((volatile unsigned int*)(0x42C90EE0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A25 *((volatile unsigned int*)(0x42C90EE4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A26 *((volatile unsigned int*)(0x42C90EE8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A27 *((volatile unsigned int*)(0x42C90EECUL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A28 *((volatile unsigned int*)(0x42C90EF0UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A29 *((volatile unsigned int*)(0x42C90EF4UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A30 *((volatile unsigned int*)(0x42C90EF8UL)) +#define bFM3_ETHERNET_MAC0_MAR30L_A31 *((volatile unsigned int*)(0x42C90EFCUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A32 *((volatile unsigned int*)(0x42C90F00UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A33 *((volatile unsigned int*)(0x42C90F04UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A34 *((volatile unsigned int*)(0x42C90F08UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A35 *((volatile unsigned int*)(0x42C90F0CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A36 *((volatile unsigned int*)(0x42C90F10UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A37 *((volatile unsigned int*)(0x42C90F14UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A38 *((volatile unsigned int*)(0x42C90F18UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A39 *((volatile unsigned int*)(0x42C90F1CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A40 *((volatile unsigned int*)(0x42C90F20UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A41 *((volatile unsigned int*)(0x42C90F24UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A42 *((volatile unsigned int*)(0x42C90F28UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A43 *((volatile unsigned int*)(0x42C90F2CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A44 *((volatile unsigned int*)(0x42C90F30UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A45 *((volatile unsigned int*)(0x42C90F34UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A46 *((volatile unsigned int*)(0x42C90F38UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_A47 *((volatile unsigned int*)(0x42C90F3CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC0 *((volatile unsigned int*)(0x42C90F60UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC1 *((volatile unsigned int*)(0x42C90F64UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC2 *((volatile unsigned int*)(0x42C90F68UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC3 *((volatile unsigned int*)(0x42C90F6CUL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC4 *((volatile unsigned int*)(0x42C90F70UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_MBC5 *((volatile unsigned int*)(0x42C90F74UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_SA *((volatile unsigned int*)(0x42C90F78UL)) +#define bFM3_ETHERNET_MAC0_MAR31H_AE *((volatile unsigned int*)(0x42C90F7CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A0 *((volatile unsigned int*)(0x42C90F80UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A1 *((volatile unsigned int*)(0x42C90F84UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A2 *((volatile unsigned int*)(0x42C90F88UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A3 *((volatile unsigned int*)(0x42C90F8CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A4 *((volatile unsigned int*)(0x42C90F90UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A5 *((volatile unsigned int*)(0x42C90F94UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A6 *((volatile unsigned int*)(0x42C90F98UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A7 *((volatile unsigned int*)(0x42C90F9CUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A8 *((volatile unsigned int*)(0x42C90FA0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A9 *((volatile unsigned int*)(0x42C90FA4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A10 *((volatile unsigned int*)(0x42C90FA8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A11 *((volatile unsigned int*)(0x42C90FACUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A12 *((volatile unsigned int*)(0x42C90FB0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A13 *((volatile unsigned int*)(0x42C90FB4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A14 *((volatile unsigned int*)(0x42C90FB8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A15 *((volatile unsigned int*)(0x42C90FBCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A16 *((volatile unsigned int*)(0x42C90FC0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A17 *((volatile unsigned int*)(0x42C90FC4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A18 *((volatile unsigned int*)(0x42C90FC8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A19 *((volatile unsigned int*)(0x42C90FCCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A20 *((volatile unsigned int*)(0x42C90FD0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A21 *((volatile unsigned int*)(0x42C90FD4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A22 *((volatile unsigned int*)(0x42C90FD8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A23 *((volatile unsigned int*)(0x42C90FDCUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A24 *((volatile unsigned int*)(0x42C90FE0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A25 *((volatile unsigned int*)(0x42C90FE4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A26 *((volatile unsigned int*)(0x42C90FE8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A27 *((volatile unsigned int*)(0x42C90FECUL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A28 *((volatile unsigned int*)(0x42C90FF0UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A29 *((volatile unsigned int*)(0x42C90FF4UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A30 *((volatile unsigned int*)(0x42C90FF8UL)) +#define bFM3_ETHERNET_MAC0_MAR31L_A31 *((volatile unsigned int*)(0x42C90FFCUL)) +#define bFM3_ETHERNET_MAC0_BMR_SWR *((volatile unsigned int*)(0x42CA0000UL)) +#define bFM3_ETHERNET_MAC0_BMR_DA *((volatile unsigned int*)(0x42CA0004UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL0 *((volatile unsigned int*)(0x42CA0008UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL1 *((volatile unsigned int*)(0x42CA000CUL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL2 *((volatile unsigned int*)(0x42CA0010UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL3 *((volatile unsigned int*)(0x42CA0014UL)) +#define bFM3_ETHERNET_MAC0_BMR_DSL4 *((volatile unsigned int*)(0x42CA0018UL)) +#define bFM3_ETHERNET_MAC0_BMR_ATDS *((volatile unsigned int*)(0x42CA001CUL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL0 *((volatile unsigned int*)(0x42CA0020UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL1 *((volatile unsigned int*)(0x42CA0024UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL2 *((volatile unsigned int*)(0x42CA0028UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL3 *((volatile unsigned int*)(0x42CA002CUL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL4 *((volatile unsigned int*)(0x42CA0030UL)) +#define bFM3_ETHERNET_MAC0_BMR_PBL5 *((volatile unsigned int*)(0x42CA0034UL)) +#define bFM3_ETHERNET_MAC0_BMR_PR0 *((volatile unsigned int*)(0x42CA0038UL)) +#define bFM3_ETHERNET_MAC0_BMR_PR1 *((volatile unsigned int*)(0x42CA003CUL)) +#define bFM3_ETHERNET_MAC0_BMR_FB *((volatile unsigned int*)(0x42CA0040UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL0 *((volatile unsigned int*)(0x42CA0044UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL1 *((volatile unsigned int*)(0x42CA0048UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL2 *((volatile unsigned int*)(0x42CA004CUL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL3 *((volatile unsigned int*)(0x42CA0050UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL4 *((volatile unsigned int*)(0x42CA0054UL)) +#define bFM3_ETHERNET_MAC0_BMR_RPBL5 *((volatile unsigned int*)(0x42CA0058UL)) +#define bFM3_ETHERNET_MAC0_BMR_USP *((volatile unsigned int*)(0x42CA005CUL)) +#define bFM3_ETHERNET_MAC0_BMR_8XPBL *((volatile unsigned int*)(0x42CA0060UL)) +#define bFM3_ETHERNET_MAC0_BMR_AAL *((volatile unsigned int*)(0x42CA0064UL)) +#define bFM3_ETHERNET_MAC0_BMR_MB *((volatile unsigned int*)(0x42CA0068UL)) +#define bFM3_ETHERNET_MAC0_BMR_TXPR *((volatile unsigned int*)(0x42CA006CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD0 *((volatile unsigned int*)(0x42CA0080UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD1 *((volatile unsigned int*)(0x42CA0084UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD2 *((volatile unsigned int*)(0x42CA0088UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD3 *((volatile unsigned int*)(0x42CA008CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD4 *((volatile unsigned int*)(0x42CA0090UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD5 *((volatile unsigned int*)(0x42CA0094UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD6 *((volatile unsigned int*)(0x42CA0098UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD7 *((volatile unsigned int*)(0x42CA009CUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD8 *((volatile unsigned int*)(0x42CA00A0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD9 *((volatile unsigned int*)(0x42CA00A4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD10 *((volatile unsigned int*)(0x42CA00A8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD11 *((volatile unsigned int*)(0x42CA00ACUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD12 *((volatile unsigned int*)(0x42CA00B0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD13 *((volatile unsigned int*)(0x42CA00B4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD14 *((volatile unsigned int*)(0x42CA00B8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD15 *((volatile unsigned int*)(0x42CA00BCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD16 *((volatile unsigned int*)(0x42CA00C0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD17 *((volatile unsigned int*)(0x42CA00C4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD18 *((volatile unsigned int*)(0x42CA00C8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD19 *((volatile unsigned int*)(0x42CA00CCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD20 *((volatile unsigned int*)(0x42CA00D0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD21 *((volatile unsigned int*)(0x42CA00D4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD22 *((volatile unsigned int*)(0x42CA00D8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD23 *((volatile unsigned int*)(0x42CA00DCUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD24 *((volatile unsigned int*)(0x42CA00E0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD25 *((volatile unsigned int*)(0x42CA00E4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD26 *((volatile unsigned int*)(0x42CA00E8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD27 *((volatile unsigned int*)(0x42CA00ECUL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD28 *((volatile unsigned int*)(0x42CA00F0UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD29 *((volatile unsigned int*)(0x42CA00F4UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD30 *((volatile unsigned int*)(0x42CA00F8UL)) +#define bFM3_ETHERNET_MAC0_TPDR_TPD31 *((volatile unsigned int*)(0x42CA00FCUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD0 *((volatile unsigned int*)(0x42CA0100UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD1 *((volatile unsigned int*)(0x42CA0104UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD2 *((volatile unsigned int*)(0x42CA0108UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD3 *((volatile unsigned int*)(0x42CA010CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD4 *((volatile unsigned int*)(0x42CA0110UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD5 *((volatile unsigned int*)(0x42CA0114UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD6 *((volatile unsigned int*)(0x42CA0118UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD7 *((volatile unsigned int*)(0x42CA011CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD8 *((volatile unsigned int*)(0x42CA0120UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD9 *((volatile unsigned int*)(0x42CA0124UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD10 *((volatile unsigned int*)(0x42CA0128UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD11 *((volatile unsigned int*)(0x42CA012CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD12 *((volatile unsigned int*)(0x42CA0130UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD13 *((volatile unsigned int*)(0x42CA0134UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD14 *((volatile unsigned int*)(0x42CA0138UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD15 *((volatile unsigned int*)(0x42CA013CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD16 *((volatile unsigned int*)(0x42CA0140UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD17 *((volatile unsigned int*)(0x42CA0144UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD18 *((volatile unsigned int*)(0x42CA0148UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD19 *((volatile unsigned int*)(0x42CA014CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD20 *((volatile unsigned int*)(0x42CA0150UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD21 *((volatile unsigned int*)(0x42CA0154UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD22 *((volatile unsigned int*)(0x42CA0158UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD23 *((volatile unsigned int*)(0x42CA015CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD24 *((volatile unsigned int*)(0x42CA0160UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD25 *((volatile unsigned int*)(0x42CA0164UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD26 *((volatile unsigned int*)(0x42CA0168UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD27 *((volatile unsigned int*)(0x42CA016CUL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD28 *((volatile unsigned int*)(0x42CA0170UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD29 *((volatile unsigned int*)(0x42CA0174UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD30 *((volatile unsigned int*)(0x42CA0178UL)) +#define bFM3_ETHERNET_MAC0_RPDR_RPD31 *((volatile unsigned int*)(0x42CA017CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL2 *((volatile unsigned int*)(0x42CA0188UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL3 *((volatile unsigned int*)(0x42CA018CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL4 *((volatile unsigned int*)(0x42CA0190UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL5 *((volatile unsigned int*)(0x42CA0194UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL6 *((volatile unsigned int*)(0x42CA0198UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL7 *((volatile unsigned int*)(0x42CA019CUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL8 *((volatile unsigned int*)(0x42CA01A0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL9 *((volatile unsigned int*)(0x42CA01A4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL10 *((volatile unsigned int*)(0x42CA01A8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL11 *((volatile unsigned int*)(0x42CA01ACUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL12 *((volatile unsigned int*)(0x42CA01B0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL13 *((volatile unsigned int*)(0x42CA01B4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL14 *((volatile unsigned int*)(0x42CA01B8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL15 *((volatile unsigned int*)(0x42CA01BCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL16 *((volatile unsigned int*)(0x42CA01C0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL17 *((volatile unsigned int*)(0x42CA01C4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL18 *((volatile unsigned int*)(0x42CA01C8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL19 *((volatile unsigned int*)(0x42CA01CCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL20 *((volatile unsigned int*)(0x42CA01D0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL21 *((volatile unsigned int*)(0x42CA01D4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL22 *((volatile unsigned int*)(0x42CA01D8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL23 *((volatile unsigned int*)(0x42CA01DCUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL24 *((volatile unsigned int*)(0x42CA01E0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL25 *((volatile unsigned int*)(0x42CA01E4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL26 *((volatile unsigned int*)(0x42CA01E8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL27 *((volatile unsigned int*)(0x42CA01ECUL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL28 *((volatile unsigned int*)(0x42CA01F0UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL29 *((volatile unsigned int*)(0x42CA01F4UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL30 *((volatile unsigned int*)(0x42CA01F8UL)) +#define bFM3_ETHERNET_MAC0_RDLAR_SRL31 *((volatile unsigned int*)(0x42CA01FCUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL2 *((volatile unsigned int*)(0x42CA0208UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL3 *((volatile unsigned int*)(0x42CA020CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL4 *((volatile unsigned int*)(0x42CA0210UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL5 *((volatile unsigned int*)(0x42CA0214UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL6 *((volatile unsigned int*)(0x42CA0218UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL7 *((volatile unsigned int*)(0x42CA021CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL8 *((volatile unsigned int*)(0x42CA0220UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL9 *((volatile unsigned int*)(0x42CA0224UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL10 *((volatile unsigned int*)(0x42CA0228UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL11 *((volatile unsigned int*)(0x42CA022CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL12 *((volatile unsigned int*)(0x42CA0230UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL13 *((volatile unsigned int*)(0x42CA0234UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL14 *((volatile unsigned int*)(0x42CA0238UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL15 *((volatile unsigned int*)(0x42CA023CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL16 *((volatile unsigned int*)(0x42CA0240UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL17 *((volatile unsigned int*)(0x42CA0244UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL18 *((volatile unsigned int*)(0x42CA0248UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL19 *((volatile unsigned int*)(0x42CA024CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL20 *((volatile unsigned int*)(0x42CA0250UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL21 *((volatile unsigned int*)(0x42CA0254UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL22 *((volatile unsigned int*)(0x42CA0258UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL23 *((volatile unsigned int*)(0x42CA025CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL24 *((volatile unsigned int*)(0x42CA0260UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL25 *((volatile unsigned int*)(0x42CA0264UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL26 *((volatile unsigned int*)(0x42CA0268UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL27 *((volatile unsigned int*)(0x42CA026CUL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL28 *((volatile unsigned int*)(0x42CA0270UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL29 *((volatile unsigned int*)(0x42CA0274UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL30 *((volatile unsigned int*)(0x42CA0278UL)) +#define bFM3_ETHERNET_MAC0_TDLAR_STL31 *((volatile unsigned int*)(0x42CA027CUL)) +#define bFM3_ETHERNET_MAC0_SR_TI *((volatile unsigned int*)(0x42CA0280UL)) +#define bFM3_ETHERNET_MAC0_SR_TPS *((volatile unsigned int*)(0x42CA0284UL)) +#define bFM3_ETHERNET_MAC0_SR_TU *((volatile unsigned int*)(0x42CA0288UL)) +#define bFM3_ETHERNET_MAC0_SR_TJT *((volatile unsigned int*)(0x42CA028CUL)) +#define bFM3_ETHERNET_MAC0_SR_OVF *((volatile unsigned int*)(0x42CA0290UL)) +#define bFM3_ETHERNET_MAC0_SR_UNF *((volatile unsigned int*)(0x42CA0294UL)) +#define bFM3_ETHERNET_MAC0_SR_RI *((volatile unsigned int*)(0x42CA0298UL)) +#define bFM3_ETHERNET_MAC0_SR_RU *((volatile unsigned int*)(0x42CA029CUL)) +#define bFM3_ETHERNET_MAC0_SR_RPS *((volatile unsigned int*)(0x42CA02A0UL)) +#define bFM3_ETHERNET_MAC0_SR_RWT *((volatile unsigned int*)(0x42CA02A4UL)) +#define bFM3_ETHERNET_MAC0_SR_ETI *((volatile unsigned int*)(0x42CA02A8UL)) +#define bFM3_ETHERNET_MAC0_SR_FBI *((volatile unsigned int*)(0x42CA02B4UL)) +#define bFM3_ETHERNET_MAC0_SR_ERI *((volatile unsigned int*)(0x42CA02B8UL)) +#define bFM3_ETHERNET_MAC0_SR_AIS *((volatile unsigned int*)(0x42CA02BCUL)) +#define bFM3_ETHERNET_MAC0_SR_NIS *((volatile unsigned int*)(0x42CA02C0UL)) +#define bFM3_ETHERNET_MAC0_SR_RS0 *((volatile unsigned int*)(0x42CA02C4UL)) +#define bFM3_ETHERNET_MAC0_SR_RS1 *((volatile unsigned int*)(0x42CA02C8UL)) +#define bFM3_ETHERNET_MAC0_SR_RS2 *((volatile unsigned int*)(0x42CA02CCUL)) +#define bFM3_ETHERNET_MAC0_SR_TS0 *((volatile unsigned int*)(0x42CA02D0UL)) +#define bFM3_ETHERNET_MAC0_SR_TS1 *((volatile unsigned int*)(0x42CA02D4UL)) +#define bFM3_ETHERNET_MAC0_SR_TS2 *((volatile unsigned int*)(0x42CA02D8UL)) +#define bFM3_ETHERNET_MAC0_SR_EB0 *((volatile unsigned int*)(0x42CA02DCUL)) +#define bFM3_ETHERNET_MAC0_SR_EB1 *((volatile unsigned int*)(0x42CA02E0UL)) +#define bFM3_ETHERNET_MAC0_SR_EB2 *((volatile unsigned int*)(0x42CA02E4UL)) +#define bFM3_ETHERNET_MAC0_SR_GLI *((volatile unsigned int*)(0x42CA02E8UL)) +#define bFM3_ETHERNET_MAC0_SR_GMI *((volatile unsigned int*)(0x42CA02ECUL)) +#define bFM3_ETHERNET_MAC0_SR_GPI *((volatile unsigned int*)(0x42CA02F0UL)) +#define bFM3_ETHERNET_MAC0_SR_TTI *((volatile unsigned int*)(0x42CA02F4UL)) +#define bFM3_ETHERNET_MAC0_SR_GLPII *((volatile unsigned int*)(0x42CA02F8UL)) +#define bFM3_ETHERNET_MAC0_OMR_SR *((volatile unsigned int*)(0x42CA0304UL)) +#define bFM3_ETHERNET_MAC0_OMR_OSF *((volatile unsigned int*)(0x42CA0308UL)) +#define bFM3_ETHERNET_MAC0_OMR_RTC0 *((volatile unsigned int*)(0x42CA030CUL)) +#define bFM3_ETHERNET_MAC0_OMR_RTC1 *((volatile unsigned int*)(0x42CA0310UL)) +#define bFM3_ETHERNET_MAC0_OMR_FUF *((volatile unsigned int*)(0x42CA0318UL)) +#define bFM3_ETHERNET_MAC0_OMR_FEF *((volatile unsigned int*)(0x42CA031CUL)) +#define bFM3_ETHERNET_MAC0_OMR_ST *((volatile unsigned int*)(0x42CA0334UL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC0 *((volatile unsigned int*)(0x42CA0338UL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC1 *((volatile unsigned int*)(0x42CA033CUL)) +#define bFM3_ETHERNET_MAC0_OMR_TTC2 *((volatile unsigned int*)(0x42CA0340UL)) +#define bFM3_ETHERNET_MAC0_OMR_FTF *((volatile unsigned int*)(0x42CA0350UL)) +#define bFM3_ETHERNET_MAC0_OMR_TSF *((volatile unsigned int*)(0x42CA0354UL)) +#define bFM3_ETHERNET_MAC0_OMR_DFF *((volatile unsigned int*)(0x42CA0360UL)) +#define bFM3_ETHERNET_MAC0_OMR_RSF *((volatile unsigned int*)(0x42CA0364UL)) +#define bFM3_ETHERNET_MAC0_OMR_DT *((volatile unsigned int*)(0x42CA0368UL)) +#define bFM3_ETHERNET_MAC0_IER_TIE *((volatile unsigned int*)(0x42CA0380UL)) +#define bFM3_ETHERNET_MAC0_IER_TSE *((volatile unsigned int*)(0x42CA0384UL)) +#define bFM3_ETHERNET_MAC0_IER_TUE *((volatile unsigned int*)(0x42CA0388UL)) +#define bFM3_ETHERNET_MAC0_IER_TJE *((volatile unsigned int*)(0x42CA038CUL)) +#define bFM3_ETHERNET_MAC0_IER_OVE *((volatile unsigned int*)(0x42CA0390UL)) +#define bFM3_ETHERNET_MAC0_IER_UNE *((volatile unsigned int*)(0x42CA0394UL)) +#define bFM3_ETHERNET_MAC0_IER_RIE *((volatile unsigned int*)(0x42CA0398UL)) +#define bFM3_ETHERNET_MAC0_IER_RUE *((volatile unsigned int*)(0x42CA039CUL)) +#define bFM3_ETHERNET_MAC0_IER_RSE *((volatile unsigned int*)(0x42CA03A0UL)) +#define bFM3_ETHERNET_MAC0_IER_RWE *((volatile unsigned int*)(0x42CA03A4UL)) +#define bFM3_ETHERNET_MAC0_IER_ETE *((volatile unsigned int*)(0x42CA03A8UL)) +#define bFM3_ETHERNET_MAC0_IER_FBE *((volatile unsigned int*)(0x42CA03B4UL)) +#define bFM3_ETHERNET_MAC0_IER_ERE *((volatile unsigned int*)(0x42CA03B8UL)) +#define bFM3_ETHERNET_MAC0_IER_AIE *((volatile unsigned int*)(0x42CA03BCUL)) +#define bFM3_ETHERNET_MAC0_IER_NIE *((volatile unsigned int*)(0x42CA03C0UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42CA0400UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42CA0404UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42CA0408UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42CA040CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42CA0410UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42CA0414UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42CA0418UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42CA041CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42CA0420UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42CA0424UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42CA0428UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42CA042CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42CA0430UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42CA0434UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42CA0438UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42CA043CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH *((volatile unsigned int*)(0x42CA0440UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42CA0444UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42CA0448UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42CA044CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42CA0450UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42CA0454UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42CA0458UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42CA045CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42CA0460UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42CA0464UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42CA0468UL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42CA046CUL)) +#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF *((volatile unsigned int*)(0x42CA0470UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0 *((volatile unsigned int*)(0x42CA0480UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1 *((volatile unsigned int*)(0x42CA0484UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2 *((volatile unsigned int*)(0x42CA0488UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3 *((volatile unsigned int*)(0x42CA048CUL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4 *((volatile unsigned int*)(0x42CA0490UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5 *((volatile unsigned int*)(0x42CA0494UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6 *((volatile unsigned int*)(0x42CA0498UL)) +#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7 *((volatile unsigned int*)(0x42CA049CUL)) +#define bFM3_ETHERNET_MAC0_AHBSR_AHBS *((volatile unsigned int*)(0x42CA0580UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42CA0900UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42CA0904UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42CA0908UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42CA090CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42CA0910UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42CA0914UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42CA0918UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42CA091CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42CA0920UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42CA0924UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42CA0928UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42CA092CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42CA0930UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42CA0934UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42CA0938UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42CA093CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42CA0940UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42CA0944UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42CA0948UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42CA094CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42CA0950UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42CA0954UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42CA0958UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42CA095CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42CA0960UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42CA0964UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42CA0968UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42CA096CUL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42CA0970UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42CA0974UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42CA0978UL)) +#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42CA097CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42CA0980UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42CA0984UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42CA0988UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42CA098CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42CA0990UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42CA0994UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42CA0998UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42CA099CUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42CA09A0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42CA09A4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42CA09A8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42CA09ACUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42CA09B0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42CA09B4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42CA09B8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42CA09BCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42CA09C0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42CA09C4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42CA09C8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42CA09CCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42CA09D0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42CA09D4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42CA09D8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42CA09DCUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42CA09E0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42CA09E4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42CA09E8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42CA09ECUL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42CA09F0UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42CA09F4UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42CA09F8UL)) +#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42CA09FCUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42CA0A00UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42CA0A04UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42CA0A08UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42CA0A0CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42CA0A10UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42CA0A14UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42CA0A18UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42CA0A1CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42CA0A20UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42CA0A24UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42CA0A28UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42CA0A2CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42CA0A30UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42CA0A34UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42CA0A38UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42CA0A3CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42CA0A40UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42CA0A44UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42CA0A48UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42CA0A4CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42CA0A50UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42CA0A54UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42CA0A58UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42CA0A5CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42CA0A60UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42CA0A64UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42CA0A68UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42CA0A6CUL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42CA0A70UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42CA0A74UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42CA0A78UL)) +#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42CA0A7CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42CA0A80UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42CA0A84UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42CA0A88UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42CA0A8CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42CA0A90UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42CA0A94UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42CA0A98UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42CA0A9CUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42CA0AA0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42CA0AA4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42CA0AA8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42CA0AACUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42CA0AB0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42CA0AB4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42CA0AB8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42CA0ABCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42CA0AC0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42CA0AC4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42CA0AC8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42CA0ACCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42CA0AD0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42CA0AD4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42CA0AD8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42CA0ADCUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42CA0AE0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42CA0AE4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42CA0AE8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42CA0AECUL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42CA0AF0UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42CA0AF4UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42CA0AF8UL)) +#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42CA0AFCUL)) + +/* ETHERNET-MAC-CONTROL registers */ +#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE *((volatile unsigned int*)(0x42CC0000UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0 *((volatile unsigned int*)(0x42CC0020UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1 *((volatile unsigned int*)(0x42CC0024UL)) +#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL *((volatile unsigned int*)(0x42CC0070UL)) +#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0 *((volatile unsigned int*)(0x42CC0100UL)) +#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1 *((volatile unsigned int*)(0x42CC0104UL)) + +/* ETHERNET-MAC1 registers*/ +#define bFM3_ETHERNET_MAC1_MCR_RE *((volatile unsigned int*)(0x42CE0008UL)) +#define bFM3_ETHERNET_MAC1_MCR_TE *((volatile unsigned int*)(0x42CE000CUL)) +#define bFM3_ETHERNET_MAC1_MCR_DC *((volatile unsigned int*)(0x42CE0010UL)) +#define bFM3_ETHERNET_MAC1_MCR_BL0 *((volatile unsigned int*)(0x42CE0014UL)) +#define bFM3_ETHERNET_MAC1_MCR_BL1 *((volatile unsigned int*)(0x42CE0018UL)) +#define bFM3_ETHERNET_MAC1_MCR_ACS *((volatile unsigned int*)(0x42CE001CUL)) +#define bFM3_ETHERNET_MAC1_MCR_LUD *((volatile unsigned int*)(0x42CE0020UL)) +#define bFM3_ETHERNET_MAC1_MCR_DR *((volatile unsigned int*)(0x42CE0024UL)) +#define bFM3_ETHERNET_MAC1_MCR_IPC *((volatile unsigned int*)(0x42CE0028UL)) +#define bFM3_ETHERNET_MAC1_MCR_DM *((volatile unsigned int*)(0x42CE002CUL)) +#define bFM3_ETHERNET_MAC1_MCR_LM *((volatile unsigned int*)(0x42CE0030UL)) +#define bFM3_ETHERNET_MAC1_MCR_DO *((volatile unsigned int*)(0x42CE0034UL)) +#define bFM3_ETHERNET_MAC1_MCR_FES *((volatile unsigned int*)(0x42CE0038UL)) +#define bFM3_ETHERNET_MAC1_MCR_PS *((volatile unsigned int*)(0x42CE003CUL)) +#define bFM3_ETHERNET_MAC1_MCR_DCRS *((volatile unsigned int*)(0x42CE0040UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG0 *((volatile unsigned int*)(0x42CE0044UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG1 *((volatile unsigned int*)(0x42CE0048UL)) +#define bFM3_ETHERNET_MAC1_MCR_IFG2 *((volatile unsigned int*)(0x42CE004CUL)) +#define bFM3_ETHERNET_MAC1_MCR_JE *((volatile unsigned int*)(0x42CE0050UL)) +#define bFM3_ETHERNET_MAC1_MCR_BE *((volatile unsigned int*)(0x42CE0054UL)) +#define bFM3_ETHERNET_MAC1_MCR_JD *((volatile unsigned int*)(0x42CE0058UL)) +#define bFM3_ETHERNET_MAC1_MCR_WD *((volatile unsigned int*)(0x42CE005CUL)) +#define bFM3_ETHERNET_MAC1_MCR_TC *((volatile unsigned int*)(0x42CE0060UL)) +#define bFM3_ETHERNET_MAC1_MCR_CST *((volatile unsigned int*)(0x42CE0064UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PR *((volatile unsigned int*)(0x42CE0080UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HUC *((volatile unsigned int*)(0x42CE0084UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HMC *((volatile unsigned int*)(0x42CE0088UL)) +#define bFM3_ETHERNET_MAC1_MFFR_DAIF *((volatile unsigned int*)(0x42CE008CUL)) +#define bFM3_ETHERNET_MAC1_MFFR_PM *((volatile unsigned int*)(0x42CE0090UL)) +#define bFM3_ETHERNET_MAC1_MFFR_DB *((volatile unsigned int*)(0x42CE0094UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PCF0 *((volatile unsigned int*)(0x42CE0098UL)) +#define bFM3_ETHERNET_MAC1_MFFR_PCF1 *((volatile unsigned int*)(0x42CE009CUL)) +#define bFM3_ETHERNET_MAC1_MFFR_SAIF *((volatile unsigned int*)(0x42CE00A0UL)) +#define bFM3_ETHERNET_MAC1_MFFR_SAF *((volatile unsigned int*)(0x42CE00A4UL)) +#define bFM3_ETHERNET_MAC1_MFFR_HPF *((volatile unsigned int*)(0x42CE00A8UL)) +#define bFM3_ETHERNET_MAC1_MFFR_RA *((volatile unsigned int*)(0x42CE00FCUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH0 *((volatile unsigned int*)(0x42CE0100UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH1 *((volatile unsigned int*)(0x42CE0104UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH2 *((volatile unsigned int*)(0x42CE0108UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH3 *((volatile unsigned int*)(0x42CE010CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH4 *((volatile unsigned int*)(0x42CE0110UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH5 *((volatile unsigned int*)(0x42CE0114UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH6 *((volatile unsigned int*)(0x42CE0118UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH7 *((volatile unsigned int*)(0x42CE011CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH8 *((volatile unsigned int*)(0x42CE0120UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH9 *((volatile unsigned int*)(0x42CE0124UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH10 *((volatile unsigned int*)(0x42CE0128UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH11 *((volatile unsigned int*)(0x42CE012CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH12 *((volatile unsigned int*)(0x42CE0130UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH13 *((volatile unsigned int*)(0x42CE0134UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH14 *((volatile unsigned int*)(0x42CE0138UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH15 *((volatile unsigned int*)(0x42CE013CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH16 *((volatile unsigned int*)(0x42CE0140UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH17 *((volatile unsigned int*)(0x42CE0144UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH18 *((volatile unsigned int*)(0x42CE0148UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH19 *((volatile unsigned int*)(0x42CE014CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH20 *((volatile unsigned int*)(0x42CE0150UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH21 *((volatile unsigned int*)(0x42CE0154UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH22 *((volatile unsigned int*)(0x42CE0158UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH23 *((volatile unsigned int*)(0x42CE015CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH24 *((volatile unsigned int*)(0x42CE0160UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH25 *((volatile unsigned int*)(0x42CE0164UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH26 *((volatile unsigned int*)(0x42CE0168UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH27 *((volatile unsigned int*)(0x42CE016CUL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH28 *((volatile unsigned int*)(0x42CE0170UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH29 *((volatile unsigned int*)(0x42CE0174UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH30 *((volatile unsigned int*)(0x42CE0178UL)) +#define bFM3_ETHERNET_MAC1_MHTRH_HTH31 *((volatile unsigned int*)(0x42CE017CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL0 *((volatile unsigned int*)(0x42CE0180UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL1 *((volatile unsigned int*)(0x42CE0184UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL2 *((volatile unsigned int*)(0x42CE0188UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL3 *((volatile unsigned int*)(0x42CE018CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL4 *((volatile unsigned int*)(0x42CE0190UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL5 *((volatile unsigned int*)(0x42CE0194UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL6 *((volatile unsigned int*)(0x42CE0198UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL7 *((volatile unsigned int*)(0x42CE019CUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL8 *((volatile unsigned int*)(0x42CE01A0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL9 *((volatile unsigned int*)(0x42CE01A4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL10 *((volatile unsigned int*)(0x42CE01A8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL11 *((volatile unsigned int*)(0x42CE01ACUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL12 *((volatile unsigned int*)(0x42CE01B0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL13 *((volatile unsigned int*)(0x42CE01B4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL14 *((volatile unsigned int*)(0x42CE01B8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL15 *((volatile unsigned int*)(0x42CE01BCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL16 *((volatile unsigned int*)(0x42CE01C0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL17 *((volatile unsigned int*)(0x42CE01C4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL18 *((volatile unsigned int*)(0x42CE01C8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL19 *((volatile unsigned int*)(0x42CE01CCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL20 *((volatile unsigned int*)(0x42CE01D0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL21 *((volatile unsigned int*)(0x42CE01D4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL22 *((volatile unsigned int*)(0x42CE01D8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL23 *((volatile unsigned int*)(0x42CE01DCUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL24 *((volatile unsigned int*)(0x42CE01E0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL25 *((volatile unsigned int*)(0x42CE01E4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL26 *((volatile unsigned int*)(0x42CE01E8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL27 *((volatile unsigned int*)(0x42CE01ECUL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL28 *((volatile unsigned int*)(0x42CE01F0UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL29 *((volatile unsigned int*)(0x42CE01F4UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL30 *((volatile unsigned int*)(0x42CE01F8UL)) +#define bFM3_ETHERNET_MAC1_MHTRL_HTL31 *((volatile unsigned int*)(0x42CE01FCUL)) +#define bFM3_ETHERNET_MAC1_GAR_GB *((volatile unsigned int*)(0x42CE0200UL)) +#define bFM3_ETHERNET_MAC1_GAR_GW *((volatile unsigned int*)(0x42CE0204UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR0 *((volatile unsigned int*)(0x42CE0208UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR1 *((volatile unsigned int*)(0x42CE020CUL)) +#define bFM3_ETHERNET_MAC1_GAR_CR2 *((volatile unsigned int*)(0x42CE0210UL)) +#define bFM3_ETHERNET_MAC1_GAR_CR3 *((volatile unsigned int*)(0x42CE0214UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR0 *((volatile unsigned int*)(0x42CE0218UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR1 *((volatile unsigned int*)(0x42CE021CUL)) +#define bFM3_ETHERNET_MAC1_GAR_GR2 *((volatile unsigned int*)(0x42CE0220UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR3 *((volatile unsigned int*)(0x42CE0224UL)) +#define bFM3_ETHERNET_MAC1_GAR_GR4 *((volatile unsigned int*)(0x42CE0228UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA0 *((volatile unsigned int*)(0x42CE022CUL)) +#define bFM3_ETHERNET_MAC1_GAR_PA1 *((volatile unsigned int*)(0x42CE0230UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA2 *((volatile unsigned int*)(0x42CE0234UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA3 *((volatile unsigned int*)(0x42CE0238UL)) +#define bFM3_ETHERNET_MAC1_GAR_PA4 *((volatile unsigned int*)(0x42CE023CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD0 *((volatile unsigned int*)(0x42CE0280UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD1 *((volatile unsigned int*)(0x42CE0284UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD2 *((volatile unsigned int*)(0x42CE0288UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD3 *((volatile unsigned int*)(0x42CE028CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD4 *((volatile unsigned int*)(0x42CE0290UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD5 *((volatile unsigned int*)(0x42CE0294UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD6 *((volatile unsigned int*)(0x42CE0298UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD7 *((volatile unsigned int*)(0x42CE029CUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD8 *((volatile unsigned int*)(0x42CE02A0UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD9 *((volatile unsigned int*)(0x42CE02A4UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD10 *((volatile unsigned int*)(0x42CE02A8UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD11 *((volatile unsigned int*)(0x42CE02ACUL)) +#define bFM3_ETHERNET_MAC1_GDR_GD12 *((volatile unsigned int*)(0x42CE02B0UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD13 *((volatile unsigned int*)(0x42CE02B4UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD14 *((volatile unsigned int*)(0x42CE02B8UL)) +#define bFM3_ETHERNET_MAC1_GDR_GD15 *((volatile unsigned int*)(0x42CE02BCUL)) +#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA *((volatile unsigned int*)(0x42CE0300UL)) +#define bFM3_ETHERNET_MAC1_FCR_TFE *((volatile unsigned int*)(0x42CE0304UL)) +#define bFM3_ETHERNET_MAC1_FCR_RFE *((volatile unsigned int*)(0x42CE0308UL)) +#define bFM3_ETHERNET_MAC1_FCR_UP *((volatile unsigned int*)(0x42CE030CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PLT0 *((volatile unsigned int*)(0x42CE0310UL)) +#define bFM3_ETHERNET_MAC1_FCR_PLT1 *((volatile unsigned int*)(0x42CE0314UL)) +#define bFM3_ETHERNET_MAC1_FCR_DZPQ *((volatile unsigned int*)(0x42CE031CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT0 *((volatile unsigned int*)(0x42CE0340UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT1 *((volatile unsigned int*)(0x42CE0344UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT2 *((volatile unsigned int*)(0x42CE0348UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT3 *((volatile unsigned int*)(0x42CE034CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT4 *((volatile unsigned int*)(0x42CE0350UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT5 *((volatile unsigned int*)(0x42CE0354UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT6 *((volatile unsigned int*)(0x42CE0358UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT7 *((volatile unsigned int*)(0x42CE035CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT8 *((volatile unsigned int*)(0x42CE0360UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT9 *((volatile unsigned int*)(0x42CE0364UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT10 *((volatile unsigned int*)(0x42CE0368UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT11 *((volatile unsigned int*)(0x42CE036CUL)) +#define bFM3_ETHERNET_MAC1_FCR_PT12 *((volatile unsigned int*)(0x42CE0370UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT13 *((volatile unsigned int*)(0x42CE0374UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT14 *((volatile unsigned int*)(0x42CE0378UL)) +#define bFM3_ETHERNET_MAC1_FCR_PT15 *((volatile unsigned int*)(0x42CE037CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL0 *((volatile unsigned int*)(0x42CE0380UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL1 *((volatile unsigned int*)(0x42CE0384UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL2 *((volatile unsigned int*)(0x42CE0388UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL3 *((volatile unsigned int*)(0x42CE038CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL4 *((volatile unsigned int*)(0x42CE0390UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL5 *((volatile unsigned int*)(0x42CE0394UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL6 *((volatile unsigned int*)(0x42CE0398UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL7 *((volatile unsigned int*)(0x42CE039CUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL8 *((volatile unsigned int*)(0x42CE03A0UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL9 *((volatile unsigned int*)(0x42CE03A4UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL10 *((volatile unsigned int*)(0x42CE03A8UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL11 *((volatile unsigned int*)(0x42CE03ACUL)) +#define bFM3_ETHERNET_MAC1_VTR_VL12 *((volatile unsigned int*)(0x42CE03B0UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL13 *((volatile unsigned int*)(0x42CE03B4UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL14 *((volatile unsigned int*)(0x42CE03B8UL)) +#define bFM3_ETHERNET_MAC1_VTR_VL15 *((volatile unsigned int*)(0x42CE03BCUL)) +#define bFM3_ETHERNET_MAC1_VTR_ETV *((volatile unsigned int*)(0x42CE03C0UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42CE0500UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42CE0504UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42CE0508UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42CE050CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42CE0510UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42CE0514UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42CE0518UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42CE051CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42CE0520UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42CE0524UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42CE0528UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42CE052CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42CE0530UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42CE0534UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42CE0538UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42CE053CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42CE0540UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42CE0544UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42CE0548UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42CE054CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42CE0550UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42CE0554UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42CE0558UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42CE055CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42CE0560UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42CE0564UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42CE0568UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42CE056CUL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42CE0570UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42CE0574UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42CE0578UL)) +#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42CE057CUL)) +#define bFM3_ETHERNET_MAC1_PMTR_PD *((volatile unsigned int*)(0x42CE0580UL)) +#define bFM3_ETHERNET_MAC1_PMTR_MPE *((volatile unsigned int*)(0x42CE0584UL)) +#define bFM3_ETHERNET_MAC1_PMTR_WFE *((volatile unsigned int*)(0x42CE0588UL)) +#define bFM3_ETHERNET_MAC1_PMTR_MPR *((volatile unsigned int*)(0x42CE0594UL)) +#define bFM3_ETHERNET_MAC1_PMTR_WPR *((volatile unsigned int*)(0x42CE0598UL)) +#define bFM3_ETHERNET_MAC1_PMTR_GU *((volatile unsigned int*)(0x42CE05A4UL)) +#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR *((volatile unsigned int*)(0x42CE05FCUL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN *((volatile unsigned int*)(0x42CE0600UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX *((volatile unsigned int*)(0x42CE0604UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN *((volatile unsigned int*)(0x42CE0608UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX *((volatile unsigned int*)(0x42CE060CUL)) +#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST *((volatile unsigned int*)(0x42CE0620UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST *((volatile unsigned int*)(0x42CE0624UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN *((volatile unsigned int*)(0x42CE0640UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_PLS *((volatile unsigned int*)(0x42CE0644UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN *((volatile unsigned int*)(0x42CE0648UL)) +#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA *((volatile unsigned int*)(0x42CE064CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT0 *((volatile unsigned int*)(0x42CE0680UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT1 *((volatile unsigned int*)(0x42CE0684UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT2 *((volatile unsigned int*)(0x42CE0688UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT3 *((volatile unsigned int*)(0x42CE068CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT4 *((volatile unsigned int*)(0x42CE0690UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT5 *((volatile unsigned int*)(0x42CE0694UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT6 *((volatile unsigned int*)(0x42CE0698UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT7 *((volatile unsigned int*)(0x42CE069CUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT8 *((volatile unsigned int*)(0x42CE06A0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT9 *((volatile unsigned int*)(0x42CE06A4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT10 *((volatile unsigned int*)(0x42CE06A8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT11 *((volatile unsigned int*)(0x42CE06ACUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT12 *((volatile unsigned int*)(0x42CE06B0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT13 *((volatile unsigned int*)(0x42CE06B4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT14 *((volatile unsigned int*)(0x42CE06B8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_TWT15 *((volatile unsigned int*)(0x42CE06BCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT0 *((volatile unsigned int*)(0x42CE06C0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT1 *((volatile unsigned int*)(0x42CE06C4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT2 *((volatile unsigned int*)(0x42CE06C8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT3 *((volatile unsigned int*)(0x42CE06CCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT4 *((volatile unsigned int*)(0x42CE06D0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT5 *((volatile unsigned int*)(0x42CE06D4UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT6 *((volatile unsigned int*)(0x42CE06D8UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT7 *((volatile unsigned int*)(0x42CE06DCUL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT8 *((volatile unsigned int*)(0x42CE06E0UL)) +#define bFM3_ETHERNET_MAC1_LPITCR_LIT9 *((volatile unsigned int*)(0x42CE06E4UL)) +#define bFM3_ETHERNET_MAC1_ISR_RGIS *((volatile unsigned int*)(0x42CE0700UL)) +#define bFM3_ETHERNET_MAC1_ISR_PIS *((volatile unsigned int*)(0x42CE070CUL)) +#define bFM3_ETHERNET_MAC1_ISR_MIS *((volatile unsigned int*)(0x42CE0710UL)) +#define bFM3_ETHERNET_MAC1_ISR_RIS *((volatile unsigned int*)(0x42CE0714UL)) +#define bFM3_ETHERNET_MAC1_ISR_TIS *((volatile unsigned int*)(0x42CE0718UL)) +#define bFM3_ETHERNET_MAC1_ISR_COIS *((volatile unsigned int*)(0x42CE071CUL)) +#define bFM3_ETHERNET_MAC1_ISR_TSIS *((volatile unsigned int*)(0x42CE0724UL)) +#define bFM3_ETHERNET_MAC1_ISR_LPIIS *((volatile unsigned int*)(0x42CE0728UL)) +#define bFM3_ETHERNET_MAC1_IMR_RGIM *((volatile unsigned int*)(0x42CE0780UL)) +#define bFM3_ETHERNET_MAC1_IMR_PIM *((volatile unsigned int*)(0x42CE078CUL)) +#define bFM3_ETHERNET_MAC1_IMR_TSIM *((volatile unsigned int*)(0x42CE0794UL)) +#define bFM3_ETHERNET_MAC1_IMR_LPIIM *((volatile unsigned int*)(0x42CE0798UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A32 *((volatile unsigned int*)(0x42CE0800UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A33 *((volatile unsigned int*)(0x42CE0804UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A34 *((volatile unsigned int*)(0x42CE0808UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A35 *((volatile unsigned int*)(0x42CE080CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A36 *((volatile unsigned int*)(0x42CE0810UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A37 *((volatile unsigned int*)(0x42CE0814UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A38 *((volatile unsigned int*)(0x42CE0818UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A39 *((volatile unsigned int*)(0x42CE081CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A40 *((volatile unsigned int*)(0x42CE0820UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A41 *((volatile unsigned int*)(0x42CE0824UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A42 *((volatile unsigned int*)(0x42CE0828UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A43 *((volatile unsigned int*)(0x42CE082CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A44 *((volatile unsigned int*)(0x42CE0830UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A45 *((volatile unsigned int*)(0x42CE0834UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A46 *((volatile unsigned int*)(0x42CE0838UL)) +#define bFM3_ETHERNET_MAC1_MAR0H_A47 *((volatile unsigned int*)(0x42CE083CUL)) +#define bFM3_ETHERNET_MAC1_MAR0H_MO *((volatile unsigned int*)(0x42CE087CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A0 *((volatile unsigned int*)(0x42CE0880UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A1 *((volatile unsigned int*)(0x42CE0884UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A2 *((volatile unsigned int*)(0x42CE0888UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A3 *((volatile unsigned int*)(0x42CE088CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A4 *((volatile unsigned int*)(0x42CE0890UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A5 *((volatile unsigned int*)(0x42CE0894UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A6 *((volatile unsigned int*)(0x42CE0898UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A7 *((volatile unsigned int*)(0x42CE089CUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A8 *((volatile unsigned int*)(0x42CE08A0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A9 *((volatile unsigned int*)(0x42CE08A4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A10 *((volatile unsigned int*)(0x42CE08A8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A11 *((volatile unsigned int*)(0x42CE08ACUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A12 *((volatile unsigned int*)(0x42CE08B0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A13 *((volatile unsigned int*)(0x42CE08B4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A14 *((volatile unsigned int*)(0x42CE08B8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A15 *((volatile unsigned int*)(0x42CE08BCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A16 *((volatile unsigned int*)(0x42CE08C0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A17 *((volatile unsigned int*)(0x42CE08C4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A18 *((volatile unsigned int*)(0x42CE08C8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A19 *((volatile unsigned int*)(0x42CE08CCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A20 *((volatile unsigned int*)(0x42CE08D0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A21 *((volatile unsigned int*)(0x42CE08D4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A22 *((volatile unsigned int*)(0x42CE08D8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A23 *((volatile unsigned int*)(0x42CE08DCUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A24 *((volatile unsigned int*)(0x42CE08E0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A25 *((volatile unsigned int*)(0x42CE08E4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A26 *((volatile unsigned int*)(0x42CE08E8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A27 *((volatile unsigned int*)(0x42CE08ECUL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A28 *((volatile unsigned int*)(0x42CE08F0UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A29 *((volatile unsigned int*)(0x42CE08F4UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A30 *((volatile unsigned int*)(0x42CE08F8UL)) +#define bFM3_ETHERNET_MAC1_MAR0L_A31 *((volatile unsigned int*)(0x42CE08FCUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A32 *((volatile unsigned int*)(0x42CE0900UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A33 *((volatile unsigned int*)(0x42CE0904UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A34 *((volatile unsigned int*)(0x42CE0908UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A35 *((volatile unsigned int*)(0x42CE090CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A36 *((volatile unsigned int*)(0x42CE0910UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A37 *((volatile unsigned int*)(0x42CE0914UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A38 *((volatile unsigned int*)(0x42CE0918UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A39 *((volatile unsigned int*)(0x42CE091CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A40 *((volatile unsigned int*)(0x42CE0920UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A41 *((volatile unsigned int*)(0x42CE0924UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A42 *((volatile unsigned int*)(0x42CE0928UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A43 *((volatile unsigned int*)(0x42CE092CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A44 *((volatile unsigned int*)(0x42CE0930UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A45 *((volatile unsigned int*)(0x42CE0934UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A46 *((volatile unsigned int*)(0x42CE0938UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_A47 *((volatile unsigned int*)(0x42CE093CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC0 *((volatile unsigned int*)(0x42CE0960UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC1 *((volatile unsigned int*)(0x42CE0964UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC2 *((volatile unsigned int*)(0x42CE0968UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC3 *((volatile unsigned int*)(0x42CE096CUL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC4 *((volatile unsigned int*)(0x42CE0970UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_MBC5 *((volatile unsigned int*)(0x42CE0974UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_SA *((volatile unsigned int*)(0x42CE0978UL)) +#define bFM3_ETHERNET_MAC1_MAR1H_AE *((volatile unsigned int*)(0x42CE097CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A0 *((volatile unsigned int*)(0x42CE0980UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A1 *((volatile unsigned int*)(0x42CE0984UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A2 *((volatile unsigned int*)(0x42CE0988UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A3 *((volatile unsigned int*)(0x42CE098CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A4 *((volatile unsigned int*)(0x42CE0990UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A5 *((volatile unsigned int*)(0x42CE0994UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A6 *((volatile unsigned int*)(0x42CE0998UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A7 *((volatile unsigned int*)(0x42CE099CUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A8 *((volatile unsigned int*)(0x42CE09A0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A9 *((volatile unsigned int*)(0x42CE09A4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A10 *((volatile unsigned int*)(0x42CE09A8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A11 *((volatile unsigned int*)(0x42CE09ACUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A12 *((volatile unsigned int*)(0x42CE09B0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A13 *((volatile unsigned int*)(0x42CE09B4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A14 *((volatile unsigned int*)(0x42CE09B8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A15 *((volatile unsigned int*)(0x42CE09BCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A16 *((volatile unsigned int*)(0x42CE09C0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A17 *((volatile unsigned int*)(0x42CE09C4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A18 *((volatile unsigned int*)(0x42CE09C8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A19 *((volatile unsigned int*)(0x42CE09CCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A20 *((volatile unsigned int*)(0x42CE09D0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A21 *((volatile unsigned int*)(0x42CE09D4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A22 *((volatile unsigned int*)(0x42CE09D8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A23 *((volatile unsigned int*)(0x42CE09DCUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A24 *((volatile unsigned int*)(0x42CE09E0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A25 *((volatile unsigned int*)(0x42CE09E4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A26 *((volatile unsigned int*)(0x42CE09E8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A27 *((volatile unsigned int*)(0x42CE09ECUL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A28 *((volatile unsigned int*)(0x42CE09F0UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A29 *((volatile unsigned int*)(0x42CE09F4UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A30 *((volatile unsigned int*)(0x42CE09F8UL)) +#define bFM3_ETHERNET_MAC1_MAR1L_A31 *((volatile unsigned int*)(0x42CE09FCUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A32 *((volatile unsigned int*)(0x42CE0A00UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A33 *((volatile unsigned int*)(0x42CE0A04UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A34 *((volatile unsigned int*)(0x42CE0A08UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A35 *((volatile unsigned int*)(0x42CE0A0CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A36 *((volatile unsigned int*)(0x42CE0A10UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A37 *((volatile unsigned int*)(0x42CE0A14UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A38 *((volatile unsigned int*)(0x42CE0A18UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A39 *((volatile unsigned int*)(0x42CE0A1CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A40 *((volatile unsigned int*)(0x42CE0A20UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A41 *((volatile unsigned int*)(0x42CE0A24UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A42 *((volatile unsigned int*)(0x42CE0A28UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A43 *((volatile unsigned int*)(0x42CE0A2CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A44 *((volatile unsigned int*)(0x42CE0A30UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A45 *((volatile unsigned int*)(0x42CE0A34UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A46 *((volatile unsigned int*)(0x42CE0A38UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_A47 *((volatile unsigned int*)(0x42CE0A3CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC0 *((volatile unsigned int*)(0x42CE0A60UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC1 *((volatile unsigned int*)(0x42CE0A64UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC2 *((volatile unsigned int*)(0x42CE0A68UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC3 *((volatile unsigned int*)(0x42CE0A6CUL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC4 *((volatile unsigned int*)(0x42CE0A70UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_MBC5 *((volatile unsigned int*)(0x42CE0A74UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_SA *((volatile unsigned int*)(0x42CE0A78UL)) +#define bFM3_ETHERNET_MAC1_MAR2H_AE *((volatile unsigned int*)(0x42CE0A7CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A0 *((volatile unsigned int*)(0x42CE0A80UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A1 *((volatile unsigned int*)(0x42CE0A84UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A2 *((volatile unsigned int*)(0x42CE0A88UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A3 *((volatile unsigned int*)(0x42CE0A8CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A4 *((volatile unsigned int*)(0x42CE0A90UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A5 *((volatile unsigned int*)(0x42CE0A94UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A6 *((volatile unsigned int*)(0x42CE0A98UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A7 *((volatile unsigned int*)(0x42CE0A9CUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A8 *((volatile unsigned int*)(0x42CE0AA0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A9 *((volatile unsigned int*)(0x42CE0AA4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A10 *((volatile unsigned int*)(0x42CE0AA8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A11 *((volatile unsigned int*)(0x42CE0AACUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A12 *((volatile unsigned int*)(0x42CE0AB0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A13 *((volatile unsigned int*)(0x42CE0AB4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A14 *((volatile unsigned int*)(0x42CE0AB8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A15 *((volatile unsigned int*)(0x42CE0ABCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A16 *((volatile unsigned int*)(0x42CE0AC0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A17 *((volatile unsigned int*)(0x42CE0AC4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A18 *((volatile unsigned int*)(0x42CE0AC8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A19 *((volatile unsigned int*)(0x42CE0ACCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A20 *((volatile unsigned int*)(0x42CE0AD0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A21 *((volatile unsigned int*)(0x42CE0AD4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A22 *((volatile unsigned int*)(0x42CE0AD8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A23 *((volatile unsigned int*)(0x42CE0ADCUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A24 *((volatile unsigned int*)(0x42CE0AE0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A25 *((volatile unsigned int*)(0x42CE0AE4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A26 *((volatile unsigned int*)(0x42CE0AE8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A27 *((volatile unsigned int*)(0x42CE0AECUL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A28 *((volatile unsigned int*)(0x42CE0AF0UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A29 *((volatile unsigned int*)(0x42CE0AF4UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A30 *((volatile unsigned int*)(0x42CE0AF8UL)) +#define bFM3_ETHERNET_MAC1_MAR2L_A31 *((volatile unsigned int*)(0x42CE0AFCUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A32 *((volatile unsigned int*)(0x42CE0B00UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A33 *((volatile unsigned int*)(0x42CE0B04UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A34 *((volatile unsigned int*)(0x42CE0B08UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A35 *((volatile unsigned int*)(0x42CE0B0CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A36 *((volatile unsigned int*)(0x42CE0B10UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A37 *((volatile unsigned int*)(0x42CE0B14UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A38 *((volatile unsigned int*)(0x42CE0B18UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A39 *((volatile unsigned int*)(0x42CE0B1CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A40 *((volatile unsigned int*)(0x42CE0B20UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A41 *((volatile unsigned int*)(0x42CE0B24UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A42 *((volatile unsigned int*)(0x42CE0B28UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A43 *((volatile unsigned int*)(0x42CE0B2CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A44 *((volatile unsigned int*)(0x42CE0B30UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A45 *((volatile unsigned int*)(0x42CE0B34UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A46 *((volatile unsigned int*)(0x42CE0B38UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_A47 *((volatile unsigned int*)(0x42CE0B3CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC0 *((volatile unsigned int*)(0x42CE0B60UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC1 *((volatile unsigned int*)(0x42CE0B64UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC2 *((volatile unsigned int*)(0x42CE0B68UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC3 *((volatile unsigned int*)(0x42CE0B6CUL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC4 *((volatile unsigned int*)(0x42CE0B70UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_MBC5 *((volatile unsigned int*)(0x42CE0B74UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_SA *((volatile unsigned int*)(0x42CE0B78UL)) +#define bFM3_ETHERNET_MAC1_MAR3H_AE *((volatile unsigned int*)(0x42CE0B7CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A0 *((volatile unsigned int*)(0x42CE0B80UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A1 *((volatile unsigned int*)(0x42CE0B84UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A2 *((volatile unsigned int*)(0x42CE0B88UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A3 *((volatile unsigned int*)(0x42CE0B8CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A4 *((volatile unsigned int*)(0x42CE0B90UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A5 *((volatile unsigned int*)(0x42CE0B94UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A6 *((volatile unsigned int*)(0x42CE0B98UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A7 *((volatile unsigned int*)(0x42CE0B9CUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A8 *((volatile unsigned int*)(0x42CE0BA0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A9 *((volatile unsigned int*)(0x42CE0BA4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A10 *((volatile unsigned int*)(0x42CE0BA8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A11 *((volatile unsigned int*)(0x42CE0BACUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A12 *((volatile unsigned int*)(0x42CE0BB0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A13 *((volatile unsigned int*)(0x42CE0BB4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A14 *((volatile unsigned int*)(0x42CE0BB8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A15 *((volatile unsigned int*)(0x42CE0BBCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A16 *((volatile unsigned int*)(0x42CE0BC0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A17 *((volatile unsigned int*)(0x42CE0BC4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A18 *((volatile unsigned int*)(0x42CE0BC8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A19 *((volatile unsigned int*)(0x42CE0BCCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A20 *((volatile unsigned int*)(0x42CE0BD0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A21 *((volatile unsigned int*)(0x42CE0BD4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A22 *((volatile unsigned int*)(0x42CE0BD8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A23 *((volatile unsigned int*)(0x42CE0BDCUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A24 *((volatile unsigned int*)(0x42CE0BE0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A25 *((volatile unsigned int*)(0x42CE0BE4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A26 *((volatile unsigned int*)(0x42CE0BE8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A27 *((volatile unsigned int*)(0x42CE0BECUL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A28 *((volatile unsigned int*)(0x42CE0BF0UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A29 *((volatile unsigned int*)(0x42CE0BF4UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A30 *((volatile unsigned int*)(0x42CE0BF8UL)) +#define bFM3_ETHERNET_MAC1_MAR3L_A31 *((volatile unsigned int*)(0x42CE0BFCUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A32 *((volatile unsigned int*)(0x42CE0C00UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A33 *((volatile unsigned int*)(0x42CE0C04UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A34 *((volatile unsigned int*)(0x42CE0C08UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A35 *((volatile unsigned int*)(0x42CE0C0CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A36 *((volatile unsigned int*)(0x42CE0C10UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A37 *((volatile unsigned int*)(0x42CE0C14UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A38 *((volatile unsigned int*)(0x42CE0C18UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A39 *((volatile unsigned int*)(0x42CE0C1CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A40 *((volatile unsigned int*)(0x42CE0C20UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A41 *((volatile unsigned int*)(0x42CE0C24UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A42 *((volatile unsigned int*)(0x42CE0C28UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A43 *((volatile unsigned int*)(0x42CE0C2CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A44 *((volatile unsigned int*)(0x42CE0C30UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A45 *((volatile unsigned int*)(0x42CE0C34UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A46 *((volatile unsigned int*)(0x42CE0C38UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_A47 *((volatile unsigned int*)(0x42CE0C3CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC0 *((volatile unsigned int*)(0x42CE0C60UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC1 *((volatile unsigned int*)(0x42CE0C64UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC2 *((volatile unsigned int*)(0x42CE0C68UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC3 *((volatile unsigned int*)(0x42CE0C6CUL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC4 *((volatile unsigned int*)(0x42CE0C70UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_MBC5 *((volatile unsigned int*)(0x42CE0C74UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_SA *((volatile unsigned int*)(0x42CE0C78UL)) +#define bFM3_ETHERNET_MAC1_MAR4H_AE *((volatile unsigned int*)(0x42CE0C7CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A0 *((volatile unsigned int*)(0x42CE0C80UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A1 *((volatile unsigned int*)(0x42CE0C84UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A2 *((volatile unsigned int*)(0x42CE0C88UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A3 *((volatile unsigned int*)(0x42CE0C8CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A4 *((volatile unsigned int*)(0x42CE0C90UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A5 *((volatile unsigned int*)(0x42CE0C94UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A6 *((volatile unsigned int*)(0x42CE0C98UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A7 *((volatile unsigned int*)(0x42CE0C9CUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A8 *((volatile unsigned int*)(0x42CE0CA0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A9 *((volatile unsigned int*)(0x42CE0CA4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A10 *((volatile unsigned int*)(0x42CE0CA8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A11 *((volatile unsigned int*)(0x42CE0CACUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A12 *((volatile unsigned int*)(0x42CE0CB0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A13 *((volatile unsigned int*)(0x42CE0CB4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A14 *((volatile unsigned int*)(0x42CE0CB8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A15 *((volatile unsigned int*)(0x42CE0CBCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A16 *((volatile unsigned int*)(0x42CE0CC0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A17 *((volatile unsigned int*)(0x42CE0CC4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A18 *((volatile unsigned int*)(0x42CE0CC8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A19 *((volatile unsigned int*)(0x42CE0CCCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A20 *((volatile unsigned int*)(0x42CE0CD0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A21 *((volatile unsigned int*)(0x42CE0CD4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A22 *((volatile unsigned int*)(0x42CE0CD8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A23 *((volatile unsigned int*)(0x42CE0CDCUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A24 *((volatile unsigned int*)(0x42CE0CE0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A25 *((volatile unsigned int*)(0x42CE0CE4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A26 *((volatile unsigned int*)(0x42CE0CE8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A27 *((volatile unsigned int*)(0x42CE0CECUL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A28 *((volatile unsigned int*)(0x42CE0CF0UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A29 *((volatile unsigned int*)(0x42CE0CF4UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A30 *((volatile unsigned int*)(0x42CE0CF8UL)) +#define bFM3_ETHERNET_MAC1_MAR4L_A31 *((volatile unsigned int*)(0x42CE0CFCUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A32 *((volatile unsigned int*)(0x42CE0D00UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A33 *((volatile unsigned int*)(0x42CE0D04UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A34 *((volatile unsigned int*)(0x42CE0D08UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A35 *((volatile unsigned int*)(0x42CE0D0CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A36 *((volatile unsigned int*)(0x42CE0D10UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A37 *((volatile unsigned int*)(0x42CE0D14UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A38 *((volatile unsigned int*)(0x42CE0D18UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A39 *((volatile unsigned int*)(0x42CE0D1CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A40 *((volatile unsigned int*)(0x42CE0D20UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A41 *((volatile unsigned int*)(0x42CE0D24UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A42 *((volatile unsigned int*)(0x42CE0D28UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A43 *((volatile unsigned int*)(0x42CE0D2CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A44 *((volatile unsigned int*)(0x42CE0D30UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A45 *((volatile unsigned int*)(0x42CE0D34UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A46 *((volatile unsigned int*)(0x42CE0D38UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_A47 *((volatile unsigned int*)(0x42CE0D3CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC0 *((volatile unsigned int*)(0x42CE0D60UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC1 *((volatile unsigned int*)(0x42CE0D64UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC2 *((volatile unsigned int*)(0x42CE0D68UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC3 *((volatile unsigned int*)(0x42CE0D6CUL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC4 *((volatile unsigned int*)(0x42CE0D70UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_MBC5 *((volatile unsigned int*)(0x42CE0D74UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_SA *((volatile unsigned int*)(0x42CE0D78UL)) +#define bFM3_ETHERNET_MAC1_MAR5H_AE *((volatile unsigned int*)(0x42CE0D7CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A0 *((volatile unsigned int*)(0x42CE0D80UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A1 *((volatile unsigned int*)(0x42CE0D84UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A2 *((volatile unsigned int*)(0x42CE0D88UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A3 *((volatile unsigned int*)(0x42CE0D8CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A4 *((volatile unsigned int*)(0x42CE0D90UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A5 *((volatile unsigned int*)(0x42CE0D94UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A6 *((volatile unsigned int*)(0x42CE0D98UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A7 *((volatile unsigned int*)(0x42CE0D9CUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A8 *((volatile unsigned int*)(0x42CE0DA0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A9 *((volatile unsigned int*)(0x42CE0DA4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A10 *((volatile unsigned int*)(0x42CE0DA8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A11 *((volatile unsigned int*)(0x42CE0DACUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A12 *((volatile unsigned int*)(0x42CE0DB0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A13 *((volatile unsigned int*)(0x42CE0DB4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A14 *((volatile unsigned int*)(0x42CE0DB8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A15 *((volatile unsigned int*)(0x42CE0DBCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A16 *((volatile unsigned int*)(0x42CE0DC0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A17 *((volatile unsigned int*)(0x42CE0DC4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A18 *((volatile unsigned int*)(0x42CE0DC8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A19 *((volatile unsigned int*)(0x42CE0DCCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A20 *((volatile unsigned int*)(0x42CE0DD0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A21 *((volatile unsigned int*)(0x42CE0DD4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A22 *((volatile unsigned int*)(0x42CE0DD8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A23 *((volatile unsigned int*)(0x42CE0DDCUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A24 *((volatile unsigned int*)(0x42CE0DE0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A25 *((volatile unsigned int*)(0x42CE0DE4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A26 *((volatile unsigned int*)(0x42CE0DE8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A27 *((volatile unsigned int*)(0x42CE0DECUL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A28 *((volatile unsigned int*)(0x42CE0DF0UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A29 *((volatile unsigned int*)(0x42CE0DF4UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A30 *((volatile unsigned int*)(0x42CE0DF8UL)) +#define bFM3_ETHERNET_MAC1_MAR5L_A31 *((volatile unsigned int*)(0x42CE0DFCUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A32 *((volatile unsigned int*)(0x42CE0E00UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A33 *((volatile unsigned int*)(0x42CE0E04UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A34 *((volatile unsigned int*)(0x42CE0E08UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A35 *((volatile unsigned int*)(0x42CE0E0CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A36 *((volatile unsigned int*)(0x42CE0E10UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A37 *((volatile unsigned int*)(0x42CE0E14UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A38 *((volatile unsigned int*)(0x42CE0E18UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A39 *((volatile unsigned int*)(0x42CE0E1CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A40 *((volatile unsigned int*)(0x42CE0E20UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A41 *((volatile unsigned int*)(0x42CE0E24UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A42 *((volatile unsigned int*)(0x42CE0E28UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A43 *((volatile unsigned int*)(0x42CE0E2CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A44 *((volatile unsigned int*)(0x42CE0E30UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A45 *((volatile unsigned int*)(0x42CE0E34UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A46 *((volatile unsigned int*)(0x42CE0E38UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_A47 *((volatile unsigned int*)(0x42CE0E3CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC0 *((volatile unsigned int*)(0x42CE0E60UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC1 *((volatile unsigned int*)(0x42CE0E64UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC2 *((volatile unsigned int*)(0x42CE0E68UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC3 *((volatile unsigned int*)(0x42CE0E6CUL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC4 *((volatile unsigned int*)(0x42CE0E70UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_MBC5 *((volatile unsigned int*)(0x42CE0E74UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_SA *((volatile unsigned int*)(0x42CE0E78UL)) +#define bFM3_ETHERNET_MAC1_MAR6H_AE *((volatile unsigned int*)(0x42CE0E7CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A0 *((volatile unsigned int*)(0x42CE0E80UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A1 *((volatile unsigned int*)(0x42CE0E84UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A2 *((volatile unsigned int*)(0x42CE0E88UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A3 *((volatile unsigned int*)(0x42CE0E8CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A4 *((volatile unsigned int*)(0x42CE0E90UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A5 *((volatile unsigned int*)(0x42CE0E94UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A6 *((volatile unsigned int*)(0x42CE0E98UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A7 *((volatile unsigned int*)(0x42CE0E9CUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A8 *((volatile unsigned int*)(0x42CE0EA0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A9 *((volatile unsigned int*)(0x42CE0EA4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A10 *((volatile unsigned int*)(0x42CE0EA8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A11 *((volatile unsigned int*)(0x42CE0EACUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A12 *((volatile unsigned int*)(0x42CE0EB0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A13 *((volatile unsigned int*)(0x42CE0EB4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A14 *((volatile unsigned int*)(0x42CE0EB8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A15 *((volatile unsigned int*)(0x42CE0EBCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A16 *((volatile unsigned int*)(0x42CE0EC0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A17 *((volatile unsigned int*)(0x42CE0EC4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A18 *((volatile unsigned int*)(0x42CE0EC8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A19 *((volatile unsigned int*)(0x42CE0ECCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A20 *((volatile unsigned int*)(0x42CE0ED0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A21 *((volatile unsigned int*)(0x42CE0ED4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A22 *((volatile unsigned int*)(0x42CE0ED8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A23 *((volatile unsigned int*)(0x42CE0EDCUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A24 *((volatile unsigned int*)(0x42CE0EE0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A25 *((volatile unsigned int*)(0x42CE0EE4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A26 *((volatile unsigned int*)(0x42CE0EE8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A27 *((volatile unsigned int*)(0x42CE0EECUL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A28 *((volatile unsigned int*)(0x42CE0EF0UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A29 *((volatile unsigned int*)(0x42CE0EF4UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A30 *((volatile unsigned int*)(0x42CE0EF8UL)) +#define bFM3_ETHERNET_MAC1_MAR6L_A31 *((volatile unsigned int*)(0x42CE0EFCUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A32 *((volatile unsigned int*)(0x42CE0F00UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A33 *((volatile unsigned int*)(0x42CE0F04UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A34 *((volatile unsigned int*)(0x42CE0F08UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A35 *((volatile unsigned int*)(0x42CE0F0CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A36 *((volatile unsigned int*)(0x42CE0F10UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A37 *((volatile unsigned int*)(0x42CE0F14UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A38 *((volatile unsigned int*)(0x42CE0F18UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A39 *((volatile unsigned int*)(0x42CE0F1CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A40 *((volatile unsigned int*)(0x42CE0F20UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A41 *((volatile unsigned int*)(0x42CE0F24UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A42 *((volatile unsigned int*)(0x42CE0F28UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A43 *((volatile unsigned int*)(0x42CE0F2CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A44 *((volatile unsigned int*)(0x42CE0F30UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A45 *((volatile unsigned int*)(0x42CE0F34UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A46 *((volatile unsigned int*)(0x42CE0F38UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_A47 *((volatile unsigned int*)(0x42CE0F3CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC0 *((volatile unsigned int*)(0x42CE0F60UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC1 *((volatile unsigned int*)(0x42CE0F64UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC2 *((volatile unsigned int*)(0x42CE0F68UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC3 *((volatile unsigned int*)(0x42CE0F6CUL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC4 *((volatile unsigned int*)(0x42CE0F70UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_MBC5 *((volatile unsigned int*)(0x42CE0F74UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_SA *((volatile unsigned int*)(0x42CE0F78UL)) +#define bFM3_ETHERNET_MAC1_MAR7H_AE *((volatile unsigned int*)(0x42CE0F7CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A0 *((volatile unsigned int*)(0x42CE0F80UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A1 *((volatile unsigned int*)(0x42CE0F84UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A2 *((volatile unsigned int*)(0x42CE0F88UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A3 *((volatile unsigned int*)(0x42CE0F8CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A4 *((volatile unsigned int*)(0x42CE0F90UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A5 *((volatile unsigned int*)(0x42CE0F94UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A6 *((volatile unsigned int*)(0x42CE0F98UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A7 *((volatile unsigned int*)(0x42CE0F9CUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A8 *((volatile unsigned int*)(0x42CE0FA0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A9 *((volatile unsigned int*)(0x42CE0FA4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A10 *((volatile unsigned int*)(0x42CE0FA8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A11 *((volatile unsigned int*)(0x42CE0FACUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A12 *((volatile unsigned int*)(0x42CE0FB0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A13 *((volatile unsigned int*)(0x42CE0FB4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A14 *((volatile unsigned int*)(0x42CE0FB8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A15 *((volatile unsigned int*)(0x42CE0FBCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A16 *((volatile unsigned int*)(0x42CE0FC0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A17 *((volatile unsigned int*)(0x42CE0FC4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A18 *((volatile unsigned int*)(0x42CE0FC8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A19 *((volatile unsigned int*)(0x42CE0FCCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A20 *((volatile unsigned int*)(0x42CE0FD0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A21 *((volatile unsigned int*)(0x42CE0FD4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A22 *((volatile unsigned int*)(0x42CE0FD8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A23 *((volatile unsigned int*)(0x42CE0FDCUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A24 *((volatile unsigned int*)(0x42CE0FE0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A25 *((volatile unsigned int*)(0x42CE0FE4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A26 *((volatile unsigned int*)(0x42CE0FE8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A27 *((volatile unsigned int*)(0x42CE0FECUL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A28 *((volatile unsigned int*)(0x42CE0FF0UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A29 *((volatile unsigned int*)(0x42CE0FF4UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A30 *((volatile unsigned int*)(0x42CE0FF8UL)) +#define bFM3_ETHERNET_MAC1_MAR7L_A31 *((volatile unsigned int*)(0x42CE0FFCUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A32 *((volatile unsigned int*)(0x42CE1000UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A33 *((volatile unsigned int*)(0x42CE1004UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A34 *((volatile unsigned int*)(0x42CE1008UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A35 *((volatile unsigned int*)(0x42CE100CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A36 *((volatile unsigned int*)(0x42CE1010UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A37 *((volatile unsigned int*)(0x42CE1014UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A38 *((volatile unsigned int*)(0x42CE1018UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A39 *((volatile unsigned int*)(0x42CE101CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A40 *((volatile unsigned int*)(0x42CE1020UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A41 *((volatile unsigned int*)(0x42CE1024UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A42 *((volatile unsigned int*)(0x42CE1028UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A43 *((volatile unsigned int*)(0x42CE102CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A44 *((volatile unsigned int*)(0x42CE1030UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A45 *((volatile unsigned int*)(0x42CE1034UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A46 *((volatile unsigned int*)(0x42CE1038UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_A47 *((volatile unsigned int*)(0x42CE103CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC0 *((volatile unsigned int*)(0x42CE1060UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC1 *((volatile unsigned int*)(0x42CE1064UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC2 *((volatile unsigned int*)(0x42CE1068UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC3 *((volatile unsigned int*)(0x42CE106CUL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC4 *((volatile unsigned int*)(0x42CE1070UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_MBC5 *((volatile unsigned int*)(0x42CE1074UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_SA *((volatile unsigned int*)(0x42CE1078UL)) +#define bFM3_ETHERNET_MAC1_MAR8H_AE *((volatile unsigned int*)(0x42CE107CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A0 *((volatile unsigned int*)(0x42CE1080UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A1 *((volatile unsigned int*)(0x42CE1084UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A2 *((volatile unsigned int*)(0x42CE1088UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A3 *((volatile unsigned int*)(0x42CE108CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A4 *((volatile unsigned int*)(0x42CE1090UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A5 *((volatile unsigned int*)(0x42CE1094UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A6 *((volatile unsigned int*)(0x42CE1098UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A7 *((volatile unsigned int*)(0x42CE109CUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A8 *((volatile unsigned int*)(0x42CE10A0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A9 *((volatile unsigned int*)(0x42CE10A4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A10 *((volatile unsigned int*)(0x42CE10A8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A11 *((volatile unsigned int*)(0x42CE10ACUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A12 *((volatile unsigned int*)(0x42CE10B0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A13 *((volatile unsigned int*)(0x42CE10B4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A14 *((volatile unsigned int*)(0x42CE10B8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A15 *((volatile unsigned int*)(0x42CE10BCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A16 *((volatile unsigned int*)(0x42CE10C0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A17 *((volatile unsigned int*)(0x42CE10C4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A18 *((volatile unsigned int*)(0x42CE10C8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A19 *((volatile unsigned int*)(0x42CE10CCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A20 *((volatile unsigned int*)(0x42CE10D0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A21 *((volatile unsigned int*)(0x42CE10D4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A22 *((volatile unsigned int*)(0x42CE10D8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A23 *((volatile unsigned int*)(0x42CE10DCUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A24 *((volatile unsigned int*)(0x42CE10E0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A25 *((volatile unsigned int*)(0x42CE10E4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A26 *((volatile unsigned int*)(0x42CE10E8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A27 *((volatile unsigned int*)(0x42CE10ECUL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A28 *((volatile unsigned int*)(0x42CE10F0UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A29 *((volatile unsigned int*)(0x42CE10F4UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A30 *((volatile unsigned int*)(0x42CE10F8UL)) +#define bFM3_ETHERNET_MAC1_MAR8L_A31 *((volatile unsigned int*)(0x42CE10FCUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A32 *((volatile unsigned int*)(0x42CE1100UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A33 *((volatile unsigned int*)(0x42CE1104UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A34 *((volatile unsigned int*)(0x42CE1108UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A35 *((volatile unsigned int*)(0x42CE110CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A36 *((volatile unsigned int*)(0x42CE1110UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A37 *((volatile unsigned int*)(0x42CE1114UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A38 *((volatile unsigned int*)(0x42CE1118UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A39 *((volatile unsigned int*)(0x42CE111CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A40 *((volatile unsigned int*)(0x42CE1120UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A41 *((volatile unsigned int*)(0x42CE1124UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A42 *((volatile unsigned int*)(0x42CE1128UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A43 *((volatile unsigned int*)(0x42CE112CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A44 *((volatile unsigned int*)(0x42CE1130UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A45 *((volatile unsigned int*)(0x42CE1134UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A46 *((volatile unsigned int*)(0x42CE1138UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_A47 *((volatile unsigned int*)(0x42CE113CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC0 *((volatile unsigned int*)(0x42CE1160UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC1 *((volatile unsigned int*)(0x42CE1164UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC2 *((volatile unsigned int*)(0x42CE1168UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC3 *((volatile unsigned int*)(0x42CE116CUL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC4 *((volatile unsigned int*)(0x42CE1170UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_MBC5 *((volatile unsigned int*)(0x42CE1174UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_SA *((volatile unsigned int*)(0x42CE1178UL)) +#define bFM3_ETHERNET_MAC1_MAR9H_AE *((volatile unsigned int*)(0x42CE117CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A0 *((volatile unsigned int*)(0x42CE1180UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A1 *((volatile unsigned int*)(0x42CE1184UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A2 *((volatile unsigned int*)(0x42CE1188UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A3 *((volatile unsigned int*)(0x42CE118CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A4 *((volatile unsigned int*)(0x42CE1190UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A5 *((volatile unsigned int*)(0x42CE1194UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A6 *((volatile unsigned int*)(0x42CE1198UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A7 *((volatile unsigned int*)(0x42CE119CUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A8 *((volatile unsigned int*)(0x42CE11A0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A9 *((volatile unsigned int*)(0x42CE11A4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A10 *((volatile unsigned int*)(0x42CE11A8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A11 *((volatile unsigned int*)(0x42CE11ACUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A12 *((volatile unsigned int*)(0x42CE11B0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A13 *((volatile unsigned int*)(0x42CE11B4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A14 *((volatile unsigned int*)(0x42CE11B8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A15 *((volatile unsigned int*)(0x42CE11BCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A16 *((volatile unsigned int*)(0x42CE11C0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A17 *((volatile unsigned int*)(0x42CE11C4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A18 *((volatile unsigned int*)(0x42CE11C8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A19 *((volatile unsigned int*)(0x42CE11CCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A20 *((volatile unsigned int*)(0x42CE11D0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A21 *((volatile unsigned int*)(0x42CE11D4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A22 *((volatile unsigned int*)(0x42CE11D8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A23 *((volatile unsigned int*)(0x42CE11DCUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A24 *((volatile unsigned int*)(0x42CE11E0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A25 *((volatile unsigned int*)(0x42CE11E4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A26 *((volatile unsigned int*)(0x42CE11E8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A27 *((volatile unsigned int*)(0x42CE11ECUL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A28 *((volatile unsigned int*)(0x42CE11F0UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A29 *((volatile unsigned int*)(0x42CE11F4UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A30 *((volatile unsigned int*)(0x42CE11F8UL)) +#define bFM3_ETHERNET_MAC1_MAR9L_A31 *((volatile unsigned int*)(0x42CE11FCUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A32 *((volatile unsigned int*)(0x42CE1200UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A33 *((volatile unsigned int*)(0x42CE1204UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A34 *((volatile unsigned int*)(0x42CE1208UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A35 *((volatile unsigned int*)(0x42CE120CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A36 *((volatile unsigned int*)(0x42CE1210UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A37 *((volatile unsigned int*)(0x42CE1214UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A38 *((volatile unsigned int*)(0x42CE1218UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A39 *((volatile unsigned int*)(0x42CE121CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A40 *((volatile unsigned int*)(0x42CE1220UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A41 *((volatile unsigned int*)(0x42CE1224UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A42 *((volatile unsigned int*)(0x42CE1228UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A43 *((volatile unsigned int*)(0x42CE122CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A44 *((volatile unsigned int*)(0x42CE1230UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A45 *((volatile unsigned int*)(0x42CE1234UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A46 *((volatile unsigned int*)(0x42CE1238UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_A47 *((volatile unsigned int*)(0x42CE123CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC0 *((volatile unsigned int*)(0x42CE1260UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC1 *((volatile unsigned int*)(0x42CE1264UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC2 *((volatile unsigned int*)(0x42CE1268UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC3 *((volatile unsigned int*)(0x42CE126CUL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC4 *((volatile unsigned int*)(0x42CE1270UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_MBC5 *((volatile unsigned int*)(0x42CE1274UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_SA *((volatile unsigned int*)(0x42CE1278UL)) +#define bFM3_ETHERNET_MAC1_MAR10H_AE *((volatile unsigned int*)(0x42CE127CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A0 *((volatile unsigned int*)(0x42CE1280UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A1 *((volatile unsigned int*)(0x42CE1284UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A2 *((volatile unsigned int*)(0x42CE1288UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A3 *((volatile unsigned int*)(0x42CE128CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A4 *((volatile unsigned int*)(0x42CE1290UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A5 *((volatile unsigned int*)(0x42CE1294UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A6 *((volatile unsigned int*)(0x42CE1298UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A7 *((volatile unsigned int*)(0x42CE129CUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A8 *((volatile unsigned int*)(0x42CE12A0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A9 *((volatile unsigned int*)(0x42CE12A4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A10 *((volatile unsigned int*)(0x42CE12A8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A11 *((volatile unsigned int*)(0x42CE12ACUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A12 *((volatile unsigned int*)(0x42CE12B0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A13 *((volatile unsigned int*)(0x42CE12B4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A14 *((volatile unsigned int*)(0x42CE12B8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A15 *((volatile unsigned int*)(0x42CE12BCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A16 *((volatile unsigned int*)(0x42CE12C0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A17 *((volatile unsigned int*)(0x42CE12C4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A18 *((volatile unsigned int*)(0x42CE12C8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A19 *((volatile unsigned int*)(0x42CE12CCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A20 *((volatile unsigned int*)(0x42CE12D0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A21 *((volatile unsigned int*)(0x42CE12D4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A22 *((volatile unsigned int*)(0x42CE12D8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A23 *((volatile unsigned int*)(0x42CE12DCUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A24 *((volatile unsigned int*)(0x42CE12E0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A25 *((volatile unsigned int*)(0x42CE12E4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A26 *((volatile unsigned int*)(0x42CE12E8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A27 *((volatile unsigned int*)(0x42CE12ECUL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A28 *((volatile unsigned int*)(0x42CE12F0UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A29 *((volatile unsigned int*)(0x42CE12F4UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A30 *((volatile unsigned int*)(0x42CE12F8UL)) +#define bFM3_ETHERNET_MAC1_MAR10L_A31 *((volatile unsigned int*)(0x42CE12FCUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A32 *((volatile unsigned int*)(0x42CE1300UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A33 *((volatile unsigned int*)(0x42CE1304UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A34 *((volatile unsigned int*)(0x42CE1308UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A35 *((volatile unsigned int*)(0x42CE130CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A36 *((volatile unsigned int*)(0x42CE1310UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A37 *((volatile unsigned int*)(0x42CE1314UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A38 *((volatile unsigned int*)(0x42CE1318UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A39 *((volatile unsigned int*)(0x42CE131CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A40 *((volatile unsigned int*)(0x42CE1320UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A41 *((volatile unsigned int*)(0x42CE1324UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A42 *((volatile unsigned int*)(0x42CE1328UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A43 *((volatile unsigned int*)(0x42CE132CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A44 *((volatile unsigned int*)(0x42CE1330UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A45 *((volatile unsigned int*)(0x42CE1334UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A46 *((volatile unsigned int*)(0x42CE1338UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_A47 *((volatile unsigned int*)(0x42CE133CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC0 *((volatile unsigned int*)(0x42CE1360UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC1 *((volatile unsigned int*)(0x42CE1364UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC2 *((volatile unsigned int*)(0x42CE1368UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC3 *((volatile unsigned int*)(0x42CE136CUL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC4 *((volatile unsigned int*)(0x42CE1370UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_MBC5 *((volatile unsigned int*)(0x42CE1374UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_SA *((volatile unsigned int*)(0x42CE1378UL)) +#define bFM3_ETHERNET_MAC1_MAR11H_AE *((volatile unsigned int*)(0x42CE137CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A0 *((volatile unsigned int*)(0x42CE1380UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A1 *((volatile unsigned int*)(0x42CE1384UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A2 *((volatile unsigned int*)(0x42CE1388UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A3 *((volatile unsigned int*)(0x42CE138CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A4 *((volatile unsigned int*)(0x42CE1390UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A5 *((volatile unsigned int*)(0x42CE1394UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A6 *((volatile unsigned int*)(0x42CE1398UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A7 *((volatile unsigned int*)(0x42CE139CUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A8 *((volatile unsigned int*)(0x42CE13A0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A9 *((volatile unsigned int*)(0x42CE13A4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A10 *((volatile unsigned int*)(0x42CE13A8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A11 *((volatile unsigned int*)(0x42CE13ACUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A12 *((volatile unsigned int*)(0x42CE13B0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A13 *((volatile unsigned int*)(0x42CE13B4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A14 *((volatile unsigned int*)(0x42CE13B8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A15 *((volatile unsigned int*)(0x42CE13BCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A16 *((volatile unsigned int*)(0x42CE13C0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A17 *((volatile unsigned int*)(0x42CE13C4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A18 *((volatile unsigned int*)(0x42CE13C8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A19 *((volatile unsigned int*)(0x42CE13CCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A20 *((volatile unsigned int*)(0x42CE13D0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A21 *((volatile unsigned int*)(0x42CE13D4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A22 *((volatile unsigned int*)(0x42CE13D8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A23 *((volatile unsigned int*)(0x42CE13DCUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A24 *((volatile unsigned int*)(0x42CE13E0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A25 *((volatile unsigned int*)(0x42CE13E4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A26 *((volatile unsigned int*)(0x42CE13E8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A27 *((volatile unsigned int*)(0x42CE13ECUL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A28 *((volatile unsigned int*)(0x42CE13F0UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A29 *((volatile unsigned int*)(0x42CE13F4UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A30 *((volatile unsigned int*)(0x42CE13F8UL)) +#define bFM3_ETHERNET_MAC1_MAR11L_A31 *((volatile unsigned int*)(0x42CE13FCUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A32 *((volatile unsigned int*)(0x42CE1400UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A33 *((volatile unsigned int*)(0x42CE1404UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A34 *((volatile unsigned int*)(0x42CE1408UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A35 *((volatile unsigned int*)(0x42CE140CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A36 *((volatile unsigned int*)(0x42CE1410UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A37 *((volatile unsigned int*)(0x42CE1414UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A38 *((volatile unsigned int*)(0x42CE1418UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A39 *((volatile unsigned int*)(0x42CE141CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A40 *((volatile unsigned int*)(0x42CE1420UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A41 *((volatile unsigned int*)(0x42CE1424UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A42 *((volatile unsigned int*)(0x42CE1428UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A43 *((volatile unsigned int*)(0x42CE142CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A44 *((volatile unsigned int*)(0x42CE1430UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A45 *((volatile unsigned int*)(0x42CE1434UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A46 *((volatile unsigned int*)(0x42CE1438UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_A47 *((volatile unsigned int*)(0x42CE143CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC0 *((volatile unsigned int*)(0x42CE1460UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC1 *((volatile unsigned int*)(0x42CE1464UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC2 *((volatile unsigned int*)(0x42CE1468UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC3 *((volatile unsigned int*)(0x42CE146CUL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC4 *((volatile unsigned int*)(0x42CE1470UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_MBC5 *((volatile unsigned int*)(0x42CE1474UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_SA *((volatile unsigned int*)(0x42CE1478UL)) +#define bFM3_ETHERNET_MAC1_MAR12H_AE *((volatile unsigned int*)(0x42CE147CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A0 *((volatile unsigned int*)(0x42CE1480UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A1 *((volatile unsigned int*)(0x42CE1484UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A2 *((volatile unsigned int*)(0x42CE1488UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A3 *((volatile unsigned int*)(0x42CE148CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A4 *((volatile unsigned int*)(0x42CE1490UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A5 *((volatile unsigned int*)(0x42CE1494UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A6 *((volatile unsigned int*)(0x42CE1498UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A7 *((volatile unsigned int*)(0x42CE149CUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A8 *((volatile unsigned int*)(0x42CE14A0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A9 *((volatile unsigned int*)(0x42CE14A4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A10 *((volatile unsigned int*)(0x42CE14A8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A11 *((volatile unsigned int*)(0x42CE14ACUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A12 *((volatile unsigned int*)(0x42CE14B0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A13 *((volatile unsigned int*)(0x42CE14B4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A14 *((volatile unsigned int*)(0x42CE14B8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A15 *((volatile unsigned int*)(0x42CE14BCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A16 *((volatile unsigned int*)(0x42CE14C0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A17 *((volatile unsigned int*)(0x42CE14C4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A18 *((volatile unsigned int*)(0x42CE14C8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A19 *((volatile unsigned int*)(0x42CE14CCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A20 *((volatile unsigned int*)(0x42CE14D0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A21 *((volatile unsigned int*)(0x42CE14D4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A22 *((volatile unsigned int*)(0x42CE14D8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A23 *((volatile unsigned int*)(0x42CE14DCUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A24 *((volatile unsigned int*)(0x42CE14E0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A25 *((volatile unsigned int*)(0x42CE14E4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A26 *((volatile unsigned int*)(0x42CE14E8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A27 *((volatile unsigned int*)(0x42CE14ECUL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A28 *((volatile unsigned int*)(0x42CE14F0UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A29 *((volatile unsigned int*)(0x42CE14F4UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A30 *((volatile unsigned int*)(0x42CE14F8UL)) +#define bFM3_ETHERNET_MAC1_MAR12L_A31 *((volatile unsigned int*)(0x42CE14FCUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A32 *((volatile unsigned int*)(0x42CE1500UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A33 *((volatile unsigned int*)(0x42CE1504UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A34 *((volatile unsigned int*)(0x42CE1508UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A35 *((volatile unsigned int*)(0x42CE150CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A36 *((volatile unsigned int*)(0x42CE1510UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A37 *((volatile unsigned int*)(0x42CE1514UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A38 *((volatile unsigned int*)(0x42CE1518UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A39 *((volatile unsigned int*)(0x42CE151CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A40 *((volatile unsigned int*)(0x42CE1520UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A41 *((volatile unsigned int*)(0x42CE1524UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A42 *((volatile unsigned int*)(0x42CE1528UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A43 *((volatile unsigned int*)(0x42CE152CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A44 *((volatile unsigned int*)(0x42CE1530UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A45 *((volatile unsigned int*)(0x42CE1534UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A46 *((volatile unsigned int*)(0x42CE1538UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_A47 *((volatile unsigned int*)(0x42CE153CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC0 *((volatile unsigned int*)(0x42CE1560UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC1 *((volatile unsigned int*)(0x42CE1564UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC2 *((volatile unsigned int*)(0x42CE1568UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC3 *((volatile unsigned int*)(0x42CE156CUL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC4 *((volatile unsigned int*)(0x42CE1570UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_MBC5 *((volatile unsigned int*)(0x42CE1574UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_SA *((volatile unsigned int*)(0x42CE1578UL)) +#define bFM3_ETHERNET_MAC1_MAR13H_AE *((volatile unsigned int*)(0x42CE157CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A0 *((volatile unsigned int*)(0x42CE1580UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A1 *((volatile unsigned int*)(0x42CE1584UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A2 *((volatile unsigned int*)(0x42CE1588UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A3 *((volatile unsigned int*)(0x42CE158CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A4 *((volatile unsigned int*)(0x42CE1590UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A5 *((volatile unsigned int*)(0x42CE1594UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A6 *((volatile unsigned int*)(0x42CE1598UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A7 *((volatile unsigned int*)(0x42CE159CUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A8 *((volatile unsigned int*)(0x42CE15A0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A9 *((volatile unsigned int*)(0x42CE15A4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A10 *((volatile unsigned int*)(0x42CE15A8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A11 *((volatile unsigned int*)(0x42CE15ACUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A12 *((volatile unsigned int*)(0x42CE15B0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A13 *((volatile unsigned int*)(0x42CE15B4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A14 *((volatile unsigned int*)(0x42CE15B8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A15 *((volatile unsigned int*)(0x42CE15BCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A16 *((volatile unsigned int*)(0x42CE15C0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A17 *((volatile unsigned int*)(0x42CE15C4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A18 *((volatile unsigned int*)(0x42CE15C8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A19 *((volatile unsigned int*)(0x42CE15CCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A20 *((volatile unsigned int*)(0x42CE15D0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A21 *((volatile unsigned int*)(0x42CE15D4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A22 *((volatile unsigned int*)(0x42CE15D8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A23 *((volatile unsigned int*)(0x42CE15DCUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A24 *((volatile unsigned int*)(0x42CE15E0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A25 *((volatile unsigned int*)(0x42CE15E4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A26 *((volatile unsigned int*)(0x42CE15E8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A27 *((volatile unsigned int*)(0x42CE15ECUL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A28 *((volatile unsigned int*)(0x42CE15F0UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A29 *((volatile unsigned int*)(0x42CE15F4UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A30 *((volatile unsigned int*)(0x42CE15F8UL)) +#define bFM3_ETHERNET_MAC1_MAR13L_A31 *((volatile unsigned int*)(0x42CE15FCUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A32 *((volatile unsigned int*)(0x42CE1600UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A33 *((volatile unsigned int*)(0x42CE1604UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A34 *((volatile unsigned int*)(0x42CE1608UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A35 *((volatile unsigned int*)(0x42CE160CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A36 *((volatile unsigned int*)(0x42CE1610UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A37 *((volatile unsigned int*)(0x42CE1614UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A38 *((volatile unsigned int*)(0x42CE1618UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A39 *((volatile unsigned int*)(0x42CE161CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A40 *((volatile unsigned int*)(0x42CE1620UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A41 *((volatile unsigned int*)(0x42CE1624UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A42 *((volatile unsigned int*)(0x42CE1628UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A43 *((volatile unsigned int*)(0x42CE162CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A44 *((volatile unsigned int*)(0x42CE1630UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A45 *((volatile unsigned int*)(0x42CE1634UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A46 *((volatile unsigned int*)(0x42CE1638UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_A47 *((volatile unsigned int*)(0x42CE163CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC0 *((volatile unsigned int*)(0x42CE1660UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC1 *((volatile unsigned int*)(0x42CE1664UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC2 *((volatile unsigned int*)(0x42CE1668UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC3 *((volatile unsigned int*)(0x42CE166CUL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC4 *((volatile unsigned int*)(0x42CE1670UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_MBC5 *((volatile unsigned int*)(0x42CE1674UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_SA *((volatile unsigned int*)(0x42CE1678UL)) +#define bFM3_ETHERNET_MAC1_MAR14H_AE *((volatile unsigned int*)(0x42CE167CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A0 *((volatile unsigned int*)(0x42CE1680UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A1 *((volatile unsigned int*)(0x42CE1684UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A2 *((volatile unsigned int*)(0x42CE1688UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A3 *((volatile unsigned int*)(0x42CE168CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A4 *((volatile unsigned int*)(0x42CE1690UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A5 *((volatile unsigned int*)(0x42CE1694UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A6 *((volatile unsigned int*)(0x42CE1698UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A7 *((volatile unsigned int*)(0x42CE169CUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A8 *((volatile unsigned int*)(0x42CE16A0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A9 *((volatile unsigned int*)(0x42CE16A4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A10 *((volatile unsigned int*)(0x42CE16A8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A11 *((volatile unsigned int*)(0x42CE16ACUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A12 *((volatile unsigned int*)(0x42CE16B0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A13 *((volatile unsigned int*)(0x42CE16B4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A14 *((volatile unsigned int*)(0x42CE16B8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A15 *((volatile unsigned int*)(0x42CE16BCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A16 *((volatile unsigned int*)(0x42CE16C0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A17 *((volatile unsigned int*)(0x42CE16C4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A18 *((volatile unsigned int*)(0x42CE16C8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A19 *((volatile unsigned int*)(0x42CE16CCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A20 *((volatile unsigned int*)(0x42CE16D0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A21 *((volatile unsigned int*)(0x42CE16D4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A22 *((volatile unsigned int*)(0x42CE16D8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A23 *((volatile unsigned int*)(0x42CE16DCUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A24 *((volatile unsigned int*)(0x42CE16E0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A25 *((volatile unsigned int*)(0x42CE16E4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A26 *((volatile unsigned int*)(0x42CE16E8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A27 *((volatile unsigned int*)(0x42CE16ECUL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A28 *((volatile unsigned int*)(0x42CE16F0UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A29 *((volatile unsigned int*)(0x42CE16F4UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A30 *((volatile unsigned int*)(0x42CE16F8UL)) +#define bFM3_ETHERNET_MAC1_MAR14L_A31 *((volatile unsigned int*)(0x42CE16FCUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A32 *((volatile unsigned int*)(0x42CE1700UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A33 *((volatile unsigned int*)(0x42CE1704UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A34 *((volatile unsigned int*)(0x42CE1708UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A35 *((volatile unsigned int*)(0x42CE170CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A36 *((volatile unsigned int*)(0x42CE1710UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A37 *((volatile unsigned int*)(0x42CE1714UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A38 *((volatile unsigned int*)(0x42CE1718UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A39 *((volatile unsigned int*)(0x42CE171CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A40 *((volatile unsigned int*)(0x42CE1720UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A41 *((volatile unsigned int*)(0x42CE1724UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A42 *((volatile unsigned int*)(0x42CE1728UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A43 *((volatile unsigned int*)(0x42CE172CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A44 *((volatile unsigned int*)(0x42CE1730UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A45 *((volatile unsigned int*)(0x42CE1734UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A46 *((volatile unsigned int*)(0x42CE1738UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_A47 *((volatile unsigned int*)(0x42CE173CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC0 *((volatile unsigned int*)(0x42CE1760UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC1 *((volatile unsigned int*)(0x42CE1764UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC2 *((volatile unsigned int*)(0x42CE1768UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC3 *((volatile unsigned int*)(0x42CE176CUL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC4 *((volatile unsigned int*)(0x42CE1770UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_MBC5 *((volatile unsigned int*)(0x42CE1774UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_SA *((volatile unsigned int*)(0x42CE1778UL)) +#define bFM3_ETHERNET_MAC1_MAR15H_AE *((volatile unsigned int*)(0x42CE177CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A0 *((volatile unsigned int*)(0x42CE1780UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A1 *((volatile unsigned int*)(0x42CE1784UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A2 *((volatile unsigned int*)(0x42CE1788UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A3 *((volatile unsigned int*)(0x42CE178CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A4 *((volatile unsigned int*)(0x42CE1790UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A5 *((volatile unsigned int*)(0x42CE1794UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A6 *((volatile unsigned int*)(0x42CE1798UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A7 *((volatile unsigned int*)(0x42CE179CUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A8 *((volatile unsigned int*)(0x42CE17A0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A9 *((volatile unsigned int*)(0x42CE17A4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A10 *((volatile unsigned int*)(0x42CE17A8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A11 *((volatile unsigned int*)(0x42CE17ACUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A12 *((volatile unsigned int*)(0x42CE17B0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A13 *((volatile unsigned int*)(0x42CE17B4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A14 *((volatile unsigned int*)(0x42CE17B8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A15 *((volatile unsigned int*)(0x42CE17BCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A16 *((volatile unsigned int*)(0x42CE17C0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A17 *((volatile unsigned int*)(0x42CE17C4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A18 *((volatile unsigned int*)(0x42CE17C8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A19 *((volatile unsigned int*)(0x42CE17CCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A20 *((volatile unsigned int*)(0x42CE17D0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A21 *((volatile unsigned int*)(0x42CE17D4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A22 *((volatile unsigned int*)(0x42CE17D8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A23 *((volatile unsigned int*)(0x42CE17DCUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A24 *((volatile unsigned int*)(0x42CE17E0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A25 *((volatile unsigned int*)(0x42CE17E4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A26 *((volatile unsigned int*)(0x42CE17E8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A27 *((volatile unsigned int*)(0x42CE17ECUL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A28 *((volatile unsigned int*)(0x42CE17F0UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A29 *((volatile unsigned int*)(0x42CE17F4UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A30 *((volatile unsigned int*)(0x42CE17F8UL)) +#define bFM3_ETHERNET_MAC1_MAR15L_A31 *((volatile unsigned int*)(0x42CE17FCUL)) +#define bFM3_ETHERNET_MAC1_RGSR_LM *((volatile unsigned int*)(0x42CE1B00UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LSP0 *((volatile unsigned int*)(0x42CE1B04UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LSP1 *((volatile unsigned int*)(0x42CE1B08UL)) +#define bFM3_ETHERNET_MAC1_RGSR_LS *((volatile unsigned int*)(0x42CE1B0CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSE *((volatile unsigned int*)(0x42CEE000UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TFCU *((volatile unsigned int*)(0x42CEE004UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSI *((volatile unsigned int*)(0x42CEE008UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSU *((volatile unsigned int*)(0x42CEE00CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TITE *((volatile unsigned int*)(0x42CEE010UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TARU *((volatile unsigned int*)(0x42CEE014UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSEA *((volatile unsigned int*)(0x42CEE020UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSDB *((volatile unsigned int*)(0x42CEE024UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSV2E *((volatile unsigned int*)(0x42CEE028UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TETSP *((volatile unsigned int*)(0x42CEE02CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E *((volatile unsigned int*)(0x42CEE030UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E *((volatile unsigned int*)(0x42CEE034UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TETSEM *((volatile unsigned int*)(0x42CEE038UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSMRM *((volatile unsigned int*)(0x42CEE03CUL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSPS0 *((volatile unsigned int*)(0x42CEE040UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSPS1 *((volatile unsigned int*)(0x42CEE044UL)) +#define bFM3_ETHERNET_MAC1_TSCR_TSENMF *((volatile unsigned int*)(0x42CEE048UL)) +#define bFM3_ETHERNET_MAC1_TSCR_ATSFC *((volatile unsigned int*)(0x42CEE060UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC0 *((volatile unsigned int*)(0x42CEE080UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC1 *((volatile unsigned int*)(0x42CEE084UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC2 *((volatile unsigned int*)(0x42CEE088UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC3 *((volatile unsigned int*)(0x42CEE08CUL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC4 *((volatile unsigned int*)(0x42CEE090UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC5 *((volatile unsigned int*)(0x42CEE094UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC6 *((volatile unsigned int*)(0x42CEE098UL)) +#define bFM3_ETHERNET_MAC1_SSIR_SSINC7 *((volatile unsigned int*)(0x42CEE09CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS0 *((volatile unsigned int*)(0x42CEE100UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS1 *((volatile unsigned int*)(0x42CEE104UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS2 *((volatile unsigned int*)(0x42CEE108UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS3 *((volatile unsigned int*)(0x42CEE10CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS4 *((volatile unsigned int*)(0x42CEE110UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS5 *((volatile unsigned int*)(0x42CEE114UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS6 *((volatile unsigned int*)(0x42CEE118UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS7 *((volatile unsigned int*)(0x42CEE11CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS8 *((volatile unsigned int*)(0x42CEE120UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS9 *((volatile unsigned int*)(0x42CEE124UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS10 *((volatile unsigned int*)(0x42CEE128UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS11 *((volatile unsigned int*)(0x42CEE12CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS12 *((volatile unsigned int*)(0x42CEE130UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS13 *((volatile unsigned int*)(0x42CEE134UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS14 *((volatile unsigned int*)(0x42CEE138UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS15 *((volatile unsigned int*)(0x42CEE13CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS16 *((volatile unsigned int*)(0x42CEE140UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS17 *((volatile unsigned int*)(0x42CEE144UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS18 *((volatile unsigned int*)(0x42CEE148UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS19 *((volatile unsigned int*)(0x42CEE14CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS20 *((volatile unsigned int*)(0x42CEE150UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS21 *((volatile unsigned int*)(0x42CEE154UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS22 *((volatile unsigned int*)(0x42CEE158UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS23 *((volatile unsigned int*)(0x42CEE15CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS24 *((volatile unsigned int*)(0x42CEE160UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS25 *((volatile unsigned int*)(0x42CEE164UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS26 *((volatile unsigned int*)(0x42CEE168UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS27 *((volatile unsigned int*)(0x42CEE16CUL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS28 *((volatile unsigned int*)(0x42CEE170UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS29 *((volatile unsigned int*)(0x42CEE174UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS30 *((volatile unsigned int*)(0x42CEE178UL)) +#define bFM3_ETHERNET_MAC1_STSR_TSS31 *((volatile unsigned int*)(0x42CEE17CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS0 *((volatile unsigned int*)(0x42CEE080UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS1 *((volatile unsigned int*)(0x42CEE084UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS2 *((volatile unsigned int*)(0x42CEE088UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS3 *((volatile unsigned int*)(0x42CEE08CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS4 *((volatile unsigned int*)(0x42CEE090UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS5 *((volatile unsigned int*)(0x42CEE094UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS6 *((volatile unsigned int*)(0x42CEE098UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS7 *((volatile unsigned int*)(0x42CEE09CUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS8 *((volatile unsigned int*)(0x42CEE0A0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS9 *((volatile unsigned int*)(0x42CEE0A4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS10 *((volatile unsigned int*)(0x42CEE0A8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS11 *((volatile unsigned int*)(0x42CEE0ACUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS12 *((volatile unsigned int*)(0x42CEE0B0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS13 *((volatile unsigned int*)(0x42CEE0B4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS14 *((volatile unsigned int*)(0x42CEE0B8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS15 *((volatile unsigned int*)(0x42CEE0BCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS16 *((volatile unsigned int*)(0x42CEE0C0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS17 *((volatile unsigned int*)(0x42CEE0C4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS18 *((volatile unsigned int*)(0x42CEE0C8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS19 *((volatile unsigned int*)(0x42CEE0CCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS20 *((volatile unsigned int*)(0x42CEE0D0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS21 *((volatile unsigned int*)(0x42CEE0D4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS22 *((volatile unsigned int*)(0x42CEE0D8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS23 *((volatile unsigned int*)(0x42CEE0DCUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS24 *((volatile unsigned int*)(0x42CEE0E0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS25 *((volatile unsigned int*)(0x42CEE0E4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS26 *((volatile unsigned int*)(0x42CEE0E8UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS27 *((volatile unsigned int*)(0x42CEE0ECUL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS28 *((volatile unsigned int*)(0x42CEE0F0UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS29 *((volatile unsigned int*)(0x42CEE0F4UL)) +#define bFM3_ETHERNET_MAC1_STNR_TSSS30 *((volatile unsigned int*)(0x42CEE0F8UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS0 *((volatile unsigned int*)(0x42CEE200UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS1 *((volatile unsigned int*)(0x42CEE204UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS2 *((volatile unsigned int*)(0x42CEE208UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS3 *((volatile unsigned int*)(0x42CEE20CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS4 *((volatile unsigned int*)(0x42CEE210UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS5 *((volatile unsigned int*)(0x42CEE214UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS6 *((volatile unsigned int*)(0x42CEE218UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS7 *((volatile unsigned int*)(0x42CEE21CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS8 *((volatile unsigned int*)(0x42CEE220UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS9 *((volatile unsigned int*)(0x42CEE224UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS10 *((volatile unsigned int*)(0x42CEE228UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS11 *((volatile unsigned int*)(0x42CEE22CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS12 *((volatile unsigned int*)(0x42CEE230UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS13 *((volatile unsigned int*)(0x42CEE234UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS14 *((volatile unsigned int*)(0x42CEE238UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS15 *((volatile unsigned int*)(0x42CEE23CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS16 *((volatile unsigned int*)(0x42CEE240UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS17 *((volatile unsigned int*)(0x42CEE244UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS18 *((volatile unsigned int*)(0x42CEE248UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS19 *((volatile unsigned int*)(0x42CEE24CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS20 *((volatile unsigned int*)(0x42CEE250UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS21 *((volatile unsigned int*)(0x42CEE254UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS22 *((volatile unsigned int*)(0x42CEE258UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS23 *((volatile unsigned int*)(0x42CEE25CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS24 *((volatile unsigned int*)(0x42CEE260UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS25 *((volatile unsigned int*)(0x42CEE264UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS26 *((volatile unsigned int*)(0x42CEE268UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS27 *((volatile unsigned int*)(0x42CEE26CUL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS28 *((volatile unsigned int*)(0x42CEE270UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS29 *((volatile unsigned int*)(0x42CEE274UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS30 *((volatile unsigned int*)(0x42CEE278UL)) +#define bFM3_ETHERNET_MAC1_STSUR_TSS31 *((volatile unsigned int*)(0x42CEE27CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS0 *((volatile unsigned int*)(0x42CEE280UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS1 *((volatile unsigned int*)(0x42CEE284UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS2 *((volatile unsigned int*)(0x42CEE288UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS3 *((volatile unsigned int*)(0x42CEE28CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS4 *((volatile unsigned int*)(0x42CEE290UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS5 *((volatile unsigned int*)(0x42CEE294UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS6 *((volatile unsigned int*)(0x42CEE298UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS7 *((volatile unsigned int*)(0x42CEE29CUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS8 *((volatile unsigned int*)(0x42CEE2A0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS9 *((volatile unsigned int*)(0x42CEE2A4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS10 *((volatile unsigned int*)(0x42CEE2A8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS11 *((volatile unsigned int*)(0x42CEE2ACUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS12 *((volatile unsigned int*)(0x42CEE2B0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS13 *((volatile unsigned int*)(0x42CEE2B4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS14 *((volatile unsigned int*)(0x42CEE2B8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS15 *((volatile unsigned int*)(0x42CEE2BCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS16 *((volatile unsigned int*)(0x42CEE2C0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS17 *((volatile unsigned int*)(0x42CEE2C4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS18 *((volatile unsigned int*)(0x42CEE2C8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS19 *((volatile unsigned int*)(0x42CEE2CCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS20 *((volatile unsigned int*)(0x42CEE2D0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS21 *((volatile unsigned int*)(0x42CEE2D4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS22 *((volatile unsigned int*)(0x42CEE2D8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS23 *((volatile unsigned int*)(0x42CEE2DCUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS24 *((volatile unsigned int*)(0x42CEE2E0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS25 *((volatile unsigned int*)(0x42CEE2E4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS26 *((volatile unsigned int*)(0x42CEE2E8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS27 *((volatile unsigned int*)(0x42CEE2ECUL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS28 *((volatile unsigned int*)(0x42CEE2F0UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS29 *((volatile unsigned int*)(0x42CEE2F4UL)) +#define bFM3_ETHERNET_MAC1_STNUR_TSSS30 *((volatile unsigned int*)(0x42CEE2F8UL)) +#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB *((volatile unsigned int*)(0x42CEE2FCUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR0 *((volatile unsigned int*)(0x42CEE300UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR1 *((volatile unsigned int*)(0x42CEE304UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR2 *((volatile unsigned int*)(0x42CEE308UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR3 *((volatile unsigned int*)(0x42CEE30CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR4 *((volatile unsigned int*)(0x42CEE310UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR5 *((volatile unsigned int*)(0x42CEE314UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR6 *((volatile unsigned int*)(0x42CEE318UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR7 *((volatile unsigned int*)(0x42CEE31CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR8 *((volatile unsigned int*)(0x42CEE320UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR9 *((volatile unsigned int*)(0x42CEE324UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR10 *((volatile unsigned int*)(0x42CEE328UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR11 *((volatile unsigned int*)(0x42CEE32CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR12 *((volatile unsigned int*)(0x42CEE330UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR13 *((volatile unsigned int*)(0x42CEE334UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR14 *((volatile unsigned int*)(0x42CEE338UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR15 *((volatile unsigned int*)(0x42CEE33CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR16 *((volatile unsigned int*)(0x42CEE340UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR17 *((volatile unsigned int*)(0x42CEE344UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR18 *((volatile unsigned int*)(0x42CEE348UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR19 *((volatile unsigned int*)(0x42CEE34CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR20 *((volatile unsigned int*)(0x42CEE350UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR21 *((volatile unsigned int*)(0x42CEE354UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR22 *((volatile unsigned int*)(0x42CEE358UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR23 *((volatile unsigned int*)(0x42CEE35CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR24 *((volatile unsigned int*)(0x42CEE360UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR25 *((volatile unsigned int*)(0x42CEE364UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR26 *((volatile unsigned int*)(0x42CEE368UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR27 *((volatile unsigned int*)(0x42CEE36CUL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR28 *((volatile unsigned int*)(0x42CEE370UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR29 *((volatile unsigned int*)(0x42CEE374UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR30 *((volatile unsigned int*)(0x42CEE378UL)) +#define bFM3_ETHERNET_MAC1_TSAR_TSAR31 *((volatile unsigned int*)(0x42CEE37CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR0 *((volatile unsigned int*)(0x42CEE380UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR1 *((volatile unsigned int*)(0x42CEE384UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR2 *((volatile unsigned int*)(0x42CEE388UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR3 *((volatile unsigned int*)(0x42CEE38CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR4 *((volatile unsigned int*)(0x42CEE390UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR5 *((volatile unsigned int*)(0x42CEE394UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR6 *((volatile unsigned int*)(0x42CEE398UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR7 *((volatile unsigned int*)(0x42CEE39CUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR8 *((volatile unsigned int*)(0x42CEE3A0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR9 *((volatile unsigned int*)(0x42CEE3A4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR10 *((volatile unsigned int*)(0x42CEE3A8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR11 *((volatile unsigned int*)(0x42CEE3ACUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR12 *((volatile unsigned int*)(0x42CEE3B0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR13 *((volatile unsigned int*)(0x42CEE3B4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR14 *((volatile unsigned int*)(0x42CEE3B8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR15 *((volatile unsigned int*)(0x42CEE3BCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR16 *((volatile unsigned int*)(0x42CEE3C0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR17 *((volatile unsigned int*)(0x42CEE3C4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR18 *((volatile unsigned int*)(0x42CEE3C8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR19 *((volatile unsigned int*)(0x42CEE3CCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR20 *((volatile unsigned int*)(0x42CEE3D0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR21 *((volatile unsigned int*)(0x42CEE3D4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR22 *((volatile unsigned int*)(0x42CEE3D8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR23 *((volatile unsigned int*)(0x42CEE3DCUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR24 *((volatile unsigned int*)(0x42CEE3E0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR25 *((volatile unsigned int*)(0x42CEE3E4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR26 *((volatile unsigned int*)(0x42CEE3E8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR27 *((volatile unsigned int*)(0x42CEE3ECUL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR28 *((volatile unsigned int*)(0x42CEE3F0UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR29 *((volatile unsigned int*)(0x42CEE3F4UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR30 *((volatile unsigned int*)(0x42CEE3F8UL)) +#define bFM3_ETHERNET_MAC1_TTSR_TSTR31 *((volatile unsigned int*)(0x42CEE3FCUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR0 *((volatile unsigned int*)(0x42CEE400UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR1 *((volatile unsigned int*)(0x42CEE404UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR2 *((volatile unsigned int*)(0x42CEE408UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR3 *((volatile unsigned int*)(0x42CEE40CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR4 *((volatile unsigned int*)(0x42CEE410UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR5 *((volatile unsigned int*)(0x42CEE414UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR6 *((volatile unsigned int*)(0x42CEE418UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR7 *((volatile unsigned int*)(0x42CEE41CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR8 *((volatile unsigned int*)(0x42CEE420UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR9 *((volatile unsigned int*)(0x42CEE424UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR10 *((volatile unsigned int*)(0x42CEE428UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR11 *((volatile unsigned int*)(0x42CEE42CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR12 *((volatile unsigned int*)(0x42CEE430UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR13 *((volatile unsigned int*)(0x42CEE434UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR14 *((volatile unsigned int*)(0x42CEE438UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR15 *((volatile unsigned int*)(0x42CEE43CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR16 *((volatile unsigned int*)(0x42CEE440UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR17 *((volatile unsigned int*)(0x42CEE444UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR18 *((volatile unsigned int*)(0x42CEE448UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR19 *((volatile unsigned int*)(0x42CEE44CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR20 *((volatile unsigned int*)(0x42CEE450UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR21 *((volatile unsigned int*)(0x42CEE454UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR22 *((volatile unsigned int*)(0x42CEE458UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR23 *((volatile unsigned int*)(0x42CEE45CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR24 *((volatile unsigned int*)(0x42CEE460UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR25 *((volatile unsigned int*)(0x42CEE464UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR26 *((volatile unsigned int*)(0x42CEE468UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR27 *((volatile unsigned int*)(0x42CEE46CUL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR28 *((volatile unsigned int*)(0x42CEE470UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR29 *((volatile unsigned int*)(0x42CEE474UL)) +#define bFM3_ETHERNET_MAC1_TTNR_TSTR30 *((volatile unsigned int*)(0x42CEE478UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42CEE480UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42CEE484UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42CEE488UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42CEE48CUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42CEE490UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42CEE494UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42CEE498UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42CEE49CUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42CEE4A0UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42CEE4A4UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42CEE4A8UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42CEE4ACUL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42CEE4B0UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42CEE4B4UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42CEE4B8UL)) +#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42CEE4BCUL)) +#define bFM3_ETHERNET_MAC1_TSR_TSSOVF *((volatile unsigned int*)(0x42CEE500UL)) +#define bFM3_ETHERNET_MAC1_TSR_TSTART *((volatile unsigned int*)(0x42CEE504UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSTS *((volatile unsigned int*)(0x42CEE508UL)) +#define bFM3_ETHERNET_MAC1_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSSTM *((volatile unsigned int*)(0x42CEE560UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS0 *((volatile unsigned int*)(0x42CEE564UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS1 *((volatile unsigned int*)(0x42CEE568UL)) +#define bFM3_ETHERNET_MAC1_TSR_ATSNS2 *((volatile unsigned int*)(0x42CEE56CUL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42CEE580UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42CEE584UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42CEE588UL)) +#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42CEE58CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN0 *((volatile unsigned int*)(0x42CEE600UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN1 *((volatile unsigned int*)(0x42CEE604UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN2 *((volatile unsigned int*)(0x42CEE608UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN3 *((volatile unsigned int*)(0x42CEE60CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN4 *((volatile unsigned int*)(0x42CEE610UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN5 *((volatile unsigned int*)(0x42CEE614UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN6 *((volatile unsigned int*)(0x42CEE618UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN7 *((volatile unsigned int*)(0x42CEE61CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN8 *((volatile unsigned int*)(0x42CEE620UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN9 *((volatile unsigned int*)(0x42CEE624UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN10 *((volatile unsigned int*)(0x42CEE628UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN11 *((volatile unsigned int*)(0x42CEE62CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN12 *((volatile unsigned int*)(0x42CEE630UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN13 *((volatile unsigned int*)(0x42CEE634UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN14 *((volatile unsigned int*)(0x42CEE638UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN15 *((volatile unsigned int*)(0x42CEE63CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN16 *((volatile unsigned int*)(0x42CEE640UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN17 *((volatile unsigned int*)(0x42CEE644UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN18 *((volatile unsigned int*)(0x42CEE648UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN19 *((volatile unsigned int*)(0x42CEE64CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN20 *((volatile unsigned int*)(0x42CEE650UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN21 *((volatile unsigned int*)(0x42CEE654UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN22 *((volatile unsigned int*)(0x42CEE658UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN23 *((volatile unsigned int*)(0x42CEE65CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN24 *((volatile unsigned int*)(0x42CEE660UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN25 *((volatile unsigned int*)(0x42CEE664UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN26 *((volatile unsigned int*)(0x42CEE668UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN27 *((volatile unsigned int*)(0x42CEE66CUL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN28 *((volatile unsigned int*)(0x42CEE670UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN29 *((volatile unsigned int*)(0x42CEE674UL)) +#define bFM3_ETHERNET_MAC1_ATNR_ATN30 *((volatile unsigned int*)(0x42CEE678UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS0 *((volatile unsigned int*)(0x42CEE680UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS1 *((volatile unsigned int*)(0x42CEE684UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS2 *((volatile unsigned int*)(0x42CEE688UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS3 *((volatile unsigned int*)(0x42CEE68CUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS4 *((volatile unsigned int*)(0x42CEE690UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS5 *((volatile unsigned int*)(0x42CEE694UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS6 *((volatile unsigned int*)(0x42CEE698UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS7 *((volatile unsigned int*)(0x42CEE69CUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS8 *((volatile unsigned int*)(0x42CEE6A0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS9 *((volatile unsigned int*)(0x42CEE6A4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS10 *((volatile unsigned int*)(0x42CEE6A8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS11 *((volatile unsigned int*)(0x42CEE6ACUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS12 *((volatile unsigned int*)(0x42CEE6B0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS13 *((volatile unsigned int*)(0x42CEE6B4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS14 *((volatile unsigned int*)(0x42CEE6B8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS15 *((volatile unsigned int*)(0x42CEE6BCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS16 *((volatile unsigned int*)(0x42CEE6C0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS17 *((volatile unsigned int*)(0x42CEE6C4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS18 *((volatile unsigned int*)(0x42CEE6C8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS19 *((volatile unsigned int*)(0x42CEE6CCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS20 *((volatile unsigned int*)(0x42CEE6D0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS21 *((volatile unsigned int*)(0x42CEE6D4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS22 *((volatile unsigned int*)(0x42CEE6D8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS23 *((volatile unsigned int*)(0x42CEE6DCUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS24 *((volatile unsigned int*)(0x42CEE6E0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS25 *((volatile unsigned int*)(0x42CEE6E4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS26 *((volatile unsigned int*)(0x42CEE6E8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS27 *((volatile unsigned int*)(0x42CEE6ECUL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS28 *((volatile unsigned int*)(0x42CEE6F0UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS29 *((volatile unsigned int*)(0x42CEE6F4UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS30 *((volatile unsigned int*)(0x42CEE6F8UL)) +#define bFM3_ETHERNET_MAC1_ATSR_ATS31 *((volatile unsigned int*)(0x42CEE6FCUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A32 *((volatile unsigned int*)(0x42CF0000UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A33 *((volatile unsigned int*)(0x42CF0004UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A34 *((volatile unsigned int*)(0x42CF0008UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A35 *((volatile unsigned int*)(0x42CF000CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A36 *((volatile unsigned int*)(0x42CF0010UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A37 *((volatile unsigned int*)(0x42CF0014UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A38 *((volatile unsigned int*)(0x42CF0018UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A39 *((volatile unsigned int*)(0x42CF001CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A40 *((volatile unsigned int*)(0x42CF0020UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A41 *((volatile unsigned int*)(0x42CF0024UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A42 *((volatile unsigned int*)(0x42CF0028UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A43 *((volatile unsigned int*)(0x42CF002CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A44 *((volatile unsigned int*)(0x42CF0030UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A45 *((volatile unsigned int*)(0x42CF0034UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A46 *((volatile unsigned int*)(0x42CF0038UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_A47 *((volatile unsigned int*)(0x42CF003CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC0 *((volatile unsigned int*)(0x42CF0060UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC1 *((volatile unsigned int*)(0x42CF0064UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC2 *((volatile unsigned int*)(0x42CF0068UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC3 *((volatile unsigned int*)(0x42CF006CUL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC4 *((volatile unsigned int*)(0x42CF0070UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_MBC5 *((volatile unsigned int*)(0x42CF0074UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_SA *((volatile unsigned int*)(0x42CF0078UL)) +#define bFM3_ETHERNET_MAC1_MAR16H_AE *((volatile unsigned int*)(0x42CF007CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A0 *((volatile unsigned int*)(0x42CF0080UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A1 *((volatile unsigned int*)(0x42CF0084UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A2 *((volatile unsigned int*)(0x42CF0088UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A3 *((volatile unsigned int*)(0x42CF008CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A4 *((volatile unsigned int*)(0x42CF0090UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A5 *((volatile unsigned int*)(0x42CF0094UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A6 *((volatile unsigned int*)(0x42CF0098UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A7 *((volatile unsigned int*)(0x42CF009CUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A8 *((volatile unsigned int*)(0x42CF00A0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A9 *((volatile unsigned int*)(0x42CF00A4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A10 *((volatile unsigned int*)(0x42CF00A8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A11 *((volatile unsigned int*)(0x42CF00ACUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A12 *((volatile unsigned int*)(0x42CF00B0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A13 *((volatile unsigned int*)(0x42CF00B4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A14 *((volatile unsigned int*)(0x42CF00B8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A15 *((volatile unsigned int*)(0x42CF00BCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A16 *((volatile unsigned int*)(0x42CF00C0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A17 *((volatile unsigned int*)(0x42CF00C4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A18 *((volatile unsigned int*)(0x42CF00C8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A19 *((volatile unsigned int*)(0x42CF00CCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A20 *((volatile unsigned int*)(0x42CF00D0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A21 *((volatile unsigned int*)(0x42CF00D4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A22 *((volatile unsigned int*)(0x42CF00D8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A23 *((volatile unsigned int*)(0x42CF00DCUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A24 *((volatile unsigned int*)(0x42CF00E0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A25 *((volatile unsigned int*)(0x42CF00E4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A26 *((volatile unsigned int*)(0x42CF00E8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A27 *((volatile unsigned int*)(0x42CF00ECUL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A28 *((volatile unsigned int*)(0x42CF00F0UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A29 *((volatile unsigned int*)(0x42CF00F4UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A30 *((volatile unsigned int*)(0x42CF00F8UL)) +#define bFM3_ETHERNET_MAC1_MAR16L_A31 *((volatile unsigned int*)(0x42CF00FCUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A32 *((volatile unsigned int*)(0x42CF0100UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A33 *((volatile unsigned int*)(0x42CF0104UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A34 *((volatile unsigned int*)(0x42CF0108UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A35 *((volatile unsigned int*)(0x42CF010CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A36 *((volatile unsigned int*)(0x42CF0110UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A37 *((volatile unsigned int*)(0x42CF0114UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A38 *((volatile unsigned int*)(0x42CF0118UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A39 *((volatile unsigned int*)(0x42CF011CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A40 *((volatile unsigned int*)(0x42CF0120UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A41 *((volatile unsigned int*)(0x42CF0124UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A42 *((volatile unsigned int*)(0x42CF0128UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A43 *((volatile unsigned int*)(0x42CF012CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A44 *((volatile unsigned int*)(0x42CF0130UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A45 *((volatile unsigned int*)(0x42CF0134UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A46 *((volatile unsigned int*)(0x42CF0138UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_A47 *((volatile unsigned int*)(0x42CF013CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC0 *((volatile unsigned int*)(0x42CF0160UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC1 *((volatile unsigned int*)(0x42CF0164UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC2 *((volatile unsigned int*)(0x42CF0168UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC3 *((volatile unsigned int*)(0x42CF016CUL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC4 *((volatile unsigned int*)(0x42CF0170UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_MBC5 *((volatile unsigned int*)(0x42CF0174UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_SA *((volatile unsigned int*)(0x42CF0178UL)) +#define bFM3_ETHERNET_MAC1_MAR17H_AE *((volatile unsigned int*)(0x42CF017CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A0 *((volatile unsigned int*)(0x42CF0180UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A1 *((volatile unsigned int*)(0x42CF0184UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A2 *((volatile unsigned int*)(0x42CF0188UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A3 *((volatile unsigned int*)(0x42CF018CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A4 *((volatile unsigned int*)(0x42CF0190UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A5 *((volatile unsigned int*)(0x42CF0194UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A6 *((volatile unsigned int*)(0x42CF0198UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A7 *((volatile unsigned int*)(0x42CF019CUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A8 *((volatile unsigned int*)(0x42CF01A0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A9 *((volatile unsigned int*)(0x42CF01A4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A10 *((volatile unsigned int*)(0x42CF01A8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A11 *((volatile unsigned int*)(0x42CF01ACUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A12 *((volatile unsigned int*)(0x42CF01B0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A13 *((volatile unsigned int*)(0x42CF01B4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A14 *((volatile unsigned int*)(0x42CF01B8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A15 *((volatile unsigned int*)(0x42CF01BCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A16 *((volatile unsigned int*)(0x42CF01C0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A17 *((volatile unsigned int*)(0x42CF01C4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A18 *((volatile unsigned int*)(0x42CF01C8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A19 *((volatile unsigned int*)(0x42CF01CCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A20 *((volatile unsigned int*)(0x42CF01D0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A21 *((volatile unsigned int*)(0x42CF01D4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A22 *((volatile unsigned int*)(0x42CF01D8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A23 *((volatile unsigned int*)(0x42CF01DCUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A24 *((volatile unsigned int*)(0x42CF01E0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A25 *((volatile unsigned int*)(0x42CF01E4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A26 *((volatile unsigned int*)(0x42CF01E8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A27 *((volatile unsigned int*)(0x42CF01ECUL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A28 *((volatile unsigned int*)(0x42CF01F0UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A29 *((volatile unsigned int*)(0x42CF01F4UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A30 *((volatile unsigned int*)(0x42CF01F8UL)) +#define bFM3_ETHERNET_MAC1_MAR17L_A31 *((volatile unsigned int*)(0x42CF01FCUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A32 *((volatile unsigned int*)(0x42CF0200UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A33 *((volatile unsigned int*)(0x42CF0204UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A34 *((volatile unsigned int*)(0x42CF0208UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A35 *((volatile unsigned int*)(0x42CF020CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A36 *((volatile unsigned int*)(0x42CF0210UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A37 *((volatile unsigned int*)(0x42CF0214UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A38 *((volatile unsigned int*)(0x42CF0218UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A39 *((volatile unsigned int*)(0x42CF021CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A40 *((volatile unsigned int*)(0x42CF0220UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A41 *((volatile unsigned int*)(0x42CF0224UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A42 *((volatile unsigned int*)(0x42CF0228UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A43 *((volatile unsigned int*)(0x42CF022CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A44 *((volatile unsigned int*)(0x42CF0230UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A45 *((volatile unsigned int*)(0x42CF0234UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A46 *((volatile unsigned int*)(0x42CF0238UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_A47 *((volatile unsigned int*)(0x42CF023CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC0 *((volatile unsigned int*)(0x42CF0260UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC1 *((volatile unsigned int*)(0x42CF0264UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC2 *((volatile unsigned int*)(0x42CF0268UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC3 *((volatile unsigned int*)(0x42CF026CUL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC4 *((volatile unsigned int*)(0x42CF0270UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_MBC5 *((volatile unsigned int*)(0x42CF0274UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_SA *((volatile unsigned int*)(0x42CF0278UL)) +#define bFM3_ETHERNET_MAC1_MAR18H_AE *((volatile unsigned int*)(0x42CF027CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A0 *((volatile unsigned int*)(0x42CF0280UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A1 *((volatile unsigned int*)(0x42CF0284UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A2 *((volatile unsigned int*)(0x42CF0288UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A3 *((volatile unsigned int*)(0x42CF028CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A4 *((volatile unsigned int*)(0x42CF0290UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A5 *((volatile unsigned int*)(0x42CF0294UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A6 *((volatile unsigned int*)(0x42CF0298UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A7 *((volatile unsigned int*)(0x42CF029CUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A8 *((volatile unsigned int*)(0x42CF02A0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A9 *((volatile unsigned int*)(0x42CF02A4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A10 *((volatile unsigned int*)(0x42CF02A8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A11 *((volatile unsigned int*)(0x42CF02ACUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A12 *((volatile unsigned int*)(0x42CF02B0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A13 *((volatile unsigned int*)(0x42CF02B4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A14 *((volatile unsigned int*)(0x42CF02B8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A15 *((volatile unsigned int*)(0x42CF02BCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A16 *((volatile unsigned int*)(0x42CF02C0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A17 *((volatile unsigned int*)(0x42CF02C4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A18 *((volatile unsigned int*)(0x42CF02C8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A19 *((volatile unsigned int*)(0x42CF02CCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A20 *((volatile unsigned int*)(0x42CF02D0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A21 *((volatile unsigned int*)(0x42CF02D4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A22 *((volatile unsigned int*)(0x42CF02D8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A23 *((volatile unsigned int*)(0x42CF02DCUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A24 *((volatile unsigned int*)(0x42CF02E0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A25 *((volatile unsigned int*)(0x42CF02E4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A26 *((volatile unsigned int*)(0x42CF02E8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A27 *((volatile unsigned int*)(0x42CF02ECUL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A28 *((volatile unsigned int*)(0x42CF02F0UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A29 *((volatile unsigned int*)(0x42CF02F4UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A30 *((volatile unsigned int*)(0x42CF02F8UL)) +#define bFM3_ETHERNET_MAC1_MAR18L_A31 *((volatile unsigned int*)(0x42CF02FCUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A32 *((volatile unsigned int*)(0x42CF0300UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A33 *((volatile unsigned int*)(0x42CF0304UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A34 *((volatile unsigned int*)(0x42CF0308UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A35 *((volatile unsigned int*)(0x42CF030CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A36 *((volatile unsigned int*)(0x42CF0310UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A37 *((volatile unsigned int*)(0x42CF0314UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A38 *((volatile unsigned int*)(0x42CF0318UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A39 *((volatile unsigned int*)(0x42CF031CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A40 *((volatile unsigned int*)(0x42CF0320UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A41 *((volatile unsigned int*)(0x42CF0324UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A42 *((volatile unsigned int*)(0x42CF0328UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A43 *((volatile unsigned int*)(0x42CF032CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A44 *((volatile unsigned int*)(0x42CF0330UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A45 *((volatile unsigned int*)(0x42CF0334UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A46 *((volatile unsigned int*)(0x42CF0338UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_A47 *((volatile unsigned int*)(0x42CF033CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC0 *((volatile unsigned int*)(0x42CF0360UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC1 *((volatile unsigned int*)(0x42CF0364UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC2 *((volatile unsigned int*)(0x42CF0368UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC3 *((volatile unsigned int*)(0x42CF036CUL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC4 *((volatile unsigned int*)(0x42CF0370UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_MBC5 *((volatile unsigned int*)(0x42CF0374UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_SA *((volatile unsigned int*)(0x42CF0378UL)) +#define bFM3_ETHERNET_MAC1_MAR19H_AE *((volatile unsigned int*)(0x42CF037CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A0 *((volatile unsigned int*)(0x42CF0380UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A1 *((volatile unsigned int*)(0x42CF0384UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A2 *((volatile unsigned int*)(0x42CF0388UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A3 *((volatile unsigned int*)(0x42CF038CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A4 *((volatile unsigned int*)(0x42CF0390UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A5 *((volatile unsigned int*)(0x42CF0394UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A6 *((volatile unsigned int*)(0x42CF0398UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A7 *((volatile unsigned int*)(0x42CF039CUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A8 *((volatile unsigned int*)(0x42CF03A0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A9 *((volatile unsigned int*)(0x42CF03A4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A10 *((volatile unsigned int*)(0x42CF03A8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A11 *((volatile unsigned int*)(0x42CF03ACUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A12 *((volatile unsigned int*)(0x42CF03B0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A13 *((volatile unsigned int*)(0x42CF03B4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A14 *((volatile unsigned int*)(0x42CF03B8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A15 *((volatile unsigned int*)(0x42CF03BCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A16 *((volatile unsigned int*)(0x42CF03C0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A17 *((volatile unsigned int*)(0x42CF03C4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A18 *((volatile unsigned int*)(0x42CF03C8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A19 *((volatile unsigned int*)(0x42CF03CCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A20 *((volatile unsigned int*)(0x42CF03D0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A21 *((volatile unsigned int*)(0x42CF03D4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A22 *((volatile unsigned int*)(0x42CF03D8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A23 *((volatile unsigned int*)(0x42CF03DCUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A24 *((volatile unsigned int*)(0x42CF03E0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A25 *((volatile unsigned int*)(0x42CF03E4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A26 *((volatile unsigned int*)(0x42CF03E8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A27 *((volatile unsigned int*)(0x42CF03ECUL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A28 *((volatile unsigned int*)(0x42CF03F0UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A29 *((volatile unsigned int*)(0x42CF03F4UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A30 *((volatile unsigned int*)(0x42CF03F8UL)) +#define bFM3_ETHERNET_MAC1_MAR19L_A31 *((volatile unsigned int*)(0x42CF03FCUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A32 *((volatile unsigned int*)(0x42CF0400UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A33 *((volatile unsigned int*)(0x42CF0404UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A34 *((volatile unsigned int*)(0x42CF0408UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A35 *((volatile unsigned int*)(0x42CF040CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A36 *((volatile unsigned int*)(0x42CF0410UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A37 *((volatile unsigned int*)(0x42CF0414UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A38 *((volatile unsigned int*)(0x42CF0418UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A39 *((volatile unsigned int*)(0x42CF041CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A40 *((volatile unsigned int*)(0x42CF0420UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A41 *((volatile unsigned int*)(0x42CF0424UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A42 *((volatile unsigned int*)(0x42CF0428UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A43 *((volatile unsigned int*)(0x42CF042CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A44 *((volatile unsigned int*)(0x42CF0430UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A45 *((volatile unsigned int*)(0x42CF0434UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A46 *((volatile unsigned int*)(0x42CF0438UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_A47 *((volatile unsigned int*)(0x42CF043CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC0 *((volatile unsigned int*)(0x42CF0460UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC1 *((volatile unsigned int*)(0x42CF0464UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC2 *((volatile unsigned int*)(0x42CF0468UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC3 *((volatile unsigned int*)(0x42CF046CUL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC4 *((volatile unsigned int*)(0x42CF0470UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_MBC5 *((volatile unsigned int*)(0x42CF0474UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_SA *((volatile unsigned int*)(0x42CF0478UL)) +#define bFM3_ETHERNET_MAC1_MAR20H_AE *((volatile unsigned int*)(0x42CF047CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A0 *((volatile unsigned int*)(0x42CF0480UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A1 *((volatile unsigned int*)(0x42CF0484UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A2 *((volatile unsigned int*)(0x42CF0488UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A3 *((volatile unsigned int*)(0x42CF048CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A4 *((volatile unsigned int*)(0x42CF0490UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A5 *((volatile unsigned int*)(0x42CF0494UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A6 *((volatile unsigned int*)(0x42CF0498UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A7 *((volatile unsigned int*)(0x42CF049CUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A8 *((volatile unsigned int*)(0x42CF04A0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A9 *((volatile unsigned int*)(0x42CF04A4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A10 *((volatile unsigned int*)(0x42CF04A8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A11 *((volatile unsigned int*)(0x42CF04ACUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A12 *((volatile unsigned int*)(0x42CF04B0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A13 *((volatile unsigned int*)(0x42CF04B4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A14 *((volatile unsigned int*)(0x42CF04B8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A15 *((volatile unsigned int*)(0x42CF04BCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A16 *((volatile unsigned int*)(0x42CF04C0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A17 *((volatile unsigned int*)(0x42CF04C4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A18 *((volatile unsigned int*)(0x42CF04C8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A19 *((volatile unsigned int*)(0x42CF04CCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A20 *((volatile unsigned int*)(0x42CF04D0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A21 *((volatile unsigned int*)(0x42CF04D4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A22 *((volatile unsigned int*)(0x42CF04D8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A23 *((volatile unsigned int*)(0x42CF04DCUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A24 *((volatile unsigned int*)(0x42CF04E0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A25 *((volatile unsigned int*)(0x42CF04E4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A26 *((volatile unsigned int*)(0x42CF04E8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A27 *((volatile unsigned int*)(0x42CF04ECUL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A28 *((volatile unsigned int*)(0x42CF04F0UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A29 *((volatile unsigned int*)(0x42CF04F4UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A30 *((volatile unsigned int*)(0x42CF04F8UL)) +#define bFM3_ETHERNET_MAC1_MAR20L_A31 *((volatile unsigned int*)(0x42CF04FCUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A32 *((volatile unsigned int*)(0x42CF0500UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A33 *((volatile unsigned int*)(0x42CF0504UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A34 *((volatile unsigned int*)(0x42CF0508UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A35 *((volatile unsigned int*)(0x42CF050CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A36 *((volatile unsigned int*)(0x42CF0510UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A37 *((volatile unsigned int*)(0x42CF0514UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A38 *((volatile unsigned int*)(0x42CF0518UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A39 *((volatile unsigned int*)(0x42CF051CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A40 *((volatile unsigned int*)(0x42CF0520UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A41 *((volatile unsigned int*)(0x42CF0524UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A42 *((volatile unsigned int*)(0x42CF0528UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A43 *((volatile unsigned int*)(0x42CF052CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A44 *((volatile unsigned int*)(0x42CF0530UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A45 *((volatile unsigned int*)(0x42CF0534UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A46 *((volatile unsigned int*)(0x42CF0538UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_A47 *((volatile unsigned int*)(0x42CF053CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC0 *((volatile unsigned int*)(0x42CF0560UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC1 *((volatile unsigned int*)(0x42CF0564UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC2 *((volatile unsigned int*)(0x42CF0568UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC3 *((volatile unsigned int*)(0x42CF056CUL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC4 *((volatile unsigned int*)(0x42CF0570UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_MBC5 *((volatile unsigned int*)(0x42CF0574UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_SA *((volatile unsigned int*)(0x42CF0578UL)) +#define bFM3_ETHERNET_MAC1_MAR21H_AE *((volatile unsigned int*)(0x42CF057CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A0 *((volatile unsigned int*)(0x42CF0580UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A1 *((volatile unsigned int*)(0x42CF0584UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A2 *((volatile unsigned int*)(0x42CF0588UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A3 *((volatile unsigned int*)(0x42CF058CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A4 *((volatile unsigned int*)(0x42CF0590UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A5 *((volatile unsigned int*)(0x42CF0594UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A6 *((volatile unsigned int*)(0x42CF0598UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A7 *((volatile unsigned int*)(0x42CF059CUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A8 *((volatile unsigned int*)(0x42CF05A0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A9 *((volatile unsigned int*)(0x42CF05A4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A10 *((volatile unsigned int*)(0x42CF05A8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A11 *((volatile unsigned int*)(0x42CF05ACUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A12 *((volatile unsigned int*)(0x42CF05B0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A13 *((volatile unsigned int*)(0x42CF05B4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A14 *((volatile unsigned int*)(0x42CF05B8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A15 *((volatile unsigned int*)(0x42CF05BCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A16 *((volatile unsigned int*)(0x42CF05C0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A17 *((volatile unsigned int*)(0x42CF05C4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A18 *((volatile unsigned int*)(0x42CF05C8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A19 *((volatile unsigned int*)(0x42CF05CCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A20 *((volatile unsigned int*)(0x42CF05D0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A21 *((volatile unsigned int*)(0x42CF05D4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A22 *((volatile unsigned int*)(0x42CF05D8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A23 *((volatile unsigned int*)(0x42CF05DCUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A24 *((volatile unsigned int*)(0x42CF05E0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A25 *((volatile unsigned int*)(0x42CF05E4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A26 *((volatile unsigned int*)(0x42CF05E8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A27 *((volatile unsigned int*)(0x42CF05ECUL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A28 *((volatile unsigned int*)(0x42CF05F0UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A29 *((volatile unsigned int*)(0x42CF05F4UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A30 *((volatile unsigned int*)(0x42CF05F8UL)) +#define bFM3_ETHERNET_MAC1_MAR21L_A31 *((volatile unsigned int*)(0x42CF05FCUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A32 *((volatile unsigned int*)(0x42CF0600UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A33 *((volatile unsigned int*)(0x42CF0604UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A34 *((volatile unsigned int*)(0x42CF0608UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A35 *((volatile unsigned int*)(0x42CF060CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A36 *((volatile unsigned int*)(0x42CF0610UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A37 *((volatile unsigned int*)(0x42CF0614UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A38 *((volatile unsigned int*)(0x42CF0618UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A39 *((volatile unsigned int*)(0x42CF061CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A40 *((volatile unsigned int*)(0x42CF0620UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A41 *((volatile unsigned int*)(0x42CF0624UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A42 *((volatile unsigned int*)(0x42CF0628UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A43 *((volatile unsigned int*)(0x42CF062CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A44 *((volatile unsigned int*)(0x42CF0630UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A45 *((volatile unsigned int*)(0x42CF0634UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A46 *((volatile unsigned int*)(0x42CF0638UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_A47 *((volatile unsigned int*)(0x42CF063CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC0 *((volatile unsigned int*)(0x42CF0660UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC1 *((volatile unsigned int*)(0x42CF0664UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC2 *((volatile unsigned int*)(0x42CF0668UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC3 *((volatile unsigned int*)(0x42CF066CUL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC4 *((volatile unsigned int*)(0x42CF0670UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_MBC5 *((volatile unsigned int*)(0x42CF0674UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_SA *((volatile unsigned int*)(0x42CF0678UL)) +#define bFM3_ETHERNET_MAC1_MAR22H_AE *((volatile unsigned int*)(0x42CF067CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A0 *((volatile unsigned int*)(0x42CF0680UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A1 *((volatile unsigned int*)(0x42CF0684UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A2 *((volatile unsigned int*)(0x42CF0688UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A3 *((volatile unsigned int*)(0x42CF068CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A4 *((volatile unsigned int*)(0x42CF0690UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A5 *((volatile unsigned int*)(0x42CF0694UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A6 *((volatile unsigned int*)(0x42CF0698UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A7 *((volatile unsigned int*)(0x42CF069CUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A8 *((volatile unsigned int*)(0x42CF06A0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A9 *((volatile unsigned int*)(0x42CF06A4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A10 *((volatile unsigned int*)(0x42CF06A8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A11 *((volatile unsigned int*)(0x42CF06ACUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A12 *((volatile unsigned int*)(0x42CF06B0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A13 *((volatile unsigned int*)(0x42CF06B4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A14 *((volatile unsigned int*)(0x42CF06B8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A15 *((volatile unsigned int*)(0x42CF06BCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A16 *((volatile unsigned int*)(0x42CF06C0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A17 *((volatile unsigned int*)(0x42CF06C4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A18 *((volatile unsigned int*)(0x42CF06C8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A19 *((volatile unsigned int*)(0x42CF06CCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A20 *((volatile unsigned int*)(0x42CF06D0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A21 *((volatile unsigned int*)(0x42CF06D4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A22 *((volatile unsigned int*)(0x42CF06D8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A23 *((volatile unsigned int*)(0x42CF06DCUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A24 *((volatile unsigned int*)(0x42CF06E0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A25 *((volatile unsigned int*)(0x42CF06E4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A26 *((volatile unsigned int*)(0x42CF06E8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A27 *((volatile unsigned int*)(0x42CF06ECUL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A28 *((volatile unsigned int*)(0x42CF06F0UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A29 *((volatile unsigned int*)(0x42CF06F4UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A30 *((volatile unsigned int*)(0x42CF06F8UL)) +#define bFM3_ETHERNET_MAC1_MAR22L_A31 *((volatile unsigned int*)(0x42CF06FCUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A32 *((volatile unsigned int*)(0x42CF0700UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A33 *((volatile unsigned int*)(0x42CF0704UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A34 *((volatile unsigned int*)(0x42CF0708UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A35 *((volatile unsigned int*)(0x42CF070CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A36 *((volatile unsigned int*)(0x42CF0710UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A37 *((volatile unsigned int*)(0x42CF0714UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A38 *((volatile unsigned int*)(0x42CF0718UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A39 *((volatile unsigned int*)(0x42CF071CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A40 *((volatile unsigned int*)(0x42CF0720UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A41 *((volatile unsigned int*)(0x42CF0724UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A42 *((volatile unsigned int*)(0x42CF0728UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A43 *((volatile unsigned int*)(0x42CF072CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A44 *((volatile unsigned int*)(0x42CF0730UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A45 *((volatile unsigned int*)(0x42CF0734UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A46 *((volatile unsigned int*)(0x42CF0738UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_A47 *((volatile unsigned int*)(0x42CF073CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC0 *((volatile unsigned int*)(0x42CF0760UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC1 *((volatile unsigned int*)(0x42CF0764UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC2 *((volatile unsigned int*)(0x42CF0768UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC3 *((volatile unsigned int*)(0x42CF076CUL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC4 *((volatile unsigned int*)(0x42CF0770UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_MBC5 *((volatile unsigned int*)(0x42CF0774UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_SA *((volatile unsigned int*)(0x42CF0778UL)) +#define bFM3_ETHERNET_MAC1_MAR23H_AE *((volatile unsigned int*)(0x42CF077CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A0 *((volatile unsigned int*)(0x42CF0780UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A1 *((volatile unsigned int*)(0x42CF0784UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A2 *((volatile unsigned int*)(0x42CF0788UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A3 *((volatile unsigned int*)(0x42CF078CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A4 *((volatile unsigned int*)(0x42CF0790UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A5 *((volatile unsigned int*)(0x42CF0794UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A6 *((volatile unsigned int*)(0x42CF0798UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A7 *((volatile unsigned int*)(0x42CF079CUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A8 *((volatile unsigned int*)(0x42CF07A0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A9 *((volatile unsigned int*)(0x42CF07A4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A10 *((volatile unsigned int*)(0x42CF07A8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A11 *((volatile unsigned int*)(0x42CF07ACUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A12 *((volatile unsigned int*)(0x42CF07B0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A13 *((volatile unsigned int*)(0x42CF07B4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A14 *((volatile unsigned int*)(0x42CF07B8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A15 *((volatile unsigned int*)(0x42CF07BCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A16 *((volatile unsigned int*)(0x42CF07C0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A17 *((volatile unsigned int*)(0x42CF07C4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A18 *((volatile unsigned int*)(0x42CF07C8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A19 *((volatile unsigned int*)(0x42CF07CCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A20 *((volatile unsigned int*)(0x42CF07D0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A21 *((volatile unsigned int*)(0x42CF07D4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A22 *((volatile unsigned int*)(0x42CF07D8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A23 *((volatile unsigned int*)(0x42CF07DCUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A24 *((volatile unsigned int*)(0x42CF07E0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A25 *((volatile unsigned int*)(0x42CF07E4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A26 *((volatile unsigned int*)(0x42CF07E8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A27 *((volatile unsigned int*)(0x42CF07ECUL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A28 *((volatile unsigned int*)(0x42CF07F0UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A29 *((volatile unsigned int*)(0x42CF07F4UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A30 *((volatile unsigned int*)(0x42CF07F8UL)) +#define bFM3_ETHERNET_MAC1_MAR23L_A31 *((volatile unsigned int*)(0x42CF07FCUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A32 *((volatile unsigned int*)(0x42CF0800UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A33 *((volatile unsigned int*)(0x42CF0804UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A34 *((volatile unsigned int*)(0x42CF0808UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A35 *((volatile unsigned int*)(0x42CF080CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A36 *((volatile unsigned int*)(0x42CF0810UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A37 *((volatile unsigned int*)(0x42CF0814UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A38 *((volatile unsigned int*)(0x42CF0818UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A39 *((volatile unsigned int*)(0x42CF081CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A40 *((volatile unsigned int*)(0x42CF0820UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A41 *((volatile unsigned int*)(0x42CF0824UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A42 *((volatile unsigned int*)(0x42CF0828UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A43 *((volatile unsigned int*)(0x42CF082CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A44 *((volatile unsigned int*)(0x42CF0830UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A45 *((volatile unsigned int*)(0x42CF0834UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A46 *((volatile unsigned int*)(0x42CF0838UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_A47 *((volatile unsigned int*)(0x42CF083CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC0 *((volatile unsigned int*)(0x42CF0860UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC1 *((volatile unsigned int*)(0x42CF0864UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC2 *((volatile unsigned int*)(0x42CF0868UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC3 *((volatile unsigned int*)(0x42CF086CUL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC4 *((volatile unsigned int*)(0x42CF0870UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_MBC5 *((volatile unsigned int*)(0x42CF0874UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_SA *((volatile unsigned int*)(0x42CF0878UL)) +#define bFM3_ETHERNET_MAC1_MAR24H_AE *((volatile unsigned int*)(0x42CF087CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A0 *((volatile unsigned int*)(0x42CF0880UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A1 *((volatile unsigned int*)(0x42CF0884UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A2 *((volatile unsigned int*)(0x42CF0888UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A3 *((volatile unsigned int*)(0x42CF088CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A4 *((volatile unsigned int*)(0x42CF0890UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A5 *((volatile unsigned int*)(0x42CF0894UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A6 *((volatile unsigned int*)(0x42CF0898UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A7 *((volatile unsigned int*)(0x42CF089CUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A8 *((volatile unsigned int*)(0x42CF08A0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A9 *((volatile unsigned int*)(0x42CF08A4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A10 *((volatile unsigned int*)(0x42CF08A8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A11 *((volatile unsigned int*)(0x42CF08ACUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A12 *((volatile unsigned int*)(0x42CF08B0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A13 *((volatile unsigned int*)(0x42CF08B4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A14 *((volatile unsigned int*)(0x42CF08B8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A15 *((volatile unsigned int*)(0x42CF08BCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A16 *((volatile unsigned int*)(0x42CF08C0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A17 *((volatile unsigned int*)(0x42CF08C4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A18 *((volatile unsigned int*)(0x42CF08C8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A19 *((volatile unsigned int*)(0x42CF08CCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A20 *((volatile unsigned int*)(0x42CF08D0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A21 *((volatile unsigned int*)(0x42CF08D4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A22 *((volatile unsigned int*)(0x42CF08D8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A23 *((volatile unsigned int*)(0x42CF08DCUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A24 *((volatile unsigned int*)(0x42CF08E0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A25 *((volatile unsigned int*)(0x42CF08E4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A26 *((volatile unsigned int*)(0x42CF08E8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A27 *((volatile unsigned int*)(0x42CF08ECUL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A28 *((volatile unsigned int*)(0x42CF08F0UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A29 *((volatile unsigned int*)(0x42CF08F4UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A30 *((volatile unsigned int*)(0x42CF08F8UL)) +#define bFM3_ETHERNET_MAC1_MAR24L_A31 *((volatile unsigned int*)(0x42CF08FCUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A32 *((volatile unsigned int*)(0x42CF0900UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A33 *((volatile unsigned int*)(0x42CF0904UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A34 *((volatile unsigned int*)(0x42CF0908UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A35 *((volatile unsigned int*)(0x42CF090CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A36 *((volatile unsigned int*)(0x42CF0910UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A37 *((volatile unsigned int*)(0x42CF0914UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A38 *((volatile unsigned int*)(0x42CF0918UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A39 *((volatile unsigned int*)(0x42CF091CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A40 *((volatile unsigned int*)(0x42CF0920UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A41 *((volatile unsigned int*)(0x42CF0924UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A42 *((volatile unsigned int*)(0x42CF0928UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A43 *((volatile unsigned int*)(0x42CF092CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A44 *((volatile unsigned int*)(0x42CF0930UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A45 *((volatile unsigned int*)(0x42CF0934UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A46 *((volatile unsigned int*)(0x42CF0938UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_A47 *((volatile unsigned int*)(0x42CF093CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC0 *((volatile unsigned int*)(0x42CF0960UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC1 *((volatile unsigned int*)(0x42CF0964UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC2 *((volatile unsigned int*)(0x42CF0968UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC3 *((volatile unsigned int*)(0x42CF096CUL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC4 *((volatile unsigned int*)(0x42CF0970UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_MBC5 *((volatile unsigned int*)(0x42CF0974UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_SA *((volatile unsigned int*)(0x42CF0978UL)) +#define bFM3_ETHERNET_MAC1_MAR25H_AE *((volatile unsigned int*)(0x42CF097CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A0 *((volatile unsigned int*)(0x42CF0980UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A1 *((volatile unsigned int*)(0x42CF0984UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A2 *((volatile unsigned int*)(0x42CF0988UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A3 *((volatile unsigned int*)(0x42CF098CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A4 *((volatile unsigned int*)(0x42CF0990UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A5 *((volatile unsigned int*)(0x42CF0994UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A6 *((volatile unsigned int*)(0x42CF0998UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A7 *((volatile unsigned int*)(0x42CF099CUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A8 *((volatile unsigned int*)(0x42CF09A0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A9 *((volatile unsigned int*)(0x42CF09A4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A10 *((volatile unsigned int*)(0x42CF09A8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A11 *((volatile unsigned int*)(0x42CF09ACUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A12 *((volatile unsigned int*)(0x42CF09B0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A13 *((volatile unsigned int*)(0x42CF09B4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A14 *((volatile unsigned int*)(0x42CF09B8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A15 *((volatile unsigned int*)(0x42CF09BCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A16 *((volatile unsigned int*)(0x42CF09C0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A17 *((volatile unsigned int*)(0x42CF09C4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A18 *((volatile unsigned int*)(0x42CF09C8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A19 *((volatile unsigned int*)(0x42CF09CCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A20 *((volatile unsigned int*)(0x42CF09D0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A21 *((volatile unsigned int*)(0x42CF09D4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A22 *((volatile unsigned int*)(0x42CF09D8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A23 *((volatile unsigned int*)(0x42CF09DCUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A24 *((volatile unsigned int*)(0x42CF09E0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A25 *((volatile unsigned int*)(0x42CF09E4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A26 *((volatile unsigned int*)(0x42CF09E8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A27 *((volatile unsigned int*)(0x42CF09ECUL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A28 *((volatile unsigned int*)(0x42CF09F0UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A29 *((volatile unsigned int*)(0x42CF09F4UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A30 *((volatile unsigned int*)(0x42CF09F8UL)) +#define bFM3_ETHERNET_MAC1_MAR25L_A31 *((volatile unsigned int*)(0x42CF09FCUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A32 *((volatile unsigned int*)(0x42CF0A00UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A33 *((volatile unsigned int*)(0x42CF0A04UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A34 *((volatile unsigned int*)(0x42CF0A08UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A35 *((volatile unsigned int*)(0x42CF0A0CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A36 *((volatile unsigned int*)(0x42CF0A10UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A37 *((volatile unsigned int*)(0x42CF0A14UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A38 *((volatile unsigned int*)(0x42CF0A18UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A39 *((volatile unsigned int*)(0x42CF0A1CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A40 *((volatile unsigned int*)(0x42CF0A20UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A41 *((volatile unsigned int*)(0x42CF0A24UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A42 *((volatile unsigned int*)(0x42CF0A28UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A43 *((volatile unsigned int*)(0x42CF0A2CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A44 *((volatile unsigned int*)(0x42CF0A30UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A45 *((volatile unsigned int*)(0x42CF0A34UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A46 *((volatile unsigned int*)(0x42CF0A38UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_A47 *((volatile unsigned int*)(0x42CF0A3CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC0 *((volatile unsigned int*)(0x42CF0A60UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC1 *((volatile unsigned int*)(0x42CF0A64UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC2 *((volatile unsigned int*)(0x42CF0A68UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC3 *((volatile unsigned int*)(0x42CF0A6CUL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC4 *((volatile unsigned int*)(0x42CF0A70UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_MBC5 *((volatile unsigned int*)(0x42CF0A74UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_SA *((volatile unsigned int*)(0x42CF0A78UL)) +#define bFM3_ETHERNET_MAC1_MAR26H_AE *((volatile unsigned int*)(0x42CF0A7CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A0 *((volatile unsigned int*)(0x42CF0A80UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A1 *((volatile unsigned int*)(0x42CF0A84UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A2 *((volatile unsigned int*)(0x42CF0A88UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A3 *((volatile unsigned int*)(0x42CF0A8CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A4 *((volatile unsigned int*)(0x42CF0A90UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A5 *((volatile unsigned int*)(0x42CF0A94UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A6 *((volatile unsigned int*)(0x42CF0A98UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A7 *((volatile unsigned int*)(0x42CF0A9CUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A8 *((volatile unsigned int*)(0x42CF0AA0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A9 *((volatile unsigned int*)(0x42CF0AA4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A10 *((volatile unsigned int*)(0x42CF0AA8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A11 *((volatile unsigned int*)(0x42CF0AACUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A12 *((volatile unsigned int*)(0x42CF0AB0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A13 *((volatile unsigned int*)(0x42CF0AB4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A14 *((volatile unsigned int*)(0x42CF0AB8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A15 *((volatile unsigned int*)(0x42CF0ABCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A16 *((volatile unsigned int*)(0x42CF0AC0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A17 *((volatile unsigned int*)(0x42CF0AC4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A18 *((volatile unsigned int*)(0x42CF0AC8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A19 *((volatile unsigned int*)(0x42CF0ACCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A20 *((volatile unsigned int*)(0x42CF0AD0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A21 *((volatile unsigned int*)(0x42CF0AD4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A22 *((volatile unsigned int*)(0x42CF0AD8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A23 *((volatile unsigned int*)(0x42CF0ADCUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A24 *((volatile unsigned int*)(0x42CF0AE0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A25 *((volatile unsigned int*)(0x42CF0AE4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A26 *((volatile unsigned int*)(0x42CF0AE8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A27 *((volatile unsigned int*)(0x42CF0AECUL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A28 *((volatile unsigned int*)(0x42CF0AF0UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A29 *((volatile unsigned int*)(0x42CF0AF4UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A30 *((volatile unsigned int*)(0x42CF0AF8UL)) +#define bFM3_ETHERNET_MAC1_MAR26L_A31 *((volatile unsigned int*)(0x42CF0AFCUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A32 *((volatile unsigned int*)(0x42CF0B00UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A33 *((volatile unsigned int*)(0x42CF0B04UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A34 *((volatile unsigned int*)(0x42CF0B08UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A35 *((volatile unsigned int*)(0x42CF0B0CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A36 *((volatile unsigned int*)(0x42CF0B10UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A37 *((volatile unsigned int*)(0x42CF0B14UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A38 *((volatile unsigned int*)(0x42CF0B18UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A39 *((volatile unsigned int*)(0x42CF0B1CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A40 *((volatile unsigned int*)(0x42CF0B20UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A41 *((volatile unsigned int*)(0x42CF0B24UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A42 *((volatile unsigned int*)(0x42CF0B28UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A43 *((volatile unsigned int*)(0x42CF0B2CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A44 *((volatile unsigned int*)(0x42CF0B30UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A45 *((volatile unsigned int*)(0x42CF0B34UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A46 *((volatile unsigned int*)(0x42CF0B38UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_A47 *((volatile unsigned int*)(0x42CF0B3CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC0 *((volatile unsigned int*)(0x42CF0B60UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC1 *((volatile unsigned int*)(0x42CF0B64UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC2 *((volatile unsigned int*)(0x42CF0B68UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC3 *((volatile unsigned int*)(0x42CF0B6CUL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC4 *((volatile unsigned int*)(0x42CF0B70UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_MBC5 *((volatile unsigned int*)(0x42CF0B74UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_SA *((volatile unsigned int*)(0x42CF0B78UL)) +#define bFM3_ETHERNET_MAC1_MAR27H_AE *((volatile unsigned int*)(0x42CF0B7CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A0 *((volatile unsigned int*)(0x42CF0B80UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A1 *((volatile unsigned int*)(0x42CF0B84UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A2 *((volatile unsigned int*)(0x42CF0B88UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A3 *((volatile unsigned int*)(0x42CF0B8CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A4 *((volatile unsigned int*)(0x42CF0B90UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A5 *((volatile unsigned int*)(0x42CF0B94UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A6 *((volatile unsigned int*)(0x42CF0B98UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A7 *((volatile unsigned int*)(0x42CF0B9CUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A8 *((volatile unsigned int*)(0x42CF0BA0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A9 *((volatile unsigned int*)(0x42CF0BA4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A10 *((volatile unsigned int*)(0x42CF0BA8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A11 *((volatile unsigned int*)(0x42CF0BACUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A12 *((volatile unsigned int*)(0x42CF0BB0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A13 *((volatile unsigned int*)(0x42CF0BB4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A14 *((volatile unsigned int*)(0x42CF0BB8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A15 *((volatile unsigned int*)(0x42CF0BBCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A16 *((volatile unsigned int*)(0x42CF0BC0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A17 *((volatile unsigned int*)(0x42CF0BC4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A18 *((volatile unsigned int*)(0x42CF0BC8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A19 *((volatile unsigned int*)(0x42CF0BCCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A20 *((volatile unsigned int*)(0x42CF0BD0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A21 *((volatile unsigned int*)(0x42CF0BD4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A22 *((volatile unsigned int*)(0x42CF0BD8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A23 *((volatile unsigned int*)(0x42CF0BDCUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A24 *((volatile unsigned int*)(0x42CF0BE0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A25 *((volatile unsigned int*)(0x42CF0BE4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A26 *((volatile unsigned int*)(0x42CF0BE8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A27 *((volatile unsigned int*)(0x42CF0BECUL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A28 *((volatile unsigned int*)(0x42CF0BF0UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A29 *((volatile unsigned int*)(0x42CF0BF4UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A30 *((volatile unsigned int*)(0x42CF0BF8UL)) +#define bFM3_ETHERNET_MAC1_MAR27L_A31 *((volatile unsigned int*)(0x42CF0BFCUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A32 *((volatile unsigned int*)(0x42CF0C00UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A33 *((volatile unsigned int*)(0x42CF0C04UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A34 *((volatile unsigned int*)(0x42CF0C08UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A35 *((volatile unsigned int*)(0x42CF0C0CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A36 *((volatile unsigned int*)(0x42CF0C10UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A37 *((volatile unsigned int*)(0x42CF0C14UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A38 *((volatile unsigned int*)(0x42CF0C18UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A39 *((volatile unsigned int*)(0x42CF0C1CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A40 *((volatile unsigned int*)(0x42CF0C20UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A41 *((volatile unsigned int*)(0x42CF0C24UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A42 *((volatile unsigned int*)(0x42CF0C28UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A43 *((volatile unsigned int*)(0x42CF0C2CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A44 *((volatile unsigned int*)(0x42CF0C30UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A45 *((volatile unsigned int*)(0x42CF0C34UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A46 *((volatile unsigned int*)(0x42CF0C38UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_A47 *((volatile unsigned int*)(0x42CF0C3CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC0 *((volatile unsigned int*)(0x42CF0C60UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC1 *((volatile unsigned int*)(0x42CF0C64UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC2 *((volatile unsigned int*)(0x42CF0C68UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC3 *((volatile unsigned int*)(0x42CF0C6CUL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC4 *((volatile unsigned int*)(0x42CF0C70UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_MBC5 *((volatile unsigned int*)(0x42CF0C74UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_SA *((volatile unsigned int*)(0x42CF0C78UL)) +#define bFM3_ETHERNET_MAC1_MAR28H_AE *((volatile unsigned int*)(0x42CF0C7CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A0 *((volatile unsigned int*)(0x42CF0C80UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A1 *((volatile unsigned int*)(0x42CF0C84UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A2 *((volatile unsigned int*)(0x42CF0C88UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A3 *((volatile unsigned int*)(0x42CF0C8CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A4 *((volatile unsigned int*)(0x42CF0C90UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A5 *((volatile unsigned int*)(0x42CF0C94UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A6 *((volatile unsigned int*)(0x42CF0C98UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A7 *((volatile unsigned int*)(0x42CF0C9CUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A8 *((volatile unsigned int*)(0x42CF0CA0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A9 *((volatile unsigned int*)(0x42CF0CA4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A10 *((volatile unsigned int*)(0x42CF0CA8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A11 *((volatile unsigned int*)(0x42CF0CACUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A12 *((volatile unsigned int*)(0x42CF0CB0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A13 *((volatile unsigned int*)(0x42CF0CB4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A14 *((volatile unsigned int*)(0x42CF0CB8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A15 *((volatile unsigned int*)(0x42CF0CBCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A16 *((volatile unsigned int*)(0x42CF0CC0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A17 *((volatile unsigned int*)(0x42CF0CC4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A18 *((volatile unsigned int*)(0x42CF0CC8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A19 *((volatile unsigned int*)(0x42CF0CCCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A20 *((volatile unsigned int*)(0x42CF0CD0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A21 *((volatile unsigned int*)(0x42CF0CD4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A22 *((volatile unsigned int*)(0x42CF0CD8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A23 *((volatile unsigned int*)(0x42CF0CDCUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A24 *((volatile unsigned int*)(0x42CF0CE0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A25 *((volatile unsigned int*)(0x42CF0CE4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A26 *((volatile unsigned int*)(0x42CF0CE8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A27 *((volatile unsigned int*)(0x42CF0CECUL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A28 *((volatile unsigned int*)(0x42CF0CF0UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A29 *((volatile unsigned int*)(0x42CF0CF4UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A30 *((volatile unsigned int*)(0x42CF0CF8UL)) +#define bFM3_ETHERNET_MAC1_MAR28L_A31 *((volatile unsigned int*)(0x42CF0CFCUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A32 *((volatile unsigned int*)(0x42CF0D00UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A33 *((volatile unsigned int*)(0x42CF0D04UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A34 *((volatile unsigned int*)(0x42CF0D08UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A35 *((volatile unsigned int*)(0x42CF0D0CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A36 *((volatile unsigned int*)(0x42CF0D10UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A37 *((volatile unsigned int*)(0x42CF0D14UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A38 *((volatile unsigned int*)(0x42CF0D18UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A39 *((volatile unsigned int*)(0x42CF0D1CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A40 *((volatile unsigned int*)(0x42CF0D20UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A41 *((volatile unsigned int*)(0x42CF0D24UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A42 *((volatile unsigned int*)(0x42CF0D28UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A43 *((volatile unsigned int*)(0x42CF0D2CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A44 *((volatile unsigned int*)(0x42CF0D30UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A45 *((volatile unsigned int*)(0x42CF0D34UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A46 *((volatile unsigned int*)(0x42CF0D38UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_A47 *((volatile unsigned int*)(0x42CF0D3CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC0 *((volatile unsigned int*)(0x42CF0D60UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC1 *((volatile unsigned int*)(0x42CF0D64UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC2 *((volatile unsigned int*)(0x42CF0D68UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC3 *((volatile unsigned int*)(0x42CF0D6CUL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC4 *((volatile unsigned int*)(0x42CF0D70UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_MBC5 *((volatile unsigned int*)(0x42CF0D74UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_SA *((volatile unsigned int*)(0x42CF0D78UL)) +#define bFM3_ETHERNET_MAC1_MAR29H_AE *((volatile unsigned int*)(0x42CF0D7CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A0 *((volatile unsigned int*)(0x42CF0D80UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A1 *((volatile unsigned int*)(0x42CF0D84UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A2 *((volatile unsigned int*)(0x42CF0D88UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A3 *((volatile unsigned int*)(0x42CF0D8CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A4 *((volatile unsigned int*)(0x42CF0D90UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A5 *((volatile unsigned int*)(0x42CF0D94UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A6 *((volatile unsigned int*)(0x42CF0D98UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A7 *((volatile unsigned int*)(0x42CF0D9CUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A8 *((volatile unsigned int*)(0x42CF0DA0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A9 *((volatile unsigned int*)(0x42CF0DA4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A10 *((volatile unsigned int*)(0x42CF0DA8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A11 *((volatile unsigned int*)(0x42CF0DACUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A12 *((volatile unsigned int*)(0x42CF0DB0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A13 *((volatile unsigned int*)(0x42CF0DB4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A14 *((volatile unsigned int*)(0x42CF0DB8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A15 *((volatile unsigned int*)(0x42CF0DBCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A16 *((volatile unsigned int*)(0x42CF0DC0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A17 *((volatile unsigned int*)(0x42CF0DC4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A18 *((volatile unsigned int*)(0x42CF0DC8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A19 *((volatile unsigned int*)(0x42CF0DCCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A20 *((volatile unsigned int*)(0x42CF0DD0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A21 *((volatile unsigned int*)(0x42CF0DD4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A22 *((volatile unsigned int*)(0x42CF0DD8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A23 *((volatile unsigned int*)(0x42CF0DDCUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A24 *((volatile unsigned int*)(0x42CF0DE0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A25 *((volatile unsigned int*)(0x42CF0DE4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A26 *((volatile unsigned int*)(0x42CF0DE8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A27 *((volatile unsigned int*)(0x42CF0DECUL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A28 *((volatile unsigned int*)(0x42CF0DF0UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A29 *((volatile unsigned int*)(0x42CF0DF4UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A30 *((volatile unsigned int*)(0x42CF0DF8UL)) +#define bFM3_ETHERNET_MAC1_MAR29L_A31 *((volatile unsigned int*)(0x42CF0DFCUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A32 *((volatile unsigned int*)(0x42CF0E00UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A33 *((volatile unsigned int*)(0x42CF0E04UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A34 *((volatile unsigned int*)(0x42CF0E08UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A35 *((volatile unsigned int*)(0x42CF0E0CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A36 *((volatile unsigned int*)(0x42CF0E10UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A37 *((volatile unsigned int*)(0x42CF0E14UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A38 *((volatile unsigned int*)(0x42CF0E18UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A39 *((volatile unsigned int*)(0x42CF0E1CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A40 *((volatile unsigned int*)(0x42CF0E20UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A41 *((volatile unsigned int*)(0x42CF0E24UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A42 *((volatile unsigned int*)(0x42CF0E28UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A43 *((volatile unsigned int*)(0x42CF0E2CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A44 *((volatile unsigned int*)(0x42CF0E30UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A45 *((volatile unsigned int*)(0x42CF0E34UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A46 *((volatile unsigned int*)(0x42CF0E38UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_A47 *((volatile unsigned int*)(0x42CF0E3CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC0 *((volatile unsigned int*)(0x42CF0E60UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC1 *((volatile unsigned int*)(0x42CF0E64UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC2 *((volatile unsigned int*)(0x42CF0E68UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC3 *((volatile unsigned int*)(0x42CF0E6CUL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC4 *((volatile unsigned int*)(0x42CF0E70UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_MBC5 *((volatile unsigned int*)(0x42CF0E74UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_SA *((volatile unsigned int*)(0x42CF0E78UL)) +#define bFM3_ETHERNET_MAC1_MAR30H_AE *((volatile unsigned int*)(0x42CF0E7CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A0 *((volatile unsigned int*)(0x42CF0E80UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A1 *((volatile unsigned int*)(0x42CF0E84UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A2 *((volatile unsigned int*)(0x42CF0E88UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A3 *((volatile unsigned int*)(0x42CF0E8CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A4 *((volatile unsigned int*)(0x42CF0E90UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A5 *((volatile unsigned int*)(0x42CF0E94UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A6 *((volatile unsigned int*)(0x42CF0E98UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A7 *((volatile unsigned int*)(0x42CF0E9CUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A8 *((volatile unsigned int*)(0x42CF0EA0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A9 *((volatile unsigned int*)(0x42CF0EA4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A10 *((volatile unsigned int*)(0x42CF0EA8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A11 *((volatile unsigned int*)(0x42CF0EACUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A12 *((volatile unsigned int*)(0x42CF0EB0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A13 *((volatile unsigned int*)(0x42CF0EB4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A14 *((volatile unsigned int*)(0x42CF0EB8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A15 *((volatile unsigned int*)(0x42CF0EBCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A16 *((volatile unsigned int*)(0x42CF0EC0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A17 *((volatile unsigned int*)(0x42CF0EC4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A18 *((volatile unsigned int*)(0x42CF0EC8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A19 *((volatile unsigned int*)(0x42CF0ECCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A20 *((volatile unsigned int*)(0x42CF0ED0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A21 *((volatile unsigned int*)(0x42CF0ED4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A22 *((volatile unsigned int*)(0x42CF0ED8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A23 *((volatile unsigned int*)(0x42CF0EDCUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A24 *((volatile unsigned int*)(0x42CF0EE0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A25 *((volatile unsigned int*)(0x42CF0EE4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A26 *((volatile unsigned int*)(0x42CF0EE8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A27 *((volatile unsigned int*)(0x42CF0EECUL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A28 *((volatile unsigned int*)(0x42CF0EF0UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A29 *((volatile unsigned int*)(0x42CF0EF4UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A30 *((volatile unsigned int*)(0x42CF0EF8UL)) +#define bFM3_ETHERNET_MAC1_MAR30L_A31 *((volatile unsigned int*)(0x42CF0EFCUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A32 *((volatile unsigned int*)(0x42CF0F00UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A33 *((volatile unsigned int*)(0x42CF0F04UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A34 *((volatile unsigned int*)(0x42CF0F08UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A35 *((volatile unsigned int*)(0x42CF0F0CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A36 *((volatile unsigned int*)(0x42CF0F10UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A37 *((volatile unsigned int*)(0x42CF0F14UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A38 *((volatile unsigned int*)(0x42CF0F18UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A39 *((volatile unsigned int*)(0x42CF0F1CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A40 *((volatile unsigned int*)(0x42CF0F20UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A41 *((volatile unsigned int*)(0x42CF0F24UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A42 *((volatile unsigned int*)(0x42CF0F28UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A43 *((volatile unsigned int*)(0x42CF0F2CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A44 *((volatile unsigned int*)(0x42CF0F30UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A45 *((volatile unsigned int*)(0x42CF0F34UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A46 *((volatile unsigned int*)(0x42CF0F38UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_A47 *((volatile unsigned int*)(0x42CF0F3CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC0 *((volatile unsigned int*)(0x42CF0F60UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC1 *((volatile unsigned int*)(0x42CF0F64UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC2 *((volatile unsigned int*)(0x42CF0F68UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC3 *((volatile unsigned int*)(0x42CF0F6CUL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC4 *((volatile unsigned int*)(0x42CF0F70UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_MBC5 *((volatile unsigned int*)(0x42CF0F74UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_SA *((volatile unsigned int*)(0x42CF0F78UL)) +#define bFM3_ETHERNET_MAC1_MAR31H_AE *((volatile unsigned int*)(0x42CF0F7CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A0 *((volatile unsigned int*)(0x42CF0F80UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A1 *((volatile unsigned int*)(0x42CF0F84UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A2 *((volatile unsigned int*)(0x42CF0F88UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A3 *((volatile unsigned int*)(0x42CF0F8CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A4 *((volatile unsigned int*)(0x42CF0F90UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A5 *((volatile unsigned int*)(0x42CF0F94UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A6 *((volatile unsigned int*)(0x42CF0F98UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A7 *((volatile unsigned int*)(0x42CF0F9CUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A8 *((volatile unsigned int*)(0x42CF0FA0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A9 *((volatile unsigned int*)(0x42CF0FA4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A10 *((volatile unsigned int*)(0x42CF0FA8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A11 *((volatile unsigned int*)(0x42CF0FACUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A12 *((volatile unsigned int*)(0x42CF0FB0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A13 *((volatile unsigned int*)(0x42CF0FB4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A14 *((volatile unsigned int*)(0x42CF0FB8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A15 *((volatile unsigned int*)(0x42CF0FBCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A16 *((volatile unsigned int*)(0x42CF0FC0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A17 *((volatile unsigned int*)(0x42CF0FC4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A18 *((volatile unsigned int*)(0x42CF0FC8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A19 *((volatile unsigned int*)(0x42CF0FCCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A20 *((volatile unsigned int*)(0x42CF0FD0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A21 *((volatile unsigned int*)(0x42CF0FD4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A22 *((volatile unsigned int*)(0x42CF0FD8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A23 *((volatile unsigned int*)(0x42CF0FDCUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A24 *((volatile unsigned int*)(0x42CF0FE0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A25 *((volatile unsigned int*)(0x42CF0FE4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A26 *((volatile unsigned int*)(0x42CF0FE8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A27 *((volatile unsigned int*)(0x42CF0FECUL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A28 *((volatile unsigned int*)(0x42CF0FF0UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A29 *((volatile unsigned int*)(0x42CF0FF4UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A30 *((volatile unsigned int*)(0x42CF0FF8UL)) +#define bFM3_ETHERNET_MAC1_MAR31L_A31 *((volatile unsigned int*)(0x42CF0FFCUL)) +#define bFM3_ETHERNET_MAC1_BMR_SWR *((volatile unsigned int*)(0x42D00000UL)) +#define bFM3_ETHERNET_MAC1_BMR_DA *((volatile unsigned int*)(0x42D00004UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL0 *((volatile unsigned int*)(0x42D00008UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL1 *((volatile unsigned int*)(0x42D0000CUL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL2 *((volatile unsigned int*)(0x42D00010UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL3 *((volatile unsigned int*)(0x42D00014UL)) +#define bFM3_ETHERNET_MAC1_BMR_DSL4 *((volatile unsigned int*)(0x42D00018UL)) +#define bFM3_ETHERNET_MAC1_BMR_ATDS *((volatile unsigned int*)(0x42D0001CUL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL0 *((volatile unsigned int*)(0x42D00020UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL1 *((volatile unsigned int*)(0x42D00024UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL2 *((volatile unsigned int*)(0x42D00028UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL3 *((volatile unsigned int*)(0x42D0002CUL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL4 *((volatile unsigned int*)(0x42D00030UL)) +#define bFM3_ETHERNET_MAC1_BMR_PBL5 *((volatile unsigned int*)(0x42D00034UL)) +#define bFM3_ETHERNET_MAC1_BMR_PR0 *((volatile unsigned int*)(0x42D00038UL)) +#define bFM3_ETHERNET_MAC1_BMR_PR1 *((volatile unsigned int*)(0x42D0003CUL)) +#define bFM3_ETHERNET_MAC1_BMR_FB *((volatile unsigned int*)(0x42D00040UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL0 *((volatile unsigned int*)(0x42D00044UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL1 *((volatile unsigned int*)(0x42D00048UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL2 *((volatile unsigned int*)(0x42D0004CUL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL3 *((volatile unsigned int*)(0x42D00050UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL4 *((volatile unsigned int*)(0x42D00054UL)) +#define bFM3_ETHERNET_MAC1_BMR_RPBL5 *((volatile unsigned int*)(0x42D00058UL)) +#define bFM3_ETHERNET_MAC1_BMR_USP *((volatile unsigned int*)(0x42D0005CUL)) +#define bFM3_ETHERNET_MAC1_BMR_8XPBL *((volatile unsigned int*)(0x42D00060UL)) +#define bFM3_ETHERNET_MAC1_BMR_AAL *((volatile unsigned int*)(0x42D00064UL)) +#define bFM3_ETHERNET_MAC1_BMR_MB *((volatile unsigned int*)(0x42D00068UL)) +#define bFM3_ETHERNET_MAC1_BMR_TXPR *((volatile unsigned int*)(0x42D0006CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD0 *((volatile unsigned int*)(0x42D00080UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD1 *((volatile unsigned int*)(0x42D00084UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD2 *((volatile unsigned int*)(0x42D00088UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD3 *((volatile unsigned int*)(0x42D0008CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD4 *((volatile unsigned int*)(0x42D00090UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD5 *((volatile unsigned int*)(0x42D00094UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD6 *((volatile unsigned int*)(0x42D00098UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD7 *((volatile unsigned int*)(0x42D0009CUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD8 *((volatile unsigned int*)(0x42D000A0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD9 *((volatile unsigned int*)(0x42D000A4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD10 *((volatile unsigned int*)(0x42D000A8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD11 *((volatile unsigned int*)(0x42D000ACUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD12 *((volatile unsigned int*)(0x42D000B0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD13 *((volatile unsigned int*)(0x42D000B4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD14 *((volatile unsigned int*)(0x42D000B8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD15 *((volatile unsigned int*)(0x42D000BCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD16 *((volatile unsigned int*)(0x42D000C0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD17 *((volatile unsigned int*)(0x42D000C4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD18 *((volatile unsigned int*)(0x42D000C8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD19 *((volatile unsigned int*)(0x42D000CCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD20 *((volatile unsigned int*)(0x42D000D0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD21 *((volatile unsigned int*)(0x42D000D4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD22 *((volatile unsigned int*)(0x42D000D8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD23 *((volatile unsigned int*)(0x42D000DCUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD24 *((volatile unsigned int*)(0x42D000E0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD25 *((volatile unsigned int*)(0x42D000E4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD26 *((volatile unsigned int*)(0x42D000E8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD27 *((volatile unsigned int*)(0x42D000ECUL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD28 *((volatile unsigned int*)(0x42D000F0UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD29 *((volatile unsigned int*)(0x42D000F4UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD30 *((volatile unsigned int*)(0x42D000F8UL)) +#define bFM3_ETHERNET_MAC1_TPDR_TPD31 *((volatile unsigned int*)(0x42D000FCUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD0 *((volatile unsigned int*)(0x42D00100UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD1 *((volatile unsigned int*)(0x42D00104UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD2 *((volatile unsigned int*)(0x42D00108UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD3 *((volatile unsigned int*)(0x42D0010CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD4 *((volatile unsigned int*)(0x42D00110UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD5 *((volatile unsigned int*)(0x42D00114UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD6 *((volatile unsigned int*)(0x42D00118UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD7 *((volatile unsigned int*)(0x42D0011CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD8 *((volatile unsigned int*)(0x42D00120UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD9 *((volatile unsigned int*)(0x42D00124UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD10 *((volatile unsigned int*)(0x42D00128UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD11 *((volatile unsigned int*)(0x42D0012CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD12 *((volatile unsigned int*)(0x42D00130UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD13 *((volatile unsigned int*)(0x42D00134UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD14 *((volatile unsigned int*)(0x42D00138UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD15 *((volatile unsigned int*)(0x42D0013CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD16 *((volatile unsigned int*)(0x42D00140UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD17 *((volatile unsigned int*)(0x42D00144UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD18 *((volatile unsigned int*)(0x42D00148UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD19 *((volatile unsigned int*)(0x42D0014CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD20 *((volatile unsigned int*)(0x42D00150UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD21 *((volatile unsigned int*)(0x42D00154UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD22 *((volatile unsigned int*)(0x42D00158UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD23 *((volatile unsigned int*)(0x42D0015CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD24 *((volatile unsigned int*)(0x42D00160UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD25 *((volatile unsigned int*)(0x42D00164UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD26 *((volatile unsigned int*)(0x42D00168UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD27 *((volatile unsigned int*)(0x42D0016CUL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD28 *((volatile unsigned int*)(0x42D00170UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD29 *((volatile unsigned int*)(0x42D00174UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD30 *((volatile unsigned int*)(0x42D00178UL)) +#define bFM3_ETHERNET_MAC1_RPDR_RPD31 *((volatile unsigned int*)(0x42D0017CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL2 *((volatile unsigned int*)(0x42D00188UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL3 *((volatile unsigned int*)(0x42D0018CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL4 *((volatile unsigned int*)(0x42D00190UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL5 *((volatile unsigned int*)(0x42D00194UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL6 *((volatile unsigned int*)(0x42D00198UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL7 *((volatile unsigned int*)(0x42D0019CUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL8 *((volatile unsigned int*)(0x42D001A0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL9 *((volatile unsigned int*)(0x42D001A4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL10 *((volatile unsigned int*)(0x42D001A8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL11 *((volatile unsigned int*)(0x42D001ACUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL12 *((volatile unsigned int*)(0x42D001B0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL13 *((volatile unsigned int*)(0x42D001B4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL14 *((volatile unsigned int*)(0x42D001B8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL15 *((volatile unsigned int*)(0x42D001BCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL16 *((volatile unsigned int*)(0x42D001C0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL17 *((volatile unsigned int*)(0x42D001C4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL18 *((volatile unsigned int*)(0x42D001C8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL19 *((volatile unsigned int*)(0x42D001CCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL20 *((volatile unsigned int*)(0x42D001D0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL21 *((volatile unsigned int*)(0x42D001D4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL22 *((volatile unsigned int*)(0x42D001D8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL23 *((volatile unsigned int*)(0x42D001DCUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL24 *((volatile unsigned int*)(0x42D001E0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL25 *((volatile unsigned int*)(0x42D001E4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL26 *((volatile unsigned int*)(0x42D001E8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL27 *((volatile unsigned int*)(0x42D001ECUL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL28 *((volatile unsigned int*)(0x42D001F0UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL29 *((volatile unsigned int*)(0x42D001F4UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL30 *((volatile unsigned int*)(0x42D001F8UL)) +#define bFM3_ETHERNET_MAC1_RDLAR_SRL31 *((volatile unsigned int*)(0x42D001FCUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL2 *((volatile unsigned int*)(0x42D00208UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL3 *((volatile unsigned int*)(0x42D0020CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL4 *((volatile unsigned int*)(0x42D00210UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL5 *((volatile unsigned int*)(0x42D00214UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL6 *((volatile unsigned int*)(0x42D00218UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL7 *((volatile unsigned int*)(0x42D0021CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL8 *((volatile unsigned int*)(0x42D00220UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL9 *((volatile unsigned int*)(0x42D00224UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL10 *((volatile unsigned int*)(0x42D00228UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL11 *((volatile unsigned int*)(0x42D0022CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL12 *((volatile unsigned int*)(0x42D00230UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL13 *((volatile unsigned int*)(0x42D00234UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL14 *((volatile unsigned int*)(0x42D00238UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL15 *((volatile unsigned int*)(0x42D0023CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL16 *((volatile unsigned int*)(0x42D00240UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL17 *((volatile unsigned int*)(0x42D00244UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL18 *((volatile unsigned int*)(0x42D00248UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL19 *((volatile unsigned int*)(0x42D0024CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL20 *((volatile unsigned int*)(0x42D00250UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL21 *((volatile unsigned int*)(0x42D00254UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL22 *((volatile unsigned int*)(0x42D00258UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL23 *((volatile unsigned int*)(0x42D0025CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL24 *((volatile unsigned int*)(0x42D00260UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL25 *((volatile unsigned int*)(0x42D00264UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL26 *((volatile unsigned int*)(0x42D00268UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL27 *((volatile unsigned int*)(0x42D0026CUL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL28 *((volatile unsigned int*)(0x42D00270UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL29 *((volatile unsigned int*)(0x42D00274UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL30 *((volatile unsigned int*)(0x42D00278UL)) +#define bFM3_ETHERNET_MAC1_TDLAR_STL31 *((volatile unsigned int*)(0x42D0027CUL)) +#define bFM3_ETHERNET_MAC1_SR_TI *((volatile unsigned int*)(0x42D00280UL)) +#define bFM3_ETHERNET_MAC1_SR_TPS *((volatile unsigned int*)(0x42D00284UL)) +#define bFM3_ETHERNET_MAC1_SR_TU *((volatile unsigned int*)(0x42D00288UL)) +#define bFM3_ETHERNET_MAC1_SR_TJT *((volatile unsigned int*)(0x42D0028CUL)) +#define bFM3_ETHERNET_MAC1_SR_OVF *((volatile unsigned int*)(0x42D00290UL)) +#define bFM3_ETHERNET_MAC1_SR_UNF *((volatile unsigned int*)(0x42D00294UL)) +#define bFM3_ETHERNET_MAC1_SR_RI *((volatile unsigned int*)(0x42D00298UL)) +#define bFM3_ETHERNET_MAC1_SR_RU *((volatile unsigned int*)(0x42D0029CUL)) +#define bFM3_ETHERNET_MAC1_SR_RPS *((volatile unsigned int*)(0x42D002A0UL)) +#define bFM3_ETHERNET_MAC1_SR_RWT *((volatile unsigned int*)(0x42D002A4UL)) +#define bFM3_ETHERNET_MAC1_SR_ETI *((volatile unsigned int*)(0x42D002A8UL)) +#define bFM3_ETHERNET_MAC1_SR_FBI *((volatile unsigned int*)(0x42D002B4UL)) +#define bFM3_ETHERNET_MAC1_SR_ERI *((volatile unsigned int*)(0x42D002B8UL)) +#define bFM3_ETHERNET_MAC1_SR_AIS *((volatile unsigned int*)(0x42D002BCUL)) +#define bFM3_ETHERNET_MAC1_SR_NIS *((volatile unsigned int*)(0x42D002C0UL)) +#define bFM3_ETHERNET_MAC1_SR_RS0 *((volatile unsigned int*)(0x42D002C4UL)) +#define bFM3_ETHERNET_MAC1_SR_RS1 *((volatile unsigned int*)(0x42D002C8UL)) +#define bFM3_ETHERNET_MAC1_SR_RS2 *((volatile unsigned int*)(0x42D002CCUL)) +#define bFM3_ETHERNET_MAC1_SR_TS0 *((volatile unsigned int*)(0x42D002D0UL)) +#define bFM3_ETHERNET_MAC1_SR_TS1 *((volatile unsigned int*)(0x42D002D4UL)) +#define bFM3_ETHERNET_MAC1_SR_TS2 *((volatile unsigned int*)(0x42D002D8UL)) +#define bFM3_ETHERNET_MAC1_SR_EB0 *((volatile unsigned int*)(0x42D002DCUL)) +#define bFM3_ETHERNET_MAC1_SR_EB1 *((volatile unsigned int*)(0x42D002E0UL)) +#define bFM3_ETHERNET_MAC1_SR_EB2 *((volatile unsigned int*)(0x42D002E4UL)) +#define bFM3_ETHERNET_MAC1_SR_GLI *((volatile unsigned int*)(0x42D002E8UL)) +#define bFM3_ETHERNET_MAC1_SR_GMI *((volatile unsigned int*)(0x42D002ECUL)) +#define bFM3_ETHERNET_MAC1_SR_GPI *((volatile unsigned int*)(0x42D002F0UL)) +#define bFM3_ETHERNET_MAC1_SR_TTI *((volatile unsigned int*)(0x42D002F4UL)) +#define bFM3_ETHERNET_MAC1_SR_GLPII *((volatile unsigned int*)(0x42D002F8UL)) +#define bFM3_ETHERNET_MAC1_OMR_SR *((volatile unsigned int*)(0x42D00304UL)) +#define bFM3_ETHERNET_MAC1_OMR_OSF *((volatile unsigned int*)(0x42D00308UL)) +#define bFM3_ETHERNET_MAC1_OMR_RTC0 *((volatile unsigned int*)(0x42D0030CUL)) +#define bFM3_ETHERNET_MAC1_OMR_RTC1 *((volatile unsigned int*)(0x42D00310UL)) +#define bFM3_ETHERNET_MAC1_OMR_FUF *((volatile unsigned int*)(0x42D00318UL)) +#define bFM3_ETHERNET_MAC1_OMR_FEF *((volatile unsigned int*)(0x42D0031CUL)) +#define bFM3_ETHERNET_MAC1_OMR_ST *((volatile unsigned int*)(0x42D00334UL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC0 *((volatile unsigned int*)(0x42D00338UL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC1 *((volatile unsigned int*)(0x42D0033CUL)) +#define bFM3_ETHERNET_MAC1_OMR_TTC2 *((volatile unsigned int*)(0x42D00340UL)) +#define bFM3_ETHERNET_MAC1_OMR_FTF *((volatile unsigned int*)(0x42D00350UL)) +#define bFM3_ETHERNET_MAC1_OMR_TSF *((volatile unsigned int*)(0x42D00354UL)) +#define bFM3_ETHERNET_MAC1_OMR_DFF *((volatile unsigned int*)(0x42D00360UL)) +#define bFM3_ETHERNET_MAC1_OMR_RSF *((volatile unsigned int*)(0x42D00364UL)) +#define bFM3_ETHERNET_MAC1_OMR_DT *((volatile unsigned int*)(0x42D00368UL)) +#define bFM3_ETHERNET_MAC1_IER_TIE *((volatile unsigned int*)(0x42D00380UL)) +#define bFM3_ETHERNET_MAC1_IER_TSE *((volatile unsigned int*)(0x42D00384UL)) +#define bFM3_ETHERNET_MAC1_IER_TUE *((volatile unsigned int*)(0x42D00388UL)) +#define bFM3_ETHERNET_MAC1_IER_TJE *((volatile unsigned int*)(0x42D0038CUL)) +#define bFM3_ETHERNET_MAC1_IER_OVE *((volatile unsigned int*)(0x42D00390UL)) +#define bFM3_ETHERNET_MAC1_IER_UNE *((volatile unsigned int*)(0x42D00394UL)) +#define bFM3_ETHERNET_MAC1_IER_RIE *((volatile unsigned int*)(0x42D00398UL)) +#define bFM3_ETHERNET_MAC1_IER_RUE *((volatile unsigned int*)(0x42D0039CUL)) +#define bFM3_ETHERNET_MAC1_IER_RSE *((volatile unsigned int*)(0x42D003A0UL)) +#define bFM3_ETHERNET_MAC1_IER_RWE *((volatile unsigned int*)(0x42D003A4UL)) +#define bFM3_ETHERNET_MAC1_IER_ETE *((volatile unsigned int*)(0x42D003A8UL)) +#define bFM3_ETHERNET_MAC1_IER_FBE *((volatile unsigned int*)(0x42D003B4UL)) +#define bFM3_ETHERNET_MAC1_IER_ERE *((volatile unsigned int*)(0x42D003B8UL)) +#define bFM3_ETHERNET_MAC1_IER_AIE *((volatile unsigned int*)(0x42D003BCUL)) +#define bFM3_ETHERNET_MAC1_IER_NIE *((volatile unsigned int*)(0x42D003C0UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42D00400UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42D00404UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42D00408UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42D0040CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42D00410UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42D00414UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42D00418UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42D0041CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42D00420UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42D00424UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42D00428UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42D0042CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42D00430UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42D00434UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42D00438UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42D0043CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH *((volatile unsigned int*)(0x42D00440UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42D00444UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42D00448UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42D0044CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42D00450UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42D00454UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42D00458UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42D0045CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42D00460UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42D00464UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42D00468UL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42D0046CUL)) +#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF *((volatile unsigned int*)(0x42D00470UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0 *((volatile unsigned int*)(0x42D00480UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1 *((volatile unsigned int*)(0x42D00484UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2 *((volatile unsigned int*)(0x42D00488UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3 *((volatile unsigned int*)(0x42D0048CUL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4 *((volatile unsigned int*)(0x42D00490UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5 *((volatile unsigned int*)(0x42D00494UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6 *((volatile unsigned int*)(0x42D00498UL)) +#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7 *((volatile unsigned int*)(0x42D0049CUL)) +#define bFM3_ETHERNET_MAC1_AHBSR_AHBS *((volatile unsigned int*)(0x42D00580UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42D00900UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42D00904UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42D00908UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42D0090CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42D00910UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42D00914UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42D00918UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42D0091CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42D00920UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42D00924UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42D00928UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42D0092CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42D00930UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42D00934UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42D00938UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42D0093CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42D00940UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42D00944UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42D00948UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42D0094CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42D00950UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42D00954UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42D00958UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42D0095CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42D00960UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42D00964UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42D00968UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42D0096CUL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42D00970UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42D00974UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42D00978UL)) +#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42D0097CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42D00980UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42D00984UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42D00988UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42D0098CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42D00990UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42D00994UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42D00998UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42D0099CUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42D009A0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42D009A4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42D009A8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42D009ACUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42D009B0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42D009B4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42D009B8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42D009BCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42D009C0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42D009C4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42D009C8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42D009CCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42D009D0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42D009D4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42D009D8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42D009DCUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42D009E0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42D009E4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42D009E8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42D009ECUL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42D009F0UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42D009F4UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42D009F8UL)) +#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42D009FCUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42D00A00UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42D00A04UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42D00A08UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42D00A0CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42D00A10UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42D00A14UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42D00A18UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42D00A1CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42D00A20UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42D00A24UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42D00A28UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42D00A2CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42D00A30UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42D00A34UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42D00A38UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42D00A3CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42D00A40UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42D00A44UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42D00A48UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42D00A4CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42D00A50UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42D00A54UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42D00A58UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42D00A5CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42D00A60UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42D00A64UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42D00A68UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42D00A6CUL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42D00A70UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42D00A74UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42D00A78UL)) +#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42D00A7CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42D00A80UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42D00A84UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42D00A88UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42D00A8CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42D00A90UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42D00A94UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42D00A98UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42D00A9CUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42D00AA0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42D00AA4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42D00AA8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42D00AACUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42D00AB0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42D00AB4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42D00AB8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42D00ABCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42D00AC0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42D00AC4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42D00AC8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42D00ACCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42D00AD0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42D00AD4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42D00AD8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42D00ADCUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42D00AE0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42D00AE4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42D00AE8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42D00AECUL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42D00AF0UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42D00AF4UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42D00AF8UL)) +#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42D00AFCUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9B610T_H_ */ + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S new file mode 100644 index 0000000000..85d59276e2 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S @@ -0,0 +1,333 @@ +;/************************************************************************/ +;/* (C) Fujitsu Semiconductor Europe GmbH */ +;/* */ +;/* The following software deliverable is intended for and must only be */ +;/* used for reference and in an evaluation laboratory environment. */ +;/* It is provided on an as-is basis without charge and is subject to */ +;/* alterations. */ +;/* It is the user’s obligation to fully test the software in its */ +;/* environment and to ensure proper functionality, qualification and */ +;/* compliance with component specifications. */ +;/* */ +;/* In the event the software deliverable includes the use of open */ +;/* source components, the provisions of the governing open source */ +;/* license agreement shall apply with respect to such software */ +;/* deliverable. */ +;/* FSEU does not warrant that the deliverables do not infringe any */ +;/* third party intellectual property right (IPR). In the event that */ +;/* the deliverables infringe a third party IPR it is the sole */ +;/* responsibility of the customer to obtain necessary licenses to */ +;/* continue the usage of the deliverable. */ +;/* */ +;/* To the maximum extent permitted by applicable law FSEU disclaims all */ +;/* warranties, whether express or implied, in particular, but not */ +;/* limited to, warranties of merchantability and fitness for a */ +;/* particular purpose for which the deliverable is not designated. */ +;/* */ +;/* To the maximum extent permitted by applicable law, FSEU's liability */ +;/* is restricted to intention and gross negligence. */ +;/* FSEU is not liable for consequential damages. */ +;/* */ +;/* (V1.4) */ +;/************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.02 */ +;/* Date 2011-07-25 */ +;/* Target-mcu MB9B61x */ +;/************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0 + DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1 + DCD USB0F_Handler ; 34: USB0 Function + DCD USB0_Handler ; 35: USB0 Function / USB0 HOST + DCD USB1F_Handler ; 36: USB1 Function + DCD USB1_Handler ; 37: USB1 Function / USB1 HOST + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15 + DCD DummyHandler ; 47: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT LVD_Handler [WEAK] + EXPORT MFT_WG_IRQHandler [WEAK] + EXPORT INT0_7_Handler [WEAK] + EXPORT INT8_31_Handler [WEAK] + EXPORT DT_Handler [WEAK] + EXPORT MFS0RX_IRQHandler [WEAK] + EXPORT MFS0TX_IRQHandler [WEAK] + EXPORT MFS1RX_IRQHandler [WEAK] + EXPORT MFS1TX_IRQHandler [WEAK] + EXPORT MFS2RX_IRQHandler [WEAK] + EXPORT MFS2TX_IRQHandler [WEAK] + EXPORT MFS3RX_IRQHandler [WEAK] + EXPORT MFS3TX_IRQHandler [WEAK] + EXPORT MFS4RX_IRQHandler [WEAK] + EXPORT MFS4TX_IRQHandler [WEAK] + EXPORT MFS5RX_IRQHandler [WEAK] + EXPORT MFS5TX_IRQHandler [WEAK] + EXPORT MFS6RX_IRQHandler [WEAK] + EXPORT MFS6TX_IRQHandler [WEAK] + EXPORT MFS7RX_IRQHandler [WEAK] + EXPORT MFS7TX_IRQHandler [WEAK] + EXPORT PPG_Handler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT MFT_FRT_IRQHandler [WEAK] + EXPORT MFT_IPC_IRQHandler [WEAK] + EXPORT MFT_OPC_IRQHandler [WEAK] + EXPORT BT0_7_IRQHandler [WEAK] + EXPORT ETHER_MAC0_IRQHandler [WEAK] + EXPORT ETHER_MAC1_IRQHandler [WEAK] + EXPORT USB0F_Handler [WEAK] + EXPORT USB0_Handler [WEAK] + EXPORT USB1F_Handler [WEAK] + EXPORT USB1_Handler [WEAK] + EXPORT DMAC0_Handler [WEAK] + EXPORT DMAC1_Handler [WEAK] + EXPORT DMAC2_Handler [WEAK] + EXPORT DMAC3_Handler [WEAK] + EXPORT DMAC4_Handler [WEAK] + EXPORT DMAC5_Handler [WEAK] + EXPORT DMAC6_Handler [WEAK] + EXPORT DMAC7_Handler [WEAK] + EXPORT BT8_15_IRQHandler [WEAK] + EXPORT DummyHandler [WEAK] + +CSV_Handler +SWDT_Handler +LVD_Handler +MFT_WG_IRQHandler +INT0_7_Handler +INT8_31_Handler +DT_Handler +MFS0RX_IRQHandler +MFS0TX_IRQHandler +MFS1RX_IRQHandler +MFS1TX_IRQHandler +MFS2RX_IRQHandler +MFS2TX_IRQHandler +MFS3RX_IRQHandler +MFS3TX_IRQHandler +MFS4RX_IRQHandler +MFS4TX_IRQHandler +MFS5RX_IRQHandler +MFS5TX_IRQHandler +MFS6RX_IRQHandler +MFS6TX_IRQHandler +MFS7RX_IRQHandler +MFS7TX_IRQHandler +PPG_Handler +TIM_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +MFT_FRT_IRQHandler +MFT_IPC_IRQHandler +MFT_OPC_IRQHandler +BT0_7_IRQHandler +DMAC0_Handler +DMAC1_Handler +DMAC2_Handler +DMAC3_Handler +DMAC4_Handler +DMAC5_Handler +DMAC6_Handler +DMAC7_Handler +ETHER_MAC0_IRQHandler +ETHER_MAC1_IRQHandler +USB0F_Handler +USB0_Handler +USB1F_Handler +USB1_Handler +BT8_15_IRQHandler +DummyHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c new file mode 100644 index 0000000000..ef641de1ef --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c @@ -0,0 +1,244 @@ +/* + **************************************************************************** +** +** File : startup_mb9bf61x.c +** +** Abstract : This file contains interrupt vector and startup code. +** +** Functions : Reset_Handler +** +** Target : Fujitsu FM3 microcontrollers +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** + **************************************************************************** +*/ + +/** +**=========================================================================== +** Revisions +**=========================================================================== +** Date Modification +** 2011-08-18 First issue. +**=========================================================================== +*/ + +/** +**=========================================================================== +** External declarations +**=========================================================================== +*/ +extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector; +extern unsigned long _estack; +extern void __libc_init_array(); +extern void SystemInit(); +extern void main(); + +/** +**=========================================================================== +** Default interrupt handler +**=========================================================================== +*/ +void Default_Handler() +{ + /* Hang here */ + while(1) + { + } +} + +/** +**=========================================================================== +** Reset handler +**=========================================================================== +*/ +__attribute__((naked)) void Reset_Handler() +{ + /* Data and BSS variables */ + unsigned long *srcdata, *dstdata, *sbss; + + /* Set up the stack pointer */ + asm("ldr sp,=_estack\n\t"); + + /* Set up vector table offset register */ + dstdata = (unsigned long *)0xe000ed08; + *dstdata = (unsigned long)&_isr_vector; + + srcdata = &_sidata; + dstdata = &_sdata; + sbss = &_sbss; + + /* Copy data */ + while(dstdata != &_edata) + { + *(dstdata++) = *(srcdata++); + } + + /* Clear BSS */ + while(sbss != &_ebss) + { + *(sbss++) = '\0'; + } + + /* Run static constructors */ + //__libc_init_array(); + + /* Call the clock system initialization function.*/ + SystemInit(); + + /* Jump to main */ + main(); + + /* In case main returns, use default handler */ + Default_Handler(); +} + +/** +**=========================================================================== +** Weak definitions of handlers point to Default_Handler if not implemented +**=========================================================================== +*/ +void NMI_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler"))); + +void CSV_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void LVD_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DT_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void PPG_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); +void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void USB0_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void USB1_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler"))); +void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); + + +/** +**=========================================================================== +** Interrupt Vector Table +**=========================================================================== +*/ +void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = { + /* Processor exceptions */ + (void (*)(void))&_estack, /* 0 - Stack pointer */ + Reset_Handler, /* 1 - Reset */ + NMI_Handler, /* 2 - NMI */ + HardFault_Handler, /* 3 - Hard fault */ + MemManage_Handler, /* 4 - Memory management fault */ + BusFault_Handler, /* 5 - Bus fault */ + UsageFault_Handler, /* 6 - Usage fault */ + 0, /* 7 - Reserved */ + 0, /* 8 - Reserved */ + 0, /* 9 - Reserved */ + 0, /* 10 - Reserved */ + SVC_Handler, /* 11 - SVCall */ + DebugMonitor_Handler, /* 12 - Reserved for Debug */ + 0, /* 13 - Reserved */ + PendSV_Handler, /* 14 - PendSV */ + SysTick_Handler, /* 15 - Systick */ + + /* External Interrupts */ + CSV_Handler, /* 0: Clock Super Visor */ + SWDT_Handler, /* 1: Software Watchdog Timer */ + LVD_Handler, /* 2: Low Voltage Detector */ + MFT_WG_IRQHandler, /* 3: Wave Form Generator / DTIF */ + INT0_7_Handler, /* 4: External Interrupt Request ch.0 to ch.7 */ + INT8_31_Handler, /* 5: External Interrupt Request ch.8 to ch.31 */ + DT_Handler, /* 6: Dual Timer / Quad Decoder */ + MFS0RX_IRQHandler, /* 7: MultiFunction Serial ch.0 */ + MFS0TX_IRQHandler, /* 8: MultiFunction Serial ch.0 */ + MFS1RX_IRQHandler, /* 9: MultiFunction Serial ch.1 */ + MFS1TX_IRQHandler, /* 10: MultiFunction Serial ch.1 */ + MFS2RX_IRQHandler, /* 11: MultiFunction Serial ch.2 */ + MFS2TX_IRQHandler, /* 12: MultiFunction Serial ch.2 */ + MFS3RX_IRQHandler, /* 13: MultiFunction Serial ch.3 */ + MFS3TX_IRQHandler, /* 14: MultiFunction Serial ch.3 */ + MFS4RX_IRQHandler, /* 15: MultiFunction Serial ch.4 */ + MFS4TX_IRQHandler, /* 16: MultiFunction Serial ch.4 */ + MFS5RX_IRQHandler, /* 17: MultiFunction Serial ch.5 */ + MFS5TX_IRQHandler, /* 18: MultiFunction Serial ch.5 */ + MFS6RX_IRQHandler, /* 19: MultiFunction Serial ch.6 */ + MFS6TX_IRQHandler, /* 20: MultiFunction Serial ch.6 */ + MFS7RX_IRQHandler, /* 21: MultiFunction Serial ch.7 */ + MFS7TX_IRQHandler, /* 22: MultiFunction Serial ch.7 */ + PPG_Handler, /* 23: PPG */ + TIM_IRQHandler, /* 24: OSC / PLL / Watch Counter */ + ADC0_IRQHandler, /* 25: ADC0 */ + ADC1_IRQHandler, /* 26: ADC1 */ + ADC2_IRQHandler, /* 27: ADC2 */ + MFT_FRT_IRQHandler, /* 28: Free-run Timer */ + MFT_IPC_IRQHandler, /* 29: Input Capture */ + MFT_OPC_IRQHandler, /* 30: Output Compare */ + BT0_7_IRQHandler, /* 31: Base Timer ch.0 to ch.7 */ + ETHER_MAC0_IRQHandler, /* 32: Ethernet MAC ch.0 */ + ETHER_MAC1_IRQHandler, /* 33: Ethernet MAC ch.1 */ + USB0F_Handler, /* 34: USB0 Function */ + USB0_Handler, /* 35: USB0 Function / USB0 HOST */ + USB1F_Handler, /* 36: USB1 Function */ + USB1_Handler, /* 37: USB1 Function / USB1 HOST */ + DMAC0_Handler, /* 38: DMAC ch.0 */ + DMAC1_Handler, /* 39: DMAC ch.1 */ + DMAC2_Handler, /* 40: DMAC ch.2 */ + DMAC3_Handler, /* 41: DMAC ch.3 */ + DMAC4_Handler, /* 42: DMAC ch.4 */ + DMAC5_Handler, /* 43: DMAC ch.5 */ + DMAC6_Handler, /* 44: DMAC ch.6 */ + DMAC7_Handler, /* 45: DMAC ch.7 */ + BT8_15_IRQHandler, /* 46: Base Timer ch.8 to ch.15 */ + Default_Handler /* 47: Reserved */ +}; diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S new file mode 100644 index 0000000000..7bc1acf0cd --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S @@ -0,0 +1,417 @@ +;/************************************************************************/ +;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +;/* */ +;/* The following software deliverable is intended for and must only be */ +;/* used for reference and in an evaluation laboratory environment. */ +;/* It is provided on an as-is basis without charge and is subject to */ +;/* alterations. */ +;/* It is the user's obligation to fully test the software in its */ +;/* environment and to ensure proper functionality, qualification and */ +;/* compliance with component specifications. */ +;/* */ +;/* In the event the software deliverable includes the use of open */ +;/* source components, the provisions of the governing open source */ +;/* license agreement shall apply with respect to such software */ +;/* deliverable. */ +;/* FSEU does not warrant that the deliverables do not infringe any */ +;/* third party intellectual property right (IPR). In the event that */ +;/* the deliverables infringe a third party IPR it is the sole */ +;/* responsibility of the customer to obtain necessary licenses to */ +;/* continue the usage of the deliverable. */ +;/* */ +;/* To the maximum extent permitted by applicable law FSEU disclaims all */ +;/* warranties, whether express or implied, in particular, but not */ +;/* limited to, warranties of merchantability and fitness for a */ +;/* particular purpose for which the deliverable is not designated. */ +;/* */ +;/* To the maximum extent permitted by applicable law, FSEU's liability */ +;/* is restricted to intentional misconduct and gross negligence. */ +;/* FSEU is not liable for consequential damages. */ +;/* */ +;/* (V1.5) */ +;/************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.00 */ +;/* Date 2011-07-25 */ +;/* Target-mcu MB9B610 */ +;/************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD MemManage_Handler ; MPU Fault + DCD BusFault_Handler ; Bus Fault + DCD UsageFault_Handler ; Usage Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD DebugMon_Handler ; Debug Monitor + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0 + DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1 + DCD USB0F_Handler ; 34: USB0 Function + DCD USB0_Handler ; 35: USB0 Function / USB0 HOST + DCD USB1F_Handler ; 36: USB1 Function + DCD USB1_Handler ; 37: USB1 Function / USB1 HOST + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15 + DCD DummyHandler ; 47: Reserved + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + + PUBWEAK CSV_Handler + SECTION .text:CODE:REORDER(1) +CSV_Handler + B CSV_Handler + + PUBWEAK SWDT_Handler + SECTION .text:CODE:REORDER(1) +SWDT_Handler + B SWDT_Handler + + PUBWEAK LVD_Handler + SECTION .text:CODE:REORDER(1) +LVD_Handler + B LVD_Handler + + PUBWEAK MFT_WG_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_WG_IRQHandler + B MFT_WG_IRQHandler + + PUBWEAK INT0_7_Handler + SECTION .text:CODE:REORDER(1) +INT0_7_Handler + B INT0_7_Handler + + PUBWEAK INT8_31_Handler + SECTION .text:CODE:REORDER(1) +INT8_31_Handler + B INT8_31_Handler + + PUBWEAK DT_Handler + SECTION .text:CODE:REORDER(1) +DT_Handler + B DT_Handler + + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0RX_IRQHandler + B MFS0RX_IRQHandler + + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0TX_IRQHandler + B MFS0TX_IRQHandler + + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1RX_IRQHandler + B MFS1RX_IRQHandler + + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1TX_IRQHandler + B MFS1TX_IRQHandler + + PUBWEAK MFS2RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2RX_IRQHandler + B MFS2RX_IRQHandler + + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2TX_IRQHandler + B MFS2TX_IRQHandler + + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3RX_IRQHandler + B MFS3RX_IRQHandler + + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3TX_IRQHandler + B MFS3TX_IRQHandler + + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4RX_IRQHandler + B MFS4RX_IRQHandler + + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4TX_IRQHandler + B MFS4TX_IRQHandler + + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5RX_IRQHandler + B MFS5RX_IRQHandler + + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5TX_IRQHandler + B MFS5TX_IRQHandler + + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6RX_IRQHandler + B MFS6RX_IRQHandler + + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6TX_IRQHandler + B MFS6TX_IRQHandler + + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7RX_IRQHandler + B MFS7RX_IRQHandler + + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7TX_IRQHandler + B MFS7TX_IRQHandler + + PUBWEAK PPG_Handler + SECTION .text:CODE:REORDER(1) +PPG_Handler + B PPG_Handler + + PUBWEAK TIM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM_IRQHandler + B TIM_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK MFT_FRT_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_FRT_IRQHandler + B MFT_FRT_IRQHandler + + PUBWEAK MFT_IPC_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_IPC_IRQHandler + B MFT_IPC_IRQHandler + + PUBWEAK MFT_OPC_IRQHandler + SECTION .text:CODE:REORDER(1) +MFT_OPC_IRQHandler + B MFT_OPC_IRQHandler + + PUBWEAK BT0_7_IRQHandler + SECTION .text:CODE:REORDER(1) +BT0_7_IRQHandler + B BT0_7_IRQHandler + + PUBWEAK ETHER_MAC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ETHER_MAC0_IRQHandler + B ETHER_MAC0_IRQHandler + + PUBWEAK ETHER_MAC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ETHER_MAC1_IRQHandler + B ETHER_MAC1_IRQHandler + + PUBWEAK USB0F_Handler + SECTION .text:CODE:REORDER(1) +USB0F_Handler + B USB0F_Handler + + PUBWEAK USB0_Handler + SECTION .text:CODE:REORDER(1) +USB0_Handler + B USB0_Handler + + PUBWEAK USB1F_Handler + SECTION .text:CODE:REORDER(1) +USB1F_Handler + B USB1F_Handler + + PUBWEAK USB1_Handler + SECTION .text:CODE:REORDER(1) +USB1_Handler + B USB1_Handler + + PUBWEAK DMAC0_Handler + SECTION .text:CODE:REORDER(1) +DMAC0_Handler + B DMAC0_Handler + + + PUBWEAK DMAC1_Handler + SECTION .text:CODE:REORDER(1) +DMAC1_Handler + B DMAC1_Handler + + PUBWEAK DMAC2_Handler + SECTION .text:CODE:REORDER(1) +DMAC2_Handler + B DMAC2_Handler + + PUBWEAK DMAC3_Handler + SECTION .text:CODE:REORDER(1) +DMAC3_Handler + B DMAC3_Handler + + PUBWEAK DMAC4_Handler + SECTION .text:CODE:REORDER(1) +DMAC4_Handler + B DMAC4_Handler + + PUBWEAK DMAC5_Handler + SECTION .text:CODE:REORDER(1) +DMAC5_Handler + B DMAC5_Handler + + PUBWEAK DMAC6_Handler + SECTION .text:CODE:REORDER(1) +DMAC6_Handler + B DMAC6_Handler + + PUBWEAK DMAC7_Handler + SECTION .text:CODE:REORDER(1) +DMAC7_Handler + B DMAC7_Handler + + PUBWEAK BT8_15_IRQHandler + SECTION .text:CODE:REORDER(1) +BT8_15_IRQHandler + B BT8_15_IRQHandler + + PUBWEAK DummyHandler + SECTION .text:CODE:REORDER(1) +DummyHandler + B DummyHandler + + END diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c new file mode 100644 index 0000000000..a039f02431 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c @@ -0,0 +1,206 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ + +#include "board.h" + +/** \file system_mb9bf61x.c + ** + ** FM3 system initialization functions + ** All adjustments can be done in belonging header file. + ** + ** History: + ** 2011-07-07 V1.0 MWi original version + ******************************************************************************/ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = __HCLK; + +/** + ****************************************************************************** + ** \brief Update the System Core Clock with current core Clock retrieved from + ** cpu registers. + ** \param none + ** \return none + ******************************************************************************/ +void SystemCoreClockUpdate (void) { + uint32_t masterClk; + uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance + + switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) { + case 0: /* internal High-speed Cr osc. */ + masterClk = __CLKHC; + break; + + case 1: /* external main osc. */ + masterClk = __CLKMO; + break; + + case 2: /* PLL clock */ + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violation: + // "Unordered accesses to a volatile location" + u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1)); + masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1)); + break; + + case 4: /* internal Low-speed CR osc. */ + masterClk = __CLKLC; + break; + + case 5: /* external Sub osc. */ + masterClk = __CLKSO; + break; + + default: + masterClk = 0Ul; + break; + } + + switch (FM3_CRG->BSC_PSR & 0x07) { + case 0: + SystemCoreClock = masterClk; + break; + + case 1: + SystemCoreClock = masterClk / 2; + break; + + case 2: + SystemCoreClock = masterClk / 3; + break; + + case 3: + SystemCoreClock = masterClk / 4; + break; + + case 4: + SystemCoreClock = masterClk / 6; + break; + + case 5: + SystemCoreClock = masterClk /8; + break; + + case 6: + SystemCoreClock = masterClk /16; + break; + + default: + SystemCoreClock = 0Ul; + break; + } + +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit (void) { + + static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance + +#if (HWWD_DISABLE) /* HW Watchdog Disable */ + FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */ + FM3_HWWDT->WDG_LCK = 0xE5331AAE; + FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */ +#endif + +#if (CLOCK_SETUP) /* Clock Setup */ + FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */ + FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */ + FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */ + FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */ + FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */ + FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */ + + FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */ + + if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */ + while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */ + } + + if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ + while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ + } + + FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */ + FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */ + FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */ + + if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */ + FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */ + while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */ + } + + FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */ + + { + volatile unsigned int i; + for(i=0;i<200000;i++); + } + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violations: + // "Unordered reads and writes to or from same location" and + // "Unordered accesses to a volatile location" + do + { + u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0); + }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead); +#endif // (CLOCK_SETUP) + +#if (CR_TRIM_SETUP) + /* CR Trimming Data */ + if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) ) + { + /* UnLock (MCR_FTRM) */ + FM3_CRTRIM->MCR_RLR = 0x1ACCE554; + /* Set MCR_FTRM */ + FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM; + /* Lock (MCR_FTRM) */ + FM3_CRTRIM->MCR_RLR = 0x00000000; + } +#endif // (CR_TRIM_SETUP) +} + + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h new file mode 100644 index 0000000000..819f3646e9 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h @@ -0,0 +1,678 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/** \file system_mb9bf61x.h + ** + ** Headerfile for FM3 system parameters + ** + ** User clock definitions can be done for the following clock settings: + ** - CLOCK_SETUP : Execute the clock settings form the settings below in + ** SystemInit() + ** - __CLKMO : External clock frequency for main oscillion + ** - __CLKSO : External clock frequency for sub oscillion + ** - SCM_CTL : System Clock Mode Control Register + ** - BSC_PSR : Base Clock Prescaler Register + ** - APBC0_PSR : APB0 Prescaler Register + ** - APBC1_PSR : APB1 Prescaler Register + ** - APBC2_PSR : APB2 Prescaler Register + ** - SWC_PSR : Software Watchdog Clock Prescaler Register + ** - TTC_PSR : Trace Clock Prescaler Register + ** - CSW_TMR : Clock Stabilization Wait Time Register + ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register + ** - PLL_CTL1 : PLL Control Register 1 + ** - PLL_CTL2 : PLL Control Register 2 + ** + ** The register settings are check for correct values of reserved bits. + ** Otherwise a preprocessor error is output and stops the build process. + ** Furthermore the 'master clock' is retrieved from the register settings + ** and the system clock (HCLK) is calculated from the Base Clock Prescaler + ** Register (BSC_PSR). This value is used for the global CMSIS variable + ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is + ** is checked. Note that not all possible wrong setting are checked! The + ** user has to take care to fulfill the settings stated in the according + ** device's data sheet! + ** + ** User definition for Hardware Watchdog: + ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit() + ** + ** User definition for CR Trimming: + ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit() + ** + ** History: + ** 2011-05-16 V1.0 MWi original version + *****************************************************************************/ + +#ifndef _SYSTEM_MB9BF61X_H_ +#define _SYSTEM_MB9BF61X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup Enable + ** (USER SETTING) + ** + ** - 0 = No clock setup done by system_mb9xfxxx.c + ** - 1 = Clock setup done by system_mb9xfxxx.c + ******************************************************************************/ +#define CLOCK_SETUP 1 // <<< Define clock setup here + +/** + ****************************************************************************** + ** \brief External Main Clock Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal + +/** + ****************************************************************************** + ** \brief External Sub Clock Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal + +/** + ****************************************************************************** + ** \brief System Clock Mode Control Register value definition + ** (USER SETTING) + ** + ** SCM_CTL + ** + ** Bit#7-5 : RCS[2:0] + ** - 0 = Internal high-speed CR oscillation (default) + ** - 1 = Main oscillation clock + ** - 2 = PLL oscillation clock + ** - 3 = (not allowed) + ** - 4 = Internal low-speed CR oscillation + ** - 5 = Sub clock oscillation + ** - 6 = (not allowed) + ** - 7 = (not allowed) + ** + ** Bit#4 : PLLE + ** - 0 = Disable PLL (default) + ** - 1 = Enable PLL + ** + ** Bit#3 : SOSCE + ** - 0 = Disable sub oscillation (default) + ** - 1 = Enable sub oscillation + ** + ** Bit#2 : (reserved) + ** + ** Bit#1 : MOSCE + ** - 0 = Disable main oscillation (default) + ** - 1 = Enable main oscillation + ** + ** Bit#0 : (reserved) + ******************************************************************************/ +#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here + +/** + ****************************************************************************** + ** \brief Base Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** BSC_PSR + ** + ** Bit#7-3 : (reserved) + ** + ** Bit#2-0 : BSR[2:0] + ** - 0 = HCLK = Master Clock + ** - 1 = HCLK = Master Clock / 2 + ** - 2 = HCLK = Master Clock / 3 + ** - 3 = HCLK = Master Clock / 4 + ** - 4 = HCLK = Master Clock / 6 + ** - 5 = HCLK = Master Clock / 8 + ** - 6 = HCLK = Master Clock / 16 + ** - 7 = (reserved) + ******************************************************************************/ +#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here + +/** + ****************************************************************************** + ** \brief APB0 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC0_PSR + ** + ** Bit#7-2 : (reserved) + ** + ** Bit#1-0 : BSR[2:0] + ** - 0 = PCLK0 = HCLK + ** - 1 = PCLK0 = HCLK / 2 + ** - 2 = PCLK0 = HCLK / 4 + ** - 3 = PCLK0 = HCLK / 8 + ******************************************************************************/ +#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here + +/** + ****************************************************************************** + ** \brief APB1 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC1_PSR + ** + ** Bit#7 : APBC1EN + ** - 0 = Disable PCLK1 output + ** - 1 = Enables PCLK1 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC1RST + ** - 0 = APB1 bus reset, inactive (default) + ** - 1 = APB1 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC1[2:0] + ** - 0 = PCLK1 = HCLK + ** - 1 = PCLK1 = HCLK / 2 + ** - 2 = PCLK1 = HCLK / 4 + ** - 3 = PCLK1 = HCLK / 8 + ******************************************************************************/ +#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here + +/** + ****************************************************************************** + ** \brief APB2 Prescaler Register value definition + ** (USER SETTING) + ** + ** APBC2_PSR + ** + ** Bit#7 : APBC2EN + ** - 0 = Disable PCLK2 output + ** - 1 = Enables PCLK2 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC2RST + ** - 0 = APB2 bus reset, inactive (default) + ** - 1 = APB2 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC2[1:0] + ** - 0 = PCLK2 = HCLK + ** - 1 = PCLK2 = HCLK / 2 + ** - 2 = PCLK2 = HCLK / 4 + ** - 3 = PCLK2 = HCLK / 8 + ******************************************************************************/ +#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here + +/** + ****************************************************************************** + ** \brief Software Watchdog Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** SWC_PSR + ** + ** Bit#7 : TESTB + ** - 0 = (not allowed) + ** - 1 = (always write "1" to this bit) + ** + ** Bit#6-2 : (reserved) + ** + ** Bit#1-0 : SWDS[2:0] + ** - 0 = SWDGOGCLK = PCLK0 + ** - 1 = SWDGOGCLK = PCLK0 / 2 + ** - 2 = SWDGOGCLK = PCLK0 / 4 + ** - 3 = SWDGOGCLK = PCLK0 / 8 + ******************************************************************************/ +#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here + +/** + ****************************************************************************** + ** \brief Trace Clock Prescaler Register value definition + ** (USER SETTING) + ** + ** TTC_PSR + ** + ** Bit#7-1 : (reserved) + ** + ** Bit#0 : TTC + ** - 0 = TPIUCLK = HCLK + ** - 1 = TPIUCLK = HCLK / 2 + ******************************************************************************/ +#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here + +/** + ****************************************************************************** + ** \brief Clock Stabilization Wait Time Register value definition + ** (USER SETTING) + ** + ** CSW_TMR + ** + ** Bit#7 : (reserved) + ** + ** Bit#6-4 : SOWT[2:0] + ** - 0 = ~10.3 ms (default) + ** - 1 = ~20.5 ms + ** - 2 = ~41 ms + ** - 3 = ~82 ms + ** - 4 = ~164 ms + ** - 5 = ~327 ms + ** - 6 = ~655 ms + ** - 7 = ~1.31 s + ** + ** Bit#3-0 : MOWT[3:0] + ** - 0 = ~500 ns (default) + ** - 1 = ~8 us + ** - 2 = ~16 us + ** - 3 = ~32 us + ** - 4 = ~64 us + ** - 5 = ~128 us + ** - 6 = ~256 us + ** - 7 = ~512 us + ** - 8 = ~1.0 ms + ** - 9 = ~2.0 ms + ** - 10 = ~4.0 ms + ** - 11 = ~8.0 ms + ** - 12 = ~33.0 ms + ** - 13 = ~131 ms + ** - 14 = ~524 ms + ** - 15 = ~2.0 s + ******************************************************************************/ +#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Clock Stabilization Wait Time Setup Register value definition + ** (USER SETTING) + ** + ** PSW_TMR + ** + ** Bit#7-5 : (reserved) + ** + ** Bit#4 : PINC + ** - 0 = Selects CLKMO (main oscillation) (default) + ** - 1 = (setting diabled) + ** + ** Bit#3 : (reserved) + ** + ** Bit#2-0 : POWT[2:0] + ** - 0 = ~128 us (default) + ** - 1 = ~256 us + ** - 2 = ~512 us + ** - 3 = ~1.02 ms + ** - 4 = ~2.05 ms + ** - 5 = ~4.10 ms + ** - 6 = ~8.20 ms + ** - 7 = ~16.40 ms + ******************************************************************************/ +#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Control Register 1 value definition + ** (USER SETTING) + ** + ** PLL_CTL1 + ** + ** Bit#7-4 : PLLK[3:0] + ** - 0 = Division(PLLK) = 1/1 (default) + ** - 1 = Division(PLLK) = 1/2 + ** - 2 = Division(PLLK) = 1/3 + ** - . . . + ** - 15 = Division(PLLK) = 1/16 + ** + ** Bit#3-0 : PLLM[3:0] + ** - 0 = Division(PLLM) = 1/1 (default) + ** - 1 = Division(PLLM) = 1/2 + ** - 2 = Division(PLLM) = 1/3 + ** - . . . + ** - 15 = Division(PLLM) = 1/16 + ******************************************************************************/ +#define PLL_CTL1_Val 0x00000001 // <<< Define PLL_CTL1 here + +/** + ****************************************************************************** + ** \brief PLL Control Register 2 value definition + ** (USER SETTING) + ** + ** PLL_CTL2 + ** + ** Bit#7-6 : (reserved) + ** + ** Bit#5-0 : PLLN[5:0] + ** - 0 = Division(PLLN) = 1/1 (default) + ** - 1 = Division(PLLN) = 1/2 + ** - 2 = Division(PLLN) = 1/3 + ** - . . . + ** - 63 = Division(PLLN) = 1/64 + ******************************************************************************/ +#define PLL_CTL2_Val 0x00000023 // <<< Define PLL_CTL2 here + +/** + ****************************************************************************** + ** \brief Hardware Watchdog disable definition + ** (USER SETTING) + ** + ** - 0 = Hardware Watchdog enable + ** - 1 = Hardware Watchdog disable + ******************************************************************************/ +#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here + +/** + ****************************************************************************** + ** \brief Trimming CR + ** (USER SETTING) + ** + ** - 0 = CR is not trimmed at startup + ** - 1 = CR is trimmed at startup + ******************************************************************************/ +#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here + + +/******************************************************************************/ +/* */ +/* END OF USER SETTINGS HERE */ +/* ========================= */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Device dependent System Clock absolute maximum ranges */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */ + +/** + ****************************************************************************** + ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMIN ( 4000000UL) + +/** + ****************************************************************************** + ** \brief Maximum Main Clock frequency using external clock + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMAX ( 50000000UL) + +/** + ****************************************************************************** + ** \brief Any case minimum Sub Clock frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMIN ( 32000UL) + +/** + ****************************************************************************** + ** \brief Maximum Sub Clock frequency using external clock + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMAX ( 100000UL) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL input frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMIN ( 4000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL input frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMAX ( 16000000UL) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL oscillation frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMIN (200000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL oscillation frequency + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKMAX (300000000UL) + +/** + ****************************************************************************** + ** \brief Absolute maximum System Clock frequency (HCLK) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __HCLKMAX (144000000UL) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking range (clock settings) + ******************************************************************************/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking bits with mask (clock settings) + ******************************************************************************/ +#define CHECK_RSVD(val, mask) (val & mask) + + +/******************************************************************************/ +/* Check register settings */ +/******************************************************************************/ +#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA)) + #error "SCM_CTL: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10) + #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" +#endif + +#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F)) + #error "CSW_TMR: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */ + #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007)) + #error "PSW_TMR: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF)) + #error "PLL_CTL1: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F)) + #error "PLL_CTL2: Invalid values of reserved bits!" + #endif +#endif + +#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007)) + #error "BSC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003)) + #error "APBC0_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083)) + #error "APBC1_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083)) + #error "APBC2_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003)) + #error "SWC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001)) + #error "TTC_PSR: Invalid values of reserved bits!" +#endif + +/******************************************************************************/ +/* Define clocks with checking settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Calculate PLL K factor from settings + ******************************************************************************/ +#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL N factor from settings + ******************************************************************************/ +#define __PLLN (((PLL_CTL2_Val ) & 0x3F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL M factor from settings + ******************************************************************************/ +#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1) + +/** + ****************************************************************************** + ** \brief Calculate PLL output frequency from settings + ******************************************************************************/ +#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) + +/******************************************************************************/ +/* Determine core clock frequency according to settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Define Master Clock from settings + ******************************************************************************/ +#if (((SCM_CTL_Val >> 5) & 0x07) == 0) + #define __MASTERCLK (__CLKHC) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 1) + #define __MASTERCLK (__CLKMO) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 2) + #define __MASTERCLK (__PLLCLK) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 4) + #define __MASTERCLK (__CLKLC) +#elif (((SCM_CTL_Val >> 5) & 0x07) == 5) + #define __MASTERCLK (__CLKSO) +#else + #define __MASTERCLK (0UL) +#endif + +/** + ****************************************************************************** + ** \brief Define System Clock Frequency (Core Clock) from settings + ******************************************************************************/ +#if ((BSC_PSR_Val & 0x07) == 0) + #define __HCLK (__MASTERCLK / 1) +#elif ((BSC_PSR_Val & 0x07) == 1) + #define __HCLK (__MASTERCLK / 2) +#elif ((BSC_PSR_Val & 0x07) == 2) + #define __HCLK (__MASTERCLK / 3) +#elif ((BSC_PSR_Val & 0x07) == 3) + #define __HCLK (__MASTERCLK / 4) +#elif ((BSC_PSR_Val & 0x07) == 4) + #define __HCLK (__MASTERCLK / 6) +#elif ((BSC_PSR_Val & 0x07) == 5) + #define __HCLK (__MASTERCLK / 8) +#elif ((BSC_PSR_Val & 0x07) == 6) + #define __HCLK (__MASTERCLK /16) +#else + #define __HCLK (0UL) +#endif + +/******************************************************************************/ +/* HCLK range check */ +/******************************************************************************/ +#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0) + #error "Main Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0) + #error "Sub Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0) + #error "PLL input frequency out of range!" +#endif + +#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0) + #error "PLL oscillation frequency out of range!" +#endif + +#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0) + #error "System Clock (HCLK) out of range!" +#endif + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +extern void SystemInit (void); // Initialize the system + +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MB9BF61X_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_common_tables.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..7a59b5923e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_const_structs.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..8d7fac0f04 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH + }; + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_math.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..65304c127d --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/arm_math.h @@ -0,0 +1,7306 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..ab31de0ee8 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0.h @@ -0,0 +1,682 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0plus.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..5cea74e9af --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,793 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm3.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..122c9aa4a8 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm3.h @@ -0,0 +1,1627 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..d65016c714 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4.h @@ -0,0 +1,1772 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4_simd.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 0000000000..83db95b5f1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmFunc.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..0a18fafc30 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmInstr.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..d213f0eed7 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc000.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..1a2a0f2e30 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc000.h @@ -0,0 +1,813 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc300.h b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..cc34d6fc0e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/core_sc300.h @@ -0,0 +1,1598 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/README.txt b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/README.txt new file mode 100644 index 0000000000..23717194f4 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/README.txt @@ -0,0 +1,37 @@ +* ------------------------------------------------------------------- +* Copyright (C) 2011-2013 ARM Limited. All rights reserved. +* +* Date: 18 March 2013 +* Revision: V3.20 +* +* Project: Cortex Microcontroller Software Interface Standard (CMSIS) +* Title: Release Note for CMSIS +* +* ------------------------------------------------------------------- + + +NOTE - Open the index.html file to access CMSIS documentation + + +The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all +Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects +and reduces time-to-market for new embedded applications. + +CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). +Any user of the software package is bound to the terms and conditions of the end user license agreement. + + +You will find the following sub-directories: + +Documentation - Contains CMSIS documentation. + +DSP_Lib - MDK project files, Examples and source files etc.. to build the + CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. + +Include - CMSIS Core Support and CMSIS DSP Include Files. + +Lib - CMSIS DSP Libraries. + +RTOS - CMSIS RTOS API template header file. + +SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/SConscript b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/SConscript new file mode 100644 index 0000000000..64f6f21408 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/SConscript @@ -0,0 +1,21 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c') + +CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/'] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S'] + +CPPDEFINES = [rtconfig.FM3_TYPE] +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf618s/SConscript b/bsp/fujitsu/mb9x/mb9bf618s/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/fujitsu/mb9x/mb9bf618s/SConstruct b/bsp/fujitsu/mb9x/mb9bf618s/SConstruct new file mode 100644 index 0000000000..97f374e663 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/SConstruct @@ -0,0 +1,35 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/fujitsu/mb9x/mb9bf618s/applications/SConscript b/bsp/fujitsu/mb9x/mb9bf618s/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf618s/applications/application.c b/bsp/fujitsu/mb9x/mb9bf618s/applications/application.c new file mode 100644 index 0000000000..737034fff6 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/applications/application.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-24 Bernard the first version + */ + +/** + * @addtogroup FM3 + */ +/*@{*/ + +#include +#include "board.h" + +void rt_init_thread_entry(void *parameter) +{ +#ifdef RT_USING_COMPONENTS_INIT + /* initialization RT-Thread Components */ + rt_components_init(); +#endif + +#ifdef RT_USING_FINSH + (RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_FINSH */ + + /**< init led device */ + { + extern void rt_led_hw_init(void); + rt_led_hw_init(); + } + +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 8, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/applications/startup.c b/bsp/fujitsu/mb9x/mb9bf618s/applications/startup.c new file mode 100644 index 0000000000..22d38bcf95 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/applications/startup.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init application */ + rt_application_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/SConscript b/bsp/fujitsu/mb9x/mb9bf618s/drivers/SConscript new file mode 100644 index 0000000000..5bbef48785 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.c b/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.c new file mode 100644 index 0000000000..8490e7a060 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" + +#include "serial.h" + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This fucntion returns milliseconds since system passed + */ +rt_uint32_t rt_hw_tick_get_millisecond(void) +{ + rt_tick_t tick; + rt_uint32_t value; + +#define TICK_MS (1000/RT_TICK_PER_SECOND) + + tick = rt_tick_get(); + value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD; + + return value; +} + +/** + * This fucntion returns microseconds since system passed + */ +rt_uint32_t rt_hw_tick_get_microsecond(void) +{ + rt_tick_t tick; + rt_uint32_t value; + +#define TICK_US (1000000/RT_TICK_PER_SECOND) + + tick = rt_tick_get(); + value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; + + return value; +} + +/** +* This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init(void) +{ + /* disable all analog input. */ + FM3_GPIO->ADE = 0; + + /* init systick */ + SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.h b/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.h new file mode 100644 index 0000000000..c082b0b54c --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/board.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#if defined MB9B610S +# include +#elif defined MB9B610T +# include +#else +# warning "you must define CPU type. e.g: MB9B610S or MB9B610T" +# warning "define MB9B610S default" +# define MB9B610S /* default: MB9B610S */ +# include +#endif + +#include "serial.h" + +//Internal SRAM memory size[Kbytes] <8-64> +//product MB9BFx16S/T MB9BFx17S/T MB9BFx18S/T +//FLASH : 512 768 1024 +//SRAM0 : 32 48 64 +//SRAM1 : 32 48 64 +#define FM3_SRAM_SIZE 128 +#define FM3_SRAM_END (0x1FFF0000 + FM3_SRAM_SIZE * 1024) + +/* RT_USING_UART */ +#define RT_USING_UART0 +//#define RT_USING_UART2 +//#define RT_USING_UART4 +#define RT_UART_RX_BUFFER_SIZE 64 + +void rt_hw_board_init(void); +rt_uint32_t rt_hw_tick_get_millisecond(void); +rt_uint32_t rt_hw_tick_get_microsecond(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/led.c b/bsp/fujitsu/mb9x/mb9bf618s/drivers/led.c new file mode 100644 index 0000000000..bfad9947e7 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/led.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include "board.h" + +#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */ + +#define LED_NUM 4 +struct fm3_gpio_ctrl +{ + uint32_t led_num; + volatile uint32_t * PDOR; + volatile uint32_t * PDIR; +}; + +struct fm3_led +{ + /* inherit from rt_device */ + struct rt_device parent; + + struct fm3_gpio_ctrl fm3_gpio_ctrl[LED_NUM]; +}; + +static struct fm3_led fm3_led; + +static rt_err_t rt_led_init (rt_device_t dev) +{ + uint32_t i; + + /* led0 : P54 */ + FM3_GPIO->PFR5 &= ~((1<<7) | (1<<6) | (1<<5) |(1<<4)); /* set P54 fuction is GPIO. */ + FM3_GPIO->DDR5 |= (1<<7) | (1<<6) | (1<<5) |(1<<4); /* set P54 output. */ + + /* LED0 */ + i = 0; + fm3_led.fm3_gpio_ctrl[i].led_num = 4; + fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; + fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; + + /* LED1 */ + i++; + fm3_led.fm3_gpio_ctrl[i].led_num = 5; + fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; + fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; + + /* LED2 */ + i++; + fm3_led.fm3_gpio_ctrl[i].led_num = 6; + fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; + fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; + + /* LED3 */ + i++; + fm3_led.fm3_gpio_ctrl[i].led_num = 7; + fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; + fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; + + return RT_EOK; +} + +static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_led_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_ubase_t index = 0; + rt_ubase_t nr = size; + rt_uint8_t * value = buffer; + + RT_ASSERT(dev == &fm3_led.parent); + RT_ASSERT((pos+size) <= LED_NUM ); + + for(index=0; index +void led(rt_uint32_t led, rt_uint32_t value) +{ + rt_uint8_t led_value = value; + rt_led_write(&fm3_led.parent, led, &led_value, 1); +} +FINSH_FUNCTION_EXPORT(led, e.g:led(0,100).) +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.c b/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.c new file mode 100644 index 0000000000..79279e79e5 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.c @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#include + +#include "serial.h" + +/** + * @addtogroup FM3 MB9B610 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + UART_ENABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + UART_DISABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->SSR & SSR_RDRF) + { + *ptr = uart->uart_device->RDR & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = '\r'; + } + + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = (*ptr & 0x1FF); + + ++ptr; + --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, + rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->SSR & SSR_RDRF) + { + rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +#ifdef RT_USING_UART0 +/* UART0 device driver structure */ +#define UART0 FM3_MFS0_UART +struct serial_int_rx uart0_int_rx; +struct serial_device uart0 = +{ + UART0, + MFS0RX_IRQn, + MFS0TX_IRQn, + &uart0_int_rx, + RT_NULL +}; +struct rt_device uart0_device; + +void MFS0RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart0_device); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /**< #ifdef RT_USING_UART0 */ + +#ifdef RT_USING_UART2 +/* UART2 device driver structure */ +#define UART2 FM3_MFS2_UART +struct serial_int_rx uart2_int_rx; +struct serial_device uart2 = +{ + UART2, + MFS2RX_IRQn, + MFS2TX_IRQn, + &uart2_int_rx, + RT_NULL +}; +struct rt_device uart2_device; + +void MFS2RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart2_device); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /**< #ifdef RT_USING_UART2 */ + +#ifdef RT_USING_UART4 +/* UART4 device driver structure */ +#define UART4 FM3_MFS4_UART +struct serial_int_rx uart4_int_rx; +struct serial_device uart4 = +{ + (FM3_MFS03_UART_TypeDef*)UART4, + MFS4RX_IRQn, + MFS4TX_IRQn, + &uart4_int_rx, + RT_NULL +}; +struct rt_device uart4_device; + +void MFS4RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart4_device); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /**< #ifdef RT_USING_UART4 */ + +void rt_hw_serial_init(void) +{ + uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); + +#ifdef RT_USING_UART0 + /* initialize UART0 */ + /* Set Uart Ch0 Port, SIN0_0:P21, SOT0_0:P22 */ + FM3_GPIO->ADE &= ~(1UL<<31); /* disable P22 AN31 function */ + FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | (1<<1) | (1<<2); + FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 & ~(3<<4 | 3<<6) | (1<<4) | (1<<6); + + uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ + uart0.uart_device->ESCR = ESCR_DATABITS_8; + uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + /* register UART0 device */ + rt_hw_serial_register(&uart0_device, + "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); +#endif /**< #ifdef RT_USING_UART0 */ + +#ifdef RT_USING_UART2 + /* initialize UART2 */ + /* Set Uart Ch2 Port, SIN2_2:P17, SOT2_2:P18 */ + FM3_GPIO->ADE &= ~(1<<7 | 1<<8); /* disable P17 AN07 and P18 AN08 function */ + FM3_GPIO->PFR1 = FM3_GPIO->PFR1 | (1<<7) | (1<<8) ; + FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | (3<<16) | (3<<18) ; + + uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + uart2.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ + uart2.uart_device->ESCR = ESCR_DATABITS_8; + uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + /* register UART2 device */ + rt_hw_serial_register(&uart2_device, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); +#endif /**< #ifdef RT_USING_UART2 */ + +#ifdef RT_USING_UART4 + /* initialize UART4 */ + /* Set Uart Ch4 Port, SIN4_2:P05, SOT4_2:P06 */ + FM3_GPIO->PFR0 = FM3_GPIO->PFR0 | (1<<5) | (1<<6); + FM3_GPIO->EPFR08 = FM3_GPIO->EPFR08 | (3<<4) | (3<<6); + + uart4.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + uart4.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ + uart4.uart_device->ESCR = ESCR_DATABITS_8; + uart4.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + /* register UART4 device */ + rt_hw_serial_register(&uart4_device, + "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart4); +#endif /**< #ifdef RT_USING_UART4 */ +} + +/*@}*/ diff --git a/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.h b/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.h new file mode 100644 index 0000000000..388f9eef86 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/drivers/serial.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#include "board.h" + +#define SMR_SOE 0x01U +#define SMR_BDS 0x04U +#define SMR_SBL 0x08U +#define SMR_WUCR 0x10U +#define SMR_MD_UART 0x00U +#define SMR_MD_UART_MP 0x20U +#define SMR_MD_SIO 0x40U +#define SMR_MD_LIN 0x60U +#define SMR_MD_I2C 0x80U + +#define SCR_TXE 0x01U +#define SCR_RXE 0x02U +#define SCR_TBIE 0x04U +#define SCR_TIE 0x08U +#define SCR_RIE 0x10U +#define SCR_UPGL 0x80U + +#define SSR_TBI 0x01U +#define SSR_TDRE 0x02U +#define SSR_RDRF 0x04U +#define SSR_ORE 0x08U +#define SSR_FRE 0x10U +#define SSR_PE 0x20U +#define SSR_REC 0x80U + +#define ESCR_P 0x08U +#define ESCR_PEN 0x10U +#define ESCR_INV 0x20U +#define ESCR_ESBL 0x40U +#define ESCR_FLWEN 0x80U +#define ESCR_DATABITS_8 0x00U +#define ESCR_DATABITS_5 0x01U +#define ESCR_DATABITS_6 0x02U +#define ESCR_DATABITS_7 0x03U +#define ESCR_DATABITS_9 0x04U + +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +/* + * Enable/DISABLE Interrupt Controller + */ +/* deviation from MISRA-C:2004 Rule 19.7 */ +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct serial_device +{ + FM3_MFS03_UART_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq, tx_irq; + + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +void rt_hw_serial_isr(rt_device_t device); +void rt_hw_serial_init(void); + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.ewp b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp new file mode 100644 index 0000000000..25f7f69663 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp @@ -0,0 +1,2012 @@ + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 15 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\application.c + + + $PROJ_DIR$\applications\startup.c + + + + CMSIS + + $PROJ_DIR$\CMSIS\DeviceSupport\fujitsu\mb9bf61x\system_mb9bf61x.c + + + $PROJ_DIR$\CMSIS\DeviceSupport\fujitsu\mb9bf61x\startup\iar\startup_mb9bf61x.S + + + + Compiler + + $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + + CPU + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S + + + + Drivers + + $PROJ_DIR$\drivers\led.c + + + $PROJ_DIR$\drivers\serial.c + + + $PROJ_DIR$\drivers\board.c + + + + Finsh + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + + Kernel + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\timer.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\irq.c + + + + POSIX + + + utestcases + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.eww b/bsp/fujitsu/mb9x/mb9bf618s/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj new file mode 100644 index 0000000000..c249d3fac1 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj @@ -0,0 +1,630 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + + + MB9BF618S + Fujitsu Semiconductors + IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000) + 6149 + mb9bf618s.h + + + + + + + + + + SFD\Fujitsu\MB9BF610\MB9BF618S.SFR + 0 + + + + Fujitsu\MB9BF610\ + Fujitsu\MB9BF610\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-fm3 + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff0000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + MB9B610S, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;CMSIS\Include;CMSIS\DeviceSupport\fujitsu\mb9bf61x;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + rtthread-fm3.sct + + + + + + + + + + + Applications + + + startup.c + 1 + applications\startup.c + + + + + application.c + 1 + applications\application.c + + + + + CMSIS + + + system_mb9bf61x.c + 1 + CMSIS\DeviceSupport\fujitsu\mb9bf61x\system_mb9bf61x.c + + + + + startup_mb9bf61x.S + 2 + CMSIS\DeviceSupport\fujitsu\mb9bf61x\startup\arm\startup_mb9bf61x.S + + + + + Compiler + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + + + syscall_mem.c + 1 + ..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + Drivers + + + serial.c + 1 + drivers\serial.c + + + + + board.c + 1 + drivers\board.c + + + + + led.c + 1 + drivers\led.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + Kernel + + + device.c + 1 + ..\..\src\device.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + clock.c + 1 + ..\..\src\clock.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.h b/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.h new file mode 100644 index 0000000000..d887692233 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.h @@ -0,0 +1,75 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +// +#define RT_USING_COMPONENTS_INIT + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE + +/* SECTION: Console options */ +/* #define RT_TINY_SIZE */ +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart0" + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_STACK_SIZE 1024 + +#endif diff --git a/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.py b/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.py new file mode 100644 index 0000000000..474ff3dd57 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +#device options +# FM3_TYPE = +# 'MB9B610S','MB9B610T', +FM3_TYPE = 'MB9B610S' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'F:\Program Files\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI_2013.05.23\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'E:/Keil' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-fm3.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread-fm3.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + CFLAGS = '' + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' + + LFLAGS = ' --config rtthread-fm3.icf' + LFLAGS += ' --semihosting' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.icf b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.icf new file mode 100644 index 0000000000..7876fa0c81 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly, block RTT_INIT_FUNC }; +place in RAM_region { readwrite, block CSTACK, last block HEAP }; diff --git a/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.ld b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.ld new file mode 100644 index 0000000000..6696a0b1c2 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.ld @@ -0,0 +1,143 @@ +/* + * linker script for Fujitsu with GNU ld + * aozima 2013-07-13 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 1M /* 1MB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram, 64KB SRAM0 + 64KB SRAM1 */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _isr_vector = .; /* define isr_vector start address */ + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.sct b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.sct new file mode 100644 index 0000000000..405f2ebb65 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/rtthread-fm3.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x1FFF0000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/template.ewp b/bsp/fujitsu/mb9x/mb9bf618s/template.ewp new file mode 100644 index 0000000000..4883fc16e7 --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/template.ewp @@ -0,0 +1,1839 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 15 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/fujitsu/mb9x/mb9bf618s/template.uvproj b/bsp/fujitsu/mb9x/mb9bf618s/template.uvproj new file mode 100644 index 0000000000..ec72dd0f7f --- /dev/null +++ b/bsp/fujitsu/mb9x/mb9bf618s/template.uvproj @@ -0,0 +1,394 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + + + MB9BF618S + Fujitsu Semiconductors + IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000) + 6149 + mb9bf618s.h + + + + + + + + + + SFD\Fujitsu\MB9BF610\MB9BF618S.SFR + 0 + + + + Fujitsu\MB9BF610\ + Fujitsu\MB9BF610\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-fm3 + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff0000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + rtthread-fm3.sct + + + + + + + + + + + + diff --git a/bsp/mb9bf500r/CMSIS/SConscript b/bsp/mb9bf500r/CMSIS/SConscript deleted file mode 100644 index 165b344fe8..0000000000 --- a/bsp/mb9bf500r/CMSIS/SConscript +++ /dev/null @@ -1,19 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -src = Glob('*.c') - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src = src + ['start_gcc.S'] -elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['start_rvds.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src = src + ['start_iar.S'] - -CPPPATH = [GetCurrentDir()] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '') - -Return('group') diff --git a/bsp/mb9bf500r/CMSIS/core_cm3.c b/bsp/mb9bf500r/CMSIS/core_cm3.c deleted file mode 100644 index f176c3acca..0000000000 --- a/bsp/mb9bf500r/CMSIS/core_cm3.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.40 - * @date 18. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif diff --git a/bsp/mb9bf500r/CMSIS/core_cm3.h b/bsp/mb9bf500r/CMSIS/core_cm3.h deleted file mode 100644 index e062e30606..0000000000 --- a/bsp/mb9bf500r/CMSIS/core_cm3.h +++ /dev/null @@ -1,1166 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CM3_H__ -#define __CORE_CM3_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - not yet checked - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - -#include /* Include standard types */ - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - -/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; -#else - uint32_t _reserved0:16; - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; - uint32_t w; -} APSR_Type; - -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 00..08 Exception number */ - uint32_t _reserved0:23; - } b; - uint32_t w; -} IPSR_Type; - -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 00..08 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; -#else - uint32_t _reserved0:7; - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; - uint32_t w; -} xPSR_Type; - -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */ - uint32_t _reserved0:29; - } b; - uint32_t w; -} CONTROL_Type; - -/*@}*/ /* end of group CMSIS_ARM_CORE */ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/* ########################## Core Instruction Access ######################### */ -#include "core_cmInstr.h" - -/* ########################### Core Function Access ########################### */ -#include "core_cmFunc.h" - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CORE_CM3_H__ */ - -/*lint -restore */ diff --git a/bsp/mb9bf500r/CMSIS/core_cmFunc.h b/bsp/mb9bf500r/CMSIS/core_cmFunc.h deleted file mode 100644 index b9500f5510..0000000000 --- a/bsp/mb9bf500r/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,912 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H__ -#define __CORE_CMFUNC_H__ - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_CONTROL(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_CONTROL(uint32_t control); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_IPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_APSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_xPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PSP(uint32_t topOfProcStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_MSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_MSP(uint32_t topOfMainStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_MSP(uint32_t mainStackPointer) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = mainStackPointer; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PRIMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PRIMASK(uint32_t priMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_BASEPRI(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_BASEPRI(uint32_t basePri); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_FAULTMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_FAULTMASK(uint32_t faultMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} -#endif /* __ARMCC_VERSION */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - - #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - -#pragma diag_suppress=Pe940 - - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __enable_irq __enable_interrupt - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __disable_irq __disable_interrupt - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -static uint32_t __get_IPSR(void) -{ - __ASM("mrs r0, ipsr"); -} - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -static uint32_t __get_xPSR(void) -{ - __ASM("mrs r0, psr"); // assembler does not know "xpsr" -} - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ - static uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -static void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -static uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -static void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - /* not yet implemented */ - return(0); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - /* not yet implemented */ -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) ); -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result __ASM ("r0") = 0; - - __ASM volatile ("MRS %0, psp\n" - "BX lr \n" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" - "BX lr \n" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) ); -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result __ASM ("r0") = 0; - - __ASM volatile ("MRS %0, msp\n" - "BX lr \n" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" - "BX lr \n" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result=0; - - __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("MSR control, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -#endif // __CORE_CMFUNC_H__ diff --git a/bsp/mb9bf500r/CMSIS/core_cmInstr.h b/bsp/mb9bf500r/CMSIS/core_cmInstr.h deleted file mode 100644 index e9bbde943d..0000000000 --- a/bsp/mb9bf500r/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,684 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H__ -#define __CORE_CMINSTR_H__ - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -#define __NOP __nop - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -#define __WFI __wfi - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -#define __SEV __sev - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -#define __ISB() __isb(0xF) - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -#define __DSB() __dsb(0xF) - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -#define __REV __rev - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -#if (__ARMCC_VERSION < 400677) -extern uint32_t __REV16(uint16_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -#if (__ARMCC_VERSION < 400677) -extern int32_t __REVSH(int16_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -#define __RBIT __rbit - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -#define __STREXB(value, ptr) __strex(value, ptr) - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -#define __STREXH(value, ptr) __strex(value, ptr) - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#if (__ARMCC_VERSION < 400000) -extern void __CLREX(void); -#else /* (__ARMCC_VERSION >= 400000) */ -#define __CLREX __clrex -#endif /* __ARMCC_VERSION */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - -#pragma diag_suppress=Pe940 - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -#define __NOP __no_operation - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -static __INLINE void __WFI() { __ASM ("wfi"); } - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -static __INLINE void __WFE() { __ASM ("wfe"); } - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -static __INLINE void __SEV() { __ASM ("sev"); } - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -/* intrinsic void __ISB(void) (see intrinsics.h */ - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -/* intrinsic void __DSB(void) (see intrinsics.h */ - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -/* intrinsic void __DMB(void) (see intrinsics.h */ - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */ - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -static uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -static uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -static uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -static uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */ -static uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -static uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -static uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */ -static uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); -} - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -static __INLINE void __CLREX() { __ASM ("clrex"); } - -#endif /* (__CORTEX_M >= 0x03) */ - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -static __INLINE void __NOP() { __ASM volatile ("nop"); } - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -static __INLINE void __WFI() { __ASM volatile ("wfi"); } - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -static __INLINE void __WFE() { __ASM volatile ("wfe"); } - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -static __INLINE void __SEV() { __ASM volatile ("sev"); } - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -static __INLINE void __ISB() { __ASM volatile ("isb"); } - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -static __INLINE void __DSB() { __ASM volatile ("dsb"); } - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -static __INLINE void __DMB() { __ASM volatile ("dmb"); } - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -static __INLINE uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -static __INLINE int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -static __INLINE uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -static __INLINE uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -static __INLINE uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -#endif // __CORE_CMINSTR_H__ diff --git a/bsp/mb9bf500r/CMSIS/mb9bf506r.h b/bsp/mb9bf500r/CMSIS/mb9bf506r.h deleted file mode 100644 index 68d3e8b362..0000000000 --- a/bsp/mb9bf500r/CMSIS/mb9bf506r.h +++ /dev/null @@ -1,9739 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/* */ -/* Header File for Device MB9BF506R */ -/* Version V1.00 */ -/* Date 2011-01-21 */ -/* */ -/************************************************************************/ - -#ifndef _MB9BF506R_H_ -#define _MB9BF506R_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - - -/****************************************************************************** - * Interrupt Number Definition - ******************************************************************************/ -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSVC_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Super Visor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detector */ - WFG_IRQn = 3, /* Wave Form Generator */ - EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ - EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ - DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ - MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */ - MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */ - MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */ - MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */ - MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */ - MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */ - MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */ - MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */ - MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */ - MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */ - MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */ - MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */ - MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */ - MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */ - MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */ - MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */ - PPG_IRQn = 23, /* PPG */ - OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ - ADC0_IRQn = 25, /* ADC0 */ - ADC1_IRQn = 26, /* ADC1 */ - ADC2_IRQn = 27, /* ADC2 */ - FRTIM_IRQn = 28, /* Free-run Timer */ - INCAP_IRQn = 29, /* Input Capture */ - OUTCOMP_IRQn = 30, /* Output Compare */ - BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ - CAN0_IRQn = 32, /* CAN ch.0 */ - CAN1_IRQn = 33, /* CAN ch.1 */ - USBF_IRQn = 34, /* USB Function */ - USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ - /* Reserved = 36, */ - /* Reserved = 37, */ - DMAC0_IRQn = 38, /* DMAC ch.0 */ - DMAC1_IRQn = 39, /* DMAC ch.1 */ - DMAC2_IRQn = 40, /* DMAC ch.2 */ - DMAC3_IRQn = 41, /* DMAC ch.3 */ - DMAC4_IRQn = 42, /* DMAC ch.4 */ - DMAC5_IRQn = 43, /* DMAC ch.5 */ - DMAC6_IRQn = 44, /* DMAC ch.6 */ - DMAC7_IRQn = 45, /* DMAC ch.7 */ - /* Reserved = 46, */ - /* Reserved = 47, */ -} IRQn_Type; - - -#include "core_cm3.h" -#include "system_mb9bf50x.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - __IO uint32_t FASZR; - __IO uint32_t FRWTR; - __IO uint32_t FSTR; - uint8_t RESERVED0[4]; - __IO uint32_t FSYNDN; - uint8_t RESERVED1[236]; - __IO uint32_t CRTRMM; -}FM3_FIF_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - __IO uint8_t SCM_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t SCM_STR; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - __IO uint16_t RST_STR; - uint8_t RESERVED2[2]; - __IO uint8_t BSC_PSR; - uint8_t RESERVED3[3]; - __IO uint8_t APBC0_PSR; - uint8_t RESERVED4[3]; - __IO uint8_t APBC1_PSR; - uint8_t RESERVED5[3]; - __IO uint8_t APBC2_PSR; - uint8_t RESERVED6[3]; - __IO uint8_t SWC_PSR; - uint8_t RESERVED7[7]; - __IO uint8_t TTC_PSR; - uint8_t RESERVED8[7]; - __IO uint8_t CSW_TMR; - uint8_t RESERVED9[3]; - __IO uint8_t PSW_TMR; - uint8_t RESERVED10[3]; - __IO uint8_t PLL_CTL1; - uint8_t RESERVED11[3]; - __IO uint8_t PLL_CTL2; - uint8_t RESERVED12[3]; - __IO uint16_t CSV_CTL; - uint8_t RESERVED13[2]; - __IO uint8_t CSV_STR; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - __IO uint8_t DBWDT_CTL; - uint8_t RESERVED18[11]; - __IO uint8_t INT_ENR; - uint8_t RESERVED19[3]; - __IO uint8_t INT_STR; - uint8_t RESERVED20[3]; - __IO uint8_t INT_CLR; -}FM3_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - __IO uint8_t WDG_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - __IO uint8_t WDG_RIS; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM3_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - __IO uint8_t WDOGCONTROL; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - __IO uint8_t WDOGRIS; - uint8_t RESERVED1[3055]; - __IO uint32_t WDOGLOCK; -}FM3_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMER1LOAD; - __IO uint32_t TIMER1VALUE; - __IO uint32_t TIMER1CONTROL; - __IO uint32_t TIMER1INTCLR; - __IO uint32_t TIMER1RIS; - __IO uint32_t TIMER1MIS; - __IO uint32_t TIMER1BGLOAD; - uint8_t RESERVED0[4]; - __IO uint32_t TIMER2LOAD; - __IO uint32_t TIMER2VALUE; - __IO uint32_t TIMER2CONTROL; - __IO uint32_t TIMER2INTCLR; - __IO uint32_t TIMER2RIS; - __IO uint32_t TIMER2MIS; - __IO uint32_t TIMER2BGLOAD; -}FM3_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[40]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - uint8_t RESERVED2[2]; - __IO uint16_t TCSA0; - uint8_t RESERVED3[2]; - __IO uint16_t TCSB0; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT1; - uint8_t RESERVED6[2]; - __IO uint16_t TCSA1; - uint8_t RESERVED7[2]; - __IO uint16_t TCSB1; - uint8_t RESERVED8[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED9[2]; - __IO uint16_t TCDT2; - uint8_t RESERVED10[2]; - __IO uint16_t TCSA2; - uint8_t RESERVED11[2]; - __IO uint16_t TCSB2; -}FM3_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - __IO uint16_t OCCP0; - uint8_t RESERVED0[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP5; - uint8_t RESERVED5[2]; - __IO uint8_t OCSA10; - __IO uint8_t OCSB10; - uint8_t RESERVED6[2]; - __IO uint8_t OCSA32; - __IO uint8_t OCSB32; - uint8_t RESERVED7[2]; - __IO uint8_t OCSA54; - __IO uint8_t OCSB54; - uint8_t RESERVED8[3]; - __IO uint8_t OCSC; - uint8_t RESERVED9[50]; - __IO uint8_t OCFS10; - __IO uint8_t OCFS32; - uint8_t RESERVED10[2]; - __IO uint8_t OCFS54; -}FM3_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[128]; - __IO uint16_t WFTM10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTM32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTM54; - uint8_t RESERVED3[2]; - __IO uint16_t WFSA10; - uint8_t RESERVED4[2]; - __IO uint16_t WFSA32; - uint8_t RESERVED5[2]; - __IO uint16_t WFSA54; - uint8_t RESERVED6[2]; - __IO uint16_t WFIR; - uint8_t RESERVED7[2]; - __IO uint16_t NZCL; -}FM3_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[96]; - __IO uint8_t ICFS10; - __IO uint8_t ICFS32; - uint8_t RESERVED1[6]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - uint8_t RESERVED5[2]; - __IO uint8_t ICSA10; - __IO uint8_t ICSB10; - uint8_t RESERVED6[2]; - __IO uint8_t ICSA32; - __IO uint8_t ICSB32; -}FM3_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[160]; - __IO uint16_t ACCP0; - uint8_t RESERVED1[2]; - __IO uint16_t ACCPDN0; - uint8_t RESERVED2[2]; - __IO uint16_t ACCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACCPDN1; - uint8_t RESERVED4[2]; - __IO uint16_t ACCP2; - uint8_t RESERVED5[2]; - __IO uint16_t ACCPDN2; - uint8_t RESERVED6[2]; - __IO uint8_t ACSB; - uint8_t RESERVED7[3]; - __IO uint16_t ACSA; - uint8_t RESERVED8[2]; - __IO uint16_t ATSA; -}FM3_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t TTCR0; - uint8_t RESERVED1[7]; - __IO uint8_t COMP0; - uint8_t RESERVED2[2]; - __IO uint8_t COMP2; - uint8_t RESERVED3[4]; - __IO uint8_t COMP4; - uint8_t RESERVED4[2]; - __IO uint8_t COMP6; - uint8_t RESERVED5[12]; - __IO uint8_t TTCR1; - uint8_t RESERVED6[7]; - __IO uint8_t COMP1; - uint8_t RESERVED7[2]; - __IO uint8_t COMP3; - uint8_t RESERVED8[4]; - __IO uint8_t COMP5; - uint8_t RESERVED9[2]; - __IO uint8_t COMP7; - uint8_t RESERVED10[203]; - __IO uint16_t TRG; - uint8_t RESERVED11[2]; - __IO uint16_t REVC; - uint8_t RESERVED12[250]; - __IO uint8_t PPGC1; - __IO uint8_t PPGC0; - uint8_t RESERVED13[2]; - __IO uint8_t PPGC3; - __IO uint8_t PPGC2; - uint8_t RESERVED14[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED15[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED18[2]; - __IO uint8_t GATEC0; - uint8_t RESERVED19[39]; - __IO uint8_t PPGC5; - __IO uint8_t PPGC4; - uint8_t RESERVED20[2]; - __IO uint8_t PPGC7; - __IO uint8_t PPGC6; - uint8_t RESERVED21[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED25[2]; - __IO uint8_t GATEC4; - uint8_t RESERVED26[39]; - __IO uint8_t PPGC9; - __IO uint8_t PPGC8; - uint8_t RESERVED27[2]; - __IO uint8_t PPGC11; - __IO uint8_t PPGC10; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED30[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED31[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED32[2]; - __IO uint8_t GATEC8; - uint8_t RESERVED33[39]; - __IO uint8_t PPGC13; - __IO uint8_t PPGC12; - uint8_t RESERVED34[2]; - __IO uint8_t PPGC15; - __IO uint8_t PPGC14; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED37[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED38[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED39[2]; - __IO uint8_t GATEC12; -}FM3_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - __IO uint16_t TMCR; - uint8_t RESERVED3[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - __IO uint16_t TMCR; - uint8_t RESERVED3[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - __IO uint16_t TMCR; - uint8_t RESERVED2[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - __IO uint16_t TMCR; - uint8_t RESERVED2[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t BTSEL0123; -}FM3_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t BTSEL4567; -}FM3_BTIOSEL47_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - __IO uint16_t BTSSSR; -}FM3_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - __IO uint16_t QICR; - struct { - __IO uint8_t QICRL; - __IO uint8_t QICRH; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t QCR; - struct { - __IO uint8_t QCRL; - __IO uint8_t QCRH; - }; - }; - uint8_t RESERVED6[2]; - __IO uint16_t QECR; -}FM3_QPRC_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - __IO uint8_t ADSR; - __IO uint8_t ADCR; - uint8_t RESERVED0[6]; - __IO uint8_t SFNS; - __IO uint8_t SCCR; - uint8_t RESERVED1[2]; - union { - __IO uint32_t SCFD; - struct { - __IO uint16_t SCFDL; - __IO uint16_t SCFDH; - }; - }; - union { - __IO uint16_t SCIS23; - struct { - __IO uint8_t SCIS2; - __IO uint8_t SCIS3; - }; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t SCIS01; - struct { - __IO uint8_t SCIS0; - __IO uint8_t SCIS1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t PFNS; - __IO uint8_t PCCR; - uint8_t RESERVED4[2]; - union { - __IO uint32_t PCFD; - struct { - __IO uint16_t PCFDL; - __IO uint16_t PCFDH; - }; - }; - __IO uint8_t PCIS; - uint8_t RESERVED5[3]; - __IO uint8_t CMPCR; - uint8_t RESERVED6; - __IO uint16_t CMPD; - union { - __IO uint16_t ADSS23; - struct { - __IO uint8_t ADSS2; - __IO uint8_t ADSS3; - }; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t ADSS01; - struct { - __IO uint8_t ADSS0; - __IO uint8_t ADSS1; - }; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t ADST01; - struct { - __IO uint8_t ADST1; - __IO uint8_t ADST0; - }; - }; - uint8_t RESERVED9[2]; - __IO uint8_t ADCT; - uint8_t RESERVED10[3]; - __IO uint8_t PRTSL; - __IO uint8_t SCTSL; - uint8_t RESERVED11[2]; - __IO uint8_t ADCEN; -}FM3_ADC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - __IO uint8_t MCR_PSR; - uint8_t RESERVED0[3]; - __IO uint16_t MCR_FTRM; - uint8_t RESERVED1[6]; - __IO uint32_t MCR_RLR; -}FM3_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - __IO uint16_t ENIR; - uint8_t RESERVED0[2]; - __IO uint16_t EIRR; - uint8_t RESERVED1[2]; - __IO uint16_t EICL; - uint8_t RESERVED2[2]; - __IO uint32_t ELVR; - uint8_t RESERVED3[4]; - __IO uint8_t NMIRR; - uint8_t RESERVED4[3]; - __IO uint8_t NMICL; -}FM3_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - __IO uint32_t DRQSEL; - uint8_t RESERVED0[12]; - __IO uint32_t EXC02MON; - __IO uint32_t IRQ00MON; - __IO uint32_t IRQ01MON; - __IO uint32_t IRQ02MON; - __IO uint32_t IRQ03MON; - __IO uint32_t IRQ04MON; - __IO uint32_t IRQ05MON; - __IO uint32_t IRQ06MON; - __IO uint32_t IRQ07MON; - __IO uint32_t IRQ08MON; - __IO uint32_t IRQ09MON; - __IO uint32_t IRQ10MON; - __IO uint32_t IRQ11MON; - __IO uint32_t IRQ12MON; - __IO uint32_t IRQ13MON; - __IO uint32_t IRQ14MON; - __IO uint32_t IRQ15MON; - __IO uint32_t IRQ16MON; - __IO uint32_t IRQ17MON; - __IO uint32_t IRQ18MON; - __IO uint32_t IRQ19MON; - __IO uint32_t IRQ20MON; - __IO uint32_t IRQ21MON; - __IO uint32_t IRQ22MON; - __IO uint32_t IRQ23MON; - __IO uint32_t IRQ24MON; - __IO uint32_t IRQ25MON; - __IO uint32_t IRQ26MON; - __IO uint32_t IRQ27MON; - __IO uint32_t IRQ28MON; - __IO uint32_t IRQ29MON; - __IO uint32_t IRQ30MON; - __IO uint32_t IRQ31MON; - __IO uint32_t IRQ32MON; - __IO uint32_t IRQ33MON; - __IO uint32_t IRQ34MON; - __IO uint32_t IRQ35MON; - __IO uint32_t IRQ36MON; - __IO uint32_t IRQ37MON; - __IO uint32_t IRQ38MON; - __IO uint32_t IRQ39MON; - __IO uint32_t IRQ40MON; - __IO uint32_t IRQ41MON; - __IO uint32_t IRQ42MON; - __IO uint32_t IRQ43MON; - __IO uint32_t IRQ44MON; - __IO uint32_t IRQ45MON; - __IO uint32_t IRQ46MON; - __IO uint32_t IRQ47MON; -}FM3_INTREQ_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - __IO uint32_t PFR0; - __IO uint32_t PFR1; - __IO uint32_t PFR2; - __IO uint32_t PFR3; - __IO uint32_t PFR4; - __IO uint32_t PFR5; - __IO uint32_t PFR6; - __IO uint32_t PFR7; - __IO uint32_t PFR8; - uint8_t RESERVED0[220]; - __IO uint32_t PCR0; - __IO uint32_t PCR1; - __IO uint32_t PCR2; - __IO uint32_t PCR3; - __IO uint32_t PCR4; - __IO uint32_t PCR5; - __IO uint32_t PCR6; - __IO uint32_t PCR7; - uint8_t RESERVED1[224]; - __IO uint32_t DDR0; - __IO uint32_t DDR1; - __IO uint32_t DDR2; - __IO uint32_t DDR3; - __IO uint32_t DDR4; - __IO uint32_t DDR5; - __IO uint32_t DDR6; - __IO uint32_t DDR7; - __IO uint32_t DDR8; - uint8_t RESERVED2[220]; - __IO uint32_t PDIR0; - __IO uint32_t PDIR1; - __IO uint32_t PDIR2; - __IO uint32_t PDIR3; - __IO uint32_t PDIR4; - __IO uint32_t PDIR5; - __IO uint32_t PDIR6; - __IO uint32_t PDIR7; - __IO uint32_t PDIR8; - uint8_t RESERVED3[220]; - __IO uint32_t PDOR0; - __IO uint32_t PDOR1; - __IO uint32_t PDOR2; - __IO uint32_t PDOR3; - __IO uint32_t PDOR4; - __IO uint32_t PDOR5; - __IO uint32_t PDOR6; - __IO uint32_t PDOR7; - __IO uint32_t PDOR8; - uint8_t RESERVED4[220]; - __IO uint32_t ADE; - uint8_t RESERVED5[124]; - __IO uint32_t SPSR; - uint8_t RESERVED6[124]; - __IO uint32_t EPFR00; - __IO uint32_t EPFR01; - __IO uint32_t EPFR02; - uint8_t RESERVED7[4]; - __IO uint32_t EPFR04; - __IO uint32_t EPFR05; - __IO uint32_t EPFR06; - __IO uint32_t EPFR07; - __IO uint32_t EPFR08; - __IO uint32_t EPFR09; - __IO uint32_t EPFR10; -}FM3_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - __IO uint8_t LVD_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t LVD_STR; - uint8_t RESERVED1[3]; - __IO uint8_t LVD_CLR; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - __IO uint8_t LVD_STR2; -}FM3_LVD_TypeDef; - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USB clock registers */ -typedef struct -{ - __IO uint8_t UCCR; - uint8_t RESERVED0[3]; - __IO uint8_t UPCR1; - uint8_t RESERVED1[3]; - __IO uint8_t UPCR2; - uint8_t RESERVED2[3]; - __IO uint8_t UPCR3; - uint8_t RESERVED3[3]; - __IO uint8_t UPCR4; - uint8_t RESERVED4[3]; - __IO uint8_t UP_STR; - uint8_t RESERVED5[3]; - __IO uint8_t UPINT_ENR; - uint8_t RESERVED6[3]; - __IO uint8_t UPINT_CLR; - uint8_t RESERVED7[3]; - __IO uint8_t UPINT_STR; - uint8_t RESERVED8[15]; - __IO uint8_t USBEN; -}FM3_USBCLK_TypeDef; - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CAN prescaler register */ -typedef struct -{ - __IO uint8_t CANPRE; -}FM3_CANPRE_TypeDef; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_UART_TypeDef; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_CSIO_TypeDef; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_LIN_TypeDef; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* I2C channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t IBCR; - uint8_t RESERVED0[2]; - __IO uint8_t IBSR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t ISBA; - __IO uint8_t ISMK; -}FM3_MFS03_I2C_TypeDef; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_UART_TypeDef; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_CSIO_TypeDef; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_LIN_TypeDef; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* I2C channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t IBCR; - uint8_t RESERVED0[2]; - __IO uint8_t IBSR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t ISBA; - __IO uint8_t ISMK; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_I2C_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - __IO uint8_t CRCCR; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM3_CRC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - __IO uint8_t WCRD; - __IO uint8_t WCRL; - __IO uint8_t WCCR; - uint8_t RESERVED0[13]; - __IO uint16_t CLK_SEL; - uint8_t RESERVED1[2]; - __IO uint8_t CLK_EN; -}FM3_WC_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - __IO uint32_t MODE0; - __IO uint32_t MODE1; - __IO uint32_t MODE2; - __IO uint32_t MODE3; - __IO uint32_t MODE4; - __IO uint32_t MODE5; - __IO uint32_t MODE6; - __IO uint32_t MODE7; - __IO uint32_t TIM0; - __IO uint32_t TIM1; - __IO uint32_t TIM2; - __IO uint32_t TIM3; - __IO uint32_t TIM4; - __IO uint32_t TIM5; - __IO uint32_t TIM6; - __IO uint32_t TIM7; - __IO uint32_t AREA0; - __IO uint32_t AREA1; - __IO uint32_t AREA2; - __IO uint32_t AREA3; - __IO uint32_t AREA4; - __IO uint32_t AREA5; - __IO uint32_t AREA6; - __IO uint32_t AREA7; -}FM3_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - __IO uint16_t HCNT; - struct { - __IO uint8_t HCNT0; - __IO uint8_t HCNT1; - }; - }; - uint8_t RESERVED0[2]; - __IO uint8_t HIRQ; - __IO uint8_t HERR; - uint8_t RESERVED1[2]; - __IO uint8_t HSTATE; - __IO uint8_t HFCOMP; - uint8_t RESERVED2[2]; - union { - __IO uint16_t HRTIMER; - struct { - __IO uint8_t HRTIMER0; - __IO uint8_t HRTIMER1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t HRTIMER2; - __IO uint8_t HADR; - uint8_t RESERVED4[2]; - union { - __IO uint16_t HEOF; - struct { - __IO uint8_t HEOF0; - __IO uint8_t HEOF1; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t HFRAME; - struct { - __IO uint8_t HFRAME0; - __IO uint8_t HFRAME1; - }; - }; - uint8_t RESERVED6[2]; - __IO uint8_t HTOKEN; - uint8_t RESERVED7[3]; - __IO uint16_t UDCC; - uint8_t RESERVED8[2]; - __IO uint16_t EP0C; - uint8_t RESERVED9[2]; - __IO uint16_t EP1C; - uint8_t RESERVED10[2]; - __IO uint16_t EP2C; - uint8_t RESERVED11[2]; - __IO uint16_t EP3C; - uint8_t RESERVED12[2]; - __IO uint16_t EP4C; - uint8_t RESERVED13[2]; - __IO uint16_t EP5C; - uint8_t RESERVED14[2]; - __IO uint16_t TMSP; - uint8_t RESERVED15[2]; - __IO uint8_t UDCS; - __IO uint8_t UDCIE; - uint8_t RESERVED16[2]; - __IO uint16_t EP0IS; - uint8_t RESERVED17[2]; - __IO uint16_t EP0OS; - uint8_t RESERVED18[2]; - __IO uint16_t EP1S; - uint8_t RESERVED19[2]; - __IO uint16_t EP2S; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - __IO uint16_t EP4S; - uint8_t RESERVED22[2]; - __IO uint16_t EP5S; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM3_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - __IO uint32_t DMACR; - uint8_t RESERVED0[12]; - __IO uint32_t DMACA0; - __IO uint32_t DMACB0; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - __IO uint32_t DMACA1; - __IO uint32_t DMACB1; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - __IO uint32_t DMACA2; - __IO uint32_t DMACB2; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - __IO uint32_t DMACA3; - __IO uint32_t DMACB3; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - __IO uint32_t DMACA4; - __IO uint32_t DMACB4; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - __IO uint32_t DMACA5; - __IO uint32_t DMACB5; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - __IO uint32_t DMACA6; - __IO uint32_t DMACB6; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - __IO uint32_t DMACA7; - __IO uint32_t DMACB7; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM3_DMAC_TypeDef; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN channel 0 registers */ -typedef struct -{ - __IO uint16_t CTRLR; - __IO uint16_t STATR; - __IO uint16_t ERRCNT; - __IO uint16_t BTR; - __IO uint16_t INTR; - __IO uint16_t TESTR; - __IO uint16_t BRPER; - uint8_t RESERVED0[2]; - __IO uint16_t IF1CREQ; - __IO uint16_t IF1CMSK; - union { - __IO uint32_t IF1MSK; - struct { - __IO uint16_t IF1MSK1; - __IO uint16_t IF1MSK2; - }; - }; - union { - __IO uint32_t IF1ARB; - struct { - __IO uint16_t IF1ARB1; - __IO uint16_t IF1ARB2; - }; - }; - __IO uint16_t IF1MCTR; - uint8_t RESERVED1[2]; - union { - __IO uint32_t IF1DTA_L; - struct { - __IO uint16_t IF1DTA1_L; - __IO uint16_t IF1DTA2_L; - }; - }; - union { - __IO uint32_t IF1DTB_L; - struct { - __IO uint16_t IF1DTB1_L; - __IO uint16_t IF1DTB2_L; - }; - }; - uint8_t RESERVED2[8]; - union { - __IO uint32_t IF1DTA_B; - struct { - __IO uint16_t IF1DTA2_B; - __IO uint16_t IF1DTA1_B; - }; - }; - union { - __IO uint32_t IF1DTB_B; - struct { - __IO uint16_t IF1DTB2_B; - __IO uint16_t IF1DTB1_B; - }; - }; - uint8_t RESERVED3[8]; - __IO uint16_t IF2CREQ; - __IO uint16_t IF2CMSK; - union { - __IO uint32_t IF2MSK; - struct { - __IO uint16_t IF2MSK1; - __IO uint16_t IF2MSK2; - }; - }; - union { - __IO uint32_t IF2ARB; - struct { - __IO uint16_t IF2ARB1; - __IO uint16_t IF2ARB2; - }; - }; - __IO uint16_t IF2MCTR; - uint8_t RESERVED4[2]; - union { - __IO uint32_t IF2DTA_L; - struct { - __IO uint16_t IF2DTA1_L; - __IO uint16_t IF2DTA2_L; - }; - }; - union { - __IO uint32_t IF2DTB_L; - struct { - __IO uint16_t IF2DTB1_L; - __IO uint16_t IF2DTB2_L; - }; - }; - uint8_t RESERVED5[8]; - union { - __IO uint32_t IF2DTA_B; - struct { - __IO uint16_t IF2DTA2_B; - __IO uint16_t IF2DTA1_B; - }; - }; - union { - __IO uint32_t IF2DTB_B; - struct { - __IO uint16_t IF2DTB2_B; - __IO uint16_t IF2DTB1_B; - }; - }; - uint8_t RESERVED6[24]; - union { - __IO uint32_t TREQR; - struct { - __IO uint16_t TREQR1; - __IO uint16_t TREQR2; - }; - }; - uint8_t RESERVED7[12]; - union { - __IO uint32_t NEWDT; - struct { - __IO uint16_t NEWDT1; - __IO uint16_t NEWDT2; - }; - }; - uint8_t RESERVED8[12]; - union { - __IO uint32_t INTPND; - struct { - __IO uint16_t INTPND1; - __IO uint16_t INTPND2; - }; - }; - uint8_t RESERVED9[12]; - union { - __IO uint32_t MSGVAL; - struct { - __IO uint16_t MSGVAL1; - __IO uint16_t MSGVAL2; - }; - }; -}FM3_CAN_TypeDef; - - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ -#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ -#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ -#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ -#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ -#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ -#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ -#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ -#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ -#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ -#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ -#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ -#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ -#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ -#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ -#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ -#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ -#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ -#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ -#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ -#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ -#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ -#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ -#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ -#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ -#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ -#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ -#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ -#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ -#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ -#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ -#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ -#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ -#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ -#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ -#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE) -#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) -#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) -#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) -#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) -#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) -#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) -#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) -#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) -#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) -#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) -#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) -#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) -#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) -#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) -#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) -#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) -#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) -#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) -#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) -#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) -#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) -#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) -#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) -#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) -#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) -#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) -#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) -#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) -#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) -#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) -#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) -#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) -#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) -#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) -#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) -#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) -#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) -#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) -#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) -#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) -#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) -#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) -#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) -#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) -#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) -#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) -#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) -#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) -#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) -#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) -#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) -#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) -#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) -#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) -#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) -#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) -#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) -#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) -#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) -#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) -#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) -#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) -#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) -#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) -#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) -#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) -#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) -#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) -#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) -#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) -#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) -#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) -#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) -#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) -#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) -#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) -#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) -#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) -#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) -#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) -#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) -#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) -#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) -#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) -#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) -#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) -#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) -#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) -#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) -#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) -#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) -#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) -#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) -#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) -#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) -#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) -#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) -#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) -#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) -#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) -#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Flash interface registers */ -#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) - -/* Clock and reset registers */ -#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) -#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) - -/* Dual timer 1/2 registers */ -#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) -#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) -#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) -#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) -#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) -#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) -#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) -#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) -#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) -#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) -#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) -#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) -#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) -#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) -#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) -#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) -#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) -#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) -#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) -#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) -#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) -#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) -#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) -#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) -#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) -#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) -#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) -#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) -#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) -#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) -#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) -#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) -#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) -#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) -#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) -#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) -#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) -#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) -#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) -#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) -#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) -#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) -#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) -#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) -#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) -#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) -#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) -#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) -#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) -#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) -#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) -#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) -#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) -#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) -#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) -#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) -#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) -#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) -#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) -#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) -#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) -#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) -#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) -#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) -#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) -#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) -#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) -#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) -#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) -#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) -#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) -#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) -#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) -#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) -#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) -#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) -#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) -#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL)) -#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL)) -#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) -#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) -#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) -#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) -#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) -#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) -#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) -#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) -#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL)) -#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL)) -#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) -#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) -#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) -#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) -#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) -#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) -#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) -#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) -#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) -#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) -#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) -#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) -#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) -#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) -#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) -#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) -#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) -#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) -#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) -#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) -#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) -#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) -#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) -#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) -#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) -#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) -#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) -#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) -#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) -#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) -#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) -#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) -#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) -#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) -#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) -#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) -#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) -#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) -#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) -#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) -#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) -#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) -#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) -#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) -#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) -#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) -#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) -#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) -#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) -#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) -#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) -#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) -#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) -#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) -#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) -#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) -#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) -#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) -#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) -#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) -#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) -#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) -#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) -#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) -#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) -#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) -#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) -#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) -#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) -#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) -#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) -#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) -#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) -#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) -#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) -#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) -#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) -#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) -#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) -#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL)) -#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL)) -#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) -#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) -#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) -#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) -#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) -#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) -#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) -#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) -#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL)) -#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL)) -#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) -#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) -#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) -#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) -#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) -#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) -#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) -#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) -#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) -#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) -#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) -#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) -#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) -#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) -#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) -#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) -#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) -#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) -#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) - -/* CR trimming registers */ -#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) - -/* External interrupt registers */ -#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) -#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) -#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) -#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) -#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) -#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) -#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) -#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) -#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) -#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) -#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) -#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) -#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) -#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) -#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) -#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) -#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) -#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) -#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) -#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) -#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) -#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) -#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) -#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) -#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) -#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) -#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) -#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) -#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) - -/* General purpose I/O registers */ -#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) -#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) -#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) -#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) -#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) -#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) -#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) -#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) -#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) -#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) -#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) -#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) -#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) -#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) -#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) -#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) -#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) -#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) -#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) -#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) -#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) -#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) -#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) -#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) -#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) -#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) -#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) -#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) -#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) -#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) -#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) -#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) -#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) -#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) -#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) -#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) -#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) -#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) -#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) -#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) -#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) -#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) -#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) -#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) -#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) -#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) -#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) -#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) -#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) -#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) -#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) -#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) -#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) -#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) -#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) -#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) -#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) -#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) -#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) -#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) -#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) -#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) -#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) -#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) -#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) -#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) -#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) -#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) -#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) -#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) -#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) -#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) -#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) -#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) -#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) -#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) -#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) -#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) -#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) -#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) -#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) -#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) -#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) -#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) -#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) -#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) -#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) -#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) -#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) -#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) -#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) -#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) -#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) -#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) -#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) -#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) -#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) -#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) -#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) -#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) -#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) -#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) -#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) -#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) -#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) -#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) -#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) -#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) -#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) -#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) -#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) -#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) -#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) -#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) -#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) -#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) -#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) -#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) -#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) -#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) -#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) -#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) -#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) -#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) -#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) -#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) -#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) -#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) -#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) -#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) -#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) -#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) -#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) -#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) -#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) -#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) -#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) -#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) -#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) -#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) -#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) -#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) -#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) -#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) -#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) -#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) -#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) -#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) -#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) -#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) -#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) -#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) -#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) -#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) -#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) -#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) -#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) -#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) -#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) -#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) -#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) -#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) -#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) -#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) -#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) -#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) -#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) -#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) -#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) -#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) -#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) -#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) -#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) -#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) -#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) -#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) -#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) -#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) -#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) -#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) -#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) -#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) -#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) -#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) -#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) -#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) -#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) -#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) -#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) -#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) -#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) -#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) -#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) -#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) -#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) -#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) -#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) -#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) -#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) -#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) -#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) -#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) -#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) -#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) -#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) -#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) -#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) -#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) -#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) -#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) -#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) -#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) -#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) -#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) -#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) -#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) -#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) -#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) -#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) -#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) -#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) -#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) -#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) -#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) -#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) -#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) -#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) -#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) -#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) -#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) -#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) -#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) -#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) -#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) -#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) -#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) -#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) -#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) -#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) -#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) -#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) -#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) -#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) -#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) -#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) -#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) -#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) -#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) -#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) -#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) -#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) -#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) -#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) -#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) -#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) -#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) -#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) -#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) -#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) -#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) -#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) -#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) -#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) -#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) -#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) -#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) -#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) -#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) -#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) -#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) -#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) -#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) -#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) -#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) -#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) -#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) -#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) -#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) -#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) -#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) -#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) -#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) -#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) -#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) -#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) -#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) -#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) -#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) -#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) -#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) -#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) -#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) -#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) -#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) -#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) -#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) -#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) -#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) -#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) -#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) -#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) -#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) -#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) -#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) -#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) -#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) -#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) -#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) -#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) -#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) -#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) -#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) -#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) -#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) -#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) -#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) -#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) -#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) -#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) -#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) -#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) -#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) -#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) -#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) -#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) -#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) -#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) -#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) -#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) -#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) -#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) -#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) -#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) -#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) -#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) -#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) -#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) -#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) -#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) -#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) -#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) -#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) -#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) -#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) -#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) -#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) -#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) -#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) -#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) -#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) -#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) -#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) -#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) -#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) -#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) -#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) -#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) -#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) -#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) -#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) -#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) -#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) -#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) -#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) -#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) -#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) -#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) -#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) -#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) -#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) -#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) -#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) -#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) -#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) -#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) -#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) -#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) -#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) -#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) -#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) -#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) -#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) -#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) -#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) -#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) -#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) -#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) -#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) -#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) -#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) -#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) -#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) -#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) -#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) -#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) -#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) -#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) -#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) -#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) -#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) -#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) -#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) -#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) -#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) -#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) -#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) -#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) -#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) -#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) -#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) -#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) -#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) -#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) -#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) -#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) -#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) -#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) -#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) -#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) -#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) -#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) -#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) -#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) -#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) -#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) -#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) -#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) -#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) -#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) -#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) -#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) -#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) -#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) -#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) -#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) -#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) -#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) -#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) -#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) -#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) -#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) -#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) -#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) -#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) -#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) -#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) -#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) -#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) -#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) -#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) -#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) -#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) -#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) -#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) -#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) -#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) -#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) -#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) -#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) -#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) -#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) -#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) -#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) -#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) -#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) -#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) -#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) -#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) -#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) -#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) -#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) -#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) -#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) -#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) -#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) -#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) -#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) -#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) -#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) -#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) -#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) -#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) -#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) -#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) -#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) -#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) -#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) -#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) -#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) -#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) -#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) -#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) -#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) -#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) -#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) -#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) -#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) -#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) -#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) -#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) -#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) -#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) -#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) -#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) -#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) -#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) -#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) -#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) -#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) -#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) -#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) -#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) -#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) -#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) -#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) -#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) -#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) -#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) -#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) -#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) -#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) -#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) -#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) -#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) -#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) -#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) -#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) -#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) -#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) -#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) -#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) -#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) -#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) -#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) -#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) -#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) -#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) -#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) -#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) -#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) -#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) -#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) -#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) -#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) -#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) -#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) -#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) -#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) -#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) -#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) -#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) -#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) -#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) -#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) -#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) -#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) -#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) -#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) -#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) -#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) -#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) -#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) -#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) -#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) -#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) -#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) -#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) -#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) -#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) -#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) -#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) -#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) -#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) -#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) -#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) -#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) -#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) -#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) -#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) -#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) -#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) -#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) -#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) -#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) -#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) -#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) -#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) -#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) -#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) -#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) -#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) -#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) -#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) -#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) -#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) -#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) -#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) -#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) -#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) -#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) -#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) -#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) -#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) -#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) -#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) -#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) -#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) -#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) -#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) -#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) -#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) -#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) -#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) -#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) -#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) -#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) -#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) -#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) -#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) -#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) -#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) -#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) -#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) -#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) -#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) -#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) -#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) -#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) -#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) -#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) -#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) -#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) -#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) -#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) -#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) -#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) -#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) -#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) -#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) -#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) -#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) -#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) -#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) -#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) -#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) -#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) -#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) -#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) -#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) -#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) -#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) -#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) -#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) -#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) -#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) -#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) -#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) -#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) -#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) -#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) -#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) -#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) -#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) -#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) -#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) -#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) -#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) -#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) -#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) -#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) -#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) -#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) -#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) -#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) -#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) -#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) -#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) -#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) -#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) -#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) -#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) -#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) -#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) -#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) -#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) -#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) -#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) -#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) -#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) -#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) -#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) -#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) -#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) -#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) -#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) -#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) -#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) -#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) -#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) -#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) -#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) -#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) -#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) -#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) -#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) -#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) -#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) -#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) -#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) -#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) -#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) -#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) -#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) -#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) -#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) -#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) -#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) -#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) -#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) -#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) -#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) -#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) -#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) -#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) -#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) -#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) -#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) -#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) -#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) -#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) -#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) -#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) -#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) -#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) -#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) -#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) -#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) -#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) -#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) -#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) -#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) -#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) -#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) -#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) - -/* Low voltage detection registers */ -#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* USB clock registers */ -#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) -#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) -#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) - -/* CAN prescaler register */ -#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) -#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) -#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) -#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) - -/* UART asynchronous channel 0 registers */ -#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* UART synchronous channel 0 registers */ -#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) - -/* UART LIN channel 0 registers */ -#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* I2C channel 0 registers */ -#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) - -/* UART asynchronous channel 1 registers */ -#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* UART synchronous channel 1 registers */ -#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) - -/* UART LIN channel 1 registers */ -#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* I2C channel 1 registers */ -#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) - -/* UART asynchronous channel 2 registers */ -#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* UART synchronous channel 2 registers */ -#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) - -/* UART LIN channel 2 registers */ -#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* I2C channel 2 registers */ -#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) - -/* UART asynchronous channel 3 registers */ -#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* UART synchronous channel 3 registers */ -#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) - -/* UART LIN channel 3 registers */ -#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* I2C channel 3 registers */ -#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) - -/* UART asynchronous channel 4 registers */ -#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART synchronous channel 4 registers */ -#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* UART LIN channel 4 registers */ -#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* I2C channel 4 registers */ -#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* UART asynchronous channel 5 registers */ -#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART synchronous channel 5 registers */ -#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* UART LIN channel 5 registers */ -#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* I2C channel 5 registers */ -#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* UART asynchronous channel 6 registers */ -#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART synchronous channel 6 registers */ -#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* UART LIN channel 6 registers */ -#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* I2C channel 6 registers */ -#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* UART asynchronous channel 7 registers */ -#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART synchronous channel 7 registers */ -#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* UART LIN channel 7 registers */ -#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* I2C channel 7 registers */ -#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* CRC registers */ -#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* External bus interface registers */ -#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) -#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) -#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) -#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) -#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) -#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) -#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) -#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) -#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) -#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) -#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) -#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) -#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) -#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) -#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) -#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) -#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) -#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) -#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) -#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) -#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) -#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) -#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) -#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) -#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) -#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) -#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) -#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) -#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) -#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) -#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) -#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) -#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) -#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) -#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) -#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) -#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) -#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) -#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) -#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) -#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) -#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) -#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) -#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) -#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) -#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) -#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) -#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) -#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) -#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) -#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) -#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) -#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) -#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) -#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) -#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) -#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) -#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) -#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) -#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) -#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) -#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) -#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) -#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) -#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) -#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) -#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) -#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) -#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) -#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) -#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) -#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) -#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) -#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) -#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) -#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) -#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) -#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) -#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) -#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) -#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) -#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) -#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) -#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) -#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) -#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) -#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) -#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) -#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) -#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) -#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) -#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) -#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) -#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) -#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) -#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) -#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) -#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) -#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) -#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) -#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) -#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) -#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) -#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) -#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) -#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) -#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) -#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) -#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) -#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) -#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) -#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) -#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) -#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) -#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) -#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) -#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) -#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) -#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) -#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) -#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) -#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) -#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) -#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) -#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) -#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) -#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) -#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) -#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) -#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) -#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) -#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) -#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) -#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) -#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) -#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) -#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) -#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) -#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) -#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) -#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) -#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) -#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) -#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) -#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) -#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) -#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) -#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) -#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) -#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) -#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) -#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) -#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) -#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) -#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) -#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) -#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) -#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) -#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) -#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) -#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) -#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) -#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) -#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) -#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) -#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) -#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) -#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) -#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) -#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) -#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) -#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) - -/* USB channel 0 registers */ -#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* DMA controller */ -#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* CAN channel 0 registers */ -#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) -#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) -#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) -#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) -#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) -#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) -#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) -#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) -#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) -#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) -#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) -#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) -#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) -#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) -#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) -#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) -#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) -#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) -#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) -#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) -#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) -#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) -#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) -#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) -#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) -#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) -#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) -#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) -#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) -#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) -#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) -#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) -#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) -#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) -#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) -#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) -#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) -#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) -#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) -#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) -#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) -#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) -#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) -#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) -#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) -#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) -#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) -#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) -#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) -#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) -#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) -#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) -#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) -#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) -#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) -#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) -#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) -#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) -#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) -#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) -#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) -#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) -#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) -#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) -#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) -#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) -#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) -#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) -#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) -#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) -#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) -#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) -#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) -#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) -#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) -#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) -#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) -#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) -#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) -#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) -#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) -#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) -#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) -#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) -#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) -#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) -#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) -#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) -#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) -#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) -#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) -#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) -#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) -#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) -#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) -#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) -#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) -#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) -#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) -#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) -#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) -#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) -#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) -#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) -#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) -#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) -#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) -#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) -#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) -#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) -#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) -#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) -#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) -#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) -#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) - -/* CAN channel 1 registers */ -#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) -#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) -#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) -#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) -#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) -#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) -#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) -#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) -#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) -#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) -#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) -#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) -#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) -#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) -#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) -#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) -#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) -#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) -#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) -#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) -#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) -#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) -#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) -#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) -#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) -#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) -#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) -#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) -#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) -#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) -#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) -#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) -#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) -#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) -#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) -#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) -#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) -#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) -#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) -#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) -#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) -#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) -#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) -#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) -#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) -#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) -#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) -#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) -#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) -#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) -#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) -#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) -#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) -#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) -#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) -#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) -#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) -#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) -#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) -#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) -#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) -#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) -#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) -#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) -#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) -#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) -#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) -#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) -#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) -#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) -#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) -#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) -#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) -#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) -#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) -#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) -#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) -#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) -#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) -#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) -#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) -#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) -#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) -#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) -#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) -#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) -#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) -#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) -#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) -#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) -#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) -#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) -#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) -#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) -#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) -#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) -#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) -#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) -#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) -#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) -#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) -#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) -#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) -#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) -#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) -#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) -#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) -#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) -#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) -#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) -#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) -#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) -#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) -#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) -#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9BF506R_H_ */ - diff --git a/bsp/mb9bf500r/CMSIS/start_gcc.S b/bsp/mb9bf500r/CMSIS/start_gcc.S deleted file mode 100644 index 8789adb8f6..0000000000 --- a/bsp/mb9bf500r/CMSIS/start_gcc.S +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-07-01 lgnq first version - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -// .equ Initial_spTop, 0x20000200 -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* restore original stack pointer */ - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - .word CSV_IRQHandler - .word SWDT_IRQHandler - .word LVD_IRQHandler - .word WFG_IRQHandler - .word EXINT0_7_IRQHandler - .word EXINT8_15_IRQHandler - .word DTIM_QDU_IRQHandler - .word MFS0RX_IRQHandler - .word MFS0TX_IRQHandler - .word MFS1RX_IRQHandler - .word MFS1TX_IRQHandler - .word MFS2RX_IRQHandler - .word MFS2TX_IRQHandler - .word MFS3RX_IRQHandler - .word MFS3TX_IRQHandler - .word MFS4RX_IRQHandler - .word MFS4TX_IRQHandler - .word MFS5RX_IRQHandler - .word MFS5TX_IRQHandler - .word MFS6RX_IRQHandler - .word MFS6TX_IRQHandler - .word MFS7RX_IRQHandler - .word MFS7TX_IRQHandler - .word PPG_IRQHandler - .word OSC_PLL_WC_IRQHandler - .word ADC0_IRQHandler - .word ADC1_IRQHandler - .word ADC2_IRQHandler - .word FRTIM_IRQHandler - .word INCAP_IRQHandler - .word OUTCOMP_IRQHandler - .word BTIM_IRQHandler - .word CAN0_IRQHandler - .word CAN1_IRQHandler - .word USBF_IRQHandler - .word USBF_USBH_IRQHandler - .word RESERVED_1_IRQHandler - .word RESERVED_2_IRQHandler - .word DMAC0_IRQHandler - .word DMAC1_IRQHandler - .word DMAC2_IRQHandler - .word DMAC3_IRQHandler - .word DMAC4_IRQHandler - .word DMAC5_IRQHandler - .word DMAC6_IRQHandler - .word DMAC7_IRQHandler - .word RESERVED_3_IRQHandler - .word RESERVED_4_IRQHandler - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak CSV_IRQHandler - .thumb_set CSV_IRQHandler,Default_Handler - - .weak SWDT_IRQHandler - .thumb_set SWDT_IRQHandler,Default_Handler - - .weak LVD_IRQHandler - .thumb_set LVD_IRQHandler,Default_Handler - - .weak WFG_IRQHandler - .thumb_set WFG_IRQHandler,Default_Handler - - .weak EXINT0_7_IRQHandler - .thumb_set EXINT0_7_IRQHandler,Default_Handler - - .weak EXINT8_15_IRQHandler - .thumb_set EXINT8_15_IRQHandler,Default_Handler - - .weak DTIM_QDU_IRQHandler - .thumb_set DTIM_QDU_IRQHandler,Default_Handler - - .weak MFS0RX_IRQHandler - .thumb_set MFS0RX_IRQHandler,Default_Handler - - .weak MFS0TX_IRQHandler - .thumb_set MFS0TX_IRQHandler,Default_Handler - - .weak MFS1RX_IRQHandler - .thumb_set MFS1RX_IRQHandler,Default_Handler - - .weak MFS1TX_IRQHandler - .thumb_set MFS1TX_IRQHandler,Default_Handler - - .weak MFS2RX_IRQHandler - .thumb_set MFS2RX_IRQHandler,Default_Handler - - .weak MFS2TX_IRQHandler - .thumb_set MFS2TX_IRQHandler,Default_Handler - - .weak MFS3RX_IRQHandler - .thumb_set MFS3RX_IRQHandler,Default_Handler - - .weak MFS3TX_IRQHandler - .thumb_set MFS3TX_IRQHandler,Default_Handler - - .weak MFS4RX_IRQHandler - .thumb_set MFS4RX_IRQHandler,Default_Handler - - .weak MFS4TX_IRQHandler - .thumb_set MFS4TX_IRQHandler,Default_Handler - - .weak MFS5RX_IRQHandler - .thumb_set MFS5RX_IRQHandler,Default_Handler - - .weak MFS5TX_IRQHandler - .thumb_set MFS5TX_IRQHandler,Default_Handler - - .weak MFS6RX_IRQHandler - .thumb_set MFS6RX_IRQHandler,Default_Handler - - .weak MFS6TX_IRQHandler - .thumb_set MFS6TX_IRQHandler,Default_Handler - - .weak MFS7RX_IRQHandler - .thumb_set MFS7RX_IRQHandler,Default_Handler - - .weak MFS7TX_IRQHandler - .thumb_set MFS7TX_IRQHandler,Default_Handler - - .weak PPG_IRQHandler - .thumb_set PPG_IRQHandler,Default_Handler - - .weak OSC_PLL_WC_IRQHandler - .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler - - .weak ADC0_IRQHandler - .thumb_set ADC0_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak ADC2_IRQHandler - .thumb_set ADC2_IRQHandler,Default_Handler - - .weak FRTIM_IRQHandler - .thumb_set FRTIM_IRQHandler,Default_Handler - - .weak INCAP_IRQHandler - .thumb_set INCAP_IRQHandler,Default_Handler - - .weak OUTCOMP_IRQHandler - .thumb_set OUTCOMP_IRQHandler,Default_Handler - - .weak BTIM_IRQHandler - .thumb_set BTIM_IRQHandler,Default_Handler - - .weak CAN0_IRQHandler - .thumb_set CAN0_IRQHandler,Default_Handler - - .weak CAN1_IRQHandler - .thumb_set CAN1_IRQHandler,Default_Handler - - .weak USBF_IRQHandler - .thumb_set USBF_IRQHandler,Default_Handler - - .weak USBF_USBH_IRQHandler - .thumb_set USBF_USBH_IRQHandler,Default_Handler - - .weak RESERVED_1_IRQHandler - .thumb_set RESERVED_1_IRQHandler,Default_Handler - - .weak RESERVED_2_IRQHandler - .thumb_set RESERVED_2_IRQHandler,Default_Handler - - .weak DMAC0_IRQHandler - .thumb_set DMAC0_IRQHandler,Default_Handler - - .weak DMAC1_IRQHandler - .thumb_set DMAC1_IRQHandler,Default_Handler - - .weak DMAC2_IRQHandler - .thumb_set DMAC2_IRQHandler,Default_Handler - - .weak DMAC3_IRQHandler - .thumb_set DMAC3_IRQHandler,Default_Handler - - .weak DMAC4_IRQHandler - .thumb_set DMAC4_IRQHandler,Default_Handler - - .weak DMAC5_IRQHandler - .thumb_set DMAC5_IRQHandler,Default_Handler - - .weak DMAC6_IRQHandler - .thumb_set DMAC6_IRQHandler,Default_Handler - - .weak DMAC7_IRQHandler - .thumb_set DMAC7_IRQHandler,Default_Handler - - .weak RESERVED_3_IRQHandler - .thumb_set RESERVED_3_IRQHandler,Default_Handler - - .weak RESERVED_4_IRQHandler - .thumb_set RESERVED_4_IRQHandler,Default_Handler - diff --git a/bsp/mb9bf500r/CMSIS/start_iar.S b/bsp/mb9bf500r/CMSIS/start_iar.S deleted file mode 100644 index e60f066822..0000000000 --- a/bsp/mb9bf500r/CMSIS/start_iar.S +++ /dev/null @@ -1,359 +0,0 @@ -;/* -; * Copyright (c) 2006-2021, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; */ - -#include "rtconfig.h" - - MODULE ?cstartup - -;; ICODE is the same segment as cstartup. By placing __low_level_init -;; in the same segment, we make sure it can be reached with BL. */ - - SECTION CSTACK:DATA:NOROOT(3) - SECTION .icode:CODE:NOROOT(2) - -#ifdef RT_USING_UART2 - IMPORT MFS2RX_IRQHandler -#endif - PUBLIC __low_level_init - - PUBWEAK SystemInit_ExtMemCtl - SECTION .text:CODE:REORDER(2) - THUMB -SystemInit_ExtMemCtl - BX LR - -__low_level_init: - ;; Initialize hardware. - LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller - MOV R11, LR - BLX R0 - LDR R1, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R1 - MOV R0,#1 - ;; Return with BX to be independent of mode of caller - BX R11 - - ;; Forward declaration of sections. - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD __iar_program_start - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD CSV_IRQHandler ; Clock Super Visor - DCD SWDT_IRQHandler ; Software Watchdog Timer - DCD LVD_IRQHandler ; Low Voltage Detector - DCD WFG_IRQHandler ; Wave Form Generator - DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 - DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 - DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 -#ifdef RT_USING_UART2 - DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 -#else - DCD NULL_IRQHandler ; MultiFunction Serial ch.2 -#endif - DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 - DCD PPG_IRQHandler ; PPG - DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; ADC0 - DCD ADC1_IRQHandler ; ADC1 - DCD ADC2_IRQHandler ; ADC2 - DCD FRTIM_IRQHandler ; Free-run Timer - DCD INCAP_IRQHandler ; Input Capture - DCD OUTCOMP_IRQHandler ; Output Compare - DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; CAN ch.0 - DCD CAN1_IRQHandler ; CAN ch.1 - DCD USBF_IRQHandler ; USB Function - DCD USBF_USBH_IRQHandler ; USB Function / USB HOST - DCD RESERVED_1_IRQHandler ; Reserved_1 - DCD RESERVED_2_IRQHandler ; Reserved_2 - DCD DMAC0_IRQHandler ; DMAC ch.0 - DCD DMAC1_IRQHandler ; DMAC ch.1 - DCD DMAC2_IRQHandler ; DMAC ch.2 - DCD DMAC3_IRQHandler ; DMAC ch.3 - DCD DMAC4_IRQHandler ; DMAC ch.4 - DCD DMAC5_IRQHandler ; DMAC ch.5 - DCD DMAC6_IRQHandler ; DMAC ch.6 - DCD DMAC7_IRQHandler ; DMAC ch.7 - DCD RESERVED_3_IRQHandler ; Reserved_3 - DCD RESERVED_4_IRQHandler ; Reserved_4 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - PUBWEAK CSV_IRQHandler - SECTION .text:CODE:REORDER(1) -CSV_IRQHandler - B CSV_IRQHandler - PUBWEAK SWDT_IRQHandler - SECTION .text:CODE:REORDER(1) -SWDT_IRQHandler - B SWDT_IRQHandler - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - PUBWEAK WFG_IRQHandler - SECTION .text:CODE:REORDER(1) -WFG_IRQHandler - B WFG_IRQHandler - PUBWEAK EXINT0_7_IRQHandler - SECTION .text:CODE:REORDER(1) -EXINT0_7_IRQHandler - B EXINT0_7_IRQHandler - PUBWEAK EXINT8_15_IRQHandler - SECTION .text:CODE:REORDER(1) -EXINT8_15_IRQHandler - B EXINT8_15_IRQHandler - PUBWEAK DTIM_QDU_IRQHandler - SECTION .text:CODE:REORDER(1) -DTIM_QDU_IRQHandler - B DTIM_QDU_IRQHandler - PUBWEAK MFS0RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0RX_IRQHandler - B MFS0RX_IRQHandler - PUBWEAK MFS0TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0TX_IRQHandler - B MFS0TX_IRQHandler - PUBWEAK MFS1RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1RX_IRQHandler - B MFS1RX_IRQHandler - PUBWEAK MFS1TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1TX_IRQHandler - B MFS1TX_IRQHandler - PUBWEAK NULL_IRQHandler - SECTION .text:CODE:REORDER(1) -NULL_IRQHandler - B NULL_IRQHandler - PUBWEAK MFS2TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2TX_IRQHandler - B MFS2TX_IRQHandler - PUBWEAK MFS3RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3RX_IRQHandler - B MFS3RX_IRQHandler - PUBWEAK MFS3TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3TX_IRQHandler - B MFS3TX_IRQHandler - PUBWEAK MFS4RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4RX_IRQHandler - B MFS4RX_IRQHandler - PUBWEAK MFS4TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4TX_IRQHandler - B MFS4TX_IRQHandler - PUBWEAK MFS5RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5RX_IRQHandler - B MFS5RX_IRQHandler - PUBWEAK MFS5TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5TX_IRQHandler - B MFS5TX_IRQHandler - PUBWEAK MFS6RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6RX_IRQHandler - B MFS6RX_IRQHandler - PUBWEAK MFS6TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6TX_IRQHandler - B MFS6TX_IRQHandler - PUBWEAK MFS7RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7RX_IRQHandler - B MFS7RX_IRQHandler - PUBWEAK MFS7TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7TX_IRQHandler - B MFS7TX_IRQHandler - PUBWEAK PPG_IRQHandler - SECTION .text:CODE:REORDER(1) -PPG_IRQHandler - B PPG_IRQHandler - PUBWEAK OSC_PLL_WC_IRQHandler - SECTION .text:CODE:REORDER(1) -OSC_PLL_WC_IRQHandler - B OSC_PLL_WC_IRQHandler - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC0_IRQHandler - B ADC0_IRQHandler - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - PUBWEAK FRTIM_IRQHandler - SECTION .text:CODE:REORDER(1) -FRTIM_IRQHandler - B FRTIM_IRQHandler - PUBWEAK INCAP_IRQHandler - SECTION .text:CODE:REORDER(1) -INCAP_IRQHandler - B INCAP_IRQHandler - PUBWEAK OUTCOMP_IRQHandler - SECTION .text:CODE:REORDER(1) -OUTCOMP_IRQHandler - B OUTCOMP_IRQHandler - PUBWEAK BTIM_IRQHandler - SECTION .text:CODE:REORDER(1) -BTIM_IRQHandler - B BTIM_IRQHandler - PUBWEAK CAN0_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN0_IRQHandler - B CAN0_IRQHandler - PUBWEAK CAN1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_IRQHandler - B CAN1_IRQHandler - PUBWEAK USBF_IRQHandler - SECTION .text:CODE:REORDER(1) -USBF_IRQHandler - B USBF_IRQHandler - PUBWEAK USBF_USBH_IRQHandler - SECTION .text:CODE:REORDER(1) -USBF_USBH_IRQHandler - B USBF_USBH_IRQHandler - PUBWEAK RESERVED_1_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_1_IRQHandler - B RESERVED_1_IRQHandler - PUBWEAK RESERVED_2_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_2_IRQHandler - B RESERVED_2_IRQHandler - PUBWEAK DMAC0_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC0_IRQHandler - B DMAC0_IRQHandler - PUBWEAK DMAC1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC1_IRQHandler - B DMAC1_IRQHandler - PUBWEAK DMAC2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC2_IRQHandler - B DMAC2_IRQHandler - PUBWEAK DMAC3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC3_IRQHandler - B DMAC3_IRQHandler - PUBWEAK DMAC4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC4_IRQHandler - B DMAC4_IRQHandler - PUBWEAK DMAC5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC5_IRQHandler - B DMAC5_IRQHandler - PUBWEAK DMAC6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC6_IRQHandler - B DMAC6_IRQHandler - PUBWEAK DMAC7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC7_IRQHandler - B DMAC7_IRQHandler - PUBWEAK RESERVED_3_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_3_IRQHandler - B RESERVED_3_IRQHandler - PUBWEAK RESERVED_4_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_4_IRQHandler - B RESERVED_4_IRQHandler - - END diff --git a/bsp/mb9bf500r/CMSIS/start_rvds.S b/bsp/mb9bf500r/CMSIS/start_rvds.S deleted file mode 100644 index 451f17aa0d..0000000000 --- a/bsp/mb9bf500r/CMSIS/start_rvds.S +++ /dev/null @@ -1,287 +0,0 @@ -; /* -; * Copyright (c) 2006-2021, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2011-02-23 Bernard first implementation -; */ - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0. -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; 32: CAN ch.0 - DCD CAN1_IRQHandler ; 33: CAN ch.1 - DCD USBF_Handler ; 34: USB Function - DCD USB_Handler ; 35: USB Function / USB HOST - DCD DummyHandler ; 36: Reserved - DCD DummyHandler ; 37: Reserved - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD DummyHandler ; 46: Reserved - DCD DummyHandler ; 47: Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R1, = __initial_sp ; restore original stack pointer - MSR MSP, R1 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT CSV_Handler [WEAK] - EXPORT SWDT_Handler [WEAK] - EXPORT LVD_Handler [WEAK] - EXPORT MFT_WG_IRQHandler [WEAK] - EXPORT INT0_7_Handler [WEAK] - EXPORT INT8_15_Handler [WEAK] - EXPORT DT_Handler [WEAK] - EXPORT MFS0RX_IRQHandler [WEAK] - EXPORT MFS0TX_IRQHandler [WEAK] - EXPORT MFS1RX_IRQHandler [WEAK] - EXPORT MFS1TX_IRQHandler [WEAK] - EXPORT MFS2RX_IRQHandler [WEAK] - EXPORT MFS2TX_IRQHandler [WEAK] - EXPORT MFS3RX_IRQHandler [WEAK] - EXPORT MFS3TX_IRQHandler [WEAK] - EXPORT MFS4RX_IRQHandler [WEAK] - EXPORT MFS4TX_IRQHandler [WEAK] - EXPORT MFS5RX_IRQHandler [WEAK] - EXPORT MFS5TX_IRQHandler [WEAK] - EXPORT MFS6RX_IRQHandler [WEAK] - EXPORT MFS6TX_IRQHandler [WEAK] - EXPORT MFS7RX_IRQHandler [WEAK] - EXPORT MFS7TX_IRQHandler [WEAK] - EXPORT PPG_Handler [WEAK] - EXPORT TIM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT MFT_FRT_IRQHandler [WEAK] - EXPORT MFT_IPC_IRQHandler [WEAK] - EXPORT MFT_OPC_IRQHandler [WEAK] - EXPORT BT_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT USBF_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT DMAC0_Handler [WEAK] - EXPORT DMAC1_Handler [WEAK] - EXPORT DMAC2_Handler [WEAK] - EXPORT DMAC3_Handler [WEAK] - EXPORT DMAC4_Handler [WEAK] - EXPORT DMAC5_Handler [WEAK] - EXPORT DMAC6_Handler [WEAK] - EXPORT DMAC7_Handler [WEAK] - EXPORT DummyHandler [WEAK] - -CSV_Handler -SWDT_Handler -LVD_Handler -MFT_WG_IRQHandler -INT0_7_Handler -INT8_15_Handler -DT_Handler -MFS0RX_IRQHandler -MFS0TX_IRQHandler -MFS1RX_IRQHandler -MFS1TX_IRQHandler -MFS2RX_IRQHandler -MFS2TX_IRQHandler -MFS3RX_IRQHandler -MFS3TX_IRQHandler -MFS4RX_IRQHandler -MFS4TX_IRQHandler -MFS5RX_IRQHandler -MFS5TX_IRQHandler -MFS6RX_IRQHandler -MFS6TX_IRQHandler -MFS7RX_IRQHandler -MFS7TX_IRQHandler -PPG_Handler -TIM_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -MFT_FRT_IRQHandler -MFT_IPC_IRQHandler -MFT_OPC_IRQHandler -BT_IRQHandler -CAN0_IRQHandler -CAN1_IRQHandler -USBF_Handler -USB_Handler -DMAC0_Handler -DMAC1_Handler -DMAC2_Handler -DMAC3_Handler -DMAC4_Handler -DMAC5_Handler -DMAC6_Handler -DMAC7_Handler -DummyHandler - B . - ENDP - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - ENDIF - - END diff --git a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c deleted file mode 100644 index 12f9772e9f..0000000000 --- a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c +++ /dev/null @@ -1,111 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user’s obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intention and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.4) */ -/************************************************************************/ - -#include "mb9bf506r.h" - -/* - * 80MHz : Master Clock - */ -const uint32_t SystemFrequency = 80000000UL; - -uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */ -uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */ -uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */ -uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */ -uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */ - -/* - * Prototype of internal function - */ -static void ClockInit(void); -static void HwwdtDisable(void); - - -/* - * Setup the microcontroller system - */ -void SystemInit (void) -{ - HwwdtDisable(); /* Disable Hardware Watchdog */ - ClockInit(); /* Initialize Clock */ -} -/* - * Initialize Clock - */ -static void ClockInit(void) -{ - /*set Main clock stabilization - wait time to 2ms*/ - FM3_CRG->CSW_TMR = 0x79; - /*Enable Main Oscilator*/ - FM3_CRG->SCM_CTL |= 1<<1; - /*Wait stabilization end*/ - while(!(FM3_CRG->SCM_STR & 0x02)); - - /* sub CLK enable */ - //FM3_CRG->SCM_CTL |= 0x08; - //while(!(FM3_CRG->SCM_STR & 0x08)); - - /*Set PLL stabilization - wait time to 512uS*/ - FM3_CRG->PSW_TMR |= 2; - /*Set PLL to 80MHz*/ - FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/ - FM3_CRG->PLL_CTL2 = 19; /*N = 20*/ - /*Enable PLL*/ - FM3_CRG->SCM_CTL |= 0x10; - /*Set bus prescalers*/ - FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/ - FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/ - FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/ - FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/ - /*Wait PLL stabilizatoin end*/ - while(!(FM3_CRG->SCM_STR & 0x10)); - /*Select PLL for main clock*/ - FM3_CRG->SCM_CTL |= 2<<5; - /*Wait PLL to be connected*/ - while((FM3_CRG->SCM_STR & 0xe0) != 0x40); - -} -/* - * Stop HW Watchdog Timer - */ -static void HwwdtDisable(void) -{ - /* UnLock (except WDG_CTL) */ - FM3_HWWDT->WDG_LCK = 0x1ACCE551; - /* UnLock (WDG_CTL) */ - FM3_HWWDT->WDG_LCK = 0xE5331AAE; - /* Disable WDG */ - FM3_HWWDT->WDG_CTL = 0x00; -} diff --git a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h deleted file mode 100644 index 2750d1efcb..0000000000 --- a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h +++ /dev/null @@ -1,71 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ - -#ifndef _SYSTEM_MB9BF50X_H_ -#define _SYSTEM_MB9BF50X_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/mb9bf500r/SConscript b/bsp/mb9bf500r/SConscript deleted file mode 100644 index 2679fc6ce5..0000000000 --- a/bsp/mb9bf500r/SConscript +++ /dev/null @@ -1,16 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'cpuusage.c'] -src_drv = ['adc.c', 'lcd.c', 'key.c'] - -if GetDepend('RT_USING_RTGUI'): - src_drv += ['info.c'] - -src = src_bsp + src_drv -CPPPATH = [GetCurrentDir()] -CPPDEFINES = [] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/mb9bf500r/SConstruct b/bsp/mb9bf500r/SConstruct deleted file mode 100644 index 67d8d9c3a5..0000000000 --- a/bsp/mb9bf500r/SConstruct +++ /dev/null @@ -1,37 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/CMSIS', duplicate=0) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/mb9bf500r/adc.c b/bsp/mb9bf500r/adc.c deleted file mode 100644 index 2e431e90c9..0000000000 --- a/bsp/mb9bf500r/adc.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq First version - */ - -#include -#include -#include "mb9bf506r.h" -#include "adc.h" -#include "led.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#include -#endif - -static struct rt_device adc; - -static rt_err_t rt_adc_init(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); - - if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - /* I/O setting AN08 - P18 */ - FM3_GPIO->ADE |= 0x100; - FM3_GPIO->PFR1 = 0x100; - - /* A/DC setting */ - FM3_ADC0->SCIS1 = 0x01; - FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ - FM3_ADC0->ADST1 = 0x43; - FM3_ADC0->ADCT = 0x02; - FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ - FM3_ADC0->CMPCR = 0x00; /* disable comparator */ - - /* starting A/DC */ - FM3_ADC0->SCCR |= 0x01; /* A/DC start */ - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - return RT_EOK; -} - -static rt_err_t rt_adc_control(rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_ADC_START: - FM3_ADC0->SCCR |= 0x1; - break; - - case RT_DEVICE_CTRL_ADC_RESULT: - while(FM3_ADC0->ADSR & 0x1) - ; - *((rt_uint16_t*)args) = FM3_ADC0->SCFD; - *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; - *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; - break; - } - return RT_EOK; -} - -extern struct rt_messagequeue mq; -extern rt_thread_t info_tid; -rt_uint16_t adc_value; -static void adc_thread_entry(void *parameter) -{ - rt_device_t device; - -#ifdef RT_USING_RTGUI - struct rtgui_event_command ecmd; - - RTGUI_EVENT_COMMAND_INIT(&ecmd); - ecmd.type = RTGUI_CMD_USER_INT; - ecmd.command_id = ADC_UPDATE; -#else - struct lcd_msg msg; -#endif - - device = rt_device_find("adc"); - - while(1) - { - rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); - rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); - pwm_update(adc_value/3); -#ifdef RT_USING_RTGUI - rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); -#else - msg.type = ADC_MSG; - msg.adc_value = adc_value; - rt_mq_send(&mq, &msg, sizeof(msg)); -#endif - rt_thread_delay(20); - } -} - -static rt_thread_t adc_thread; -void rt_hw_adc_init(void) -{ - adc.type = RT_Device_Class_Char; - adc.rx_indicate = RT_NULL; - adc.tx_complete = RT_NULL; - adc.init = rt_adc_init; - adc.open = RT_NULL; - adc.close = RT_NULL; - adc.read = RT_NULL; - adc.write = RT_NULL; - adc.control = rt_adc_control; - adc.user_data = RT_NULL; - - adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); - if(adc_thread != RT_NULL) - rt_thread_startup(adc_thread); - - /* register a character device */ - rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); -} - diff --git a/bsp/mb9bf500r/adc.h b/bsp/mb9bf500r/adc.h deleted file mode 100644 index c8846b0beb..0000000000 --- a/bsp/mb9bf500r/adc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __ADC_H__ -#define __ADC_H__ - -/* Exported constants ---------------------------------------------------------*/ -/* Exported macro -------------------------------------------------------------*/ -#define ADC_MODE_SINGLE 0x00UL -#define ADC_MODE_SCAN 0x01UL -#define ADC_MODE_TAILGATE 0x02UL - -#define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ -#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ - -#define ADC_UPDATE 0 - -/* Exported functions --------------------------------------------------------- */ -void rt_hw_adc_init(void); - -#endif /*__ADC_H__ */ diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c deleted file mode 100644 index 1cbd0c2d83..0000000000 --- a/bsp/mb9bf500r/application.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard the first version - */ - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -#include -#include "board.h" -#include "led.h" -#include "key.h" -#include "adc.h" -#include "lcd.h" -#include "cpuusage.h" - -#ifdef RT_USING_RTGUI -#include -#include -extern void rtgui_startup(); -#endif - -struct rt_messagequeue mq; -static char msg_pool[2048]; - -void rt_init_thread_entry(void *parameter) -{ - rt_device_t lcd; - - rt_hw_led_init(); - rt_hw_key_init(); - rt_hw_adc_init(); - rt_hw_lcd_init(); - rt_hw_cpu_init(); - -#ifdef RT_USING_RTGUI - extern void rtgui_system_server_init(void); - - /* find lcd device */ - lcd = rt_device_find("lcd"); - - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); - - /* init rtgui system server */ - rtgui_system_server_init(); - - /* startup rtgui */ - rtgui_startup(); -#else - { - char buf[20] = {'\0'}; - struct lcd_msg msg; - rt_device_t device; - device = rt_device_find("lcd"); - rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); - x = 1; - y = 1; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); - x = 1; - y = 20; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); - x = 1; - y = 40; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); - - while(1) - { - if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) - { - switch(msg.type) - { - case ADC_MSG: - x = 40; - y = 1; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%04d", msg.adc_value); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case CPU_MSG: - x = 40; - y = 20; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case KEY_MSG: - x = 40; - y = 40; - rt_memset(buf, 0, sizeof(buf)); - switch(msg.key) - { - case KEY_DOWN: - rt_sprintf(buf, "DOWN KEY "); - break; - case KEY_UP: - rt_sprintf(buf, "UP KEY "); - break; - case KEY_RIGHT: - rt_sprintf(buf, "RIGHT KEY"); - break; - case KEY_LEFT: - rt_sprintf(buf, "LEFT KEY "); - break; - case KEY_ENTER: - rt_sprintf(buf, "ENTER KEY"); - break; - default: - rt_sprintf(buf, "NO KEY "); - break; - } - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - } - } - } - } -#endif -} - -int rt_application_init(void) -{ - rt_thread_t init_thread; - - rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); - - init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); - if(init_thread != RT_NULL) - rt_thread_startup(init_thread); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf500r/board.c b/bsp/mb9bf500r/board.c deleted file mode 100644 index f52a5fa3a8..0000000000 --- a/bsp/mb9bf500r/board.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" -#include "core_cm3.h" - -extern const uint32_t SystemFrequency; - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** -* This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init() -{ - /* init systick */ - SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND); -} - -/*@}*/ diff --git a/bsp/mb9bf500r/board.h b/bsp/mb9bf500r/board.h deleted file mode 100644 index 2b419c759e..0000000000 --- a/bsp/mb9bf500r/board.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -//Internal SRAM memory size[Kbytes] <8-64> -//MB9BF500 : 32 -//MB9BF504 : 32 -//MB9BF505 : 48 -//MB9BF506 : 64 -#define FM3_SRAM_SIZE 32 -#define FM3_SRAM_END (0x1FFFC000 + FM3_SRAM_SIZE * 1024) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/mb9bf500r/cpuusage.c b/bsp/mb9bf500r/cpuusage.c deleted file mode 100644 index df8ba2c240..0000000000 --- a/bsp/mb9bf500r/cpuusage.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#include -#include -#include "cpuusage.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#include -#endif - -#define CPU_USAGE_CALC_TICK 10 -#define CPU_USAGE_LOOP 100 - -static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; -static rt_uint32_t total_count = 0; - -static void cpu_usage_idle_hook() -{ - rt_tick_t tick; - rt_uint32_t count; - volatile rt_uint32_t loop; - - if (total_count == 0) - { - loop = 0; - - /* get total count */ - rt_enter_critical(); - tick = rt_tick_get(); - while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - total_count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } - rt_exit_critical(); - } - - count = 0; - loop = 0; - /* get CPU usage */ - tick = rt_tick_get(); - while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } - - /* calculate major and minor */ - if (count < total_count) - { - count = total_count - count; - cpu_usage_major = (count * 100) / total_count; - cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; - } - else - { - total_count = count; - - /* no CPU usage */ - cpu_usage_major = 0; - cpu_usage_minor = 0; - } -} - -void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor) -{ - RT_ASSERT(major != RT_NULL); - RT_ASSERT(minor != RT_NULL); - - *major = cpu_usage_major; - *minor = cpu_usage_minor; -} - -void cpu_usage_init() -{ - /* set idle thread hook */ - rt_thread_idle_sethook(cpu_usage_idle_hook); -} -extern struct rt_messagequeue mq; -extern rt_thread_t info_tid; -static void cpu_thread_entry(void *parameter) -{ -#ifdef RT_USING_RTGUI - struct rtgui_event_command ecmd; - - RTGUI_EVENT_COMMAND_INIT(&ecmd); - ecmd.type = RTGUI_CMD_USER_INT; - ecmd.command_id = CPU_UPDATE; -#else - struct lcd_msg msg; -#endif - - while (1) - { -#ifdef RT_USING_RTGUI - rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); -#else - msg.type = CPU_MSG; - msg.major = cpu_usage_major; - msg.minor = cpu_usage_minor; - rt_mq_send(&mq, &msg, sizeof(msg)); -#endif - rt_thread_delay(20); - } -} - -static rt_thread_t cpu_thread; -void rt_hw_cpu_init(void) -{ - cpu_usage_init(); - cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5); - if(cpu_thread != RT_NULL) - rt_thread_startup(cpu_thread); -} diff --git a/bsp/mb9bf500r/cpuusage.h b/bsp/mb9bf500r/cpuusage.h deleted file mode 100644 index 6a53481f3f..0000000000 --- a/bsp/mb9bf500r/cpuusage.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __CPUUSAGE_H__ -#define __CPUUSAGE_H__ - -#define CPU_UPDATE 1 - -void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor); -void rt_hw_cpu_init(void); - -#endif /*__ADC_H__ */ diff --git a/bsp/mb9bf500r/fm3_easy_kit.ewp b/bsp/mb9bf500r/fm3_easy_kit.ewp deleted file mode 100644 index d51d49cf6b..0000000000 --- a/bsp/mb9bf500r/fm3_easy_kit.ewp +++ /dev/null @@ -1,2027 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - CMSIS - - $PROJ_DIR$\CMSIS\core_cm3.c - - - $PROJ_DIR$\CMSIS\start_iar.S - - - $PROJ_DIR$\CMSIS\system_mb9bf50x.c - - - - FM3 - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - Kernel - - $PROJ_DIR$\..\..\src\clock.c - - - $PROJ_DIR$\..\..\src\device.c - - - $PROJ_DIR$\..\..\src\idle.c - - - $PROJ_DIR$\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\src\irq.c - - - $PROJ_DIR$\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\src\mem.c - - - $PROJ_DIR$\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\src\object.c - - - $PROJ_DIR$\..\..\src\rtm.c - - - $PROJ_DIR$\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\src\slab.c - - - $PROJ_DIR$\..\..\src\thread.c - - - $PROJ_DIR$\..\..\src\timer.c - - - - Rtgui - - $PROJ_DIR$\..\..\components\rtgui\widgets\about_view.c - - - $PROJ_DIR$\..\..\components\rtgui\common\asc12font.c - - - $PROJ_DIR$\..\..\components\rtgui\common\asc16font.c - - - $PROJ_DIR$\..\..\components\rtgui\common\blit.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\box.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\button.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\checkbox.c - - - $PROJ_DIR$\..\..\components\rtgui\common\color.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\combobox.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\container.c - - - $PROJ_DIR$\..\..\components\rtgui\common\dc.c - - - $PROJ_DIR$\..\..\components\rtgui\common\dc_buffer.c - - - $PROJ_DIR$\..\..\components\rtgui\common\dc_client.c - - - $PROJ_DIR$\..\..\components\rtgui\common\dc_hw.c - - - $PROJ_DIR$\..\..\components\rtgui\server\driver.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\filelist_view.c - - - $PROJ_DIR$\..\..\components\rtgui\common\filerw.c - - - $PROJ_DIR$\..\..\components\rtgui\common\font.c - - - $PROJ_DIR$\..\..\components\rtgui\common\font_bmp.c - - - $PROJ_DIR$\..\..\components\rtgui\common\font_freetype.c - - - $PROJ_DIR$\..\..\components\rtgui\common\font_hz_bmp.c - - - $PROJ_DIR$\..\..\components\rtgui\common\font_hz_file.c - - - $PROJ_DIR$\..\..\components\rtgui\common\framebuffer_driver.c - - - $PROJ_DIR$\..\..\components\rtgui\common\hz12font.c - - - $PROJ_DIR$\..\..\components\rtgui\common\hz16font.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\iconbox.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_bmp.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_container.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_hdc.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_jpg.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_png.c - - - $PROJ_DIR$\..\..\components\rtgui\common\image_xpm.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\label.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\list_view.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\listbox.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\listctrl.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\menu.c - - - $PROJ_DIR$\..\..\components\rtgui\server\mouse.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\notebook.c - - - $PROJ_DIR$\..\..\components\rtgui\server\panel.c - - - $PROJ_DIR$\..\..\components\rtgui\common\pixel_driver.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\progressbar.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\radiobox.c - - - $PROJ_DIR$\..\..\components\rtgui\common\region.c - - - $PROJ_DIR$\..\..\components\rtgui\common\rtgui_object.c - - - $PROJ_DIR$\..\..\components\rtgui\common\rtgui_system.c - - - $PROJ_DIR$\..\..\components\rtgui\common\rtgui_theme.c - - - $PROJ_DIR$\..\..\components\rtgui\common\rtgui_xml.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\scrollbar.c - - - $PROJ_DIR$\..\..\components\rtgui\server\server.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\slider.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\staticline.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\textbox.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\textview.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\title.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\toplevel.c - - - $PROJ_DIR$\..\..\components\rtgui\server\topwin.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\view.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\widget.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\window.c - - - $PROJ_DIR$\..\..\components\rtgui\widgets\workbench.c - - - - Startup - - $PROJ_DIR$\adc.c - - - $PROJ_DIR$\application.c - - - $PROJ_DIR$\board.c - - - $PROJ_DIR$\cpuusage.c - - - $PROJ_DIR$\info.c - - - $PROJ_DIR$\key.c - - - $PROJ_DIR$\lcd.c - - - $PROJ_DIR$\led.c - - - $PROJ_DIR$\startup.c - - - - - diff --git a/bsp/mb9bf500r/fm3_easy_kit.eww b/bsp/mb9bf500r/fm3_easy_kit.eww deleted file mode 100644 index bdaf802ebd..0000000000 --- a/bsp/mb9bf500r/fm3_easy_kit.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\fm3_easy_kit.ewp - - - - - diff --git a/bsp/mb9bf500r/fm3_rom.ld b/bsp/mb9bf500r/fm3_rom.ld deleted file mode 100644 index 3d0151d23b..0000000000 --- a/bsp/mb9bf500r/fm3_rom.ld +++ /dev/null @@ -1,133 +0,0 @@ -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x0000C000 -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/mb9bf500r/fm3_rom.sct b/bsp/mb9bf500r/fm3_rom.sct deleted file mode 100644 index f1a09f4900..0000000000 --- a/bsp/mb9bf500r/fm3_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00040000 { ; load region size_region - ER_IROM1 0x00000000 0x00040000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00004000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/mb9bf500r/font.h b/bsp/mb9bf500r/font.h deleted file mode 100644 index 92253c59c3..0000000000 --- a/bsp/mb9bf500r/font.h +++ /dev/null @@ -1,970 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#ifndef __FONT_H -#define __FONT_H - -/* Font definition */ -#define ________ 0x00 -#define _______X 0x01 -#define ______X_ 0x02 -#define ______XX 0x03 -#define _____X__ 0x04 -#define _____X_X 0x05 -#define _____XX_ 0x06 -#define _____XXX 0x07 -#define ____X___ 0x08 -#define ____X__X 0x09 -#define ____X_X_ 0x0a -#define ____X_XX 0x0b -#define ____XX__ 0x0c -#define ____XX_X 0x0d -#define ____XXX_ 0x0e -#define ____XXXX 0x0f -#define ___X____ 0x10 -#define ___X___X 0x11 -#define ___X__X_ 0x12 -#define ___X__XX 0x13 -#define ___X_X__ 0x14 -#define ___X_X_X 0x15 -#define ___X_XX_ 0x16 -#define ___X_XXX 0x17 -#define ___XX___ 0x18 -#define ___XX__X 0x19 -#define ___XX_X_ 0x1a -#define ___XX_XX 0x1b -#define ___XXX__ 0x1c -#define ___XXX_X 0x1d -#define ___XXXX_ 0x1e -#define ___XXXXX 0x1f -#define __X_____ 0x20 -#define __X____X 0x21 -#define __X___X_ 0x22 -#define __X___XX 0x23 -#define __X__X__ 0x24 -#define __X__X_X 0x25 -#define __X__XX_ 0x26 -#define __X__XXX 0x27 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-#define X_X_X_X_ 0xaa -#define X_X_X_XX 0xab -#define X_X_XX__ 0xac -#define X_X_XX_X 0xad -#define X_X_XXX_ 0xae -#define X_X_XXXX 0xaf -#define X_XX____ 0xb0 -#define X_XX___X 0xb1 -#define X_XX__X_ 0xb2 -#define X_XX__XX 0xb3 -#define X_XX_X__ 0xb4 -#define X_XX_X_X 0xb5 -#define X_XX_XX_ 0xb6 -#define X_XX_XXX 0xb7 -#define X_XXX___ 0xb8 -#define X_XXX__X 0xb9 -#define X_XXX_X_ 0xba -#define X_XXX_XX 0xbb -#define X_XXXX__ 0xbc -#define X_XXXX_X 0xbd -#define X_XXXXX_ 0xbe -#define X_XXXXXX 0xbf -#define XX______ 0xc0 -#define XX_____X 0xc1 -#define XX____X_ 0xc2 -#define XX____XX 0xc3 -#define XX___X__ 0xc4 -#define XX___X_X 0xc5 -#define XX___XX_ 0xc6 -#define XX___XXX 0xc7 -#define XX__X___ 0xc8 -#define XX__X__X 0xc9 -#define XX__X_X_ 0xca -#define XX__X_XX 0xcb -#define XX__XX__ 0xcc -#define XX__XX_X 0xcd -#define XX__XXX_ 0xce -#define XX__XXXX 0xcf -#define XX_X____ 0xd0 -#define XX_X___X 0xd1 -#define XX_X__X_ 0xd2 -#define XX_X__XX 0xd3 -#define XX_X_X__ 0xd4 -#define XX_X_X_X 0xd5 -#define XX_X_XX_ 0xd6 -#define XX_X_XXX 0xd7 -#define XX_XX___ 0xd8 -#define XX_XX__X 0xd9 -#define XX_XX_X_ 0xda -#define XX_XX_XX 0xdb -#define XX_XXX__ 0xdc -#define XX_XXX_X 0xdd -#define XX_XXXX_ 0xde -#define XX_XXXXX 0xdf -#define XXX_____ 0xe0 -#define XXX____X 0xe1 -#define XXX___X_ 0xe2 -#define XXX___XX 0xe3 -#define XXX__X__ 0xe4 -#define XXX__X_X 0xe5 -#define XXX__XX_ 0xe6 -#define XXX__XXX 0xe7 -#define XXX_X___ 0xe8 -#define XXX_X__X 0xe9 -#define XXX_X_X_ 0xea -#define XXX_X_XX 0xeb -#define XXX_XX__ 0xec -#define XXX_XX_X 0xed -#define XXX_XXX_ 0xee -#define XXX_XXXX 0xef -#define XXXX____ 0xf0 -#define XXXX___X 0xf1 -#define XXXX__X_ 0xf2 -#define XXXX__XX 0xf3 -#define XXXX_X__ 0xf4 -#define XXXX_X_X 0xf5 -#define XXXX_XX_ 0xf6 -#define XXXX_XXX 0xf7 -#define XXXXX___ 0xf8 -#define XXXXX__X 0xf9 -#define XXXXX_X_ 0xfa -#define XXXXX_XX 0xfb -#define XXXXXX__ 0xfc -#define XXXXXX_X 0xfd -#define XXXXXXX_ 0xfe -#define XXXXXXXX 0xff - - - - -const unsigned char FONTTYPE8_8[][8] = { -/* blank */ - { - ________, - ________, - ________, - ________, - ________, - ________, - ________, - ________} - -/* 0 */ - ,{ - __XXX___, - _XX_XX__, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* 1 */ - ,{ - ___XX___, - __XXX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - _XXXXXX_, - ________} - -/* 2 */ - ,{ - _XXXXX__, - XX___XX_, - _____XX_, - ___XXX__, - __XX____, - _XX__XX_, - XXXXXXX_, - ________} - -/* 3 */ - ,{ - _XXXXX__, - XX___XX_, - _____XX_, - __XXXX__, - _____XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 4 */ - ,{ - ___XXX__, - __XXXX__, - _XX_XX__, - XX__XX__, - XXXXXXX_, - ____XX__, - ___XXXX_, - ________} - -/* 5 */ - ,{ - XXXXXXX_, - XX______, - XX______, - XXXXXX__, - _____XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 6 */ - ,{ - __XXX___, - _XX_____, - XX______, - XXXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 7 */ - ,{ - XXXXXXX_, - XX___XX_, - ____XX__, - ___XX___, - __XX____, - __XX____, - __XX____, - ________} - -/* 8 */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 9 */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXXX_, - _____XX_, - ____XX__, - _XXXX___, - ________} - -/* A */ - ,{ - __XXX___, - _XX_XX__, - XX___XX_, - XXXXXXX_, - XX___XX_, - XX___XX_, - XX___XX_, - ________} - -/* B */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX__XX_, - _XX__XX_, - XXXXXX__, - ________} - -/* C */ - ,{ - __XXXX__, - _XX__XX_, - XX______, - XX______, - XX______, - _XX__XX_, - __XXXX__, - ________} - -/* D */ - ,{ - XXXXX___, - _XX_XX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - _XX_XX__, - XXXXX___, - ________} - -/* E */ - ,{ - XXXXXXX_, - _XX___X_, - _XX_X___, - _XXXX___, - _XX_X___, - _XX___X_, - XXXXXXX_, - ________} - -/* F */ - ,{ - XXXXXXX_, - _XX___X_, - _XX_X___, - _XXXX___, - _XX_X___, - _XX_____, - XXXX____, - ________} - -/* G */ - ,{ - __XXXX__, - _XX__XX_, - XX______, - XX______, - XX__XXX_, - _XX__XX_, - __XXX_X_, - ________} - -/* H */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XXXXXXX_, - XX___XX_, - XX___XX_, - XX___XX_, - ________} - -/* I */ - ,{ - __XXXX__, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* J */ - ,{ - ___XXXX_, - ____XX__, - ____XX__, - ____XX__, - XX__XX__, - XX__XX__, - _XXXX___, - ________} - -/* K */ - ,{ - XXX__XX_, - _XX__XX_, - _XX_XX__, - _XXXX___, - _XX_XX__, - _XX__XX_, - XXX__XX_, - ________} - -/* L */ - ,{ - XXXX____, - _XX_____, - _XX_____, - _XX_____, - _XX___X_, - _XX__XX_, - XXXXXXX_, - ________} - -/* M */ - ,{ - XX___XX_, - XXX_XXX_, - XXXXXXX_, - XXXXXXX_, - XX_X_XX_, - XX___XX_, - XX___XX_, - ________} - -/* N */ - ,{ - XX___XX_, - XXX__XX_, - XXXX_XX_, - XX_XXXX_, - XX__XXX_, - XX___XX_, - XX___XX_, - ________} - -/* O */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* P */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* Q */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX__XXX_, - _XXXXX__, - ____XXX_} - -/* R */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_XX__, - _XX__XX_, - XXX__XX_, - ________} - -/* S */ - ,{ - __XXXX__, - _XX__XX_, - __XX____, - ___XX___, - ____XX__, - _XX__XX_, - __XXXX__, - ________} - -/* T */ - ,{ - _XXXXXX_, - _XXXXXX_, - _X_XX_X_, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* U */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* V */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* W */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX_X_XX_, - XX_X_XX_, - XXXXXXX_, - _XX_XX__, - ________} - -/* X */ - ,{ - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - _XX_XX__, - XX___XX_, - XX___XX_, - ________} - -/* Y */ - ,{ - _XX__XX_, - _XX__XX_, - _XX__XX_, - __XXXX__, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* Z */ - ,{ - XXXXXXX_, - XX___XX_, - X___XX__, - ___XX___, - __XX__X_, - _XX__XX_, - XXXXXXX_, - ________} - -/* a */ - ,{ - ________, - ________, - _XXXX___, - ____XX__, - _XXXXX__, - XX__XX__, - _XXX_XX_, - ________} - -/* b */ - ,{ - XXX_____, - _XX_____, - _XXXXX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - XX_XXX__, - ________} - -/* c */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XX______, - XX___XX_, - _XXXXX__, - ________} - -/* d */ - ,{ - ___XXX__, - ____XX__, - _XXXXX__, - XX__XX__, - XX__XX__, - XX__XX__, - _XXX_XX_, - ________} - -/* e */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XXXXXXX_, - XX______, - _XXXXX__, - ________} - -/* f */ - ,{ - __XXXX__, - _XX__XX_, - _XX_____, - XXXXX___, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* g */ - ,{ - ________, - ________, - _XXX_XX_, - XX__XX__, - XX__XX__, - _XXXXX__, - ____XX__, - XXXXX___} - -/* h */ - ,{ - XXX_____, - _XX_____, - _XX_XX__, - _XXX_XX_, - _XX__XX_, - _XX__XX_, - XXX__XX_, - ________} - -/* i */ - ,{ - ___XX___, - ________, - __XXX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* j */ - ,{ - _____XX_, - ________, - _____XX_, - _____XX_, - _____XX_, - _XX__XX_, - _XX__XX_, - __XXXX__} - -/* k */ - ,{ - XXX_____, - _XX_____, - _XX__XX_, - _XX_XX__, - _XXXX___, - _XX_XX__, - XXX__XX_, - ________} - -/* l */ - ,{ - __XXX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* m */ - ,{ - ________, - ________, - XXX_XX__, - XXXXXXX_, - XX_X_XX_, - XX_X_XX_, - XX_X_XX_, - ________} - -/* n */ - ,{ - ________, - ________, - XX_XXX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - _XX__XX_, - ________} - -/* o */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* p */ - ,{ - ________, - ________, - XX_XXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_____, - XXXX____} - -/* q */ - ,{ - ________, - ________, - _XXX_XX_, - XX__XX__, - XX__XX__, - _XXXXX__, - ____XX__, - ___XXXX_} - -/* r */ - ,{ - ________, - ________, - XX_XXX__, - _XXX_XX_, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* s */ - ,{ - ________, - ________, - _XXXXXX_, - XX______, - _XXXXX__, - _____XX_, - XXXXXX__, - ________} - -/* t */ - ,{ - __XX____, - __XX____, - XXXXXX__, - __XX____, - __XX____, - __XX_XX_, - ___XXX__, - ________} - -/* u */ - ,{ - ________, - ________, - XX__XX__, - XX__XX__, - XX__XX__, - XX__XX__, - _XXX_XX_, - ________} - -/* v */ - ,{ - ________, - ________, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* w */ - ,{ - ________, - ________, - XX___XX_, - XX_X_XX_, - XX_X_XX_, - XXXXXXX_, - _XX_XX__, - ________} - -/* x */ - ,{ - ________, - ________, - XX___XX_, - _XX_XX__, - __XXX___, - _XX_XX__, - XX___XX_, - ________} - -/* y */ - ,{ - ________, - ________, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXXX_, - _____XX_, - XXXXXX__} - -/* z */ - ,{ - ________, - ________, - _XXXXXX_, - _X__XX__, - ___XX___, - __XX__X_, - _XXXXXX_, - ________} - -}; - -#endif /* __FONT_H */ diff --git a/bsp/mb9bf500r/info.c b/bsp/mb9bf500r/info.c deleted file mode 100644 index fcf514f1b0..0000000000 --- a/bsp/mb9bf500r/info.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#include - -#ifdef RT_USING_RTGUI -#include -#include -#include - -#include -#include - -#include "adc.h" -#include "cpuusage.h" - -extern rt_uint16_t adc_value; -static rt_uint8_t index = 0 ; -static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) -{ - if (event->type == RTGUI_EVENT_PAINT) - { - struct rtgui_dc* dc; - struct rtgui_rect rect; - - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rtgui_widget_get_rect(widget, &rect); - - rtgui_dc_fill_rect(dc, &rect); - rect.x2 -= 1; rect.y2 -= 1; - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); - rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); - - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); - rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); - - /* shrink border */ - rtgui_rect_inflate(&rect, -1); - - /* draw text */ - rtgui_widget_get_rect(widget, &rect); - rect.y1 += 25; - rtgui_dc_draw_text(dc, " FM3 Easy Kit Demo", &rect); - rect.y1 += 10; - rtgui_dc_draw_text(dc, " rt-thread / RTGUI", &rect); - rtgui_dc_end_drawing(dc, RT_TRUE); - - return RT_FALSE; - } - else if (event->type == RTGUI_EVENT_KBD) - { - struct rtgui_dc* dc; - struct rtgui_rect rect; - struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; - if (ekbd->type == RTGUI_KEYDOWN) - { - char key_str[16]; - switch (ekbd->key) - { - case RTGUIK_LEFT: - rt_sprintf(key_str, "%s", "L"); - break; - case RTGUIK_RIGHT: - rt_sprintf(key_str, "%s", "R"); - break; - case RTGUIK_DOWN: - rt_sprintf(key_str, "%s", "D"); - break; - case RTGUIK_UP: - rt_sprintf(key_str, "%s", "U"); - break; - default: - rt_sprintf(key_str, "%s", "S"); - break; - } - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rect.x1 = 118; - rect.y1 = 1; - rect.x2 = 127; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - rtgui_dc_draw_text(dc, key_str, &rect); - rtgui_dc_end_drawing(dc, RT_TRUE); - } - else if (ekbd->type == RTGUI_KEYUP) - { - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rect.x1 = 118; - rect.y1 = 1; - rect.x2 = 127; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - //rtgui_dc_draw_text(dc, key_str, &rect); - rtgui_dc_end_drawing(dc, RT_TRUE); - } - } - else if (event->type == RTGUI_EVENT_COMMAND) - { - char str[16]; - struct rtgui_dc* dc; - struct rtgui_rect rect; - struct rtgui_event_command* ecmd; - rt_uint8_t major,minor; - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - - ecmd = (struct rtgui_event_command*)event; - switch (ecmd->command_id) - { - case ADC_UPDATE: - rect.x1 = 1; - rect.y1 = 1; - rect.x2 = 117; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "ADC = %d mv", adc_value); - rtgui_dc_draw_text(dc, str, &rect); - break; - case CPU_UPDATE: - cpu_usage_get(&major, &minor); - rect.x1 = 1; - rect.y1 = 12; - rect.x2 = 127; - rect.y2 = 22; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "CPU : %d.%d%", major, minor); - rtgui_dc_draw_text(dc, str, &rect); - - rect.y1 = 23; - rect.y2 = 63; - index++; - if (index == 127) - { - index = 1; - rtgui_dc_fill_rect(dc, &rect); - } - if (major>40) - rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2); - else - rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2); - break; - } - rtgui_dc_end_drawing(dc, RT_TRUE); - } - - return rtgui_view_event_handler(widget, event); -} - -static void info_entry(void* parameter) -{ - rt_mq_t mq; - struct rtgui_view* view; - struct rtgui_workbench* workbench; - - mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); - rtgui_thread_register(rt_thread_self(), mq); - - workbench = rtgui_workbench_create("info", "workbench"); - if(workbench == RT_NULL) - return; - - view = rtgui_view_create("view"); - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; - RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black; - rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); - - rtgui_workbench_add_view(workbench, view); - /* this view can be focused */ - RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; - /* set widget focus */ - rtgui_widget_focus(RTGUI_WIDGET(view)); - - rtgui_view_show(view, RT_FALSE); - - rtgui_workbench_event_loop(workbench); - - rtgui_thread_deregister(rt_thread_self()); - rt_mq_delete(mq); -} - -rt_thread_t info_tid; -void info_init() -{ - info_tid = rt_thread_create("info", - info_entry, RT_NULL, - 2048, 25, 10); - - if (info_tid != RT_NULL) rt_thread_startup(info_tid); -} - -void rtgui_startup() -{ - rtgui_rect_t rect; - - rtgui_system_server_init(); - - /* register dock panel */ - rect.x1 = 0; - rect.y1 = 0; - rect.x2 = 128; - rect.y2 = 64; - rtgui_panel_register("info", &rect); - rtgui_panel_set_default_focused("info"); - - /*init info workbench */ - info_init(); -} - -#endif diff --git a/bsp/mb9bf500r/key.c b/bsp/mb9bf500r/key.c deleted file mode 100644 index 1886e72974..0000000000 --- a/bsp/mb9bf500r/key.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include "key.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#endif - -static void key_io_init(void) -{ - /*Select CPIO function*/ - KEY_PFR &= ~KEY_MASK; - /*Set CPIO Pull-Up function*/ - KEY_PCR |= KEY_MASK; - /*Make button pins inputs*/ - KEY_DDR &= ~KEY_MASK; -} - -static void key_thread_entry(void *parameter) -{ -#ifdef RT_USING_RTGUI - rt_time_t next_delay; - rt_uint8_t i; - - struct rtgui_event_kbd kbd_event; - - key_io_init(); - - /* init keyboard event */ - RTGUI_EVENT_KBD_INIT(&kbd_event); - kbd_event.mod = RTGUI_KMOD_NONE; - kbd_event.unicode = 0; - - while (1) - { - next_delay = RT_TICK_PER_SECOND/10; - kbd_event.key = RTGUIK_UNKNOWN; - kbd_event.type = RTGUI_KEYDOWN; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - for(i=0; ; i++) - { - rt_thread_delay( next_delay ); - if (KEY_ENTER_GETVALUE() == 0) - { - if (i>=4) - { - /* HOME key */ - kbd_event.key = RTGUIK_HOME; - next_delay = RT_TICK_PER_SECOND/5; - break; - } - } - else - { - kbd_event.key = RTGUIK_RETURN; - break; - } - } - } - - if (KEY_DOWN_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_LEFT; - } - - if (kbd_event.key != RTGUIK_UNKNOWN) - { - /* post down event */ - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - else - { - kbd_event.type = RTGUI_KEYUP; - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - /* wait next key press */ - rt_thread_delay(next_delay); - } -#else - extern struct rt_messagequeue mq; - rt_time_t next_delay; - struct lcd_msg msg; - msg.type = KEY_MSG; - - key_io_init(); - - while (1) - { - msg.key = NO_KEY; - - next_delay = RT_TICK_PER_SECOND/10; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - msg.key = KEY_ENTER; - } - - if (KEY_DOWN_GETVALUE() == 0) - { - msg.key = KEY_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - msg.key = KEY_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - msg.key = KEY_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - msg.key = KEY_LEFT; - } - - rt_mq_send(&mq, &msg, sizeof(msg)); - - /* wait next key press */ - rt_thread_delay(next_delay); - } -#endif -} - -static rt_thread_t key_thread; -void rt_hw_key_init(void) -{ - key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); - if (key_thread != RT_NULL) - rt_thread_startup(key_thread); -} diff --git a/bsp/mb9bf500r/key.h b/bsp/mb9bf500r/key.h deleted file mode 100644 index 45c044c7c0..0000000000 --- a/bsp/mb9bf500r/key.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-06 lgnq - */ -#ifndef __KEY_H__ -#define __KEY_H__ - -#include "mb9bf506r.h" - -#define KEY_DOWN (1<<0) -#define KEY_ENTER (1<<1) -#define KEY_LEFT (1<<2) -#define KEY_RIGHT (1<<3) -#define KEY_UP (1<<4) -#define NO_KEY (1<<5) - -#define KEY_MASK (KEY_DOWN | KEY_ENTER | KEY_LEFT | KEY_RIGHT | KEY_UP) -#define KEY_PFR (FM3_GPIO->PFR7) -#define KEY_PCR (FM3_GPIO->PCR7) -#define KEY_PDIR (FM3_GPIO->PDIR7) -#define KEY_DDR (FM3_GPIO->DDR7) - -#define RT_DEVICE_CTRL_KEY_SCAN 0 -#define RT_DEVICE_CTRL_KEY_STATUS 1 - -#define SET_BIT(byte, bit) ((byte) |= (1<<(bit))) -#define CLR_BIT(byte, bit) ((byte) &= ~(1<<(bit))) -#define TST_BIT(byte, bit) (((byte) & (1<<(bit)))?1:0) - -#define KEY_ENTER_GETVALUE() TST_BIT(KEY_PDIR, 1) -#define KEY_DOWN_GETVALUE() TST_BIT(KEY_PDIR, 0) -#define KEY_UP_GETVALUE() TST_BIT(KEY_PDIR, 4) -#define KEY_RIGHT_GETVALUE() TST_BIT(KEY_PDIR, 3) -#define KEY_LEFT_GETVALUE() TST_BIT(KEY_PDIR, 2) - -void rt_hw_key_init(void); - -#endif diff --git a/bsp/mb9bf500r/lcd.c b/bsp/mb9bf500r/lcd.c deleted file mode 100644 index 8b61abf2e0..0000000000 --- a/bsp/mb9bf500r/lcd.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-05 lgnq ZYMG12864C3 LCD driver - */ - -#include -#include "lcd.h" -#include "font.h" - -static struct rt_device_graphic_info _lcd_info; -static rt_uint8_t gui_disp_buf[GUI_LCM_YMAX/8][GUI_LCM_XMAX]; -const unsigned char BIT_MASK[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; -/* simple font: ' ', '0'~'9','a'~'z','A'~'Z' */ -extern const unsigned char FONTTYPE8_8[][8]; - -rt_uint32_t x; -rt_uint32_t y; - -void power_delay(void) -{ - rt_uint32_t i = 0x4ffff; - while(i--) - ; -} - -void delay(void) -{ - rt_uint8_t i = 0x8; - while(i--) - ; -} - -void reset_delay(void) -{ - rt_uint8_t i = 0xff; - while(i--) - ; -} - -void lcd_write_cmd(unsigned char command) -{ - rt_uint8_t i; - - LCD_PS_LOW(); - LCD_CS_LOW(); - LCD_CD_LOW(); - for (i=0; i<8; i++) - { - if (command & (0x80 >> i)) - LCD_DATA_HIGH(); - else - LCD_DATA_LOW(); - - LCD_CLK_LOW(); - delay(); - LCD_CLK_HIGH(); - delay(); - } - LCD_CS_HIGH(); -} - -void lcd_write_data(unsigned char data) -{ - rt_uint8_t i; - - LCD_PS_LOW(); - LCD_CS_LOW(); - LCD_CD_HIGH(); - for (i=0; i<8; i++) - { - if (data & (0x80 >> i)) - LCD_DATA_HIGH(); - else - LCD_DATA_LOW(); - - LCD_CLK_LOW(); - delay(); - LCD_CLK_HIGH(); - delay(); - } - LCD_CS_HIGH(); -} - -#ifdef RT_USING_RTGUI -#include -#include - -static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) -{ - rt_uint8_t i,j = GUI_LCM_XMAX; - rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; - - for (i=0; i> 4; - lcd_write_cmd(SET_PAGE_ADDR_0 | page); - lcd_write_cmd(SET_COLH_ADDR_0 | colh); - lcd_write_cmd(SET_COLL_ADDR_0 | coll); - lcd_write_data(gui_disp_buf[page][i]); - } -} - -const struct rtgui_graphic_driver_ops _lcd_ops = -{ - rt_hw_lcd_set_pixel, - rt_hw_lcd_get_pixel, - rt_hw_lcd_draw_hline, - rt_hw_lcd_draw_vline, - rt_hw_lcd_draw_raw_hline -}; -#endif - -void lcd_io_init() -{ - /* Release the analog input function*/ - FM3_GPIO->ADE =0x03; - /*Select CPIO function*/ - LCD_CS_PFR &= ~LCD_CS; - /*Make pin output*/ - LCD_CS_DDR |= LCD_CS; - /*Select CPIO function*/ - LCD_CD_PFR &= ~LCD_CD; - /*Make pin output*/ - LCD_CD_DDR |= LCD_CD; - /*Select CPIO function*/ - LCD_PS_PFR &= ~LCD_PS; - /*Make pin output*/ - LCD_PS_DDR |= LCD_PS; - /*Select CPIO function*/ - LCD_CLK_PFR &= ~LCD_CLK; - /*Make pin output*/ - LCD_CLK_DDR |= LCD_CLK; - /*Select CPIO function*/ - LCD_DATA_PFR &= ~LCD_DATA; - /*Make pin output*/ - LCD_DATA_DDR |= LCD_DATA; -} - -/* RT-Thread Device Interface */ -static rt_err_t rt_lcd_init (rt_device_t dev) -{ - lcd_io_init(); - - power_delay(); - lcd_write_cmd(DISPLAY_OFF); - reset_delay(); - // Resetting circuit - lcd_write_cmd(RESET_LCD); - reset_delay(); - // LCD bias setting - lcd_write_cmd(SET_LCD_BIAS_9); - reset_delay(); - // ADC selection: display from left to right - lcd_write_cmd(SET_ADC_NORMAL); - reset_delay(); - // Common output state selection: display from up to down - lcd_write_cmd(COM_SCAN_DIR_REVERSE); - reset_delay(); - - lcd_write_cmd(POWER_BOOSTER_ON); - power_delay(); // 50ms requried - lcd_write_cmd(POWER_REGULATOR_ON); - power_delay(); // 50ms - lcd_write_cmd(POWER_FOLLOWER_ON); - power_delay(); // 50ms - - // Setting the built-in resistance radio for regulation of the V0 voltage - // Electronic volume control - // Power control setting - lcd_write_cmd(SET_ELECVOL_REG|0x05); - delay(); - lcd_write_cmd(SET_ELECVOL_MODE); - delay(); - lcd_write_cmd(SET_ELECVOL_REG); - delay(); - // LCD_Clear(); - delay(); - lcd_write_cmd(SET_PAGE_ADDR_0); - delay(); - lcd_write_cmd(SET_COLH_ADDR_0); - delay(); - lcd_write_cmd(SET_COLL_ADDR_0); - delay(); - lcd_write_cmd(DISPLAY_ON); - delay(); - - lcd_write_cmd(DISPLAY_ALL_ON); - delay(); - lcd_write_cmd(DISPLAY_OFF); - delay(); - lcd_write_cmd(DISPLAY_ON); - delay(); - lcd_write_cmd(DISPLAY_ALL_NORMAL); - delay(); - - return RT_EOK; -} - -/******************************************************************************* -* Function Name : LCD_FillAll -* Description : Fill the whole LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_FillAll(unsigned char* buffer) -{ - unsigned char i,j = GUI_LCM_XMAX; - unsigned char* p = buffer; - - for (i=0; i> 4; - - lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. - lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr - lcd_write_cmd(SET_COLL_ADDR_0 | coll); - lcd_write_data(gui_disp_buf[page][x]); -} - -/**************************************************************************** -* Function Name : LCD_PutChar -* Description : output a char to screen - (the char only can be ' ','0'~'9','A'~'Z','a'~'z') -* Input : x X-coordinate - y Y-coordinate - ch character -* Output : None -* Return : 1 Success - 0 Fail -****************************************************************************/ -unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) -{ - unsigned char data; - unsigned char i, j; - - if( x >=(GUI_LCM_XMAX-8) ) return(0); - if( y >=(GUI_LCM_YMAX-8) ) return(0); - - if(ch == 0x20) - ch -= 0x20; - else if((ch >= 0x30)&&(ch <= 0x39)) - ch -= 0x2f; - else if((ch >= 0x41)&&(ch <= 0x5a)) - ch -= 0x36; - else if((ch >= 0x61)&&(ch <= 0x7a)) - ch -= 0x3C; - else - return(0); - - for(i = 0; i < 8; i++) - { - data = FONTTYPE8_8[ch][i]; - - for(j = 0; j < 8; j++) - { - if( (data&BIT_MASK[j]) == 0) - gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); - else - gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); - LCD_UpdatePoint(x, y); - x ++; - } - x -= 8; - y++; - } - - return(1); -} - -/**************************************************************************** -* Function Name : LCD_PutString -* Description : output string to screen -* Input : x X-coordinate - y Y-coordinate - str pointer to string -* Output : None -* Return : None -****************************************************************************/ -void LCD_PutString(unsigned long x, unsigned long y, char *str) -{ - while(1) - { - if( (*str)=='\0' ) break; - if( LCD_PutChar(x, y, *str++) == 0 ) break; - x += 6; - } -} - -static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) -{ - switch (cmd) - { -#ifdef RT_USING_RTGUI - case RTGRAPHIC_CTRL_RECT_UPDATE: - rt_hw_lcd_update(args); - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; -#else - case RT_DEVICE_CTRL_LCD_DISPLAY_ON: - lcd_write_cmd(DISPLAY_ON); - break; - case RT_DEVICE_CTRL_LCD_DISPLAY_OFF: - lcd_write_cmd(DISPLAY_OFF); - break; - case RT_DEVICE_CTRL_LCD_PUT_STRING: - LCD_PutString(x, y, (char*)args); - break; - case RT_DEVICE_CTRL_LCD_CLEAR_SCR: - LCD_ClearSCR(); - break; -#endif - } - - return RT_EOK; -} - -void rt_hw_lcd_init(void) -{ - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = RT_NULL; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; -#ifdef RT_USING_RTGUI - lcd->user_data = (void*)&_lcd_ops; -#endif - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); -} diff --git a/bsp/mb9bf500r/lcd.h b/bsp/mb9bf500r/lcd.h deleted file mode 100644 index e0fa9efdc3..0000000000 --- a/bsp/mb9bf500r/lcd.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2008-03-29 Yi.Qiu - * 2011-06-13 lgnq modified for FM3 easy kit - */ -#ifndef __LCD_H__ -#define __LCD_H__ - -#include -#include "mb9bf506r.h" - -/********* LCD Hardward Interface ************* -LCD_CS PORT1.7 -LCD_CD PORT1.6 -LCD_WR PORT1.5 -LCD_RD PORT1.4 -LCD_SCK PORT1.3 -LCD_MOSI PORT1.2 -LCD_C86 PORT1.1 -LCD_PS PORT1.0 -LCD_DATA[0..7] PORT5.[0..7] -***********************************************/ -#define LCD_CS (1UL << 7) -#define LCD_CS_DDR (FM3_GPIO->DDR1) -#define LCD_CS_PFR (FM3_GPIO->PFR1) -#define LCD_CS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CD (1UL << 6) -#define LCD_CD_DDR (FM3_GPIO->DDR1) -#define LCD_CD_PFR (FM3_GPIO->PFR1) -#define LCD_CD_PDOR (FM3_GPIO->PDOR1) - -#define LCD_PS (1UL << 0) -#define LCD_PS_DDR (FM3_GPIO->DDR1) -#define LCD_PS_PFR (FM3_GPIO->PFR1) -#define LCD_PS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CLK (1UL << 6) -#define LCD_CLK_DDR (FM3_GPIO->DDR5) -#define LCD_CLK_PFR (FM3_GPIO->PFR5) -#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) - -#define LCD_DATA (1UL << 7) -#define LCD_DATA_DDR (FM3_GPIO->DDR5) -#define LCD_DATA_PFR (FM3_GPIO->PFR5) -#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) - -/* LCD driver for ZYMG12864C3 */ -#define LCD_WIDTH 128 -#define LCD_HEIGHT 64 - -// Driver the LCD with Parallel or serial interface and the command/data control pin is gpio -#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS -#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS - -#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD -#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD - -#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS -#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS - -#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK -#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK - -#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA -#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA - -// define the arrtibute of ZYMG12864(LCM) -#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 -#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 -#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) - -/* set LCD command */ -#define DISPLAY_ON 0xAF // A0,RD,WR:010 -#define DISPLAY_OFF 0xAE // A0,RD,WR:010 - -#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 -#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 -#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; -#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 - -#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 -#define STATUS_BUSY 0x80 -#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n -#define STATUS_DISPLAY_OFF 0x20 -#define STATUS_RESET 0x80 - -#define WRITE_DATA 0x-- // A0,RD,WR:110 -#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable - -#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 -#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 -#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 -#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color -#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 -#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 - -/************************************************************* -* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* ---------------|----------|----------|----------|--------- * -* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * -* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * -**************************************************************/ - -#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 -#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 - -#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating -#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. -#define RESET_LCD 0xE2 // A0,RD,WR:010 - - -/************************************************************************************** -* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* --------------|-------------|-------------|-------------|------------------------ * -* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * -* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * -***************************************************************************************/ - -#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 -#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 - -// 0 0 1 0 1 | Booster On | Regulator On | Follower On -#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 -#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 -#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 - -#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large - -#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command -#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. - -#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command -#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command -#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command - -#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command -#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command -#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command -#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command - -#define COMMAND_NOP 0xE3 // A0,RD,WR:010 -#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use - -#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 -#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 -#define RT_DEVICE_CTRL_LCD_GET_BPP 2 -#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 -#define RT_DEVICE_CTRL_LCD_POWER_ON 4 -#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 -#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 -#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 -#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 -#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 -#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 -#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 - -enum -{ - ADC_MSG, - KEY_MSG, - CPU_MSG, - MAX_MSG, -}; - -struct lcd_msg -{ - rt_uint8_t type; - rt_uint16_t adc_value; - rt_uint8_t key; - rt_uint16_t major; - rt_uint16_t minor; -}; - -extern rt_uint32_t x; -extern rt_uint32_t y; - -void rt_hw_lcd_init(void); - -#endif diff --git a/bsp/mb9bf500r/led.c b/bsp/mb9bf500r/led.c deleted file mode 100644 index ee28af7035..0000000000 --- a/bsp/mb9bf500r/led.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include - -#include "mb9bf506r.h" -#include "led.h" - -void rt_hw_led_on(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - LED_PDOR &= ~LED1; - break; - case 2: - LED_PDOR &= ~LED2; - break; - case 3: - LED_PDOR &= ~LED3; - break; - default: - break; - } -} - -void rt_hw_led_off(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - LED_PDOR |= LED1; - break; - case 2: - LED_PDOR |= LED2; - break; - case 3: - LED_PDOR |= LED3; - break; - default: - break; - } -} - -void rt_hw_led_toggle(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - if (LED_PDOR&LED1) - LED_PDOR &= ~LED1; - else - LED_PDOR |= LED1; - break; - case 2: - if (LED_PDOR&LED2) - LED_PDOR &= ~LED2; - else - LED_PDOR |= LED2; - break; - case 3: - if (LED_PDOR&LED3) - LED_PDOR &= ~LED3; - else - LED_PDOR |= LED3; - break; - default: - break; - } -} - -static rt_err_t led_io_init(void) -{ - /*Select CPIO function*/ - LED_PFR &= ~LED_MASK; - /*Set Pin to turn off leds*/ - LED_PDOR |= LED_MASK; - /*Make led pins outputs*/ - LED_DDR |= LED_MASK; - - //LED3 is controled by PWM - FM3_GPIO->PFR3 = 0x1000; - FM3_GPIO->EPFR04 = 0x00080000; - FM3_BT2_PWM->TMCR = 0x0018; - FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ - FM3_BT2_PWM->STC = 0x00; - FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ - FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ - - FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ - return RT_EOK; -} - -void pwm_update(rt_uint16_t value) -{ - FM3_BT2_PWM->PDUT = value; -} - -static void led1_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(1); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void led2_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(2); - rt_thread_delay(RT_TICK_PER_SECOND/2); - } -} - -static rt_thread_t led1_thread; -static rt_thread_t led2_thread; -void rt_hw_led_init(void) -{ - led_io_init(); - - led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) - rt_thread_startup(led1_thread); - - led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) - rt_thread_startup(led2_thread); -} - - diff --git a/bsp/mb9bf500r/led.h b/bsp/mb9bf500r/led.h deleted file mode 100644 index c4a433cb81..0000000000 --- a/bsp/mb9bf500r/led.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __LED_H__ -#define __LED_H__ - -#include "mb9bf506r.h" - -#define LEDS_MAX_NUMBER 4 - -/*LEDs*/ -#define LED1 (1UL<<10) -#define LED2 (1UL<<11) -#define LED3 (1UL<<12) -#define LED_MASK (LED1 | LED2 | LED3) - -#define LED_PFR (FM3_GPIO->PFR3) -#define LED_DDR (FM3_GPIO->DDR3) -#define LED_PDOR (FM3_GPIO->PDOR3) - -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 - -void rt_hw_led_init(void); -void rt_hw_led_on(rt_uint8_t num); -void rt_hw_led_off(rt_uint8_t num); -void rt_hw_led_toggle(rt_uint8_t num); -void pwm_update(rt_uint16_t value); - -#endif diff --git a/bsp/mb9bf500r/mb9bf500r.icf b/bsp/mb9bf500r/mb9bf500r.icf deleted file mode 100644 index ff723823ce..0000000000 --- a/bsp/mb9bf500r/mb9bf500r.icf +++ /dev/null @@ -1,32 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/bsp/mb9bf500r/project.uvopt b/bsp/mb9bf500r/project.uvopt deleted file mode 100644 index f4ebac8267..0000000000 --- a/bsp/mb9bf500r/project.uvopt +++ /dev/null @@ -1,559 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - RT-Thread FM3 - 0x4 - ARM-ADS - - 4000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\obj\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 0 - 7 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - Startup - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 43 - 0 - 121 - 121 - 0 - .\application.c - application.c - - - 1 - 2 - 1 - 0 - 0 - 20 - 0 - 32 - 34 - 0 - .\board.c - board.c - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\startup.c - startup.c - - - 1 - 4 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\adc.c - adc.c - - - 1 - 5 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\cpuusage.c - cpuusage.c - - - 1 - 6 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\key.c - key.c - - - 1 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\lcd.c - lcd.c - - - 1 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\led.c - led.c - - - 1 - 9 - 1 - 0 - 0 - 39 - 0 - 14 - 25 - 0 - .\info.c - info.c - - - - - FM3 - 0 - 0 - 0 - - 2 - 10 - 2 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - context_rvds.S - - - 2 - 11 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\cortex-m3\cpuport.c - cpuport.c - - - - - CMSIS - 0 - 0 - 0 - - 3 - 12 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\CMSIS\core_cm3.c - core_cm3.c - - - 3 - 13 - 2 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - .\CMSIS\start_rvds.S - start_rvds.S - - - 3 - 14 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\CMSIS\system_mb9bf50x.c - system_mb9bf50x.c - - - - - Kernel - 0 - 0 - 0 - - 4 - 15 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\clock.c - clock.c - - - 4 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\device.c - device.c - - - 4 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\idle.c - idle.c - - - 4 - 18 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\ipc.c - ipc.c - - - 4 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\irq.c - irq.c - - - 4 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\kservice.c - kservice.c - - - 4 - 21 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\mem.c - mem.c - - - 4 - 22 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\mempool.c - mempool.c - - - 4 - 24 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\object.c - object.c - - - 4 - 26 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\scheduler.c - scheduler.c - - - 4 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\slab.c - slab.c - - - 4 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\thread.c - thread.c - - - 4 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\timer.c - timer.c - - - - diff --git a/bsp/mb9bf500r/project.uvproj b/bsp/mb9bf500r/project.uvproj deleted file mode 100644 index 971e04f6e1..0000000000 --- a/bsp/mb9bf500r/project.uvproj +++ /dev/null @@ -1,547 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread FM3 - 0x4 - ARM-ADS - - - MB9BF500R - Fujitsu Semiconductors - IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0003FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - - "STARTUP\FUJITSU\MB9BF50x\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BF50x_256 -FS00 -FL040000) - 5155 - MB9BF50x.h - - - - - - - - - - - 0 - - - - Fujitsu\MB9BF50x\ - Fujitsu\MB9BF50x\ - - 0 - 0 - 0 - 0 - 1 - - .\obj\ - rtthread-fm3 - 1 - 0 - 0 - 1 - 1 - .\obj\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - 0 - 7 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - CMSIS;.;..\..\include;..\..\components\rtgui\include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x10000000 - - - - - - - - - - - - Startup - - - application.c - 1 - .\application.c - - - board.c - 1 - .\board.c - - - startup.c - 1 - .\startup.c - - - adc.c - 1 - .\adc.c - - - cpuusage.c - 1 - .\cpuusage.c - - - key.c - 1 - .\key.c - - - lcd.c - 1 - .\lcd.c - - - led.c - 1 - .\led.c - - - info.c - 1 - .\info.c - - - - - FM3 - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - CMSIS - - - core_cm3.c - 1 - .\CMSIS\core_cm3.c - - - start_rvds.S - 2 - .\CMSIS\start_rvds.S - - - system_mb9bf50x.c - 1 - .\CMSIS\system_mb9bf50x.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - device.c - 1 - ..\..\src\device.c - - - idle.c - 1 - ..\..\src\idle.c - - - ipc.c - 1 - ..\..\src\ipc.c - - - irq.c - 1 - ..\..\src\irq.c - - - kservice.c - 1 - ..\..\src\kservice.c - - - mem.c - 1 - ..\..\src\mem.c - - - mempool.c - 1 - ..\..\src\mempool.c - - - object.c - 1 - ..\..\src\object.c - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - slab.c - 1 - ..\..\src\slab.c - - - thread.c - 1 - ..\..\src\thread.c - - - timer.c - 1 - ..\..\src\timer.c - - - - - - - - diff --git a/bsp/mb9bf500r/rtconfig.h b/bsp/mb9bf500r/rtconfig.h deleted file mode 100644 index ac37ecb464..0000000000 --- a/bsp/mb9bf500r/rtconfig.h +++ /dev/null @@ -1,88 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 - -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -/* #define RT_DEBUG */ -#define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ -#define RT_USING_HOOK - -/* SECTION: IPC */ -/* Using Semaphore */ -#define RT_USING_SEMAPHORE - -/* Using Mutex */ -#define RT_USING_MUTEX - -/* Using Event */ -#define RT_USING_EVENT - -/* Using MailBox */ -#define RT_USING_MAILBOX - -/* Using Message Queue */ -#define RT_USING_MESSAGEQUEUE - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ -#define RT_USING_HEAP - -/* Using Small MM */ -#define RT_USING_SMALL_MEM - -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE -/* RT_USING_UART */ -#define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 - -/* SECTION: Console options */ -#define RT_TINY_SIZE -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 - -/* SECTION: RTGUI support */ -/* using RTGUI support */ -/* #define RT_USING_RTGUI */ - -/* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT16 -/* support 12 weight font */ -#define RTGUI_USING_FONT12 -/* support Chinese font */ -//#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -//#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -/* #define RTGUI_USING_HZ_FILE */ -/* use Chinese bitmap font */ -//#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -//#define RTGUI_USING_SMALL_SIZE -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ -#define RTGUI_DEFAULT_FONT_SIZE 12 - -#endif diff --git a/bsp/mb9bf500r/rtconfig.py b/bsp/mb9bf500r/rtconfig.py deleted file mode 100644 index 24ae26d0ab..0000000000 --- a/bsp/mb9bf500r/rtconfig.py +++ /dev/null @@ -1,124 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='gcc' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' -elif CROSS_TOOL == 'iar': - print('================ERROR============================') - print('Not support iar yet!') - print('=================================================') - exit(0) - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter fm3_rom.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - CFLAGS = '' - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' - - LFLAGS = ' --config mb9bf500r.icf' - LFLAGS += ' --semihosting' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf500r/startup.c b/bsp/mb9bf500r/startup.c deleted file mode 100644 index 1e7309ae3e..0000000000 --- a/bsp/mb9bf500r/startup.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" -/** - * @addtogroup FM3 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init application */ - rt_application_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* init system setting */ - SystemInit(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf506r/SConscript b/bsp/mb9bf506r/SConscript deleted file mode 100644 index 0992612410..0000000000 --- a/bsp/mb9bf506r/SConscript +++ /dev/null @@ -1,12 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/mb9bf506r/SConstruct b/bsp/mb9bf506r/SConstruct deleted file mode 100644 index 97f374e663..0000000000 --- a/bsp/mb9bf506r/SConstruct +++ /dev/null @@ -1,35 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/mb9bf506r/applications/SConscript b/bsp/mb9bf506r/applications/SConscript deleted file mode 100644 index 4ccb177207..0000000000 --- a/bsp/mb9bf506r/applications/SConscript +++ /dev/null @@ -1,9 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf506r/applications/application.c b/bsp/mb9bf506r/applications/application.c deleted file mode 100644 index fdc42a9100..0000000000 --- a/bsp/mb9bf506r/applications/application.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-05-24 Bernard the first version - */ - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -#include -#include "board.h" -#include "led.h" - -#ifdef RT_USING_DFS -/* dfs init */ -#include -/* dfs filesystem:ELM filesystem init */ -#include -/* dfs Filesystem APIs */ -#include -#endif - -void rt_init_thread_entry(void *parameter) -{ - /* LED Initialization */ - rt_hw_led_init(); - -#ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); -#endif - - /* Filesystem Initialization */ -#ifdef RT_USING_DFS - /* mount nand fat partition 1 as root directory */ - if (dfs_mount("nand", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); -#endif -} - -int rt_application_init(void) -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c deleted file mode 100644 index ccb31d40b4..0000000000 --- a/bsp/mb9bf506r/applications/startup.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* initialize board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - -#ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_DEVICE -#if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS) - rt_hw_nand_init(); -#endif -#endif - - /* initialize application */ - rt_application_init(); - - /* initialize timer */ - rt_system_timer_init(); - - /* initialize timer thread */ - rt_system_timer_thread_init(); - - /* initialize idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf506r/drivers/SConscript b/bsp/mb9bf506r/drivers/SConscript deleted file mode 100644 index f4b66bd711..0000000000 --- a/bsp/mb9bf506r/drivers/SConscript +++ /dev/null @@ -1,16 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') - -# remove no need file. -if GetDepend('RT_USING_LWIP') == False: - SrcRemove(src, 'emac.c') -if GetDepend('RT_USING_DFS') == False: - SrcRemove(src, 'sd.c') - -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c deleted file mode 100644 index d687bea929..0000000000 --- a/bsp/mb9bf506r/drivers/board.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mcu.h" - -#include "fm3_uart.h" -#include "nand.h" - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init(void) -{ - /* init systick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - - /* initialize nand flash device */ - rt_hw_nand_init(); -} - -/*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.h b/bsp/mb9bf506r/drivers/board.h deleted file mode 100644 index d2f252990c..0000000000 --- a/bsp/mb9bf506r/drivers/board.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -//Internal SRAM memory size[Kbytes] <8-64> -//MB9BF500 : 32 -//MB9BF504 : 32 -//MB9BF505 : 48 -//MB9BF506 : 64 -#define FM3_SRAM_SIZE 64 -#define FM3_SRAM_END (0x1FFF8000 + FM3_SRAM_SIZE * 1024) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c deleted file mode 100644 index ece042cca4..0000000000 --- a/bsp/mb9bf506r/drivers/fm3_uart.c +++ /dev/null @@ -1,929 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-05-15 lgnq first version. - * 2012-05-28 heyuanjie87 change interfaces - */ - -#include -#include -#include "fm3_uart.h" - -#if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) -/* UART0 device driver structure */ -struct uart03_device uart0 = -{ - FM3_MFS0_UART, - MFS0RX_IRQn, - MFS0TX_IRQn, -}; -struct rt_serial_device serial0; - -void MFS0RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) -/* UART1 device driver structure */ -struct uart03_device uart1 = -{ - FM3_MFS1_UART, - MFS1RX_IRQn, - MFS1TX_IRQn, -}; -struct rt_serial_device serial1; - -void MFS1RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) -/* UART2 device driver structure */ -struct uart03_device uart2 = -{ - FM3_MFS2_UART, - MFS2RX_IRQn, - MFS2TX_IRQn, -}; -struct rt_serial_device serial2; - -void MFS2RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) -/* UART3 device driver structure */ -struct uart03_device uart3 = -{ - FM3_MFS3_UART, - MFS3RX_IRQn, - MFS3TX_IRQn, -}; -struct rt_serial_device serial3; - -void MFS3RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) -/* UART4 device driver structure */ -struct uart47_device uart4 = -{ - FM3_MFS4_UART, - MFS4RX_IRQn, - MFS4TX_IRQn, - FIFO_SIZE, -}; -struct rt_serial_device serial4; - -void MFS4RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) -/* UART5 device driver structure */ -struct uart47_device uart5 = -{ - FM3_MFS5_UART, - MFS5RX_IRQn, - MFS5TX_IRQn, - FIFO_SIZE, -}; -struct rt_serial_device serial5; - -void MFS5RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) -/* UART6 device driver structure */ -struct uart47_device uart6 = -{ - FM3_MFS6_UART, - MFS6RX_IRQn, - MFS6TX_IRQn, - FIFO_SIZE, -}; -struct rt_serial_device serial6; - -void MFS6RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) -/* UART7 device driver structure */ -struct uart47_device uart7 = -{ - FM3_MFS7_UART, - MFS7RX_IRQn, - MFS7TX_IRQn, - FIFO_SIZE, -}; -struct rt_serial_device serial7; - -void MFS7RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif - -void uart_pin_setup(void) -{ -#if defined(RT_USING_UART0_0) - /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ - FM3_GPIO->PFR2_f.P1 = 1; - FM3_GPIO->PFR2_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 1; - FM3_GPIO->EPFR07_f.SIN0S1 = 0; - FM3_GPIO->EPFR07_f.SOT0B0 = 1; - FM3_GPIO->EPFR07_f.SOT0B1 = 0; -#elif defined(RT_USING_UART0_1) - /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ - FM3_GPIO->PFR1_f.P4 = 1; - FM3_GPIO->PFR1_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 0; - FM3_GPIO->EPFR07_f.SIN0S1 = 1; - FM3_GPIO->EPFR07_f.SOT0B0 = 0; - FM3_GPIO->EPFR07_f.SOT0B1 = 1; -#endif - -#if defined(RT_USING_UART1_0) - /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ - FM3_GPIO->PFR5_f.P6 = 1; - FM3_GPIO->PFR5_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 1; - FM3_GPIO->EPFR07_f.SIN1S1 = 0; - FM3_GPIO->EPFR07_f.SOT1B0 = 1; - FM3_GPIO->EPFR07_f.SOT1B1 = 0; -#elif defined(RT_USING_UART1_1) - /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ - FM3_GPIO->PFR1_f.P1 = 1; - FM3_GPIO->PFR1_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 0; - FM3_GPIO->EPFR07_f.SIN1S1 = 1; - FM3_GPIO->EPFR07_f.SOT1B0 = 0; - FM3_GPIO->EPFR07_f.SOT1B1 = 1; -#endif - -#if defined(RT_USING_UART2_0) - /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ - FM3_GPIO->PFR7_f.P2 = 1; - FM3_GPIO->PFR7_f.P3 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 0; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 0; -#elif defined(RT_USING_UART2_1) - /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ - FM3_GPIO->PFR2_f.P4 = 1; - FM3_GPIO->PFR2_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 0; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 0; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; -#elif defined(RT_USING_UART2_2) - /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ - FM3_GPIO->PFR1_f.P7 = 1; - FM3_GPIO->PFR1_f.P8 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; -#endif - -#if defined(RT_USING_UART3_0) - /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ - FM3_GPIO->PFR6_f.P6 = 1; - FM3_GPIO->PFR6_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 0; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 0; -#elif defined(RT_USING_UART3_1) - /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ - FM3_GPIO->PFR5_f.P0 = 1; - FM3_GPIO->PFR5_f.P1 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 0; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 0; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; -#elif defined(RT_USING_UART3_2) - /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ - FM3_GPIO->PFR4_f.P8 = 1; - FM3_GPIO->PFR4_f.P9 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; -#endif - -#if defined(RT_USING_UART4_0) - /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ - FM3_GPIO->PFR0_f.PA = 1; - FM3_GPIO->PFR0_f.PB = 1; - FM3_GPIO->PFR0_f.PD = 1; - FM3_GPIO->PFR0_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 0; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 0; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 0; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 0; -#elif defined(RT_USING_UART4_1) - /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ - FM3_GPIO->PFR1_f.PA = 1; - FM3_GPIO->PFR1_f.PB = 1; - FM3_GPIO->PFR1_f.PD = 1; - FM3_GPIO->PFR1_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 0; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 0; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 0; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 0; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; -#elif defined(RT_USING_UART4_2) - /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ - FM3_GPIO->PFR0_f.P5 = 1; - FM3_GPIO->PFR0_f.P6 = 1; - FM3_GPIO->PFR0_f.P8 = 1; - FM3_GPIO->PFR0_f.P9 = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; -#endif - -#if defined(RT_USING_UART5_0) - /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ - FM3_GPIO->PFR6_f.P0 = 1; - FM3_GPIO->PFR6_f.P1 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 0; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 0; -#elif defined(RT_USING_UART5_1) - /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ - FM3_GPIO->PFR6_f.P3 = 1; - FM3_GPIO->PFR6_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 0; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 0; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; -#elif defined(RT_USING_UART5_2) - /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ - FM3_GPIO->PFR3_f.P6 = 1; - FM3_GPIO->PFR3_f.P7 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; -#endif - -#if defined(RT_USING_UART6_0) - /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ - FM3_GPIO->PFR5_f.P3 = 1; - FM3_GPIO->PFR5_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 1; - FM3_GPIO->EPFR08_f.SIN6S1 = 0; - FM3_GPIO->EPFR08_f.SOT6B0 = 1; - FM3_GPIO->EPFR08_f.SOT6B1 = 0; -#elif defined(RT_USING_UART6_1) - /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ - FM3_GPIO->PFR3_f.P2 = 1; - FM3_GPIO->PFR3_f.P3 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 0; - FM3_GPIO->EPFR08_f.SIN6S1 = 1; - FM3_GPIO->EPFR08_f.SOT6B0 = 0; - FM3_GPIO->EPFR08_f.SOT6B1 = 1; -#endif - -#if defined(RT_USING_UART7_0) - /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ - FM3_GPIO->PFR5_f.P9 = 1; - FM3_GPIO->PFR5_f.PA = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 1; - FM3_GPIO->EPFR08_f.SIN7S1 = 0; - FM3_GPIO->EPFR08_f.SOT7B0 = 1; - FM3_GPIO->EPFR08_f.SOT7B1 = 0; -#elif defined(RT_USING_UART7_1) - /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ - FM3_GPIO->PFR4_f.PD = 1; - FM3_GPIO->PFR4_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 0; - FM3_GPIO->EPFR08_f.SIN7S1 = 1; - FM3_GPIO->EPFR08_f.SOT7B0 = 0; - FM3_GPIO->EPFR08_f.SOT7B1 = 1; -#endif -} - -static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } - - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } - - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } - - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } - - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - return RT_EOK; -} - -static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } - - return (RT_EOK); -} - -static int uart03_putc(struct rt_serial_device *serial, char c) -{ - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* while send buffer is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to send buffer */ - uart->uart_regs->TDR = c; - - return (1); -} - -static int uart03_getc(struct rt_serial_device *serial) -{ - struct uart03_device *uart; - int ch; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* receive buffer is full */ - if (uart->uart_regs->SSR & SSR_RDRF) - { - ch = uart->uart_regs->RDR & 0xff; - return (ch); - } - else - return (-1); -} - -static struct rt_uart_ops uart03_ops = -{ - uart03_configure, - uart03_control, - uart03_putc, - uart03_getc, -}; - -static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } - - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } - - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } - - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } - - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - /* configure fifo */ - /* Disable the Data Lost detection */ - uart->uart_regs->FCR1_f.FLSTE = 0; - /* Enable the received FIFO idle detection */ - uart->uart_regs->FCR1_f.FRIE = 1; - /* Requests for the transmit FIFO data */ - uart->uart_regs->FCR1_f.FDRQ = 1; - /* Disable the transmit FIFO interrupt */ - uart->uart_regs->FCR1_f.FTIE = 0; - /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ - uart->uart_regs->FCR1_f.FSEL = 0; - - /* Transfer data count */ - uart->uart_regs->FBYTE1 = 0; - /* Set the data count to generate a received interrupt */ - uart->uart_regs->FBYTE2 = uart->fifo_size; - - /* FIFO pointer Not reloaded */ - uart->uart_regs->FCR0_f.FLD = 0; - /* FIFO pointer Not saved */ - uart->uart_regs->FCR0_f.FSET = 0; - /* FIFO2 is reset */ - uart->uart_regs->FCR0_f.FCL2 = 1; - /* FIFO1 is reset */ - uart->uart_regs->FCR0_f.FCL1 = 1; - /* Enables the FIFO2 operation */ - uart->uart_regs->FCR0_f.FE2 = 1; - /* Enables the FIFO1 operation */ - uart->uart_regs->FCR0_f.FE1 = 1; - - /* enable receive and send */ - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - return RT_EOK; -} - -static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } - - return (RT_EOK); -} - -static int uart47_putc(struct rt_serial_device *serial, char c) -{ - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - /* while send fifo is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to fifo */ - uart->uart_regs->TDR = c; - - return (1); -} - -static int uart47_getc(struct rt_serial_device *serial) -{ - int ch; - struct uart47_device *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - /* receive is disabled */ - if (!(uart->uart_regs->SCR & SCR_RXE)) - return (-1); - /* receive fifo is not full */ - if ((uart->uart_regs->SSR & SSR_RDRF) == 0) - return (-1); - /* read char */ - ch = uart->uart_regs->RDR & 0xff; - - return (ch); -} - -static struct rt_uart_ops uart47_ops = -{ - uart47_configure, - uart47_control, - uart47_putc, - uart47_getc, -}; - -void rt_hw_serial_init(void) -{ - struct serial_configure config; - - uart_pin_setup(); - -#if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial0.ops = &uart03_ops; - serial0.config = config; - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); -#endif - -#if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial1.ops = &uart03_ops; - serial1.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&serial1, - "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart1); -#endif - -#if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial2.ops = &uart03_ops; - serial2.config = config; - - /* register UART2 device */ - rt_hw_serial_register(&serial2, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); -#endif - -#if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial3.ops = &uart03_ops; - serial3.config = config; - - /* register UART3 device */ - rt_hw_serial_register(&serial3, - "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart3); -#endif - -#if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial4.ops = &uart47_ops; - serial4.config = config; - - /* register UART4 device */ - rt_hw_serial_register(&serial4, - "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart4); -#endif - -#if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial5.ops = &uart47_ops; - serial5.config = config; - - /* register UART5 device */ - rt_hw_serial_register(&serial5, - "uart5", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart5); -#endif - -#if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial6.ops = &uart47_ops; - serial6.config = config; - - /* register UART6 device */ - rt_hw_serial_register(&serial6, - "uart6", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart6); -#endif - -#if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; - - serial7.ops = &uart47_ops; - serial7.config = config; - - /* register UART7 device */ - rt_hw_serial_register(&serial7, - "uart7", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart7); -#endif -} diff --git a/bsp/mb9bf506r/drivers/fm3_uart.h b/bsp/mb9bf506r/drivers/fm3_uart.h deleted file mode 100644 index 824592c850..0000000000 --- a/bsp/mb9bf506r/drivers/fm3_uart.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#ifndef __FM3_UART_H__ -#define __FM3_UART_H__ - -#include -#include "mb9bf506r.h" - -#define SMR_SOE 0x01U -#define SMR_BDS 0x04U -#define SMR_SBL 0x08U -#define SMR_WUCR 0x10U -#define SMR_MD_UART 0x00U -#define SMR_MD_UART_MP 0x20U -#define SMR_MD_SIO 0x40U -#define SMR_MD_LIN 0x60U -#define SMR_MD_I2C 0x80U - -#define SCR_TXE 0x01U -#define SCR_RXE 0x02U -#define SCR_TBIE 0x04U -#define SCR_TIE 0x08U -#define SCR_RIE 0x10U -#define SCR_UPGL 0x80U - -#define SSR_TBI 0x01U -#define SSR_TDRE 0x02U -#define SSR_RDRF 0x04U -#define SSR_ORE 0x08U -#define SSR_FRE 0x10U -#define SSR_PE 0x20U -#define SSR_REC 0x80U - -#define ESCR_P 0x08U -#define ESCR_PEN 0x10U -#define ESCR_INV 0x20U -#define ESCR_ESBL 0x40U -#define ESCR_FLWEN 0x80U -#define ESCR_DATABITS_8 0x00U -#define ESCR_DATABITS_5 0x01U -#define ESCR_DATABITS_6 0x02U -#define ESCR_DATABITS_7 0x03U -#define ESCR_DATABITS_9 0x04U - -#define FIFO_SIZE 16 - -/* - * Enable/DISABLE Interrupt Controller - */ -/* deviation from MISRA-C:2004 Rule 19.7 */ -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -struct uart03_device -{ - FM3_MFS03_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; -}; - -struct uart47_device -{ - FM3_MFS47_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - rt_uint8_t fifo_size; -}; - -void rt_hw_serial_init(void); - -#endif diff --git a/bsp/mb9bf506r/drivers/led.c b/bsp/mb9bf506r/drivers/led.c deleted file mode 100644 index 3f6a11fcfe..0000000000 --- a/bsp/mb9bf506r/drivers/led.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include - -#include "mb9bf506r.h" -#include "led.h" - -void rt_hw_led_on(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - USER_LED_PDOR &= ~USER_LED1; - break; - case 2: - USER_LED_PDOR &= ~USER_LED2; - break; - case 3: - USER_LED_PDOR &= ~USER_LED3; - break; - default: - break; - } -} - -void rt_hw_led_off(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - USER_LED_PDOR |= USER_LED1; - break; - case 2: - USER_LED_PDOR |= USER_LED2; - break; - case 3: - USER_LED_PDOR |= USER_LED3; - break; - default: - break; - } -} - -void rt_hw_led_toggle(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - if (USER_LED_PDOR&USER_LED1) - USER_LED_PDOR &= ~USER_LED1; - else - USER_LED_PDOR |= USER_LED1; - break; - case 2: - if (USER_LED_PDOR&USER_LED2) - USER_LED_PDOR &= ~USER_LED2; - else - USER_LED_PDOR |= USER_LED2; - break; - case 3: - if (USER_LED_PDOR&USER_LED3) - USER_LED_PDOR &= ~USER_LED3; - else - USER_LED_PDOR |= USER_LED3; - break; - default: - break; - } -} - -void led_init(void) -{ - /*Select CPIO function*/ - USER_LED_PFR &= ~USER_LED_MASK; - /* disable analog input */ - FM3_GPIO->ADE &= ~USER_LED_MASK; - /*Set CPIO Pull-Up function*/ - USER_LED_PCR |= USER_LED_MASK; - /*Make led pins outputs*/ - USER_LED_DDR |= USER_LED_MASK; - USER_LED_PDOR |= USER_LED_MASK; -} - -void pwm_update(rt_uint16_t value) -{ - FM3_BT2_PWM->PDUT = value; -} - -static void led1_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(1); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void led2_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(2); - rt_thread_delay(RT_TICK_PER_SECOND/2); - } -} - -static rt_thread_t led1_thread; -static rt_thread_t led2_thread; -void rt_hw_led_init(void) -{ - led_init(); - - led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) - rt_thread_startup(led1_thread); - - led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) - rt_thread_startup(led2_thread); -} - - diff --git a/bsp/mb9bf506r/drivers/led.h b/bsp/mb9bf506r/drivers/led.h deleted file mode 100644 index bcbfaf9b62..0000000000 --- a/bsp/mb9bf506r/drivers/led.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __LED_H__ -#define __LED_H__ - -#include "mb9bf506r.h" - -#define LEDS_MAX_NUMBER 4 - -/* LED */ -#define USER_LED1 (1UL<<0x9) -#define USER_LED2 (1UL<<0xa) -#define USER_LED3 (1UL<<0xb) - -#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) -#define USER_LED_PFR FM3_GPIO->PFR1 -#define USER_LED_PCR FM3_GPIO->PCR1 -#define USER_LED_PDOR FM3_GPIO->PDOR1 -#define USER_LED_DDR FM3_GPIO->DDR1 - -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 - -void rt_hw_led_init(void); -void rt_hw_led_on(rt_uint8_t num); -void rt_hw_led_off(rt_uint8_t num); -void rt_hw_led_toggle(rt_uint8_t num); -void pwm_update(rt_uint16_t value); - -#endif diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c deleted file mode 100644 index 1c03120d14..0000000000 --- a/bsp/mb9bf506r/drivers/nand.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-05-25 Bernard first version - */ - -#include "nand.h" -#include "mb9bf506r.h" - -/* - * NandFlash driver for SamSung K9F5608 - * 32M x 8bit - */ -#define PAGE_SIZE 512 -#define PAGE_PER_BLOCK 32 -#define BLOCK_NUM 2048 - -/* device driver debug trace */ -/* #define NAND_DEBUG */ -#ifdef NAND_DEBUG -#define trace_log rt_kprintf -#else -#define trace_log(...) -#endif - -/* - * OOB, - * when block has been erased, OOB is 0xff. - * when block has been written, OOB is 0x00. - */ -struct rt_device_nand -{ - struct rt_device parent; /* which is inherited from rt_device */ - - rt_uint16_t block_num; /* total block number in device */ - rt_uint16_t page_per_block; /* pages in one block */ - rt_uint16_t page_size; /* page size */ - - /* this buffer which used as to save data before erase block */ - rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; -}; -static struct rt_device_nand _nand; - -/* Flash operation definition */ -#define NF_CMD(cmd) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_CMD_OFFSET) = (unsigned char)(cmd);} -#define NF_ADDR(addr) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ADDR_OFFSET)= (unsigned char)(addr);} -#define NF_RDDATA() (*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)) -#define NF_WRDATA(data) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)= (unsigned char)(data);} -#define NF_CLR_ALE() {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ALE_OFFSET) = (unsigned char)0;} - -/* Flash Control IO definition */ -#define NF_OE_H() {IO_NF_PDOR |= NF_EN;} -#define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} - -#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} -#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} - -static unsigned char NF_ReadStatus(void); -static void Wait(unsigned int cnt); -static void NF_Reset(void); - -static void Wait(unsigned int cnt) -{ - while(cnt--); -} - -static void NF_Reset(void) -{ - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_RESET); - NF_OE_H(); - - Wait(10000); /* wait for Trst */ -} - -static unsigned char NF_ReadStatus(void) -{ - unsigned int timeout=0; - NF_DATA_OUT(); - NF_CMD(NAND_CMD_STATUS); - NF_DATA_IN(); - - while(!(NF_RDDATA() & 0x40)) - { - timeout++; - if(timeout == 0x00080000) - return FLASH_NG; - } - if(NF_RDDATA() & 0x01)return FLASH_NG; - - return FLASH_OK; -} - -/* - * @ Funciton: NF_Init - * Parameter: None - * Return: None - */ -static void NF_Init(void) -{ - FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ - FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ - |1<<6 /* ALE, CLE, WEX, REX enable */ - |1<<0); /* D0-D7 enable */ - FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ - FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ - - IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); - IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); - IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ - - /*Reset NAND*/ - NF_Reset(); -} - -static void NF_UnInit(void) -{ - FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ - FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ - |1<<6 /* disable ALE, CLE, WEX, REX enable */ - |1<<0); /* disable D0-D7 enable */ - FM3_EXBUS->MODE7 &= ~(1<<4); - IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); - IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); - IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ -} - -/* - * @ Funciton: NF_ReadPage - * Parameter: block (max: 2048) - * page (max:32) - * buffer: pointer to data buffer - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, - unsigned char *oob) -{ - unsigned int blockPage,i; - - NF_Init(); - blockPage=(block<<5)+page; /* 1 block=32 page */ - NF_OE_L(); - NF_DATA_OUT(); - if (buffer != RT_NULL) - { - volatile unsigned char ch; - - NF_CMD(NAND_CMD_READ0); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for(i=0;i<512;i++) /* read 512 bytes data */ - buffer[i] = NF_RDDATA(); - for(i=0;i<16;i++) /* read 16 bytes oob */ - if (oob != RT_NULL) - oob[i] = NF_RDDATA(); - else - ch = NF_RDDATA(); - } - else - { - NF_CMD(NAND_CMD_READOOB); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for (i=0; i<16; i++) /* read 16 bytes oob */ - oob[i] = NF_RDDATA(); - } - - NF_OE_H(); - NF_UnInit(); - return 0; -} - -/* - * @ Funciton: NF_EraseBlock - * Parameter: block (max: 2048) - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_EraseBlock(unsigned int block) -{ - rt_uint32_t blockPage; - - trace_log("Erase block %d: ", block); - - NF_Init(); - blockPage = (block << 5); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_ERASE1); /* send erase command */ - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage >> 8) & 0xff); - NF_CMD(NAND_CMD_ERASE2); /* start erase */ - - if(NF_ReadStatus()) - { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - trace_log("Failed\n"); - rt_kprintf("erase block failed\n"); - - return FLASH_NG; - } - - NF_OE_H(); - NF_UnInit(); - - trace_log("OK\n"); - - return FLASH_OK; -} - -/* - * @ Funciton: NF_WritePage - * Parameter: block (max: 2048) - * page (max:32) - * buffer: pointer to data buffer - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) -{ - unsigned int blockPage,i; - unsigned char se[16] = {0}; - unsigned char data; - - blockPage = (block<<5)+page; - NF_Init(); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(0x00); /* set programming area */ - NF_CMD(NAND_CMD_SEQIN); /* send write command */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); - NF_CLR_ALE(); - - for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ - for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ - - NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ - - if(NF_ReadStatus()) - { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - - trace_log("write failed\n"); - return FLASH_NG; - } - - /* verify the write data */ - NF_DATA_OUT(); - NF_CMD(NAND_CMD_READ0); /* send read command */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - for(i=0; i<512; i++) - { - data=NF_RDDATA(); /* verify 1-512 byte */ - if(data != buffer[i]) - { - trace_log("block %d, page %d\n", block , page); - trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); - - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - return FLASH_NG; - } - } - - for(i=0; i<16; i++) - { - data=NF_RDDATA(); /* verify 16 byte dummy data */ - if(data != se[i]) - { - trace_log("block %d, page %d\n", block , page); - trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - return FLASH_NG; - } - } - - NF_OE_H(); - NF_UnInit(); - return FLASH_OK; -} - -/* - * @ Funciton: NF_ReadID - * Parameter: id: pointer to device ID - * Return: None - */ -void NF_ReadID(unsigned char *id) -{ - unsigned char maker_code; - NF_Init(); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_READID); - NF_ADDR(0x00); - NF_CLR_ALE(); - Wait(10); - NF_DATA_IN(); - maker_code = NF_RDDATA(); - maker_code = maker_code; - *id = NF_RDDATA(); - NF_OE_H(); - NF_UnInit(); -} - -static rt_err_t rt_nand_init (rt_device_t dev) -{ - /* empty implementation */ - return RT_EOK; -} - -static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) -{ - /* empty implementation */ - return RT_EOK; -} - -static rt_err_t rt_nand_close(rt_device_t dev) -{ - /* empty implementation */ - return RT_EOK; -} - -/* nand device read */ -static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_ubase_t block; /* block of position */ - rt_ubase_t page, index; /* page in block of position */ - rt_uint8_t *page_ptr, oob[16]; - struct rt_device_nand *nand; - - /* get nand device */ - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand read: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - /* set page buffer pointer */ - page_ptr = (rt_uint8_t*) buffer; - for (index = 0; index < size; index ++) - { - NF_ReadPage(block, page + index, page_ptr, oob); - page_ptr += nand->page_size; - - if (page + index > nand->page_per_block) - { - block += 1; - page = 0; - } - } - - /* return read size (count of block) */ - return size; -} - -/* - * write pages by erase block first - * @param nand the nand device driver - * @param block the block of page - * @param page the page - * @param buffer the data buffer to be written - * @param pages the number of pages to be written - */ -static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, - rt_ubase_t block, rt_ubase_t page, - const rt_uint8_t *buffer, rt_ubase_t pages) -{ - rt_ubase_t index; - rt_uint32_t page_status; - rt_uint8_t *page_ptr, oob[16]; - - /* set page status */ - page_status = 0; - - /* read each page in block */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - NF_ReadPage(block, index, page_ptr, oob); - if (!oob[0]) - page_status |= (1 << index); - page_ptr += nand->page_size; - } - - /* erase block */ - NF_EraseBlock(block); - - page_ptr = &(nand->block_buffer[page * nand->page_size]); - /* merge buffer to page buffer */ - for (index = 0; index < pages; index ++) - { - rt_memcpy(page_ptr, buffer, nand->page_size); - - /* set page status */ - page_status |= (1 << (page + index)); - - /* move to next page */ - page_ptr += nand->page_size; - buffer += nand->page_size; - } - - /* write to flash */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - if (page_status & (1 << index)) - NF_WritePage(block, index, page_ptr); - - /* move to next page */ - page_ptr += nand->page_size; - } - - return 0; -} - -/* nand device write */ -static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, - const void* buffer, rt_size_t size) -{ - rt_ubase_t block, page; - rt_uint8_t oob[16]; - struct rt_device_nand *nand; - - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand write: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - if (size == 1) - { - /* write one page */ - - /* read oob to get page status */ - NF_ReadPage(block, page, RT_NULL, oob); - if (oob[0]) - NF_WritePage(block, page, buffer); - else - /* erase block and then write page */ - rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); - } - else if (size > 1) - { - rt_ubase_t index; - rt_ubase_t need_erase_block; - const rt_uint8_t *page_ptr; - rt_ubase_t chunk_pages, pages; - - pages = size; - page_ptr = (const rt_uint8_t*) buffer; - do - { - need_erase_block = 0; - /* calculate pages in current chunk */ - if (pages > nand->page_per_block - page) - chunk_pages = nand->page_per_block - page; - else - chunk_pages = pages; - - /* get page status in current block */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_ReadPage(block, index, RT_NULL, oob); - if (!oob[0]) - { - /* this page has data, need erase this block firstly */ - need_erase_block = 1; - break; - } - } - - if (need_erase_block) - { - /* erase block and then write it */ - rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); - page_ptr += chunk_pages * nand->page_size; - } - else - { - /* write pages directly */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_WritePage(block, index, page_ptr); - page_ptr += nand->page_size; - } - } - - pages -= chunk_pages; - page = 0; block ++; /* move to next block */ - } - while (pages); - } - - return size; -} - -static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args) -{ - struct rt_device_nand *nand; - - nand = (struct rt_device_nand*) dev; - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - { - struct rt_device_blk_geometry *geometry; - - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; - - geometry->bytes_per_sector = nand->page_size; - geometry->block_size = nand->page_size * nand->page_per_block; - geometry->sector_count = nand->block_num * nand->page_per_block; - } - break; - } - - return RT_EOK; -} - -void rt_hw_nand_init(void) -{ - /* initialize nand flash structure */ - _nand.block_num = BLOCK_NUM; - _nand.page_per_block = PAGE_PER_BLOCK; - _nand.page_size = PAGE_SIZE; - - rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); - - _nand.parent.type = RT_Device_Class_MTD; - _nand.parent.rx_indicate = RT_NULL; - _nand.parent.tx_complete = RT_NULL; - _nand.parent.init = rt_nand_init; - _nand.parent.open = rt_nand_open; - _nand.parent.close = rt_nand_close; - _nand.parent.read = rt_nand_read; - _nand.parent.write = rt_nand_write; - _nand.parent.control = rt_nand_control; - - /* register a MTD device */ - rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); -} - -#ifdef NAND_DEBUG -#include -unsigned char nand_buffer[512]; -unsigned char nand_oob[16]; - -void dump_mem(unsigned char* buffer, int length) -{ - int i; - - if (length > 64) length = 64; - for (i = 0; i < length; i ++) - { - rt_kprintf("%02x ", *buffer++); - if (((i+1) % 16) == 0) - rt_kprintf("\n"); - } - rt_kprintf("\n"); -} - -void nand_read(int block, int page) -{ - rt_kprintf("read block %d, page %d\n", block, page); - - NF_ReadPage(block, page, nand_buffer, nand_oob); - rt_kprintf("page data:\n"); - dump_mem(nand_buffer, 512); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); - -void nand_write(int block, int page) -{ - int i; - for (i = 0; i < 512; i ++) - nand_buffer[i] = i; - - NF_WritePage(block, page, nand_buffer); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); - -void nand_erase(int block) -{ - NF_EraseBlock(block); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); - -void nand_readoob(int block, int page) -{ - rt_kprintf("read oob on block %d, page %d\n", block, page); - - NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); - -void nand_erase_chip(void) -{ - int i; - unsigned char id; - - NF_ReadID(&id); - rt_kprintf("id: %02x\n", id); - - for (i = 0; i < 2048; i ++) - { - NF_EraseBlock(i); - } -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); -#endif diff --git a/bsp/mb9bf506r/drivers/nand.h b/bsp/mb9bf506r/drivers/nand.h deleted file mode 100644 index d00909ddce..0000000000 --- a/bsp/mb9bf506r/drivers/nand.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-05-25 Bernard first version - */ - -#ifndef __NAND_H__ -#define __NAND_H__ - -#include - -#define IO_NF_PFR FM3_GPIO->PFR3 -#define IO_NF_DDR FM3_GPIO->DDR3 -#define IO_NF_PDOR FM3_GPIO->PDOR3 - -#define NF_EN 0x0008 -#define NF_DATA_DIR 0x0004 - -#define EXT_BUS_BASE_ADDR 0x60000000 -#define EXT_CS7_OFFSET 0x0E000000 -#define EXT_CS7_SIZE 0x02000000 - -#define NF_FLASH_BASE_ADDR (EXT_BUS_BASE_ADDR+EXT_CS7_OFFSET) - -#define NF_ALE_OFFSET 0x00003000 -#define NF_ADDR_OFFSET 0x00002000 -#define NF_CMD_OFFSET 0x00001000 -#define NF_DATA_OFFSET 0x00000000 - -/* NAND command */ -#define NAND_CMD_READ0 0x00 -#define NAND_CMD_READ1 0x01 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE1 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_SEQIN 0x80 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_READID1 0x91 -#define NAND_CMD_ERASE2 0xd0 -#define NAND_CMD_RESET 0xff - -#define FLASH_OK 0 -#define FLASH_NG 1 - -/* nand flash device initialization */ -void rt_hw_nand_init(void); - -#endif diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h b/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h deleted file mode 100644 index 1b7029a755..0000000000 --- a/bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h +++ /dev/null @@ -1,209 +0,0 @@ -/************************************************** - * - * This file shall be included in appropriate CMSIS header - * files, to provide required functions and intrinsics when - * building with the IAR C/C++ Compiler for ARM (iccarm). - * - * Copyright 2011 IAR Systems. All rights reserved. - * - * $Revision: 50409 $ - * - **************************************************/ - -#ifndef __CMSIS_IAR_H__ -#define __CMSIS_IAR_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#include - -#if (__CORE__ == __ARM6M__) - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz - #define __SSAT __cmsis_iar_ssat -#endif - -#pragma diag_suppress=Pe940 -#pragma diag_suppress=Pe177 - -#define __enable_irq __enable_interrupt -#define __disable_irq __disable_interrupt -#define __NOP __no_operation - -#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ - -#if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */ - -static uint32_t __get_APSR(void) -{ - __ASM("mrs r0, apsr"); -} - -static uint32_t __get_xPSR(void) -{ - __ASM("mrs r0, psr"); /* assembler does not know "xpsr" */ -} - -#endif /* __VER__ < 6010002 */ - -static uint32_t __get_IPSR(void) -{ - __ASM("mrs r0, ipsr"); -} - -static uint32_t __get_PSR(void) -{ - __ASM("mrs r0, psr"); -} - -static uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); -} - -static void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); -} - -static uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); -} - -static void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); -} - -static __INLINE void __WFI(void) -{ - __ASM ("wfi"); -} - -static __INLINE void __WFE(void) -{ - __ASM ("wfe"); -} - -static __INLINE void __SEV(void) -{ - __ASM ("sev"); -} - -static uint32_t __REV16(uint32_t value) -{ - __ASM("rev16 r0, r0"); -} - -#else /* __VER__ < 6020000 */ - -static uint32_t __get_xPSR(void) -{ - return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */ -} - -#endif /* __VER__ < 6020000 */ - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - -#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ - -static __INLINE void __enable_fault_irq(void) -{ - __ASM ("cpsie f"); -} - -static __INLINE void __disable_fault_irq(void) -{ - __ASM ("cpsid f"); -} - -static uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); -} - -static uint8_t __LDREXB(volatile uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); -} - -static uint16_t __LDREXH(volatile uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); -} - -static uint32_t __LDREXW(volatile uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); -} - -static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); -} - -static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); -} - -static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); -} - -static __INLINE void __CLREX(void) -{ - __ASM ("clrex"); -} - -#else /* __VER__ >= 6020000 --------------------- */ - -#define __LDREXW __LDREX -#define __STREXW __STREX -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#endif /* __VER__ < 6020000 */ - -#endif /* (__CORTEX_M >= 0x03) */ - -#if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - -#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */ - -static uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */ - __ASM("vmrs r0, fpscr"); -#else - return(0); -#endif -} - -static void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */ - __ASM("vmsr fpscr, r0"); -#endif -} - -#endif /* __VER__ < 6020000 */ - -#endif /* (__CORTEX_M == 0x04) */ - -static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); -} - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_IAR_H__ */ diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index 0173893fbd..0000000000 --- a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1612 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.01 - * @date 22. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 3c932e0d6e..0000000000 --- a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h b/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 597e64df04..0000000000 --- a/bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h deleted file mode 100644 index df507ee456..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mb9bf506r.h +++ /dev/null @@ -1,17483 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/* */ -/* Header File for Device MB9BF506R */ -/* Version V1.03 */ -/* Date 2011-05-16 */ -/* */ -/************************************************************************/ - -#ifndef _MB9BF506R_H_ -#define _MB9BF506R_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - - -/****************************************************************************** - * Interrupt Number Definition - ******************************************************************************/ -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Super Visor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detector */ - WFG_IRQn = 3, /* Wave Form Generator */ - EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ - EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ - DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ - MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ - MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ - MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ - MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ - MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ - MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ - MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ - MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ - MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ - MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ - MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ - MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ - MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ - MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ - MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ - MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ - PPG_IRQn = 23, /* PPG */ - OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ - ADC0_IRQn = 25, /* ADC0 */ - ADC1_IRQn = 26, /* ADC1 */ - ADC2_IRQn = 27, /* ADC2 */ - FRTIM_IRQn = 28, /* Free-run Timer */ - INCAP_IRQn = 29, /* Input Capture */ - OUTCOMP_IRQn = 30, /* Output Compare */ - BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ - CAN0_IRQn = 32, /* CAN ch.0 */ - CAN1_IRQn = 33, /* CAN ch.1 */ - USBF_IRQn = 34, /* USB Function */ - USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ - /* Reserved = 36 */ - /* Reserved = 37 */ - DMAC0_IRQn = 38, /* DMAC ch.0 */ - DMAC1_IRQn = 39, /* DMAC ch.1 */ - DMAC2_IRQn = 40, /* DMAC ch.2 */ - DMAC3_IRQn = 41, /* DMAC ch.3 */ - DMAC4_IRQn = 42, /* DMAC ch.4 */ - DMAC5_IRQn = 43, /* DMAC ch.5 */ - DMAC6_IRQn = 44, /* DMAC ch.6 */ - DMAC7_IRQn = 45 /* DMAC ch.7 */ - /* Reserved = 46 */ - /* Reserved = 47 */ -} IRQn_Type; - - -#include "core_cm3.h" -#include "system_mb9bf50x.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * Peripheral register bit fields - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash_IF_MODULE register bit fields */ -typedef struct stc_flash_if_faszr_field -{ - __IO uint32_t ASZ0 : 1; - __IO uint32_t ASZ1 : 1; -} stc_flash_if_faszr_field_t; - -typedef struct stc_flash_if_frwtr_field -{ - __IO uint32_t RWT0 : 1; - __IO uint32_t RWT1 : 1; -} stc_flash_if_frwtr_field_t; - -typedef struct stc_flash_if_fstr_field -{ - __IO uint32_t RDY : 1; - __IO uint32_t HNG : 1; - __IO uint32_t EER : 1; -} stc_flash_if_fstr_field_t; - -typedef struct stc_flash_if_fsyndn_field -{ - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; -} stc_flash_if_fsyndn_field_t; - -typedef struct stc_flash_if_crtrmm_field -{ - __IO uint32_t TRMM0 : 1; - __IO uint32_t TRMM1 : 1; - __IO uint32_t TRMM2 : 1; - __IO uint32_t TRMM3 : 1; - __IO uint32_t TRMM4 : 1; - __IO uint32_t TRMM5 : 1; - __IO uint32_t TRMM6 : 1; - __IO uint32_t TRMM7 : 1; - __IO uint32_t TRMM8 : 1; - __IO uint32_t TRMM9 : 1; -} stc_flash_if_crtrmm_field_t; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock_Reset_MODULE register bit fields */ -typedef struct stc_crg_scm_ctl_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MOSCE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SOSCE : 1; - __IO uint8_t PLLE : 1; - __IO uint8_t RCS0 : 1; - __IO uint8_t RCS1 : 1; - __IO uint8_t RCS2 : 1; -} stc_crg_scm_ctl_field_t; - -typedef struct stc_crg_scm_str_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MORDY : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SORDY : 1; - __IO uint8_t PLRDY : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t RCM2 : 1; -} stc_crg_scm_str_field_t; - -typedef struct stc_crg_rst_str_field -{ - __IO uint16_t PONR : 1; - __IO uint16_t INITX : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SWDT : 1; - __IO uint16_t HWDT : 1; - __IO uint16_t CSVR : 1; - __IO uint16_t FCSR : 1; - __IO uint16_t SRST : 1; -} stc_crg_rst_str_field_t; - -typedef struct stc_crg_bsc_psr_field -{ - __IO uint8_t BSR0 : 1; - __IO uint8_t BSR1 : 1; - __IO uint8_t BSR2 : 1; -} stc_crg_bsc_psr_field_t; - -typedef struct stc_crg_apbc0_psr_field -{ - __IO uint8_t APBC00 : 1; - __IO uint8_t APBC01 : 1; -} stc_crg_apbc0_psr_field_t; - -typedef struct stc_crg_apbc1_psr_field -{ - __IO uint8_t APBC10 : 1; - __IO uint8_t APBC11 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC1RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC1EN : 1; -} stc_crg_apbc1_psr_field_t; - -typedef struct stc_crg_apbc2_psr_field -{ - __IO uint8_t APBC20 : 1; - __IO uint8_t APBC21 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC2RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC2EN : 1; -} stc_crg_apbc2_psr_field_t; - -typedef struct stc_crg_swc_psr_field -{ - __IO uint8_t SWDS0 : 1; - __IO uint8_t SWDS1 : 1; - uint8_t RESERVED1 : 5; - __IO uint8_t TESTB : 1; -} stc_crg_swc_psr_field_t; - -typedef struct stc_crg_ttc_psr_field -{ - __IO uint8_t TTC : 1; -} stc_crg_ttc_psr_field_t; - -typedef struct stc_crg_csw_tmr_field -{ - __IO uint8_t MOWT0 : 1; - __IO uint8_t MOWT1 : 1; - __IO uint8_t MOWT2 : 1; - __IO uint8_t MOWT3 : 1; - __IO uint8_t SOWT0 : 1; - __IO uint8_t SOWT1 : 1; - __IO uint8_t SOWT2 : 1; -} stc_crg_csw_tmr_field_t; - -typedef struct stc_crg_psw_tmr_field -{ - __IO uint8_t POWT0 : 1; - __IO uint8_t POWT1 : 1; - __IO uint8_t POWT2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t PINC : 1; -} stc_crg_psw_tmr_field_t; - -typedef struct stc_crg_pll_ctl1_field -{ - __IO uint8_t PLLM0 : 1; - __IO uint8_t PLLM1 : 1; - __IO uint8_t PLLM2 : 1; - __IO uint8_t PLLM3 : 1; - __IO uint8_t PLLK0 : 1; - __IO uint8_t PLLK1 : 1; - __IO uint8_t PLLK2 : 1; - __IO uint8_t PLLK3 : 1; -} stc_crg_pll_ctl1_field_t; - -typedef struct stc_crg_pll_ctl2_field -{ - __IO uint8_t PLLN0 : 1; - __IO uint8_t PLLN1 : 1; - __IO uint8_t PLLN2 : 1; - __IO uint8_t PLLN3 : 1; - __IO uint8_t PLLN4 : 1; - __IO uint8_t PLLN5 : 1; -} stc_crg_pll_ctl2_field_t; - -typedef struct stc_crg_csv_ctl_field -{ - __IO uint16_t MCSVE : 1; - __IO uint16_t SCSVE : 1; - uint16_t RESERVED1 : 6; - __IO uint16_t FCSDE : 1; - __IO uint16_t FCSRE : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t FCD0 : 1; - __IO uint16_t FCD1 : 1; - __IO uint16_t FCD2 : 1; -} stc_crg_csv_ctl_field_t; - -typedef struct stc_crg_csv_str_field -{ - __IO uint8_t MCMF : 1; - __IO uint8_t SCMF : 1; -} stc_crg_csv_str_field_t; - -typedef struct stc_crg_dbwdt_ctl_field -{ - uint8_t RESERVED1 : 5; - __IO uint8_t DPSWBE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t DPHWBE : 1; -} stc_crg_dbwdt_ctl_field_t; - -typedef struct stc_crg_int_enr_field -{ - __IO uint8_t MCSE : 1; - __IO uint8_t SCSE : 1; - __IO uint8_t PCSE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSE : 1; -} stc_crg_int_enr_field_t; - -typedef struct stc_crg_int_str_field -{ - __IO uint8_t MCSI : 1; - __IO uint8_t SCSI : 1; - __IO uint8_t PCSI : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSI : 1; -} stc_crg_int_str_field_t; - -typedef struct stc_crg_int_clr_field -{ - __IO uint8_t MCSC : 1; - __IO uint8_t SCSC : 1; - __IO uint8_t PCSC : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSC : 1; -} stc_crg_int_clr_field_t; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* HWWDT_MODULE register bit fields */ -typedef struct stc_hwwdt_wdg_ctl_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_hwwdt_wdg_ctl_field_t; - -typedef struct stc_hwwdt_wdg_ris_field -{ - __IO uint8_t RIS : 1; -} stc_hwwdt_wdg_ris_field_t; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* SWWDT_MODULE register bit fields */ -typedef struct stc_swwdt_wdogcontrol_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_swwdt_wdogcontrol_field_t; - -typedef struct stc_swwdt_wdogris_field -{ - __IO uint8_t RIS : 1; -} stc_swwdt_wdogris_field_t; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* DTIM_MODULE register bit fields */ -typedef struct stc_dtim_timer1control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer1control_field_t; - -typedef struct stc_dtim_timer1ris_field -{ - __IO uint32_t TIMERXRIS : 1; -} stc_dtim_timer1ris_field_t; - -typedef struct stc_dtim_timer1mis_field -{ - __IO uint32_t TIMERXRIS : 1; -} stc_dtim_timer1mis_field_t; - -typedef struct stc_dtim_timer2control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer2control_field_t; - -typedef struct stc_dtim_timer2ris_field -{ - __IO uint32_t TIMERXRIS : 1; -} stc_dtim_timer2ris_field_t; - -typedef struct stc_dtim_timer2mis_field -{ - __IO uint32_t TIMERXRIS : 1; -} stc_dtim_timer2mis_field_t; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* MFT_FRT_MODULE register bit fields */ -typedef struct stc_mft_frt_tcsa0_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa0_field_t; - -typedef struct stc_mft_frt_tcsb0_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb0_field_t; - -typedef struct stc_mft_frt_tcsa1_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa1_field_t; - -typedef struct stc_mft_frt_tcsb1_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb1_field_t; - -typedef struct stc_mft_frt_tcsa2_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa2_field_t; - -typedef struct stc_mft_frt_tcsb2_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb2_field_t; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* MFT_OCU_MODULE register bit fields */ -typedef struct stc_mft_ocu_ocsa10_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa10_field_t; - -typedef struct stc_mft_ocu_ocsb10_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; -} stc_mft_ocu_ocsb10_field_t; - -typedef struct stc_mft_ocu_ocsa32_field -{ - __IO uint8_t CST2 : 1; - __IO uint8_t CST3 : 1; - __IO uint8_t BDIS2 : 1; - __IO uint8_t BDIS3 : 1; - __IO uint8_t IOE2 : 1; - __IO uint8_t IOE3 : 1; - __IO uint8_t IOP2 : 1; - __IO uint8_t IOP3 : 1; -} stc_mft_ocu_ocsa32_field_t; - -typedef struct stc_mft_ocu_ocsb32_field -{ - __IO uint8_t OTD2 : 1; - __IO uint8_t OTD3 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS2 : 1; - __IO uint8_t BTS3 : 1; -} stc_mft_ocu_ocsb32_field_t; - -typedef struct stc_mft_ocu_ocsa54_field -{ - __IO uint8_t CST4 : 1; - __IO uint8_t CST5 : 1; - __IO uint8_t BDIS4 : 1; - __IO uint8_t BDIS5 : 1; - __IO uint8_t IOE4 : 1; - __IO uint8_t IOE5 : 1; - __IO uint8_t IOP4 : 1; - __IO uint8_t IOP5 : 1; -} stc_mft_ocu_ocsa54_field_t; - -typedef struct stc_mft_ocu_ocsb54_field -{ - __IO uint8_t OTD4 : 1; - __IO uint8_t OTD5 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS4 : 1; - __IO uint8_t BTS5 : 1; -} stc_mft_ocu_ocsb54_field_t; - -typedef struct stc_mft_ocu_ocsc_field -{ - __IO uint8_t MOD0 : 1; - __IO uint8_t MOD1 : 1; - __IO uint8_t MOD2 : 1; - __IO uint8_t MOD3 : 1; - __IO uint8_t MOD4 : 1; - __IO uint8_t MOD5 : 1; -} stc_mft_ocu_ocsc_field_t; - -typedef struct stc_mft_ocu_ocfs10_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs10_field_t; - -typedef struct stc_mft_ocu_ocfs32_field -{ - __IO uint8_t FSO20 : 1; - __IO uint8_t FSO21 : 1; - __IO uint8_t FSO22 : 1; - __IO uint8_t FSO23 : 1; - __IO uint8_t FSO30 : 1; - __IO uint8_t FSO31 : 1; - __IO uint8_t FSO32 : 1; - __IO uint8_t FSO33 : 1; -} stc_mft_ocu_ocfs32_field_t; - -typedef struct stc_mft_ocu_ocfs54_field -{ - __IO uint8_t FSO40 : 1; - __IO uint8_t FSO41 : 1; - __IO uint8_t FSO42 : 1; - __IO uint8_t FSO43 : 1; - __IO uint8_t FSO50 : 1; - __IO uint8_t FSO51 : 1; - __IO uint8_t FSO52 : 1; - __IO uint8_t FSO53 : 1; -} stc_mft_ocu_ocfs54_field_t; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* MFT_WFG_MODULE register bit fields */ -typedef struct stc_mft_wfg_wfsa10_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa10_field_t; - -typedef struct stc_mft_wfg_wfsa32_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa32_field_t; - -typedef struct stc_mft_wfg_wfsa54_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa54_field_t; - -typedef struct stc_mft_wfg_wfir_field -{ - __IO uint16_t DTIF : 1; - __IO uint16_t DTIC : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t TMIF10 : 1; - __IO uint16_t TMIC10 : 1; - __IO uint16_t TMIE10 : 1; - __IO uint16_t TMIS10 : 1; - __IO uint16_t TMIF32 : 1; - __IO uint16_t TMIC32 : 1; - __IO uint16_t TMIE32 : 1; - __IO uint16_t TMIS32 : 1; - __IO uint16_t TMIF54 : 1; - __IO uint16_t TMIC54 : 1; - __IO uint16_t TMIE54 : 1; - __IO uint16_t TMIS54 : 1; -} stc_mft_wfg_wfir_field_t; - -typedef struct stc_mft_wfg_nzcl_field -{ - __IO uint16_t DTIE : 1; - __IO uint16_t NWS0 : 1; - __IO uint16_t NWS1 : 1; - __IO uint16_t NWS2 : 1; - __IO uint16_t SDTI : 1; -} stc_mft_wfg_nzcl_field_t; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* MFT_ICU_MODULE register bit fields */ -typedef struct stc_mft_icu_icfs10_field -{ - __IO uint8_t FSI00 : 1; - __IO uint8_t FSI01 : 1; - __IO uint8_t FSI02 : 1; - __IO uint8_t FSI03 : 1; - __IO uint8_t FSI10 : 1; - __IO uint8_t FSI11 : 1; - __IO uint8_t FSI12 : 1; - __IO uint8_t FSI13 : 1; -} stc_mft_icu_icfs10_field_t; - -typedef struct stc_mft_icu_icfs32_field -{ - __IO uint8_t FSI20 : 1; - __IO uint8_t FSI21 : 1; - __IO uint8_t FSI22 : 1; - __IO uint8_t FSI23 : 1; - __IO uint8_t FSI30 : 1; - __IO uint8_t FSI31 : 1; - __IO uint8_t FSI32 : 1; - __IO uint8_t FSI33 : 1; -} stc_mft_icu_icfs32_field_t; - -typedef struct stc_mft_icu_icsa10_field -{ - __IO uint8_t EG00 : 1; - __IO uint8_t EG01 : 1; - __IO uint8_t EG10 : 1; - __IO uint8_t EG11 : 1; - __IO uint8_t ICE0 : 1; - __IO uint8_t ICE1 : 1; - __IO uint8_t ICP0 : 1; - __IO uint8_t ICP1 : 1; -} stc_mft_icu_icsa10_field_t; - -typedef struct stc_mft_icu_icsb10_field -{ - __IO uint8_t IEI0 : 1; - __IO uint8_t IEI1 : 1; -} stc_mft_icu_icsb10_field_t; - -typedef struct stc_mft_icu_icsa32_field -{ - __IO uint8_t EG20 : 1; - __IO uint8_t EG21 : 1; - __IO uint8_t EG30 : 1; - __IO uint8_t EG31 : 1; - __IO uint8_t ICE2 : 1; - __IO uint8_t ICE3 : 1; - __IO uint8_t ICP2 : 1; - __IO uint8_t ICP3 : 1; -} stc_mft_icu_icsa32_field_t; - -typedef struct stc_mft_icu_icsb32_field -{ - __IO uint8_t IEI2 : 1; - __IO uint8_t IEI3 : 1; -} stc_mft_icu_icsb32_field_t; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* MFT_ADCMP_MODULE register bit fields */ -typedef struct stc_mft_adcmp_acsb_field -{ - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t BDIS2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; - __IO uint8_t BTS2 : 1; -} stc_mft_adcmp_acsb_field_t; - -typedef struct stc_mft_adcmp_acsa_field -{ - __IO uint16_t CE00 : 1; - __IO uint16_t CE01 : 1; - __IO uint16_t CE10 : 1; - __IO uint16_t CE11 : 1; - __IO uint16_t CE20 : 1; - __IO uint16_t CE21 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SEL00 : 1; - __IO uint16_t SEL01 : 1; - __IO uint16_t SEL10 : 1; - __IO uint16_t SEL11 : 1; - __IO uint16_t SEL20 : 1; - __IO uint16_t SEL21 : 1; -} stc_mft_adcmp_acsa_field_t; - -typedef struct stc_mft_adcmp_atsa_field -{ - __IO uint16_t AD0S0 : 1; - __IO uint16_t AD0S1 : 1; - __IO uint16_t AD1S0 : 1; - __IO uint16_t AD1S1 : 1; - __IO uint16_t AD2S0 : 1; - __IO uint16_t AD2S1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t AD0P0 : 1; - __IO uint16_t AD0P1 : 1; - __IO uint16_t AD1P0 : 1; - __IO uint16_t AD1P1 : 1; - __IO uint16_t AD2P0 : 1; - __IO uint16_t AD2P1 : 1; -} stc_mft_adcmp_atsa_field_t; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* MFT_PPG_MODULE register bit fields */ -typedef struct stc_mft_ppg_ttcr0_field -{ - __IO uint8_t STR0 : 1; - __IO uint8_t MONI0 : 1; - __IO uint8_t CS00 : 1; - __IO uint8_t CS01 : 1; - __IO uint8_t TRG0O : 1; - __IO uint8_t TRG2O : 1; - __IO uint8_t TRG4O : 1; - __IO uint8_t TRG6O : 1; -} stc_mft_ppg_ttcr0_field_t; - -typedef struct stc_mft_ppg_ttcr1_field -{ - __IO uint8_t STR1 : 1; - __IO uint8_t MONI1 : 1; - __IO uint8_t CS10 : 1; - __IO uint8_t CS11 : 1; - __IO uint8_t TRG1O : 1; - __IO uint8_t TRG3O : 1; - __IO uint8_t TRG5O : 1; - __IO uint8_t TRG7O : 1; -} stc_mft_ppg_ttcr1_field_t; - -typedef struct stc_mft_ppg_trg_field -{ - __IO uint16_t PEN00 : 1; - __IO uint16_t PEN01 : 1; - __IO uint16_t PEN02 : 1; - __IO uint16_t PEN03 : 1; - __IO uint16_t PEN04 : 1; - __IO uint16_t PEN05 : 1; - __IO uint16_t PEN06 : 1; - __IO uint16_t PEN07 : 1; - __IO uint16_t PEN08 : 1; - __IO uint16_t PEN09 : 1; - __IO uint16_t PEN10 : 1; - __IO uint16_t PEN11 : 1; - __IO uint16_t PEN12 : 1; - __IO uint16_t PEN13 : 1; - __IO uint16_t PEN14 : 1; - __IO uint16_t PEN15 : 1; -} stc_mft_ppg_trg_field_t; - -typedef struct stc_mft_ppg_revc_field -{ - __IO uint16_t REV00 : 1; - __IO uint16_t REV01 : 1; - __IO uint16_t REV02 : 1; - __IO uint16_t REV03 : 1; - __IO uint16_t REV04 : 1; - __IO uint16_t REV05 : 1; - __IO uint16_t REV06 : 1; - __IO uint16_t REV07 : 1; - __IO uint16_t REV08 : 1; - __IO uint16_t REV09 : 1; - __IO uint16_t REV10 : 1; - __IO uint16_t REV11 : 1; - __IO uint16_t REV12 : 1; - __IO uint16_t REV13 : 1; - __IO uint16_t REV14 : 1; - __IO uint16_t REV15 : 1; -} stc_mft_ppg_revc_field_t; - -typedef struct stc_mft_ppg_ppgc1_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc1_field_t; - -typedef struct stc_mft_ppg_ppgc0_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc0_field_t; - -typedef struct stc_mft_ppg_ppgc3_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc3_field_t; - -typedef struct stc_mft_ppg_ppgc2_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc2_field_t; - -typedef struct stc_mft_ppg_gatec0_field -{ - __IO uint8_t EDGE0 : 1; - __IO uint8_t STRG0 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE2 : 1; - __IO uint8_t STRG2 : 1; -} stc_mft_ppg_gatec0_field_t; - -typedef struct stc_mft_ppg_ppgc5_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc5_field_t; - -typedef struct stc_mft_ppg_ppgc4_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc4_field_t; - -typedef struct stc_mft_ppg_ppgc7_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc7_field_t; - -typedef struct stc_mft_ppg_ppgc6_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc6_field_t; - -typedef struct stc_mft_ppg_gatec4_field -{ - __IO uint8_t EDGE4 : 1; - __IO uint8_t STRG4 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE6 : 1; - __IO uint8_t STRG6 : 1; -} stc_mft_ppg_gatec4_field_t; - -typedef struct stc_mft_ppg_ppgc9_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc9_field_t; - -typedef struct stc_mft_ppg_ppgc8_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc8_field_t; - -typedef struct stc_mft_ppg_ppgc11_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc11_field_t; - -typedef struct stc_mft_ppg_ppgc10_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc10_field_t; - -typedef struct stc_mft_ppg_gatec8_field -{ - __IO uint8_t EDGE8 : 1; - __IO uint8_t STRG8 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE10 : 1; - __IO uint8_t STRG10 : 1; -} stc_mft_ppg_gatec8_field_t; - -typedef struct stc_mft_ppg_ppgc13_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc13_field_t; - -typedef struct stc_mft_ppg_ppgc12_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc12_field_t; - -typedef struct stc_mft_ppg_ppgc15_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc15_field_t; - -typedef struct stc_mft_ppg_ppgc14_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc14_field_t; - -typedef struct stc_mft_ppg_gatec12_field -{ - __IO uint8_t EDGE12 : 1; - __IO uint8_t STRG12 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE14 : 1; - __IO uint8_t STRG14 : 1; -} stc_mft_ppg_gatec12_field_t; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* BT_PPG_MODULE register bit fields */ -typedef struct stc_bt_ppg_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_ppg_tmcr_field_t; - -typedef struct stc_bt_ppg_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_ppg_stc_field_t; - -typedef struct stc_bt_ppg_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_ppg_tmcr2_field_t; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* BT_PWM_MODULE register bit fields */ -typedef struct stc_bt_pwm_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwm_tmcr_field_t; - -typedef struct stc_bt_pwm_stc_field -{ - __IO uint8_t UDIR : 1; - __IO uint8_t DTIR : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t UDIE : 1; - __IO uint8_t DTIE : 1; - __IO uint8_t TGIE : 1; -} stc_bt_pwm_stc_field_t; - -typedef struct stc_bt_pwm_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwm_tmcr2_field_t; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* BT_RT_MODULE register bit fields */ -typedef struct stc_bt_rt_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_rt_tmcr_field_t; - -typedef struct stc_bt_rt_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_rt_stc_field_t; - -typedef struct stc_bt_rt_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_rt_tmcr2_field_t; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* BT_PWC_MODULE register bit fields */ -typedef struct stc_bt_pwc_tmcr_field -{ - uint16_t RESERVED1 : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t EGS2 : 1; - uint16_t RESERVED3 : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwc_tmcr_field_t; - -typedef struct stc_bt_pwc_stc_field -{ - __IO uint8_t OVIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t EDIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t OVIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t EDIE : 1; - __IO uint8_t ERR : 1; -} stc_bt_pwc_stc_field_t; - -typedef struct stc_bt_pwc_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwc_tmcr2_field_t; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* BTIOSEL03_MODULE register bit fields */ -typedef struct stc_btiosel03_btsel0123_field -{ - __IO uint8_t SEL01_0 : 1; - __IO uint8_t SEL01_1 : 1; - __IO uint8_t SEL01_2 : 1; - __IO uint8_t SEL01_3 : 1; - __IO uint8_t SEL23_0 : 1; - __IO uint8_t SEL23_1 : 1; - __IO uint8_t SEL23_2 : 1; - __IO uint8_t SEL23_3 : 1; -} stc_btiosel03_btsel0123_field_t; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* BTIOSEL47_MODULE register bit fields */ -typedef struct stc_btiosel47_btsel4567_field -{ - __IO uint8_t SEL45_0 : 1; - __IO uint8_t SEL45_1 : 1; - __IO uint8_t SEL45_2 : 1; - __IO uint8_t SEL45_3 : 1; - __IO uint8_t SEL67_0 : 1; - __IO uint8_t SEL67_1 : 1; - __IO uint8_t SEL67_2 : 1; - __IO uint8_t SEL67_3 : 1; -} stc_btiosel47_btsel4567_field_t; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* SBSSR_MODULE register bit fields */ -typedef struct stc_sbssr_btsssr_field -{ - __IO uint16_t SSR0 : 1; - __IO uint16_t SSR1 : 1; - __IO uint16_t SSR2 : 1; - __IO uint16_t SSR3 : 1; - __IO uint16_t SSR4 : 1; - __IO uint16_t SSR5 : 1; - __IO uint16_t SSR6 : 1; - __IO uint16_t SSR7 : 1; - __IO uint16_t SSR8 : 1; - __IO uint16_t SSR9 : 1; - __IO uint16_t SSR10 : 1; - __IO uint16_t SSR11 : 1; - __IO uint16_t SSR12 : 1; - __IO uint16_t SSR13 : 1; - __IO uint16_t SSR14 : 1; - __IO uint16_t SSR15 : 1; -} stc_sbssr_btsssr_field_t; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* QPRC_MODULE register bit fields */ -typedef struct stc_qprc_qicr_field -{ - __IO uint16_t QPCMIE : 1; - __IO uint16_t QPCMF : 1; - __IO uint16_t QPRCMIE : 1; - __IO uint16_t QPRCMF : 1; - __IO uint16_t OUZIE : 1; - __IO uint16_t UFDF : 1; - __IO uint16_t OFDF : 1; - __IO uint16_t ZIIF : 1; - __IO uint16_t CDCIE : 1; - __IO uint16_t CDCF : 1; - __IO uint16_t DIRPC : 1; - __IO uint16_t DIROU : 1; - __IO uint16_t QPCNRCMIE : 1; - __IO uint16_t QPCNRCMF : 1; -} stc_qprc_qicr_field_t; - -typedef struct stc_qprc_qicrl_field -{ - __IO uint8_t QPCMIE : 1; - __IO uint8_t QPCMF : 1; - __IO uint8_t QPRCMIE : 1; - __IO uint8_t QPRCMF : 1; - __IO uint8_t OUZIE : 1; - __IO uint8_t UFDF : 1; - __IO uint8_t OFDF : 1; - __IO uint8_t ZIIF : 1; -} stc_qprc_qicrl_field_t; - -typedef struct stc_qprc_qicrh_field -{ - __IO uint8_t CDCIE : 1; - __IO uint8_t CDCF : 1; - __IO uint8_t DIRPC : 1; - __IO uint8_t DIROU : 1; - __IO uint8_t QPCNRCMIE : 1; - __IO uint8_t QPCNRCMF : 1; -} stc_qprc_qicrh_field_t; - -typedef struct stc_qprc_qcr_field -{ - __IO uint16_t PCM0 : 1; - __IO uint16_t PCM1 : 1; - __IO uint16_t RCM0 : 1; - __IO uint16_t RCM1 : 1; - __IO uint16_t PSTP : 1; - __IO uint16_t CGSC : 1; - __IO uint16_t RSEL : 1; - __IO uint16_t SWAP : 1; - __IO uint16_t PCRM0 : 1; - __IO uint16_t PCRM1 : 1; - __IO uint16_t AES0 : 1; - __IO uint16_t AES1 : 1; - __IO uint16_t BES0 : 1; - __IO uint16_t BES1 : 1; - __IO uint16_t CGE0 : 1; - __IO uint16_t CGE1 : 1; -} stc_qprc_qcr_field_t; - -typedef struct stc_qprc_qcrl_field -{ - __IO uint8_t PCM0 : 1; - __IO uint8_t PCM1 : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t PSTP : 1; - __IO uint8_t CGSC : 1; - __IO uint8_t RSEL : 1; - __IO uint8_t SWAP : 1; -} stc_qprc_qcrl_field_t; - -typedef struct stc_qprc_qcrh_field -{ - __IO uint8_t PCRM0 : 1; - __IO uint8_t PCRM1 : 1; - __IO uint8_t AES0 : 1; - __IO uint8_t AES1 : 1; - __IO uint8_t BES0 : 1; - __IO uint8_t BES1 : 1; - __IO uint8_t CGE0 : 1; - __IO uint8_t CGE1 : 1; -} stc_qprc_qcrh_field_t; - -typedef struct stc_qprc_qecr_field -{ - __IO uint16_t ORNGMD : 1; - __IO uint16_t ORNGF : 1; - __IO uint16_t ORNGIE : 1; -} stc_qprc_qecr_field_t; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* ADC12_MODULE register bit fields */ -typedef struct stc_adc_adsr_field -{ - __IO uint8_t SCS : 1; - __IO uint8_t PCS : 1; - __IO uint8_t PCNS : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t FDAS : 1; - __IO uint8_t ADSTP : 1; -} stc_adc_adsr_field_t; - -typedef struct stc_adc_adcr_field -{ - __IO uint8_t OVRIE : 1; - __IO uint8_t CMPIE : 1; - __IO uint8_t PCIE : 1; - __IO uint8_t SCIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t CMPIF : 1; - __IO uint8_t PCIF : 1; - __IO uint8_t SCIF : 1; -} stc_adc_adcr_field_t; - -typedef struct stc_adc_sfns_field -{ - __IO uint8_t SFS0 : 1; - __IO uint8_t SFS1 : 1; - __IO uint8_t SFS2 : 1; - __IO uint8_t SFS3 : 1; -} stc_adc_sfns_field_t; - -typedef struct stc_adc_sccr_field -{ - __IO uint8_t SSTR : 1; - __IO uint8_t SHEN : 1; - __IO uint8_t RPT : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t SFCLR : 1; - __IO uint8_t SOVR : 1; - __IO uint8_t SFUL : 1; - __IO uint8_t SEMP : 1; -} stc_adc_sccr_field_t; - -typedef struct stc_adc_scfd_field -{ - __IO uint32_t SC0 : 1; - __IO uint32_t SC1 : 1; - __IO uint32_t SC2 : 1; - __IO uint32_t SC3 : 1; - __IO uint32_t SC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; - __IO uint32_t SD3 : 1; - __IO uint32_t SD4 : 1; - __IO uint32_t SD5 : 1; - __IO uint32_t SD6 : 1; - __IO uint32_t SD7 : 1; - __IO uint32_t SD8 : 1; - __IO uint32_t SD9 : 1; - __IO uint32_t SD10 : 1; - __IO uint32_t SD11 : 1; -} stc_adc_scfd_field_t; - -typedef struct stc_adc_scfdl_field -{ - __IO uint16_t SC0 : 1; - __IO uint16_t SC1 : 1; - __IO uint16_t SC2 : 1; - __IO uint16_t SC3 : 1; - __IO uint16_t SC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t INVL : 1; -} stc_adc_scfdl_field_t; - -typedef struct stc_adc_scfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t SD0 : 1; - __IO uint16_t SD1 : 1; - __IO uint16_t SD2 : 1; - __IO uint16_t SD3 : 1; - __IO uint16_t SD4 : 1; - __IO uint16_t SD5 : 1; - __IO uint16_t SD6 : 1; - __IO uint16_t SD7 : 1; - __IO uint16_t SD8 : 1; - __IO uint16_t SD9 : 1; - __IO uint16_t SD10 : 1; - __IO uint16_t SD11 : 1; -} stc_adc_scfdh_field_t; - -typedef struct stc_adc_scis23_field -{ - __IO uint16_t AN16 : 1; - __IO uint16_t AN17 : 1; - __IO uint16_t AN18 : 1; - __IO uint16_t AN19 : 1; - __IO uint16_t AN20 : 1; - __IO uint16_t AN21 : 1; - __IO uint16_t AN22 : 1; - __IO uint16_t AN23 : 1; - __IO uint16_t AN24 : 1; - __IO uint16_t AN25 : 1; - __IO uint16_t AN26 : 1; - __IO uint16_t AN27 : 1; - __IO uint16_t AN28 : 1; - __IO uint16_t AN29 : 1; - __IO uint16_t AN30 : 1; - __IO uint16_t AN31 : 1; -} stc_adc_scis23_field_t; - -typedef struct stc_adc_scis2_field -{ - __IO uint8_t AN16 : 1; - __IO uint8_t AN17 : 1; - __IO uint8_t AN18 : 1; - __IO uint8_t AN19 : 1; - __IO uint8_t AN20 : 1; - __IO uint8_t AN21 : 1; - __IO uint8_t AN22 : 1; - __IO uint8_t AN23 : 1; -} stc_adc_scis2_field_t; - -typedef struct stc_adc_scis3_field -{ - __IO uint8_t AN24 : 1; - __IO uint8_t AN25 : 1; - __IO uint8_t AN26 : 1; - __IO uint8_t AN27 : 1; - __IO uint8_t AN28 : 1; - __IO uint8_t AN29 : 1; - __IO uint8_t AN30 : 1; - __IO uint8_t AN31 : 1; -} stc_adc_scis3_field_t; - -typedef struct stc_adc_scis01_field -{ - __IO uint16_t AN0 : 1; - __IO uint16_t AN1 : 1; - __IO uint16_t AN2 : 1; - __IO uint16_t AN3 : 1; - __IO uint16_t AN4 : 1; - __IO uint16_t AN5 : 1; - __IO uint16_t AN6 : 1; - __IO uint16_t AN7 : 1; - __IO uint16_t AN8 : 1; - __IO uint16_t AN9 : 1; - __IO uint16_t AN10 : 1; - __IO uint16_t AN11 : 1; - __IO uint16_t AN12 : 1; - __IO uint16_t AN13 : 1; - __IO uint16_t AN14 : 1; - __IO uint16_t AN15 : 1; -} stc_adc_scis01_field_t; - -typedef struct stc_adc_scis0_field -{ - __IO uint8_t AN0 : 1; - __IO uint8_t AN1 : 1; - __IO uint8_t AN2 : 1; - __IO uint8_t AN3 : 1; - __IO uint8_t AN4 : 1; - __IO uint8_t AN5 : 1; - __IO uint8_t AN6 : 1; - __IO uint8_t AN7 : 1; -} stc_adc_scis0_field_t; - -typedef struct stc_adc_scis1_field -{ - __IO uint8_t AN8 : 1; - __IO uint8_t AN9 : 1; - __IO uint8_t AN10 : 1; - __IO uint8_t AN11 : 1; - __IO uint8_t AN12 : 1; - __IO uint8_t AN13 : 1; - __IO uint8_t AN14 : 1; - __IO uint8_t AN15 : 1; -} stc_adc_scis1_field_t; - -typedef struct stc_adc_pfns_field -{ - __IO uint8_t PFS0 : 1; - __IO uint8_t PFS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t TEST0 : 1; - __IO uint8_t TEST1 : 1; -} stc_adc_pfns_field_t; - -typedef struct stc_adc_pccr_field -{ - __IO uint8_t PSTR : 1; - __IO uint8_t PHEN : 1; - __IO uint8_t PEEN : 1; - __IO uint8_t ESCE : 1; - __IO uint8_t PFCLR : 1; - __IO uint8_t POVR : 1; - __IO uint8_t PFUL : 1; - __IO uint8_t PEMP : 1; -} stc_adc_pccr_field_t; - -typedef struct stc_adc_pcfd_field -{ - __IO uint32_t PC0 : 1; - __IO uint32_t PC1 : 1; - __IO uint32_t PC2 : 1; - __IO uint32_t PC3 : 1; - __IO uint32_t PC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t PD0 : 1; - __IO uint32_t PD1 : 1; - __IO uint32_t PD2 : 1; - __IO uint32_t PD3 : 1; - __IO uint32_t PD4 : 1; - __IO uint32_t PD5 : 1; - __IO uint32_t PD6 : 1; - __IO uint32_t PD7 : 1; - __IO uint32_t PD8 : 1; - __IO uint32_t PD9 : 1; - __IO uint32_t PD10 : 1; - __IO uint32_t PD11 : 1; -} stc_adc_pcfd_field_t; - -typedef struct stc_adc_pcfdl_field -{ - __IO uint16_t PC0 : 1; - __IO uint16_t PC1 : 1; - __IO uint16_t PC2 : 1; - __IO uint16_t PC3 : 1; - __IO uint16_t PC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - __IO uint16_t RS2 : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t INVL : 1; -} stc_adc_pcfdl_field_t; - -typedef struct stc_adc_pcfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t PD0 : 1; - __IO uint16_t PD1 : 1; - __IO uint16_t PD2 : 1; - __IO uint16_t PD3 : 1; - __IO uint16_t PD4 : 1; - __IO uint16_t PD5 : 1; - __IO uint16_t PD6 : 1; - __IO uint16_t PD7 : 1; - __IO uint16_t PD8 : 1; - __IO uint16_t PD9 : 1; - __IO uint16_t PD10 : 1; - __IO uint16_t PD11 : 1; -} stc_adc_pcfdh_field_t; - -typedef struct stc_adc_pcis_field -{ - __IO uint8_t P1A0 : 1; - __IO uint8_t P1A1 : 1; - __IO uint8_t P1A2 : 1; - __IO uint8_t P2A0 : 1; - __IO uint8_t P2A1 : 1; - __IO uint8_t P2A2 : 1; - __IO uint8_t P2A3 : 1; - __IO uint8_t P2A4 : 1; -} stc_adc_pcis_field_t; - -typedef struct stc_adc_cmpcr_field -{ - __IO uint8_t CCH0 : 1; - __IO uint8_t CCH1 : 1; - __IO uint8_t CCH2 : 1; - __IO uint8_t CCH3 : 1; - __IO uint8_t CCH4 : 1; - __IO uint8_t CMD0 : 1; - __IO uint8_t CMD1 : 1; - __IO uint8_t CMPEN : 1; -} stc_adc_cmpcr_field_t; - -typedef struct stc_adc_cmpd_field -{ - uint16_t RESERVED1 : 6; - __IO uint16_t CMAD2 : 1; - __IO uint16_t CMAD3 : 1; - __IO uint16_t CMAD4 : 1; - __IO uint16_t CMAD5 : 1; - __IO uint16_t CMAD6 : 1; - __IO uint16_t CMAD7 : 1; - __IO uint16_t CMAD8 : 1; - __IO uint16_t CMAD9 : 1; - __IO uint16_t CMAD10 : 1; - __IO uint16_t CMAD11 : 1; -} stc_adc_cmpd_field_t; - -typedef struct stc_adc_adss23_field -{ - __IO uint16_t TS16 : 1; - __IO uint16_t TS17 : 1; - __IO uint16_t TS18 : 1; - __IO uint16_t TS19 : 1; - __IO uint16_t TS20 : 1; - __IO uint16_t TS21 : 1; - __IO uint16_t TS22 : 1; - __IO uint16_t TS23 : 1; - __IO uint16_t TS24 : 1; - __IO uint16_t TS25 : 1; - __IO uint16_t TS26 : 1; - __IO uint16_t TS27 : 1; - __IO uint16_t TS28 : 1; - __IO uint16_t TS29 : 1; - __IO uint16_t TS30 : 1; - __IO uint16_t TS31 : 1; -} stc_adc_adss23_field_t; - -typedef struct stc_adc_adss2_field -{ - __IO uint8_t TS16 : 1; - __IO uint8_t TS17 : 1; - __IO uint8_t TS18 : 1; - __IO uint8_t TS19 : 1; - __IO uint8_t TS20 : 1; - __IO uint8_t TS21 : 1; - __IO uint8_t TS22 : 1; - __IO uint8_t TS23 : 1; -} stc_adc_adss2_field_t; - -typedef struct stc_adc_adss3_field -{ - __IO uint8_t TS24 : 1; - __IO uint8_t TS25 : 1; - __IO uint8_t TS26 : 1; - __IO uint8_t TS27 : 1; - __IO uint8_t TS28 : 1; - __IO uint8_t TS29 : 1; - __IO uint8_t TS30 : 1; - __IO uint8_t TS31 : 1; -} stc_adc_adss3_field_t; - -typedef struct stc_adc_adss01_field -{ - __IO uint16_t TS0 : 1; - __IO uint16_t TS1 : 1; - __IO uint16_t TS2 : 1; - __IO uint16_t TS3 : 1; - __IO uint16_t TS4 : 1; - __IO uint16_t TS5 : 1; - __IO uint16_t TS6 : 1; - __IO uint16_t TS7 : 1; - __IO uint16_t TS8 : 1; - __IO uint16_t TS9 : 1; - __IO uint16_t TS10 : 1; - __IO uint16_t TS11 : 1; - __IO uint16_t TS12 : 1; - __IO uint16_t TS13 : 1; - __IO uint16_t TS14 : 1; - __IO uint16_t TS15 : 1; -} stc_adc_adss01_field_t; - -typedef struct stc_adc_adss0_field -{ - __IO uint8_t TS0 : 1; - __IO uint8_t TS1 : 1; - __IO uint8_t TS2 : 1; - __IO uint8_t TS3 : 1; - __IO uint8_t TS4 : 1; - __IO uint8_t TS5 : 1; - __IO uint8_t TS6 : 1; - __IO uint8_t TS7 : 1; -} stc_adc_adss0_field_t; - -typedef struct stc_adc_adss1_field -{ - __IO uint8_t TS8 : 1; - __IO uint8_t TS9 : 1; - __IO uint8_t TS10 : 1; - __IO uint8_t TS11 : 1; - __IO uint8_t TS12 : 1; - __IO uint8_t TS13 : 1; - __IO uint8_t TS14 : 1; - __IO uint8_t TS15 : 1; -} stc_adc_adss1_field_t; - -typedef struct stc_adc_adst01_field -{ - __IO uint16_t ST10 : 1; - __IO uint16_t ST11 : 1; - __IO uint16_t ST12 : 1; - __IO uint16_t ST13 : 1; - __IO uint16_t ST14 : 1; - __IO uint16_t STX10 : 1; - __IO uint16_t STX11 : 1; - __IO uint16_t STX12 : 1; - __IO uint16_t ST00 : 1; - __IO uint16_t ST01 : 1; - __IO uint16_t ST02 : 1; - __IO uint16_t ST03 : 1; - __IO uint16_t ST04 : 1; - __IO uint16_t STX00 : 1; - __IO uint16_t STX01 : 1; - __IO uint16_t STX02 : 1; -} stc_adc_adst01_field_t; - -typedef struct stc_adc_adst1_field -{ - __IO uint8_t ST10 : 1; - __IO uint8_t ST11 : 1; - __IO uint8_t ST12 : 1; - __IO uint8_t ST13 : 1; - __IO uint8_t ST14 : 1; - __IO uint8_t STX10 : 1; - __IO uint8_t STX11 : 1; - __IO uint8_t STX12 : 1; -} stc_adc_adst1_field_t; - -typedef struct stc_adc_adst0_field -{ - __IO uint8_t ST00 : 1; - __IO uint8_t ST01 : 1; - __IO uint8_t ST02 : 1; - __IO uint8_t ST03 : 1; - __IO uint8_t ST04 : 1; - __IO uint8_t STX00 : 1; - __IO uint8_t STX01 : 1; - __IO uint8_t STX02 : 1; -} stc_adc_adst0_field_t; - -typedef struct stc_adc_adct_field -{ - __IO uint8_t CT0 : 1; - __IO uint8_t CT1 : 1; - __IO uint8_t CT2 : 1; - __IO uint8_t CT3 : 1; - __IO uint8_t CT4 : 1; - __IO uint8_t CT5 : 1; - __IO uint8_t CT6 : 1; - __IO uint8_t CT7 : 1; -} stc_adc_adct_field_t; - -typedef struct stc_adc_prtsl_field -{ - __IO uint8_t PRTSL0 : 1; - __IO uint8_t PRTSL1 : 1; - __IO uint8_t PRTSL2 : 1; - __IO uint8_t PRTSL3 : 1; -} stc_adc_prtsl_field_t; - -typedef struct stc_adc_sctsl_field -{ - __IO uint8_t SCTSL0 : 1; - __IO uint8_t SCTSL1 : 1; - __IO uint8_t SCTSL2 : 1; - __IO uint8_t SCTSL3 : 1; -} stc_adc_sctsl_field_t; - -typedef struct stc_adc_adcen_field -{ - __IO uint8_t ENBL : 1; - __IO uint8_t READY : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CYCLSL0 : 1; - __IO uint8_t CYCLSL1 : 1; -} stc_adc_adcen_field_t; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CRTRIM_MODULE register bit fields */ -typedef struct stc_crtrim_mcr_psr_field -{ - __IO uint8_t CSR0 : 1; - __IO uint8_t CSR1 : 1; -} stc_crtrim_mcr_psr_field_t; - -typedef struct stc_crtrim_mcr_ftrm_field -{ - __IO uint16_t TRD0 : 1; - __IO uint16_t TRD1 : 1; - __IO uint16_t TRD2 : 1; - __IO uint16_t TRD3 : 1; - __IO uint16_t TRD4 : 1; - __IO uint16_t TRD5 : 1; - __IO uint16_t TRD6 : 1; - __IO uint16_t TRD7 : 1; - __IO uint16_t TRD8 : 1; - __IO uint16_t TRD9 : 1; -} stc_crtrim_mcr_ftrm_field_t; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* EXTI_MODULE register bit fields */ -typedef struct stc_exti_enir_field -{ - __IO uint16_t EN0 : 1; - __IO uint16_t EN1 : 1; - __IO uint16_t EN2 : 1; - __IO uint16_t EN3 : 1; - __IO uint16_t EN4 : 1; - __IO uint16_t EN5 : 1; - __IO uint16_t EN6 : 1; - __IO uint16_t EN7 : 1; - __IO uint16_t EN8 : 1; - __IO uint16_t EN9 : 1; - __IO uint16_t EN10 : 1; - __IO uint16_t EN11 : 1; - __IO uint16_t EN12 : 1; - __IO uint16_t EN13 : 1; - __IO uint16_t EN14 : 1; - __IO uint16_t EN15 : 1; -} stc_exti_enir_field_t; - -typedef struct stc_exti_eirr_field -{ - __IO uint16_t ER0 : 1; - __IO uint16_t ER1 : 1; - __IO uint16_t ER2 : 1; - __IO uint16_t ER3 : 1; - __IO uint16_t ER4 : 1; - __IO uint16_t ER5 : 1; - __IO uint16_t ER6 : 1; - __IO uint16_t ER7 : 1; - __IO uint16_t ER8 : 1; - __IO uint16_t ER9 : 1; - __IO uint16_t ER10 : 1; - __IO uint16_t ER11 : 1; - __IO uint16_t ER12 : 1; - __IO uint16_t ER13 : 1; - __IO uint16_t ER14 : 1; - __IO uint16_t ER15 : 1; -} stc_exti_eirr_field_t; - -typedef struct stc_exti_eicl_field -{ - __IO uint16_t ECL0 : 1; - __IO uint16_t ECL1 : 1; - __IO uint16_t ECL2 : 1; - __IO uint16_t ECL3 : 1; - __IO uint16_t ECL4 : 1; - __IO uint16_t ECL5 : 1; - __IO uint16_t ECL6 : 1; - __IO uint16_t ECL7 : 1; - __IO uint16_t ECL8 : 1; - __IO uint16_t ECL9 : 1; - __IO uint16_t ECL10 : 1; - __IO uint16_t ECL11 : 1; - __IO uint16_t ECL12 : 1; - __IO uint16_t ECL13 : 1; - __IO uint16_t ECL14 : 1; - __IO uint16_t ECL15 : 1; -} stc_exti_eicl_field_t; - -typedef struct stc_exti_elvr_field -{ - __IO uint32_t LA0 : 1; - __IO uint32_t LB0 : 1; - __IO uint32_t LA1 : 1; - __IO uint32_t LB1 : 1; - __IO uint32_t LA2 : 1; - __IO uint32_t LB2 : 1; - __IO uint32_t LA3 : 1; - __IO uint32_t LB3 : 1; - __IO uint32_t LA4 : 1; - __IO uint32_t LB4 : 1; - __IO uint32_t LA5 : 1; - __IO uint32_t LB5 : 1; - __IO uint32_t LA6 : 1; - __IO uint32_t LB6 : 1; - __IO uint32_t LA7 : 1; - __IO uint32_t LB7 : 1; - __IO uint32_t LA8 : 1; - __IO uint32_t LB8 : 1; - __IO uint32_t LA9 : 1; - __IO uint32_t LB9 : 1; - __IO uint32_t LA10 : 1; - __IO uint32_t LB10 : 1; - __IO uint32_t LA11 : 1; - __IO uint32_t LB11 : 1; - __IO uint32_t LA12 : 1; - __IO uint32_t LB12 : 1; - __IO uint32_t LA13 : 1; - __IO uint32_t LB13 : 1; - __IO uint32_t LA14 : 1; - __IO uint32_t LB14 : 1; - __IO uint32_t LA15 : 1; - __IO uint32_t LB15 : 1; -} stc_exti_elvr_field_t; - -typedef struct stc_exti_nmirr_field -{ - __IO uint8_t NR0 : 1; -} stc_exti_nmirr_field_t; - -typedef struct stc_exti_nmicl_field -{ - __IO uint8_t NCL0 : 1; -} stc_exti_nmicl_field_t; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* INTREQ_MODULE register bit fields */ -typedef struct stc_intreq_drqsel_field -{ - __IO uint32_t DRQSEL0 : 1; - __IO uint32_t DRQSEL1 : 1; - __IO uint32_t DRQSEL2 : 1; - __IO uint32_t DRQSEL3 : 1; - __IO uint32_t DRQSEL4 : 1; - __IO uint32_t DRQSEL5 : 1; - __IO uint32_t DRQSEL6 : 1; - __IO uint32_t DRQSEL7 : 1; - __IO uint32_t DRQSEL8 : 1; - __IO uint32_t DRQSEL9 : 1; - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; - __IO uint32_t DRQSEL15 : 1; - __IO uint32_t DRQSEL16 : 1; - __IO uint32_t DRQSEL17 : 1; - __IO uint32_t DRQSEL18 : 1; - __IO uint32_t DRQSEL19 : 1; - __IO uint32_t DRQSEL20 : 1; - __IO uint32_t DRQSEL21 : 1; - __IO uint32_t DRQSEL22 : 1; - __IO uint32_t DRQSEL23 : 1; - __IO uint32_t DRQSEL24 : 1; - __IO uint32_t DRQSEL25 : 1; - __IO uint32_t DRQSEL26 : 1; - __IO uint32_t DRQSEL27 : 1; - __IO uint32_t DRQSEL28 : 1; - __IO uint32_t DRQSEL29 : 1; - __IO uint32_t DRQSEL30 : 1; - __IO uint32_t DRQSEL31 : 1; -} stc_intreq_drqsel_field_t; - -typedef struct stc_intreq_exc02mon_field -{ - __IO uint32_t NMI : 1; - __IO uint32_t HWINT : 1; -} stc_intreq_exc02mon_field_t; - -typedef struct stc_intreq_irq00mon_field -{ - __IO uint32_t FCSINT : 1; -} stc_intreq_irq00mon_field_t; - -typedef struct stc_intreq_irq01mon_field -{ - __IO uint32_t SWWDTINT : 1; -} stc_intreq_irq01mon_field_t; - -typedef struct stc_intreq_irq02mon_field -{ - __IO uint32_t LVDINT : 1; -} stc_intreq_irq02mon_field_t; - -typedef struct stc_intreq_irq03mon_field -{ - __IO uint32_t WAVE0INT0 : 1; - __IO uint32_t WAVE0INT1 : 1; - __IO uint32_t WAVE0INT2 : 1; - __IO uint32_t WAVE0INT3 : 1; - __IO uint32_t WAVE1INT0 : 1; - __IO uint32_t WAVE1INT1 : 1; - __IO uint32_t WAVE1INT2 : 1; - __IO uint32_t WAVE1INT3 : 1; -} stc_intreq_irq03mon_field_t; - -typedef struct stc_intreq_irq04mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; -} stc_intreq_irq04mon_field_t; - -typedef struct stc_intreq_irq05mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; -} stc_intreq_irq05mon_field_t; - -typedef struct stc_intreq_irq06mon_field -{ - __IO uint32_t TIMINT0 : 1; - __IO uint32_t TIMINT1 : 1; - __IO uint32_t QUD0INT0 : 1; - __IO uint32_t QUD0INT1 : 1; - __IO uint32_t QUD0INT2 : 1; - __IO uint32_t QUD0INT3 : 1; - __IO uint32_t QUD0INT4 : 1; - __IO uint32_t QUD0INT5 : 1; - __IO uint32_t QUD1INT0 : 1; - __IO uint32_t QUD1INT1 : 1; - __IO uint32_t QUD1INT2 : 1; - __IO uint32_t QUD1INT3 : 1; - __IO uint32_t QUD1INT4 : 1; - __IO uint32_t QUD1INT5 : 1; -} stc_intreq_irq06mon_field_t; - -typedef struct stc_intreq_irq07mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq07mon_field_t; - -typedef struct stc_intreq_irq08mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq08mon_field_t; - -typedef struct stc_intreq_irq09mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq09mon_field_t; - -typedef struct stc_intreq_irq10mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq10mon_field_t; - -typedef struct stc_intreq_irq11mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq11mon_field_t; - -typedef struct stc_intreq_irq12mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq12mon_field_t; - -typedef struct stc_intreq_irq13mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq13mon_field_t; - -typedef struct stc_intreq_irq14mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq14mon_field_t; - -typedef struct stc_intreq_irq15mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq15mon_field_t; - -typedef struct stc_intreq_irq16mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq16mon_field_t; - -typedef struct stc_intreq_irq17mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq17mon_field_t; - -typedef struct stc_intreq_irq18mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq18mon_field_t; - -typedef struct stc_intreq_irq19mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq19mon_field_t; - -typedef struct stc_intreq_irq20mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq20mon_field_t; - -typedef struct stc_intreq_irq21mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq21mon_field_t; - -typedef struct stc_intreq_irq22mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq22mon_field_t; - -typedef struct stc_intreq_irq23mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; - __IO uint32_t PPGINT3 : 1; - __IO uint32_t PPGINT4 : 1; - __IO uint32_t PPGINT5 : 1; -} stc_intreq_irq23mon_field_t; - -typedef struct stc_intreq_irq24mon_field -{ - __IO uint32_t MOSCINT : 1; - __IO uint32_t SOSCINT : 1; - __IO uint32_t MPLLINT : 1; - __IO uint32_t UPLLINT : 1; - __IO uint32_t WCINT : 1; -} stc_intreq_irq24mon_field_t; - -typedef struct stc_intreq_irq25mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq25mon_field_t; - -typedef struct stc_intreq_irq26mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq26mon_field_t; - -typedef struct stc_intreq_irq27mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq27mon_field_t; - -typedef struct stc_intreq_irq28mon_field -{ - __IO uint32_t FRT0INT0 : 1; - __IO uint32_t FRT0INT1 : 1; - __IO uint32_t FRT0INT2 : 1; - __IO uint32_t FRT0INT3 : 1; - __IO uint32_t FRT0INT4 : 1; - __IO uint32_t FRT0INT5 : 1; - __IO uint32_t FRT1INT0 : 1; - __IO uint32_t FRT1INT1 : 1; - __IO uint32_t FRT1INT2 : 1; - __IO uint32_t FRT1INT3 : 1; - __IO uint32_t FRT1INT4 : 1; - __IO uint32_t FRT1INT5 : 1; -} stc_intreq_irq28mon_field_t; - -typedef struct stc_intreq_irq29mon_field -{ - __IO uint32_t ICU0INT0 : 1; - __IO uint32_t ICU0INT1 : 1; - __IO uint32_t ICU0INT2 : 1; - __IO uint32_t ICU0INT3 : 1; - __IO uint32_t ICU1INT0 : 1; - __IO uint32_t ICU1INT1 : 1; - __IO uint32_t ICU1INT2 : 1; - __IO uint32_t ICU1INT3 : 1; -} stc_intreq_irq29mon_field_t; - -typedef struct stc_intreq_irq30mon_field -{ - __IO uint32_t OCU0INT0 : 1; - __IO uint32_t OCU0INT1 : 1; - __IO uint32_t OCU0INT2 : 1; - __IO uint32_t OCU0INT3 : 1; - __IO uint32_t OCU0INT4 : 1; - __IO uint32_t OCU0INT5 : 1; - __IO uint32_t OCU1INT0 : 1; - __IO uint32_t OCU1INT1 : 1; - __IO uint32_t OCU1INT2 : 1; - __IO uint32_t OCU1INT3 : 1; - __IO uint32_t OCU1INT4 : 1; - __IO uint32_t OCU1INT5 : 1; -} stc_intreq_irq30mon_field_t; - -typedef struct stc_intreq_irq31mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; - __IO uint32_t BTINT8 : 1; - __IO uint32_t BTINT9 : 1; - __IO uint32_t BTINT10 : 1; - __IO uint32_t BTINT11 : 1; - __IO uint32_t BTINT12 : 1; - __IO uint32_t BTINT13 : 1; - __IO uint32_t BTINT14 : 1; - __IO uint32_t BTINT15 : 1; -} stc_intreq_irq31mon_field_t; - -typedef struct stc_intreq_irq32mon_field -{ - __IO uint32_t CANINT : 1; -} stc_intreq_irq32mon_field_t; - -typedef struct stc_intreq_irq33mon_field -{ - __IO uint32_t CANINT : 1; -} stc_intreq_irq33mon_field_t; - -typedef struct stc_intreq_irq34mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; -} stc_intreq_irq34mon_field_t; - -typedef struct stc_intreq_irq35mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; - __IO uint32_t USB0INT5 : 1; -} stc_intreq_irq35mon_field_t; - -typedef struct stc_intreq_irq38mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq38mon_field_t; - -typedef struct stc_intreq_irq39mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq39mon_field_t; - -typedef struct stc_intreq_irq40mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq40mon_field_t; - -typedef struct stc_intreq_irq41mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq41mon_field_t; - -typedef struct stc_intreq_irq42mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq42mon_field_t; - -typedef struct stc_intreq_irq43mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq43mon_field_t; - -typedef struct stc_intreq_irq44mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq44mon_field_t; - -typedef struct stc_intreq_irq45mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq45mon_field_t; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* GPIO_MODULE register bit fields */ -typedef struct stc_gpio_pfr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr0_field_t; - -typedef struct stc_gpio_pfr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr1_field_t; - -typedef struct stc_gpio_pfr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pfr2_field_t; - -typedef struct stc_gpio_pfr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr3_field_t; - -typedef struct stc_gpio_pfr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pfr4_field_t; - -typedef struct stc_gpio_pfr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pfr5_field_t; - -typedef struct stc_gpio_pfr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pfr6_field_t; - -typedef struct stc_gpio_pfr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; -} stc_gpio_pfr7_field_t; - -typedef struct stc_gpio_pfr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; -} stc_gpio_pfr8_field_t; - -typedef struct stc_gpio_pcr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr0_field_t; - -typedef struct stc_gpio_pcr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr1_field_t; - -typedef struct stc_gpio_pcr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pcr2_field_t; - -typedef struct stc_gpio_pcr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr3_field_t; - -typedef struct stc_gpio_pcr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pcr4_field_t; - -typedef struct stc_gpio_pcr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pcr5_field_t; - -typedef struct stc_gpio_pcr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pcr6_field_t; - -typedef struct stc_gpio_pcr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; -} stc_gpio_pcr7_field_t; - -typedef struct stc_gpio_ddr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr0_field_t; - -typedef struct stc_gpio_ddr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr1_field_t; - -typedef struct stc_gpio_ddr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_ddr2_field_t; - -typedef struct stc_gpio_ddr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr3_field_t; - -typedef struct stc_gpio_ddr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_ddr4_field_t; - -typedef struct stc_gpio_ddr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_ddr5_field_t; - -typedef struct stc_gpio_ddr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_ddr6_field_t; - -typedef struct stc_gpio_ddr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; -} stc_gpio_ddr7_field_t; - -typedef struct stc_gpio_ddr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; -} stc_gpio_ddr8_field_t; - -typedef struct stc_gpio_pdir0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir0_field_t; - -typedef struct stc_gpio_pdir1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir1_field_t; - -typedef struct stc_gpio_pdir2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pdir2_field_t; - -typedef struct stc_gpio_pdir3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir3_field_t; - -typedef struct stc_gpio_pdir4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdir4_field_t; - -typedef struct stc_gpio_pdir5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pdir5_field_t; - -typedef struct stc_gpio_pdir6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pdir6_field_t; - -typedef struct stc_gpio_pdir7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; -} stc_gpio_pdir7_field_t; - -typedef struct stc_gpio_pdir8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; -} stc_gpio_pdir8_field_t; - -typedef struct stc_gpio_pdor0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor0_field_t; - -typedef struct stc_gpio_pdor1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor1_field_t; - -typedef struct stc_gpio_pdor2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pdor2_field_t; - -typedef struct stc_gpio_pdor3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor3_field_t; - -typedef struct stc_gpio_pdor4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdor4_field_t; - -typedef struct stc_gpio_pdor5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pdor5_field_t; - -typedef struct stc_gpio_pdor6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; -} stc_gpio_pdor6_field_t; - -typedef struct stc_gpio_pdor7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; -} stc_gpio_pdor7_field_t; - -typedef struct stc_gpio_pdor8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; -} stc_gpio_pdor8_field_t; - -typedef struct stc_gpio_ade_field -{ - __IO uint32_t AN0 : 1; - __IO uint32_t AN1 : 1; - __IO uint32_t AN2 : 1; - __IO uint32_t AN3 : 1; - __IO uint32_t AN4 : 1; - __IO uint32_t AN5 : 1; - __IO uint32_t AN6 : 1; - __IO uint32_t AN7 : 1; - __IO uint32_t AN8 : 1; - __IO uint32_t AN9 : 1; - __IO uint32_t ANA : 1; - __IO uint32_t ANB : 1; - __IO uint32_t ANC : 1; - __IO uint32_t AND : 1; - __IO uint32_t ANE : 1; - __IO uint32_t ANF : 1; -} stc_gpio_ade_field_t; - -typedef struct stc_gpio_spsr_field -{ - __IO uint32_t SUBXC : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t USB0C : 1; -} stc_gpio_spsr_field_t; - -typedef struct stc_gpio_epfr00_field -{ - __IO uint32_t NMIS : 1; - __IO uint32_t CROUTE : 1; - uint32_t RESERVED1 : 7; - __IO uint32_t USB0PE : 1; - uint32_t RESERVED2 : 6; - __IO uint32_t JTAGEN0B : 1; - __IO uint32_t JTAGEN1S : 1; - uint32_t RESERVED3 : 6; - __IO uint32_t TRC0E : 1; - __IO uint32_t TRC1E : 1; -} stc_gpio_epfr00_field_t; - -typedef struct stc_gpio_epfr01_field -{ - __IO uint32_t RTO00E0 : 1; - __IO uint32_t RTO00E1 : 1; - __IO uint32_t RTO01E0 : 1; - __IO uint32_t RTO01E1 : 1; - __IO uint32_t RTO02E0 : 1; - __IO uint32_t RTO02E1 : 1; - __IO uint32_t RTO03E0 : 1; - __IO uint32_t RTO03E1 : 1; - __IO uint32_t RTO04E0 : 1; - __IO uint32_t RTO04E1 : 1; - __IO uint32_t RTO05E0 : 1; - __IO uint32_t RTO05E1 : 1; - __IO uint32_t DTTI0C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI0S0 : 1; - __IO uint32_t DTTI0S1 : 1; - __IO uint32_t FRCK0S0 : 1; - __IO uint32_t FRCK0S1 : 1; - __IO uint32_t IC00S0 : 1; - __IO uint32_t IC00S1 : 1; - __IO uint32_t IC00S2 : 1; - __IO uint32_t IC01S0 : 1; - __IO uint32_t IC01S1 : 1; - __IO uint32_t IC01S2 : 1; - __IO uint32_t IC02S0 : 1; - __IO uint32_t IC02S1 : 1; - __IO uint32_t IC02S2 : 1; - __IO uint32_t IC03S0 : 1; - __IO uint32_t IC03S1 : 1; - __IO uint32_t IC03S2 : 1; -} stc_gpio_epfr01_field_t; - -typedef struct stc_gpio_epfr02_field -{ - __IO uint32_t RTO10E0 : 1; - __IO uint32_t RTO10E1 : 1; - __IO uint32_t RTO11E0 : 1; - __IO uint32_t RTO11E1 : 1; - __IO uint32_t RTO12E0 : 1; - __IO uint32_t RTO12E1 : 1; - __IO uint32_t RTO13E0 : 1; - __IO uint32_t RTO13E1 : 1; - __IO uint32_t RTO14E0 : 1; - __IO uint32_t RTO14E1 : 1; - __IO uint32_t RTO15E0 : 1; - __IO uint32_t RTO15E1 : 1; - __IO uint32_t DTTI1C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI1S0 : 1; - __IO uint32_t DTTI1S1 : 1; - __IO uint32_t FRCK1S0 : 1; - __IO uint32_t FRCK1S1 : 1; - __IO uint32_t IC10S0 : 1; - __IO uint32_t IC10S1 : 1; - __IO uint32_t IC10S2 : 1; - __IO uint32_t IC11S0 : 1; - __IO uint32_t IC11S1 : 1; - __IO uint32_t IC11S2 : 1; - __IO uint32_t IC12S0 : 1; - __IO uint32_t IC12S1 : 1; - __IO uint32_t IC12S2 : 1; - __IO uint32_t IC13S0 : 1; - __IO uint32_t IC13S1 : 1; - __IO uint32_t IC13S2 : 1; -} stc_gpio_epfr02_field_t; - -typedef struct stc_gpio_epfr04_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA0E0 : 1; - __IO uint32_t TIOA0E1 : 1; - __IO uint32_t TIOB0S0 : 1; - __IO uint32_t TIOB0S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA1S0 : 1; - __IO uint32_t TIOA1S1 : 1; - __IO uint32_t TIOA1E0 : 1; - __IO uint32_t TIOA1E1 : 1; - __IO uint32_t TIOB1S0 : 1; - __IO uint32_t TIOB1S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA2E0 : 1; - __IO uint32_t TIOA2E1 : 1; - __IO uint32_t TIOB2S0 : 1; - __IO uint32_t TIOB2S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA3S0 : 1; - __IO uint32_t TIOA3S1 : 1; - __IO uint32_t TIOA3E0 : 1; - __IO uint32_t TIOA3E1 : 1; - __IO uint32_t TIOB3S0 : 1; - __IO uint32_t TIOB3S1 : 1; -} stc_gpio_epfr04_field_t; - -typedef struct stc_gpio_epfr05_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA4E0 : 1; - __IO uint32_t TIOA4E1 : 1; - __IO uint32_t TIOB4S0 : 1; - __IO uint32_t TIOB4S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA5S0 : 1; - __IO uint32_t TIOA5S1 : 1; - __IO uint32_t TIOA5E0 : 1; - __IO uint32_t TIOA5E1 : 1; - __IO uint32_t TIOB5S0 : 1; - __IO uint32_t TIOB5S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA6E0 : 1; - __IO uint32_t TIOA6E1 : 1; - __IO uint32_t TIOB6S0 : 1; - __IO uint32_t TIOB6S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA7S0 : 1; - __IO uint32_t TIOA7S1 : 1; - __IO uint32_t TIOA7E0 : 1; - __IO uint32_t TIOA7E1 : 1; - __IO uint32_t TIOB7S0 : 1; - __IO uint32_t TIOB7S1 : 1; -} stc_gpio_epfr05_field_t; - -typedef struct stc_gpio_epfr06_field -{ - __IO uint32_t EINT00S0 : 1; - __IO uint32_t EINT00S1 : 1; - __IO uint32_t EINT01S0 : 1; - __IO uint32_t EINT01S1 : 1; - __IO uint32_t EINT02S0 : 1; - __IO uint32_t EINT02S1 : 1; - __IO uint32_t EINT03S0 : 1; - __IO uint32_t EINT03S1 : 1; - __IO uint32_t EINT04S0 : 1; - __IO uint32_t EINT04S1 : 1; - __IO uint32_t EINT05S0 : 1; - __IO uint32_t EINT05S1 : 1; - __IO uint32_t EINT06S0 : 1; - __IO uint32_t EINT06S1 : 1; - __IO uint32_t EINT07S0 : 1; - __IO uint32_t EINT07S1 : 1; - __IO uint32_t EINT08S0 : 1; - __IO uint32_t EINT08S1 : 1; - __IO uint32_t EINT09S0 : 1; - __IO uint32_t EINT09S1 : 1; - __IO uint32_t EINT10S0 : 1; - __IO uint32_t EINT10S1 : 1; - __IO uint32_t EINT11S0 : 1; - __IO uint32_t EINT11S1 : 1; - __IO uint32_t EINT12S0 : 1; - __IO uint32_t EINT12S1 : 1; - __IO uint32_t EINT13S0 : 1; - __IO uint32_t EINT13S1 : 1; - __IO uint32_t EINT14S0 : 1; - __IO uint32_t EINT14S1 : 1; - __IO uint32_t EINT15S0 : 1; - __IO uint32_t EINT15S1 : 1; -} stc_gpio_epfr06_field_t; - -typedef struct stc_gpio_epfr07_field -{ - uint32_t RESERVED1 : 4; - __IO uint32_t SIN0S0 : 1; - __IO uint32_t SIN0S1 : 1; - __IO uint32_t SOT0B0 : 1; - __IO uint32_t SOT0B1 : 1; - __IO uint32_t SCK0B0 : 1; - __IO uint32_t SCK0B1 : 1; - __IO uint32_t SIN1S0 : 1; - __IO uint32_t SIN1S1 : 1; - __IO uint32_t SOT1B0 : 1; - __IO uint32_t SOT1B1 : 1; - __IO uint32_t SCK1B0 : 1; - __IO uint32_t SCK1B1 : 1; - __IO uint32_t SIN2S0 : 1; - __IO uint32_t SIN2S1 : 1; - __IO uint32_t SOT2B0 : 1; - __IO uint32_t SOT2B1 : 1; - __IO uint32_t SCK2B0 : 1; - __IO uint32_t SCK2B1 : 1; - __IO uint32_t SIN3S0 : 1; - __IO uint32_t SIN3S1 : 1; - __IO uint32_t SOT3B0 : 1; - __IO uint32_t SOT3B1 : 1; - __IO uint32_t SCK3B0 : 1; - __IO uint32_t SCK3B1 : 1; -} stc_gpio_epfr07_field_t; - -typedef struct stc_gpio_epfr08_field -{ - __IO uint32_t RTS4E0 : 1; - __IO uint32_t RTS4E1 : 1; - __IO uint32_t CTS4S0 : 1; - __IO uint32_t CTS4S1 : 1; - __IO uint32_t SIN4S0 : 1; - __IO uint32_t SIN4S1 : 1; - __IO uint32_t SOT4B0 : 1; - __IO uint32_t SOT4B1 : 1; - __IO uint32_t SCK4B0 : 1; - __IO uint32_t SCK4B1 : 1; - __IO uint32_t SIN5S0 : 1; - __IO uint32_t SIN5S1 : 1; - __IO uint32_t SOT5B0 : 1; - __IO uint32_t SOT5B1 : 1; - __IO uint32_t SCK5B0 : 1; - __IO uint32_t SCK5B1 : 1; - __IO uint32_t SIN6S0 : 1; - __IO uint32_t SIN6S1 : 1; - __IO uint32_t SOT6B0 : 1; - __IO uint32_t SOT6B1 : 1; - __IO uint32_t SCK6B0 : 1; - __IO uint32_t SCK6B1 : 1; - __IO uint32_t SIN7S0 : 1; - __IO uint32_t SIN7S1 : 1; - __IO uint32_t SOT7B0 : 1; - __IO uint32_t SOT7B1 : 1; - __IO uint32_t SCK7B0 : 1; - __IO uint32_t SCK7B1 : 1; -} stc_gpio_epfr08_field_t; - -typedef struct stc_gpio_epfr09_field -{ - __IO uint32_t QAIN0S0 : 1; - __IO uint32_t QAIN0S1 : 1; - __IO uint32_t QBIN0S0 : 1; - __IO uint32_t QBIN0S1 : 1; - __IO uint32_t QZIN0S0 : 1; - __IO uint32_t QZIN0S1 : 1; - __IO uint32_t QAIN1S0 : 1; - __IO uint32_t QAIN1S1 : 1; - __IO uint32_t QBIN1S0 : 1; - __IO uint32_t QBIN1S1 : 1; - __IO uint32_t QZIN1S0 : 1; - __IO uint32_t QZIN1S1 : 1; - __IO uint32_t ADTRG0S0 : 1; - __IO uint32_t ADTRG0S1 : 1; - __IO uint32_t ADTRG0S2 : 1; - __IO uint32_t ADTRG0S3 : 1; - __IO uint32_t ADTRG1S0 : 1; - __IO uint32_t ADTRG1S1 : 1; - __IO uint32_t ADTRG1S2 : 1; - __IO uint32_t ADTRG1S3 : 1; - __IO uint32_t ADTRG2S0 : 1; - __IO uint32_t ADTRG2S1 : 1; - __IO uint32_t ADTRG2S2 : 1; - __IO uint32_t ADTRG2S3 : 1; - __IO uint32_t CRX0S0 : 1; - __IO uint32_t CRX0S1 : 1; - __IO uint32_t CTX0E0 : 1; - __IO uint32_t CTX0E1 : 1; - __IO uint32_t CRX1S0 : 1; - __IO uint32_t CRX1S1 : 1; - __IO uint32_t CTX1E0 : 1; - __IO uint32_t CTX1E1 : 1; -} stc_gpio_epfr09_field_t; - -typedef struct stc_gpio_epfr10_field -{ - __IO uint32_t UEDEFB : 1; - __IO uint32_t UEDTHB : 1; - __IO uint32_t TESTB : 1; - __IO uint32_t UEWEXE : 1; - __IO uint32_t UEDQME : 1; - __IO uint32_t UEOEXE : 1; - __IO uint32_t UEFLSE : 1; - __IO uint32_t UECS1E : 1; - __IO uint32_t UECS2E : 1; - __IO uint32_t UECS3E : 1; - __IO uint32_t UECS4E : 1; - __IO uint32_t UECS5E : 1; - __IO uint32_t UECS6E : 1; - __IO uint32_t UECS7E : 1; - __IO uint32_t UEAOOE : 1; - __IO uint32_t UEA08E : 1; - __IO uint32_t UEA09E : 1; - __IO uint32_t UEA10E : 1; - __IO uint32_t UEA11E : 1; - __IO uint32_t UEA12E : 1; - __IO uint32_t UEA13E : 1; - __IO uint32_t UEA14E : 1; - __IO uint32_t UEA15E : 1; - __IO uint32_t UEA16E : 1; - __IO uint32_t UEA17E : 1; - __IO uint32_t UEA18E : 1; - __IO uint32_t UEA19E : 1; - __IO uint32_t UEA20E : 1; - __IO uint32_t UEA21E : 1; - __IO uint32_t UEA22E : 1; - __IO uint32_t UEA23E : 1; - __IO uint32_t UEA24E : 1; -} stc_gpio_epfr10_field_t; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* LVD_MODULE register bit fields */ -typedef struct stc_lvd_lvd_ctl_field -{ - uint8_t RESERVED1 : 2; - __IO uint8_t SVHI0 : 1; - __IO uint8_t SVHI1 : 1; - __IO uint8_t SVHI2 : 1; - __IO uint8_t SVHI3 : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t LVDIE : 1; -} stc_lvd_lvd_ctl_field_t; - -typedef struct stc_lvd_lvd_str_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIR : 1; -} stc_lvd_lvd_str_field_t; - -typedef struct stc_lvd_lvd_clr_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDCL : 1; -} stc_lvd_lvd_clr_field_t; - -typedef struct stc_lvd_lvd_str2_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIRDY : 1; -} stc_lvd_lvd_str2_field_t; - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USBCLK register bit fields */ -typedef struct stc_usbclk_uccr_field -{ - __IO uint8_t UCEN : 1; - __IO uint8_t UCSEL : 1; -} stc_usbclk_uccr_field_t; - -typedef struct stc_usbclk_upcr1_field -{ - __IO uint8_t UPLLEN : 1; - __IO uint8_t UPINC : 1; -} stc_usbclk_upcr1_field_t; - -typedef struct stc_usbclk_upcr2_field -{ - __IO uint8_t UPOWT0 : 1; - __IO uint8_t UPOWT1 : 1; - __IO uint8_t UPOWT2 : 1; -} stc_usbclk_upcr2_field_t; - -typedef struct stc_usbclk_upcr3_field -{ - __IO uint8_t UPLLK0 : 1; - __IO uint8_t UPLLK1 : 1; - __IO uint8_t UPLLK2 : 1; - __IO uint8_t UPLLK3 : 1; - __IO uint8_t UPLLK4 : 1; -} stc_usbclk_upcr3_field_t; - -typedef struct stc_usbclk_upcr4_field -{ - __IO uint8_t UPLLN0 : 1; - __IO uint8_t UPLLN1 : 1; - __IO uint8_t UPLLN2 : 1; - __IO uint8_t UPLLN3 : 1; - __IO uint8_t UPLLN4 : 1; -} stc_usbclk_upcr4_field_t; - -typedef struct stc_usbclk_up_str_field -{ - __IO uint8_t UPRDY : 1; -} stc_usbclk_up_str_field_t; - -typedef struct stc_usbclk_upint_enr_field -{ - __IO uint8_t UPCSE : 1; -} stc_usbclk_upint_enr_field_t; - -typedef struct stc_usbclk_upint_clr_field -{ - __IO uint8_t UPCSC : 1; -} stc_usbclk_upint_clr_field_t; - -typedef struct stc_usbclk_upint_str_field -{ - __IO uint8_t UPCSI : 1; -} stc_usbclk_upint_str_field_t; - -typedef struct stc_usbclk_usben_field -{ - __IO uint8_t USBEN : 1; -} stc_usbclk_usben_field_t; - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CANPRE_MODULE register bit fields */ -typedef struct stc_canpre_canpre_field -{ - __IO uint8_t CANPRE0 : 1; - __IO uint8_t CANPRE1 : 1; - __IO uint8_t CANPRE2 : 1; - __IO uint8_t CANPRE3 : 1; -} stc_canpre_canpre_field_t; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* MFS03_UART_MODULE register bit fields */ -typedef struct stc_mfs03_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_uart_smr_field_t; - -typedef struct stc_mfs03_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs03_uart_scr_field_t; - -typedef struct stc_mfs03_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs03_uart_escr_field_t; - -typedef struct stc_mfs03_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_uart_ssr_field_t; - -typedef struct stc_mfs03_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_rdr_field_t; - -typedef struct stc_mfs03_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_tdr_field_t; - -typedef struct stc_mfs03_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_uart_bgr_field_t; - -typedef struct stc_mfs03_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_uart_bgr1_field_t; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* MFS03_CSIO_MODULE register bit fields */ -typedef struct stc_mfs03_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_csio_smr_field_t; - -typedef struct stc_mfs03_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_csio_scr_field_t; - -typedef struct stc_mfs03_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs03_csio_escr_field_t; - -typedef struct stc_mfs03_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs03_csio_ssr_field_t; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* MFS03_LIN_MODULE register bit fields */ -typedef struct stc_mfs03_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_lin_smr_field_t; - -typedef struct stc_mfs03_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_lin_scr_field_t; - -typedef struct stc_mfs03_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs03_lin_escr_field_t; - -typedef struct stc_mfs03_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_lin_ssr_field_t; - -typedef struct stc_mfs03_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_lin_bgr_field_t; - -typedef struct stc_mfs03_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_lin_bgr1_field_t; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* MFS03_I2C_MODULE register bit fields */ -typedef struct stc_mfs03_i2c_smr_field -{ - __IO uint8_t ITST0 : 1; - __IO uint8_t ITST1 : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_i2c_smr_field_t; - -typedef struct stc_mfs03_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs03_i2c_ibcr_field_t; - -typedef struct stc_mfs03_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs03_i2c_ibsr_field_t; - -typedef struct stc_mfs03_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs03_i2c_ssr_field_t; - -typedef struct stc_mfs03_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs03_i2c_isba_field_t; - -typedef struct stc_mfs03_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs03_i2c_ismk_field_t; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* MFS47_UART_MODULE register bit fields */ -typedef struct stc_mfs47_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_uart_smr_field_t; - -typedef struct stc_mfs47_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs47_uart_scr_field_t; - -typedef struct stc_mfs47_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs47_uart_escr_field_t; - -typedef struct stc_mfs47_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_uart_ssr_field_t; - -typedef struct stc_mfs47_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_rdr_field_t; - -typedef struct stc_mfs47_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_tdr_field_t; - -typedef struct stc_mfs47_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_uart_bgr_field_t; - -typedef struct stc_mfs47_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_uart_bgr1_field_t; - -typedef struct stc_mfs47_uart_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_uart_fcr_field_t; - -typedef struct stc_mfs47_uart_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_uart_fcr0_field_t; - -typedef struct stc_mfs47_uart_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_uart_fcr1_field_t; - -typedef struct stc_mfs47_uart_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_uart_fbyte_field_t; - -typedef struct stc_mfs47_uart_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_uart_fbyte1_field_t; - -typedef struct stc_mfs47_uart_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_uart_fbyte2_field_t; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* MFS47_CSIO_MODULE register bit fields */ -typedef struct stc_mfs47_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_csio_smr_field_t; - -typedef struct stc_mfs47_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_csio_scr_field_t; - -typedef struct stc_mfs47_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs47_csio_escr_field_t; - -typedef struct stc_mfs47_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs47_csio_ssr_field_t; - -typedef struct stc_mfs47_csio_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_csio_fcr_field_t; - -typedef struct stc_mfs47_csio_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_csio_fcr0_field_t; - -typedef struct stc_mfs47_csio_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_csio_fcr1_field_t; - -typedef struct stc_mfs47_csio_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_csio_fbyte_field_t; - -typedef struct stc_mfs47_csio_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_csio_fbyte1_field_t; - -typedef struct stc_mfs47_csio_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_csio_fbyte2_field_t; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* MFS47_LIN_MODULE register bit fields */ -typedef struct stc_mfs47_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_lin_smr_field_t; - -typedef struct stc_mfs47_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_lin_scr_field_t; - -typedef struct stc_mfs47_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs47_lin_escr_field_t; - -typedef struct stc_mfs47_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_lin_ssr_field_t; - -typedef struct stc_mfs47_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_lin_bgr_field_t; - -typedef struct stc_mfs47_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_lin_bgr1_field_t; - -typedef struct stc_mfs47_lin_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_lin_fcr_field_t; - -typedef struct stc_mfs47_lin_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_lin_fcr0_field_t; - -typedef struct stc_mfs47_lin_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_lin_fcr1_field_t; - -typedef struct stc_mfs47_lin_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_lin_fbyte_field_t; - -typedef struct stc_mfs47_lin_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_lin_fbyte1_field_t; - -typedef struct stc_mfs47_lin_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_lin_fbyte2_field_t; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* MFS47_I2C_MODULE register bit fields */ -typedef struct stc_mfs47_i2c_smr_field -{ - __IO uint8_t ITST0 : 1; - __IO uint8_t ITST1 : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_i2c_smr_field_t; - -typedef struct stc_mfs47_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs47_i2c_ibcr_field_t; - -typedef struct stc_mfs47_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs47_i2c_ibsr_field_t; - -typedef struct stc_mfs47_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs47_i2c_ssr_field_t; - -typedef struct stc_mfs47_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs47_i2c_isba_field_t; - -typedef struct stc_mfs47_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs47_i2c_ismk_field_t; - -typedef struct stc_mfs47_i2c_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_i2c_fcr_field_t; - -typedef struct stc_mfs47_i2c_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_i2c_fcr0_field_t; - -typedef struct stc_mfs47_i2c_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_i2c_fcr1_field_t; - -typedef struct stc_mfs47_i2c_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_i2c_fbyte_field_t; - -typedef struct stc_mfs47_i2c_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_i2c_fbyte1_field_t; - -typedef struct stc_mfs47_i2c_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_i2c_fbyte2_field_t; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC_MODULE register bit fields */ -typedef struct stc_crc_crccr_field -{ - __IO uint8_t INIT : 1; - __IO uint8_t CRC32 : 1; - __IO uint8_t LTLEND : 1; - __IO uint8_t LSBFST : 1; - __IO uint8_t CRCLTE : 1; - __IO uint8_t CRCLSF : 1; - __IO uint8_t FXOR : 1; -} stc_crc_crccr_field_t; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* WC_MODULE register bit fields */ -typedef struct stc_wc_wcrd_field -{ - __IO uint8_t CTR0 : 1; - __IO uint8_t CTR1 : 1; - __IO uint8_t CTR2 : 1; - __IO uint8_t CTR3 : 1; - __IO uint8_t CTR4 : 1; - __IO uint8_t CTR5 : 1; -} stc_wc_wcrd_field_t; - -typedef struct stc_wc_wcrl_field -{ - __IO uint8_t RLC0 : 1; - __IO uint8_t RLC1 : 1; - __IO uint8_t RLC2 : 1; - __IO uint8_t RLC3 : 1; - __IO uint8_t RLC4 : 1; - __IO uint8_t RLC5 : 1; -} stc_wc_wcrl_field_t; - -typedef struct stc_wc_wccr_field -{ - __IO uint8_t WCIF : 1; - __IO uint8_t WCIE : 1; - __IO uint8_t CS0 : 1; - __IO uint8_t CS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t WCOP : 1; - __IO uint8_t WCEN : 1; -} stc_wc_wccr_field_t; - -typedef struct stc_wc_clk_sel_field -{ - __IO uint16_t SEL_IN : 1; - uint16_t RESERVED1 : 7; - __IO uint16_t SEL_OUT : 1; -} stc_wc_clk_sel_field_t; - -typedef struct stc_wc_clk_en_field -{ - __IO uint8_t CLK_EN : 1; - __IO uint8_t CLK_EN_R : 1; -} stc_wc_clk_en_field_t; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* EXBUS_MODULE register bit fields */ -typedef struct stc_exbus_mode0_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode0_field_t; - -typedef struct stc_exbus_mode1_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode1_field_t; - -typedef struct stc_exbus_mode2_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode2_field_t; - -typedef struct stc_exbus_mode3_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode3_field_t; - -typedef struct stc_exbus_mode4_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode4_field_t; - -typedef struct stc_exbus_mode5_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode5_field_t; - -typedef struct stc_exbus_mode6_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode6_field_t; - -typedef struct stc_exbus_mode7_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t TEST : 1; -} stc_exbus_mode7_field_t; - -typedef struct stc_exbus_tim0_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim0_field_t; - -typedef struct stc_exbus_tim1_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim1_field_t; - -typedef struct stc_exbus_tim2_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim2_field_t; - -typedef struct stc_exbus_tim3_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim3_field_t; - -typedef struct stc_exbus_tim4_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim4_field_t; - -typedef struct stc_exbus_tim5_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim5_field_t; - -typedef struct stc_exbus_tim6_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim6_field_t; - -typedef struct stc_exbus_tim7_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim7_field_t; - -typedef struct stc_exbus_area0_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area0_field_t; - -typedef struct stc_exbus_area1_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area1_field_t; - -typedef struct stc_exbus_area2_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area2_field_t; - -typedef struct stc_exbus_area3_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area3_field_t; - -typedef struct stc_exbus_area4_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area4_field_t; - -typedef struct stc_exbus_area5_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area5_field_t; - -typedef struct stc_exbus_area6_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area6_field_t; - -typedef struct stc_exbus_area7_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area7_field_t; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB_MODULE register bit fields */ -typedef struct stc_usb_hcnt_field -{ - __IO uint16_t HOST : 1; - __IO uint16_t URST : 1; - __IO uint16_t SOFIRE : 1; - __IO uint16_t DIRE : 1; - __IO uint16_t CNNIRE : 1; - __IO uint16_t CMPIRE : 1; - __IO uint16_t URIRE : 1; - __IO uint16_t RWKIRE : 1; - __IO uint16_t RETRY : 1; - __IO uint16_t CANCEL : 1; - __IO uint16_t SOFSTEP : 1; -} stc_usb_hcnt_field_t; - -typedef struct stc_usb_hcnt0_field -{ - __IO uint8_t HOST : 1; - __IO uint8_t URST : 1; - __IO uint8_t SOFIRE : 1; - __IO uint8_t DIRE : 1; - __IO uint8_t CNNIRE : 1; - __IO uint8_t CMPIRE : 1; - __IO uint8_t URIRE : 1; - __IO uint8_t RWKIRE : 1; -} stc_usb_hcnt0_field_t; - -typedef struct stc_usb_hcnt1_field -{ - __IO uint8_t RETRY : 1; - __IO uint8_t CANCEL : 1; - __IO uint8_t SOFSTEP : 1; -} stc_usb_hcnt1_field_t; - -typedef struct stc_usb_hirq_field -{ - __IO uint8_t SOFIRQ : 1; - __IO uint8_t DIRQ : 1; - __IO uint8_t CNNIRQ : 1; - __IO uint8_t CMPIRQ : 1; - __IO uint8_t URIRQ : 1; - __IO uint8_t RWKIRQ : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TCAN : 1; -} stc_usb_hirq_field_t; - -typedef struct stc_usb_herr_field -{ - __IO uint8_t HS0 : 1; - __IO uint8_t HS1 : 1; - __IO uint8_t STUFF : 1; - __IO uint8_t TGERR : 1; - __IO uint8_t CRC : 1; - __IO uint8_t TOUT : 1; - __IO uint8_t RERR : 1; - __IO uint8_t LSTOF : 1; -} stc_usb_herr_field_t; - -typedef struct stc_usb_hstate_field -{ - __IO uint8_t CSTAT : 1; - __IO uint8_t TMODE : 1; - __IO uint8_t SUSP : 1; - __IO uint8_t SOFBUSY : 1; - __IO uint8_t CLKSEL : 1; - __IO uint8_t ALIVE : 1; -} stc_usb_hstate_field_t; - -typedef struct stc_usb_hfcomp_field -{ - __IO uint8_t FRAMECOMP0 : 1; - __IO uint8_t FRAMECOMP1 : 1; - __IO uint8_t FRAMECOMP2 : 1; - __IO uint8_t FRAMECOMP3 : 1; - __IO uint8_t FRAMECOMP4 : 1; - __IO uint8_t FRAMECOMP5 : 1; - __IO uint8_t FRAMECOMP6 : 1; - __IO uint8_t FRAMECOMP7 : 1; -} stc_usb_hfcomp_field_t; - -typedef struct stc_usb_hrtimer_field -{ - __IO uint16_t RTIMER0 : 1; - __IO uint16_t RTIMER1 : 1; - __IO uint16_t RTIMER2 : 1; - __IO uint16_t RTIMER3 : 1; - __IO uint16_t RTIMER4 : 1; - __IO uint16_t RTIMER5 : 1; - __IO uint16_t RTIMER6 : 1; - __IO uint16_t RTIMER7 : 1; - __IO uint16_t RTIMER8 : 1; - __IO uint16_t RTIMER9 : 1; - __IO uint16_t RTIMER10 : 1; - __IO uint16_t RTIMER11 : 1; - __IO uint16_t RTIMER12 : 1; - __IO uint16_t RTIMER13 : 1; - __IO uint16_t RTIMER14 : 1; - __IO uint16_t RTIMER15 : 1; -} stc_usb_hrtimer_field_t; - -typedef struct stc_usb_hrtimer0_field -{ - __IO uint8_t RTIMER00 : 1; - __IO uint8_t RTIMER01 : 1; - __IO uint8_t RTIMER02 : 1; - __IO uint8_t RTIMER03 : 1; - __IO uint8_t RTIMER04 : 1; - __IO uint8_t RTIMER05 : 1; - __IO uint8_t RTIMER06 : 1; - __IO uint8_t RTIMER07 : 1; -} stc_usb_hrtimer0_field_t; - -typedef struct stc_usb_hrtimer1_field -{ - __IO uint8_t RTIMER10 : 1; - __IO uint8_t RTIMER11 : 1; - __IO uint8_t RTIMER12 : 1; - __IO uint8_t RTIMER13 : 1; - __IO uint8_t RTIMER14 : 1; - __IO uint8_t RTIMER15 : 1; - __IO uint8_t RTIMER16 : 1; - __IO uint8_t RTIMER17 : 1; -} stc_usb_hrtimer1_field_t; - -typedef struct stc_usb_hrtimer2_field -{ - __IO uint8_t RTIMER20 : 1; - __IO uint8_t RTIMER21 : 1; - __IO uint8_t RTIMER22 : 1; -} stc_usb_hrtimer2_field_t; - -typedef struct stc_usb_hadr_field -{ - __IO uint8_t ADDRESS0 : 1; - __IO uint8_t ADDRESS1 : 1; - __IO uint8_t ADDRESS2 : 1; - __IO uint8_t ADDRESS3 : 1; - __IO uint8_t ADDRESS4 : 1; - __IO uint8_t ADDRESS5 : 1; - __IO uint8_t ADDRESS6 : 1; -} stc_usb_hadr_field_t; - -typedef struct stc_usb_heof_field -{ - __IO uint16_t EOF0 : 1; - __IO uint16_t EOF1 : 1; - __IO uint16_t EOF2 : 1; - __IO uint16_t EOF3 : 1; - __IO uint16_t EOF4 : 1; - __IO uint16_t EOF5 : 1; - __IO uint16_t EOF6 : 1; - __IO uint16_t EOF7 : 1; - __IO uint16_t EOF8 : 1; - __IO uint16_t EOF9 : 1; - __IO uint16_t EOF10 : 1; - __IO uint16_t EOF11 : 1; - __IO uint16_t EOF12 : 1; - __IO uint16_t EOF13 : 1; - __IO uint16_t EOF14 : 1; - __IO uint16_t EOF15 : 1; -} stc_usb_heof_field_t; - -typedef struct stc_usb_heof0_field -{ - __IO uint8_t EOF00 : 1; - __IO uint8_t EOF01 : 1; - __IO uint8_t EOF02 : 1; - __IO uint8_t EOF03 : 1; - __IO uint8_t EOF04 : 1; - __IO uint8_t EOF05 : 1; - __IO uint8_t EOF06 : 1; - __IO uint8_t EOF07 : 1; -} stc_usb_heof0_field_t; - -typedef struct stc_usb_heof1_field -{ - __IO uint8_t EOF10 : 1; - __IO uint8_t EOF11 : 1; - __IO uint8_t EOF12 : 1; - __IO uint8_t EOF13 : 1; - __IO uint8_t EOF14 : 1; - __IO uint8_t EOF15 : 1; -} stc_usb_heof1_field_t; - -typedef struct stc_usb_hframe_field -{ - __IO uint16_t FRAME0 : 1; - __IO uint16_t FRAME1 : 1; - __IO uint16_t FRAME2 : 1; - __IO uint16_t FRAME3 : 1; - __IO uint16_t FRAME4 : 1; - __IO uint16_t FRAME5 : 1; - __IO uint16_t FRAME6 : 1; - __IO uint16_t FRAME7 : 1; - __IO uint16_t FRAME8 : 1; - __IO uint16_t FRAME9 : 1; - __IO uint16_t FRAME10 : 1; -} stc_usb_hframe_field_t; - -typedef struct stc_usb_hframe0_field -{ - __IO uint8_t FRAME00 : 1; - __IO uint8_t FRAME01 : 1; - __IO uint8_t FRAME02 : 1; - __IO uint8_t FRAME03 : 1; - __IO uint8_t FRAME04 : 1; - __IO uint8_t FRAME05 : 1; - __IO uint8_t FRAME06 : 1; - __IO uint8_t FRAME07 : 1; -} stc_usb_hframe0_field_t; - -typedef struct stc_usb_hframe1_field -{ - __IO uint8_t FRAME10 : 1; - __IO uint8_t FRAME11 : 1; - __IO uint8_t FRAME12 : 1; - __IO uint8_t FRAME13 : 1; -} stc_usb_hframe1_field_t; - -typedef struct stc_usb_htoken_field -{ - __IO uint8_t ENDPT0 : 1; - __IO uint8_t ENDPT1 : 1; - __IO uint8_t ENDPT2 : 1; - __IO uint8_t ENDPT3 : 1; - __IO uint8_t TKNEN0 : 1; - __IO uint8_t TKNEN1 : 1; - __IO uint8_t TKNEN2 : 1; - __IO uint8_t TGGL : 1; -} stc_usb_htoken_field_t; - -typedef struct stc_usb_udcc_field -{ - __IO uint16_t PWC : 1; - __IO uint16_t RFBK : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t STALCLREN : 1; - __IO uint16_t USTP : 1; - __IO uint16_t HCONX : 1; - __IO uint16_t RESUM : 1; - __IO uint16_t RST : 1; -} stc_usb_udcc_field_t; - -typedef struct stc_usb_ep0c_field -{ - __IO uint16_t PKS00 : 1; - __IO uint16_t PKS01 : 1; - __IO uint16_t PKS02 : 1; - __IO uint16_t PKS03 : 1; - __IO uint16_t PKS04 : 1; - __IO uint16_t PKS05 : 1; - __IO uint16_t PKS06 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; -} stc_usb_ep0c_field_t; - -typedef struct stc_usb_ep1c_field -{ - __IO uint16_t PKS10 : 1; - __IO uint16_t PKS11 : 1; - __IO uint16_t PKS12 : 1; - __IO uint16_t PKS13 : 1; - __IO uint16_t PKS14 : 1; - __IO uint16_t PKS15 : 1; - __IO uint16_t PKS16 : 1; - __IO uint16_t PKS17 : 1; - __IO uint16_t PKS18 : 1; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep1c_field_t; - -typedef struct stc_usb_ep2c_field -{ - __IO uint16_t PKS20 : 1; - __IO uint16_t PKS21 : 1; - __IO uint16_t PKS22 : 1; - __IO uint16_t PKS23 : 1; - __IO uint16_t PKS24 : 1; - __IO uint16_t PKS25 : 1; - __IO uint16_t PKS26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep2c_field_t; - -typedef struct stc_usb_ep3c_field -{ - __IO uint16_t PKS30 : 1; - __IO uint16_t PKS31 : 1; - __IO uint16_t PKS32 : 1; - __IO uint16_t PKS33 : 1; - __IO uint16_t PKS34 : 1; - __IO uint16_t PKS35 : 1; - __IO uint16_t PKS36 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep3c_field_t; - -typedef struct stc_usb_ep4c_field -{ - __IO uint16_t PKS40 : 1; - __IO uint16_t PKS41 : 1; - __IO uint16_t PKS42 : 1; - __IO uint16_t PKS43 : 1; - __IO uint16_t PKS44 : 1; - __IO uint16_t PKS45 : 1; - __IO uint16_t PKS46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep4c_field_t; - -typedef struct stc_usb_ep5c_field -{ - __IO uint16_t PKS50 : 1; - __IO uint16_t PKS51 : 1; - __IO uint16_t PKS52 : 1; - __IO uint16_t PKS53 : 1; - __IO uint16_t PKS54 : 1; - __IO uint16_t PKS55 : 1; - __IO uint16_t PKS56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep5c_field_t; - -typedef struct stc_usb_tmsp_field -{ - __IO uint16_t TMSP0 : 1; - __IO uint16_t TMSP1 : 1; - __IO uint16_t TMSP2 : 1; - __IO uint16_t TMSP3 : 1; - __IO uint16_t TMSP4 : 1; - __IO uint16_t TMSP5 : 1; - __IO uint16_t TMSP6 : 1; - __IO uint16_t TMSP7 : 1; - __IO uint16_t TMSP8 : 1; - __IO uint16_t TMSP9 : 1; - __IO uint16_t TMSP10 : 1; -} stc_usb_tmsp_field_t; - -typedef struct stc_usb_udcs_field -{ - __IO uint8_t CONF : 1; - __IO uint8_t SETP : 1; - __IO uint8_t WKUP : 1; - __IO uint8_t BRST : 1; - __IO uint8_t SOF : 1; - __IO uint8_t SUSP : 1; -} stc_usb_udcs_field_t; - -typedef struct stc_usb_udcie_field -{ - __IO uint8_t CONFIE : 1; - __IO uint8_t CONFN : 1; - __IO uint8_t WKUPIE : 1; - __IO uint8_t BRSTIE : 1; - __IO uint8_t SOFIE : 1; - __IO uint8_t SUSPIE : 1; -} stc_usb_udcie_field_t; - -typedef struct stc_usb_ep0is_field -{ - uint16_t RESERVED1 : 10; - __IO uint16_t DRQI : 1; - uint16_t RESERVED2 : 3; - __IO uint16_t DRQIIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0is_field_t; - -typedef struct stc_usb_ep0os_field -{ - __IO uint16_t SIZE0 : 1; - __IO uint16_t SIZE1 : 1; - __IO uint16_t SIZE2 : 1; - __IO uint16_t SIZE3 : 1; - __IO uint16_t SIZE4 : 1; - __IO uint16_t SIZE5 : 1; - __IO uint16_t SIZE6 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQO : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQOIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0os_field_t; - -typedef struct stc_usb_ep1s_field -{ - __IO uint16_t SIZE10 : 1; - __IO uint16_t SIZE11 : 1; - __IO uint16_t SIZE12 : 1; - __IO uint16_t SIZE13 : 1; - __IO uint16_t SIZE14 : 1; - __IO uint16_t SIZE15 : 1; - __IO uint16_t SIZE16 : 1; - __IO uint16_t SIZE17 : 1; - __IO uint16_t SIZE18 : 1; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep1s_field_t; - -typedef struct stc_usb_ep2s_field -{ - __IO uint16_t SIZE20 : 1; - __IO uint16_t SIZE21 : 1; - __IO uint16_t SIZE22 : 1; - __IO uint16_t SIZE23 : 1; - __IO uint16_t SIZE24 : 1; - __IO uint16_t SIZE25 : 1; - __IO uint16_t SIZE26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep2s_field_t; - -typedef struct stc_usb_ep4s_field -{ - __IO uint16_t SIZE40 : 1; - __IO uint16_t SIZE41 : 1; - __IO uint16_t SIZE42 : 1; - __IO uint16_t SIZE43 : 1; - __IO uint16_t SIZE44 : 1; - __IO uint16_t SIZE45 : 1; - __IO uint16_t SIZE46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep4s_field_t; - -typedef struct stc_usb_ep5s_field -{ - __IO uint16_t SIZE50 : 1; - __IO uint16_t SIZE51 : 1; - __IO uint16_t SIZE52 : 1; - __IO uint16_t SIZE53 : 1; - __IO uint16_t SIZE54 : 1; - __IO uint16_t SIZE55 : 1; - __IO uint16_t SIZE56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep5s_field_t; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMAC_MODULE register bit fields */ -typedef struct stc_dmac_dmacr_field -{ - uint32_t RESERVED1 : 24; - __IO uint32_t DH0 : 1; - __IO uint32_t DH1 : 1; - __IO uint32_t DH2 : 1; - __IO uint32_t DH3 : 1; - __IO uint32_t PR : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t DS : 1; - __IO uint32_t DE : 1; -} stc_dmac_dmacr_field_t; - -typedef struct stc_dmac_dmaca0_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca0_field_t; - -typedef struct stc_dmac_dmacb0_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb0_field_t; - -typedef struct stc_dmac_dmaca1_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca1_field_t; - -typedef struct stc_dmac_dmacb1_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb1_field_t; - -typedef struct stc_dmac_dmaca2_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca2_field_t; - -typedef struct stc_dmac_dmacb2_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb2_field_t; - -typedef struct stc_dmac_dmaca3_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca3_field_t; - -typedef struct stc_dmac_dmacb3_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb3_field_t; - -typedef struct stc_dmac_dmaca4_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca4_field_t; - -typedef struct stc_dmac_dmacb4_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb4_field_t; - -typedef struct stc_dmac_dmaca5_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca5_field_t; - -typedef struct stc_dmac_dmacb5_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb5_field_t; - -typedef struct stc_dmac_dmaca6_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca6_field_t; - -typedef struct stc_dmac_dmacb6_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb6_field_t; - -typedef struct stc_dmac_dmaca7_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca7_field_t; - -typedef struct stc_dmac_dmacb7_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb7_field_t; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN_MODULE register bit fields */ -typedef struct stc_can_ctrlr_field -{ - __IO uint16_t INIT : 1; - __IO uint16_t IE : 1; - __IO uint16_t SIE : 1; - __IO uint16_t EIE : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t DAR : 1; - __IO uint16_t CCE : 1; - __IO uint16_t TEST : 1; -} stc_can_ctrlr_field_t; - -typedef struct stc_can_statr_field -{ - __IO uint16_t LEC0 : 1; - __IO uint16_t LEC1 : 1; - __IO uint16_t LEC2 : 1; - __IO uint16_t TXOK : 1; - __IO uint16_t RXOK : 1; - __IO uint16_t EPASS : 1; - __IO uint16_t EWARM : 1; - __IO uint16_t BOFF : 1; -} stc_can_statr_field_t; - -typedef struct stc_can_errcnt_field -{ - __IO uint16_t TEC0 : 1; - __IO uint16_t TEC1 : 1; - __IO uint16_t TEC2 : 1; - __IO uint16_t TEC3 : 1; - __IO uint16_t TEC4 : 1; - __IO uint16_t TEC5 : 1; - __IO uint16_t TEC6 : 1; - __IO uint16_t TEC7 : 1; - __IO uint16_t REC0 : 1; - __IO uint16_t REC1 : 1; - __IO uint16_t REC2 : 1; - __IO uint16_t REC3 : 1; - __IO uint16_t REC4 : 1; - __IO uint16_t REC5 : 1; - __IO uint16_t REC6 : 1; - __IO uint16_t RP : 1; -} stc_can_errcnt_field_t; - -typedef struct stc_can_btr_field -{ - __IO uint16_t BRP0 : 1; - __IO uint16_t BRP1 : 1; - __IO uint16_t BRP2 : 1; - __IO uint16_t BRP3 : 1; - __IO uint16_t BRP4 : 1; - __IO uint16_t BRP5 : 1; - __IO uint16_t SJW0 : 1; - __IO uint16_t SJW1 : 1; - __IO uint16_t TSEG10 : 1; - __IO uint16_t TSEG11 : 1; - __IO uint16_t TSEG12 : 1; - __IO uint16_t TSEG13 : 1; - __IO uint16_t TSEG20 : 1; - __IO uint16_t TSEG21 : 1; - __IO uint16_t TSEG22 : 1; -} stc_can_btr_field_t; - -typedef struct stc_can_intr_field -{ - __IO uint16_t INTID0 : 1; - __IO uint16_t INTID1 : 1; - __IO uint16_t INTID2 : 1; - __IO uint16_t INTID3 : 1; - __IO uint16_t INTID4 : 1; - __IO uint16_t INTID5 : 1; - __IO uint16_t INTID6 : 1; - __IO uint16_t INTID7 : 1; - __IO uint16_t INTID8 : 1; - __IO uint16_t INTID9 : 1; - __IO uint16_t INTID10 : 1; - __IO uint16_t INTID11 : 1; - __IO uint16_t INTID12 : 1; - __IO uint16_t INTID13 : 1; - __IO uint16_t INTID14 : 1; - __IO uint16_t INTID15 : 1; -} stc_can_intr_field_t; - -typedef struct stc_can_testr_field -{ - uint16_t RESERVED1 : 2; - __IO uint16_t BASIC : 1; - __IO uint16_t SILENT : 1; - __IO uint16_t LBACK : 1; - __IO uint16_t TX0 : 1; - __IO uint16_t TX1 : 1; - __IO uint16_t RX : 1; -} stc_can_testr_field_t; - -typedef struct stc_can_brper_field -{ - __IO uint16_t BRPE0 : 1; - __IO uint16_t BRPE1 : 1; - __IO uint16_t BRPE2 : 1; - __IO uint16_t BRPE3 : 1; -} stc_can_brper_field_t; - -typedef struct stc_can_if1creq_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t BUSY : 1; -} stc_can_if1creq_field_t; - -typedef struct stc_can_if1cmsk_field -{ - __IO uint16_t DATAB : 1; - __IO uint16_t DATAA : 1; - __IO uint16_t NEWDAT : 1; - __IO uint16_t CIP : 1; - __IO uint16_t CONTROL : 1; - __IO uint16_t ARB : 1; - __IO uint16_t MASK : 1; - __IO uint16_t WRRD : 1; -} stc_can_if1cmsk_field_t; - -typedef struct stc_can_if1msk_field -{ - uint32_t RESERVED1 : 30; - __IO uint32_t MDIR : 1; - __IO uint32_t MXTD : 1; -} stc_can_if1msk_field_t; - -typedef struct stc_can_if1msk2_field -{ - uint16_t RESERVED1 : 14; - __IO uint16_t MDIR : 1; - __IO uint16_t MXTD : 1; -} stc_can_if1msk2_field_t; - -typedef struct stc_can_if1arb_field -{ - uint32_t RESERVED1 : 29; - __IO uint32_t DIR : 1; - __IO uint32_t XTD : 1; - __IO uint32_t MSGVAL : 1; -} stc_can_if1arb_field_t; - -typedef struct stc_can_if1arb2_field -{ - uint16_t RESERVED1 : 13; - __IO uint16_t DIR : 1; - __IO uint16_t XTD : 1; - __IO uint16_t MSGVAL : 1; -} stc_can_if1arb2_field_t; - -typedef struct stc_can_if1mctr_field -{ - __IO uint16_t DLC0 : 1; - __IO uint16_t DLC1 : 1; - __IO uint16_t DLC2 : 1; - __IO uint16_t DLC3 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t EOB : 1; - __IO uint16_t TXRQST : 1; - __IO uint16_t RMTEN : 1; - __IO uint16_t RXIE : 1; - __IO uint16_t TXIE : 1; - __IO uint16_t UMASK : 1; - __IO uint16_t INTPND : 1; - __IO uint16_t MSGLST : 1; - __IO uint16_t NEWDAT : 1; -} stc_can_if1mctr_field_t; - -typedef struct stc_can_if2creq_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t BUSY : 1; -} stc_can_if2creq_field_t; - -typedef struct stc_can_if2cmsk_field -{ - __IO uint16_t DATAB : 1; - __IO uint16_t DATAA : 1; - __IO uint16_t NEWDAT : 1; - __IO uint16_t CIP : 1; - __IO uint16_t CONTROL : 1; - __IO uint16_t ARB : 1; - __IO uint16_t MASK : 1; - __IO uint16_t WRRD : 1; -} stc_can_if2cmsk_field_t; - -typedef struct stc_can_if2msk_field -{ - uint32_t RESERVED1 : 30; - __IO uint32_t MDIR : 1; - __IO uint32_t MXTD : 1; -} stc_can_if2msk_field_t; - -typedef struct stc_can_if2msk2_field -{ - uint16_t RESERVED1 : 14; - __IO uint16_t MDIR : 1; - __IO uint16_t MXTD : 1; -} stc_can_if2msk2_field_t; - -typedef struct stc_can_if2arb2_field -{ - uint16_t RESERVED1 : 13; - __IO uint16_t DIR : 1; - __IO uint16_t XTD : 1; - __IO uint16_t MSGVAL : 1; -} stc_can_if2arb2_field_t; - -typedef struct stc_can_if2mctr_field -{ - __IO uint16_t DLC0 : 1; - __IO uint16_t DLC1 : 1; - __IO uint16_t DLC2 : 1; - __IO uint16_t DLC3 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t EOB : 1; - __IO uint16_t TXRQST : 1; - __IO uint16_t RMTEN : 1; - __IO uint16_t RXIE : 1; - __IO uint16_t TXIE : 1; - __IO uint16_t UMASK : 1; - __IO uint16_t INTPND : 1; - __IO uint16_t MSGLST : 1; - __IO uint16_t NEWDAT : 1; -} stc_can_if2mctr_field_t; - -typedef struct stc_can_treqr_field -{ - __IO uint32_t TXRQST1 : 1; - __IO uint32_t TXRQST2 : 1; - __IO uint32_t TXRQST3 : 1; - __IO uint32_t TXRQST4 : 1; - __IO uint32_t TXRQST5 : 1; - __IO uint32_t TXRQST6 : 1; - __IO uint32_t TXRQST7 : 1; - __IO uint32_t TXRQST8 : 1; - __IO uint32_t TXRQST9 : 1; - __IO uint32_t TXRQST10 : 1; - __IO uint32_t TXRQST11 : 1; - __IO uint32_t TXRQST12 : 1; - __IO uint32_t TXRQST13 : 1; - __IO uint32_t TXRQST14 : 1; - __IO uint32_t TXRQST15 : 1; - __IO uint32_t TXRQST16 : 1; - __IO uint32_t TXRQST17 : 1; - __IO uint32_t TXRQST18 : 1; - __IO uint32_t TXRQST19 : 1; - __IO uint32_t TXRQST20 : 1; - __IO uint32_t TXRQST21 : 1; - __IO uint32_t TXRQST22 : 1; - __IO uint32_t TXRQST23 : 1; - __IO uint32_t TXRQST24 : 1; - __IO uint32_t TXRQST25 : 1; - __IO uint32_t TXRQST26 : 1; - __IO uint32_t TXRQST27 : 1; - __IO uint32_t TXRQST28 : 1; - __IO uint32_t TXRQST29 : 1; - __IO uint32_t TXRQST30 : 1; - __IO uint32_t TXRQST31 : 1; - __IO uint32_t TXRQST32 : 1; -} stc_can_treqr_field_t; - -typedef struct stc_can_treqr1_field -{ - __IO uint16_t TXRQST1 : 1; - __IO uint16_t TXRQST2 : 1; - __IO uint16_t TXRQST3 : 1; - __IO uint16_t TXRQST4 : 1; - __IO uint16_t TXRQST5 : 1; - __IO uint16_t TXRQST6 : 1; - __IO uint16_t TXRQST7 : 1; - __IO uint16_t TXRQST8 : 1; - __IO uint16_t TXRQST9 : 1; - __IO uint16_t TXRQST10 : 1; - __IO uint16_t TXRQST11 : 1; - __IO uint16_t TXRQST12 : 1; - __IO uint16_t TXRQST13 : 1; - __IO uint16_t TXRQST14 : 1; - __IO uint16_t TXRQST15 : 1; - __IO uint16_t TXRQST16 : 1; -} stc_can_treqr1_field_t; - -typedef struct stc_can_treqr2_field -{ - __IO uint16_t TXRQST17 : 1; - __IO uint16_t TXRQST18 : 1; - __IO uint16_t TXRQST19 : 1; - __IO uint16_t TXRQST20 : 1; - __IO uint16_t TXRQST21 : 1; - __IO uint16_t TXRQST22 : 1; - __IO uint16_t TXRQST23 : 1; - __IO uint16_t TXRQST24 : 1; - __IO uint16_t TXRQST25 : 1; - __IO uint16_t TXRQST26 : 1; - __IO uint16_t TXRQST27 : 1; - __IO uint16_t TXRQST28 : 1; - __IO uint16_t TXRQST29 : 1; - __IO uint16_t TXRQST30 : 1; - __IO uint16_t TXRQST31 : 1; - __IO uint16_t TXRQST32 : 1; -} stc_can_treqr2_field_t; - -typedef struct stc_can_newdt_field -{ - __IO uint32_t NEWDAT1 : 1; - __IO uint32_t NEWDAT2 : 1; - __IO uint32_t NEWDAT3 : 1; - __IO uint32_t NEWDAT4 : 1; - __IO uint32_t NEWDAT5 : 1; - __IO uint32_t NEWDAT6 : 1; - __IO uint32_t NEWDAT7 : 1; - __IO uint32_t NEWDAT8 : 1; - __IO uint32_t NEWDAT9 : 1; - __IO uint32_t NEWDAT10 : 1; - __IO uint32_t NEWDAT11 : 1; - __IO uint32_t NEWDAT12 : 1; - __IO uint32_t NEWDAT13 : 1; - __IO uint32_t NEWDAT14 : 1; - __IO uint32_t NEWDAT15 : 1; - __IO uint32_t NEWDAT16 : 1; - __IO uint32_t NEWDAT17 : 1; - __IO uint32_t NEWDAT18 : 1; - __IO uint32_t NEWDAT19 : 1; - __IO uint32_t NEWDAT20 : 1; - __IO uint32_t NEWDAT21 : 1; - __IO uint32_t NEWDAT22 : 1; - __IO uint32_t NEWDAT23 : 1; - __IO uint32_t NEWDAT24 : 1; - __IO uint32_t NEWDAT25 : 1; - __IO uint32_t NEWDAT26 : 1; - __IO uint32_t NEWDAT27 : 1; - __IO uint32_t NEWDAT28 : 1; - __IO uint32_t NEWDAT29 : 1; - __IO uint32_t NEWDAT30 : 1; - __IO uint32_t NEWDAT31 : 1; - __IO uint32_t NEWDAT32 : 1; -} stc_can_newdt_field_t; - -typedef struct stc_can_newdt1_field -{ - __IO uint16_t NEWDAT1 : 1; - __IO uint16_t NEWDAT2 : 1; - __IO uint16_t NEWDAT3 : 1; - __IO uint16_t NEWDAT4 : 1; - __IO uint16_t NEWDAT5 : 1; - __IO uint16_t NEWDAT6 : 1; - __IO uint16_t NEWDAT7 : 1; - __IO uint16_t NEWDAT8 : 1; - __IO uint16_t NEWDAT9 : 1; - __IO uint16_t NEWDAT10 : 1; - __IO uint16_t NEWDAT11 : 1; - __IO uint16_t NEWDAT12 : 1; - __IO uint16_t NEWDAT13 : 1; - __IO uint16_t NEWDAT14 : 1; - __IO uint16_t NEWDAT15 : 1; - __IO uint16_t NEWDAT16 : 1; -} stc_can_newdt1_field_t; - -typedef struct stc_can_intpnd_field -{ - __IO uint32_t INTPND1 : 1; - __IO uint32_t INTPND2 : 1; - __IO uint32_t INTPND3 : 1; - __IO uint32_t INTPND4 : 1; - __IO uint32_t INTPND5 : 1; - __IO uint32_t INTPND6 : 1; - __IO uint32_t INTPND7 : 1; - __IO uint32_t INTPND8 : 1; - __IO uint32_t INTPND9 : 1; - __IO uint32_t INTPND10 : 1; - __IO uint32_t INTPND11 : 1; - __IO uint32_t INTPND12 : 1; - __IO uint32_t INTPND13 : 1; - __IO uint32_t INTPND14 : 1; - __IO uint32_t INTPND15 : 1; - __IO uint32_t INTPND16 : 1; - __IO uint32_t INTPND17 : 1; - __IO uint32_t INTPND18 : 1; - __IO uint32_t INTPND19 : 1; - __IO uint32_t INTPND20 : 1; - __IO uint32_t INTPND21 : 1; - __IO uint32_t INTPND22 : 1; - __IO uint32_t INTPND23 : 1; - __IO uint32_t INTPND24 : 1; - __IO uint32_t INTPND25 : 1; - __IO uint32_t INTPND26 : 1; - __IO uint32_t INTPND27 : 1; - __IO uint32_t INTPND28 : 1; - __IO uint32_t INTPND29 : 1; - __IO uint32_t INTPND30 : 1; - __IO uint32_t INTPND31 : 1; - __IO uint32_t INTPND32 : 1; -} stc_can_intpnd_field_t; - -typedef struct stc_can_intpnd1_field -{ - __IO uint16_t INTPND1 : 1; - __IO uint16_t INTPND2 : 1; - __IO uint16_t INTPND3 : 1; - __IO uint16_t INTPND4 : 1; - __IO uint16_t INTPND5 : 1; - __IO uint16_t INTPND6 : 1; - __IO uint16_t INTPND7 : 1; - __IO uint16_t INTPND8 : 1; - __IO uint16_t INTPND9 : 1; - __IO uint16_t INTPND10 : 1; - __IO uint16_t INTPND11 : 1; - __IO uint16_t INTPND12 : 1; - __IO uint16_t INTPND13 : 1; - __IO uint16_t INTPND14 : 1; - __IO uint16_t INTPND15 : 1; - __IO uint16_t INTPND16 : 1; -} stc_can_intpnd1_field_t; - -typedef struct stc_can_intpnd2_field -{ - __IO uint16_t INTPND17 : 1; - __IO uint16_t INTPND18 : 1; - __IO uint16_t INTPND19 : 1; - __IO uint16_t INTPND20 : 1; - __IO uint16_t INTPND21 : 1; - __IO uint16_t INTPND22 : 1; - __IO uint16_t INTPND23 : 1; - __IO uint16_t INTPND24 : 1; - __IO uint16_t INTPND25 : 1; - __IO uint16_t INTPND26 : 1; - __IO uint16_t INTPND27 : 1; - __IO uint16_t INTPND28 : 1; - __IO uint16_t INTPND29 : 1; - __IO uint16_t INTPND30 : 1; - __IO uint16_t INTPND31 : 1; - __IO uint16_t INTPND32 : 1; -} stc_can_intpnd2_field_t; - -typedef struct stc_can_msgval_field -{ - __IO uint32_t MSGVAL1 : 1; - __IO uint32_t MSGVAL2 : 1; - __IO uint32_t MSGVAL3 : 1; - __IO uint32_t MSGVAL4 : 1; - __IO uint32_t MSGVAL5 : 1; - __IO uint32_t MSGVAL6 : 1; - __IO uint32_t MSGVAL7 : 1; - __IO uint32_t MSGVAL8 : 1; - __IO uint32_t MSGVAL9 : 1; - __IO uint32_t MSGVAL10 : 1; - __IO uint32_t MSGVAL11 : 1; - __IO uint32_t MSGVAL12 : 1; - __IO uint32_t MSGVAL13 : 1; - __IO uint32_t MSGVAL14 : 1; - __IO uint32_t MSGVAL15 : 1; - __IO uint32_t MSGVAL16 : 1; - __IO uint32_t MSGVAL17 : 1; - __IO uint32_t MSGVAL18 : 1; - __IO uint32_t MSGVAL19 : 1; - __IO uint32_t MSGVAL20 : 1; - __IO uint32_t MSGVAL21 : 1; - __IO uint32_t MSGVAL22 : 1; - __IO uint32_t MSGVAL23 : 1; - __IO uint32_t MSGVAL24 : 1; - __IO uint32_t MSGVAL25 : 1; - __IO uint32_t MSGVAL26 : 1; - __IO uint32_t MSGVAL27 : 1; - __IO uint32_t MSGVAL28 : 1; - __IO uint32_t MSGVAL29 : 1; - __IO uint32_t MSGVAL30 : 1; - __IO uint32_t MSGVAL31 : 1; - __IO uint32_t MSGVAL32 : 1; -} stc_can_msgval_field_t; - -typedef struct stc_can_msgval1_field -{ - __IO uint16_t MSGVAL1 : 1; - __IO uint16_t MSGVAL2 : 1; - __IO uint16_t MSGVAL3 : 1; - __IO uint16_t MSGVAL4 : 1; - __IO uint16_t MSGVAL5 : 1; - __IO uint16_t MSGVAL6 : 1; - __IO uint16_t MSGVAL7 : 1; - __IO uint16_t MSGVAL8 : 1; - __IO uint16_t MSGVAL9 : 1; - __IO uint16_t MSGVAL10 : 1; - __IO uint16_t MSGVAL11 : 1; - __IO uint16_t MSGVAL12 : 1; - __IO uint16_t MSGVAL13 : 1; - __IO uint16_t MSGVAL14 : 1; - __IO uint16_t MSGVAL15 : 1; - __IO uint16_t MSGVAL16 : 1; -} stc_can_msgval1_field_t; - -typedef struct stc_can_msgval2_field -{ - __IO uint16_t MSGVAL17 : 1; - __IO uint16_t MSGVAL18 : 1; - __IO uint16_t MSGVAL19 : 1; - __IO uint16_t MSGVAL20 : 1; - __IO uint16_t MSGVAL21 : 1; - __IO uint16_t MSGVAL22 : 1; - __IO uint16_t MSGVAL23 : 1; - __IO uint16_t MSGVAL24 : 1; - __IO uint16_t MSGVAL25 : 1; - __IO uint16_t MSGVAL26 : 1; - __IO uint16_t MSGVAL27 : 1; - __IO uint16_t MSGVAL28 : 1; - __IO uint16_t MSGVAL29 : 1; - __IO uint16_t MSGVAL30 : 1; - __IO uint16_t MSGVAL31 : 1; - __IO uint16_t MSGVAL32 : 1; -} stc_can_msgval2_field_t; - - -/****************************************************************************** - * Peripheral register structures - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - union { - __IO uint32_t FASZR; - stc_flash_if_faszr_field_t FASZR_f; - }; - union { - __IO uint32_t FRWTR; - stc_flash_if_frwtr_field_t FRWTR_f; - }; - union { - __IO uint32_t FSTR; - stc_flash_if_fstr_field_t FSTR_f; - }; - uint8_t RESERVED0[4]; - union { - __IO uint32_t FSYNDN; - stc_flash_if_fsyndn_field_t FSYNDN_f; - }; - uint8_t RESERVED1[236]; - union { - __IO uint32_t CRTRMM; - stc_flash_if_crtrmm_field_t CRTRMM_f; - }; -}FM3_FLASH_IF_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - union { - __IO uint8_t SCM_CTL; - stc_crg_scm_ctl_field_t SCM_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t SCM_STR; - stc_crg_scm_str_field_t SCM_STR_f; - }; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - union { - __IO uint16_t RST_STR; - stc_crg_rst_str_field_t RST_STR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t BSC_PSR; - stc_crg_bsc_psr_field_t BSC_PSR_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t APBC0_PSR; - stc_crg_apbc0_psr_field_t APBC0_PSR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t APBC1_PSR; - stc_crg_apbc1_psr_field_t APBC1_PSR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t APBC2_PSR; - stc_crg_apbc2_psr_field_t APBC2_PSR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t SWC_PSR; - stc_crg_swc_psr_field_t SWC_PSR_f; - }; - uint8_t RESERVED7[7]; - union { - __IO uint8_t TTC_PSR; - stc_crg_ttc_psr_field_t TTC_PSR_f; - }; - uint8_t RESERVED8[7]; - union { - __IO uint8_t CSW_TMR; - stc_crg_csw_tmr_field_t CSW_TMR_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t PSW_TMR; - stc_crg_psw_tmr_field_t PSW_TMR_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PLL_CTL1; - stc_crg_pll_ctl1_field_t PLL_CTL1_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t PLL_CTL2; - stc_crg_pll_ctl2_field_t PLL_CTL2_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint16_t CSV_CTL; - stc_crg_csv_ctl_field_t CSV_CTL_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint8_t CSV_STR; - stc_crg_csv_str_field_t CSV_STR_f; - }; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - union { - __IO uint8_t DBWDT_CTL; - stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; - }; - uint8_t RESERVED18[11]; - union { - __IO uint8_t INT_ENR; - stc_crg_int_enr_field_t INT_ENR_f; - }; - uint8_t RESERVED19[3]; - union { - __IO uint8_t INT_STR; - stc_crg_int_str_field_t INT_STR_f; - }; - uint8_t RESERVED20[3]; - union { - __IO uint8_t INT_CLR; - stc_crg_int_clr_field_t INT_CLR_f; - }; -}FM3_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - union { - __IO uint8_t WDG_CTL; - stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; - }; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WDG_RIS; - stc_hwwdt_wdg_ris_field_t WDG_RIS_f; - }; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM3_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - union { - __IO uint8_t WDOGCONTROL; - stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - union { - __IO uint8_t WDOGRIS; - stc_swwdt_wdogris_field_t WDOGRIS_f; - }; - uint8_t RESERVED1[3055]; - __IO uint32_t WDOGLOCK; -}FM3_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMER1LOAD; - __IO uint32_t TIMER1VALUE; - union { - __IO uint32_t TIMER1CONTROL; - stc_dtim_timer1control_field_t TIMER1CONTROL_f; - }; - __IO uint32_t TIMER1INTCLR; - union { - __IO uint32_t TIMER1RIS; - stc_dtim_timer1ris_field_t TIMER1RIS_f; - }; - union { - __IO uint32_t TIMER1MIS; - stc_dtim_timer1mis_field_t TIMER1MIS_f; - }; - __IO uint32_t TIMER1BGLOAD; - uint8_t RESERVED0[4]; - __IO uint32_t TIMER2LOAD; - __IO uint32_t TIMER2VALUE; - union { - __IO uint32_t TIMER2CONTROL; - stc_dtim_timer2control_field_t TIMER2CONTROL_f; - }; - __IO uint32_t TIMER2INTCLR; - union { - __IO uint32_t TIMER2RIS; - stc_dtim_timer2ris_field_t TIMER2RIS_f; - }; - union { - __IO uint32_t TIMER2MIS; - stc_dtim_timer2mis_field_t TIMER2MIS_f; - }; - __IO uint32_t TIMER2BGLOAD; -}FM3_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[40]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TCSA0; - stc_mft_frt_tcsa0_field_t TCSA0_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t TCSB0; - stc_mft_frt_tcsb0_field_t TCSB0_f; - }; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT1; - uint8_t RESERVED6[2]; - union { - __IO uint16_t TCSA1; - stc_mft_frt_tcsa1_field_t TCSA1_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t TCSB1; - stc_mft_frt_tcsb1_field_t TCSB1_f; - }; - uint8_t RESERVED8[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED9[2]; - __IO uint16_t TCDT2; - uint8_t RESERVED10[2]; - union { - __IO uint16_t TCSA2; - stc_mft_frt_tcsa2_field_t TCSA2_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t TCSB2; - stc_mft_frt_tcsb2_field_t TCSB2_f; - }; -}FM3_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - __IO uint16_t OCCP0; - uint8_t RESERVED0[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP5; - uint8_t RESERVED5[2]; - union { - __IO uint8_t OCSA10; - stc_mft_ocu_ocsa10_field_t OCSA10_f; - }; - union { - __IO uint8_t OCSB10; - stc_mft_ocu_ocsb10_field_t OCSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t OCSA32; - stc_mft_ocu_ocsa32_field_t OCSA32_f; - }; - union { - __IO uint8_t OCSB32; - stc_mft_ocu_ocsb32_field_t OCSB32_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint8_t OCSA54; - stc_mft_ocu_ocsa54_field_t OCSA54_f; - }; - union { - __IO uint8_t OCSB54; - stc_mft_ocu_ocsb54_field_t OCSB54_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t OCSC; - stc_mft_ocu_ocsc_field_t OCSC_f; - }; - uint8_t RESERVED9[50]; - union { - __IO uint8_t OCFS10; - stc_mft_ocu_ocfs10_field_t OCFS10_f; - }; - union { - __IO uint8_t OCFS32; - stc_mft_ocu_ocfs32_field_t OCFS32_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint8_t OCFS54; - stc_mft_ocu_ocfs54_field_t OCFS54_f; - }; -}FM3_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[128]; - __IO uint16_t WFTM10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTM32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTM54; - uint8_t RESERVED3[2]; - union { - __IO uint16_t WFSA10; - stc_mft_wfg_wfsa10_field_t WFSA10_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t WFSA32; - stc_mft_wfg_wfsa32_field_t WFSA32_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t WFSA54; - stc_mft_wfg_wfsa54_field_t WFSA54_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t WFIR; - stc_mft_wfg_wfir_field_t WFIR_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t NZCL; - stc_mft_wfg_nzcl_field_t NZCL_f; - }; -}FM3_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[96]; - union { - __IO uint8_t ICFS10; - stc_mft_icu_icfs10_field_t ICFS10_f; - }; - union { - __IO uint8_t ICFS32; - stc_mft_icu_icfs32_field_t ICFS32_f; - }; - uint8_t RESERVED1[6]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - uint8_t RESERVED5[2]; - union { - __IO uint8_t ICSA10; - stc_mft_icu_icsa10_field_t ICSA10_f; - }; - union { - __IO uint8_t ICSB10; - stc_mft_icu_icsb10_field_t ICSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ICSA32; - stc_mft_icu_icsa32_field_t ICSA32_f; - }; - union { - __IO uint8_t ICSB32; - stc_mft_icu_icsb32_field_t ICSB32_f; - }; -}FM3_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[160]; - __IO uint16_t ACCP0; - uint8_t RESERVED1[2]; - __IO uint16_t ACCPDN0; - uint8_t RESERVED2[2]; - __IO uint16_t ACCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACCPDN1; - uint8_t RESERVED4[2]; - __IO uint16_t ACCP2; - uint8_t RESERVED5[2]; - __IO uint16_t ACCPDN2; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ACSB; - stc_mft_adcmp_acsb_field_t ACSB_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t ACSA; - stc_mft_adcmp_acsa_field_t ACSA_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t ATSA; - stc_mft_adcmp_atsa_field_t ATSA_f; - }; -}FM3_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t TTCR0; - stc_mft_ppg_ttcr0_field_t TTCR0_f; - }; - uint8_t RESERVED1[7]; - __IO uint8_t COMP0; - uint8_t RESERVED2[2]; - __IO uint8_t COMP2; - uint8_t RESERVED3[4]; - __IO uint8_t COMP4; - uint8_t RESERVED4[2]; - __IO uint8_t COMP6; - uint8_t RESERVED5[12]; - union { - __IO uint8_t TTCR1; - stc_mft_ppg_ttcr1_field_t TTCR1_f; - }; - uint8_t RESERVED6[7]; - __IO uint8_t COMP1; - uint8_t RESERVED7[2]; - __IO uint8_t COMP3; - uint8_t RESERVED8[4]; - __IO uint8_t COMP5; - uint8_t RESERVED9[2]; - __IO uint8_t COMP7; - uint8_t RESERVED10[203]; - union { - __IO uint16_t TRG; - stc_mft_ppg_trg_field_t TRG_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t REVC; - stc_mft_ppg_revc_field_t REVC_f; - }; - uint8_t RESERVED12[250]; - union { - __IO uint8_t PPGC1; - stc_mft_ppg_ppgc1_field_t PPGC1_f; - }; - union { - __IO uint8_t PPGC0; - stc_mft_ppg_ppgc0_field_t PPGC0_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint8_t PPGC3; - stc_mft_ppg_ppgc3_field_t PPGC3_f; - }; - union { - __IO uint8_t PPGC2; - stc_mft_ppg_ppgc2_field_t PPGC2_f; - }; - uint8_t RESERVED14[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED15[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED18[2]; - union { - __IO uint8_t GATEC0; - stc_mft_ppg_gatec0_field_t GATEC0_f; - }; - uint8_t RESERVED19[39]; - union { - __IO uint8_t PPGC5; - stc_mft_ppg_ppgc5_field_t PPGC5_f; - }; - union { - __IO uint8_t PPGC4; - stc_mft_ppg_ppgc4_field_t PPGC4_f; - }; - uint8_t RESERVED20[2]; - union { - __IO uint8_t PPGC7; - stc_mft_ppg_ppgc7_field_t PPGC7_f; - }; - union { - __IO uint8_t PPGC6; - stc_mft_ppg_ppgc6_field_t PPGC6_f; - }; - uint8_t RESERVED21[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint8_t GATEC4; - stc_mft_ppg_gatec4_field_t GATEC4_f; - }; - uint8_t RESERVED26[39]; - union { - __IO uint8_t PPGC9; - stc_mft_ppg_ppgc9_field_t PPGC9_f; - }; - union { - __IO uint8_t PPGC8; - stc_mft_ppg_ppgc8_field_t PPGC8_f; - }; - uint8_t RESERVED27[2]; - union { - __IO uint8_t PPGC11; - stc_mft_ppg_ppgc11_field_t PPGC11_f; - }; - union { - __IO uint8_t PPGC10; - stc_mft_ppg_ppgc10_field_t PPGC10_f; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED30[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED31[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED32[2]; - union { - __IO uint8_t GATEC8; - stc_mft_ppg_gatec8_field_t GATEC8_f; - }; - uint8_t RESERVED33[39]; - union { - __IO uint8_t PPGC13; - stc_mft_ppg_ppgc13_field_t PPGC13_f; - }; - union { - __IO uint8_t PPGC12; - stc_mft_ppg_ppgc12_field_t PPGC12_f; - }; - uint8_t RESERVED34[2]; - union { - __IO uint8_t PPGC15; - stc_mft_ppg_ppgc15_field_t PPGC15_f; - }; - union { - __IO uint8_t PPGC14; - stc_mft_ppg_ppgc14_field_t PPGC14_f; - }; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED37[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED38[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED39[2]; - union { - __IO uint8_t GATEC12; - stc_mft_ppg_gatec12_field_t GATEC12_f; - }; -}FM3_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_ppg_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_ppg_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_ppg_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_pwm_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_pwm_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwm_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t TMCR; - stc_bt_rt_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_rt_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_rt_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - union { - __IO uint16_t TMCR; - stc_bt_pwc_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_pwc_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwc_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL0123; - stc_btiosel03_btsel0123_field_t BTSEL0123_f; - }; -}FM3_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL4567; - stc_btiosel47_btsel4567_field_t BTSEL4567_f; - }; -}FM3_BTIOSEL47_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - union { - __IO uint16_t BTSSSR; - stc_sbssr_btsssr_field_t BTSSSR_f; - }; -}FM3_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t QICR; - stc_qprc_qicr_field_t QICR_f; - }; - struct { - union { - __IO uint8_t QICRL; - stc_qprc_qicrl_field_t QICRL_f; - }; - union { - __IO uint8_t QICRH; - stc_qprc_qicrh_field_t QICRH_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t QCR; - stc_qprc_qcr_field_t QCR_f; - }; - struct { - union { - __IO uint8_t QCRL; - stc_qprc_qcrl_field_t QCRL_f; - }; - union { - __IO uint8_t QCRH; - stc_qprc_qcrh_field_t QCRH_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t QECR; - stc_qprc_qecr_field_t QECR_f; - }; -}FM3_QPRC_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - union { - __IO uint8_t ADSR; - stc_adc_adsr_field_t ADSR_f; - }; - union { - __IO uint8_t ADCR; - stc_adc_adcr_field_t ADCR_f; - }; - uint8_t RESERVED0[6]; - union { - __IO uint8_t SFNS; - stc_adc_sfns_field_t SFNS_f; - }; - union { - __IO uint8_t SCCR; - stc_adc_sccr_field_t SCCR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint32_t SCFD; - stc_adc_scfd_field_t SCFD_f; - }; - struct { - union { - __IO uint16_t SCFDL; - stc_adc_scfdl_field_t SCFDL_f; - }; - union { - __IO uint16_t SCFDH; - stc_adc_scfdh_field_t SCFDH_f; - }; - }; - }; - union { - union { - __IO uint16_t SCIS23; - stc_adc_scis23_field_t SCIS23_f; - }; - struct { - union { - __IO uint8_t SCIS2; - stc_adc_scis2_field_t SCIS2_f; - }; - union { - __IO uint8_t SCIS3; - stc_adc_scis3_field_t SCIS3_f; - }; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t SCIS01; - stc_adc_scis01_field_t SCIS01_f; - }; - struct { - union { - __IO uint8_t SCIS0; - stc_adc_scis0_field_t SCIS0_f; - }; - union { - __IO uint8_t SCIS1; - stc_adc_scis1_field_t SCIS1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t PFNS; - stc_adc_pfns_field_t PFNS_f; - }; - union { - __IO uint8_t PCCR; - stc_adc_pccr_field_t PCCR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint32_t PCFD; - stc_adc_pcfd_field_t PCFD_f; - }; - struct { - union { - __IO uint16_t PCFDL; - stc_adc_pcfdl_field_t PCFDL_f; - }; - union { - __IO uint16_t PCFDH; - stc_adc_pcfdh_field_t PCFDH_f; - }; - }; - }; - union { - __IO uint8_t PCIS; - stc_adc_pcis_field_t PCIS_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t CMPCR; - stc_adc_cmpcr_field_t CMPCR_f; - }; - uint8_t RESERVED6; - union { - __IO uint16_t CMPD; - stc_adc_cmpd_field_t CMPD_f; - }; - union { - union { - __IO uint16_t ADSS23; - stc_adc_adss23_field_t ADSS23_f; - }; - struct { - union { - __IO uint8_t ADSS2; - stc_adc_adss2_field_t ADSS2_f; - }; - union { - __IO uint8_t ADSS3; - stc_adc_adss3_field_t ADSS3_f; - }; - }; - }; - uint8_t RESERVED7[2]; - union { - union { - __IO uint16_t ADSS01; - stc_adc_adss01_field_t ADSS01_f; - }; - struct { - union { - __IO uint8_t ADSS0; - stc_adc_adss0_field_t ADSS0_f; - }; - union { - __IO uint8_t ADSS1; - stc_adc_adss1_field_t ADSS1_f; - }; - }; - }; - uint8_t RESERVED8[2]; - union { - union { - __IO uint16_t ADST01; - stc_adc_adst01_field_t ADST01_f; - }; - struct { - union { - __IO uint8_t ADST1; - stc_adc_adst1_field_t ADST1_f; - }; - union { - __IO uint8_t ADST0; - stc_adc_adst0_field_t ADST0_f; - }; - }; - }; - uint8_t RESERVED9[2]; - union { - __IO uint8_t ADCT; - stc_adc_adct_field_t ADCT_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PRTSL; - stc_adc_prtsl_field_t PRTSL_f; - }; - union { - __IO uint8_t SCTSL; - stc_adc_sctsl_field_t SCTSL_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint8_t ADCEN; - stc_adc_adcen_field_t ADCEN_f; - }; -}FM3_ADC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - union { - __IO uint8_t MCR_PSR; - stc_crtrim_mcr_psr_field_t MCR_PSR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint16_t MCR_FTRM; - stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; - }; - uint8_t RESERVED1[6]; - __IO uint32_t MCR_RLR; -}FM3_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - union { - __IO uint16_t ENIR; - stc_exti_enir_field_t ENIR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint16_t EIRR; - stc_exti_eirr_field_t EIRR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t EICL; - stc_exti_eicl_field_t EICL_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint32_t ELVR; - stc_exti_elvr_field_t ELVR_f; - }; - uint8_t RESERVED3[4]; - union { - __IO uint8_t NMIRR; - stc_exti_nmirr_field_t NMIRR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t NMICL; - stc_exti_nmicl_field_t NMICL_f; - }; -}FM3_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - union { - __IO uint32_t DRQSEL; - stc_intreq_drqsel_field_t DRQSEL_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint32_t EXC02MON; - stc_intreq_exc02mon_field_t EXC02MON_f; - }; - union { - __IO uint32_t IRQ00MON; - stc_intreq_irq00mon_field_t IRQ00MON_f; - }; - union { - __IO uint32_t IRQ01MON; - stc_intreq_irq01mon_field_t IRQ01MON_f; - }; - union { - __IO uint32_t IRQ02MON; - stc_intreq_irq02mon_field_t IRQ02MON_f; - }; - union { - __IO uint32_t IRQ03MON; - stc_intreq_irq03mon_field_t IRQ03MON_f; - }; - union { - __IO uint32_t IRQ04MON; - stc_intreq_irq04mon_field_t IRQ04MON_f; - }; - union { - __IO uint32_t IRQ05MON; - stc_intreq_irq05mon_field_t IRQ05MON_f; - }; - union { - __IO uint32_t IRQ06MON; - stc_intreq_irq06mon_field_t IRQ06MON_f; - }; - union { - __IO uint32_t IRQ07MON; - stc_intreq_irq07mon_field_t IRQ07MON_f; - }; - union { - __IO uint32_t IRQ08MON; - stc_intreq_irq08mon_field_t IRQ08MON_f; - }; - union { - __IO uint32_t IRQ09MON; - stc_intreq_irq09mon_field_t IRQ09MON_f; - }; - union { - __IO uint32_t IRQ10MON; - stc_intreq_irq10mon_field_t IRQ10MON_f; - }; - union { - __IO uint32_t IRQ11MON; - stc_intreq_irq11mon_field_t IRQ11MON_f; - }; - union { - __IO uint32_t IRQ12MON; - stc_intreq_irq12mon_field_t IRQ12MON_f; - }; - union { - __IO uint32_t IRQ13MON; - stc_intreq_irq13mon_field_t IRQ13MON_f; - }; - union { - __IO uint32_t IRQ14MON; - stc_intreq_irq14mon_field_t IRQ14MON_f; - }; - union { - __IO uint32_t IRQ15MON; - stc_intreq_irq15mon_field_t IRQ15MON_f; - }; - union { - __IO uint32_t IRQ16MON; - stc_intreq_irq16mon_field_t IRQ16MON_f; - }; - union { - __IO uint32_t IRQ17MON; - stc_intreq_irq17mon_field_t IRQ17MON_f; - }; - union { - __IO uint32_t IRQ18MON; - stc_intreq_irq18mon_field_t IRQ18MON_f; - }; - union { - __IO uint32_t IRQ19MON; - stc_intreq_irq19mon_field_t IRQ19MON_f; - }; - union { - __IO uint32_t IRQ20MON; - stc_intreq_irq20mon_field_t IRQ20MON_f; - }; - union { - __IO uint32_t IRQ21MON; - stc_intreq_irq21mon_field_t IRQ21MON_f; - }; - union { - __IO uint32_t IRQ22MON; - stc_intreq_irq22mon_field_t IRQ22MON_f; - }; - union { - __IO uint32_t IRQ23MON; - stc_intreq_irq23mon_field_t IRQ23MON_f; - }; - union { - __IO uint32_t IRQ24MON; - stc_intreq_irq24mon_field_t IRQ24MON_f; - }; - union { - __IO uint32_t IRQ25MON; - stc_intreq_irq25mon_field_t IRQ25MON_f; - }; - union { - __IO uint32_t IRQ26MON; - stc_intreq_irq26mon_field_t IRQ26MON_f; - }; - union { - __IO uint32_t IRQ27MON; - stc_intreq_irq27mon_field_t IRQ27MON_f; - }; - union { - __IO uint32_t IRQ28MON; - stc_intreq_irq28mon_field_t IRQ28MON_f; - }; - union { - __IO uint32_t IRQ29MON; - stc_intreq_irq29mon_field_t IRQ29MON_f; - }; - union { - __IO uint32_t IRQ30MON; - stc_intreq_irq30mon_field_t IRQ30MON_f; - }; - union { - __IO uint32_t IRQ31MON; - stc_intreq_irq31mon_field_t IRQ31MON_f; - }; - union { - __IO uint32_t IRQ32MON; - stc_intreq_irq32mon_field_t IRQ32MON_f; - }; - union { - __IO uint32_t IRQ33MON; - stc_intreq_irq33mon_field_t IRQ33MON_f; - }; - union { - __IO uint32_t IRQ34MON; - stc_intreq_irq34mon_field_t IRQ34MON_f; - }; - union { - __IO uint32_t IRQ35MON; - stc_intreq_irq35mon_field_t IRQ35MON_f; - }; - __IO uint32_t IRQ36MON; - __IO uint32_t IRQ37MON; - union { - __IO uint32_t IRQ38MON; - stc_intreq_irq38mon_field_t IRQ38MON_f; - }; - union { - __IO uint32_t IRQ39MON; - stc_intreq_irq39mon_field_t IRQ39MON_f; - }; - union { - __IO uint32_t IRQ40MON; - stc_intreq_irq40mon_field_t IRQ40MON_f; - }; - union { - __IO uint32_t IRQ41MON; - stc_intreq_irq41mon_field_t IRQ41MON_f; - }; - union { - __IO uint32_t IRQ42MON; - stc_intreq_irq42mon_field_t IRQ42MON_f; - }; - union { - __IO uint32_t IRQ43MON; - stc_intreq_irq43mon_field_t IRQ43MON_f; - }; - union { - __IO uint32_t IRQ44MON; - stc_intreq_irq44mon_field_t IRQ44MON_f; - }; - union { - __IO uint32_t IRQ45MON; - stc_intreq_irq45mon_field_t IRQ45MON_f; - }; - __IO uint32_t IRQ46MON; - __IO uint32_t IRQ47MON; -}FM3_INTREQ_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - union { - __IO uint32_t PFR0; - stc_gpio_pfr0_field_t PFR0_f; - }; - union { - __IO uint32_t PFR1; - stc_gpio_pfr1_field_t PFR1_f; - }; - union { - __IO uint32_t PFR2; - stc_gpio_pfr2_field_t PFR2_f; - }; - union { - __IO uint32_t PFR3; - stc_gpio_pfr3_field_t PFR3_f; - }; - union { - __IO uint32_t PFR4; - stc_gpio_pfr4_field_t PFR4_f; - }; - union { - __IO uint32_t PFR5; - stc_gpio_pfr5_field_t PFR5_f; - }; - union { - __IO uint32_t PFR6; - stc_gpio_pfr6_field_t PFR6_f; - }; - union { - __IO uint32_t PFR7; - stc_gpio_pfr7_field_t PFR7_f; - }; - union { - __IO uint32_t PFR8; - stc_gpio_pfr8_field_t PFR8_f; - }; - uint8_t RESERVED0[220]; - union { - __IO uint32_t PCR0; - stc_gpio_pcr0_field_t PCR0_f; - }; - union { - __IO uint32_t PCR1; - stc_gpio_pcr1_field_t PCR1_f; - }; - union { - __IO uint32_t PCR2; - stc_gpio_pcr2_field_t PCR2_f; - }; - union { - __IO uint32_t PCR3; - stc_gpio_pcr3_field_t PCR3_f; - }; - union { - __IO uint32_t PCR4; - stc_gpio_pcr4_field_t PCR4_f; - }; - union { - __IO uint32_t PCR5; - stc_gpio_pcr5_field_t PCR5_f; - }; - union { - __IO uint32_t PCR6; - stc_gpio_pcr6_field_t PCR6_f; - }; - union { - __IO uint32_t PCR7; - stc_gpio_pcr7_field_t PCR7_f; - }; - uint8_t RESERVED1[224]; - union { - __IO uint32_t DDR0; - stc_gpio_ddr0_field_t DDR0_f; - }; - union { - __IO uint32_t DDR1; - stc_gpio_ddr1_field_t DDR1_f; - }; - union { - __IO uint32_t DDR2; - stc_gpio_ddr2_field_t DDR2_f; - }; - union { - __IO uint32_t DDR3; - stc_gpio_ddr3_field_t DDR3_f; - }; - union { - __IO uint32_t DDR4; - stc_gpio_ddr4_field_t DDR4_f; - }; - union { - __IO uint32_t DDR5; - stc_gpio_ddr5_field_t DDR5_f; - }; - union { - __IO uint32_t DDR6; - stc_gpio_ddr6_field_t DDR6_f; - }; - union { - __IO uint32_t DDR7; - stc_gpio_ddr7_field_t DDR7_f; - }; - union { - __IO uint32_t DDR8; - stc_gpio_ddr8_field_t DDR8_f; - }; - uint8_t RESERVED2[220]; - union { - __IO uint32_t PDIR0; - stc_gpio_pdir0_field_t PDIR0_f; - }; - union { - __IO uint32_t PDIR1; - stc_gpio_pdir1_field_t PDIR1_f; - }; - union { - __IO uint32_t PDIR2; - stc_gpio_pdir2_field_t PDIR2_f; - }; - union { - __IO uint32_t PDIR3; - stc_gpio_pdir3_field_t PDIR3_f; - }; - union { - __IO uint32_t PDIR4; - stc_gpio_pdir4_field_t PDIR4_f; - }; - union { - __IO uint32_t PDIR5; - stc_gpio_pdir5_field_t PDIR5_f; - }; - union { - __IO uint32_t PDIR6; - stc_gpio_pdir6_field_t PDIR6_f; - }; - union { - __IO uint32_t PDIR7; - stc_gpio_pdir7_field_t PDIR7_f; - }; - union { - __IO uint32_t PDIR8; - stc_gpio_pdir8_field_t PDIR8_f; - }; - uint8_t RESERVED3[220]; - union { - __IO uint32_t PDOR0; - stc_gpio_pdor0_field_t PDOR0_f; - }; - union { - __IO uint32_t PDOR1; - stc_gpio_pdor1_field_t PDOR1_f; - }; - union { - __IO uint32_t PDOR2; - stc_gpio_pdor2_field_t PDOR2_f; - }; - union { - __IO uint32_t PDOR3; - stc_gpio_pdor3_field_t PDOR3_f; - }; - union { - __IO uint32_t PDOR4; - stc_gpio_pdor4_field_t PDOR4_f; - }; - union { - __IO uint32_t PDOR5; - stc_gpio_pdor5_field_t PDOR5_f; - }; - union { - __IO uint32_t PDOR6; - stc_gpio_pdor6_field_t PDOR6_f; - }; - union { - __IO uint32_t PDOR7; - stc_gpio_pdor7_field_t PDOR7_f; - }; - union { - __IO uint32_t PDOR8; - stc_gpio_pdor8_field_t PDOR8_f; - }; - uint8_t RESERVED4[220]; - union { - __IO uint32_t ADE; - stc_gpio_ade_field_t ADE_f; - }; - uint8_t RESERVED5[124]; - union { - __IO uint32_t SPSR; - stc_gpio_spsr_field_t SPSR_f; - }; - uint8_t RESERVED6[124]; - union { - __IO uint32_t EPFR00; - stc_gpio_epfr00_field_t EPFR00_f; - }; - union { - __IO uint32_t EPFR01; - stc_gpio_epfr01_field_t EPFR01_f; - }; - union { - __IO uint32_t EPFR02; - stc_gpio_epfr02_field_t EPFR02_f; - }; - uint8_t RESERVED7[4]; - union { - __IO uint32_t EPFR04; - stc_gpio_epfr04_field_t EPFR04_f; - }; - union { - __IO uint32_t EPFR05; - stc_gpio_epfr05_field_t EPFR05_f; - }; - union { - __IO uint32_t EPFR06; - stc_gpio_epfr06_field_t EPFR06_f; - }; - union { - __IO uint32_t EPFR07; - stc_gpio_epfr07_field_t EPFR07_f; - }; - union { - __IO uint32_t EPFR08; - stc_gpio_epfr08_field_t EPFR08_f; - }; - union { - __IO uint32_t EPFR09; - stc_gpio_epfr09_field_t EPFR09_f; - }; - union { - __IO uint32_t EPFR10; - stc_gpio_epfr10_field_t EPFR10_f; - }; -}FM3_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - union { - __IO uint8_t LVD_CTL; - stc_lvd_lvd_ctl_field_t LVD_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t LVD_STR; - stc_lvd_lvd_str_field_t LVD_STR_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t LVD_CLR; - stc_lvd_lvd_clr_field_t LVD_CLR_f; - }; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - union { - __IO uint8_t LVD_STR2; - stc_lvd_lvd_str2_field_t LVD_STR2_f; - }; -}FM3_LVD_TypeDef; - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USB clock registers */ -typedef struct -{ - union { - __IO uint8_t UCCR; - stc_usbclk_uccr_field_t UCCR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t UPCR1; - stc_usbclk_upcr1_field_t UPCR1_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t UPCR2; - stc_usbclk_upcr2_field_t UPCR2_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t UPCR3; - stc_usbclk_upcr3_field_t UPCR3_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t UPCR4; - stc_usbclk_upcr4_field_t UPCR4_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t UP_STR; - stc_usbclk_up_str_field_t UP_STR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t UPINT_ENR; - stc_usbclk_upint_enr_field_t UPINT_ENR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t UPINT_CLR; - stc_usbclk_upint_clr_field_t UPINT_CLR_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint8_t UPINT_STR; - stc_usbclk_upint_str_field_t UPINT_STR_f; - }; - uint8_t RESERVED8[15]; - union { - __IO uint8_t USBEN; - stc_usbclk_usben_field_t USBEN_f; - }; -}FM3_USBCLK_TypeDef; - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CAN prescaler register */ -typedef struct -{ - union { - __IO uint8_t CANPRE; - stc_canpre_canpre_field_t CANPRE_f; - }; -}FM3_CANPRE_TypeDef; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs03_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs03_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_uart_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_UART_TypeDef; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_CSIO_TypeDef; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_lin_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_LIN_TypeDef; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* I2C channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs03_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs03_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs03_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs03_i2c_ismk_field_t ISMK_f; - }; -}FM3_MFS03_I2C_TypeDef; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs47_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs47_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_uart_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_uart_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_uart_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_uart_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_uart_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_uart_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_uart_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_UART_TypeDef; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_csio_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_csio_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_csio_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_csio_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_csio_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_csio_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_CSIO_TypeDef; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_lin_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_lin_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_lin_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_lin_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_lin_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_lin_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_lin_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_LIN_TypeDef; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* I2C channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs47_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs47_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs47_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs47_i2c_ismk_field_t ISMK_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_i2c_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_i2c_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_i2c_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_i2c_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_I2C_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - union { - __IO uint8_t CRCCR; - stc_crc_crccr_field_t CRCCR_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM3_CRC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - union { - __IO uint8_t WCRD; - stc_wc_wcrd_field_t WCRD_f; - }; - union { - __IO uint8_t WCRL; - stc_wc_wcrl_field_t WCRL_f; - }; - union { - __IO uint8_t WCCR; - stc_wc_wccr_field_t WCCR_f; - }; - uint8_t RESERVED0[13]; - union { - __IO uint16_t CLK_SEL; - stc_wc_clk_sel_field_t CLK_SEL_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t CLK_EN; - stc_wc_clk_en_field_t CLK_EN_f; - }; -}FM3_WC_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - union { - __IO uint32_t MODE0; - stc_exbus_mode0_field_t MODE0_f; - }; - union { - __IO uint32_t MODE1; - stc_exbus_mode1_field_t MODE1_f; - }; - union { - __IO uint32_t MODE2; - stc_exbus_mode2_field_t MODE2_f; - }; - union { - __IO uint32_t MODE3; - stc_exbus_mode3_field_t MODE3_f; - }; - union { - __IO uint32_t MODE4; - stc_exbus_mode4_field_t MODE4_f; - }; - union { - __IO uint32_t MODE5; - stc_exbus_mode5_field_t MODE5_f; - }; - union { - __IO uint32_t MODE6; - stc_exbus_mode6_field_t MODE6_f; - }; - union { - __IO uint32_t MODE7; - stc_exbus_mode7_field_t MODE7_f; - }; - union { - __IO uint32_t TIM0; - stc_exbus_tim0_field_t TIM0_f; - }; - union { - __IO uint32_t TIM1; - stc_exbus_tim1_field_t TIM1_f; - }; - union { - __IO uint32_t TIM2; - stc_exbus_tim2_field_t TIM2_f; - }; - union { - __IO uint32_t TIM3; - stc_exbus_tim3_field_t TIM3_f; - }; - union { - __IO uint32_t TIM4; - stc_exbus_tim4_field_t TIM4_f; - }; - union { - __IO uint32_t TIM5; - stc_exbus_tim5_field_t TIM5_f; - }; - union { - __IO uint32_t TIM6; - stc_exbus_tim6_field_t TIM6_f; - }; - union { - __IO uint32_t TIM7; - stc_exbus_tim7_field_t TIM7_f; - }; - union { - __IO uint32_t AREA0; - stc_exbus_area0_field_t AREA0_f; - }; - union { - __IO uint32_t AREA1; - stc_exbus_area1_field_t AREA1_f; - }; - union { - __IO uint32_t AREA2; - stc_exbus_area2_field_t AREA2_f; - }; - union { - __IO uint32_t AREA3; - stc_exbus_area3_field_t AREA3_f; - }; - union { - __IO uint32_t AREA4; - stc_exbus_area4_field_t AREA4_f; - }; - union { - __IO uint32_t AREA5; - stc_exbus_area5_field_t AREA5_f; - }; - union { - __IO uint32_t AREA6; - stc_exbus_area6_field_t AREA6_f; - }; - union { - __IO uint32_t AREA7; - stc_exbus_area7_field_t AREA7_f; - }; -}FM3_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - union { - __IO uint16_t HCNT; - stc_usb_hcnt_field_t HCNT_f; - }; - struct { - union { - __IO uint8_t HCNT0; - stc_usb_hcnt0_field_t HCNT0_f; - }; - union { - __IO uint8_t HCNT1; - stc_usb_hcnt1_field_t HCNT1_f; - }; - }; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t HIRQ; - stc_usb_hirq_field_t HIRQ_f; - }; - union { - __IO uint8_t HERR; - stc_usb_herr_field_t HERR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t HSTATE; - stc_usb_hstate_field_t HSTATE_f; - }; - union { - __IO uint8_t HFCOMP; - stc_usb_hfcomp_field_t HFCOMP_f; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t HRTIMER; - stc_usb_hrtimer_field_t HRTIMER_f; - }; - struct { - union { - __IO uint8_t HRTIMER0; - stc_usb_hrtimer0_field_t HRTIMER0_f; - }; - union { - __IO uint8_t HRTIMER1; - stc_usb_hrtimer1_field_t HRTIMER1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t HRTIMER2; - stc_usb_hrtimer2_field_t HRTIMER2_f; - }; - union { - __IO uint8_t HADR; - stc_usb_hadr_field_t HADR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t HEOF; - stc_usb_heof_field_t HEOF_f; - }; - struct { - union { - __IO uint8_t HEOF0; - stc_usb_heof0_field_t HEOF0_f; - }; - union { - __IO uint8_t HEOF1; - stc_usb_heof1_field_t HEOF1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t HFRAME; - stc_usb_hframe_field_t HFRAME_f; - }; - struct { - union { - __IO uint8_t HFRAME0; - stc_usb_hframe0_field_t HFRAME0_f; - }; - union { - __IO uint8_t HFRAME1; - stc_usb_hframe1_field_t HFRAME1_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t HTOKEN; - stc_usb_htoken_field_t HTOKEN_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t UDCC; - stc_usb_udcc_field_t UDCC_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t EP0C; - stc_usb_ep0c_field_t EP0C_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t EP1C; - stc_usb_ep1c_field_t EP1C_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint16_t EP2C; - stc_usb_ep2c_field_t EP2C_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t EP3C; - stc_usb_ep3c_field_t EP3C_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint16_t EP4C; - stc_usb_ep4c_field_t EP4C_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint16_t EP5C; - stc_usb_ep5c_field_t EP5C_f; - }; - uint8_t RESERVED14[2]; - union { - __IO uint16_t TMSP; - stc_usb_tmsp_field_t TMSP_f; - }; - uint8_t RESERVED15[2]; - union { - __IO uint8_t UDCS; - stc_usb_udcs_field_t UDCS_f; - }; - union { - __IO uint8_t UDCIE; - stc_usb_udcie_field_t UDCIE_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t EP0IS; - stc_usb_ep0is_field_t EP0IS_f; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t EP0OS; - stc_usb_ep0os_field_t EP0OS_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t EP1S; - stc_usb_ep1s_field_t EP1S_f; - }; - uint8_t RESERVED19[2]; - union { - __IO uint16_t EP2S; - stc_usb_ep2s_field_t EP2S_f; - }; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - union { - __IO uint16_t EP4S; - stc_usb_ep4s_field_t EP4S_f; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t EP5S; - stc_usb_ep5s_field_t EP5S_f; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM3_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - union { - __IO uint32_t DMACR; - stc_dmac_dmacr_field_t DMACR_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint32_t DMACA0; - stc_dmac_dmaca0_field_t DMACA0_f; - }; - union { - __IO uint32_t DMACB0; - stc_dmac_dmacb0_field_t DMACB0_f; - }; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - union { - __IO uint32_t DMACA1; - stc_dmac_dmaca1_field_t DMACA1_f; - }; - union { - __IO uint32_t DMACB1; - stc_dmac_dmacb1_field_t DMACB1_f; - }; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - union { - __IO uint32_t DMACA2; - stc_dmac_dmaca2_field_t DMACA2_f; - }; - union { - __IO uint32_t DMACB2; - stc_dmac_dmacb2_field_t DMACB2_f; - }; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - union { - __IO uint32_t DMACA3; - stc_dmac_dmaca3_field_t DMACA3_f; - }; - union { - __IO uint32_t DMACB3; - stc_dmac_dmacb3_field_t DMACB3_f; - }; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - union { - __IO uint32_t DMACA4; - stc_dmac_dmaca4_field_t DMACA4_f; - }; - union { - __IO uint32_t DMACB4; - stc_dmac_dmacb4_field_t DMACB4_f; - }; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - union { - __IO uint32_t DMACA5; - stc_dmac_dmaca5_field_t DMACA5_f; - }; - union { - __IO uint32_t DMACB5; - stc_dmac_dmacb5_field_t DMACB5_f; - }; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - union { - __IO uint32_t DMACA6; - stc_dmac_dmaca6_field_t DMACA6_f; - }; - union { - __IO uint32_t DMACB6; - stc_dmac_dmacb6_field_t DMACB6_f; - }; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - union { - __IO uint32_t DMACA7; - stc_dmac_dmaca7_field_t DMACA7_f; - }; - union { - __IO uint32_t DMACB7; - stc_dmac_dmacb7_field_t DMACB7_f; - }; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM3_DMAC_TypeDef; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN channel 0 registers */ -typedef struct -{ - union { - __IO uint16_t CTRLR; - stc_can_ctrlr_field_t CTRLR_f; - }; - union { - __IO uint16_t STATR; - stc_can_statr_field_t STATR_f; - }; - union { - __IO uint16_t ERRCNT; - stc_can_errcnt_field_t ERRCNT_f; - }; - union { - __IO uint16_t BTR; - stc_can_btr_field_t BTR_f; - }; - union { - __IO uint16_t INTR; - stc_can_intr_field_t INTR_f; - }; - union { - __IO uint16_t TESTR; - stc_can_testr_field_t TESTR_f; - }; - union { - __IO uint16_t BRPER; - stc_can_brper_field_t BRPER_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint16_t IF1CREQ; - stc_can_if1creq_field_t IF1CREQ_f; - }; - union { - __IO uint16_t IF1CMSK; - stc_can_if1cmsk_field_t IF1CMSK_f; - }; - union { - union { - __IO uint32_t IF1MSK; - stc_can_if1msk_field_t IF1MSK_f; - }; - struct { - __IO uint16_t IF1MSK1; - union { - __IO uint16_t IF1MSK2; - stc_can_if1msk2_field_t IF1MSK2_f; - }; - }; - }; - union { - union { - __IO uint32_t IF1ARB; - stc_can_if1arb_field_t IF1ARB_f; - }; - struct { - __IO uint16_t IF1ARB1; - union { - __IO uint16_t IF1ARB2; - stc_can_if1arb2_field_t IF1ARB2_f; - }; - }; - }; - union { - __IO uint16_t IF1MCTR; - stc_can_if1mctr_field_t IF1MCTR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint32_t IF1DTA_L; - struct { - __IO uint16_t IF1DTA1_L; - __IO uint16_t IF1DTA2_L; - }; - }; - union { - __IO uint32_t IF1DTB_L; - struct { - __IO uint16_t IF1DTB1_L; - __IO uint16_t IF1DTB2_L; - }; - }; - uint8_t RESERVED2[8]; - union { - __IO uint32_t IF1DTA_B; - struct { - __IO uint16_t IF1DTA2_B; - __IO uint16_t IF1DTA1_B; - }; - }; - union { - __IO uint32_t IF1DTB_B; - struct { - __IO uint16_t IF1DTB2_B; - __IO uint16_t IF1DTB1_B; - }; - }; - uint8_t RESERVED3[8]; - union { - __IO uint16_t IF2CREQ; - stc_can_if2creq_field_t IF2CREQ_f; - }; - union { - __IO uint16_t IF2CMSK; - stc_can_if2cmsk_field_t IF2CMSK_f; - }; - union { - union { - __IO uint32_t IF2MSK; - stc_can_if2msk_field_t IF2MSK_f; - }; - struct { - __IO uint16_t IF2MSK1; - union { - __IO uint16_t IF2MSK2; - stc_can_if2msk2_field_t IF2MSK2_f; - }; - }; - }; - union { - __IO uint32_t IF2ARB; - struct { - __IO uint16_t IF2ARB1; - union { - __IO uint16_t IF2ARB2; - stc_can_if2arb2_field_t IF2ARB2_f; - }; - }; - }; - union { - __IO uint16_t IF2MCTR; - stc_can_if2mctr_field_t IF2MCTR_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint32_t IF2DTA_L; - struct { - __IO uint16_t IF2DTA1_L; - __IO uint16_t IF2DTA2_L; - }; - }; - union { - __IO uint32_t IF2DTB_L; - struct { - __IO uint16_t IF2DTB1_L; - __IO uint16_t IF2DTB2_L; - }; - }; - uint8_t RESERVED5[8]; - union { - __IO uint32_t IF2DTA_B; - struct { - __IO uint16_t IF2DTA2_B; - __IO uint16_t IF2DTA1_B; - }; - }; - union { - __IO uint32_t IF2DTB_B; - struct { - __IO uint16_t IF2DTB2_B; - __IO uint16_t IF2DTB1_B; - }; - }; - uint8_t RESERVED6[24]; - union { - union { - __IO uint32_t TREQR; - stc_can_treqr_field_t TREQR_f; - }; - struct { - union { - __IO uint16_t TREQR1; - stc_can_treqr1_field_t TREQR1_f; - }; - union { - __IO uint16_t TREQR2; - stc_can_treqr2_field_t TREQR2_f; - }; - }; - }; - uint8_t RESERVED7[12]; - union { - union { - __IO uint32_t NEWDT; - stc_can_newdt_field_t NEWDT_f; - }; - struct { - union { - __IO uint16_t NEWDT1; - stc_can_newdt1_field_t NEWDT1_f; - }; - __IO uint16_t NEWDT2; - }; - }; - uint8_t RESERVED8[12]; - union { - union { - __IO uint32_t INTPND; - stc_can_intpnd_field_t INTPND_f; - }; - struct { - union { - __IO uint16_t INTPND1; - stc_can_intpnd1_field_t INTPND1_f; - }; - union { - __IO uint16_t INTPND2; - stc_can_intpnd2_field_t INTPND2_f; - }; - }; - }; - uint8_t RESERVED9[12]; - union { - union { - __IO uint32_t MSGVAL; - stc_can_msgval_field_t MSGVAL_f; - }; - struct { - union { - __IO uint16_t MSGVAL1; - stc_can_msgval1_field_t MSGVAL1_f; - }; - union { - __IO uint16_t MSGVAL2; - stc_can_msgval2_field_t MSGVAL2_f; - }; - }; - }; -}FM3_CAN_TypeDef; - - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ -#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ -#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ -#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ -#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ -#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ -#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ -#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ -#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ -#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ -#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ -#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ -#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ -#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ -#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ -#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ -#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ -#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ -#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ -#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ -#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ -#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ -#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ -#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ -#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ -#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ -#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ -#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ -#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ -#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ -#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ -#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ -#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ -#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ -#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ -#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) -#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) -#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) -#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) -#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) -#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) -#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) -#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) -#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) -#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) -#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) -#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) -#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) -#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) -#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) -#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) -#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) -#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) -#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) -#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) -#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) -#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) -#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) -#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) -#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) -#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) -#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) -#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) -#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) -#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) -#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) -#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) -#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) -#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) -#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) -#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) -#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) -#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) -#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) -#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) -#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) -#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) -#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) -#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) -#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) -#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) -#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) -#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) -#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) -#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) -#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) -#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) -#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) -#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) -#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) -#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) -#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) -#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) -#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) -#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) -#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) -#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) -#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) -#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) -#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) -#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) -#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) -#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) -#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) -#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) -#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) -#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) -#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) -#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) -#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) -#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) -#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) -#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) -#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) -#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) -#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) -#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) -#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) -#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) -#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) -#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) -#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) -#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) -#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) -#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) -#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) -#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) -#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) -#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) -#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) -#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) -#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) -#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) -#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) -#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) -#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) -#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Flash interface registers */ -#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) -#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) - -/* Clock and reset registers */ -#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) -#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) -#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) - -/* Dual timer 1/2 registers */ -#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) -#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) -#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) -#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) -#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) -#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) -#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) -#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) -#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) -#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) -#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) -#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) -#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) -#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) -#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) -#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) -#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) -#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) -#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) -#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) -#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) -#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) -#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) -#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) -#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) -#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) -#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) -#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) -#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) -#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) -#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) -#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) -#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) -#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) -#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) -#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) -#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) -#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) -#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) -#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) -#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) -#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) -#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) -#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) -#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) -#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) -#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) -#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) -#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) -#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) -#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) -#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) -#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) -#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) -#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) -#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) -#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) -#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) -#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) -#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) -#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) -#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) -#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) -#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) -#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) -#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) -#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) -#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) -#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) -#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) -#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) -#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) -#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) -#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) -#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) -#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) -#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) -#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) -#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) -#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) -#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) -#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) -#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) -#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) -#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) -#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) -#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) -#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) -#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) -#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) -#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) -#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) -#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) -#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) -#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) -#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) -#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) -#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) -#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) -#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) -#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) -#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) -#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) -#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) -#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) -#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) -#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) -#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) -#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) -#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) -#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) -#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) -#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) -#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) -#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) -#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) -#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) -#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) -#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) -#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) -#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) -#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) -#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) -#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) -#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) -#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) -#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) -#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) -#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) -#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) -#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) -#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) -#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) -#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) -#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) -#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) -#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) -#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) -#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) -#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) -#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) -#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) -#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) -#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) -#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) -#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) -#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) -#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) -#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) -#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) -#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) -#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) -#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) -#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) -#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) -#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) -#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) -#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) -#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) -#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) -#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) -#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) -#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) -#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) -#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) -#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) -#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) -#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) -#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) -#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) -#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) -#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) -#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) -#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) -#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) -#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) -#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) -#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) -#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) -#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) -#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) -#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) -#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) -#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) -#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) -#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) -#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) -#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) -#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) -#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) -#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) -#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) -#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) -#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) -#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) -#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) -#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) -#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) -#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) -#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) -#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) -#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) -#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) -#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) -#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) -#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) -#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) -#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) -#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) -#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) -#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) -#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) - -/* CR trimming registers */ -#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) - -/* External interrupt registers */ -#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) -#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) -#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) -#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) -#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) -#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) -#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) -#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) -#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) -#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) -#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) -#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) -#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) -#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) -#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) -#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) -#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) -#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) -#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) -#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) -#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) -#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) -#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) -#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) -#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) -#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) -#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) -#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) -#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) - -/* General purpose I/O registers */ -#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) -#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) -#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) -#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) -#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) -#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) -#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) -#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) -#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) -#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) -#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) -#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) -#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) -#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) -#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) -#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) -#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) -#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) -#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) -#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) -#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) -#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) -#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) -#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) -#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) -#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) -#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) -#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) -#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) -#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) -#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) -#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) -#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) -#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) -#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) -#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) -#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) -#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) -#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) -#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) -#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) -#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) -#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) -#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) -#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) -#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) -#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) -#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) -#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) -#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) -#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) -#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) -#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) -#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) -#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) -#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) -#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) -#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) -#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) -#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) -#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) -#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) -#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) -#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) -#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) -#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) -#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) -#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) -#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) -#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) -#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) -#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) -#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) -#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) -#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) -#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) -#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) -#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) -#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) -#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) -#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) -#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) -#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) -#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) -#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) -#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) -#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) -#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) -#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) -#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) -#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) -#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) -#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) -#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) -#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) -#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) -#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) -#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) -#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) -#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) -#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) -#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) -#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) -#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) -#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) -#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) -#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) -#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) -#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) -#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) -#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) -#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) -#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) -#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) -#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) -#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) -#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) -#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) -#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) -#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) -#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) -#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) -#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) -#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) -#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) -#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) -#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) -#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) -#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) -#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) -#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) -#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) -#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) -#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) -#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) -#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) -#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) -#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) -#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) -#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) -#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) -#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) -#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) -#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) -#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) -#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) -#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) -#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) -#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) -#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) -#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) -#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) -#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) -#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) -#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) -#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) -#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) -#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) -#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) -#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) -#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) -#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) -#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) -#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) -#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) -#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) -#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) -#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) -#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) -#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) -#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) -#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) -#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) -#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) -#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) -#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) -#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) -#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) -#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) -#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) -#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) -#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) -#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) -#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) -#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) -#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) -#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) -#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) -#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) -#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) -#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) -#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) -#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) -#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) -#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) -#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) -#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) -#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) -#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) -#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) -#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) -#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) -#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) -#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) -#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) -#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) -#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) -#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) -#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) -#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) -#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) -#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) -#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) -#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) -#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) -#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) -#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) -#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) -#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) -#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) -#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) -#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) -#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) -#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) -#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) -#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) -#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) -#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) -#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) -#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) -#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) -#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) -#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) -#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) -#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) -#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) -#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) -#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) -#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) -#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) -#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) -#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) -#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) -#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) -#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) -#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) -#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) -#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) -#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) -#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) -#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) -#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) -#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) -#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) -#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) -#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) -#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) -#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) -#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) -#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) -#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) -#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) -#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) -#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) -#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) -#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) -#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) -#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) -#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) -#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) -#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) -#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) -#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) -#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) -#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) -#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) -#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) -#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) -#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) -#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) -#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) -#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) -#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) -#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) -#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) -#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) -#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) -#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) -#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) -#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) -#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) -#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) -#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) -#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) -#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) -#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) -#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) -#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) -#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) -#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) -#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) -#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) -#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) -#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) -#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) -#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) -#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) -#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) -#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) -#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) -#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) -#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) -#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) -#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) -#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) -#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) -#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) -#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) -#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) -#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) -#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) -#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) -#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) -#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) -#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) -#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) -#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) -#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) -#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) -#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) -#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) -#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) -#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) -#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) -#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) -#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) -#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) -#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) -#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) -#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) -#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) -#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) -#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) -#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) -#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) -#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) -#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) -#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) -#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) -#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) -#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) -#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) -#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) -#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) -#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) -#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) -#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) -#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) -#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) -#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) -#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) -#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) -#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) -#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) -#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) -#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) -#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) -#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) -#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) -#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) -#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) -#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) -#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) -#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) -#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) -#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) -#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) -#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) -#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) -#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) -#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) -#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) -#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) -#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) -#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) -#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) -#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) -#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) -#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) -#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) -#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) -#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) -#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) -#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) -#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) -#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) -#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) -#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) -#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) -#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) -#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) -#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) -#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) -#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) -#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) -#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) -#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) -#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) -#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) -#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) -#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) -#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) -#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) -#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) -#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) -#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) -#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) -#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) -#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) -#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) -#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) -#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) -#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) -#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) -#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) -#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) -#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) -#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) -#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) -#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) -#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) -#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) -#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) -#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) -#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) -#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) -#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) -#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) -#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) -#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) -#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) -#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) -#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) -#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) -#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) -#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) -#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) -#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) -#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) -#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) -#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) -#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) -#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) -#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) -#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) -#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) -#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) -#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) -#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) -#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) -#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) -#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) -#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) -#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) -#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) -#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) -#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) -#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) -#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) -#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) -#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) -#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) -#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) -#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) -#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) -#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) -#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) -#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) -#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) -#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) -#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) -#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) -#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) -#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) -#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) -#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) -#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) -#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) -#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) -#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) -#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) -#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) -#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) -#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) -#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) -#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) -#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) -#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) -#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) -#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) -#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) -#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) -#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) -#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) -#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) -#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) -#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) -#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) -#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) -#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) -#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) -#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) -#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) -#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) -#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) -#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) -#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) -#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) -#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) -#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) -#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) -#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) -#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) -#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) -#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) -#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) -#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) -#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) -#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) -#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) -#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) -#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) -#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) -#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) -#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) -#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) -#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) -#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) -#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) -#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) -#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) -#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) -#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) -#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) -#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) -#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) -#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) -#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) -#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) -#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) -#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) -#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) -#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) -#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) -#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) -#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) -#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) -#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) -#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) -#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) -#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) -#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) -#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) -#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) -#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) -#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) -#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) -#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) -#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) -#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) -#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) -#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) -#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) -#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) -#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) -#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) -#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) -#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) -#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) -#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) -#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) -#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) -#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) -#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) -#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) -#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) -#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) -#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) -#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) -#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) -#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) -#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) -#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) -#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) -#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) -#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) -#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) -#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) -#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) -#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) -#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) -#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) -#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) -#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) -#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) -#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) -#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) -#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) -#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) -#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) -#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) -#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) -#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) -#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) -#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) -#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) -#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) -#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) -#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) -#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) -#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) -#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) -#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) -#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) -#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) -#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) -#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) -#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) -#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) -#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) -#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) -#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) -#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) -#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) -#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) -#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) -#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) -#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) -#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) -#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) -#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) -#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) -#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) -#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) -#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) -#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) -#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) -#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) -#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) -#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) -#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) -#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) -#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) -#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) -#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) -#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) -#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) -#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) -#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) -#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) -#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) -#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) -#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) -#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) -#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) -#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) -#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) -#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) -#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) -#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) -#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) -#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) -#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) -#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) -#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) -#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) -#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) -#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) -#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) -#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) -#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) -#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) -#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) -#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) -#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) -#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) -#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) -#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) -#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) -#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) -#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) -#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) -#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) -#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) -#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) -#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) -#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) -#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) -#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) -#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) -#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) -#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) -#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) -#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) -#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) -#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) -#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) -#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) -#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) -#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) -#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) -#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) -#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) -#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) -#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) -#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) -#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) -#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) -#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) -#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) -#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) -#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) -#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) -#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) -#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) -#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) -#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) -#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) -#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) -#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) -#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) -#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) -#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) -#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) -#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) -#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) -#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) -#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) -#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) -#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) -#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) -#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) -#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) -#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) - -/* Low voltage detection registers */ -#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* USB clock registers */ -#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) -#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) -#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) - -/* CAN prescaler register */ -#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) -#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) -#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) -#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) - -/* UART asynchronous channel 0 registers */ -#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* UART synchronous channel 0 registers */ -#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) - -/* UART LIN channel 0 registers */ -#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* I2C channel 0 registers */ -#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) - -/* UART asynchronous channel 1 registers */ -#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* UART synchronous channel 1 registers */ -#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) - -/* UART LIN channel 1 registers */ -#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* I2C channel 1 registers */ -#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) - -/* UART asynchronous channel 2 registers */ -#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* UART synchronous channel 2 registers */ -#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) - -/* UART LIN channel 2 registers */ -#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* I2C channel 2 registers */ -#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) - -/* UART asynchronous channel 3 registers */ -#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* UART synchronous channel 3 registers */ -#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) - -/* UART LIN channel 3 registers */ -#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* I2C channel 3 registers */ -#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) - -/* UART asynchronous channel 4 registers */ -#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART synchronous channel 4 registers */ -#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART LIN channel 4 registers */ -#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* I2C channel 4 registers */ -#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART asynchronous channel 5 registers */ -#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART synchronous channel 5 registers */ -#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART LIN channel 5 registers */ -#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* I2C channel 5 registers */ -#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART asynchronous channel 6 registers */ -#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART synchronous channel 6 registers */ -#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART LIN channel 6 registers */ -#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* I2C channel 6 registers */ -#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART asynchronous channel 7 registers */ -#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART synchronous channel 7 registers */ -#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART LIN channel 7 registers */ -#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* I2C channel 7 registers */ -#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* CRC registers */ -#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* External bus interface registers */ -#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) -#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) -#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) -#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) -#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) -#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) -#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) -#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) -#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) -#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) -#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) -#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) -#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) -#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) -#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) -#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) -#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) -#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) -#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) -#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) -#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) -#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) -#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) -#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) -#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) -#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) -#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) -#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) -#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) -#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) -#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) -#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) -#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) -#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) -#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) -#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) -#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) -#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) -#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) -#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) -#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) -#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) -#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) -#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) -#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) -#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) -#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) -#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) -#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) -#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) -#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) -#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) -#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) -#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) -#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) -#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) -#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) -#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) -#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) -#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) -#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) -#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) -#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) -#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) -#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) -#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) -#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) -#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) -#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) -#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) -#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) -#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) -#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) -#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) -#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) -#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) -#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) -#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) -#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) -#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) -#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) -#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) -#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) -#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) -#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) -#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) -#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) -#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) -#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) -#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) -#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) -#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) -#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) -#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) -#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) -#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) -#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) -#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) -#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) -#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) -#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) -#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) -#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) -#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) -#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) -#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) -#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) -#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) -#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) -#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) -#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) -#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) -#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) -#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) -#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) -#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) -#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) -#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) -#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) -#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) -#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) -#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) -#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) -#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) -#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) -#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) -#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) -#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) -#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) -#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) -#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) -#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) -#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) -#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) -#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) -#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) -#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) -#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) -#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) -#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) -#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) -#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) -#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) -#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) -#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) -#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) -#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) -#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) -#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) -#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) -#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) -#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) -#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) -#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) -#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) -#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) -#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) -#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) -#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) -#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) -#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) -#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) -#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) -#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) -#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) -#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) -#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) -#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) -#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) -#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) -#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) -#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) - -/* USB channel 0 registers */ -#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) -#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* DMA controller */ -#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* CAN channel 0 registers */ -#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) -#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) -#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) -#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) -#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) -#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) -#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) -#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) -#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) -#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) -#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) -#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) -#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) -#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) -#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) -#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) -#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) -#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) -#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) -#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) -#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) -#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) -#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) -#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) -#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) -#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) -#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) -#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) -#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) -#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) -#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) -#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) -#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) -#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) -#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) -#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) -#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) -#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) -#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) -#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) -#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) -#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) -#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) -#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) -#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) -#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) -#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) -#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) -#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) -#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) -#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) -#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) -#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) -#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) -#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) -#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) -#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) -#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) -#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) -#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) -#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) -#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) -#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) -#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) -#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) -#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) -#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) -#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) -#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) -#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) -#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) -#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) -#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) -#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) -#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) -#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) -#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) -#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) -#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) -#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) -#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) -#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) -#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) -#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) -#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) -#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) -#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) -#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) -#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) -#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) -#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) -#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) -#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) -#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) -#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) -#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) -#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) -#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) -#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) -#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) -#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) -#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) -#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) -#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) -#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) -#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) -#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) -#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) -#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) -#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) -#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) -#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) -#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) -#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) -#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) - -/* CAN channel 1 registers */ -#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) -#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) -#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) -#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) -#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) -#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) -#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) -#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) -#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) -#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) -#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) -#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) -#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) -#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) -#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) -#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) -#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) -#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) -#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) -#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) -#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) -#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) -#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) -#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) -#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) -#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) -#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) -#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) -#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) -#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) -#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) -#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) -#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) -#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) -#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) -#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) -#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) -#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) -#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) -#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) -#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) -#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) -#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) -#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) -#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) -#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) -#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) -#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) -#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) -#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) -#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) -#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) -#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) -#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) -#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) -#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) -#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) -#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) -#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) -#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) -#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) -#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) -#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) -#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) -#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) -#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) -#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) -#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) -#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) -#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) -#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) -#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) -#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) -#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) -#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) -#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) -#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) -#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) -#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) -#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) -#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) -#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) -#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) -#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) -#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) -#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) -#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) -#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) -#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) -#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) -#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) -#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) -#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) -#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) -#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) -#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) -#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) -#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) -#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) -#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) -#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) -#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) -#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) -#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) -#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) -#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) -#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) -#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) -#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) -#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) -#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) -#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) -#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) -#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) -#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9BF506R_H_ */ - diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h deleted file mode 100644 index 4e5eff2db3..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h +++ /dev/null @@ -1,62 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/** - ****************************************************************************** - ** \file mcu.h - ** - ** Header File for device dependent includes - ** - ** History: - ** 2011-05-19 V1.00 MWi first version - ** - ******************************************************************************/ - -/** - ****************************************************************************** - ** \brief MCU header file include - ** - ******************************************************************************/ -#ifndef _MB9BF506R_H_ - #include "mb9bf506r.h" -#endif - -/** - ****************************************************************************** - ** \brief MCU system start-up header file include - ** - ******************************************************************************/ -#ifndef _SYSTEM_MB9BF50X_H_ - #include "system_mb9bf50x.h" -#endif - - diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h deleted file mode 100644 index 947349e2af..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/system_mb9bf50x.h +++ /dev/null @@ -1,679 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/** \file system_mb9bf50x.h - ** - ** Headerfile for FM3 system parameters - ** - ** User clock definitions can be done for the following clock settings: - ** - CLOCK_SETUP : Execute the clock settings form the settings below in - ** SystemInit() - ** - __CLKMO : External clock frequency for main oscillion - ** - __CLKSO : External clock frequency for sub oscillion - ** - SCM_CTL : System Clock Mode Control Register - ** - BSC_PSR : Base Clock Prescaler Register - ** - APBC0_PSR : APB0 Prescaler Register - ** - APBC1_PSR : APB1 Prescaler Register - ** - APBC2_PSR : APB2 Prescaler Register - ** - SWC_PSR : Software Watchdog Clock Prescaler Register - ** - TTC_PSR : Trace Clock Prescaler Register - ** - CSW_TMR : Clock Stabilization Wait Time Register - ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register - ** - PLL_CTL1 : PLL Control Register 1 - ** - PLL_CTL2 : PLL Control Register 2 - ** - ** The register settings are check for correct values of reserved bits. - ** Otherwise a preprocessor error is output and stops the build process. - ** Furthermore the 'master clock' is retrieved from the register settings - ** and the system clock (HCLK) is calculated from the Base Clock Prescaler - ** Register (BSC_PSR). This value is used for the global CMSIS variable - ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is - ** is checked. Note that not all possible wrong setting are checked! The - ** user has to take care to fulfill the settings stated in the according - ** device's data sheet! - ** - ** User definition for Hardware Watchdog: - ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit() - ** - ** User definition for CR Trimming: - ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit() - ** - ** History: - ** 2011-05-16 V1.0 MWi original version - ** 2011-12-20 V1.1 EH corresponded to C++ - *****************************************************************************/ - -#ifndef _SYSTEM_MB9BF50X_H_ -#define _SYSTEM_MB9BF50X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************/ -/* Include files */ -/******************************************************************************/ - -#include - -/******************************************************************************/ -/* Global pre-processor symbols/macros ('define') */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* START OF USER SETTINGS HERE */ -/* =========================== */ -/* */ -/* All lines with '<<<' can be set by user. */ -/* */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Clock Setup Enable - ** (USER SETTING) - ** - ** - 0 = No clock setup done by system_mb9xfxxx.c - ** - 1 = Clock setup done by system_mb9xfxxx.c - ******************************************************************************/ -#define CLOCK_SETUP 1 // <<< Define clock setup here - -/** - ****************************************************************************** - ** \brief External Main Clock Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal - -/** - ****************************************************************************** - ** \brief External Sub Clock Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal - -/** - ****************************************************************************** - ** \brief System Clock Mode Control Register value definition - ** (USER SETTING) - ** - ** SCM_CTL - ** - ** Bit#7-5 : RCS[2:0] - ** - 0 = Internal high-speed CR oscillation (default) - ** - 1 = Main oscillation clock - ** - 2 = PLL oscillation clock - ** - 3 = (not allowed) - ** - 4 = Internal low-speed CR oscillation - ** - 5 = Sub clock oscillation - ** - 6 = (not allowed) - ** - 7 = (not allowed) - ** - ** Bit#4 : PLLE - ** - 0 = Disable PLL (default) - ** - 1 = Enable PLL - ** - ** Bit#3 : SOSCE - ** - 0 = Disable sub oscillation (default) - ** - 1 = Enable sub oscillation - ** - ** Bit#2 : (reserved) - ** - ** Bit#1 : MOSCE - ** - 0 = Disable main oscillation (default) - ** - 1 = Enable main oscillation - ** - ** Bit#0 : (reserved) - ******************************************************************************/ -#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here - -/** - ****************************************************************************** - ** \brief Base Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** BSC_PSR - ** - ** Bit#7-3 : (reserved) - ** - ** Bit#2-0 : BSR[2:0] - ** - 0 = HCLK = Master Clock - ** - 1 = HCLK = Master Clock / 2 - ** - 2 = HCLK = Master Clock / 3 - ** - 3 = HCLK = Master Clock / 4 - ** - 4 = HCLK = Master Clock / 6 - ** - 5 = HCLK = Master Clock / 8 - ** - 6 = HCLK = Master Clock / 16 - ** - 7 = (reserved) - ******************************************************************************/ -#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here - -/** - ****************************************************************************** - ** \brief APB0 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC0_PSR - ** - ** Bit#7-2 : (reserved) - ** - ** Bit#1-0 : BSR[2:0] - ** - 0 = PCLK0 = HCLK - ** - 1 = PCLK0 = HCLK / 2 - ** - 2 = PCLK0 = HCLK / 4 - ** - 3 = PCLK0 = HCLK / 8 - ******************************************************************************/ -#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here - -/** - ****************************************************************************** - ** \brief APB1 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC1_PSR - ** - ** Bit#7 : APBC1EN - ** - 0 = Disable PCLK1 output - ** - 1 = Enables PCLK1 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC1RST - ** - 0 = APB1 bus reset, inactive (default) - ** - 1 = APB1 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC1[2:0] - ** - 0 = PCLK1 = HCLK - ** - 1 = PCLK1 = HCLK / 2 - ** - 2 = PCLK1 = HCLK / 4 - ** - 3 = PCLK1 = HCLK / 8 - ******************************************************************************/ -#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here - -/** - ****************************************************************************** - ** \brief APB2 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC2_PSR - ** - ** Bit#7 : APBC2EN - ** - 0 = Disable PCLK2 output - ** - 1 = Enables PCLK2 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC2RST - ** - 0 = APB2 bus reset, inactive (default) - ** - 1 = APB2 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC2[1:0] - ** - 0 = PCLK2 = HCLK - ** - 1 = PCLK2 = HCLK / 2 - ** - 2 = PCLK2 = HCLK / 4 - ** - 3 = PCLK2 = HCLK / 8 - ******************************************************************************/ -#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here - -/** - ****************************************************************************** - ** \brief Software Watchdog Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** SWC_PSR - ** - ** Bit#7 : TESTB - ** - 0 = (not allowed) - ** - 1 = (always write "1" to this bit) - ** - ** Bit#6-2 : (reserved) - ** - ** Bit#1-0 : SWDS[2:0] - ** - 0 = SWDGOGCLK = PCLK0 - ** - 1 = SWDGOGCLK = PCLK0 / 2 - ** - 2 = SWDGOGCLK = PCLK0 / 4 - ** - 3 = SWDGOGCLK = PCLK0 / 8 - ******************************************************************************/ -#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here - -/** - ****************************************************************************** - ** \brief Trace Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** TTC_PSR - ** - ** Bit#7-1 : (reserved) - ** - ** Bit#0 : TTC - ** - 0 = TPIUCLK = HCLK - ** - 1 = TPIUCLK = HCLK / 2 - ******************************************************************************/ -#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here - -/** - ****************************************************************************** - ** \brief Clock Stabilization Wait Time Register value definition - ** (USER SETTING) - ** - ** CSW_TMR - ** - ** Bit#7 : (reserved) - ** - ** Bit#6-4 : SOWT[2:0] - ** - 0 = ~10.3 ms (default) - ** - 1 = ~20.5 ms - ** - 2 = ~41 ms - ** - 3 = ~82 ms - ** - 4 = ~164 ms - ** - 5 = ~327 ms - ** - 6 = ~655 ms - ** - 7 = ~1.31 s - ** - ** Bit#3-0 : MOWT[3:0] - ** - 0 = ~500 ns (default) - ** - 1 = ~8 us - ** - 2 = ~16 us - ** - 3 = ~32 us - ** - 4 = ~64 us - ** - 5 = ~128 us - ** - 6 = ~256 us - ** - 7 = ~512 us - ** - 8 = ~1.0 ms - ** - 9 = ~2.0 ms - ** - 10 = ~4.0 ms - ** - 11 = ~8.0 ms - ** - 12 = ~33.0 ms - ** - 13 = ~131 ms - ** - 14 = ~524 ms - ** - 15 = ~2.0 s - ******************************************************************************/ -#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Clock Stabilization Wait Time Setup Register value definition - ** (USER SETTING) - ** - ** PSW_TMR - ** - ** Bit#7-5 : (reserved) - ** - ** Bit#4 : PINC - ** - 0 = Selects CLKMO (main oscillation) (default) - ** - 1 = (setting diabled) - ** - ** Bit#3 : (reserved) - ** - ** Bit#2-0 : POWT[2:0] - ** - 0 = ~128 us (default) - ** - 1 = ~256 us - ** - 2 = ~512 us - ** - 3 = ~1.02 ms - ** - 4 = ~2.05 ms - ** - 5 = ~4.10 ms - ** - 6 = ~8.20 ms - ** - 7 = ~16.40 ms - ******************************************************************************/ -#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Control Register 1 value definition - ** (USER SETTING) - ** - ** PLL_CTL1 - ** - ** Bit#7-4 : PLLK[3:0] - ** - 0 = Division(PLLK) = 1/1 (default) - ** - 1 = Division(PLLK) = 1/2 - ** - 2 = Division(PLLK) = 1/3 - ** - . . . - ** - 15 = Division(PLLK) = 1/16 - ** - ** Bit#3-0 : PLLM[3:0] - ** - 0 = Division(PLLM) = 1/1 (default) - ** - 1 = Division(PLLM) = 1/2 - ** - 2 = Division(PLLM) = 1/3 - ** - . . . - ** - 15 = Division(PLLM) = 1/16 - ******************************************************************************/ -#define PLL_CTL1_Val 0x00000000 // <<< Define PLL_CTL1 here - -/** - ****************************************************************************** - ** \brief PLL Control Register 2 value definition - ** (USER SETTING) - ** - ** PLL_CTL2 - ** - ** Bit#7-6 : (reserved) - ** - ** Bit#5-0 : PLLN[5:0] - ** - 0 = Division(PLLN) = 1/1 (default) - ** - 1 = Division(PLLN) = 1/2 - ** - 2 = Division(PLLN) = 1/3 - ** - . . . - ** - 63 = Division(PLLN) = 1/64 - ******************************************************************************/ -#define PLL_CTL2_Val 0x00000013 // <<< Define PLL_CTL2 here - -/** - ****************************************************************************** - ** \brief Hardware Watchdog disable definition - ** (USER SETTING) - ** - ** - 0 = Hardware Watchdog enable - ** - 1 = Hardware Watchdog disable - ******************************************************************************/ -#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here - -/** - ****************************************************************************** - ** \brief Trimming CR - ** (USER SETTING) - ** - ** - 0 = CR is not trimmed at startup - ** - 1 = CR is trimmed at startup - ******************************************************************************/ -#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here - - -/******************************************************************************/ -/* */ -/* END OF USER SETTINGS HERE */ -/* ========================= */ -/* */ -/******************************************************************************/ - -/******************************************************************************/ -/* Device dependent System Clock absolute maximum ranges */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMIN ( 4000000UL) - -/** - ****************************************************************************** - ** \brief Maximum Main Clock frequency using external clock - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMAX ( 48000000UL) - -/** - ****************************************************************************** - ** \brief Any case minimum Sub Clock frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMIN ( 32000UL) - -/** - ****************************************************************************** - ** \brief Maximum Sub Clock frequency using external clock - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMAX ( 100000UL) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL input frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMIN ( 4000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL input frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMAX ( 30000000UL) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL oscillation frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMIN ( 60000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL oscillation frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMAX (120000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum System Clock frequency (HCLK) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __HCLKMAX ( 80000000UL) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking range (clock settings) - ******************************************************************************/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking bits with mask (clock settings) - ******************************************************************************/ -#define CHECK_RSVD(val, mask) (val & mask) - - -/******************************************************************************/ -/* Check register settings */ -/******************************************************************************/ -#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA)) - #error "SCM_CTL: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10) - #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" -#endif - -#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F)) - #error "CSW_TMR: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */ - #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007)) - #error "PSW_TMR: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF)) - #error "PLL_CTL1: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F)) - #error "PLL_CTL2: Invalid values of reserved bits!" - #endif -#endif - -#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007)) - #error "BSC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003)) - #error "APBC0_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083)) - #error "APBC1_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083)) - #error "APBC2_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003)) - #error "SWC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001)) - #error "TTC_PSR: Invalid values of reserved bits!" -#endif - -/******************************************************************************/ -/* Define clocks with checking settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Calculate PLL K factor from settings - ******************************************************************************/ -#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL N factor from settings - ******************************************************************************/ -#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL M factor from settings - ******************************************************************************/ -#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL output frequency from settings - ******************************************************************************/ -#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) - -/******************************************************************************/ -/* Determine core clock frequency according to settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Define Master Clock from settings - ******************************************************************************/ -#if (((SCM_CTL_Val >> 5) & 0x07) == 0) - #define __MASTERCLK (__CLKHC) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 1) - #define __MASTERCLK (__CLKMO) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 2) - #define __MASTERCLK (__PLLCLK) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 4) - #define __MASTERCLK (__CLKLC) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 5) - #define __MASTERCLK (__CLKSO) -#else - #define __MASTERCLK (0UL) -#endif - -/** - ****************************************************************************** - ** \brief Define System Clock Frequency (Core Clock) from settings - ******************************************************************************/ -#if ((BSC_PSR_Val & 0x07) == 0) - #define __HCLK (__MASTERCLK / 1) -#elif ((BSC_PSR_Val & 0x07) == 1) - #define __HCLK (__MASTERCLK / 2) -#elif ((BSC_PSR_Val & 0x07) == 2) - #define __HCLK (__MASTERCLK / 3) -#elif ((BSC_PSR_Val & 0x07) == 3) - #define __HCLK (__MASTERCLK / 4) -#elif ((BSC_PSR_Val & 0x07) == 4) - #define __HCLK (__MASTERCLK / 6) -#elif ((BSC_PSR_Val & 0x07) == 5) - #define __HCLK (__MASTERCLK / 8) -#elif ((BSC_PSR_Val & 0x07) == 6) - #define __HCLK (__MASTERCLK /16) -#else - #define __HCLK (0UL) -#endif - -/******************************************************************************/ -/* HCLK range check */ -/******************************************************************************/ -#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0) - #error "Main Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0) - #error "Sub Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0) - #error "PLL input frequency out of range!" -#endif - -#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0) - #error "PLL oscillation frequency out of range!" -#endif - -#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0) - #error "System Clock (HCLK) out of range!" -#endif - -/******************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/******************************************************************************/ - -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) - -extern void SystemInit (void); // Initialize the system - -extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S deleted file mode 100644 index 3d163aa6dd..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S +++ /dev/null @@ -1,327 +0,0 @@ -;/************************************************************************/ -;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -;/* */ -;/* The following software deliverable is intended for and must only be */ -;/* used for reference and in an evaluation laboratory environment. */ -;/* It is provided on an as-is basis without charge and is subject to */ -;/* alterations. */ -;/* It is the user's obligation to fully test the software in its */ -;/* environment and to ensure proper functionality, qualification and */ -;/* compliance with component specifications. */ -;/* */ -;/* In the event the software deliverable includes the use of open */ -;/* source components, the provisions of the governing open source */ -;/* license agreement shall apply with respect to such software */ -;/* deliverable. */ -;/* FSEU does not warrant that the deliverables do not infringe any */ -;/* third party intellectual property right (IPR). In the event that */ -;/* the deliverables infringe a third party IPR it is the sole */ -;/* responsibility of the customer to obtain necessary licenses to */ -;/* continue the usage of the deliverable. */ -;/* */ -;/* To the maximum extent permitted by applicable law FSEU disclaims all */ -;/* warranties, whether express or implied, in particular, but not */ -;/* limited to, warranties of merchantability and fitness for a */ -;/* particular purpose for which the deliverable is not designated. */ -;/* */ -;/* To the maximum extent permitted by applicable law, FSEU's liability */ -;/* is restricted to intentional misconduct and gross negligence. */ -;/* FSEU is not liable for consequential damages. */ -;/* */ -;/* (V1.5) */ -;/************************************************************************/ -;/* Startup for ARM */ -;/* Version V1.02 */ -;/* Date 2011-01-12 */ -;/* Target-mcu MB9B5xx */ -;/************************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; 32: CAN ch.0 - DCD CAN1_IRQHandler ; 33: CAN ch.1 - DCD USBF_Handler ; 34: USB Function - DCD USB_Handler ; 35: USB Function / USB HOST - DCD DummyHandler ; 36: Reserved - DCD DummyHandler ; 37: Reserved - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD DummyHandler ; 46: Reserved - DCD DummyHandler ; 47: Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT CSV_Handler [WEAK] - EXPORT SWDT_Handler [WEAK] - EXPORT LVD_Handler [WEAK] - EXPORT MFT_WG_IRQHandler [WEAK] - EXPORT INT0_7_Handler [WEAK] - EXPORT INT8_15_Handler [WEAK] - EXPORT DT_Handler [WEAK] - EXPORT MFS0RX_IRQHandler [WEAK] - EXPORT MFS0TX_IRQHandler [WEAK] - EXPORT MFS1RX_IRQHandler [WEAK] - EXPORT MFS1TX_IRQHandler [WEAK] - EXPORT MFS2RX_IRQHandler [WEAK] - EXPORT MFS2TX_IRQHandler [WEAK] - EXPORT MFS3RX_IRQHandler [WEAK] - EXPORT MFS3TX_IRQHandler [WEAK] - EXPORT MFS4RX_IRQHandler [WEAK] - EXPORT MFS4TX_IRQHandler [WEAK] - EXPORT MFS5RX_IRQHandler [WEAK] - EXPORT MFS5TX_IRQHandler [WEAK] - EXPORT MFS6RX_IRQHandler [WEAK] - EXPORT MFS6TX_IRQHandler [WEAK] - EXPORT MFS7RX_IRQHandler [WEAK] - EXPORT MFS7TX_IRQHandler [WEAK] - EXPORT PPG_Handler [WEAK] - EXPORT TIM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT MFT_FRT_IRQHandler [WEAK] - EXPORT MFT_IPC_IRQHandler [WEAK] - EXPORT MFT_OPC_IRQHandler [WEAK] - EXPORT BT_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT USBF_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT DMAC0_Handler [WEAK] - EXPORT DMAC1_Handler [WEAK] - EXPORT DMAC2_Handler [WEAK] - EXPORT DMAC3_Handler [WEAK] - EXPORT DMAC4_Handler [WEAK] - EXPORT DMAC5_Handler [WEAK] - EXPORT DMAC6_Handler [WEAK] - EXPORT DMAC7_Handler [WEAK] - EXPORT DummyHandler [WEAK] - -CSV_Handler -SWDT_Handler -LVD_Handler -MFT_WG_IRQHandler -INT0_7_Handler -INT8_15_Handler -DT_Handler -MFS0RX_IRQHandler -MFS0TX_IRQHandler -MFS1RX_IRQHandler -MFS1TX_IRQHandler -MFS2RX_IRQHandler -MFS2TX_IRQHandler -MFS3RX_IRQHandler -MFS3TX_IRQHandler -MFS4RX_IRQHandler -MFS4TX_IRQHandler -MFS5RX_IRQHandler -MFS5TX_IRQHandler -MFS6RX_IRQHandler -MFS6TX_IRQHandler -MFS7RX_IRQHandler -MFS7TX_IRQHandler -PPG_Handler -TIM_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -MFT_FRT_IRQHandler -MFT_IPC_IRQHandler -MFT_OPC_IRQHandler -BT_IRQHandler -CAN0_IRQHandler -CAN1_IRQHandler -USBF_Handler -USB_Handler -DMAC0_Handler -DMAC1_Handler -DMAC2_Handler -DMAC3_Handler -DMAC4_Handler -DMAC5_Handler -DMAC6_Handler -DMAC7_Handler -DummyHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S deleted file mode 100644 index 72981f1edb..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S +++ /dev/null @@ -1,290 +0,0 @@ -/**************************************************************************//** - * @file startup_.s - * @brief CMSIS Cortex-M# Core Device Startup File for - * Device - * @version V3.01 - * @date 06. March 2012 - * - * @note Version CodeSourcery Sourcery G++ Lite (with CS3) - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Stack_Size, 0x00000400 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Heap_Size, 0x00000100 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ -/* ToDo: Add here the vectors for the device specific external interrupts handler */ - .long CSV_Handler /* 0: Clock Super Visor */ - .long SWDT_Handler /* 1: Software Watchdog Timer */ - .long LVD_Handler /* 2: Low Voltage Detector */ - .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ - .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ - .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ - .long DT_Handler /* 6: Dual Timer / Quad Decoder */ - .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ - .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ - .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ - .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ - .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ - .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ - .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ - .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ - .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ - .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ - .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ - .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ - .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ - .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ - .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ - .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ - .long PPG_Handler /* 23: PPG */ - .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ - .long ADC0_IRQHandler /* 25: ADC0 */ - .long ADC1_IRQHandler /* 26: ADC1 */ - .long ADC2_IRQHandler /* 27: ADC2 */ - .long MFT_FRT_IRQHandler /* 28: Free-run Timer */ - .long MFT_IPC_IRQHandler /* 29: Input Capture */ - .long MFT_OPC_IRQHandler /* 30: Output Compare */ - .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ - .long CAN0_IRQHandler /* 32: CAN ch.0 */ - .long CAN1_IRQHandler /* 33: CAN ch.1 */ - .long USBF_Handler /* 34: USB Function */ - .long USB_Handler /* 35: USB Function / USB HOST */ - .long RESERVED_1_IRQHandler /* 36: Reserved */ - .long RESERVED_2_IRQHandler /* 37: Reserved */ - .long DMAC0_Handler /* 38: DMAC ch.0 */ - .long DMAC1_Handler /* 39: DMAC ch.1 */ - .long DMAC2_Handler /* 40: DMAC ch.2 */ - .long DMAC3_Handler /* 41: DMAC ch.3 */ - .long DMAC4_Handler /* 42: DMAC ch.4 */ - .long DMAC5_Handler /* 43: DMAC ch.5 */ - .long DMAC6_Handler /* 44: DMAC ch.6 */ - .long DMAC7_Handler /* 45: DMAC ch.7 */ - .long RESERVED_3_IRQHandler /* 46: Reserved */ - .long RESERVED_4_IRQHandler /* 47: Reserved */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .globl _start - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: -_start: - .fnstart - LDR R0, =SystemInit - BLX R0 - LDR R0,=_start - BX R0 - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - -/* ToDo: Add here the export definition for the device specific external interrupts handler */ -/* ToDo: Add here the names for the device specific external interrupts handler */ - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ CSV_Handler /* 0: Clock Super Visor */ - IRQ SWDT_Handler /* 1: Software Watchdog Timer */ - IRQ LVD_Handler /* 2: Low Voltage Detector */ - IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ - IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ - IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ - IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */ - IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ - IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ - IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ - IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ - IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ - IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ - IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ - IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ - IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ - IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ - IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ - IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ - IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ - IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ - IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ - IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ - IRQ PPG_Handler /* 23: PPG */ - IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ - IRQ ADC0_IRQHandler /* 25: ADC0 */ - IRQ ADC1_IRQHandler /* 26: ADC1 */ - IRQ ADC2_IRQHandler /* 27: ADC2 */ - IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */ - IRQ MFT_IPC_IRQHandler /* 29: Input Capture */ - IRQ MFT_OPC_IRQHandler /* 30: Output Compare */ - IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ - IRQ CAN0_IRQHandler /* 32: CAN ch.0 */ - IRQ CAN1_IRQHandler /* 33: CAN ch.1 */ - IRQ USBF_Handler /* 34: USB Function */ - IRQ USB_Handler /* 35: USB Function / USB HOST */ - IRQ RESERVED_1_IRQHandler /* 36: Reserved */ - IRQ RESERVED_2_IRQHandler /* 37: Reserved */ - IRQ DMAC0_Handler /* 38: DMAC ch.0 */ - IRQ DMAC1_Handler /* 39: DMAC ch.1 */ - IRQ DMAC2_Handler /* 40: DMAC ch.2 */ - IRQ DMAC3_Handler /* 41: DMAC ch.3 */ - IRQ DMAC4_Handler /* 42: DMAC ch.4 */ - IRQ DMAC5_Handler /* 43: DMAC ch.5 */ - IRQ DMAC6_Handler /* 44: DMAC ch.6 */ - IRQ DMAC7_Handler /* 45: DMAC ch.7 */ - IRQ RESERVED_3_IRQHandler /* 46: Reserved */ - IRQ RESERVED_4_IRQHandler /* 47: Reserved */ - - .end diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S deleted file mode 100644 index 9ac63778f5..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S +++ /dev/null @@ -1,402 +0,0 @@ -;/************************************************************************/ -;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -;/* */ -;/* The following software deliverable is intended for and must only be */ -;/* used for reference and in an evaluation laboratory environment. */ -;/* It is provided on an as-is basis without charge and is subject to */ -;/* alterations. */ -;/* It is the user's obligation to fully test the software in its */ -;/* environment and to ensure proper functionality, qualification and */ -;/* compliance with component specifications. */ -;/* */ -;/* In the event the software deliverable includes the use of open */ -;/* source components, the provisions of the governing open source */ -;/* license agreement shall apply with respect to such software */ -;/* deliverable. */ -;/* FSEU does not warrant that the deliverables do not infringe any */ -;/* third party intellectual property right (IPR). In the event that */ -;/* the deliverables infringe a third party IPR it is the sole */ -;/* responsibility of the customer to obtain necessary licenses to */ -;/* continue the usage of the deliverable. */ -;/* */ -;/* To the maximum extent permitted by applicable law FSEU disclaims all */ -;/* warranties, whether express or implied, in particular, but not */ -;/* limited to, warranties of merchantability and fitness for a */ -;/* particular purpose for which the deliverable is not designated. */ -;/* */ -;/* To the maximum extent permitted by applicable law, FSEU's liability */ -;/* is restricted to intentional misconduct and gross negligence. */ -;/* FSEU is not liable for consequential damages. */ -;/* */ -;/* (V1.5) */ -;/************************************************************************/ -;/* Startup for IAR */ -;/* Version V1.02 */ -;/* Date 2011-01-05 */ -;/* Target-mcu MB9B5xx */ -;/************************************************************************/ - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset - DCD NMI_Handler ; NMI - DCD HardFault_Handler ; Hard Fault - DCD MemManage_Handler ; MPU Fault - DCD BusFault_Handler ; Bus Fault - DCD UsageFault_Handler ; Usage Fault - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall - DCD DebugMon_Handler ; Debug Monitor - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV - DCD SysTick_Handler ; SysTick - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; 32: CAN ch.0 - DCD CAN1_IRQHandler ; 33: CAN ch.1 - DCD USBF_Handler ; 34: USB Function - DCD USB_Handler ; 35: USB Function / USB HOST - DCD DummyHandler ; 36: Reserved - DCD DummyHandler ; 37: Reserved - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD DummyHandler ; 46: Reserved - DCD DummyHandler ; 47: Reserved - - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - - - PUBWEAK CSV_Handler - SECTION .text:CODE:REORDER(1) -CSV_Handler - B CSV_Handler - - PUBWEAK SWDT_Handler - SECTION .text:CODE:REORDER(1) -SWDT_Handler - B SWDT_Handler - - PUBWEAK LVD_Handler - SECTION .text:CODE:REORDER(1) -LVD_Handler - B LVD_Handler - - PUBWEAK MFT_WG_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_WG_IRQHandler - B MFT_WG_IRQHandler - - PUBWEAK INT0_7_Handler - SECTION .text:CODE:REORDER(1) -INT0_7_Handler - B INT0_7_Handler - - PUBWEAK INT8_15_Handler - SECTION .text:CODE:REORDER(1) -INT8_15_Handler - B INT8_15_Handler - - PUBWEAK DT_Handler - SECTION .text:CODE:REORDER(1) -DT_Handler - B DT_Handler - - PUBWEAK MFS0RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0RX_IRQHandler - B MFS0RX_IRQHandler - - PUBWEAK MFS0TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0TX_IRQHandler - B MFS0TX_IRQHandler - - PUBWEAK MFS1RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1RX_IRQHandler - B MFS1RX_IRQHandler - - PUBWEAK MFS1TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1TX_IRQHandler - B MFS1TX_IRQHandler - - PUBWEAK MFS2RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2RX_IRQHandler - B MFS2RX_IRQHandler - - PUBWEAK MFS2TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2TX_IRQHandler - B MFS2TX_IRQHandler - - PUBWEAK MFS3RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3RX_IRQHandler - B MFS3RX_IRQHandler - - PUBWEAK MFS3TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3TX_IRQHandler - B MFS3TX_IRQHandler - - PUBWEAK MFS4RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4RX_IRQHandler - B MFS4RX_IRQHandler - - PUBWEAK MFS4TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4TX_IRQHandler - B MFS4TX_IRQHandler - - PUBWEAK MFS5RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5RX_IRQHandler - B MFS5RX_IRQHandler - - PUBWEAK MFS5TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5TX_IRQHandler - B MFS5TX_IRQHandler - - PUBWEAK MFS6RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6RX_IRQHandler - B MFS6RX_IRQHandler - - PUBWEAK MFS6TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6TX_IRQHandler - B MFS6TX_IRQHandler - - PUBWEAK MFS7RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7RX_IRQHandler - B MFS7RX_IRQHandler - - PUBWEAK MFS7TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7TX_IRQHandler - B MFS7TX_IRQHandler - - PUBWEAK PPG_Handler - SECTION .text:CODE:REORDER(1) -PPG_Handler - B PPG_Handler - - PUBWEAK TIM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM_IRQHandler - B TIM_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK MFT_FRT_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_FRT_IRQHandler - B MFT_FRT_IRQHandler - - PUBWEAK MFT_IPC_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_IPC_IRQHandler - B MFT_IPC_IRQHandler - - PUBWEAK MFT_OPC_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_OPC_IRQHandler - B MFT_OPC_IRQHandler - - PUBWEAK BT_IRQHandler - SECTION .text:CODE:REORDER(1) -BT_IRQHandler - B BT_IRQHandler - - PUBWEAK CAN0_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN0_IRQHandler - B CAN0_IRQHandler - - PUBWEAK CAN1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_IRQHandler - B CAN1_IRQHandler - - PUBWEAK USBF_Handler - SECTION .text:CODE:REORDER(1) -USBF_Handler - B USBF_Handler - - PUBWEAK USB_Handler - SECTION .text:CODE:REORDER(1) -USB_Handler - B USB_Handler - - PUBWEAK DMAC0_Handler - SECTION .text:CODE:REORDER(1) -DMAC0_Handler - B DMAC0_Handler - - - PUBWEAK DMAC1_Handler - SECTION .text:CODE:REORDER(1) -DMAC1_Handler - B DMAC1_Handler - - PUBWEAK DMAC2_Handler - SECTION .text:CODE:REORDER(1) -DMAC2_Handler - B DMAC2_Handler - - PUBWEAK DMAC3_Handler - SECTION .text:CODE:REORDER(1) -DMAC3_Handler - B DMAC3_Handler - - PUBWEAK DMAC4_Handler - SECTION .text:CODE:REORDER(1) -DMAC4_Handler - B DMAC4_Handler - - PUBWEAK DMAC5_Handler - SECTION .text:CODE:REORDER(1) -DMAC5_Handler - B DMAC5_Handler - - PUBWEAK DMAC6_Handler - SECTION .text:CODE:REORDER(1) -DMAC6_Handler - B DMAC6_Handler - - PUBWEAK DMAC7_Handler - SECTION .text:CODE:REORDER(1) -DMAC7_Handler - B DMAC7_Handler - - PUBWEAK DummyHandler - SECTION .text:CODE:REORDER(1) -DummyHandler - B DummyHandler - - END diff --git a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c b/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c deleted file mode 100644 index 6ccf1ff957..0000000000 --- a/bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c +++ /dev/null @@ -1,202 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ - -#include "mcu.h" - -/** \file system_mb9bf50x.c - ** - ** FM3 system initialization functions - ** All adjustments can be done in belonging header file. - ** - ** History: - ** 2011-05-16 V1.0 MWi original version - ******************************************************************************/ - -/** - ****************************************************************************** - ** System Clock Frequency (Core Clock) Variable according CMSIS - ******************************************************************************/ -uint32_t SystemCoreClock = __HCLK; - -/** - ****************************************************************************** - ** \brief Update the System Core Clock with current core Clock retrieved from - ** cpu registers. - ** \param none - ** \return none - ******************************************************************************/ -void SystemCoreClockUpdate (void) { - uint32_t masterClk; - uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance - - switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) { - case 0: /* internal High-speed Cr osc. */ - masterClk = __CLKHC; - break; - - case 1: /* external main osc. */ - masterClk = __CLKMO; - break; - - case 2: /* PLL clock */ - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violation: - // "Unordered accesses to a volatile location" - u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1)); - masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1)); - break; - - case 4: /* internal Low-speed CR osc. */ - masterClk = __CLKLC; - break; - - case 5: /* external Sub osc. */ - masterClk = __CLKSO; - break; - - default: - masterClk = 0Ul; - break; - } - - switch (FM3_CRG->BSC_PSR & 0x07) { - case 0: - SystemCoreClock = masterClk; - break; - - case 1: - SystemCoreClock = masterClk / 2; - break; - - case 2: - SystemCoreClock = masterClk / 3; - break; - - case 3: - SystemCoreClock = masterClk / 4; - break; - - case 4: - SystemCoreClock = masterClk / 6; - break; - - case 5: - SystemCoreClock = masterClk /8; - break; - - case 6: - SystemCoreClock = masterClk /16; - break; - - default: - SystemCoreClock = 0Ul; - break; - } - -} - -/** - ****************************************************************************** - ** \brief Setup the microcontroller system. Initialize the System and update - ** the SystemCoreClock variable. - ** - ** \param none - ** \return none - ******************************************************************************/ -void SystemInit (void) { - - static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance - -#if (HWWD_DISABLE) /* HW Watchdog Disable */ - FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */ - FM3_HWWDT->WDG_LCK = 0xE5331AAE; - FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */ -#endif - -#if (CLOCK_SETUP) /* Clock Setup */ - FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */ - FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */ - FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */ - FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */ - FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */ - FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */ - - FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */ - - if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */ - while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */ - } - - if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ - while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ - } - - FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */ - FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */ - FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */ - - if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */ - while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */ - } - - FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */ - - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violations: - // "Unordered reads and writes to or from same location" and - // "Unordered accesses to a volatile location" - do - { - u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0); - }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead); -#endif // (CLOCK_SETUP) - -#if (CR_TRIM_SETUP) - /* CR Trimming Data */ - if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) ) - { - /* UnLock (MCR_FTRM) */ - FM3_CRTRIM->MCR_RLR = 0x1ACCE554; - /* Set MCR_FTRM */ - FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM; - /* Lock (MCR_FTRM) */ - FM3_CRTRIM->MCR_RLR = 0x00000000; - } -#endif // (CR_TRIM_SETUP) -} - - - diff --git a/bsp/mb9bf506r/libraries/SConscript b/bsp/mb9bf506r/libraries/SConscript deleted file mode 100644 index a0fa5ca72d..0000000000 --- a/bsp/mb9bf506r/libraries/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -src = ['Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c'] - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += ['Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S'] -elif rtconfig.CROSS_TOOL == 'keil': - src += ['Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src += ['Device/FUJISTU/MB9BF50x/Source/IAR/startup_mb9bf50x.S'] - -CPPPATH = [cwd + '/Device/FUJISTU/MB9BF50x/Include'] - -CPPPATH += [cwd + '/CMSIS/Include'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf506r/project.ewp b/bsp/mb9bf506r/project.ewp deleted file mode 100644 index a258e109b6..0000000000 --- a/bsp/mb9bf506r/project.ewp +++ /dev/null @@ -1,1945 +0,0 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Applications - - $PROJ_DIR$\applications\application.c - - - $PROJ_DIR$\applications\startup.c - - - - CMSIS - - $PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c - - - $PROJ_DIR$\libraries\Device\FUJISTU\MB9BF50x\Source\IAR\startup_mb9bf50x.S - - - - Compiler - - $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\time.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c - - - - CPU - - $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c - - - $PROJ_DIR$\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S - - - - DeviceDrivers - - $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\ringblk_buf.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\pipe.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\ringbuffer.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\waitqueue.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\completion.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\workqueue.c - - - $PROJ_DIR$\..\..\components\drivers\serial\serial.c - - - - Drivers - - $PROJ_DIR$\drivers\fm3_uart.c - - - $PROJ_DIR$\drivers\led.c - - - $PROJ_DIR$\drivers\nand.c - - - $PROJ_DIR$\drivers\board.c - - - - Finsh - - $PROJ_DIR$\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\components\finsh\msh.c - - - - Kernel - - $PROJ_DIR$\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\src\mem.c - - - $PROJ_DIR$\..\..\src\idle.c - - - $PROJ_DIR$\..\..\src\memheap.c - - - $PROJ_DIR$\..\..\src\irq.c - - - $PROJ_DIR$\..\..\src\object.c - - - $PROJ_DIR$\..\..\src\components.c - - - $PROJ_DIR$\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\src\thread.c - - - $PROJ_DIR$\..\..\src\clock.c - - - $PROJ_DIR$\..\..\src\timer.c - - - $PROJ_DIR$\..\..\src\device.c - - - $PROJ_DIR$\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\src\scheduler.c - - - - POSIX - - - utestcases - - diff --git a/bsp/mb9bf506r/project.eww b/bsp/mb9bf506r/project.eww deleted file mode 100644 index c2cb02eb1e..0000000000 --- a/bsp/mb9bf506r/project.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/mb9bf506r/project.uvproj b/bsp/mb9bf506r/project.uvproj deleted file mode 100644 index 8eaab29744..0000000000 --- a/bsp/mb9bf506r/project.uvproj +++ /dev/null @@ -1,697 +0,0 @@ - - - 1.1 -
### uVision Project, (C) Keil Software
- - - rtthread-fm3 - 0x4 - ARM-ADS - - - MB9BF506R - Fujitsu Semiconductors - IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFF8000-0x1FFFFFFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - - "Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000) - 5216 - MB9BF506R.h - - - - - - - - - - SFD\Fujitsu\MB9B500\MB9BF506R.SFR - 0 - - - - Fujitsu\MB9B500\ - Fujitsu\MB9B500\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-stm32 - 1 - 0 - 0 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - - 0 - 7 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 0 - 0x1fff8000 - 0x8000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND - - applications;.;libraries\Device\FUJISTU\MB9BF50x\Include;libraries\CMSIS\Include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc;..\..\examples\utest\testcases\kernel - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - Applications - - - application.c - 1 - applications\application.c - - - - - startup.c - 1 - applications\startup.c - - - - - CMSIS - - - startup_mb9bf50x.S - 2 - libraries\Device\FUJISTU\MB9BF50x\Source\ARM\startup_mb9bf50x.S - - - - - system_mb9bf50x.c - 1 - libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - time.c - 1 - ..\..\components\libc\compilers\common\time.c - - - - - stdlib.c - 1 - ..\..\components\libc\compilers\common\stdlib.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - DeviceDrivers - - - ringbuffer.c - 1 - ..\..\components\drivers\ipc\ringbuffer.c - - - - - completion.c - 1 - ..\..\components\drivers\ipc\completion.c - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\ipc\ringblk_buf.c - - - - - dataqueue.c - 1 - ..\..\components\drivers\ipc\dataqueue.c - - - - - pipe.c - 1 - ..\..\components\drivers\ipc\pipe.c - - - - - workqueue.c - 1 - ..\..\components\drivers\ipc\workqueue.c - - - - - waitqueue.c - 1 - ..\..\components\drivers\ipc\waitqueue.c - - - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - - - Drivers - - - led.c - 1 - drivers\led.c - - - - - board.c - 1 - drivers\board.c - - - - - nand.c - 1 - drivers\nand.c - - - - - fm3_uart.c - 1 - drivers\fm3_uart.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - Kernel - - - components.c - 1 - ..\..\src\components.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - device.c - 1 - ..\..\src\device.c - - - - - memheap.c - 1 - ..\..\src\memheap.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - clock.c - 1 - ..\..\src\clock.c - - - - - - - diff --git a/bsp/mb9bf506r/rtconfig.h b/bsp/mb9bf506r/rtconfig.h deleted file mode 100644 index b7b675ab20..0000000000 --- a/bsp/mb9bf506r/rtconfig.h +++ /dev/null @@ -1,179 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -// - -// -#define RT_NAME_MAX 8 -// -#define RT_ALIGN_SIZE 8 -// -// 8 -// 32 -// 256 -// -#define RT_THREAD_PRIORITY_MAX 32 -// -#define RT_TICK_PER_SECOND 100 -//
-// #define RT_DEBUG -// -// #define RT_THREAD_DEBUG -// -#define RT_USING_OVERFLOW_CHECK -//
- -// -#define RT_USING_HOOK -//
-// #define RT_USING_TIMER_SOFT -// -#define RT_TIMER_THREAD_PRIO 8 -// -#define RT_TIMER_THREAD_STACK_SIZE 512 -// -#define RT_TIMER_TICK_PER_SECOND 10 -//
- -//
-// -#define RT_USING_SEMAPHORE -// -#define RT_USING_MUTEX -// -#define RT_USING_EVENT -// -#define RT_USING_MAILBOX -// -#define RT_USING_MESSAGEQUEUE -//
- -//
-// -#define RT_USING_MEMPOOL -// -#define RT_USING_MEMHEAP -// -#define RT_USING_HEAP -// -#define RT_USING_SMALL_MEM -// -// #define RT_USING_SLAB -//
- -//
-#define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA -// -#define RT_USING_UART0_0 -// -// #define RT_USING_UART0_1 -// -// #define RT_USING_UART1_0 -// -// #define RT_USING_UART1_1 -// -// #define RT_USING_UART2_0 -// -// #define RT_USING_UART2_1 -// -// #define RT_USING_UART2_2 -// -// #define RT_USING_UART3_0 -// -// #define RT_USING_UART3_1 -// -// #define RT_USING_UART3_2 -// -// #define RT_USING_UART4_0 -// -// #define RT_USING_UART4_1 -// -#define RT_USING_UART4_2 -// -// #define RT_USING_UART5_0 -// -// #define RT_USING_UART5_1 -// -// #define RT_USING_UART5_2 -// -// #define RT_USING_UART6_0 -// -// #define RT_USING_UART6_1 -// -#define RT_USING_UART7_0 -// -// #define RT_USING_UART7_1 -// -#define RT_UART_RX_BUFFER_SIZE 64 -//
- -//
-#define RT_USING_CONSOLE -// -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart0" -//
- -// -#define RT_USING_COMPONENTS_INIT -//
-#define RT_USING_FINSH -// -#define FINSH_USING_SYMTAB -// -#define FINSH_USING_DESCRIPTION -// -#define FINSH_THREAD_STACK_SIZE 4096 -//
- -//
-// -// #define RT_USING_NEWLIB -// -// #define RT_USING_PTHREADS -//
- -//
-// #define RT_USING_DFS -// -// #define DFS_USING_WORKDIR -// -#define DFS_FILESYSTEMS_MAX 2 -// -#define DFS_FD_MAX 4 -// -#define RT_USING_DFS_ELMFAT -// -// 1 -// 2 -// -#define RT_DFS_ELM_USE_LFN 1 -// -#define RT_DFS_ELM_MAX_LFN 64 -// -// #define RT_USING_DFS_YAFFS2 -// -// #define RT_USING_DFS_UFFS -// -// #define RT_USING_DFS_DEVFS -// -// #define RT_USING_DFS_NFS -// -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" -//
- -// -// #define RT_USING_CMSIS_OS -// -// #define RT_USING_BSP_CMSIS - -// - -#endif diff --git a/bsp/mb9bf506r/rtconfig.py b/bsp/mb9bf506r/rtconfig.py deleted file mode 100644 index d8b525f291..0000000000 --- a/bsp/mb9bf506r/rtconfig.py +++ /dev/null @@ -1,121 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='iar' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-mb9bf506.ld -nostartfiles' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter rtthread-mb9bf506.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - CFLAGS = '' - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' - - LFLAGS = ' --config rtthread-mb9bf506.icf' - LFLAGS += ' --semihosting' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf506r/rtthread-mb9bf506.icf b/bsp/mb9bf506r/rtthread-mb9bf506.icf deleted file mode 100644 index 66b859d099..0000000000 --- a/bsp/mb9bf506r/rtthread-mb9bf506.icf +++ /dev/null @@ -1,34 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF8000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/mb9bf506r/rtthread-mb9bf506.ld b/bsp/mb9bf506r/rtthread-mb9bf506.ld deleted file mode 100644 index 644c891306..0000000000 --- a/bsp/mb9bf506r/rtthread-mb9bf506.ld +++ /dev/null @@ -1,221 +0,0 @@ -/* Linker script to configure memory regions - * - * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 - * BugURL:https://support.codesourcery.com/GNUToolchain/ - * - * Copyright 2007 CodeSourcery. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. */ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -ENTRY(_start) -SEARCH_DIR(.) - -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512k */ - ram (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 0x00010000 /* 32k */ -} - -/* These force the linker to search for particular symbols from - * the start of the link process and thus ensure the user's - * overrides are picked up - */ -EXTERN(__cs3_reset_cortex_m) -EXTERN(__cs3_interrupt_vector_cortex_m) -EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) - -PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); -PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); -PROVIDE(__cs3_heap_start = _end); -PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - __cs3_region_start_rom = .; - *(.cs3.region-head.rom) - __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; - *(.cs3.interrupt_vector) - /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); - *(.rom) - *(.rom.b) - - __cs3_reset = __cs3_reset_cortex_m; - *(.cs3.reset) - /* Make sure we pulled in some reset code. */ - ASSERT (. != __cs3_reset, "No reset code"); - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - *(.gnu.warning) - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - __cs3_regions = .; - LONG (0) - LONG (__cs3_region_init_ram) - LONG (__cs3_region_start_ram) - LONG (__cs3_region_init_size_ram) - LONG (__cs3_region_zero_size_ram) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - } - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >rom - __exidx_end = .; - .text.align : - { - . = ALIGN(8); - _etext = .; - } >rom - __cs3_region_size_rom = LENGTH(rom); - __cs3_region_num = 1; - - .data : - { - __cs3_region_start_ram = .; - *(.cs3.region-head.ram) - KEEP(*(.jcr)) - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - *(.ram) - . = ALIGN (8); - _edata = .; - } >ram AT>rom - - .bss : - { - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - *(.ram.b) - . = ALIGN (8); - _end = .; - __end = .; - } >ram AT>rom - - .heap : - { - *(.heap) - } >ram - - __bss_end = .; - - .stack (__cs3_stack - __cs3_stack_size) : - { - *(.stack) - } >ram - - __cs3_region_init_ram = LOADADDR (.data); - __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; - __cs3_region_zero_size_ram = _end - _edata; - __cs3_region_size_ram = LENGTH(ram); - __cs3_region_num = 1; - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } - .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) } -} diff --git a/bsp/mb9bf506r/rtthread-mb9bf506.sct b/bsp/mb9bf506r/rtthread-mb9bf506.sct deleted file mode 100644 index 6a8744246a..0000000000 --- a/bsp/mb9bf506r/rtthread-mb9bf506.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00080000 { ; load region size_region - ER_IROM1 0x00000000 0x00080000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00008000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/mb9bf506r/template.ewp b/bsp/mb9bf506r/template.ewp deleted file mode 100644 index 40100eb5cb..0000000000 --- a/bsp/mb9bf506r/template.ewp +++ /dev/null @@ -1,1739 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/mb9bf506r/template.uvproj b/bsp/mb9bf506r/template.uvproj deleted file mode 100644 index 137c045dea..0000000000 --- a/bsp/mb9bf506r/template.uvproj +++ /dev/null @@ -1,388 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rtthread-fm3 - 0x4 - ARM-ADS - - - MB9BF506R - Fujitsu Semiconductors - IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFF8000-0x1FFFFFFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - - "Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000) - 5216 - MB9BF506R.h - - - - - - - - - - SFD\Fujitsu\MB9B500\MB9BF506R.SFR - 0 - - - - Fujitsu\MB9B500\ - Fujitsu\MB9B500\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-stm32 - 1 - 0 - 0 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - - 0 - 7 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 0 - 0x1fff8000 - 0x8000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s b/bsp/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s deleted file mode 100644 index 416a56f41d..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s +++ /dev/null @@ -1,584 +0,0 @@ -;******************************************************************************* -; Copyright (C) 2013 Spansion LLC. All Rights Reserved. -; -; This software is owned and published by: -; Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). -; -; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND -; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. -; -; This software contains source code for use with Spansion -; components. This software is licensed by Spansion to be adapted only -; for use in systems utilizing Spansion components. Spansion shall not be -; responsible for misuse or illegal use of this software for devices not -; supported herein. Spansion is providing this software "AS IS" and will -; not be responsible for issues arising from incorrect user implementation -; of the software. -; -; SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, -; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), -; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, -; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED -; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED -; WARRANTY OF NONINFRINGEMENT. -; SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, -; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT -; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, -; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR -; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, -; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, -; SAVINGS OR PROFITS, -; EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR -; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED -; FROM, THE SOFTWARE. -; -; This software may be replicated in part or whole for the licensed use, -; with the restriction that this Disclaimer and Copyright notice must be -; included with each copy of this software, whether used in part or whole, -; at all times. -; - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; Numbered IRQ handler vectors - -; Note: renaming to device dependent ISR function names are done in -; pdl.h (section "IRQ name definition for all type MCUs" - - DCD CSV_IRQHandler - DCD SWDT_IRQHandler - DCD LVD_IRQHandler - DCD IRQ003SEL_IRQHandler - DCD IRQ004SEL_IRQHandler - DCD IRQ005SEL_IRQHandler - DCD IRQ006SEL_IRQHandler - DCD IRQ007SEL_IRQHandler - DCD IRQ008SEL_IRQHandler - DCD IRQ009SEL_IRQHandler - DCD IRQ010SEL_IRQHandler - DCD EXINT0_IRQHandler - DCD EXINT1_IRQHandler - DCD EXINT2_IRQHandler - DCD EXINT3_IRQHandler - DCD EXINT4_IRQHandler - DCD EXINT5_IRQHandler - DCD EXINT6_IRQHandler - DCD EXINT7_IRQHandler - DCD QPRC0_IRQHandler - DCD QPRC1_IRQHandler - DCD WFG0_DTIF0_IRQHandler - DCD WFG1_DTIF1_IRQHandler - DCD WFG2_DTIF2_IRQHandler - DCD FRT0_PEAK_IRQHandler - DCD FRT0_ZERO_IRQHandler - DCD ICU0_IRQHandler - DCD OCU0_IRQHandler - DCD FRT1_PEAK_IRQHandler - DCD FRT1_ZERO_IRQHandler - DCD ICU1_IRQHandler - DCD OCU1_IRQHandler - DCD FRT2_PEAK_IRQHandler - DCD FRT2_ZERO_IRQHandler - DCD ICU2_IRQHandler - DCD OCU2_IRQHandler - DCD PPG00_02_04_IRQHandler - DCD PPG08_10_12_IRQHandler - DCD PPG16_18_20_IRQHandler - DCD BT0_IRQHandler - DCD BT1_IRQHandler - DCD BT2_IRQHandler - DCD BT3_IRQHandler - DCD BT4_IRQHandler - DCD BT5_IRQHandler - DCD BT6_IRQHandler - DCD BT7_IRQHandler - DCD DT1_2_IRAHandler - DCD WC_IRQHandler - DCD EXTBUS_ERR_Handler - DCD RTC_IRQHandler - DCD EXTINT8_IRQHandler - DCD EXTINT9_IRQHandler - DCD EXTINT10_IRQHandler - DCD EXTINT11_IRQHandler - DCD EXTINT12_IRQHandler - DCD EXTINT13_IRQHandler - DCD EXTINT14_IRQHandler - DCD EXTINT15_IRQHandler - DCD TIM_IRQHandler - DCD MFS0_RX_IRQHandler - DCD MFS0_TX_IRQHandler - DCD MFS1_RX_IRQHandler - DCD MFS1_TX_IRQHandler - DCD MFS2_RX_IRQHandler - DCD MFS2_TX_IRQHandler - DCD MFS3_RX_IRQHandler - DCD MFS3_TX_IRQHandler - DCD MFS4_RX_IRQHandler - DCD MFS4_TX_IRQHandler - DCD MFS5_RX_IRQHandler - DCD MFS5_TX_IRQHandler - DCD MFS6_RX_IRQHandler - DCD MFS6_TX_IRQHandler - DCD MFS7_RX_IRQHandler - DCD MFS7_TX_IRQHandler - DCD ADC0_IRQHandler - DCD ADC1_IRQHandler - DCD USB0_IRQHandler - DCD USB0_HOST_IRQHandler - DCD CAN0_IRQHandler - DCD CAN1_IRQHandler - DCD ETHER0_IRQHandler - DCD DMAC0_IRQHandler - DCD DMAC1_IRQHandler - DCD DMAC2_IRQHandler - DCD DMAC3_IRQHandler - DCD DMAC4_IRQHandler - DCD DMAC5_IRQHandler - DCD DMAC6_IRQHandler - DCD DMAC7_IRQHandler - DCD DSTC_IRQHandler - DCD EXINT16_17_18_19_IRQHandler - DCD EXINT20_21_22_23_IRQHandler - DCD EXINT24_25_26_27_IRQHandler - DCD EXINT28_29_30_31_IRQHandler - DCD QPRC2_IRQHandler - DCD QPRC3_IRQHandler - DCD BT8_IRQHandler - DCD BT9_IRQHandler - DCD BT10_IRQHandler - DCD BT11_IRQHandler - DCD BT12_15_IRQHandler - DCD MFS8_RX_IRQHandler - DCD MFS8_TX_IRQHandler - DCD MFS9_RX_IRQHandler - DCD MFS9_TX_IRQHandler - DCD MFS10_RX_IRQHandler - DCD MFS10_TX_IRQHandler - DCD MFS11_RX_IRQHandler - DCD MFS11_TX_IRQHandler - DCD ADC2_IRQHandler - DCD Dummy - DCD USB1_IRQHandler - DCD USB1_HOST_IRQHandler - DCD Dummy - DCD Dummy - DCD Dummy - DCD SD_IRQHandler - DCD FLASHIF_IRQHandler - DCD MFS12_RX_IRQHandler - DCD MFS12_TX_IRQHandler - DCD MFS13_RX_IRQHandler - DCD MFS13_TX_IRQHandler - DCD MFS14_RX_IRQHandler - DCD MFS14_TX_IRQHandler - DCD MFS15_RX_IRQHandler - DCD MFS15_TX_IRQHandler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR.W R0, =0xE000ED88 ; CPACR is located at address 0xE000ED88 - LDR R1, [R0] ; Read CPACR - ORR R1, R1, #(0xF << 20) ; Set bits 20-23 to enable CP10 and CP11 coprocessors - STR R1, [R0] ; Write back the modified value to the CPACR - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT CSV_IRQHandler [WEAK] - EXPORT SWDT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT IRQ003SEL_IRQHandler [WEAK] - EXPORT IRQ004SEL_IRQHandler [WEAK] - EXPORT IRQ005SEL_IRQHandler [WEAK] - EXPORT IRQ006SEL_IRQHandler [WEAK] - EXPORT IRQ007SEL_IRQHandler [WEAK] - EXPORT IRQ008SEL_IRQHandler [WEAK] - EXPORT IRQ009SEL_IRQHandler [WEAK] - EXPORT IRQ010SEL_IRQHandler [WEAK] - EXPORT EXINT0_IRQHandler [WEAK] - EXPORT EXINT1_IRQHandler [WEAK] - EXPORT EXINT2_IRQHandler [WEAK] - EXPORT EXINT3_IRQHandler [WEAK] - EXPORT EXINT4_IRQHandler [WEAK] - EXPORT EXINT5_IRQHandler [WEAK] - EXPORT EXINT6_IRQHandler [WEAK] - EXPORT EXINT7_IRQHandler [WEAK] - EXPORT QPRC0_IRQHandler [WEAK] - EXPORT QPRC1_IRQHandler [WEAK] - EXPORT WFG0_DTIF0_IRQHandler [WEAK] - EXPORT WFG1_DTIF1_IRQHandler [WEAK] - EXPORT WFG2_DTIF2_IRQHandler [WEAK] - EXPORT FRT0_PEAK_IRQHandler [WEAK] - EXPORT FRT0_ZERO_IRQHandler [WEAK] - EXPORT ICU0_IRQHandler [WEAK] - EXPORT OCU0_IRQHandler [WEAK] - EXPORT FRT1_PEAK_IRQHandler [WEAK] - EXPORT FRT1_ZERO_IRQHandler [WEAK] - EXPORT ICU1_IRQHandler [WEAK] - EXPORT OCU1_IRQHandler [WEAK] - EXPORT FRT2_PEAK_IRQHandler [WEAK] - EXPORT FRT2_ZERO_IRQHandler [WEAK] - EXPORT ICU2_IRQHandler [WEAK] - EXPORT OCU2_IRQHandler [WEAK] - EXPORT PPG00_02_04_IRQHandler [WEAK] - EXPORT PPG08_10_12_IRQHandler [WEAK] - EXPORT PPG16_18_20_IRQHandler [WEAK] - EXPORT BT0_IRQHandler [WEAK] - EXPORT BT1_IRQHandler [WEAK] - EXPORT BT2_IRQHandler [WEAK] - EXPORT BT3_IRQHandler [WEAK] - EXPORT BT4_IRQHandler [WEAK] - EXPORT BT5_IRQHandler [WEAK] - EXPORT BT6_IRQHandler [WEAK] - EXPORT BT7_IRQHandler [WEAK] - EXPORT DT1_2_IRAHandler [WEAK] - EXPORT WC_IRQHandler [WEAK] - EXPORT EXTBUS_ERR_Handler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EXTINT8_IRQHandler [WEAK] - EXPORT EXTINT9_IRQHandler [WEAK] - EXPORT EXTINT10_IRQHandler [WEAK] - EXPORT EXTINT11_IRQHandler [WEAK] - EXPORT EXTINT12_IRQHandler [WEAK] - EXPORT EXTINT13_IRQHandler [WEAK] - EXPORT EXTINT14_IRQHandler [WEAK] - EXPORT EXTINT15_IRQHandler [WEAK] - EXPORT TIM_IRQHandler [WEAK] - EXPORT MFS0_RX_IRQHandler [WEAK] - EXPORT MFS0_TX_IRQHandler [WEAK] - EXPORT MFS1_RX_IRQHandler [WEAK] - EXPORT MFS1_TX_IRQHandler [WEAK] - EXPORT MFS2_RX_IRQHandler [WEAK] - EXPORT MFS2_TX_IRQHandler [WEAK] - EXPORT MFS3_RX_IRQHandler [WEAK] - EXPORT MFS3_TX_IRQHandler [WEAK] - EXPORT MFS4_RX_IRQHandler [WEAK] - EXPORT MFS4_TX_IRQHandler [WEAK] - EXPORT MFS5_RX_IRQHandler [WEAK] - EXPORT MFS5_TX_IRQHandler [WEAK] - EXPORT MFS6_RX_IRQHandler [WEAK] - EXPORT MFS6_TX_IRQHandler [WEAK] - EXPORT MFS7_RX_IRQHandler [WEAK] - EXPORT MFS7_TX_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB0_HOST_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT ETHER0_IRQHandler [WEAK] - EXPORT DMAC0_IRQHandler [WEAK] - EXPORT DMAC1_IRQHandler [WEAK] - EXPORT DMAC2_IRQHandler [WEAK] - EXPORT DMAC3_IRQHandler [WEAK] - EXPORT DMAC4_IRQHandler [WEAK] - EXPORT DMAC5_IRQHandler [WEAK] - EXPORT DMAC6_IRQHandler [WEAK] - EXPORT DMAC7_IRQHandler [WEAK] - EXPORT DSTC_IRQHandler [WEAK] - EXPORT EXINT16_17_18_19_IRQHandler [WEAK] - EXPORT EXINT20_21_22_23_IRQHandler [WEAK] - EXPORT EXINT24_25_26_27_IRQHandler [WEAK] - EXPORT EXINT28_29_30_31_IRQHandler [WEAK] - EXPORT QPRC2_IRQHandler [WEAK] - EXPORT QPRC3_IRQHandler [WEAK] - EXPORT BT8_IRQHandler [WEAK] - EXPORT BT9_IRQHandler [WEAK] - EXPORT BT10_IRQHandler [WEAK] - EXPORT BT11_IRQHandler [WEAK] - EXPORT BT12_15_IRQHandler [WEAK] - EXPORT MFS8_RX_IRQHandler [WEAK] - EXPORT MFS8_TX_IRQHandler [WEAK] - EXPORT MFS9_RX_IRQHandler [WEAK] - EXPORT MFS9_TX_IRQHandler [WEAK] - EXPORT MFS10_RX_IRQHandler [WEAK] - EXPORT MFS10_TX_IRQHandler [WEAK] - EXPORT MFS11_RX_IRQHandler [WEAK] - EXPORT MFS11_TX_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT USB1_HOST_IRQHandler [WEAK] - EXPORT SD_IRQHandler [WEAK] - EXPORT FLASHIF_IRQHandler [WEAK] - EXPORT MFS12_RX_IRQHandler [WEAK] - EXPORT MFS12_TX_IRQHandler [WEAK] - EXPORT MFS13_RX_IRQHandler [WEAK] - EXPORT MFS13_TX_IRQHandler [WEAK] - EXPORT MFS14_RX_IRQHandler [WEAK] - EXPORT MFS14_TX_IRQHandler [WEAK] - EXPORT MFS15_RX_IRQHandler [WEAK] - EXPORT MFS15_TX_IRQHandler [WEAK] - EXPORT Dummy [WEAK] - - - -CSV_IRQHandler -SWDT_IRQHandler -LVD_IRQHandler -IRQ003SEL_IRQHandler -IRQ004SEL_IRQHandler -IRQ005SEL_IRQHandler -IRQ006SEL_IRQHandler -IRQ007SEL_IRQHandler -IRQ008SEL_IRQHandler -IRQ009SEL_IRQHandler -IRQ010SEL_IRQHandler -EXINT0_IRQHandler -EXINT1_IRQHandler -EXINT2_IRQHandler -EXINT3_IRQHandler -EXINT4_IRQHandler -EXINT5_IRQHandler -EXINT6_IRQHandler -EXINT7_IRQHandler -QPRC0_IRQHandler -QPRC1_IRQHandler -WFG0_DTIF0_IRQHandler -WFG1_DTIF1_IRQHandler -WFG2_DTIF2_IRQHandler -FRT0_PEAK_IRQHandler -FRT0_ZERO_IRQHandler -ICU0_IRQHandler -OCU0_IRQHandler -FRT1_PEAK_IRQHandler -FRT1_ZERO_IRQHandler -ICU1_IRQHandler -OCU1_IRQHandler -FRT2_PEAK_IRQHandler -FRT2_ZERO_IRQHandler -ICU2_IRQHandler -OCU2_IRQHandler -PPG00_02_04_IRQHandler -PPG08_10_12_IRQHandler -PPG16_18_20_IRQHandler -BT0_IRQHandler -BT1_IRQHandler -BT2_IRQHandler -BT3_IRQHandler -BT4_IRQHandler -BT5_IRQHandler -BT6_IRQHandler -BT7_IRQHandler -DT1_2_IRAHandler -WC_IRQHandler -EXTBUS_ERR_Handler -RTC_IRQHandler -EXTINT8_IRQHandler -EXTINT9_IRQHandler -EXTINT10_IRQHandler -EXTINT11_IRQHandler -EXTINT12_IRQHandler -EXTINT13_IRQHandler -EXTINT14_IRQHandler -EXTINT15_IRQHandler -TIM_IRQHandler -MFS0_RX_IRQHandler -MFS0_TX_IRQHandler -MFS1_RX_IRQHandler -MFS1_TX_IRQHandler -MFS2_RX_IRQHandler -MFS2_TX_IRQHandler -MFS3_RX_IRQHandler -MFS3_TX_IRQHandler -MFS4_RX_IRQHandler -MFS4_TX_IRQHandler -MFS5_RX_IRQHandler -MFS5_TX_IRQHandler -MFS6_RX_IRQHandler -MFS6_TX_IRQHandler -MFS7_RX_IRQHandler -MFS7_TX_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -USB0_IRQHandler -USB0_HOST_IRQHandler -CAN0_IRQHandler -CAN1_IRQHandler -ETHER0_IRQHandler -DMAC0_IRQHandler -DMAC1_IRQHandler -DMAC2_IRQHandler -DMAC3_IRQHandler -DMAC4_IRQHandler -DMAC5_IRQHandler -DMAC6_IRQHandler -DMAC7_IRQHandler -DSTC_IRQHandler -EXINT16_17_18_19_IRQHandler -EXINT20_21_22_23_IRQHandler -EXINT24_25_26_27_IRQHandler -EXINT28_29_30_31_IRQHandler -QPRC2_IRQHandler -QPRC3_IRQHandler -BT8_IRQHandler -BT9_IRQHandler -BT10_IRQHandler -BT11_IRQHandler -BT12_15_IRQHandler -MFS8_RX_IRQHandler -MFS8_TX_IRQHandler -MFS9_RX_IRQHandler -MFS9_TX_IRQHandler -MFS10_RX_IRQHandler -MFS10_TX_IRQHandler -MFS11_RX_IRQHandler -MFS11_TX_IRQHandler -ADC2_IRQHandler -USB1_IRQHandler -USB1_HOST_IRQHandler -SD_IRQHandler -FLASHIF_IRQHandler -MFS12_RX_IRQHandler -MFS12_TX_IRQHandler -MFS13_RX_IRQHandler -MFS13_TX_IRQHandler -MFS14_RX_IRQHandler -MFS14_TX_IRQHandler -MFS15_RX_IRQHandler -MFS15_TX_IRQHandler -Dummy - - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/base_types.h b/bsp/mb9bf568r/CMSIS/DeviceSupport/base_types.h deleted file mode 100644 index 7b2fa72b5c..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/base_types.h +++ /dev/null @@ -1,160 +0,0 @@ -/******************************************************************************* -* Copyright (C) 2013 Spansion LLC. All Rights Reserved. -* -* This software is owned and published by: -* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). -* -* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND -* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. -* -* This software contains source code for use with Spansion -* components. This software is licensed by Spansion to be adapted only -* for use in systems utilizing Spansion components. Spansion shall not be -* responsible for misuse or illegal use of this software for devices not -* supported herein. Spansion is providing this software "AS IS" and will -* not be responsible for issues arising from incorrect user implementation -* of the software. -* -* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, -* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), -* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, -* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED -* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED -* WARRANTY OF NONINFRINGEMENT. -* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, -* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT -* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, -* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR -* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, -* SAVINGS OR PROFITS, -* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR -* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED -* FROM, THE SOFTWARE. -* -* This software may be replicated in part or whole for the licensed use, -* with the restriction that this Disclaimer and Copyright notice must be -* included with each copy of this software, whether used in part or whole, -* at all times. -*/ - -/*****************************************************************************/ -/** \file base_types.h - ** - ** Additional base type definitions to stddef.h and stdint.h - ** - ** History: - ** - 2013-03-21 1.0 MWi First version. - ** - *****************************************************************************/ - -#ifndef __BASE_TYPES_H__ -#define __BASE_TYPES_H__ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include "stdint.h" - -/*****************************************************************************/ -/* Global pre-processor symbols/macros ('#define') */ -/*****************************************************************************/ -#ifndef TRUE - /** Value is true (boolean_t type) */ - #define TRUE ((boolean_t) 1) -#endif - -#ifndef FALSE - /** Value is false (boolean_t type) */ - #define FALSE ((boolean_t) 0) -#endif - -/** Returns the minimum value out of two values */ -#define MIN( X, Y ) ((X) < (Y) ? (X) : (Y)) - -/** Returns the maximum value out of two values */ -#define MAX( X, Y ) ((X) > (Y) ? (X) : (Y)) - -/** Returns the dimension of an array */ -#define DIM( X ) (sizeof(X) / sizeof(X[0])) - -/****************************************************************************** - * Global type definitions - ******************************************************************************/ - -/** logical datatype (only values are TRUE and FALSE) */ -typedef uint8_t boolean_t; - -/** single precision floating point number (4 byte) */ -typedef float float32_t; - -/** double precision floating point number (8 byte) */ -typedef double float64_t; - -/** ASCCI character for string generation (8 bit) */ -typedef char char_t; - -/** function pointer type to void/void function */ -typedef void (*func_ptr_t)(void); - -/** function pointer type to void/uint8_t function */ -typedef void (*func_ptr_arg1_t)(uint8_t); - -/** generic error codes */ -typedef enum en_result -{ - Ok = 0, ///< No error - Error = 1, ///< Non-specific error code - ErrorAddressAlignment = 2, ///< Address alignment does not match - ErrorAccessRights = 3, ///< Wrong mode (e.g. user/system) mode is set - ErrorInvalidParameter = 4, ///< Provided parameter is not valid - ErrorOperationInProgress = 5, ///< A conflicting or requested operation is still in progress - ErrorInvalidMode = 6, ///< Operation not allowed in current mode - ErrorUninitialized = 7, ///< Module (or part of it) was not initialized properly - ErrorBufferFull = 8, ///< Circular buffer can not be written because the buffer is full - ErrorTimeout = 9, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) - ErrorNotReady = 10, ///< A requested final state is not reached - OperationInProgress = 11 ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) -} en_result_t; - -/** - ****************************************************************************** - ** \brief Level - ** - ** Specifies levels. - ** - ******************************************************************************/ -typedef enum en_level -{ - PDLLow = 0, ///< Low level '0' - PDLHigh = 1 ///< High level '1' -} en_level_t; - -/** - ****************************************************************************** - ** \brief Generic Flag Code - ** - ** Specifies flags. - ** - ******************************************************************************/ -typedef enum en_flag -{ - PdlClr = 0, ///< Flag clr '0' - PdlSet = 1 ///< Flag set '1' -} en_stat_flag_t, en_int_flag_t; - -/*****************************************************************************/ -/* Global variable declarations ('extern', definition in C source) */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/*****************************************************************************/ - -#endif /* __BASE_TYPES_H__ */ - -/******************************************************************************/ -/* EOF (not truncated) */ -/******************************************************************************/ diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S b/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S deleted file mode 100644 index 72981f1edb..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S +++ /dev/null @@ -1,290 +0,0 @@ -/**************************************************************************//** - * @file startup_.s - * @brief CMSIS Cortex-M# Core Device Startup File for - * Device - * @version V3.01 - * @date 06. March 2012 - * - * @note Version CodeSourcery Sourcery G++ Lite (with CS3) - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - -/* -// Stack Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Stack_Size, 0x00000400 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - -/* -// Heap Configuration -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -// -*/ - - .equ Heap_Size, 0x00000100 - - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - -/* Vector Table */ - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack /* Top of Stack */ - .long __cs3_reset /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ -/* ToDo: Add here the vectors for the device specific external interrupts handler */ - .long CSV_Handler /* 0: Clock Super Visor */ - .long SWDT_Handler /* 1: Software Watchdog Timer */ - .long LVD_Handler /* 2: Low Voltage Detector */ - .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ - .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ - .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ - .long DT_Handler /* 6: Dual Timer / Quad Decoder */ - .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ - .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ - .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ - .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ - .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ - .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ - .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ - .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ - .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ - .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ - .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ - .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ - .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ - .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ - .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ - .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ - .long PPG_Handler /* 23: PPG */ - .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ - .long ADC0_IRQHandler /* 25: ADC0 */ - .long ADC1_IRQHandler /* 26: ADC1 */ - .long ADC2_IRQHandler /* 27: ADC2 */ - .long MFT_FRT_IRQHandler /* 28: Free-run Timer */ - .long MFT_IPC_IRQHandler /* 29: Input Capture */ - .long MFT_OPC_IRQHandler /* 30: Output Compare */ - .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ - .long CAN0_IRQHandler /* 32: CAN ch.0 */ - .long CAN1_IRQHandler /* 33: CAN ch.1 */ - .long USBF_Handler /* 34: USB Function */ - .long USB_Handler /* 35: USB Function / USB HOST */ - .long RESERVED_1_IRQHandler /* 36: Reserved */ - .long RESERVED_2_IRQHandler /* 37: Reserved */ - .long DMAC0_Handler /* 38: DMAC ch.0 */ - .long DMAC1_Handler /* 39: DMAC ch.1 */ - .long DMAC2_Handler /* 40: DMAC ch.2 */ - .long DMAC3_Handler /* 41: DMAC ch.3 */ - .long DMAC4_Handler /* 42: DMAC ch.4 */ - .long DMAC5_Handler /* 43: DMAC ch.5 */ - .long DMAC6_Handler /* 44: DMAC ch.6 */ - .long DMAC7_Handler /* 45: DMAC ch.7 */ - .long RESERVED_3_IRQHandler /* 46: Reserved */ - .long RESERVED_4_IRQHandler /* 47: Reserved */ - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - - .thumb - - -/* Reset Handler */ - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .globl _start - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: -_start: - .fnstart - LDR R0, =SystemInit - BLX R0 - LDR R0,=_start - BX R0 - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - -/* Exception Handlers */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - B . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - B . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - B . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - B . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - -/* ToDo: Add here the export definition for the device specific external interrupts handler */ -/* ToDo: Add here the names for the device specific external interrupts handler */ - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ CSV_Handler /* 0: Clock Super Visor */ - IRQ SWDT_Handler /* 1: Software Watchdog Timer */ - IRQ LVD_Handler /* 2: Low Voltage Detector */ - IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ - IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ - IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ - IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */ - IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ - IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ - IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ - IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ - IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ - IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ - IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ - IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ - IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ - IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ - IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ - IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ - IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ - IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ - IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ - IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ - IRQ PPG_Handler /* 23: PPG */ - IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ - IRQ ADC0_IRQHandler /* 25: ADC0 */ - IRQ ADC1_IRQHandler /* 26: ADC1 */ - IRQ ADC2_IRQHandler /* 27: ADC2 */ - IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */ - IRQ MFT_IPC_IRQHandler /* 29: Input Capture */ - IRQ MFT_OPC_IRQHandler /* 30: Output Compare */ - IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ - IRQ CAN0_IRQHandler /* 32: CAN ch.0 */ - IRQ CAN1_IRQHandler /* 33: CAN ch.1 */ - IRQ USBF_Handler /* 34: USB Function */ - IRQ USB_Handler /* 35: USB Function / USB HOST */ - IRQ RESERVED_1_IRQHandler /* 36: Reserved */ - IRQ RESERVED_2_IRQHandler /* 37: Reserved */ - IRQ DMAC0_Handler /* 38: DMAC ch.0 */ - IRQ DMAC1_Handler /* 39: DMAC ch.1 */ - IRQ DMAC2_Handler /* 40: DMAC ch.2 */ - IRQ DMAC3_Handler /* 41: DMAC ch.3 */ - IRQ DMAC4_Handler /* 42: DMAC ch.4 */ - IRQ DMAC5_Handler /* 43: DMAC ch.5 */ - IRQ DMAC6_Handler /* 44: DMAC ch.6 */ - IRQ DMAC7_Handler /* 45: DMAC ch.7 */ - IRQ RESERVED_3_IRQHandler /* 46: Reserved */ - IRQ RESERVED_4_IRQHandler /* 47: Reserved */ - - .end diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h b/bsp/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h deleted file mode 100644 index 317f63644c..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/mb9b560r.h +++ /dev/null @@ -1,28433 +0,0 @@ -/******************************************************************************* -* Copyright (C) 2013 Spansion LLC. All Rights Reserved. -* -* This software is owned and published by: -* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). -* -* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND -* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. -* -* This software contains source code for use with Spansion -* components. This software is licensed by Spansion to be adapted only -* for use in systems utilizing Spansion components. Spansion shall not be -* responsible for misuse or illegal use of this software for devices not -* supported herein. Spansion is providing this software "AS IS" and will -* not be responsible for issues arising from incorrect user implementation -* of the software. -* -* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, -* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), -* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, -* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED -* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED -* WARRANTY OF NONINFRINGEMENT. -* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, -* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT -* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, -* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR -* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, -* SAVINGS OR PROFITS, -* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR -* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED -* FROM, THE SOFTWARE. -* -* This software may be replicated in part or whole for the licensed use, -* with the restriction that this Disclaimer and Copyright notice must be -* included with each copy of this software, whether used in part or whole, -* at all times. -*/ -/******************************************************************************/ -/** \file mb9b560r.h - ** - ** Unfified Header File for FM4 PDL - ** - ** History: - ** - 2013-01-21 0.0.1 MWi First version - ** - 2013-02-06 0.0.2 MWi All FM3_ prexifes changed to FM4_; New defines - ** for MFS8-15 added; FM4_MFS_NFC_BASE added - ** - 2013-06-28 0.0.3 EH Modified bitband address of RTC - ** - 2013-08-08 0.0.4 EH Modified UESMCE bit of EPFR20 register to UESMCEE - ** Modified DESP bit of MONERS register to EDESP in DSTC - ** Modified DQID bit of MONERS register to ECH in DSTC - ** Modified HS bit of MONERS register to EHS in DSTC - ** Modified DREQEMSK register to DQMSK in DSTC - ** Added DQMSKCLK register in DSTC - ** Added AN16-AN31 bits to ADE register in GPIO - ** Modified FERRAD bit of FERRAD register to ERRAD - ** Modified DAC register composition - ** - 2013-08-21 0.0.5 EH Added IRQSEL_MODULE definition - ** - 2013-09-10 0.0.6 EH Modified structure of FM4_EXBUS_TypeDef - ** - ******************************************************************************/ - -#ifndef _MB9B560R_H_ -#define _MB9B560R_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present */ - -#include "mcu.h" - -/** - ****************************************************************************** - ** \brief Interrupt number definition for all type MCUs - ******************************************************************************/ -#if (PDL_MCU_INT_TYPE == PDL_INT_TYPE_A) -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Supervisor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detection */ - IRQ003SEL_IRQn = 3, /* Interrupt Selection IRQ003SEL */ - IRQ004SEL_IRQn = 4, /* Interrupt Selection IRQ004SEL */ - IRQ005SEL_IRQn = 5, /* Interrupt Selection IRQ005SEL */ - IRQ006SEL_IRQn = 6, /* Interrupt Selection IRQ006SEL */ - IRQ007SEL_IRQn = 7, /* Interrupt Selection IRQ007SEL */ - IRQ008SEL_IRQn = 8, /* Interrupt Selection IRQ008SEL */ - IRQ009SEL_IRQn = 9, /* Interrupt Selection IRQ009SEL */ - IRQ010SEL_IRQn = 10, /* Interrupt Selection IRQ010SEL */ - EXINT0_IRQn = 11, /* External Interrupt Ch. 0 */ - EXINT1_IRQn = 12, /* External Interrupt Ch. 1 */ - EXINT2_IRQn = 13, /* External Interrupt Ch. 2 */ - EXINT3_IRQn = 14, /* External Interrupt Ch. 3 */ - EXINT4_IRQn = 15, /* External Interrupt Ch. 4 */ - EXINT5_IRQn = 16, /* External Interrupt Ch. 5 */ - EXINT6_IRQn = 17, /* External Interrupt Ch. 6 */ - EXINT7_IRQn = 18, /* External Interrupt Ch. 7 */ - QPRC0_IRQn = 19, /* Quad Decoder and Revolution Counter Ch. 0 */ - QPRC1_IRQn = 20, /* Quad Decoder and Revolution Counter Ch. 1 */ - WFG0_DTIF0_IRQn = 21, /* MFT0 Wave Form Generator / DTIF */ - WFG1_DTIF1_IRQn = 22, /* MFT1 Wave Form Generator / DTIF */ - WFG2_DTIF2_IRQn = 23, /* MFT2 Wave Form Generator / DTIF */ - FRT0_PEAK_IRQn = 24, /* MFT0 Free Running Timer Peak Detection */ - FRT0_ZERO_IRQn = 25, /* MFT0 Free Running Timer Zero Detection */ - ICU0_IRQn = 26, /* MFT0 Input Capture Unit */ - OCU0_IRQn = 27, /* MFT0 Output Compare Unit */ - FRT1_PEAK_IRQn = 28, /* MFT1 Free Running Timer Peak Detection */ - FRT1_ZERO_IRQn = 29, /* MFT1 Free Running Timer Zero Detection */ - ICU1_IRQn = 30, /* MFT1 Input Capture Unit */ - OCU1_IRQn = 31, /* MFT1 Output Compare Unit */ - FRT2_PEAK_IRQn = 32, /* MFT2 Free Running Timer Peak Detection */ - FRT2_ZERO_IRQn = 33, /* MFT2 Free Running Timer Zero Detection */ - ICU2_IRQn = 34, /* MFT2 Input Capture Unit */ - OCU2_IRQn = 35, /* MFT2 Output Compare Unit */ - PPG00_02_04_IRQn = 36, /* Programmable Pulse Generator Ch. 0, 2, 4 */ - PPG08_10_12_IRQn = 37, /* Programmable Pulse Generator Ch. 8, 10, 12 */ - PPG16_18_20_IRQn = 38, /* Programmable Pulse Generator Ch. 16, 18, 20 */ - BT0_IRQn = 39, /* Base Timer Ch. 0 */ - BT1_IRQn = 40, /* Base Timer Ch. 1 */ - BT2_IRQn = 41, /* Base Timer Ch. 2 */ - BT3_IRQn = 42, /* Base Timer Ch. 3 */ - BT4_IRQn = 43, /* Base Timer Ch. 4 */ - BT5_IRQn = 44, /* Base Timer Ch. 5 */ - BT6_IRQn = 45, /* Base Timer Ch. 6 */ - BT7_IRQn = 46, /* Base Timer Ch. 7 */ - DT1_2_IRQn = 47, /* Dual Timmer Ch. 1, 2 */ - WC_IRQn = 48, /* Watch Counter */ - EXTBUS_ERR_IRQn = 49, /* External Bus Error */ - RTC_IRQn = 50, /* Realtime Clock */ - EXINT8_IRQn = 51, /* External Interrupt Ch. 8 */ - EXINT9_IRQn = 52, /* External Interrupt Ch. 9 */ - EXINT10_IRQn = 53, /* External Interrupt Ch. 10 */ - EXINT11_IRQn = 54, /* External Interrupt Ch. 11 */ - EXINT12_IRQn = 55, /* External Interrupt Ch. 12 */ - EXINT13_IRQn = 56, /* External Interrupt Ch. 13 */ - EXINT14_IRQn = 57, /* External Interrupt Ch. 14 */ - EXINT15_IRQn = 58, /* External Interrupt Ch. 15 */ - TIM_IRQn = 59, /* Clock/PLL Timer */ - MFS0_RX_IRQn = 60, /* Multifunction Serial I/F Reception Ch. 0 */ - MFS0_TX_IRQn = 61, /* Multifunction Serial I/F Transmission Ch. 0 */ - MFS1_RX_IRQn = 62, /* Multifunction Serial I/F Reception Ch. 1 */ - MFS1_TX_IRQn = 63, /* Multifunction Serial I/F Transmission Ch. 1 */ - MFS2_RX_IRQn = 64, /* Multifunction Serial I/F Reception Ch. 2 */ - MFS2_TX_IRQn = 65, /* Multifunction Serial I/F Transmission Ch. 2 */ - MFS3_RX_IRQn = 66, /* Multifunction Serial I/F Reception Ch. 3 */ - MFS3_TX_IRQn = 67, /* Multifunction Serial I/F Transmission Ch. 3 */ - MFS4_RX_IRQn = 68, /* Multifunction Serial I/F Reception Ch. 4 */ - MFS4_TX_IRQn = 69, /* Multifunction Serial I/F Transmission Ch. 4 */ - MFS5_RX_IRQn = 70, /* Multifunction Serial I/F Reception Ch. 5 */ - MFS5_TX_IRQn = 71, /* Multifunction Serial I/F Transmission Ch. 5 */ - MFS6_RX_IRQn = 72, /* Multifunction Serial I/F Reception Ch. 6 */ - MFS6_TX_IRQn = 73, /* Multifunction Serial I/F Transmission Ch. 6 */ - MFS7_RX_IRQn = 74, /* Multifunction Serial I/F Reception Ch. 7 */ - MFS7_TX_IRQn = 75, /* Multifunction Serial I/F Transmission Ch. 7 */ - ADC0_IRQn = 76, /* Analog Digital Converter Unit 0 */ - ADC1_IRQn = 77, /* Analog Digital Converter Unit 1 */ - USB0_IRQn = 78, /* USB0 Function */ - USB0_HOST_IRQn = 79, /* USB0 Function and Host */ - CAN0_IRQn = 80, /* CAN I/F Ch. 0 */ - CAN1_IRQn = 81, /* CAN I/F Ch. 1 */ - ETHER0_IRQn = 82, /* Ethernet */ - DMAC0_IRQn = 83, /* Direct Memory Access Controller Ch. 0 */ - DMAC1_IRQn = 84, /* Direct Memory Access Controller Ch. 1 */ - DMAC2_IRQn = 85, /* Direct Memory Access Controller Ch. 2 */ - DMAC3_IRQn = 86, /* Direct Memory Access Controller Ch. 3 */ - DMAC4_IRQn = 87, /* Direct Memory Access Controller Ch. 4 */ - DMAC5_IRQn = 88, /* Direct Memory Access Controller Ch. 5 */ - DMAC6_IRQn = 89, /* Direct Memory Access Controller Ch. 6 */ - DMAC7_IRQn = 90, /* Direct Memory Access Controller Ch. 7 */ - DSTC_IRQn = 91, /* DSTC SW Transfer */ - EXINT16_17_18_19_IRQn = 92, /* External Interrupt Ch. 16 - 19 */ - EXINT20_21_22_23_IRQn = 93, /* External Interrupt Ch. 20 - 23 */ - EXINT24_25_26_27_IRQn = 94, /* External Interrupt Ch. 24 - 27 */ - EXINT28_29_30_31_IRQn = 95, /* External Interrupt Ch. 28 - 31 */ - QPRC2_IRQn = 96, /* Quad Decoder and Revolution Counter Ch. 2 */ - QPRC3_IRQn = 97, /* Quad Decoder and Revolution Counter Ch. 3 */ - BT8_IRQn = 98, /* Base Timer Ch. 8 */ - BT9_IRQn = 99, /* Base Timer Ch. 9 */ - BT10_IRQn = 100, /* Base Timer Ch. 10 */ - BT11_IRQn = 101, /* Base Timer Ch. 11 */ - BT12_IRQn = 102, /* Base Timer Ch. 12 */ - MFS8_RX_IRQn = 103, /* Multifunction Serial I/F Reception Ch. 8 */ - MFS8_TX_IRQn = 104, /* Multifunction Serial I/F Transmission Ch. 8 */ - MFS9_RX_IRQn = 105, /* Multifunction Serial I/F Reception Ch. 9 */ - MFS9_TX_IRQn = 106, /* Multifunction Serial I/F Transmission Ch. 9 */ - MFS10_RX_IRQn = 107, /* Multifunction Serial I/F Reception Ch. 10 */ - MFS10_TX_IRQn = 108, /* Multifunction Serial I/F Transmission Ch. 10 */ - MFS11_RX_IRQn = 109, /* Multifunction Serial I/F Reception Ch. 11 */ - MFS11_TX_IRQn = 110, /* Multifunction Serial I/F Transmission Ch. 11 */ - ADC2_IRQn = 111, /* Analog Digital Converter Unit 2 */ - USB1_IRQn = 113, /* USB1 Function */ - USB1_HOST_IRQn = 114, /* USB1 Function and Host */ - SD_IRQn = 118, /* SD Card I/F */ - FLASH_IRQn = 119 /* Flash */ -} IRQn_Type; - -#elif (PDL_MCU_INT_TYPE == PDL_INT_TYPE_C) -typedef enum IRQn -{ - NMI_IRQn = -14, /* A<- */ - HardFault_IRQn = -13, /* A<- */ - MemManage_IRQn = -12, /* A<- */ - BusFault_IRQn = -11, /* A<- */ - UsageFault_IRQn = -10, /* A<- */ - SVC_IRQn = -5, /* A<- */ - DebugMonitor_IRQn = -4, /* A<- */ - PendSV_IRQn = -2, /* A<- */ - SysTick_IRQn = -1, /* A<- */ - - CSV_IRQn = 0, /* A<- */ - SWDT_IRQn = 1, /* A<- */ - LVD_IRQn = 2, /* A<- */ - WFG_IRQn = 3, /* A<- */ - EXINT0_7_IRQn = 4, /* A<- */ - EXINT8_31_IRQn = 5, /* A<- */ - MFS0_8_RX_IRQn = 6, /* A<- */ - MFS0_8_TX_IRQn = 7, /* A<- */ - MFS1_9_RX_IRQn = 8, /* A<- */ - MFS1_9_TX_IRQn = 9, /* A<- */ - MFS2_10_RX_IRQn = 10,/* A<- */ - MFS2_10_TX_IRQn = 11,/* A<- */ - MFS3_11_RX_IRQn = 12, /* A<- */ - MFS3_11_TX_IRQn = 13, /* A<- */ - MFS4_12_RX_IRQn = 14, /* A<- */ - MFS4_12_TX_IRQn = 15, /* A<- */ - MFS5_13_RX_IRQn = 16, /* A<- */ - MFS5_13_TX_IRQn = 17, /* A<- */ - MFS6_14_RX_IRQn = 18, /* A<- */ - MFS6_14_TX_IRQn = 19, /* A<- */ - MFS7_15_RX_IRQn = 20, /* A<- */ - MFS7_15_TX_IRQn = 21, /* A<- */ - PPG_IRQn = 22, /* A<- */ - OSC_PLL_WC_RTC_IRQn = 23, /* A<- */ - ADC0_IRQn = 24, /* A<- */ - FRTIM_IRQn = 25, /* A<- */ - INCAP_IRQn = 26, /* A<- */ - OUTCOMP_IRQn = 27, /* A<- */ - BTIM0_7_IRQn = 28, /* A<- */ - ADC2_LCD_IRQn = 29, /* A<- */ - USB1F_HDMICEC0_IRQn = 30, /* A<- */ - USB1F_USB1H_HDMICEC1_IRQn = 31, /* A<- */ -} IRQn_Type; -#else - #error Interrupt Type not found! -#endif // PDL_INT_TYPE - -#include "core_cm4.h" -#include "system_mb9bf56xr.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * INTREQ_MODULE Bit fields and registers depending on device type - ******************************************************************************/ -#if (PDL_MCU_INT_TYPE == PDL_INT_TYPE_A) - -/* Interrupt request read registers */ -typedef struct -{ - __IO uint32_t DRQSEL; - uint8_t RESERVED0[12]; - __IO uint32_t EXC02MON; - __IO uint32_t IRQ00MON; - __IO uint32_t IRQ01MON; - __IO uint32_t IRQ02MON; - __IO uint32_t IRQ03MON; - __IO uint32_t IRQ04MON; - __IO uint32_t IRQ05MON; - __IO uint32_t IRQ06MON; - __IO uint32_t IRQ07MON; - __IO uint32_t IRQ08MON; - __IO uint32_t IRQ09MON; - __IO uint32_t IRQ10MON; - __IO uint32_t IRQ11MON; - __IO uint32_t IRQ12MON; - __IO uint32_t IRQ13MON; - __IO uint32_t IRQ14MON; - __IO uint32_t IRQ15MON; - __IO uint32_t IRQ16MON; - __IO uint32_t IRQ17MON; - __IO uint32_t IRQ18MON; - __IO uint32_t IRQ19MON; - __IO uint32_t IRQ20MON; - __IO uint32_t IRQ21MON; - __IO uint32_t IRQ22MON; - __IO uint32_t IRQ23MON; - __IO uint32_t IRQ24MON; - __IO uint32_t IRQ25MON; - __IO uint32_t IRQ26MON; - __IO uint32_t IRQ27MON; - __IO uint32_t IRQ28MON; - __IO uint32_t IRQ29MON; - __IO uint32_t IRQ30MON; - __IO uint32_t IRQ31MON; - __IO uint32_t IRQ32MON; - __IO uint32_t IRQ33MON; - __IO uint32_t IRQ34MON; - __IO uint32_t IRQ35MON; - __IO uint32_t IRQ36MON; - __IO uint32_t IRQ37MON; - __IO uint32_t IRQ38MON; - __IO uint32_t IRQ39MON; - __IO uint32_t IRQ40MON; - __IO uint32_t IRQ41MON; - __IO uint32_t IRQ42MON; - __IO uint32_t IRQ43MON; - __IO uint32_t IRQ44MON; - __IO uint32_t IRQ45MON; - __IO uint32_t IRQ46MON; - __IO uint32_t IRQ47MON; -}PDL_INTREQ_TypeDef; - -#define PDL_INTREQ_BASE (PDL_PERIPH_BASE + 0x31000UL) // Interrupt request read registers -#define PDL_INTREQ ((PDL_INTREQ_TypeDef *)PDL_INTREQ_BASE) - -#elif (PDL_MCU_INT_TYPE == PDL_INT_TYPE_C) - -/* Interrupt request read registers */ -typedef struct -{ - uint8_t RESERVED0[16]; - __IO uint32_t EXC02MON; - __IO uint32_t IRQ00MON; - __IO uint32_t IRQ01MON; - __IO uint32_t IRQ02MON; - __IO uint32_t IRQ03MON; - __IO uint32_t IRQ04MON; - __IO uint32_t IRQ05MON; - __IO uint32_t IRQ06MON; - __IO uint32_t IRQ07MON; - __IO uint32_t IRQ08MON; - __IO uint32_t IRQ09MON; - __IO uint32_t IRQ10MON; - __IO uint32_t IRQ11MON; - __IO uint32_t IRQ12MON; - __IO uint32_t IRQ13MON; - __IO uint32_t IRQ14MON; - __IO uint32_t IRQ15MON; - __IO uint32_t IRQ16MON; - __IO uint32_t IRQ17MON; - __IO uint32_t IRQ18MON; - __IO uint32_t IRQ19MON; - __IO uint32_t IRQ20MON; - __IO uint32_t IRQ21MON; - __IO uint32_t IRQ22MON; - __IO uint32_t IRQ23MON; - __IO uint32_t IRQ24MON; - __IO uint32_t IRQ25MON; - __IO uint32_t IRQ26MON; - __IO uint32_t IRQ27MON; - __IO uint32_t IRQ28MON; - __IO uint32_t IRQ29MON; - __IO uint32_t IRQ30MON; - __IO uint32_t IRQ31MON; -}PDL_INTREQ_TypeDef; - -#define PDL_INTREQ_BASE (PDL_PERIPH_BASE + 0x31000UL) // Interrupt request read registers -#define FPDL_INTREQ ((PDL_INTREQ_TypeDef *)PDL_INTREQ_BASE) - -#endif // PDL_INT_TYPE - - -/****************************************************************************** - * Peripheral register bit fields - ******************************************************************************/ - -/****************************************************************************** - * WorkFlash_IF_MODULE - ******************************************************************************/ -/* WorkFlash_IF_MODULE register bit fields */ -typedef struct stc_workflash_if_wfaszr_field -{ - __IO uint32_t ASZ : 1; -} stc_workflash_if_wfaszr_field_t; - -typedef struct stc_workflash_if_wfrwtr_field -{ - __IO uint32_t RWT : 3; -} stc_workflash_if_wfrwtr_field_t; - -typedef struct stc_workflash_if_wfstr_field -{ - __IO uint32_t RDY : 1; - __IO uint32_t HNG : 1; -} stc_workflash_if_wfstr_field_t; - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash_IF_MODULE register bit fields */ -typedef struct stc_flash_if_faszr_field -{ - __IO uint32_t ASZ : 2; -} stc_flash_if_faszr_field_t; - -typedef struct stc_flash_if_frwtr_field -{ - __IO uint32_t RWT : 2; -} stc_flash_if_frwtr_field_t; - -typedef struct stc_flash_if_fstr_field -{ - __IO uint32_t RDY : 1; - __IO uint32_t HNG : 1; - __IO uint32_t ERR : 1; -} stc_flash_if_fstr_field_t; - -typedef struct stc_flash_if_fsyndn_field -{ - __IO uint32_t SD : 3; -} stc_flash_if_fsyndn_field_t; - -typedef struct stc_flash_if_fbfcr_field -{ - __IO uint32_t BE : 1; - __IO uint32_t BS : 1; -} stc_flash_if_fbfcr_field_t; - -typedef struct stc_flash_if_ficr_field -{ - __IO uint32_t RDYIE : 1; - __IO uint32_t HANGIE : 1; - __IO uint32_t ERRIE : 1; -} stc_flash_if_ficr_field_t; - -typedef struct stc_flash_if_fisr_field -{ - __IO uint32_t RDYIF : 1; - __IO uint32_t HANGIF : 1; - __IO uint32_t ERRIF : 1; -} stc_flash_if_fisr_field_t; - -typedef struct stc_flash_if_ficlr_field -{ - __IO uint32_t RDYIC : 1; - __IO uint32_t HANGIC : 1; - __IO uint32_t ERRIC : 1; -} stc_flash_if_ficlr_field_t; - -typedef struct stc_flash_if_crtrmm_field -{ - __IO uint32_t TRMM :10; - uint32_t RESERVED10 : 6; - __IO uint32_t TTRMM : 5; -} stc_flash_if_crtrmm_field_t; - -/****************************************************************************** - * UNIQUE_ID_MODULE - ******************************************************************************/ -/* UNIQUE_ID_MODULE register bit fields */ -typedef struct stc_unique_id_uidr0_field -{ - uint32_t RESERVED0 : 4; - __IO uint32_t UID :28; -} stc_unique_id_uidr0_field_t; - -typedef struct stc_unique_id_uidr1_field -{ - __IO uint32_t UID :13; -} stc_unique_id_uidr1_field_t; - -/****************************************************************************** - * ECC_CAPTURE_MODULE - ******************************************************************************/ -/* ECC_CAPTURE_MODULE register bit fields */ -typedef struct stc_ecc_capture_ferrad_field -{ - __IO uint32_t ERRAD :23; -} stc_ecc_capture_ferrad_field_t; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock_Reset_MODULE register bit fields */ -typedef struct stc_crg_scm_ctl_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MOSCE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SOSCE : 1; - __IO uint8_t PLLE : 1; - __IO uint8_t RCS : 3; -} stc_crg_scm_ctl_field_t; - -typedef struct stc_crg_scm_str_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MORDY : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SORDY : 1; - __IO uint8_t PLRDY : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t RCM2 : 1; -} stc_crg_scm_str_field_t; - -typedef struct stc_crg_rst_str_field -{ - __IO uint16_t PONR : 1; - __IO uint16_t INITX : 1; - __IO uint16_t LVDH : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t SWDT : 1; - __IO uint16_t HWDT : 1; - __IO uint16_t CSVR : 1; - __IO uint16_t FCSR : 1; - __IO uint16_t SRST : 1; -} stc_crg_rst_str_field_t; - -typedef struct stc_crg_bsc_psr_field -{ - __IO uint8_t BSR0 : 1; - __IO uint8_t BSR1 : 1; - __IO uint8_t BSR2 : 1; -} stc_crg_bsc_psr_field_t; - -typedef struct stc_crg_apbc0_psr_field -{ - __IO uint8_t APBC00 : 1; - __IO uint8_t APBC01 : 1; -} stc_crg_apbc0_psr_field_t; - -typedef struct stc_crg_apbc1_psr_field -{ - __IO uint8_t APBC10 : 1; - __IO uint8_t APBC11 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC1RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC1EN : 1; -} stc_crg_apbc1_psr_field_t; - -typedef struct stc_crg_apbc2_psr_field -{ - __IO uint8_t APBC20 : 1; - __IO uint8_t APBC21 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC2RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC2EN : 1; -} stc_crg_apbc2_psr_field_t; - -typedef struct stc_crg_swc_psr_field -{ - __IO uint8_t SWDS0 : 1; - __IO uint8_t SWDS1 : 1; - uint8_t RESERVED1 : 5; - __IO uint8_t TESTB : 1; -} stc_crg_swc_psr_field_t; - -typedef struct stc_crg_ttc_psr_field -{ - __IO uint8_t TTC : 2; -} stc_crg_ttc_psr_field_t; - -typedef struct stc_crg_csw_tmr_field -{ - __IO uint8_t MOWT0 : 1; - __IO uint8_t MOWT1 : 1; - __IO uint8_t MOWT2 : 1; - __IO uint8_t MOWT3 : 1; - __IO uint8_t SOWT0 : 1; - __IO uint8_t SOWT1 : 1; - __IO uint8_t SOWT2 : 1; - __IO uint8_t SOWT3 : 1; -} stc_crg_csw_tmr_field_t; - -typedef struct stc_crg_psw_tmr_field -{ - __IO uint8_t POWT0 : 1; - __IO uint8_t POWT1 : 1; - __IO uint8_t POWT2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t PINC : 1; -} stc_crg_psw_tmr_field_t; - -typedef struct stc_crg_pll_ctl1_field -{ - __IO uint8_t PLLM0 : 1; - __IO uint8_t PLLM1 : 1; - __IO uint8_t PLLM2 : 1; - __IO uint8_t PLLM3 : 1; - __IO uint8_t PLLK0 : 1; - __IO uint8_t PLLK1 : 1; - __IO uint8_t PLLK2 : 1; - __IO uint8_t PLLK3 : 1; -} stc_crg_pll_ctl1_field_t; - -typedef struct stc_crg_pll_ctl2_field -{ - __IO uint8_t PLLN0 : 1; - __IO uint8_t PLLN1 : 1; - __IO uint8_t PLLN2 : 1; - __IO uint8_t PLLN3 : 1; - __IO uint8_t PLLN4 : 1; - __IO uint8_t PLLN5 : 1; -} stc_crg_pll_ctl2_field_t; - -typedef struct stc_crg_csv_ctl_field -{ - __IO uint16_t MCSVE : 1; - __IO uint16_t SCSVE : 1; - uint16_t RESERVED1 : 6; - __IO uint16_t FCSDE : 1; - __IO uint16_t FCSRE : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t FCD0 : 1; - __IO uint16_t FCD1 : 1; - __IO uint16_t FCD2 : 1; -} stc_crg_csv_ctl_field_t; - -typedef struct stc_crg_csv_str_field -{ - __IO uint8_t MCMF : 1; - __IO uint8_t SCMF : 1; -} stc_crg_csv_str_field_t; - -typedef struct stc_crg_dbwdt_ctl_field -{ - uint8_t RESERVED1 : 5; - __IO uint8_t DPSWBE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t DPHWBE : 1; -} stc_crg_dbwdt_ctl_field_t; - -typedef struct stc_crg_int_enr_field -{ - __IO uint8_t MCSE : 1; - __IO uint8_t SCSE : 1; - __IO uint8_t PCSE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSE : 1; -} stc_crg_int_enr_field_t; - -typedef struct stc_crg_int_str_field -{ - __IO uint8_t MCSI : 1; - __IO uint8_t SCSI : 1; - __IO uint8_t PCSI : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSI : 1; -} stc_crg_int_str_field_t; - -typedef struct stc_crg_int_clr_field -{ - __IO uint8_t MCSC : 1; - __IO uint8_t SCSC : 1; - __IO uint8_t PCSC : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSC : 1; -} stc_crg_int_clr_field_t; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* HWWDT_MODULE register bit fields */ -typedef struct stc_hwwdt_wdg_ctl_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_hwwdt_wdg_ctl_field_t; - -typedef struct stc_hwwdt_wdg_ris_field -{ - __IO uint8_t RIS : 1; -} stc_hwwdt_wdg_ris_field_t; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* SWWDT_MODULE register bit fields */ -typedef struct stc_swwdt_wdogcontrol_field -{ - union { - struct { - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; - __IO uint8_t TWD : 2; - __IO uint8_t SPM : 1; - uint8_t RESERVED1 : 3; - }; - struct { - uint8_t RESERVED2 : 2; - __IO uint8_t TWD0 : 1; - __IO uint8_t TWD1 : 1; - uint8_t RESERVED3 : 4; - }; - }; -} stc_swwdt_wdogcontrol_field_t; - -typedef struct stc_swwdt_wdogris_field -{ - __IO uint8_t RIS : 1; - uint8_t RESERVED1 : 7; -} stc_swwdt_wdogris_field_t; - -typedef struct stc_swwdt_wdogspmc_field -{ - __IO uint8_t TGR : 1; - uint8_t RESERVED1 : 7; -} stc_swwdt_wdogspmc_field_t; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* DTIM_MODULE register bit fields */ -typedef struct stc_dtim_timerXcontrol_field -{ - union { - struct { - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE : 2; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; - uint32_t RESERVED2 : 24; - }; - struct { - uint32_t RESERVED3 : 2; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED4 : 28; - }; - }; -} stc_dtim_timerXcontrol_field_t; - -typedef struct stc_dtim_timerXris_field -{ - __IO uint32_t TIMERXRIS : 1; - uint32_t RESERVED1 : 31; -} stc_dtim_timerXris_field_t; - -typedef struct stc_dtim_timerXmis_field -{ - __IO uint32_t TIMERXMIS : 1; - uint32_t RESERVED1 : 31; -} stc_dtim_timerXmis_field_t; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* MFT_FRT_MODULE register bit fields */ -typedef struct stc_mft_frt_tcsa0_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa0_field_t; - -typedef struct stc_mft_frt_tcsc0_field -{ - __IO uint16_t MSZI : 4; - __IO uint16_t MSPI : 4; - __IO uint16_t MSZC : 4; - __IO uint16_t MSPC : 4; -} stc_mft_frt_tcsc0_field_t; - -typedef struct stc_mft_frt_tcsa1_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa1_field_t; - -typedef struct stc_mft_frt_tcsc1_field -{ - __IO uint16_t MSZI : 4; - __IO uint16_t MSPI : 4; - __IO uint16_t MSZC : 4; - __IO uint16_t MSPC : 4; -} stc_mft_frt_tcsc1_field_t; - -typedef struct stc_mft_frt_tcsa2_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa2_field_t; - -typedef struct stc_mft_frt_tcsc2_field -{ - __IO uint16_t MSZI : 4; - __IO uint16_t MSPI : 4; - __IO uint16_t MSZC : 4; - __IO uint16_t MSPC : 4; -} stc_mft_frt_tcsc2_field_t; - -typedef struct stc_mft_frt_tcal_field -{ - __IO uint32_t STOP00 : 1; - __IO uint32_t STOP01 : 1; - __IO uint32_t STOP02 : 1; - __IO uint32_t STOP10 : 1; - __IO uint32_t STOP11 : 1; - __IO uint32_t STOP12 : 1; - __IO uint32_t STOP20 : 1; - __IO uint32_t STOP21 : 1; - __IO uint32_t STOP22 : 1; - __IO uint32_t RESERVED1 : 7; - __IO uint32_t SCLR00 : 1; - __IO uint32_t SCLR01 : 1; - __IO uint32_t SCLR02 : 1; - __IO uint32_t SCLR10 : 1; - __IO uint32_t SCLR11 : 1; - __IO uint32_t SCLR12 : 1; - __IO uint32_t SCLR20 : 1; - __IO uint32_t SCLR21 : 1; - __IO uint32_t SCLR22 : 1; - __IO uint32_t RESERVED2 : 7; -} stc_mft_frt_tcal_field_t; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* MFT_OCU_MODULE register bit fields */ -typedef struct stc_mft_ocu_ocsa10_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t RESERVED1 : 2; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa10_field_t; - -typedef struct stc_mft_ocu_ocsb10_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t FM4 : 1; -} stc_mft_ocu_ocsb10_field_t; - -typedef struct stc_mft_ocu_ocsa32_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t RESERVED1 : 2; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa32_field_t; - -typedef struct stc_mft_ocu_ocsb32_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t FM4 : 1; -} stc_mft_ocu_ocsb32_field_t; - -typedef struct stc_mft_ocu_ocsa54_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t RESERVED1 : 2; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa54_field_t; - -typedef struct stc_mft_ocu_ocsb54_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t FM4 : 1; -} stc_mft_ocu_ocsb54_field_t; - -typedef struct stc_mft_ocu_ocsc_field -{ - __IO uint8_t MOD0 : 1; - __IO uint8_t MOD1 : 1; - __IO uint8_t MOD2 : 1; - __IO uint8_t MOD3 : 1; - __IO uint8_t MOD4 : 1; - __IO uint8_t MOD5 : 1; -} stc_mft_ocu_ocsc_field_t; - -typedef struct stc_mft_ocu_ocfs10_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs10_field_t; - -typedef struct stc_mft_ocu_ocfs32_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs32_field_t; - -typedef struct stc_mft_ocu_ocfs54_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs54_field_t; - -typedef struct stc_mft_ocu_ocsd10_field -{ - __IO uint8_t OCCP0BUFE : 2; - __IO uint8_t OCCP1BUFE : 2; - __IO uint8_t OCSE0BUFE : 2; - __IO uint8_t OCSE1BUFE : 2; -} stc_mft_ocu_ocsd10_field_t; - -typedef struct stc_mft_ocu_ocsd32_field -{ - __IO uint8_t OCCP2BUFE : 2; - __IO uint8_t OCCP3BUFE : 2; - __IO uint8_t OCSE2BUFE : 2; - __IO uint8_t OCSE3BUFE : 2; -} stc_mft_ocu_ocsd32_field_t; - -typedef struct stc_mft_ocu_ocsd54_field -{ - __IO uint8_t OCCP4BUFE : 2; - __IO uint8_t OCCP5BUFE : 2; - __IO uint8_t OCSE4BUFE : 2; - __IO uint8_t OCSE5BUFE : 2; -} stc_mft_ocu_ocsd54_field_t; - -typedef struct stc_mft_ocu_ocse0_field -{ - __IO uint16_t OCSE : 16; -} stc_mft_ocu_ocse0_field_t; - -typedef struct stc_mft_ocu_ocse1_field -{ - __IO uint32_t OCSE : 32; -} stc_mft_ocu_ocse1_field_t; - -typedef struct stc_mft_ocu_ocse2_field -{ - __IO uint16_t OCSE : 16; -} stc_mft_ocu_ocse2_field_t; - -typedef struct stc_mft_ocu_ocse3_field -{ - __IO uint32_t OCSE : 32; -} stc_mft_ocu_ocse3_field_t; - -typedef struct stc_mft_ocu_ocse4_field -{ - __IO uint16_t OCSE : 16; -} stc_mft_ocu_ocse4_field_t; - -typedef struct stc_mft_ocu_ocse5_field -{ - __IO uint32_t OCSE : 32; -} stc_mft_ocu_ocse5_field_t; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* MFT_WFG_MODULE register bit fields */ -typedef struct stc_mft_wfg_wfsa10_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 2; -} stc_mft_wfg_wfsa10_field_t; - -typedef struct stc_mft_wfg_wfsa32_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 2; -} stc_mft_wfg_wfsa32_field_t; - -typedef struct stc_mft_wfg_wfsa54_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 2; -} stc_mft_wfg_wfsa54_field_t; - -typedef struct stc_mft_wfg_wfir_field -{ - __IO uint16_t DTIFA : 1; - __IO uint16_t DTICA : 1; - __IO uint16_t DTIFB : 1; - __IO uint16_t DTICB : 1; - __IO uint16_t TMIF10 : 1; - __IO uint16_t TMIC10 : 1; - __IO uint16_t TMIE10 : 1; - __IO uint16_t TMIS10 : 1; - __IO uint16_t TMIF32 : 1; - __IO uint16_t TMIC32 : 1; - __IO uint16_t TMIE32 : 1; - __IO uint16_t TMIS32 : 1; - __IO uint16_t TMIF54 : 1; - __IO uint16_t TMIC54 : 1; - __IO uint16_t TMIE54 : 1; - __IO uint16_t TMIS54 : 1; -} stc_mft_wfg_wfir_field_t; - -typedef struct stc_mft_wfg_nzcl_field -{ - __IO uint16_t DTIEA : 1; - __IO uint16_t NWS0 : 1; - __IO uint16_t NWS1 : 1; - __IO uint16_t NWS2 : 1; - __IO uint16_t SDTI : 1; - __IO uint16_t DTIEB : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t DIMA : 1; - __IO uint16_t DIMB : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t WIM10 : 1; - __IO uint16_t WIM32 : 1; - __IO uint16_t WIM54 : 1; - uint16_t RESERVED3 : 1; -} stc_mft_wfg_nzcl_field_t; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* MFT_ICU_MODULE register bit fields */ -typedef struct stc_mft_icu_icfs10_field -{ - __IO uint8_t FSI00 : 1; - __IO uint8_t FSI01 : 1; - __IO uint8_t FSI02 : 1; - __IO uint8_t FSI03 : 1; - __IO uint8_t FSI10 : 1; - __IO uint8_t FSI11 : 1; - __IO uint8_t FSI12 : 1; - __IO uint8_t FSI13 : 1; -} stc_mft_icu_icfs10_field_t; - -typedef struct stc_mft_icu_icfs32_field -{ - __IO uint8_t FSI00 : 1; - __IO uint8_t FSI01 : 1; - __IO uint8_t FSI02 : 1; - __IO uint8_t FSI03 : 1; - __IO uint8_t FSI10 : 1; - __IO uint8_t FSI11 : 1; - __IO uint8_t FSI12 : 1; - __IO uint8_t FSI13 : 1; -} stc_mft_icu_icfs32_field_t; - -typedef struct stc_mft_icu_icsa10_field -{ - __IO uint8_t EG00 : 1; - __IO uint8_t EG01 : 1; - __IO uint8_t EG10 : 1; - __IO uint8_t EG11 : 1; - __IO uint8_t ICE0 : 1; - __IO uint8_t ICE1 : 1; - __IO uint8_t ICP0 : 1; - __IO uint8_t ICP1 : 1; -} stc_mft_icu_icsa10_field_t; - -typedef struct stc_mft_icu_icsb10_field -{ - __IO uint8_t IEI0 : 1; - __IO uint8_t IEI1 : 1; -} stc_mft_icu_icsb10_field_t; - -typedef struct stc_mft_icu_icsa32_field -{ - __IO uint8_t EG00 : 1; - __IO uint8_t EG01 : 1; - __IO uint8_t EG10 : 1; - __IO uint8_t EG11 : 1; - __IO uint8_t ICE0 : 1; - __IO uint8_t ICE1 : 1; - __IO uint8_t ICP0 : 1; - __IO uint8_t ICP1 : 1; -} stc_mft_icu_icsa32_field_t; - -typedef struct stc_mft_icu_icsb32_field -{ - __IO uint8_t IEI0 : 1; - __IO uint8_t IEI1 : 1; -} stc_mft_icu_icsb32_field_t; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* MFT_ADCMP_MODULE register bit fields */ -typedef struct stc_mft_adcmp_acfs10_field -{ - __IO uint8_t FSA0 : 4; - __IO uint8_t FSA1 : 4; -} stc_mft_adcmp_acfs10_field_t; - -typedef struct stc_mft_adcmp_acfs32_field -{ - __IO uint8_t FSA2 : 4; - __IO uint8_t FSA3 : 4; -} stc_mft_adcmp_acfs32_field_t; - -typedef struct stc_mft_adcmp_acfs54_field -{ - __IO uint8_t FSA4 : 4; - __IO uint8_t FSA5 : 4; -} stc_mft_adcmp_acfs54_field_t; - -typedef struct stc_mft_adcmp_acsa_field -{ - __IO uint16_t CE10 : 2; - __IO uint16_t CE32 : 2; - __IO uint16_t CE54 : 2; - uint16_t RESERVED1 : 2; - __IO uint16_t SEL10 : 2; - __IO uint16_t SEL32 : 2; - __IO uint16_t SEL54 : 2; -} stc_mft_adcmp_acsa_field_t; - -typedef struct stc_mft_adcmp_acsc_field -{ - __IO uint8_t BUFE : 2; - __IO uint8_t ADSEL : 3; - uint8_t RESERVED1 : 3; -} stc_mft_adcmp_acsc_field_t; - -typedef struct stc_mft_adcmp_acsd_field -{ - __IO uint8_t AMOD : 1; - __IO uint8_t OCUS : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t DE : 1; - __IO uint8_t PE : 1; - __IO uint8_t UE : 1; - __IO uint8_t ZE : 1; -} stc_mft_adcmp_acsd_field_t; - -/****************************************************************************** - * DAC MODULE - ******************************************************************************/ -typedef struct stc_dacr_field -{ - __IO uint8_t DAE : 1; - __IO uint8_t DRDY : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t DAC10 : 1; - __IO uint8_t DDAS : 1; - __IO uint8_t RESERVED2 : 2; -} stc_dacr_field_t; - -typedef struct stc_dadr_field -{ - __IO uint16_t DA : 12; - __IO uint16_t RESERVED : 4; -} stc_dadr_field_t; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* MFT_PPG_MODULE register bit fields */ -typedef struct stc_mft_ppg_ttcr0_field -{ - __IO uint8_t STR0 : 1; - __IO uint8_t MONI0 : 1; - __IO uint8_t CS00 : 1; - __IO uint8_t CS01 : 1; - __IO uint8_t TRG0O : 1; - __IO uint8_t TRG2O : 1; - __IO uint8_t TRG4O : 1; - __IO uint8_t TRG6O : 1; -} stc_mft_ppg_ttcr0_field_t; - -typedef struct stc_mft_ppg_ttcr1_field -{ - __IO uint8_t STR1 : 1; - __IO uint8_t MONI1 : 1; - __IO uint8_t CS10 : 1; - __IO uint8_t CS11 : 1; - __IO uint8_t TRG1O : 1; - __IO uint8_t TRG3O : 1; - __IO uint8_t TRG5O : 1; - __IO uint8_t TRG7O : 1; -} stc_mft_ppg_ttcr1_field_t; - -typedef struct stc_mft_ppg_ttcr2_field -{ - __IO uint8_t STR2 : 1; - __IO uint8_t MONI2 : 1; - __IO uint8_t CS20 : 1; - __IO uint8_t CS21 : 1; - __IO uint8_t TRG16O : 1; - __IO uint8_t TRG18O : 1; - __IO uint8_t TRG20O : 1; - __IO uint8_t TRG22O : 1; -} stc_mft_ppg_ttcr2_field_t; - -typedef struct stc_mft_ppg_trg_field -{ - __IO uint16_t PEN00 : 1; - __IO uint16_t PEN01 : 1; - __IO uint16_t PEN02 : 1; - __IO uint16_t PEN03 : 1; - __IO uint16_t PEN04 : 1; - __IO uint16_t PEN05 : 1; - __IO uint16_t PEN06 : 1; - __IO uint16_t PEN07 : 1; - __IO uint16_t PEN08 : 1; - __IO uint16_t PEN09 : 1; - __IO uint16_t PEN10 : 1; - __IO uint16_t PEN11 : 1; - __IO uint16_t PEN12 : 1; - __IO uint16_t PEN13 : 1; - __IO uint16_t PEN14 : 1; - __IO uint16_t PEN15 : 1; -} stc_mft_ppg_trg0_field_t; - -typedef struct stc_mft_ppg_trg1_field -{ - __IO uint16_t PEN16 : 1; - __IO uint16_t PEN17 : 1; - __IO uint16_t PEN18 : 1; - __IO uint16_t PEN19 : 1; - __IO uint16_t PEN20 : 1; - __IO uint16_t PEN21 : 1; - __IO uint16_t PEN22 : 1; - __IO uint16_t PEN23 : 1; -} stc_mft_ppg_trg1_field_t; - -typedef struct stc_mft_ppg_revc_field -{ - __IO uint16_t REV00 : 1; - __IO uint16_t REV01 : 1; - __IO uint16_t REV02 : 1; - __IO uint16_t REV03 : 1; - __IO uint16_t REV04 : 1; - __IO uint16_t REV05 : 1; - __IO uint16_t REV06 : 1; - __IO uint16_t REV07 : 1; - __IO uint16_t REV08 : 1; - __IO uint16_t REV09 : 1; - __IO uint16_t REV10 : 1; - __IO uint16_t REV11 : 1; - __IO uint16_t REV12 : 1; - __IO uint16_t REV13 : 1; - __IO uint16_t REV14 : 1; - __IO uint16_t REV15 : 1; -} stc_mft_ppg_revc0_field_t; - -typedef struct stc_mft_ppg_revc1_field -{ - __IO uint16_t REV16 : 1; - __IO uint16_t REV17 : 1; - __IO uint16_t REV18 : 1; - __IO uint16_t REV19 : 1; - __IO uint16_t REV20 : 1; - __IO uint16_t REV21 : 1; - __IO uint16_t REV22 : 1; - __IO uint16_t REV23 : 1; -} stc_mft_ppg_revc1_field_t; - -typedef struct stc_mft_ppg_ppgc1_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc1_field_t; - -typedef struct stc_mft_ppg_ppgc0_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc0_field_t; - -typedef struct stc_mft_ppg_ppgc3_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc3_field_t; - -typedef struct stc_mft_ppg_ppgc2_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc2_field_t; - -typedef struct stc_mft_ppg_gatec0_field -{ - __IO uint8_t EDGE0 : 1; - __IO uint8_t STRG0 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE2 : 1; - __IO uint8_t STRG2 : 1; -} stc_mft_ppg_gatec0_field_t; - -typedef struct stc_mft_ppg_ppgc5_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc5_field_t; - -typedef struct stc_mft_ppg_ppgc4_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc4_field_t; - -typedef struct stc_mft_ppg_ppgc7_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc7_field_t; - -typedef struct stc_mft_ppg_ppgc6_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc6_field_t; - -typedef struct stc_mft_ppg_gatec4_field -{ - __IO uint8_t EDGE4 : 1; - __IO uint8_t STRG4 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE6 : 1; - __IO uint8_t STRG6 : 1; -} stc_mft_ppg_gatec4_field_t; - -typedef struct stc_mft_ppg_ppgc9_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc9_field_t; - -typedef struct stc_mft_ppg_ppgc8_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc8_field_t; - -typedef struct stc_mft_ppg_ppgc11_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc11_field_t; - -typedef struct stc_mft_ppg_ppgc10_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc10_field_t; - -typedef struct stc_mft_ppg_gatec8_field -{ - __IO uint8_t EDGE8 : 1; - __IO uint8_t STRG8 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE10 : 1; - __IO uint8_t STRG10 : 1; -} stc_mft_ppg_gatec8_field_t; - -typedef struct stc_mft_ppg_ppgc13_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc13_field_t; - -typedef struct stc_mft_ppg_ppgc12_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc12_field_t; - -typedef struct stc_mft_ppg_ppgc15_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc15_field_t; - -typedef struct stc_mft_ppg_ppgc14_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc14_field_t; - -typedef struct stc_mft_ppg_gatec12_field -{ - __IO uint8_t EDGE12 : 1; - __IO uint8_t STRG12 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE14 : 1; - __IO uint8_t STRG14 : 1; -} stc_mft_ppg_gatec12_field_t; - -typedef struct stc_mft_ppg_ppgc17_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc17_field_t; - -typedef struct stc_mft_ppg_ppgc16_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc16_field_t; - -typedef struct stc_mft_ppg_ppgc19_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc19_field_t; - -typedef struct stc_mft_ppg_ppgc18_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc18_field_t; - -typedef struct stc_mft_ppg_gatec16_field -{ - __IO uint8_t EDGE16 : 1; - __IO uint8_t STRG16 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE18 : 1; - __IO uint8_t STRG18 : 1; -} stc_mft_ppg_gatec16_field_t; - -typedef struct stc_mft_ppg_ppgc21_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc21_field_t; - -typedef struct stc_mft_ppg_ppgc20_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc20_field_t; - -typedef struct stc_mft_ppg_ppgc23_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc23_field_t; - -typedef struct stc_mft_ppg_ppgc22_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc22_field_t; - -typedef struct stc_mft_ppg_gatec20_field -{ - __IO uint8_t EDGE20 : 1; - __IO uint8_t STRG20 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE22 : 1; - __IO uint8_t STRG22 : 1; -} stc_mft_ppg_gatec20_field_t; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* BT_PPG_MODULE register bit fields */ -typedef struct stc_bt_ppg_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_ppg_tmcr_field_t; - -typedef struct stc_bt_ppg_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_ppg_stc_field_t; - -typedef struct stc_bt_ppg_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_ppg_tmcr2_field_t; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* BT_PWM_MODULE register bit fields */ -typedef struct stc_bt_pwm_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwm_tmcr_field_t; - -typedef struct stc_bt_pwm_stc_field -{ - __IO uint8_t UDIR : 1; - __IO uint8_t DTIR : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t UDIE : 1; - __IO uint8_t DTIE : 1; - __IO uint8_t TGIE : 1; -} stc_bt_pwm_stc_field_t; - -typedef struct stc_bt_pwm_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwm_tmcr2_field_t; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* BT_RT_MODULE register bit fields */ -typedef struct stc_bt_rt_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_rt_tmcr_field_t; - -typedef struct stc_bt_rt_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_rt_stc_field_t; - -typedef struct stc_bt_rt_tmcr2_field -{ - __IO uint8_t CKS3 : 1; - __IO uint8_t RESERVED1 : 6; - __IO uint8_t GATE : 1; -} stc_bt_rt_tmcr2_field_t; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* BT_PWC_MODULE register bit fields */ -typedef struct stc_bt_pwc_tmcr_field -{ - uint16_t RESERVED1 : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t EGS2 : 1; - uint16_t RESERVED3 : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwc_tmcr_field_t; - -typedef struct stc_bt_pwc_stc_field -{ - __IO uint8_t OVIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t EDIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t OVIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t EDIE : 1; - __IO uint8_t ERR : 1; -} stc_bt_pwc_stc_field_t; - -typedef struct stc_bt_pwc_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwc_tmcr2_field_t; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* BTIOSEL03_MODULE register bit fields */ -typedef struct stc_btiosel03_btsel0123_field -{ - __IO uint8_t SEL01_0 : 1; - __IO uint8_t SEL01_1 : 1; - __IO uint8_t SEL01_2 : 1; - __IO uint8_t SEL01_3 : 1; - __IO uint8_t SEL23_0 : 1; - __IO uint8_t SEL23_1 : 1; - __IO uint8_t SEL23_2 : 1; - __IO uint8_t SEL23_3 : 1; -} stc_btiosel03_btsel0123_field_t; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* BTIOSEL47_MODULE register bit fields */ -typedef struct stc_btiosel47_btsel4567_field -{ - __IO uint8_t SEL45_0 : 1; - __IO uint8_t SEL45_1 : 1; - __IO uint8_t SEL45_2 : 1; - __IO uint8_t SEL45_3 : 1; - __IO uint8_t SEL67_0 : 1; - __IO uint8_t SEL67_1 : 1; - __IO uint8_t SEL67_2 : 1; - __IO uint8_t SEL67_3 : 1; -} stc_btiosel47_btsel4567_field_t; - -/****************************************************************************** - * BTIOSEL811_MODULE - ******************************************************************************/ -/* BTIOSEL811_MODULE register bit fields */ -typedef struct stc_btiosel8b_btsel89ab_field -{ - __IO uint8_t SEL89_0 : 1; - __IO uint8_t SEL89_1 : 1; - __IO uint8_t SEL89_2 : 1; - __IO uint8_t SEL89_3 : 1; - __IO uint8_t SELAB_0 : 1; - __IO uint8_t SELAB_1 : 1; - __IO uint8_t SELAB_2 : 1; - __IO uint8_t SELAB_3 : 1; -} stc_btiosel8b_btsel89ab_field_t; - -/****************************************************************************** - * BTIOSEL1215_MODULE - ******************************************************************************/ -/* BTIOSEL1215_MODULE register bit fields */ -typedef struct stc_btioselcf_btselcdef_field -{ - __IO uint8_t SELCD_0 : 1; - __IO uint8_t SELCD_1 : 1; - __IO uint8_t SELCD_2 : 1; - __IO uint8_t SELCD_3 : 1; - __IO uint8_t SELEF_0 : 1; - __IO uint8_t SELEF_1 : 1; - __IO uint8_t SELEF_2 : 1; - __IO uint8_t SELEF_3 : 1; -} stc_btioselcf_btselcdef_field_t; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* SBSSR_MODULE register bit fields */ -typedef struct stc_sbssr_btsssr_field -{ - __IO uint16_t SSR0 : 1; - __IO uint16_t SSR1 : 1; - __IO uint16_t SSR2 : 1; - __IO uint16_t SSR3 : 1; - __IO uint16_t SSR4 : 1; - __IO uint16_t SSR5 : 1; - __IO uint16_t SSR6 : 1; - __IO uint16_t SSR7 : 1; - __IO uint16_t SSR8 : 1; - __IO uint16_t SSR9 : 1; - __IO uint16_t SSR10 : 1; - __IO uint16_t SSR11 : 1; - __IO uint16_t SSR12 : 1; - __IO uint16_t SSR13 : 1; - __IO uint16_t SSR14 : 1; - __IO uint16_t SSR15 : 1; -} stc_sbssr_btsssr_field_t; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* QPRC_MODULE register bit fields */ -typedef struct stc_qprc_qicr_field -{ - __IO uint16_t QPCMIE : 1; - __IO uint16_t QPCMF : 1; - __IO uint16_t QPRCMIE : 1; - __IO uint16_t QPRCMF : 1; - __IO uint16_t OUZIE : 1; - __IO uint16_t UFDF : 1; - __IO uint16_t OFDF : 1; - __IO uint16_t ZIIF : 1; - __IO uint16_t CDCIE : 1; - __IO uint16_t CDCF : 1; - __IO uint16_t DIRPC : 1; - __IO uint16_t DIROU : 1; - __IO uint16_t QPCNRCMIE : 1; - __IO uint16_t QPCNRCMF : 1; -} stc_qprc_qicr_field_t; - -typedef struct stc_qprc_qicrl_field -{ - __IO uint8_t QPCMIE : 1; - __IO uint8_t QPCMF : 1; - __IO uint8_t QPRCMIE : 1; - __IO uint8_t QPRCMF : 1; - __IO uint8_t OUZIE : 1; - __IO uint8_t UFDF : 1; - __IO uint8_t OFDF : 1; - __IO uint8_t ZIIF : 1; -} stc_qprc_qicrl_field_t; - -typedef struct stc_qprc_qicrh_field -{ - __IO uint8_t CDCIE : 1; - __IO uint8_t CDCF : 1; - __IO uint8_t DIRPC : 1; - __IO uint8_t DIROU : 1; - __IO uint8_t QPCNRCMIE : 1; - __IO uint8_t QPCNRCMF : 1; -} stc_qprc_qicrh_field_t; - -typedef struct stc_qprc_qcr_field -{ - __IO uint16_t PCM0 : 1; - __IO uint16_t PCM1 : 1; - __IO uint16_t RCM0 : 1; - __IO uint16_t RCM1 : 1; - __IO uint16_t PSTP : 1; - __IO uint16_t CGSC : 1; - __IO uint16_t RSEL : 1; - __IO uint16_t SWAP : 1; - __IO uint16_t PCRM0 : 1; - __IO uint16_t PCRM1 : 1; - __IO uint16_t AES0 : 1; - __IO uint16_t AES1 : 1; - __IO uint16_t BES0 : 1; - __IO uint16_t BES1 : 1; - __IO uint16_t CGE0 : 1; - __IO uint16_t CGE1 : 1; -} stc_qprc_qcr_field_t; - -typedef struct stc_qprc_qcrl_field -{ - __IO uint8_t PCM0 : 1; - __IO uint8_t PCM1 : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t PSTP : 1; - __IO uint8_t CGSC : 1; - __IO uint8_t RSEL : 1; - __IO uint8_t SWAP : 1; -} stc_qprc_qcrl_field_t; - -typedef struct stc_qprc_qcrh_field -{ - __IO uint8_t PCRM0 : 1; - __IO uint8_t PCRM1 : 1; - __IO uint8_t AES0 : 1; - __IO uint8_t AES1 : 1; - __IO uint8_t BES0 : 1; - __IO uint8_t BES1 : 1; - __IO uint8_t CGE0 : 1; - __IO uint8_t CGE1 : 1; -} stc_qprc_qcrh_field_t; - -typedef struct stc_qprc_qecr_field -{ - __IO uint16_t ORNGMD : 1; - __IO uint16_t ORNGF : 1; - __IO uint16_t ORNGIE : 1; -} stc_qprc_qecr_field_t; - -/****************************************************************************** - * QPRC_NF_MODULE - ******************************************************************************/ -/* QPRC_NF_MODULE register bit fields */ -typedef struct stc_qprc_nf_nfctla_field -{ - __IO uint8_t AINNWS : 3; - uint8_t RESERVED1 : 1; - __IO uint8_t AINLV : 1; - __IO uint8_t AINMD : 1; -} stc_qprc_nf_nfctla_field_t; - -typedef struct stc_qprc_nf_nfctlb_field -{ - __IO uint8_t BINNWS : 3; - uint8_t RESERVED1 : 1; - __IO uint8_t BINLV : 1; - __IO uint8_t BINMD : 1; -} stc_qprc_nf_nfctlb_field_t; - -typedef struct stc_qprc_nf_nfrctlz_field -{ - __IO uint8_t ZINNWS : 3; - uint8_t RESERVED1 : 1; - __IO uint8_t ZINLV : 1; - __IO uint8_t ZINMD : 1; -} stc_qprc_nf_nfrctlz_field_t; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* ADC12_MODULE register bit fields */ -typedef struct stc_adc_adsr_field -{ - __IO uint8_t SCS : 1; - __IO uint8_t PCS : 1; - __IO uint8_t PCNS : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t FDAS : 1; - __IO uint8_t ADSTP : 1; -} stc_adc_adsr_field_t; - -typedef struct stc_adc_adcr_field -{ - __IO uint8_t OVRIE : 1; - __IO uint8_t CMPIE : 1; - __IO uint8_t PCIE : 1; - __IO uint8_t SCIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t CMPIF : 1; - __IO uint8_t PCIF : 1; - __IO uint8_t SCIF : 1; -} stc_adc_adcr_field_t; - -typedef struct stc_adc_sfns_field -{ - __IO uint8_t SFS0 : 1; - __IO uint8_t SFS1 : 1; - __IO uint8_t SFS2 : 1; - __IO uint8_t SFS3 : 1; -} stc_adc_sfns_field_t; - -typedef struct stc_adc_sccr_field -{ - __IO uint8_t SSTR : 1; - __IO uint8_t SHEN : 1; - __IO uint8_t RPT : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t SFCLR : 1; - __IO uint8_t SOVR : 1; - __IO uint8_t SFUL : 1; - __IO uint8_t SEMP : 1; -} stc_adc_sccr_field_t; - -typedef struct stc_adc_scfd_field -{ - __IO uint32_t SC0 : 1; - __IO uint32_t SC1 : 1; - __IO uint32_t SC2 : 1; - __IO uint32_t SC3 : 1; - __IO uint32_t SC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; - __IO uint32_t SD3 : 1; - __IO uint32_t SD4 : 1; - __IO uint32_t SD5 : 1; - __IO uint32_t SD6 : 1; - __IO uint32_t SD7 : 1; - __IO uint32_t SD8 : 1; - __IO uint32_t SD9 : 1; - __IO uint32_t SD10 : 1; - __IO uint32_t SD11 : 1; -} stc_adc_scfd_field_t; - -typedef struct stc_adc_scfdl_field -{ - __IO uint16_t SC0 : 1; - __IO uint16_t SC1 : 1; - __IO uint16_t SC2 : 1; - __IO uint16_t SC3 : 1; - __IO uint16_t SC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t INVL : 1; -} stc_adc_scfdl_field_t; - -typedef struct stc_adc_scfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t SD0 : 1; - __IO uint16_t SD1 : 1; - __IO uint16_t SD2 : 1; - __IO uint16_t SD3 : 1; - __IO uint16_t SD4 : 1; - __IO uint16_t SD5 : 1; - __IO uint16_t SD6 : 1; - __IO uint16_t SD7 : 1; - __IO uint16_t SD8 : 1; - __IO uint16_t SD9 : 1; - __IO uint16_t SD10 : 1; - __IO uint16_t SD11 : 1; -} stc_adc_scfdh_field_t; - -typedef struct stc_adc_scis23_field -{ - __IO uint16_t AN16 : 1; - __IO uint16_t AN17 : 1; - __IO uint16_t AN18 : 1; - __IO uint16_t AN19 : 1; - __IO uint16_t AN20 : 1; - __IO uint16_t AN21 : 1; - __IO uint16_t AN22 : 1; - __IO uint16_t AN23 : 1; - __IO uint16_t AN24 : 1; - __IO uint16_t AN25 : 1; - __IO uint16_t AN26 : 1; - __IO uint16_t AN27 : 1; - __IO uint16_t AN28 : 1; - __IO uint16_t AN29 : 1; - __IO uint16_t AN30 : 1; - __IO uint16_t AN31 : 1; -} stc_adc_scis23_field_t; - -typedef struct stc_adc_scis2_field -{ - __IO uint8_t AN16 : 1; - __IO uint8_t AN17 : 1; - __IO uint8_t AN18 : 1; - __IO uint8_t AN19 : 1; - __IO uint8_t AN20 : 1; - __IO uint8_t AN21 : 1; - __IO uint8_t AN22 : 1; - __IO uint8_t AN23 : 1; -} stc_adc_scis2_field_t; - -typedef struct stc_adc_scis3_field -{ - __IO uint8_t AN24 : 1; - __IO uint8_t AN25 : 1; - __IO uint8_t AN26 : 1; - __IO uint8_t AN27 : 1; - __IO uint8_t AN28 : 1; - __IO uint8_t AN29 : 1; - __IO uint8_t AN30 : 1; - __IO uint8_t AN31 : 1; -} stc_adc_scis3_field_t; - -typedef struct stc_adc_scis01_field -{ - __IO uint16_t AN0 : 1; - __IO uint16_t AN1 : 1; - __IO uint16_t AN2 : 1; - __IO uint16_t AN3 : 1; - __IO uint16_t AN4 : 1; - __IO uint16_t AN5 : 1; - __IO uint16_t AN6 : 1; - __IO uint16_t AN7 : 1; - __IO uint16_t AN8 : 1; - __IO uint16_t AN9 : 1; - __IO uint16_t AN10 : 1; - __IO uint16_t AN11 : 1; - __IO uint16_t AN12 : 1; - __IO uint16_t AN13 : 1; - __IO uint16_t AN14 : 1; - __IO uint16_t AN15 : 1; -} stc_adc_scis01_field_t; - -typedef struct stc_adc_scis0_field -{ - __IO uint8_t AN0 : 1; - __IO uint8_t AN1 : 1; - __IO uint8_t AN2 : 1; - __IO uint8_t AN3 : 1; - __IO uint8_t AN4 : 1; - __IO uint8_t AN5 : 1; - __IO uint8_t AN6 : 1; - __IO uint8_t AN7 : 1; -} stc_adc_scis0_field_t; - -typedef struct stc_adc_scis1_field -{ - __IO uint8_t AN8 : 1; - __IO uint8_t AN9 : 1; - __IO uint8_t AN10 : 1; - __IO uint8_t AN11 : 1; - __IO uint8_t AN12 : 1; - __IO uint8_t AN13 : 1; - __IO uint8_t AN14 : 1; - __IO uint8_t AN15 : 1; -} stc_adc_scis1_field_t; - -typedef struct stc_adc_pfns_field -{ - __IO uint8_t PFS : 2; - uint8_t RESERVED1 : 2; - __IO uint8_t TEST0 : 1; - __IO uint8_t TEST1 : 1; -} stc_adc_pfns_field_t; - -typedef struct stc_adc_pccr_field -{ - __IO uint8_t PSTR : 1; - __IO uint8_t PHEN : 1; - __IO uint8_t PEEN : 1; - __IO uint8_t ESCE : 1; - __IO uint8_t PFCLR : 1; - __IO uint8_t POVR : 1; - __IO uint8_t PFUL : 1; - __IO uint8_t PEMP : 1; -} stc_adc_pccr_field_t; - -typedef struct stc_adc_pcfd_field -{ - __IO uint32_t PC0 : 1; - __IO uint32_t PC1 : 1; - __IO uint32_t PC2 : 1; - __IO uint32_t PC3 : 1; - __IO uint32_t PC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t PD0 : 1; - __IO uint32_t PD1 : 1; - __IO uint32_t PD2 : 1; - __IO uint32_t PD3 : 1; - __IO uint32_t PD4 : 1; - __IO uint32_t PD5 : 1; - __IO uint32_t PD6 : 1; - __IO uint32_t PD7 : 1; - __IO uint32_t PD8 : 1; - __IO uint32_t PD9 : 1; - __IO uint32_t PD10 : 1; - __IO uint32_t PD11 : 1; -} stc_adc_pcfd_field_t; - -typedef struct stc_adc_pcfdl_field -{ - __IO uint16_t PC0 : 1; - __IO uint16_t PC1 : 1; - __IO uint16_t PC2 : 1; - __IO uint16_t PC3 : 1; - __IO uint16_t PC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - __IO uint16_t RS2 : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t INVL : 1; -} stc_adc_pcfdl_field_t; - -typedef struct stc_adc_pcfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t PD0 : 1; - __IO uint16_t PD1 : 1; - __IO uint16_t PD2 : 1; - __IO uint16_t PD3 : 1; - __IO uint16_t PD4 : 1; - __IO uint16_t PD5 : 1; - __IO uint16_t PD6 : 1; - __IO uint16_t PD7 : 1; - __IO uint16_t PD8 : 1; - __IO uint16_t PD9 : 1; - __IO uint16_t PD10 : 1; - __IO uint16_t PD11 : 1; -} stc_adc_pcfdh_field_t; - -typedef struct stc_adc_pcis_field -{ - __IO uint8_t P1A : 3; - __IO uint8_t P2A : 5; -} stc_adc_pcis_field_t; - -typedef struct stc_adc_cmpcr_field -{ - __IO uint8_t CCH : 5; - __IO uint8_t CMD0 : 1; - __IO uint8_t CMD1 : 1; - __IO uint8_t CMPEN : 1; -} stc_adc_cmpcr_field_t; - -typedef struct stc_adc_cmpd_field -{ - uint16_t RESERVED1 : 6; - __IO uint16_t CMAD2 : 1; - __IO uint16_t CMAD3 : 1; - __IO uint16_t CMAD4 : 1; - __IO uint16_t CMAD5 : 1; - __IO uint16_t CMAD6 : 1; - __IO uint16_t CMAD7 : 1; - __IO uint16_t CMAD8 : 1; - __IO uint16_t CMAD9 : 1; - __IO uint16_t CMAD10 : 1; - __IO uint16_t CMAD11 : 1; -} stc_adc_cmpd_field_t; - -typedef struct stc_adc_adss23_field -{ - __IO uint16_t TS16 : 1; - __IO uint16_t TS17 : 1; - __IO uint16_t TS18 : 1; - __IO uint16_t TS19 : 1; - __IO uint16_t TS20 : 1; - __IO uint16_t TS21 : 1; - __IO uint16_t TS22 : 1; - __IO uint16_t TS23 : 1; - __IO uint16_t TS24 : 1; - __IO uint16_t TS25 : 1; - __IO uint16_t TS26 : 1; - __IO uint16_t TS27 : 1; - __IO uint16_t TS28 : 1; - __IO uint16_t TS29 : 1; - __IO uint16_t TS30 : 1; - __IO uint16_t TS31 : 1; -} stc_adc_adss23_field_t; - -typedef struct stc_adc_adss2_field -{ - __IO uint8_t TS16 : 1; - __IO uint8_t TS17 : 1; - __IO uint8_t TS18 : 1; - __IO uint8_t TS19 : 1; - __IO uint8_t TS20 : 1; - __IO uint8_t TS21 : 1; - __IO uint8_t TS22 : 1; - __IO uint8_t TS23 : 1; -} stc_adc_adss2_field_t; - -typedef struct stc_adc_adss3_field -{ - __IO uint8_t TS24 : 1; - __IO uint8_t TS25 : 1; - __IO uint8_t TS26 : 1; - __IO uint8_t TS27 : 1; - __IO uint8_t TS28 : 1; - __IO uint8_t TS29 : 1; - __IO uint8_t TS30 : 1; - __IO uint8_t TS31 : 1; -} stc_adc_adss3_field_t; - -typedef struct stc_adc_adss01_field -{ - __IO uint16_t TS0 : 1; - __IO uint16_t TS1 : 1; - __IO uint16_t TS2 : 1; - __IO uint16_t TS3 : 1; - __IO uint16_t TS4 : 1; - __IO uint16_t TS5 : 1; - __IO uint16_t TS6 : 1; - __IO uint16_t TS7 : 1; - __IO uint16_t TS8 : 1; - __IO uint16_t TS9 : 1; - __IO uint16_t TS10 : 1; - __IO uint16_t TS11 : 1; - __IO uint16_t TS12 : 1; - __IO uint16_t TS13 : 1; - __IO uint16_t TS14 : 1; - __IO uint16_t TS15 : 1; -} stc_adc_adss01_field_t; - -typedef struct stc_adc_adss0_field -{ - __IO uint8_t TS0 : 1; - __IO uint8_t TS1 : 1; - __IO uint8_t TS2 : 1; - __IO uint8_t TS3 : 1; - __IO uint8_t TS4 : 1; - __IO uint8_t TS5 : 1; - __IO uint8_t TS6 : 1; - __IO uint8_t TS7 : 1; -} stc_adc_adss0_field_t; - -typedef struct stc_adc_adss1_field -{ - __IO uint8_t TS8 : 1; - __IO uint8_t TS9 : 1; - __IO uint8_t TS10 : 1; - __IO uint8_t TS11 : 1; - __IO uint8_t TS12 : 1; - __IO uint8_t TS13 : 1; - __IO uint8_t TS14 : 1; - __IO uint8_t TS15 : 1; -} stc_adc_adss1_field_t; - -typedef struct stc_adc_adst01_field -{ - __IO uint16_t ST10 : 1; - __IO uint16_t ST11 : 1; - __IO uint16_t ST12 : 1; - __IO uint16_t ST13 : 1; - __IO uint16_t ST14 : 1; - __IO uint16_t STX10 : 1; - __IO uint16_t STX11 : 1; - __IO uint16_t STX12 : 1; - __IO uint16_t ST00 : 1; - __IO uint16_t ST01 : 1; - __IO uint16_t ST02 : 1; - __IO uint16_t ST03 : 1; - __IO uint16_t ST04 : 1; - __IO uint16_t STX00 : 1; - __IO uint16_t STX01 : 1; - __IO uint16_t STX02 : 1; -} stc_adc_adst01_field_t; - -typedef struct stc_adc_adst1_field -{ - __IO uint8_t ST1 : 5; - __IO uint8_t STX1 : 3; -} stc_adc_adst1_field_t; - -typedef struct stc_adc_adst0_field -{ - __IO uint8_t ST0 : 5; - __IO uint8_t STX0 : 3; -} stc_adc_adst0_field_t; - -typedef struct stc_adc_adct_field -{ - __IO uint8_t CT0 : 1; - __IO uint8_t CT1 : 1; - __IO uint8_t CT2 : 1; -} stc_adc_adct_field_t; - -typedef struct stc_adc_prtsl_field -{ - __IO uint8_t PRTSL0 : 1; - __IO uint8_t PRTSL1 : 1; - __IO uint8_t PRTSL2 : 1; - __IO uint8_t PRTSL3 : 1; -} stc_adc_prtsl_field_t; - -typedef struct stc_adc_sctsl_field -{ - __IO uint8_t SCTSL0 : 1; - __IO uint8_t SCTSL1 : 1; - __IO uint8_t SCTSL2 : 1; - __IO uint8_t SCTSL3 : 1; -} stc_adc_sctsl_field_t; - -typedef struct stc_adc_adcen_field -{ - __IO uint16_t ENBL : 1; - __IO uint16_t READY : 1; - __IO uint16_t RESERVED : 6; - __IO uint16_t ENBLTIME : 8; -} stc_adc_adcen_field_t; - -typedef struct stc_adc_wcmpdh_field -{ - uint16_t RESERVED : 6; - __IO uint16_t CMHD : 10; -} stc_adc_wcmpdh_field_t; - -typedef struct stc_adc_wcmpcr_field -{ - uint8_t RESERVED : 2; - __IO uint8_t RCOE : 1; - __IO uint8_t RCOIE : 1; - __IO uint8_t RCOIRRS : 1; - __IO uint8_t RCOCD : 3; -} stc_adc_wcmpcr_field_t; - -typedef struct stc_adc_wcmpdl_field -{ - uint16_t RESERVED : 6; - __IO uint16_t CMLD : 10; -} stc_adc_wcmpdl_field_t; - -typedef struct stc_adc_wcmpsr_field -{ - __IO uint8_t WCCH : 5; - __IO uint8_t WCMD : 1; - __IO uint8_t RESERVED : 2; -} stc_adc_wcmpsr_field_t; - -typedef struct stc_adc_wcmrcot_field -{ - __IO uint32_t RCOOF : 1; - uint32_t RESERVED : 31; -} stc_adc_wcmrcot_field_t; - -typedef struct stc_adc_wcmrcif_field -{ - __IO uint32_t RCINT : 1; - uint32_t RESERVED : 31; -} stc_adc_wcmrcif_field_t; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CRTRIM_MODULE register bit fields */ -typedef struct stc_crtrim_mcr_psr_field -{ - __IO uint8_t CSR : 3; -} stc_crtrim_mcr_psr_field_t; - -typedef struct stc_crtrim_mcr_ftrm_field -{ - __IO uint16_t TRD :10; -} stc_crtrim_mcr_ftrm_field_t; - -typedef struct stc_crtrim_mcr_ttrm_field -{ - __IO uint8_t TRT : 5; -} stc_crtrim_mcr_ttrm_field_t; - -typedef struct stc_crtrim_mcr_rlr_field -{ - __IO uint32_t TRMLCK :32; -} stc_crtrim_mcr_rlr_field_t; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* EXTI_MODULE register bit fields */ -typedef struct stc_exti_enir_field -{ - __IO uint32_t EN0 : 1; - __IO uint32_t EN1 : 1; - __IO uint32_t EN2 : 1; - __IO uint32_t EN3 : 1; - __IO uint32_t EN4 : 1; - __IO uint32_t EN5 : 1; - __IO uint32_t EN6 : 1; - __IO uint32_t EN7 : 1; - __IO uint32_t EN8 : 1; - __IO uint32_t EN9 : 1; - __IO uint32_t EN10 : 1; - __IO uint32_t EN11 : 1; - __IO uint32_t EN12 : 1; - __IO uint32_t EN13 : 1; - __IO uint32_t EN14 : 1; - __IO uint32_t EN15 : 1; - __IO uint32_t EN16 : 1; - __IO uint32_t EN17 : 1; - __IO uint32_t EN18 : 1; - __IO uint32_t EN19 : 1; - __IO uint32_t EN20 : 1; - __IO uint32_t EN21 : 1; - __IO uint32_t EN22 : 1; - __IO uint32_t EN23 : 1; - __IO uint32_t EN24 : 1; - __IO uint32_t EN25 : 1; - __IO uint32_t EN26 : 1; - __IO uint32_t EN27 : 1; - __IO uint32_t EN28 : 1; - __IO uint32_t EN29 : 1; - __IO uint32_t EN30 : 1; - __IO uint32_t EN31 : 1; -} stc_exti_enir_field_t; - -typedef struct stc_exti_eirr_field -{ - __IO uint32_t ER0 : 1; - __IO uint32_t ER1 : 1; - __IO uint32_t ER2 : 1; - __IO uint32_t ER3 : 1; - __IO uint32_t ER4 : 1; - __IO uint32_t ER5 : 1; - __IO uint32_t ER6 : 1; - __IO uint32_t ER7 : 1; - __IO uint32_t ER8 : 1; - __IO uint32_t ER9 : 1; - __IO uint32_t ER10 : 1; - __IO uint32_t ER11 : 1; - __IO uint32_t ER12 : 1; - __IO uint32_t ER13 : 1; - __IO uint32_t ER14 : 1; - __IO uint32_t ER15 : 1; - __IO uint32_t ER16 : 1; - __IO uint32_t ER17 : 1; - __IO uint32_t ER18 : 1; - __IO uint32_t ER19 : 1; - __IO uint32_t ER20 : 1; - __IO uint32_t ER21 : 1; - __IO uint32_t ER22 : 1; - __IO uint32_t ER23 : 1; - __IO uint32_t ER24 : 1; - __IO uint32_t ER25 : 1; - __IO uint32_t ER26 : 1; - __IO uint32_t ER27 : 1; - __IO uint32_t ER28 : 1; - __IO uint32_t ER29 : 1; - __IO uint32_t ER30 : 1; - __IO uint32_t ER31 : 1; -} stc_exti_eirr_field_t; - -typedef struct stc_exti_eicl_field -{ - __IO uint32_t ECL0 : 1; - __IO uint32_t ECL1 : 1; - __IO uint32_t ECL2 : 1; - __IO uint32_t ECL3 : 1; - __IO uint32_t ECL4 : 1; - __IO uint32_t ECL5 : 1; - __IO uint32_t ECL6 : 1; - __IO uint32_t ECL7 : 1; - __IO uint32_t ECL8 : 1; - __IO uint32_t ECL9 : 1; - __IO uint32_t ECL10 : 1; - __IO uint32_t ECL11 : 1; - __IO uint32_t ECL12 : 1; - __IO uint32_t ECL13 : 1; - __IO uint32_t ECL14 : 1; - __IO uint32_t ECL15 : 1; - __IO uint32_t ECL16 : 1; - __IO uint32_t ECL17 : 1; - __IO uint32_t ECL18 : 1; - __IO uint32_t ECL19 : 1; - __IO uint32_t ECL20 : 1; - __IO uint32_t ECL21 : 1; - __IO uint32_t ECL22 : 1; - __IO uint32_t ECL23 : 1; - __IO uint32_t ECL24 : 1; - __IO uint32_t ECL25 : 1; - __IO uint32_t ECL26 : 1; - __IO uint32_t ECL27 : 1; - __IO uint32_t ECL28 : 1; - __IO uint32_t ECL29 : 1; - __IO uint32_t ECL30 : 1; - __IO uint32_t ECL31 : 1; -} stc_exti_eicl_field_t; - -typedef struct stc_exti_elvr_field -{ - __IO uint32_t LA0 : 1; - __IO uint32_t LB0 : 1; - __IO uint32_t LA1 : 1; - __IO uint32_t LB1 : 1; - __IO uint32_t LA2 : 1; - __IO uint32_t LB2 : 1; - __IO uint32_t LA3 : 1; - __IO uint32_t LB3 : 1; - __IO uint32_t LA4 : 1; - __IO uint32_t LB4 : 1; - __IO uint32_t LA5 : 1; - __IO uint32_t LB5 : 1; - __IO uint32_t LA6 : 1; - __IO uint32_t LB6 : 1; - __IO uint32_t LA7 : 1; - __IO uint32_t LB7 : 1; - __IO uint32_t LA8 : 1; - __IO uint32_t LB8 : 1; - __IO uint32_t LA9 : 1; - __IO uint32_t LB9 : 1; - __IO uint32_t LA10 : 1; - __IO uint32_t LB10 : 1; - __IO uint32_t LA11 : 1; - __IO uint32_t LB11 : 1; - __IO uint32_t LA12 : 1; - __IO uint32_t LB12 : 1; - __IO uint32_t LA13 : 1; - __IO uint32_t LB13 : 1; - __IO uint32_t LA14 : 1; - __IO uint32_t LB14 : 1; - __IO uint32_t LA15 : 1; - __IO uint32_t LB15 : 1; -} stc_exti_elvr_field_t; - -typedef struct stc_exti_elvr1_field -{ - __IO uint32_t LA16 : 1; - __IO uint32_t LB16 : 1; - __IO uint32_t LA17 : 1; - __IO uint32_t LB17 : 1; - __IO uint32_t LA18 : 1; - __IO uint32_t LB18 : 1; - __IO uint32_t LA19 : 1; - __IO uint32_t LB19 : 1; - __IO uint32_t LA20 : 1; - __IO uint32_t LB20 : 1; - __IO uint32_t LA21 : 1; - __IO uint32_t LB21 : 1; - __IO uint32_t LA22 : 1; - __IO uint32_t LB22 : 1; - __IO uint32_t LA23 : 1; - __IO uint32_t LB23 : 1; - __IO uint32_t LA24 : 1; - __IO uint32_t LB24 : 1; - __IO uint32_t LA25 : 1; - __IO uint32_t LB25 : 1; - __IO uint32_t LA26 : 1; - __IO uint32_t LB26 : 1; - __IO uint32_t LA27 : 1; - __IO uint32_t LB27 : 1; - __IO uint32_t LA28 : 1; - __IO uint32_t LB28 : 1; - __IO uint32_t LA29 : 1; - __IO uint32_t LB29 : 1; - __IO uint32_t LA30 : 1; - __IO uint32_t LB30 : 1; - __IO uint32_t LA31 : 1; - __IO uint32_t LB31 : 1; -} stc_exti_elvr1_field_t; - -typedef struct stc_exti_nmirr_field -{ - __IO uint8_t NR : 1; -} stc_exti_nmirr_field_t; - -typedef struct stc_exti_nmicl_field -{ - __IO uint8_t NCL : 1; -} stc_exti_nmicl_field_t; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* INTREQ_MODULE register bit fields */ -typedef struct stc_intreq_drqsel_field -{ - __IO uint32_t DRQSEL0 : 1; - __IO uint32_t DRQSEL1 : 1; - __IO uint32_t DRQSEL2 : 1; - __IO uint32_t DRQSEL3 : 1; - __IO uint32_t DRQSEL4 : 1; - __IO uint32_t DRQSEL5 : 1; - __IO uint32_t DRQSEL6 : 1; - __IO uint32_t DRQSEL7 : 1; - __IO uint32_t DRQSEL8 : 1; - __IO uint32_t DRQSEL9 : 1; - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; - __IO uint32_t DRQSEL15 : 1; - __IO uint32_t DRQSEL16 : 1; - __IO uint32_t DRQSEL17 : 1; - __IO uint32_t DRQSEL18 : 1; - __IO uint32_t DRQSEL19 : 1; - __IO uint32_t DRQSEL20 : 1; - __IO uint32_t DRQSEL21 : 1; - __IO uint32_t DRQSEL22 : 1; - __IO uint32_t DRQSEL23 : 1; - __IO uint32_t DRQSEL24 : 1; - __IO uint32_t DRQSEL25 : 1; - __IO uint32_t DRQSEL26 : 1; - __IO uint32_t DRQSEL27 : 1; - __IO uint32_t DRQSEL28 : 1; - __IO uint32_t DRQSEL29 : 1; - __IO uint32_t DRQSEL30 : 1; - __IO uint32_t DRQSEL31 : 1; -} stc_intreq_drqsel_field_t; - -typedef struct stc_intreq_oddpks_field -{ - __IO uint8_t ODDPKS0 : 1; - __IO uint8_t ODDPKS1 : 1; - __IO uint8_t ODDPKS2 : 1; - __IO uint8_t ODDPKS3 : 1; - __IO uint8_t ODDPKS4 : 1; -} stc_intreq_oddpks_field_t; - -typedef struct stc_intreq_irq003sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq003sel_field_t; - -typedef struct stc_intreq_irq004sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq004sel_field_t; - -typedef struct stc_intreq_irq005sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq005sel_field_t; - -typedef struct stc_intreq_irq006sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq006sel_field_t; - -typedef struct stc_intreq_irq007sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq007sel_field_t; - -typedef struct stc_intreq_irq008sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq008sel_field_t; - -typedef struct stc_intreq_irq009sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq009sel_field_t; - -typedef struct stc_intreq_irq010sel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED8 : 8; - __IO uint32_t SELBIT : 8; -} stc_intreq_irq010sel_field_t; - -typedef struct stc_intreq_exc02mon_field -{ - __IO uint32_t NMI : 1; - __IO uint32_t HWINT : 1; -} stc_intreq_exc02mon_field_t; - -typedef struct stc_intreq_irq000mon_field -{ - __IO uint32_t FCSINT : 1; -} stc_intreq_irq000mon_field_t; - -typedef struct stc_intreq_irq001mon_field -{ - __IO uint32_t SWWDTINT : 1; -} stc_intreq_irq001mon_field_t; - -typedef struct stc_intreq_irq002mon_field -{ - __IO uint32_t LVDINT : 1; -} stc_intreq_irq002mon_field_t; - -typedef struct stc_intreq_irq003mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq003mon_field_t; - -typedef struct stc_intreq_irq004mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq004mon_field_t; - -typedef struct stc_intreq_irq005mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq005mon_field_t; - -typedef struct stc_intreq_irq006mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq006mon_field_t; - -typedef struct stc_intreq_irq007mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq007mon_field_t; - -typedef struct stc_intreq_irq008mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq008mon_field_t; - -typedef struct stc_intreq_irq009mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq009mon_field_t; - -typedef struct stc_intreq_irq010mon_field -{ - __IO uint32_t IRQBIT0 : 1; - __IO uint32_t IRQBIT1 : 1; - __IO uint32_t IRQBIT2 : 1; - __IO uint32_t IRQBIT3 : 1; - __IO uint32_t IRQBIT4 : 1; - __IO uint32_t IRQBIT5 : 1; - __IO uint32_t IRQBIT6 : 1; - __IO uint32_t IRQBIT7 : 1; -} stc_intreq_irq010mon_field_t; - -typedef struct stc_intreq_irq011mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq011mon_field_t; - -typedef struct stc_intreq_irq012mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq012mon_field_t; - -typedef struct stc_intreq_irq013mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq013mon_field_t; - -typedef struct stc_intreq_irq014mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq014mon_field_t; - -typedef struct stc_intreq_irq015mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq015mon_field_t; - -typedef struct stc_intreq_irq016mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq016mon_field_t; - -typedef struct stc_intreq_irq017mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq017mon_field_t; - -typedef struct stc_intreq_irq018mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq018mon_field_t; - -typedef struct stc_intreq_irq019mon_field -{ - __IO uint32_t QUDINT0 : 1; - __IO uint32_t QUDINT1 : 1; - __IO uint32_t QUDINT2 : 1; - __IO uint32_t QUDINT3 : 1; - __IO uint32_t QUDINT4 : 1; - __IO uint32_t QUDINT5 : 1; -} stc_intreq_irq019mon_field_t; - -typedef struct stc_intreq_irq020mon_field -{ - __IO uint32_t QUDINT0 : 1; - __IO uint32_t QUDINT1 : 1; - __IO uint32_t QUDINT2 : 1; - __IO uint32_t QUDINT3 : 1; - __IO uint32_t QUDINT4 : 1; - __IO uint32_t QUDINT5 : 1; -} stc_intreq_irq020mon_field_t; - -typedef struct stc_intreq_irq021mon_field -{ - __IO uint32_t WAVEINT0 : 1; - __IO uint32_t WAVEINT1 : 1; - __IO uint32_t WAVEINT2 : 1; - __IO uint32_t WAVEINT3 : 1; -} stc_intreq_irq021mon_field_t; - -typedef struct stc_intreq_irq022mon_field -{ - __IO uint32_t WAVEINT0 : 1; - __IO uint32_t WAVEINT1 : 1; - __IO uint32_t WAVEINT2 : 1; - __IO uint32_t WAVEINT3 : 1; -} stc_intreq_irq022mon_field_t; - -typedef struct stc_intreq_irq023mon_field -{ - __IO uint32_t WAVEINT0 : 1; - __IO uint32_t WAVEINT1 : 1; - __IO uint32_t WAVEINT2 : 1; - __IO uint32_t WAVEINT3 : 1; -} stc_intreq_irq023mon_field_t; - -typedef struct stc_intreq_irq024mon_field -{ - __IO uint32_t FRT_PEAK_INT0: 1; - __IO uint32_t FRT_PEAK_INT1: 1; - __IO uint32_t FRT_PEAK_INT2: 1; -} stc_intreq_irq024mon_field_t; - -typedef struct stc_intreq_irq025mon_field -{ - __IO uint32_t FRT_ZERO_INT0: 1; - __IO uint32_t FRT_ZERO_INT1: 1; - __IO uint32_t FRT_ZERO_INT2: 1; -} stc_intreq_irq025mon_field_t; - -typedef struct stc_intreq_irq026mon_field -{ - __IO uint32_t ICUINT0 : 1; - __IO uint32_t ICUINT1 : 1; - __IO uint32_t ICUINT2 : 1; - __IO uint32_t ICUINT3 : 1; -} stc_intreq_irq026mon_field_t; - -typedef struct stc_intreq_irq027mon_field -{ - __IO uint32_t OCUINT0 : 1; - __IO uint32_t OCUINT1 : 1; - __IO uint32_t OCUINT2 : 1; - __IO uint32_t OCUINT3 : 1; - __IO uint32_t OCUINT4 : 1; - __IO uint32_t OCUINT5 : 1; -} stc_intreq_irq027mon_field_t; - -typedef struct stc_intreq_irq028mon_field -{ - __IO uint32_t FRT_PEAK_INT0: 1; - __IO uint32_t FRT_PEAK_INT1: 1; - __IO uint32_t FRT_PEAK_INT2: 1; -} stc_intreq_irq028mon_field_t; - -typedef struct stc_intreq_irq029mon_field -{ - __IO uint32_t FRT_ZERO_INT0: 1; - __IO uint32_t FRT_ZERO_INT1: 1; - __IO uint32_t FRT_ZERO_INT2: 1; -} stc_intreq_irq029mon_field_t; - -typedef struct stc_intreq_irq030mon_field -{ - __IO uint32_t ICUINT0 : 1; - __IO uint32_t ICUINT1 : 1; - __IO uint32_t ICUINT2 : 1; - __IO uint32_t ICUINT3 : 1; -} stc_intreq_irq030mon_field_t; - -typedef struct stc_intreq_irq031mon_field -{ - __IO uint32_t OCUINT0 : 1; - __IO uint32_t OCUINT1 : 1; - __IO uint32_t OCUINT2 : 1; - __IO uint32_t OCUINT3 : 1; - __IO uint32_t OCUINT4 : 1; - __IO uint32_t OCUINT5 : 1; -} stc_intreq_irq031mon_field_t; - -typedef struct stc_intreq_irq032mon_field -{ - __IO uint32_t FRT_PEAK_INT0: 1; - __IO uint32_t FRT_PEAK_INT1: 1; - __IO uint32_t FRT_PEAK_INT2: 1; -} stc_intreq_irq032mon_field_t; - -typedef struct stc_intreq_irq033mon_field -{ - __IO uint32_t FRT_ZERO_INT0: 1; - __IO uint32_t FRT_ZERO_INT1: 1; - __IO uint32_t FRT_ZERO_INT2: 1; -} stc_intreq_irq033mon_field_t; - -typedef struct stc_intreq_irq034mon_field -{ - __IO uint32_t ICUINT0 : 1; - __IO uint32_t ICUINT1 : 1; - __IO uint32_t ICUINT2 : 1; - __IO uint32_t ICUINT3 : 1; -} stc_intreq_irq034mon_field_t; - -typedef struct stc_intreq_irq035mon_field -{ - __IO uint32_t OCUINT0 : 1; - __IO uint32_t OCUINT1 : 1; - __IO uint32_t OCUINT2 : 1; - __IO uint32_t OCUINT3 : 1; - __IO uint32_t OCUINT4 : 1; - __IO uint32_t OCUINT5 : 1; -} stc_intreq_irq035mon_field_t; - -typedef struct stc_intreq_irq036mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; -} stc_intreq_irq036mon_field_t; - -typedef struct stc_intreq_irq037mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; -} stc_intreq_irq037mon_field_t; - -typedef struct stc_intreq_irq038mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; -} stc_intreq_irq038mon_field_t; - -typedef struct stc_intreq_irq039mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq039mon_field_t; - -typedef struct stc_intreq_irq040mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq040mon_field_t; - -typedef struct stc_intreq_irq041mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq041mon_field_t; - -typedef struct stc_intreq_irq042mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq042mon_field_t; - -typedef struct stc_intreq_irq043mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq043mon_field_t; - -typedef struct stc_intreq_irq044mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq044mon_field_t; - -typedef struct stc_intreq_irq045mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq045mon_field_t; - -typedef struct stc_intreq_irq046mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq046mon_field_t; - -typedef struct stc_intreq_irq047mon_field -{ - __IO uint32_t TIMINT1 : 1; - __IO uint32_t TIMINT2 : 1; -} stc_intreq_irq047mon_field_t; - -typedef struct stc_intreq_irq048mon_field -{ - __IO uint32_t WCINT : 1; -} stc_intreq_irq048mon_field_t; - -typedef struct stc_intreq_irq049mon_field -{ - __IO uint32_t BMEMCS : 1; -} stc_intreq_irq049mon_field_t; - -typedef struct stc_intreq_irq050mon_field -{ - __IO uint32_t RTCINT : 1; -} stc_intreq_irq050mon_field_t; - -typedef struct stc_intreq_irq051mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq051mon_field_t; - -typedef struct stc_intreq_irq052mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq052mon_field_t; - -typedef struct stc_intreq_irq053mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq053mon_field_t; - -typedef struct stc_intreq_irq054mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq054mon_field_t; - -typedef struct stc_intreq_irq055mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq055mon_field_t; - -typedef struct stc_intreq_irq056mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq056mon_field_t; - -typedef struct stc_intreq_irq057mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq057mon_field_t; - -typedef struct stc_intreq_irq058mon_field -{ - __IO uint32_t EXTINT : 1; -} stc_intreq_irq058mon_field_t; - -typedef struct stc_intreq_irq059mon_field -{ - __IO uint32_t MOSCINT : 1; - __IO uint32_t SOSCINT : 1; - __IO uint32_t MPLLINT : 1; - __IO uint32_t UPLLINT : 1; -} stc_intreq_irq059mon_field_t; - -typedef struct stc_intreq_irq060mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq060mon_field_t; - -typedef struct stc_intreq_irq061mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq061mon_field_t; - -typedef struct stc_intreq_irq062mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq062mon_field_t; - -typedef struct stc_intreq_irq063mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq063mon_field_t; - -typedef struct stc_intreq_irq064mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq064mon_field_t; - -typedef struct stc_intreq_irq065mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq065mon_field_t; - -typedef struct stc_intreq_irq066mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq066mon_field_t; - -typedef struct stc_intreq_irq067mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq067mon_field_t; - -typedef struct stc_intreq_irq068mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq068mon_field_t; - -typedef struct stc_intreq_irq069mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq069mon_field_t; - -typedef struct stc_intreq_irq070mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq070mon_field_t; - -typedef struct stc_intreq_irq071mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq071mon_field_t; - -typedef struct stc_intreq_irq072mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq072mon_field_t; - -typedef struct stc_intreq_irq073mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq073mon_field_t; - -typedef struct stc_intreq_irq074mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq074mon_field_t; - -typedef struct stc_intreq_irq075mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq075mon_field_t; - -typedef struct stc_intreq_irq076mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; - __IO uint32_t ADCINT4 : 1; -} stc_intreq_irq076mon_field_t; - -typedef struct stc_intreq_irq077mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; - __IO uint32_t ADCINT4 : 1; -} stc_intreq_irq077mon_field_t; - -typedef struct stc_intreq_irq078mon_field -{ - __IO uint32_t USB_DRQ_INT0: 1; - __IO uint32_t USB_DRQ_INT1: 1; - __IO uint32_t USB_DRQ_INT2: 1; - __IO uint32_t USB_DRQ_INT3: 1; - __IO uint32_t USB_DRQ_INT4: 1; -} stc_intreq_irq078mon_field_t; - -typedef struct stc_intreq_irq079mon_field -{ - __IO uint32_t USB_INT0 : 1; - __IO uint32_t USB_INT1 : 1; - __IO uint32_t USB_INT2 : 1; - __IO uint32_t USB_INT3 : 1; - __IO uint32_t USB_INT4 : 1; - __IO uint32_t USB_INT5 : 1; -} stc_intreq_irq079mon_field_t; - -typedef struct stc_intreq_irq080mon_field -{ - __IO uint32_t CANINT : 1; -} stc_intreq_irq080mon_field_t; - -typedef struct stc_intreq_irq081mon_field -{ - __IO uint32_t CANINT : 1; -} stc_intreq_irq081mon_field_t; - -typedef struct stc_intreq_irq082mon_field -{ - __IO uint32_t MACSBD : 1; - __IO uint32_t MACPMT : 1; - __IO uint32_t MACLPI : 1; -} stc_intreq_irq082mon_field_t; - -typedef struct stc_intreq_irq083mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq083mon_field_t; - -typedef struct stc_intreq_irq084mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq084mon_field_t; - -typedef struct stc_intreq_irq085mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq085mon_field_t; - -typedef struct stc_intreq_irq086mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq086mon_field_t; - -typedef struct stc_intreq_irq087mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq087mon_field_t; - -typedef struct stc_intreq_irq088mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq088mon_field_t; - -typedef struct stc_intreq_irq089mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq089mon_field_t; - -typedef struct stc_intreq_irq090mon_field -{ - __IO uint32_t DMACINT : 1; -} stc_intreq_irq090mon_field_t; - -typedef struct stc_intreq_irq091mon_field -{ - __IO uint32_t DSTCINT0 : 1; - __IO uint32_t DSTCINT1 : 1; -} stc_intreq_irq091mon_field_t; - -typedef struct stc_intreq_irq092mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; -} stc_intreq_irq092mon_field_t; - -typedef struct stc_intreq_irq093mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; -} stc_intreq_irq093mon_field_t; - -typedef struct stc_intreq_irq094mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; -} stc_intreq_irq094mon_field_t; - -typedef struct stc_intreq_irq095mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; -} stc_intreq_irq095mon_field_t; - -typedef struct stc_intreq_irq096mon_field -{ - __IO uint32_t QUDINT0 : 1; - __IO uint32_t QUDINT1 : 1; - __IO uint32_t QUDINT2 : 1; - __IO uint32_t QUDINT3 : 1; - __IO uint32_t QUDINT4 : 1; - __IO uint32_t QUDINT5 : 1; -} stc_intreq_irq096mon_field_t; - -typedef struct stc_intreq_irq097mon_field -{ - __IO uint32_t QUDINT0 : 1; - __IO uint32_t QUDINT1 : 1; - __IO uint32_t QUDINT2 : 1; - __IO uint32_t QUDINT3 : 1; - __IO uint32_t QUDINT4 : 1; - __IO uint32_t QUDINT5 : 1; -} stc_intreq_irq097mon_field_t; - -typedef struct stc_intreq_irq098mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq098mon_field_t; - -typedef struct stc_intreq_irq099mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq099mon_field_t; - -typedef struct stc_intreq_irq100mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq100mon_field_t; - -typedef struct stc_intreq_irq101mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; -} stc_intreq_irq101mon_field_t; - -typedef struct stc_intreq_irq102mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; -} stc_intreq_irq102mon_field_t; - -typedef struct stc_intreq_irq103mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq103mon_field_t; - -typedef struct stc_intreq_irq104mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq104mon_field_t; - -typedef struct stc_intreq_irq105mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq105mon_field_t; - -typedef struct stc_intreq_irq106mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq106mon_field_t; - -typedef struct stc_intreq_irq107mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq107mon_field_t; - -typedef struct stc_intreq_irq108mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq108mon_field_t; - -typedef struct stc_intreq_irq109mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq109mon_field_t; - -typedef struct stc_intreq_irq110mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq110mon_field_t; - -typedef struct stc_intreq_irq111mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; - __IO uint32_t ADCINT4 : 1; -} stc_intreq_irq111mon_field_t; - -typedef struct stc_intreq_irq113mon_field -{ - __IO uint32_t USB_DRQ_INT0: 1; - __IO uint32_t USB_DRQ_INT1: 1; - __IO uint32_t USB_DRQ_INT2: 1; - __IO uint32_t USB_DRQ_INT3: 1; - __IO uint32_t USB_DRQ_INT4: 1; -} stc_intreq_irq113mon_field_t; - -typedef struct stc_intreq_irq114mon_field -{ - __IO uint32_t USB_INT0 : 1; - __IO uint32_t USB_INT1 : 1; - __IO uint32_t USB_INT2 : 1; - __IO uint32_t USB_INT3 : 1; - __IO uint32_t USB_INT4 : 1; - __IO uint32_t USB_INT5 : 1; -} stc_intreq_irq114mon_field_t; - -typedef struct stc_intreq_irq118mon_field -{ - __IO uint32_t SDINT0 : 1; - __IO uint32_t SDINT1 : 1; -} stc_intreq_irq118mon_field_t; - -typedef struct stc_intreq_irq119mon_field -{ - __IO uint32_t FLINT : 1; -} stc_intreq_irq119mon_field_t; - -typedef struct stc_intreq_irq120mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq120mon_field_t; - -typedef struct stc_intreq_irq121mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq121mon_field_t; - -typedef struct stc_intreq_irq122mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq122mon_field_t; - -typedef struct stc_intreq_irq123mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq123mon_field_t; - -typedef struct stc_intreq_irq124mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq124mon_field_t; - -typedef struct stc_intreq_irq125mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq125mon_field_t; - -typedef struct stc_intreq_irq126mon_field -{ - __IO uint32_t MFSRINT : 1; -} stc_intreq_irq126mon_field_t; - -typedef struct stc_intreq_irq127mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq127mon_field_t; - -/****************************************************************************** - * IRQSEL_MODULE -******************************************************************************/ -typedef struct stc_irqsel_field -{ - __IO uint32_t SELIRQ : 8; - uint32_t RESERVED0 : 8; - __IO uint32_t SELBIT : 8; - uint32_t RESERVED1 : 8; -} stc_irqsel_field_t; - -/****************************************************************************** - * DSTC_MODULE - ******************************************************************************/ -/* DSTC_MODULE register bit fields */ -typedef struct stc_dstc_hwdesp_field -{ - __IO uint32_t CHANNEL : 8; - uint32_t RESERVED1 : 8; - __IO uint32_t HWDESP : 14; - uint32_t RESERVED2 : 2; -} stc_dstc_hwdesp_field_t; - -typedef struct stc_dstc_cfg_field -{ - __IO uint8_t SWINTE : 1; - __IO uint8_t ERINTE : 1; - __IO uint8_t RBDIS : 1; - __IO uint8_t ESTE : 1; - __IO uint8_t SWPR : 3; - uint8_t RESERVED : 1; -} stc_dstc_cfg_field_t; - -typedef struct stc_dstc_swtr_field -{ - __IO uint16_t SWDESP : 14; - __IO uint16_t SWREQ : 1; - __IO uint16_t SWST : 1; -} stc_dstc_swtr_field_t; - -typedef struct stc_dstc_moners_field -{ - __IO uint32_t EST : 3; - __IO uint32_t DER : 1; - __IO uint32_t ESTOP : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t EHS : 1; - __IO uint32_t RESERVED2 : 1; - __IO uint32_t ECH : 8; - __IO uint32_t EDESP : 14; - uint32_t RESERVED3 : 2; -} stc_dstc_moners_field_t; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* GPIO_MODULE register bit fields */ -typedef struct stc_gpio_pfr0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; -} stc_gpio_pfr0_field_t; - -typedef struct stc_gpio_pfr1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_pfr1_field_t; - -typedef struct stc_gpio_pfr2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_pfr2_field_t; - -typedef struct stc_gpio_pfr3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_pfr3_field_t; - -typedef struct stc_gpio_pfr4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_pfr4_field_t; - -typedef struct stc_gpio_pfr5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_pfr5_field_t; - -typedef struct stc_gpio_pfr6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_pfr6_field_t; - -typedef struct stc_gpio_pfr7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_pfr7_field_t; - -typedef struct stc_gpio_pfr8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_pfr8_field_t; - -typedef struct stc_gpio_pfre_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_pfre_field_t; - -typedef struct stc_gpio_pcr0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; -} stc_gpio_pcr0_field_t; - -typedef struct stc_gpio_pcr1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_pcr1_field_t; - -typedef struct stc_gpio_pcr2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_pcr2_field_t; - -typedef struct stc_gpio_pcr3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_pcr3_field_t; - -typedef struct stc_gpio_pcr4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_pcr4_field_t; - -typedef struct stc_gpio_pcr5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_pcr5_field_t; - -typedef struct stc_gpio_pcr6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_pcr6_field_t; - -typedef struct stc_gpio_pcr7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_pcr7_field_t; - -typedef struct stc_gpio_pcr8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_pcr8_field_t; - -typedef struct stc_gpio_pcre_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_pcre_field_t; - -typedef struct stc_gpio_ddr0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; - __IO uint32_t P0F : 1; -} stc_gpio_ddr0_field_t; - -typedef struct stc_gpio_ddr1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_ddr1_field_t; - -typedef struct stc_gpio_ddr2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_ddr2_field_t; - -typedef struct stc_gpio_ddr3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_ddr3_field_t; - -typedef struct stc_gpio_ddr4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_ddr4_field_t; - -typedef struct stc_gpio_ddr5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_ddr5_field_t; - -typedef struct stc_gpio_ddr6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_ddr6_field_t; - -typedef struct stc_gpio_ddr7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_ddr7_field_t; - -typedef struct stc_gpio_ddr8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_ddr8_field_t; - -typedef struct stc_gpio_ddre_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_ddre_field_t; - -typedef struct stc_gpio_pdir0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; - __IO uint32_t P0F : 1; -} stc_gpio_pdir0_field_t; - -typedef struct stc_gpio_pdir1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_pdir1_field_t; - -typedef struct stc_gpio_pdir2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_pdir2_field_t; - -typedef struct stc_gpio_pdir3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_pdir3_field_t; - -typedef struct stc_gpio_pdir4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_pdir4_field_t; - -typedef struct stc_gpio_pdir5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_pdir5_field_t; - -typedef struct stc_gpio_pdir6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_pdir6_field_t; - -typedef struct stc_gpio_pdir7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_pdir7_field_t; - -typedef struct stc_gpio_pdir8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_pdir8_field_t; - -typedef struct stc_gpio_pdire_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_pdire_field_t; - -typedef struct stc_gpio_pdor0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; - __IO uint32_t P0F : 1; -} stc_gpio_pdor0_field_t; - -typedef struct stc_gpio_pdor1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_pdor1_field_t; - -typedef struct stc_gpio_pdor2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_pdor2_field_t; - -typedef struct stc_gpio_pdor3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_pdor3_field_t; - -typedef struct stc_gpio_pdor4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_pdor4_field_t; - -typedef struct stc_gpio_pdor5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_pdor5_field_t; - -typedef struct stc_gpio_pdor6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_pdor6_field_t; - -typedef struct stc_gpio_pdor7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_pdor7_field_t; - -typedef struct stc_gpio_pdor8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_pdor8_field_t; - -typedef struct stc_gpio_pdore_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_pdore_field_t; - -typedef struct stc_gpio_ade_field -{ - __IO uint32_t AN00 : 1; - __IO uint32_t AN01 : 1; - __IO uint32_t AN02 : 1; - __IO uint32_t AN03 : 1; - __IO uint32_t AN04 : 1; - __IO uint32_t AN05 : 1; - __IO uint32_t AN06 : 1; - __IO uint32_t AN07 : 1; - __IO uint32_t AN08 : 1; - __IO uint32_t AN09 : 1; - __IO uint32_t AN10 : 1; - __IO uint32_t AN11 : 1; - __IO uint32_t AN12 : 1; - __IO uint32_t AN13 : 1; - __IO uint32_t AN14 : 1; - __IO uint32_t AN15 : 1; - __IO uint32_t AN16 : 1; - __IO uint32_t AN17 : 1; - __IO uint32_t AN18 : 1; - __IO uint32_t AN19 : 1; - __IO uint32_t AN20 : 1; - __IO uint32_t AN21 : 1; - __IO uint32_t AN22 : 1; - __IO uint32_t AN23 : 1; - __IO uint32_t AN24 : 1; - __IO uint32_t AN25 : 1; - __IO uint32_t AN26 : 1; - __IO uint32_t AN27 : 1; - __IO uint32_t AN28 : 1; - __IO uint32_t AN29 : 1; - __IO uint32_t AN30 : 1; - __IO uint32_t AN31 : 1; -} stc_gpio_ade_field_t; - -typedef struct stc_gpio_spsr_field -{ - uint32_t RESERVED0 : 2; - __IO uint32_t MAINXC : 2; - __IO uint32_t USB0C : 1; - __IO uint32_t USB1C : 1; -} stc_gpio_spsr_field_t; - -typedef struct stc_gpio_epfr00_field -{ - __IO uint32_t NMIS : 1; - __IO uint32_t CROUTE : 2; - uint32_t RESERVED3 : 1; - __IO uint32_t RTCCOE : 2; - __IO uint32_t SUBOUTE : 2; - uint32_t RESERVED8 : 1; - __IO uint32_t USBP0E : 1; - uint32_t RESERVED10 : 3; - __IO uint32_t USBP1E : 1; - uint32_t RESERVED14 : 2; - __IO uint32_t JTAGEN0B : 1; - __IO uint32_t JTAGEN1S : 1; - uint32_t RESERVED18 : 6; - __IO uint32_t TRC0E : 1; - __IO uint32_t TRC1E : 1; -} stc_gpio_epfr00_field_t; - -typedef struct stc_gpio_epfr01_field -{ - __IO uint32_t RTO00E : 2; - __IO uint32_t RTO01E : 2; - __IO uint32_t RTO02E : 2; - __IO uint32_t RTO03E : 2; - __IO uint32_t RTO04E : 2; - __IO uint32_t RTO05E : 2; - __IO uint32_t DTTI0C : 1; - uint32_t RESERVED13 : 3; - __IO uint32_t DTTI0S : 2; - __IO uint32_t FRCK0S : 2; - __IO uint32_t IC00S : 3; - __IO uint32_t IC01S : 3; - __IO uint32_t IC02S : 3; - __IO uint32_t IC03S : 3; -} stc_gpio_epfr01_field_t; - -typedef struct stc_gpio_epfr02_field -{ - __IO uint32_t RTO10E : 2; - __IO uint32_t RTO11E : 2; - __IO uint32_t RTO12E : 2; - __IO uint32_t RTO13E : 2; - __IO uint32_t RTO14E : 2; - __IO uint32_t RTO15E : 2; - __IO uint32_t DTTI1C : 1; - uint32_t RESERVED13 : 3; - __IO uint32_t DTTI1S : 2; - __IO uint32_t FRCK1S : 2; - __IO uint32_t IC10S : 3; - __IO uint32_t IC11S : 3; - __IO uint32_t IC12S : 3; - __IO uint32_t IC13S : 3; -} stc_gpio_epfr02_field_t; - -typedef struct stc_gpio_epfr03_field -{ - __IO uint32_t RTO20E : 2; - __IO uint32_t RTO21E : 2; - __IO uint32_t RTO22E : 2; - __IO uint32_t RTO23E : 2; - __IO uint32_t RTO24E : 2; - __IO uint32_t RTO25E : 2; - __IO uint32_t DTTI2C : 1; - uint32_t RESERVED13 : 3; - __IO uint32_t DTTI2S : 2; - __IO uint32_t FRCK2S : 2; - __IO uint32_t IC20S : 3; - __IO uint32_t IC21S : 3; - __IO uint32_t IC22S : 3; - __IO uint32_t IC23S : 3; -} stc_gpio_epfr03_field_t; - -typedef struct stc_gpio_epfr04_field -{ - uint32_t RESERVED0 : 2; - __IO uint32_t TIOA0E : 2; - __IO uint32_t TIOB0S : 3; - uint32_t RESERVED7 : 1; - __IO uint32_t TIOA1S : 2; - __IO uint32_t TIOA1E : 2; - __IO uint32_t TIOB1S : 2; - uint32_t RESERVED14 : 4; - __IO uint32_t TIOA2E : 2; - __IO uint32_t TIOB2S : 2; - uint32_t RESERVED22 : 2; - __IO uint32_t TIOA3S : 2; - __IO uint32_t TIOA3E : 2; - __IO uint32_t TIOB3S : 2; -} stc_gpio_epfr04_field_t; - -typedef struct stc_gpio_epfr05_field -{ - uint32_t RESERVED0 : 2; - __IO uint32_t TIOA4E : 2; - __IO uint32_t TIOB4S : 2; - uint32_t RESERVED6 : 2; - __IO uint32_t TIOA5S : 2; - __IO uint32_t TIOA5E : 2; - __IO uint32_t TIOB5S : 2; - uint32_t RESERVED14 : 4; - __IO uint32_t TIOA6E : 2; - __IO uint32_t TIOB6S : 2; - uint32_t RESERVED22 : 2; - __IO uint32_t TIOA7S : 2; - __IO uint32_t TIOA7E : 2; - __IO uint32_t TIOB7S : 2; -} stc_gpio_epfr05_field_t; - -typedef struct stc_gpio_epfr06_field -{ - __IO uint32_t EINT00S : 2; - __IO uint32_t EINT01S : 2; - __IO uint32_t EINT02S : 2; - __IO uint32_t EINT03S : 2; - __IO uint32_t EINT04S : 2; - __IO uint32_t EINT05S : 2; - __IO uint32_t EINT06S : 2; - __IO uint32_t EINT07S : 2; - __IO uint32_t EINT08S : 2; - __IO uint32_t EINT09S : 2; - __IO uint32_t EINT10S : 2; - __IO uint32_t EINT11S : 2; - __IO uint32_t EINT12S : 2; - __IO uint32_t EINT13S : 2; - __IO uint32_t EINT14S : 2; - __IO uint32_t EINT15S : 2; -} stc_gpio_epfr06_field_t; - -typedef struct stc_gpio_epfr07_field -{ - uint32_t RESERVED0 : 4; - __IO uint32_t SIN0S : 2; - __IO uint32_t SOT0B : 2; - __IO uint32_t SCK0B : 2; - __IO uint32_t SIN1S : 2; - __IO uint32_t SOT1B : 2; - __IO uint32_t SCK1B : 2; - __IO uint32_t SIN2S : 2; - __IO uint32_t SOT2B : 2; - __IO uint32_t SCK2B : 2; - __IO uint32_t SIN3S : 2; - __IO uint32_t SOT3B : 2; - __IO uint32_t SCK3B : 2; -} stc_gpio_epfr07_field_t; - -typedef struct stc_gpio_epfr08_field -{ - __IO uint32_t RTS4E : 2; - __IO uint32_t CTS4S : 2; - __IO uint32_t SIN4S : 2; - __IO uint32_t SOT4B : 2; - __IO uint32_t SCK4B : 2; - __IO uint32_t SIN5S : 2; - __IO uint32_t SOT5B : 2; - __IO uint32_t SCK5B : 2; - __IO uint32_t SIN6S : 2; - __IO uint32_t SOT6B : 2; - __IO uint32_t SCK6B : 2; - __IO uint32_t SIN7S : 2; - __IO uint32_t SOT7B : 2; - __IO uint32_t SCK7B : 2; - __IO uint32_t RTS5E : 2; - __IO uint32_t CTS5S : 2; -} stc_gpio_epfr08_field_t; - -typedef struct stc_gpio_epfr09_field -{ - __IO uint32_t QAIN0S : 2; - __IO uint32_t QBIN0S : 2; - __IO uint32_t QZIN0S : 2; - __IO uint32_t QAIN1S : 2; - __IO uint32_t QBIN1S : 2; - __IO uint32_t QZIN1S : 2; - __IO uint32_t ADTRG0S : 4; - __IO uint32_t ADTRG1S : 4; - __IO uint32_t ADTRG2S : 4; - __IO uint32_t CRX0S : 2; - __IO uint32_t CTX0E : 2; - __IO uint32_t CRX1S : 2; - __IO uint32_t CTX1E : 2; -} stc_gpio_epfr09_field_t; - -typedef struct stc_gpio_epfr10_field -{ - __IO uint32_t UEDEFB : 1; - __IO uint32_t UEDTHB : 1; - __IO uint32_t UECLKE : 1; - __IO uint32_t UEWEXE : 1; - __IO uint32_t UEDQME : 1; - __IO uint32_t UEOEXE : 1; - __IO uint32_t UEFLSE : 1; - __IO uint32_t UECS1E : 1; - __IO uint32_t UECS2E : 1; - __IO uint32_t UECS3E : 1; - __IO uint32_t UECS4E : 1; - __IO uint32_t UECS5E : 1; - __IO uint32_t UECS6E : 1; - __IO uint32_t UECS7E : 1; - __IO uint32_t UEAOOE : 1; - __IO uint32_t UEA08E : 1; - __IO uint32_t UEA09E : 1; - __IO uint32_t UEA10E : 1; - __IO uint32_t UEA11E : 1; - __IO uint32_t UEA12E : 1; - __IO uint32_t UEA13E : 1; - __IO uint32_t UEA14E : 1; - __IO uint32_t UEA15E : 1; - __IO uint32_t UEA16E : 1; - __IO uint32_t UEA17E : 1; - __IO uint32_t UEA18E : 1; - __IO uint32_t UEA19E : 1; - __IO uint32_t UEA20E : 1; - __IO uint32_t UEA21E : 1; - __IO uint32_t UEA22E : 1; - __IO uint32_t UEA23E : 1; - __IO uint32_t UEA24E : 1; -} stc_gpio_epfr10_field_t; - -typedef struct stc_gpio_epfr11_field -{ - __IO uint32_t UEALEE : 1; - __IO uint32_t UECS0E : 1; - __IO uint32_t UEA01E : 1; - __IO uint32_t UEA02E : 1; - __IO uint32_t UEA03E : 1; - __IO uint32_t UEA04E : 1; - __IO uint32_t UEA05E : 1; - __IO uint32_t UEA06E : 1; - __IO uint32_t UEA07E : 1; - __IO uint32_t UED00B : 1; - __IO uint32_t UED01B : 1; - __IO uint32_t UED02B : 1; - __IO uint32_t UED03B : 1; - __IO uint32_t UED04B : 1; - __IO uint32_t UED05B : 1; - __IO uint32_t UED06B : 1; - __IO uint32_t UED07B : 1; - __IO uint32_t UED08B : 1; - __IO uint32_t UED09B : 1; - __IO uint32_t UED10B : 1; - __IO uint32_t UED11B : 1; - __IO uint32_t UED12B : 1; - __IO uint32_t UED13B : 1; - __IO uint32_t UED14B : 1; - __IO uint32_t UED15B : 1; - __IO uint32_t UERLC : 1; -} stc_gpio_epfr11_field_t; - -typedef struct stc_gpio_epfr12_field -{ - uint32_t RESERVED0 : 2; - __IO uint32_t TIOA8E : 2; - __IO uint32_t TIOB8S : 2; - uint32_t RESERVED6 : 2; - __IO uint32_t TIOA9S : 2; - __IO uint32_t TIOA9E : 2; - __IO uint32_t TIOB9S : 2; - uint32_t RESERVED14 : 4; - __IO uint32_t TIOA10E : 2; - __IO uint32_t TIOB10S : 2; - uint32_t RESERVED22 : 2; - __IO uint32_t TIOA11S : 2; - __IO uint32_t TIOA11E : 2; - __IO uint32_t TIOB11S : 2; -} stc_gpio_epfr12_field_t; - -typedef struct stc_gpio_epfr13_field -{ - uint32_t RESERVED0 : 2; - __IO uint32_t TIOA12E : 2; - __IO uint32_t TIOB12S : 2; - uint32_t RESERVED6 : 2; - __IO uint32_t TIOA13S : 2; - __IO uint32_t TIOA13E : 2; - __IO uint32_t TIOB13S : 2; - uint32_t RESERVED14 : 4; - __IO uint32_t TIOA14E : 2; - __IO uint32_t TIOB14S : 2; - uint32_t RESERVED22 : 2; - __IO uint32_t TIOA15S : 2; - __IO uint32_t TIOA15E : 2; - __IO uint32_t TIOB15S : 2; -} stc_gpio_epfr13_field_t; - -typedef struct stc_gpio_epfr14_field -{ - __IO uint32_t QAIN2S : 2; - __IO uint32_t QBIN2S : 2; - __IO uint32_t QZIN2S : 2; - uint32_t RESERVED6 :12; - __IO uint32_t E_TD0E : 1; - __IO uint32_t E_TD1E : 1; - __IO uint32_t E_TE0E : 1; - __IO uint32_t E_TE1E : 1; - __IO uint32_t E_MC0E : 1; - __IO uint32_t E_MC1B : 1; - __IO uint32_t E_MD0B : 1; - __IO uint32_t E_MD1B : 1; - __IO uint32_t E_CKE : 1; - __IO uint32_t E_PSE : 1; - __IO uint32_t E_SPLC : 2; -} stc_gpio_epfr14_field_t; - -typedef struct stc_gpio_epfr15_field -{ - __IO uint32_t EINT16S : 2; - __IO uint32_t EINT17S : 2; - __IO uint32_t EINT18S : 2; - __IO uint32_t EINT19S : 2; - __IO uint32_t EINT20S : 2; - __IO uint32_t EINT21S : 2; - __IO uint32_t EINT22S : 2; - __IO uint32_t EINT23S : 2; - __IO uint32_t EINT24S : 2; - __IO uint32_t EINT25S : 2; - __IO uint32_t EINT26S : 2; - __IO uint32_t EINT27S : 2; - __IO uint32_t EINT28S : 2; - __IO uint32_t EINT29S : 2; - __IO uint32_t EINT30S : 2; - __IO uint32_t EINT31S : 2; -} stc_gpio_epfr15_field_t; - -typedef struct stc_gpio_epfr16_field -{ - __IO uint32_t SCS6B : 2; - __IO uint32_t SCS7B : 2; - __IO uint32_t SIN8S : 2; - __IO uint32_t SOT8B : 2; - __IO uint32_t SCK8B : 2; - __IO uint32_t SIN9S : 2; - __IO uint32_t SOT9B : 2; - __IO uint32_t SCK9B : 2; - __IO uint32_t SIN10S : 2; - __IO uint32_t SOT10B : 2; - __IO uint32_t SCK10B : 2; - __IO uint32_t SIN11S : 2; - __IO uint32_t SOT11B : 2; - __IO uint32_t SCK11B : 2; - __IO uint32_t SFMPAC : 1; - __IO uint32_t SFMPBC : 1; -} stc_gpio_epfr16_field_t; - -typedef struct stc_gpio_epfr17_field -{ - uint32_t RESERVED0 : 4; - __IO uint32_t SIN12S : 2; - __IO uint32_t SOT12B : 2; - __IO uint32_t SCK12B : 2; - __IO uint32_t SIN13S : 2; - __IO uint32_t SOT13B : 2; - __IO uint32_t SCK13B : 2; - __IO uint32_t SIN14S : 2; - __IO uint32_t SOT14B : 2; - __IO uint32_t SCK14B : 2; - __IO uint32_t SIN15S : 2; - __IO uint32_t SOT15B : 2; - __IO uint32_t SCK15B : 2; -} stc_gpio_epfr17_field_t; - -typedef struct stc_gpio_epfr18_field -{ - uint32_t RESERVED0 : 4; - __IO uint32_t QAIN3S : 2; - __IO uint32_t QBIN3S : 2; - __IO uint32_t QZIN3S : 2; - uint32_t RESERVED10 : 4; - __IO uint32_t SDCLKE : 2; - __IO uint32_t SDCMDB : 2; - __IO uint32_t SDDATA0B : 2; - __IO uint32_t SDDATA1B : 2; - __IO uint32_t SDDATA2B : 2; - __IO uint32_t SDDATA3B : 2; - __IO uint32_t SDCDS : 2; - __IO uint32_t SDWPS : 2; -} stc_gpio_epfr18_field_t; - -typedef struct stc_gpio_epfr20_field -{ - __IO uint32_t UESMCEE : 1; - __IO uint32_t UESMCKE : 1; - __IO uint32_t UERASE : 1; - __IO uint32_t UECASE : 1; - __IO uint32_t UEDWEXE : 1; - __IO uint32_t UECSXE : 1; - __IO uint32_t UEDQM2E : 1; - __IO uint32_t UEDQM3E : 1; - __IO uint32_t UEDTHHB : 1; - __IO uint32_t UED16B : 1; - __IO uint32_t UED17B : 1; - __IO uint32_t UED18B : 1; - __IO uint32_t UED19B : 1; - __IO uint32_t UED20B : 1; - __IO uint32_t UED21B : 1; - __IO uint32_t UED22B : 1; - __IO uint32_t UED23B : 1; - __IO uint32_t UED24B : 1; - __IO uint32_t UED25B : 1; - __IO uint32_t UED26B : 1; - __IO uint32_t UED27B : 1; - __IO uint32_t UED28B : 1; - __IO uint32_t UED29B : 1; - __IO uint32_t UED30B : 1; - __IO uint32_t UED31B : 1; -} stc_gpio_epfr20_field_t; - -typedef struct stc_gpio_pzr0_field -{ - __IO uint32_t P00 : 1; - __IO uint32_t P01 : 1; - __IO uint32_t P02 : 1; - __IO uint32_t P03 : 1; - __IO uint32_t P04 : 1; - __IO uint32_t P05 : 1; - __IO uint32_t P06 : 1; - __IO uint32_t P07 : 1; - __IO uint32_t P08 : 1; - __IO uint32_t P09 : 1; - __IO uint32_t P0A : 1; - __IO uint32_t P0B : 1; - __IO uint32_t P0C : 1; - __IO uint32_t P0D : 1; - __IO uint32_t P0E : 1; - __IO uint32_t P0F : 1; -} stc_gpio_pzr0_field_t; - -typedef struct stc_gpio_pzr1_field -{ - __IO uint32_t P10 : 1; - __IO uint32_t P11 : 1; - __IO uint32_t P12 : 1; - __IO uint32_t P13 : 1; - __IO uint32_t P14 : 1; - __IO uint32_t P15 : 1; - __IO uint32_t P16 : 1; - __IO uint32_t P17 : 1; - __IO uint32_t P18 : 1; - __IO uint32_t P19 : 1; - __IO uint32_t P1A : 1; - __IO uint32_t P1B : 1; - __IO uint32_t P1C : 1; - __IO uint32_t P1D : 1; - __IO uint32_t P1E : 1; - __IO uint32_t P1F : 1; -} stc_gpio_pzr1_field_t; - -typedef struct stc_gpio_pzr2_field -{ - __IO uint32_t P20 : 1; - __IO uint32_t P21 : 1; - __IO uint32_t P22 : 1; - __IO uint32_t P23 : 1; - __IO uint32_t P24 : 1; - __IO uint32_t P25 : 1; - __IO uint32_t P26 : 1; - __IO uint32_t P27 : 1; -} stc_gpio_pzr2_field_t; - -typedef struct stc_gpio_pzr3_field -{ - __IO uint32_t P30 : 1; - __IO uint32_t P31 : 1; - __IO uint32_t P32 : 1; - __IO uint32_t P33 : 1; - __IO uint32_t P34 : 1; - __IO uint32_t P35 : 1; - __IO uint32_t P36 : 1; - __IO uint32_t P37 : 1; - __IO uint32_t P38 : 1; - __IO uint32_t P39 : 1; - __IO uint32_t P3A : 1; - __IO uint32_t P3B : 1; - __IO uint32_t P3C : 1; - __IO uint32_t P3D : 1; - __IO uint32_t P3E : 1; - __IO uint32_t P3F : 1; -} stc_gpio_pzr3_field_t; - -typedef struct stc_gpio_pzr4_field -{ - __IO uint32_t P40 : 1; - __IO uint32_t P41 : 1; - __IO uint32_t P42 : 1; - __IO uint32_t P43 : 1; - __IO uint32_t P44 : 1; - __IO uint32_t P45 : 1; - __IO uint32_t P46 : 1; - __IO uint32_t P47 : 1; - __IO uint32_t P48 : 1; - __IO uint32_t P49 : 1; - __IO uint32_t P4A : 1; - __IO uint32_t P4B : 1; - __IO uint32_t P4C : 1; - __IO uint32_t P4D : 1; - __IO uint32_t P4E : 1; -} stc_gpio_pzr4_field_t; - -typedef struct stc_gpio_pzr5_field -{ - __IO uint32_t P50 : 1; - __IO uint32_t P51 : 1; - __IO uint32_t P52 : 1; - __IO uint32_t P53 : 1; - __IO uint32_t P54 : 1; - __IO uint32_t P55 : 1; - __IO uint32_t P56 : 1; - __IO uint32_t P57 : 1; - __IO uint32_t P58 : 1; - __IO uint32_t P59 : 1; - __IO uint32_t P5A : 1; - __IO uint32_t P5B : 1; -} stc_gpio_pzr5_field_t; - -typedef struct stc_gpio_pzr6_field -{ - __IO uint32_t P60 : 1; - __IO uint32_t P61 : 1; - __IO uint32_t P62 : 1; - __IO uint32_t P63 : 1; - __IO uint32_t P64 : 1; - __IO uint32_t P65 : 1; - __IO uint32_t P66 : 1; - __IO uint32_t P67 : 1; - __IO uint32_t P68 : 1; -} stc_gpio_pzr6_field_t; - -typedef struct stc_gpio_pzr7_field -{ - __IO uint32_t P70 : 1; - __IO uint32_t P71 : 1; - __IO uint32_t P72 : 1; - __IO uint32_t P73 : 1; - __IO uint32_t P74 : 1; -} stc_gpio_pzr7_field_t; - -typedef struct stc_gpio_pzr8_field -{ - __IO uint32_t P80 : 1; - __IO uint32_t P81 : 1; -} stc_gpio_pzr8_field_t; - -typedef struct stc_gpio_pzre_field -{ - __IO uint32_t PE0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t PE2 : 1; - __IO uint32_t PE3 : 1; -} stc_gpio_pzre_field_t; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* LVD_MODULE register bit fields */ -typedef struct stc_lvd_lvd_ctl_field -{ - union { - struct { - uint8_t RESERVED1 : 2; - __IO uint8_t SVHI : 4; - uint8_t RESERVED2 : 1; - __IO uint8_t LVDIE : 1; - }; - struct { - uint8_t RESERVED3 : 2; - __IO uint8_t SVHI0 : 1; - __IO uint8_t SVHI1 : 1; - __IO uint8_t SVHI2 : 1; - __IO uint8_t SVHI3 : 1; - uint8_t RESERVED4 : 2; - }; - }; -} stc_lvd_lvd_ctl_field_t; - -typedef struct stc_lvd_lvd_str_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIR : 1; -} stc_lvd_lvd_str_field_t; - -typedef struct stc_lvd_lvd_clr_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDCL : 1; -} stc_lvd_lvd_clr_field_t; - -typedef struct stc_lvd_lvd_str2_field -{ - uint8_t RESERVED1 : 6; - __IO uint8_t LVDRRDY : 1; - __IO uint8_t LVDIRDY : 1; -} stc_lvd_lvd_str2_field_t; - -/****************************************************************************** - * DS_MODULE - ******************************************************************************/ -/* DS_MODULE register bit fields */ -typedef struct stc_ds_rck_ctl_field -{ - __IO uint8_t RTCCKE : 1; -} stc_ds_rck_ctl_field_t; - -typedef struct stc_ds_pmd_ctl_field -{ - __IO uint8_t RTCE : 1; -} stc_ds_pmd_ctl_field_t; - -typedef struct stc_ds_wrfsr_field -{ - __IO uint8_t WINITX : 1; - __IO uint8_t WLVDH : 1; -} stc_ds_wrfsr_field_t; - -typedef struct stc_ds_wifsr_field -{ - __IO uint16_t WRTCI : 1; - __IO uint16_t WLVDI : 1; - __IO uint16_t WUI0 : 1; - __IO uint16_t WUI1 : 1; - __IO uint16_t WUI2 : 1; - __IO uint16_t WUI3 : 1; - __IO uint16_t WUI4 : 1; - __IO uint16_t WUI5 : 1; -} stc_ds_wifsr_field_t; - -typedef struct stc_ds_wier_field -{ - __IO uint16_t WRTCE : 1; - __IO uint16_t WLVDE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t WUI1E : 1; - __IO uint16_t WUI2E : 1; - __IO uint16_t WUI3E : 1; - __IO uint16_t WUI4E : 1; - __IO uint16_t WUI5E : 1; -} stc_ds_wier_field_t; - -typedef struct stc_ds_wilvr_field -{ - __IO uint8_t WUI1LV : 1; - __IO uint8_t WUI2LV : 1; - __IO uint8_t WUI3LV : 1; - __IO uint8_t WUI4LV : 1; - __IO uint8_t WUI5LV : 1; -} stc_ds_wilvr_field_t; - -typedef struct stc_ds_dsramr_field -{ - __IO uint8_t SRAMR : 2; -} stc_ds_dsramr_field_t; - -/****************************************************************************** - * USB Ethernet CLK - ******************************************************************************/ -/* USB ETHERNET CLK register bit fields */ -typedef struct stc_usbethernetclk_uccr_field -{ - __IO uint8_t UCEN0 : 1; - __IO uint8_t UCSEL0 : 1; - __IO uint8_t UCSEL1 : 1; - __IO uint8_t UCEN1 : 1; - __IO uint8_t ECEN : 1; - __IO uint8_t ECSEL0 : 1; - __IO uint8_t ECSEL1 : 1; -} stc_usbethernetclk_uccr_field_t; - -typedef struct stc_usbethernetclk_upcr1_field -{ - __IO uint8_t UPLLEN : 1; - __IO uint8_t UPINC : 1; -} stc_usbethernetclk_upcr1_field_t; - -typedef struct stc_usbethernetclk_upcr2_field -{ - __IO uint8_t UPOWT0 : 1; - __IO uint8_t UPOWT1 : 1; - __IO uint8_t UPOWT2 : 1; -} stc_usbethernetclk_upcr2_field_t; - -typedef struct stc_usbethernetclk_upcr3_field -{ - __IO uint8_t UPLLK0 : 1; - __IO uint8_t UPLLK1 : 1; - __IO uint8_t UPLLK2 : 1; - __IO uint8_t UPLLK3 : 1; - __IO uint8_t UPLLK4 : 1; -} stc_usbethernetclk_upcr3_field_t; - -typedef struct stc_usbethernetclk_upcr4_field -{ - __IO uint8_t UPLLN0 : 1; - __IO uint8_t UPLLN1 : 1; - __IO uint8_t UPLLN2 : 1; - __IO uint8_t UPLLN3 : 1; - __IO uint8_t UPLLN4 : 1; - __IO uint8_t UPLLN5 : 1; - __IO uint8_t UPLLN6 : 1; -} stc_usbethernetclk_upcr4_field_t; - -typedef struct stc_usbethernetclk_up_str_field -{ - __IO uint8_t UPRDY : 1; -} stc_usbethernetclk_up_str_field_t; - -typedef struct stc_usbethernetclk_upint_enr_field -{ - __IO uint8_t UPCSE : 1; -} stc_usbethernetclk_upint_enr_field_t; - -typedef struct stc_usbethernetclk_upint_clr_field -{ - __IO uint8_t UPCSC : 1; -} stc_usbethernetclk_upint_clr_field_t; - -typedef struct stc_usbethernetclk_upint_str_field -{ - __IO uint8_t UPCSI : 1; -} stc_usbethernetclk_upint_str_field_t; - -typedef struct stc_usbethernetclk_upcr5_field -{ - __IO uint8_t UPLLM0 : 1; - __IO uint8_t UPLLM1 : 1; - __IO uint8_t UPLLM2 : 1; - __IO uint8_t UPLLM3 : 1; -} stc_usbethernetclk_upcr5_field_t; - -typedef struct stc_usbethernetclk_upcr6_field -{ - __IO uint8_t UBSR0 : 1; - __IO uint8_t UBSR1 : 1; - __IO uint8_t UBSR2 : 1; - __IO uint8_t UBSR3 : 1; -} stc_usbethernetclk_upcr6_field_t; - -typedef struct stc_usbethernetclk_upcr7_field -{ - __IO uint8_t EPLLEN : 1; -} stc_usbethernetclk_upcr7_field_t; - -typedef struct stc_usbethernetclk_usben0_field -{ - __IO uint8_t USBEN0 : 1; -} stc_usbethernetclk_usben0_field_t; - -typedef struct stc_usbethernetclk_usben1_field -{ - __IO uint8_t USBEN1 : 1; -} stc_usbethernetclk_usben1_field_t; - - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USBCLK register bit fields */ -typedef struct stc_usbclk_uccr_field -{ - __IO uint8_t UCEN : 1; - __IO uint8_t UCSEL : 1; -} stc_usbclk_uccr_field_t; - -typedef struct stc_usbclk_upcr1_field -{ - __IO uint8_t UPLLEN : 1; - __IO uint8_t UPINC : 1; -} stc_usbclk_upcr1_field_t; - -typedef struct stc_usbclk_upcr2_field -{ - __IO uint8_t UPOWT0 : 1; - __IO uint8_t UPOWT1 : 1; - __IO uint8_t UPOWT2 : 1; -} stc_usbclk_upcr2_field_t; - -typedef struct stc_usbclk_upcr3_field -{ - __IO uint8_t UPLLK0 : 1; - __IO uint8_t UPLLK1 : 1; - __IO uint8_t UPLLK2 : 1; - __IO uint8_t UPLLK3 : 1; - __IO uint8_t UPLLK4 : 1; -} stc_usbclk_upcr3_field_t; - -typedef struct stc_usbclk_upcr4_field -{ - __IO uint8_t UPLLN0 : 1; - __IO uint8_t UPLLN1 : 1; - __IO uint8_t UPLLN2 : 1; - __IO uint8_t UPLLN3 : 1; - __IO uint8_t UPLLN4 : 1; -} stc_usbclk_upcr4_field_t; - -typedef struct stc_usbclk_up_str_field -{ - __IO uint8_t UPRDY : 1; -} stc_usbclk_up_str_field_t; - -typedef struct stc_usbclk_upint_enr_field -{ - __IO uint8_t UPCSE : 1; -} stc_usbclk_upint_enr_field_t; - -typedef struct stc_usbclk_upint_clr_field -{ - __IO uint8_t UPCSC : 1; -} stc_usbclk_upint_clr_field_t; - -typedef struct stc_usbclk_upint_str_field -{ - __IO uint8_t UPCSI : 1; -} stc_usbclk_upint_str_field_t; - -typedef struct stc_usbclk_usben_field -{ - __IO uint8_t USBEN : 1; -} stc_usbclk_usben_field_t; - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CANPRE_MODULE register bit fields */ -typedef struct stc_canpre_canpre_field -{ - __IO uint8_t CANPRE0 : 1; - __IO uint8_t CANPRE1 : 1; - __IO uint8_t CANPRE2 : 1; - __IO uint8_t CANPRE3 : 1; -} stc_canpre_canpre_field_t; - -/****************************************************************************** - * MFS_MODULE(COMMON) - ******************************************************************************/ -/* MFS_MODULE(COMMON) register bit fields */ -typedef struct stc_mfs_smr_field -{ - union { - struct { - __IO uint8_t SOE : 1; /* for UART/CSIO/LIN */ - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; /* for UART/CSIO */ - __IO uint8_t SBL : 1; /* for UART/LIN */ - __IO uint8_t WUCR : 1; /* for UART/LIN */ - __IO uint8_t MD : 3; /* for UART/CSIO/LIN/I2C */ - }; - struct { - uint8_t RESERVED2 : 1; - __IO uint8_t SCKE : 1; /* for CSIO */ - uint8_t RESERVED3 : 1; - __IO uint8_t SCINV : 1; /* for CSIO */ - uint8_t RESERVED4 : 4; - }; - struct { - uint8_t RESERVED5 : 2; - __IO uint8_t TIE : 1; /* for I2C */ - __IO uint8_t RIE : 1; /* for I2C */ - uint8_t RESERVED6 : 4; - }; - }; -} stc_mfs_smr_field_t; - -typedef struct stc_mfs_scr_field -{ - union { - struct { - __IO uint8_t TXE : 1; /* for UART/CSIO/LIN */ - __IO uint8_t RXE : 1; /* for UART/CSIO/LIN */ - __IO uint8_t TBIE : 1; /* for UART/CSIO/LIN */ - __IO uint8_t TIE : 1; /* for UART/CSIO/LIN */ - __IO uint8_t RIE : 1; /* for UART/CSIO/LIN */ - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; /* for UART/CSIO/LIN */ - }; - struct { - uint8_t RESERVED2 : 5; - __IO uint8_t SPI : 1; /* for CSIO */ - __IO uint8_t MS : 1; /* for CSIO/LIN */ - uint8_t RESERVED3 : 1; - }; - struct { - uint8_t RESERVED4 : 5; - __IO uint8_t LBR : 1; /* for LIN */ - uint8_t RESERVED5 : 2; - }; - }; -} stc_mfs_scr_field_t; - -typedef struct stc_mfs_escr_field -{ - union { - struct { - __IO uint8_t L : 3; /* for UART/CSIO */ - __IO uint8_t P : 1; /* for UART */ - __IO uint8_t PEN : 1; /* for UART */ - __IO uint8_t INV : 1; /* for UART */ - __IO uint8_t ESBL : 1; /* for UART/LIN */ - __IO uint8_t FLWEN : 1; /* for UART */ - }; - struct { - __IO uint8_t L0 : 1; /* for UART/CSIO */ - __IO uint8_t L1 : 1; /* for UART/CSIO */ - __IO uint8_t L2 : 1; /* for UART/CSIO */ - __IO uint8_t WT : 2; /* for CSIO */ - uint8_t RESERVED2 : 1; - __IO uint8_t L3 : 1; /* for CSIO */ - __IO uint8_t SOP : 1; /* for CSIO */ - }; - struct { - uint8_t RESERVED3 : 3; - __IO uint8_t WT0 : 1; /* for CSIO */ - __IO uint8_t WT1 : 1; /* for CSIO */ - uint8_t RESERVED4 : 3; - }; - struct { - __IO uint8_t DEL : 2; /* for LIN */ - __IO uint8_t LBL : 2; /* for LIN */ - __IO uint8_t LBIE : 1; /* for LIN */ - uint8_t RESERVED5 : 3; - }; - struct { - __IO uint8_t DEL0 : 1; /* for LIN */ - __IO uint8_t DEL1 : 1; /* for LIN */ - __IO uint8_t LBL0 : 1; /* for LIN */ - __IO uint8_t LBL1 : 1; /* for LIN */ - uint8_t RESERVED6 : 4; - }; - }; -} stc_mfs_escr_field_t; - -typedef struct stc_mfs_ssr_field -{ - union { - struct { - __IO uint8_t TBI : 1; /* for UART/CSIO/LIN/I2C */ - __IO uint8_t TDRE : 1; /* for UART/CSIO/LIN/I2C */ - __IO uint8_t RDRF : 1; /* for UART/CSIO/LIN/I2C */ - __IO uint8_t ORE : 1; /* for UART/CSIO/LIN/I2C */ - __IO uint8_t FRE : 1; /* for UART/LIN */ - __IO uint8_t PE : 1; /* for UART */ - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; /* for UART/CSIO/LIN/I2C */ - }; - struct { - uint8_t RESERVED2 : 4; - __IO uint8_t AWC : 1; /* for CSIO */ - uint8_t RESERVED3 : 3; - }; - struct { - uint8_t RESERVED4 : 5; - __IO uint8_t LBD : 1; /* for LIN */ - uint8_t RESERVED5 : 2; - }; - struct { - uint8_t RESERVED6 : 4; - __IO uint8_t TBIE : 1; /* for I2C */ - __IO uint8_t DMA : 1; /* for I2C */ - __IO uint8_t TSET : 1; /* for I2C */ - uint8_t RESERVED7 : 1; - }; - }; -} stc_mfs_ssr_field_t; - -typedef struct stc_mfs_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs_bgr_field_t; - -typedef struct stc_mfs_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs_bgr1_field_t; - -typedef struct stc_mfs_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs_fcr_field_t; - -typedef struct stc_mfs_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; - uint8_t RESERVED1 : 1; -} stc_mfs_fcr0_field_t; - -typedef struct stc_mfs_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs_fcr1_field_t; - -typedef struct stc_mfs_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs_fbyte_field_t; - -typedef struct stc_mfs_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs_fbyte1_field_t; - -typedef struct stc_mfs_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs_fbyte2_field_t; - -/****************************************************************************** - * MFS_MODULE(UART) - ******************************************************************************/ -/* MFS_MODULE(UART) register bit fields */ -typedef struct stc_mfs_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; - uint16_t RESERVED2 : 7; -} stc_mfs_uart_rdr_field_t; - -typedef struct stc_mfs_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; - uint16_t RESERVED2 : 7; -} stc_mfs_uart_tdr_field_t; - -/****************************************************************************** - * MFS_MODULE(CSIO) - ******************************************************************************/ -/* MFS_MODULE(CSIO) register bit fields */ -typedef struct stc_mfs_csio_scstr10_field -{ - __IO uint16_t CSHD0 : 1; - __IO uint16_t CSHD1 : 1; - __IO uint16_t CSHD2 : 1; - __IO uint16_t CSHD3 : 1; - __IO uint16_t CSHD4 : 1; - __IO uint16_t CSHD5 : 1; - __IO uint16_t CSHD6 : 1; - __IO uint16_t CSHD7 : 1; - __IO uint16_t CSSU0 : 1; - __IO uint16_t CSSU1 : 1; - __IO uint16_t CSSU2 : 1; - __IO uint16_t CSSU3 : 1; - __IO uint16_t CSSU4 : 1; - __IO uint16_t CSSU5 : 1; - __IO uint16_t CSSU6 : 1; - __IO uint16_t CSSU7 : 1; -} stc_mfs_csio_scstr10_field_t; - -typedef struct stc_mfs_csio_scstr0_field -{ - __IO uint8_t CSHD0 : 1; - __IO uint8_t CSHD1 : 1; - __IO uint8_t CSHD2 : 1; - __IO uint8_t CSHD3 : 1; - __IO uint8_t CSHD4 : 1; - __IO uint8_t CSHD5 : 1; - __IO uint8_t CSHD6 : 1; - __IO uint8_t CSHD7 : 1; -} stc_mfs_csio_scstr0_field_t; - -typedef struct stc_mfs_csio_scstr1_field -{ - __IO uint8_t CSSU0 : 1; - __IO uint8_t CSSU1 : 1; - __IO uint8_t CSSU2 : 1; - __IO uint8_t CSSU3 : 1; - __IO uint8_t CSSU4 : 1; - __IO uint8_t CSSU5 : 1; - __IO uint8_t CSSU6 : 1; - __IO uint8_t CSSU7 : 1; -} stc_mfs_csio_scstr1_field_t; - -typedef struct stc_mfs_csio_scstr32_field -{ - __IO uint16_t CSDS0 : 1; - __IO uint16_t CSDS1 : 1; - __IO uint16_t CSDS2 : 1; - __IO uint16_t CSDS3 : 1; - __IO uint16_t CSDS4 : 1; - __IO uint16_t CSDS5 : 1; - __IO uint16_t CSDS6 : 1; - __IO uint16_t CSDS7 : 1; - __IO uint16_t CSDS8 : 1; - __IO uint16_t CSDS9 : 1; - __IO uint16_t CSDS10 : 1; - __IO uint16_t CSDS11 : 1; - __IO uint16_t CSDS12 : 1; - __IO uint16_t CSDS13 : 1; - __IO uint16_t CSDS14 : 1; - __IO uint16_t CSDS15 : 1; -} stc_mfs_csio_scstr32_field_t; - -typedef struct stc_mfs_csio_scstr2_field -{ - __IO uint8_t CSDS0 : 1; - __IO uint8_t CSDS1 : 1; - __IO uint8_t CSDS2 : 1; - __IO uint8_t CSDS3 : 1; - __IO uint8_t CSDS4 : 1; - __IO uint8_t CSDS5 : 1; - __IO uint8_t CSDS6 : 1; - __IO uint8_t CSDS7 : 1; -} stc_mfs_csio_scstr2_field_t; - -typedef struct stc_mfs_csio_scstr3_field -{ - __IO uint8_t CSDS8 : 1; - __IO uint8_t CSDS9 : 1; - __IO uint8_t CSDS10 : 1; - __IO uint8_t CSDS11 : 1; - __IO uint8_t CSDS12 : 1; - __IO uint8_t CSDS13 : 1; - __IO uint8_t CSDS14 : 1; - __IO uint8_t CSDS15 : 1; -} stc_mfs_csio_scstr3_field_t; - -typedef struct stc_mfs_csio_sacsr_field -{ - __IO uint16_t TMRE : 1; - __IO uint16_t TDIV : 4; - uint16_t RESERVED1 : 1; - __IO uint16_t TSYNE : 1; - __IO uint16_t TINTE : 1; - __IO uint16_t TINT : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t CSE : 1; - __IO uint16_t CSEIE : 1; - __IO uint16_t TBEEN : 1; - uint16_t RESERVED3 : 2; -} stc_mfs_csio_sacsr_field_t; - -typedef struct stc_mfs_csio_sacsr0_field -{ - __IO uint8_t TMRE : 1; - __IO uint8_t TDIV : 4; - uint8_t RESERVED1 : 1; - __IO uint8_t TSYNE : 1; - __IO uint8_t TINTE : 1; -} stc_mfs_csio_sacsr0_field_t; - -typedef struct stc_mfs_csio_sacsr1_field -{ - __IO uint8_t TINT : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CSE : 1; - __IO uint8_t CSEIE : 1; - __IO uint8_t TBEEN : 1; - uint8_t RESERVED2 : 2; -} stc_mfs_csio_sacsr1_field_t; - -typedef struct stc_mfs_csio_stmr_field -{ - __IO uint16_t TM0 : 1; - __IO uint16_t TM1 : 1; - __IO uint16_t TM2 : 1; - __IO uint16_t TM3 : 1; - __IO uint16_t TM4 : 1; - __IO uint16_t TM5 : 1; - __IO uint16_t TM6 : 1; - __IO uint16_t TM7 : 1; - __IO uint16_t TM8 : 1; - __IO uint16_t TM9 : 1; - __IO uint16_t TM10 : 1; - __IO uint16_t TM11 : 1; - __IO uint16_t TM12 : 1; - __IO uint16_t TM13 : 1; - __IO uint16_t TM14 : 1; - __IO uint16_t TM15 : 1; -} stc_mfs_csio_stmr_field_t; - -typedef struct stc_mfs_csio_stmr0_field -{ - __IO uint8_t TM0 : 1; - __IO uint8_t TM1 : 1; - __IO uint8_t TM2 : 1; - __IO uint8_t TM3 : 1; - __IO uint8_t TM4 : 1; - __IO uint8_t TM5 : 1; - __IO uint8_t TM6 : 1; - __IO uint8_t TM7 : 1; -} stc_mfs_csio_stmr0_field_t; - -typedef struct stc_mfs_csio_stmr1_field -{ - __IO uint8_t TM8 : 1; - __IO uint8_t TM9 : 1; - __IO uint8_t TM10 : 1; - __IO uint8_t TM11 : 1; - __IO uint8_t TM12 : 1; - __IO uint8_t TM13 : 1; - __IO uint8_t TM14 : 1; - __IO uint8_t TM15 : 1; -} stc_mfs_csio_stmr1_field_t; - -typedef struct stc_mfs_csio_stmcr_field -{ - __IO uint16_t TC0 : 1; - __IO uint16_t TC1 : 1; - __IO uint16_t TC2 : 1; - __IO uint16_t TC3 : 1; - __IO uint16_t TC4 : 1; - __IO uint16_t TC5 : 1; - __IO uint16_t TC6 : 1; - __IO uint16_t TC7 : 1; - __IO uint16_t TC8 : 1; - __IO uint16_t TC9 : 1; - __IO uint16_t TC10 : 1; - __IO uint16_t TC11 : 1; - __IO uint16_t TC12 : 1; - __IO uint16_t TC13 : 1; - __IO uint16_t TC14 : 1; - __IO uint16_t TC15 : 1; -} stc_mfs_csio_stmcr_field_t; - -typedef struct stc_mfs_csio_stmcr0_field -{ - __IO uint8_t TC0 : 1; - __IO uint8_t TC1 : 1; - __IO uint8_t TC2 : 1; - __IO uint8_t TC3 : 1; - __IO uint8_t TC4 : 1; - __IO uint8_t TC5 : 1; - __IO uint8_t TC6 : 1; - __IO uint8_t TC7 : 1; -} stc_mfs_csio_stmcr0_field_t; - -typedef struct stc_mfs_csio_stmcr1_field -{ - __IO uint8_t TC8 : 1; - __IO uint8_t TC9 : 1; - __IO uint8_t TC10 : 1; - __IO uint8_t TC11 : 1; - __IO uint8_t TC12 : 1; - __IO uint8_t TC13 : 1; - __IO uint8_t TC14 : 1; - __IO uint8_t TC15 : 1; -} stc_mfs_csio_stmcr1_field_t; - -typedef struct stc_mfs_csio_scscr_field -{ - __IO uint16_t CSOE : 1; - __IO uint16_t CSEN0 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t CSLVL : 1; - __IO uint16_t CDIV : 3; - __IO uint16_t SCAM : 1; - uint16_t RESERVED2 : 6; -} stc_mfs_csio_scscr_field_t; - -/****************************************************************************** - * MFS_MODULE(I2C) - ******************************************************************************/ -/* MFS_MODULE(I2C) register bit fields */ -typedef struct stc_mfs_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t ACT_SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs_i2c_ibcr_field_t; - -typedef struct stc_mfs_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs_i2c_ibsr_field_t; - -typedef struct stc_mfs_i2c_isba_field -{ - union { - struct { - __IO uint8_t SA : 7; - __IO uint8_t SAEN : 1; - }; - struct { - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - uint8_t RESERVED1 : 1; - }; - }; -} stc_mfs_i2c_isba_field_t; - -typedef struct stc_mfs_i2c_ismk_field -{ - union { - struct { - __IO uint8_t SM : 7; - __IO uint8_t EN : 1; - }; - struct { - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - uint8_t RESERVED1 : 1; - }; - }; -} stc_mfs_i2c_ismk_field_t; - -typedef struct stc_mfs_i2c_nfcr_field -{ - __IO uint8_t NFT : 5; - uint8_t RESERVED1 : 3; -} stc_mfs_i2c_nfcr_field_t; - -typedef struct stc_mfs_i2c_eibcr_field -{ - __IO uint8_t BEC : 1; - __IO uint8_t SOCE : 1; - __IO uint8_t SCLC : 1; - __IO uint8_t SDAC : 1; - __IO uint8_t SCLS : 1; - __IO uint8_t SDAS : 1; - uint8_t RESERVED1 : 2; -} stc_mfs_i2c_eibcr_field_t; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC_MODULE register bit fields */ -typedef struct stc_crc_crccr_field -{ - __IO uint8_t INIT : 1; - __IO uint8_t CRC32 : 1; - __IO uint8_t LTLEND : 1; - __IO uint8_t LSBFST : 1; - __IO uint8_t CRCLTE : 1; - __IO uint8_t CRCLSF : 1; - __IO uint8_t FXOR : 1; -} stc_crc_crccr_field_t; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* WC_MODULE register bit fields */ -typedef struct stc_wc_wcrd_field -{ - __IO uint8_t CTR0 : 1; - __IO uint8_t CTR1 : 1; - __IO uint8_t CTR2 : 1; - __IO uint8_t CTR3 : 1; - __IO uint8_t CTR4 : 1; - __IO uint8_t CTR5 : 1; -} stc_wc_wcrd_field_t; - -typedef struct stc_wc_wcrl_field -{ - __IO uint8_t RLC0 : 1; - __IO uint8_t RLC1 : 1; - __IO uint8_t RLC2 : 1; - __IO uint8_t RLC3 : 1; - __IO uint8_t RLC4 : 1; - __IO uint8_t RLC5 : 1; -} stc_wc_wcrl_field_t; - -typedef struct stc_wc_wccr_field -{ - __IO uint8_t WCIF : 1; - __IO uint8_t WCIE : 1; - __IO uint8_t CS0 : 1; - __IO uint8_t CS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t WCOP : 1; - __IO uint8_t WCEN : 1; -} stc_wc_wccr_field_t; - -typedef struct stc_wc_clk_sel_field -{ - __IO uint16_t SEL_IN : 2; - uint16_t RESERVED1 : 6; - __IO uint16_t SEL_OUT : 3; -} stc_wc_clk_sel_field_t; - -typedef struct stc_wc_clk_en_field -{ - __IO uint8_t CLK_EN : 1; - __IO uint8_t CLK_EN_R : 1; -} stc_wc_clk_en_field_t; - -/****************************************************************************** - * RTC_MODULE - ******************************************************************************/ -/* RTC_MODULE register bit fields */ -/* RTC CNT */ -typedef struct stc_rtc_wtcr10_field -{ - __IO uint8_t ST : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t RUN : 1; - __IO uint8_t SRST : 1; - __IO uint8_t SCST : 1; - __IO uint8_t SCRST : 1; - __IO uint8_t BUSY : 1; - __IO uint8_t TRANS : 1; -} stc_rtc_wtcr10_field_t; - -typedef struct stc_rtc_wtcr11_field -{ - __IO uint8_t MIEN : 1; - __IO uint8_t HEN : 1; - __IO uint8_t DEN : 1; - __IO uint8_t MOEN : 1; - __IO uint8_t YEN : 1; - uint8_t RESERVED1 : 3; -} stc_rtc_wtcr11_field_t; - -typedef struct stc_rtc_wtcr12_field -{ - __IO uint8_t INTSSI : 1; - __IO uint8_t INTSI : 1; - __IO uint8_t INTMI : 1; - __IO uint8_t INTHI : 1; - __IO uint8_t INTTMI : 1; - __IO uint8_t INTALI : 1; - __IO uint8_t INTERI : 1; - __IO uint8_t INTCRI : 1; -} stc_rtc_wtcr12_field_t; - -typedef struct stc_rtc_wtcr13_field -{ - __IO uint8_t INTSSIE : 1; - __IO uint8_t INTSIE : 1; - __IO uint8_t INTMIE : 1; - __IO uint8_t INTHIE : 1; - __IO uint8_t INTTMIE : 1; - __IO uint8_t INTALIE : 1; - __IO uint8_t INTERIE : 1; - __IO uint8_t INTCRIE : 1; -} stc_rtc_wtcr13_field_t; - -typedef struct stc_rtc_wtcr20_field -{ - __IO uint8_t CREAD : 1; - __IO uint8_t CWRITE : 1; - __IO uint8_t BREAD : 1; - __IO uint8_t BWRITE : 1; - __IO uint8_t PREAD : 1; - __IO uint8_t PWRITE : 1; - uint8_t RESERVED1 : 2; -} stc_rtc_wtcr20_field_t; - -typedef struct stc_rtc_wtcr21_field -{ - __IO uint8_t TMST : 1; - __IO uint8_t TMEN : 1; - __IO uint8_t TMRUN : 1; - uint8_t RESERVED1 : 5; -} stc_rtc_wtcr21_field_t; - -typedef struct stc_rtc_wtsr_field -{ - union { - struct { - __IO uint8_t S : 4; - __IO uint8_t TS : 3; - uint8_t RESERVED1 : 1; - }; - struct { - __IO uint8_t S0 : 1; - __IO uint8_t S1 : 1; - __IO uint8_t S2 : 1; - __IO uint8_t S3 : 1; - __IO uint8_t TS0 : 1; - __IO uint8_t TS1 : 1; - __IO uint8_t TS2 : 1; - uint8_t RESERVED2 : 1; - }; - }; -} stc_rtc_wtsr_field_t; - -typedef struct stc_rtc_wtmir_field -{ - union { - struct { - __IO uint8_t MI : 4; - __IO uint8_t TMI : 3; - uint8_t RESERVED1 : 1; - }; - struct { - __IO uint8_t MI0 : 1; - __IO uint8_t MI1 : 1; - __IO uint8_t MI2 : 1; - __IO uint8_t MI3 : 1; - __IO uint8_t TMI0 : 1; - __IO uint8_t TMI1 : 1; - __IO uint8_t TMI2 : 1; - uint8_t RESERVED2 : 1; - }; - }; -} stc_rtc_wtmir_field_t; - -typedef struct stc_rtc_wthr_field -{ - union { - struct { - __IO uint8_t H : 4; - __IO uint8_t TH : 2; - uint8_t RESERVED1 : 2; - }; - struct { - __IO uint8_t H0 : 1; - __IO uint8_t H1 : 1; - __IO uint8_t H2 : 1; - __IO uint8_t H3 : 1; - __IO uint8_t TH0 : 1; - __IO uint8_t TH1 : 1; - uint8_t RESERVED2 : 2; - }; - }; -} stc_rtc_wthr_field_t; - -typedef struct stc_rtc_wtdr_field -{ - union { - struct { - __IO uint8_t D : 4; - __IO uint8_t TD : 2; - uint8_t RESERVED1 : 2; - }; - struct { - __IO uint8_t D0 : 1; - __IO uint8_t D1 : 1; - __IO uint8_t D2 : 1; - __IO uint8_t D3 : 1; - __IO uint8_t TD0 : 1; - __IO uint8_t TD1 : 1; - uint8_t RESERVED2 : 2; - }; - }; -} stc_rtc_wtdr_field_t; - -typedef struct stc_rtc_wtdw_field -{ - union { - struct { - __IO uint8_t DW : 3; - uint8_t RESERVED1 : 5; - }; - struct { - __IO uint8_t DW0 : 1; - __IO uint8_t DW1 : 1; - __IO uint8_t DW2 : 1; - uint8_t RESERVED2 : 5; - }; - }; -} stc_rtc_wtdw_field_t; - -typedef struct stc_rtc_wtmor_field -{ - union { - struct { - __IO uint8_t MO : 4; - __IO uint8_t TMO : 1; - uint8_t RESERVED1 : 3; - }; - struct { - __IO uint8_t MO0 : 1; - __IO uint8_t MO1 : 1; - __IO uint8_t MO2 : 1; - __IO uint8_t MO3 : 1; - uint8_t RESERVED2 : 4; - }; - }; -} stc_rtc_wtmor_field_t; - -typedef struct stc_rtc_wtyr_field -{ - union { - struct { - __IO uint8_t Y : 4; - __IO uint8_t TY : 4; - }; - struct { - __IO uint8_t Y0 : 1; - __IO uint8_t Y1 : 1; - __IO uint8_t Y2 : 1; - __IO uint8_t Y3 : 1; - __IO uint8_t TY0 : 1; - __IO uint8_t TY1 : 1; - __IO uint8_t TY2 : 1; - __IO uint8_t TY3 : 1; - }; - }; -} stc_rtc_wtyr_field_t; - -typedef struct stc_rtc_almir_field -{ - union { - struct { - __IO uint8_t AMI : 4; - __IO uint8_t TAMI : 3; - uint8_t RESERVED1 : 1; - }; - struct { - __IO uint8_t AMI0 : 1; - __IO uint8_t AMI1 : 1; - __IO uint8_t AMI2 : 1; - __IO uint8_t AMI3 : 1; - __IO uint8_t TAMI0 : 1; - __IO uint8_t TAMI1 : 1; - __IO uint8_t TAMI2 : 1; - uint8_t RESERVED2 : 1; - }; - }; -} stc_rtc_almir_field_t; - -typedef struct stc_rtc_alhr_field -{ - union { - struct { - __IO uint8_t AH : 4; - __IO uint8_t TAH : 2; - uint8_t RESERVED1 : 2; - }; - struct { - __IO uint8_t AH0 : 1; - __IO uint8_t AH1 : 1; - __IO uint8_t AH2 : 1; - __IO uint8_t AH3 : 1; - __IO uint8_t TAH0 : 1; - __IO uint8_t TAH1 : 1; - uint8_t RESERVED2 : 2; - }; - }; -} stc_rtc_alhr_field_t; - -typedef struct stc_rtc_aldr_field -{ - union { - struct { - __IO uint8_t AD : 4; - __IO uint8_t TAD : 2; - uint8_t RESERVED1 : 2; - }; - struct { - __IO uint8_t AD0 : 1; - __IO uint8_t AD1 : 1; - __IO uint8_t AD2 : 1; - __IO uint8_t AD3 : 1; - __IO uint8_t TAD0 : 1; - __IO uint8_t TAD1 : 1; - uint8_t RESERVED2 : 2; - }; - }; -} stc_rtc_aldr_field_t; - -typedef struct stc_rtc_almor_field -{ - union { - struct { - __IO uint8_t AMO : 4; - __IO uint8_t TAMO : 1; - uint8_t RESERVED1 : 3; - }; - struct { - __IO uint8_t AMO0 : 1; - __IO uint8_t AMO1 : 1; - __IO uint8_t AMO2 : 1; - __IO uint8_t AMO3 : 1; - uint8_t RESERVED2 : 4; - }; - }; -} stc_rtc_almor_field_t; - -typedef struct stc_rtc_alyr_field -{ - union { - struct { - __IO uint8_t AY : 4; - __IO uint8_t TAY : 4; - }; - struct { - __IO uint8_t AY0 : 1; - __IO uint8_t AY1 : 1; - __IO uint8_t AY2 : 1; - __IO uint8_t AY3 : 1; - __IO uint8_t TAY0 : 1; - __IO uint8_t TAY1 : 1; - __IO uint8_t TAY2 : 1; - __IO uint8_t TAY3 : 1; - }; - }; -} stc_rtc_alyr_field_t; - -typedef struct stc_rtc_wttr0_field -{ - __IO uint8_t TM0 : 1; - __IO uint8_t TM1 : 1; - __IO uint8_t TM2 : 1; - __IO uint8_t TM3 : 1; - __IO uint8_t TM4 : 1; - __IO uint8_t TM5 : 1; - __IO uint8_t TM6 : 1; - __IO uint8_t TM7 : 1; -} stc_rtc_wttr0_field_t; - -typedef struct stc_rtc_wttr1_field -{ - __IO uint8_t TM8 : 1; - __IO uint8_t TM9 : 1; - __IO uint8_t TM10 : 1; - __IO uint8_t TM11 : 1; - __IO uint8_t TM12 : 1; - __IO uint8_t TM13 : 1; - __IO uint8_t TM14 : 1; - __IO uint8_t TM15 : 1; -} stc_rtc_wttr1_field_t; - -typedef struct stc_rtc_wttr2_field -{ - __IO uint8_t TM16 : 1; - __IO uint8_t TM17 : 1; - uint8_t RESERVED1 : 6; -} stc_rtc_wttr2_field_t; - -/* RTC CLK */ -typedef struct stc_rtc_wtcal1_field -{ - union { - struct { - __IO uint8_t WTCAL1 : 2; - uint8_t RESERVED1 : 6; - }; - struct { - __IO uint8_t WTCAL10 : 1; - __IO uint8_t WTCAL11 : 1; - uint8_t RESERVED2 : 6; - }; - }; -} stc_rtc_wtcal1_field_t; - -typedef struct stc_rtc_wtcalen_field -{ - __IO uint8_t WTCALEN : 1; - uint8_t RESERVED1 : 7; -} stc_rtc_wtcalen_field_t; - -typedef struct stc_rtc_wtdiv_field -{ - union { - struct { - __IO uint8_t WTDIV : 4; - uint8_t RESERVED1 : 4; - }; - struct { - __IO uint8_t WTDIV0 : 1; - __IO uint8_t WTDIV1 : 1; - __IO uint8_t WTDIV2 : 1; - __IO uint8_t WTDIV3 : 1; - uint8_t RESERVED2 : 4; - }; - }; -} stc_rtc_wtdiv_field_t; - -typedef struct stc_rtc_wtdiven_field -{ - __IO uint8_t WTDIVEN : 1; - __IO uint8_t WTDIVRDY : 1; - uint8_t RESERVED1 : 6; -} stc_rtc_wtdiven_field_t; - -typedef struct stc_rtc_wtcalprd_field -{ - union { - struct { - __IO uint8_t WTCALPRD : 6; - uint8_t RESERVED1 : 2; - }; - struct { - __IO uint8_t WTCALPRD0 : 1; - __IO uint8_t WTCALPRD1 : 1; - __IO uint8_t WTCALPRD2 : 1; - __IO uint8_t WTCALPRD3 : 1; - __IO uint8_t WTCALPRD4 : 1; - __IO uint8_t WTCALPRD5 : 1; - uint8_t RESERVED2 : 2; - }; - }; -} stc_rtc_wtcalprd_field_t; - -typedef struct stc_rtc_wtcosel_field -{ - __IO uint8_t WTCOSEL : 1; - __IO uint8_t WTDIVRDY : 7; -} stc_rtc_wtcosel_field_t; - -/* VBVat Domain */ -typedef struct stc_rtc_vb_clkdiv_field -{ - __IO uint8_t DIV : 8; -} stc_rtc_vb_clkdiv_field_t; - -typedef struct stc_rtc_wtosccnt_field -{ - __IO uint8_t SOSCEX : 1; - __IO uint8_t SOSCNTL : 1; -} stc_rtc_wtosccnt_field_t; - -typedef struct stc_rtc_boost_field -{ - __IO uint8_t BOOST : 2; -} stc_rtc_boost_field_t; - -typedef struct stc_rtc_ewkup_field -{ - __IO uint8_t WUP0 : 1; -} stc_rtc_ewkup_field_t; - -typedef struct stc_rtc_vdet_field -{ - uint8_t RESERVED0 : 7; - __IO uint8_t PON : 1; -} stc_rtc_vdet_field_t; - -typedef struct stc_rtc_hibrst_field -{ - __IO uint8_t HIBRST : 1; -} stc_rtc_hibrst_field_t; - -typedef struct stc_rtc_vbpfr_field -{ - __IO uint8_t VPFR0 : 1; - __IO uint8_t VPFR1 : 1; - __IO uint8_t VPFR2 : 1; - __IO uint8_t VPFR3 : 1; - __IO uint8_t SPSR0 : 1; - __IO uint8_t SPSR1 : 1; -} stc_rtc_vbpfr_field_t; - -typedef struct stc_rtc_vbpcr_field -{ - __IO uint8_t VPCR0 : 1; - __IO uint8_t VPCR1 : 1; - __IO uint8_t VPCR2 : 1; - __IO uint8_t VPCR3 : 1; -} stc_rtc_vbpcr_field_t; - -typedef struct stc_rtc_vbddr_field -{ - __IO uint8_t VDDR0 : 1; - __IO uint8_t VDDR1 : 1; - __IO uint8_t VDDR2 : 1; - __IO uint8_t VDDR3 : 1; -} stc_rtc_vbddr_field_t; - -typedef struct stc_rtc_vbdir_field -{ - __IO uint8_t VDIR0 : 1; - __IO uint8_t VDIR1 : 1; - __IO uint8_t VDIR2 : 1; - __IO uint8_t VDIR3 : 1; -} stc_rtc_vbdir_field_t; - -typedef struct stc_rtc_vbdor_field -{ - __IO uint8_t VDOR0 : 1; - __IO uint8_t VDOR1 : 1; - __IO uint8_t VDOR2 : 1; - __IO uint8_t VDOR3 : 1; -} stc_rtc_vbdor_field_t; - -typedef struct stc_rtc_vbpzr_field -{ - __IO uint8_t VPZR0 : 1; - __IO uint8_t VPZR1 : 1; -} stc_rtc_vbpzr_field_t; - -/****************************************************************************** - * LCR_MODULE - ******************************************************************************/ -/* LCR_MODULE register bit fields */ -typedef struct stc_lcr_lcr_prsld_field -{ - __IO uint8_t LCR_PRSLD : 6; -} stc_lcr_lcr_prsld_field_t; - -/****************************************************************************** - * CLK_GATING_MODULE - ******************************************************************************/ -/* CLK_GATING_MODULE register bit fields */ -typedef struct stc_clk_gating_cken0_field -{ - __IO uint32_t MFSCK0 : 1; - __IO uint32_t MFSCK1 : 1; - __IO uint32_t MFSCK2 : 1; - __IO uint32_t MFSCK3 : 1; - __IO uint32_t MFSCK4 : 1; - __IO uint32_t MFSCK5 : 1; - __IO uint32_t MFSCK6 : 1; - __IO uint32_t MFSCK7 : 1; - __IO uint32_t MFSCK8 : 1; - __IO uint32_t MFSCK9 : 1; - __IO uint32_t MFSCK10 : 1; - __IO uint32_t MFSCK11 : 1; - __IO uint32_t MFSCK12 : 1; - __IO uint32_t MFSCK13 : 1; - __IO uint32_t MFSCK14 : 1; - __IO uint32_t MFSCK15 : 1; - __IO uint32_t ADCCK0 : 1; - __IO uint32_t ADCCK1 : 1; - __IO uint32_t ADCCK2 : 1; - __IO uint32_t ADCCK3 : 1; - uint32_t RESERVED20 : 4; - __IO uint32_t DMACK : 1; - uint32_t RESERVED25 : 1; - __IO uint32_t EXBCK : 1; - uint32_t RESERVED27 : 1; - __IO uint32_t GIOCK : 1; -} stc_clk_gating_cken0_field_t; - -typedef struct stc_clk_gating_mrst0_field -{ - __IO uint32_t MFSRST0 : 1; - __IO uint32_t MFSRST1 : 1; - __IO uint32_t MFSRST2 : 1; - __IO uint32_t MFSRST3 : 1; - __IO uint32_t MFSRST4 : 1; - __IO uint32_t MFSRST5 : 1; - __IO uint32_t MFSRST6 : 1; - __IO uint32_t MFSRST7 : 1; - __IO uint32_t MFSRST8 : 1; - __IO uint32_t MFSRST9 : 1; - __IO uint32_t MFSRST10 : 1; - __IO uint32_t MFSRST11 : 1; - __IO uint32_t MFSRST12 : 1; - __IO uint32_t MFSRST13 : 1; - __IO uint32_t MFSRST14 : 1; - __IO uint32_t MFSRST15 : 1; - __IO uint32_t ADCRST0 : 1; - __IO uint32_t ADCRST1 : 1; - __IO uint32_t ADCRST2 : 1; - __IO uint32_t ADCRST3 : 1; - uint32_t RESERVED20 : 4; - __IO uint32_t DMARST : 1; - uint32_t RESERVED25 : 1; - __IO uint32_t EXBRST : 1; -} stc_clk_gating_mrst0_field_t; - -typedef struct stc_clk_gating_cken1_field -{ - __IO uint32_t BTMCK0 : 1; - __IO uint32_t BTMCK1 : 1; - __IO uint32_t BTMCK2 : 1; - __IO uint32_t BTMCK3 : 1; - uint32_t RESERVED4 : 4; - __IO uint32_t MFTCK0 : 1; - __IO uint32_t MFTCK1 : 1; - __IO uint32_t MFTCK2 : 1; - __IO uint32_t MFTCK3 : 1; - uint32_t RESERVED12 : 4; - __IO uint32_t QDUCK0 : 1; - __IO uint32_t QDUCK1 : 1; - __IO uint32_t QDUCK2 : 1; - __IO uint32_t QDUCK3 : 1; -} stc_clk_gating_cken1_field_t; - -typedef struct stc_clk_gating_mrst1_field -{ - __IO uint32_t BTMRST0 : 1; - __IO uint32_t BTMRST1 : 1; - __IO uint32_t BTMRST2 : 1; - __IO uint32_t BTMRST3 : 1; - uint32_t RESERVED4 : 4; - __IO uint32_t MFTRST0 : 1; - __IO uint32_t MFTRST1 : 1; - __IO uint32_t MFTRST2 : 1; - __IO uint32_t MFTRST3 : 1; - uint32_t RESERVED12 : 4; - __IO uint32_t QDURST0 : 1; - __IO uint32_t QDURST1 : 1; - __IO uint32_t QDURST2 : 1; - __IO uint32_t QDURST3 : 1; -} stc_clk_gating_mrst1_field_t; - -typedef struct stc_clk_gating_cken2_field -{ - __IO uint32_t USBCK0 : 1; - __IO uint32_t USBCK1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t CANCK0 : 1; - __IO uint32_t CANCK1 : 1; - uint32_t RESERVED6 : 2; - __IO uint32_t SDCCK : 1; -} stc_clk_gating_cken2_field_t; - -typedef struct stc_clk_gating_mrst2_field -{ - __IO uint32_t USBRST0 : 1; - __IO uint32_t USBRST1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t CANRST0 : 1; - __IO uint32_t CANRST1 : 1; - uint32_t RESERVED6 : 2; - __IO uint32_t SDCRST : 1; -} stc_clk_gating_mrst2_field_t; - - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* EXBUS_MODULE register bit fields */ -typedef struct stc_exbus_mode_field -{ - __IO uint32_t WDTH : 2; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; - uint32_t RESERVED : 18; -} stc_exbus_mode_field_t; - -typedef struct stc_exbus_tim_field -{ - __IO uint32_t RACC : 4; - __IO uint32_t RADC : 4; - __IO uint32_t FRADC : 4; - __IO uint32_t RIDLC : 4; - __IO uint32_t WACC : 4; - __IO uint32_t WADC : 4; - __IO uint32_t WWEC : 4; - __IO uint32_t WIDLC : 4; -} stc_exbus_tim_field_t; - -typedef struct stc_exbus_area_field -{ - __IO uint32_t ADDR : 8; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK : 7; - uint32_t RESERVED2 : 9; -} stc_exbus_area_field_t; - -typedef struct stc_exbus_atim_field -{ - __IO uint32_t ALC : 4; - __IO uint32_t ALES : 4; - __IO uint32_t ALEW : 4; - uint32_t RESERVED : 20; -} stc_exbus_atim_field_t; - -typedef struct stc_exbus_sdmode_field -{ - __IO uint32_t SDON : 1; - __IO uint32_t PDON : 1; - __IO uint32_t ROFF : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t CASEL : 2; - uint32_t RESERVED2 : 2; - __IO uint32_t RASEL : 4; - __IO uint32_t BASEL : 4; - __IO uint32_t MSDCLK : 1; - uint32_t RESERVED3 : 15; -} stc_exbus_sdmode_field_t; - -typedef struct stc_exbus_reftim_field -{ - __IO uint32_t REFC : 16; - __IO uint32_t NREF : 8; - __IO uint32_t PREF : 1; - uint32_t RESERVED : 7; -} stc_exbus_reftim_field_t; - -typedef struct stc_exbus_pwrdwn_field -{ - __IO uint32_t PDC : 16; - uint32_t RESERVED : 16; -} stc_exbus_pwrdwn_field_t; - -typedef struct stc_exbus_sdtim_field -{ - __IO uint32_t CL : 2; - uint32_t RESERVED1 : 2; - __IO uint32_t TRC : 4; - __IO uint32_t TRP : 4; - __IO uint32_t TRCD : 4; - __IO uint32_t TRAS : 4; - __IO uint32_t TREFC : 4; - __IO uint32_t TDPL : 2; - uint32_t RESERVED2 : 6; -} stc_exbus_sdtim_field_t; - -typedef struct stc_exbus_sdcmd_field -{ - __IO uint32_t SDAD : 16; - __IO uint32_t SDWE : 1; - __IO uint32_t SDCAS : 1; - __IO uint32_t SDRAS : 1; - __IO uint32_t SDCS : 1; - __IO uint32_t SDCKE : 1; - uint32_t RESERVED2 : 10; - __IO uint32_t PEND : 1; -} stc_exbus_sdcmd_field_t; - -typedef struct stc_exbus_memcerr_field -{ - __IO uint32_t SFER : 1; - __IO uint32_t SDER : 1; - __IO uint32_t SFION : 1; - __IO uint32_t SDION : 1; - uint32_t RESERVED : 28; -} stc_exbus_memcerr_field_t; - -typedef struct stc_exbus_dclkr_field -{ - __IO uint32_t MDIV : 4; - __IO uint32_t MCLKON : 1; - uint32_t RESERVED : 27; -} stc_exbus_dclkr_field_t; - -typedef struct stc_exbus_est_field -{ - __IO uint32_t WERR : 1; - uint32_t RESERVED : 31; -} stc_exbus_est_field_t; - -typedef struct stc_exbus_wead_field -{ - __IO uint32_t ADDR : 32; -} stc_exbus_wead_field_t; - -typedef struct stc_exbus_esclr_field -{ - __IO uint32_t WERRCLR : 1; - uint32_t RESERVED : 31; -} stc_exbus_esclr_field_t; - -typedef struct stc_exbus_amode_field -{ - __IO uint32_t WAEN : 1; - uint32_t RESERVED : 31; -} stc_exbus_amode_field_t; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB_MODULE register bit fields */ -typedef struct stc_usb_hcnt_field -{ - __IO uint16_t HOST : 1; - __IO uint16_t URST : 1; - __IO uint16_t SOFIRE : 1; - __IO uint16_t DIRE : 1; - __IO uint16_t CNNIRE : 1; - __IO uint16_t CMPIRE : 1; - __IO uint16_t URIRE : 1; - __IO uint16_t RWKIRE : 1; - __IO uint16_t RETRY : 1; - __IO uint16_t CANCEL : 1; - __IO uint16_t SOFSTEP : 1; -} stc_usb_hcnt_field_t; - -typedef struct stc_usb_hcnt0_field -{ - __IO uint8_t HOST : 1; - __IO uint8_t URST : 1; - __IO uint8_t SOFIRE : 1; - __IO uint8_t DIRE : 1; - __IO uint8_t CNNIRE : 1; - __IO uint8_t CMPIRE : 1; - __IO uint8_t URIRE : 1; - __IO uint8_t RWKIRE : 1; -} stc_usb_hcnt0_field_t; - -typedef struct stc_usb_hcnt1_field -{ - __IO uint8_t RETRY : 1; - __IO uint8_t CANCEL : 1; - __IO uint8_t SOFSTEP : 1; -} stc_usb_hcnt1_field_t; - -typedef struct stc_usb_hirq_field -{ - __IO uint8_t SOFIRQ : 1; - __IO uint8_t DIRQ : 1; - __IO uint8_t CNNIRQ : 1; - __IO uint8_t CMPIRQ : 1; - __IO uint8_t URIRQ : 1; - __IO uint8_t RWKIRQ : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TCAN : 1; -} stc_usb_hirq_field_t; - -typedef struct stc_usb_herr_field -{ - __IO uint8_t HS0 : 1; - __IO uint8_t HS1 : 1; - __IO uint8_t STUFF : 1; - __IO uint8_t TGERR : 1; - __IO uint8_t CRC : 1; - __IO uint8_t TOUT : 1; - __IO uint8_t RERR : 1; - __IO uint8_t LSTOF : 1; -} stc_usb_herr_field_t; - -typedef struct stc_usb_hstate_field -{ - __IO uint8_t CSTAT : 1; - __IO uint8_t TMODE : 1; - __IO uint8_t SUSP : 1; - __IO uint8_t SOFBUSY : 1; - __IO uint8_t CLKSEL : 1; - __IO uint8_t ALIVE : 1; -} stc_usb_hstate_field_t; - -typedef struct stc_usb_hfcomp_field -{ - __IO uint8_t FRAMECOMP0 : 1; - __IO uint8_t FRAMECOMP1 : 1; - __IO uint8_t FRAMECOMP2 : 1; - __IO uint8_t FRAMECOMP3 : 1; - __IO uint8_t FRAMECOMP4 : 1; - __IO uint8_t FRAMECOMP5 : 1; - __IO uint8_t FRAMECOMP6 : 1; - __IO uint8_t FRAMECOMP7 : 1; -} stc_usb_hfcomp_field_t; - -typedef struct stc_usb_hrtimer_field -{ - __IO uint16_t RTIMER0 : 1; - __IO uint16_t RTIMER1 : 1; - __IO uint16_t RTIMER2 : 1; - __IO uint16_t RTIMER3 : 1; - __IO uint16_t RTIMER4 : 1; - __IO uint16_t RTIMER5 : 1; - __IO uint16_t RTIMER6 : 1; - __IO uint16_t RTIMER7 : 1; - __IO uint16_t RTIMER8 : 1; - __IO uint16_t RTIMER9 : 1; - __IO uint16_t RTIMER10 : 1; - __IO uint16_t RTIMER11 : 1; - __IO uint16_t RTIMER12 : 1; - __IO uint16_t RTIMER13 : 1; - __IO uint16_t RTIMER14 : 1; - __IO uint16_t RTIMER15 : 1; -} stc_usb_hrtimer_field_t; - -typedef struct stc_usb_hrtimer0_field -{ - __IO uint8_t RTIMER00 : 1; - __IO uint8_t RTIMER01 : 1; - __IO uint8_t RTIMER02 : 1; - __IO uint8_t RTIMER03 : 1; - __IO uint8_t RTIMER04 : 1; - __IO uint8_t RTIMER05 : 1; - __IO uint8_t RTIMER06 : 1; - __IO uint8_t RTIMER07 : 1; -} stc_usb_hrtimer0_field_t; - -typedef struct stc_usb_hrtimer1_field -{ - __IO uint8_t RTIMER10 : 1; - __IO uint8_t RTIMER11 : 1; - __IO uint8_t RTIMER12 : 1; - __IO uint8_t RTIMER13 : 1; - __IO uint8_t RTIMER14 : 1; - __IO uint8_t RTIMER15 : 1; - __IO uint8_t RTIMER16 : 1; - __IO uint8_t RTIMER17 : 1; -} stc_usb_hrtimer1_field_t; - -typedef struct stc_usb_hrtimer2_field -{ - __IO uint8_t RTIMER20 : 1; - __IO uint8_t RTIMER21 : 1; - __IO uint8_t RTIMER22 : 1; -} stc_usb_hrtimer2_field_t; - -typedef struct stc_usb_hadr_field -{ - __IO uint8_t ADDRESS0 : 1; - __IO uint8_t ADDRESS1 : 1; - __IO uint8_t ADDRESS2 : 1; - __IO uint8_t ADDRESS3 : 1; - __IO uint8_t ADDRESS4 : 1; - __IO uint8_t ADDRESS5 : 1; - __IO uint8_t ADDRESS6 : 1; -} stc_usb_hadr_field_t; - -typedef struct stc_usb_heof_field -{ - __IO uint16_t EOF0 : 1; - __IO uint16_t EOF1 : 1; - __IO uint16_t EOF2 : 1; - __IO uint16_t EOF3 : 1; - __IO uint16_t EOF4 : 1; - __IO uint16_t EOF5 : 1; - __IO uint16_t EOF6 : 1; - __IO uint16_t EOF7 : 1; - __IO uint16_t EOF8 : 1; - __IO uint16_t EOF9 : 1; - __IO uint16_t EOF10 : 1; - __IO uint16_t EOF11 : 1; - __IO uint16_t EOF12 : 1; - __IO uint16_t EOF13 : 1; - __IO uint16_t EOF14 : 1; - __IO uint16_t EOF15 : 1; -} stc_usb_heof_field_t; - -typedef struct stc_usb_heof0_field -{ - __IO uint8_t EOF00 : 1; - __IO uint8_t EOF01 : 1; - __IO uint8_t EOF02 : 1; - __IO uint8_t EOF03 : 1; - __IO uint8_t EOF04 : 1; - __IO uint8_t EOF05 : 1; - __IO uint8_t EOF06 : 1; - __IO uint8_t EOF07 : 1; -} stc_usb_heof0_field_t; - -typedef struct stc_usb_heof1_field -{ - __IO uint8_t EOF10 : 1; - __IO uint8_t EOF11 : 1; - __IO uint8_t EOF12 : 1; - __IO uint8_t EOF13 : 1; - __IO uint8_t EOF14 : 1; - __IO uint8_t EOF15 : 1; -} stc_usb_heof1_field_t; - -typedef struct stc_usb_hframe_field -{ - __IO uint16_t FRAME0 : 1; - __IO uint16_t FRAME1 : 1; - __IO uint16_t FRAME2 : 1; - __IO uint16_t FRAME3 : 1; - __IO uint16_t FRAME4 : 1; - __IO uint16_t FRAME5 : 1; - __IO uint16_t FRAME6 : 1; - __IO uint16_t FRAME7 : 1; - __IO uint16_t FRAME8 : 1; - __IO uint16_t FRAME9 : 1; - __IO uint16_t FRAME10 : 1; -} stc_usb_hframe_field_t; - -typedef struct stc_usb_hframe0_field -{ - __IO uint8_t FRAME00 : 1; - __IO uint8_t FRAME01 : 1; - __IO uint8_t FRAME02 : 1; - __IO uint8_t FRAME03 : 1; - __IO uint8_t FRAME04 : 1; - __IO uint8_t FRAME05 : 1; - __IO uint8_t FRAME06 : 1; - __IO uint8_t FRAME07 : 1; -} stc_usb_hframe0_field_t; - -typedef struct stc_usb_hframe1_field -{ - __IO uint8_t FRAME10 : 1; - __IO uint8_t FRAME11 : 1; - __IO uint8_t FRAME12 : 1; - __IO uint8_t FRAME13 : 1; -} stc_usb_hframe1_field_t; - -typedef struct stc_usb_htoken_field -{ - __IO uint8_t ENDPT0 : 1; - __IO uint8_t ENDPT1 : 1; - __IO uint8_t ENDPT2 : 1; - __IO uint8_t ENDPT3 : 1; - __IO uint8_t TKNEN0 : 1; - __IO uint8_t TKNEN1 : 1; - __IO uint8_t TKNEN2 : 1; - __IO uint8_t TGGL : 1; -} stc_usb_htoken_field_t; - -typedef struct stc_usb_udcc_field -{ - __IO uint16_t PWC : 1; - __IO uint16_t RFBK : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t STALCLREN : 1; - __IO uint16_t USTP : 1; - __IO uint16_t HCONX : 1; - __IO uint16_t RESUM : 1; - __IO uint16_t RST : 1; -} stc_usb_udcc_field_t; - -typedef struct stc_usb_ep0c_field -{ - __IO uint16_t PKS00 : 1; - __IO uint16_t PKS01 : 1; - __IO uint16_t PKS02 : 1; - __IO uint16_t PKS03 : 1; - __IO uint16_t PKS04 : 1; - __IO uint16_t PKS05 : 1; - __IO uint16_t PKS06 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; -} stc_usb_ep0c_field_t; - -typedef struct stc_usb_ep1c_field -{ - __IO uint16_t PKS10 : 1; - __IO uint16_t PKS11 : 1; - __IO uint16_t PKS12 : 1; - __IO uint16_t PKS13 : 1; - __IO uint16_t PKS14 : 1; - __IO uint16_t PKS15 : 1; - __IO uint16_t PKS16 : 1; - __IO uint16_t PKS17 : 1; - __IO uint16_t PKS18 : 1; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep1c_field_t; - -typedef struct stc_usb_ep2c_field -{ - __IO uint16_t PKS20 : 1; - __IO uint16_t PKS21 : 1; - __IO uint16_t PKS22 : 1; - __IO uint16_t PKS23 : 1; - __IO uint16_t PKS24 : 1; - __IO uint16_t PKS25 : 1; - __IO uint16_t PKS26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep2c_field_t; - -typedef struct stc_usb_ep3c_field -{ - __IO uint16_t PKS30 : 1; - __IO uint16_t PKS31 : 1; - __IO uint16_t PKS32 : 1; - __IO uint16_t PKS33 : 1; - __IO uint16_t PKS34 : 1; - __IO uint16_t PKS35 : 1; - __IO uint16_t PKS36 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep3c_field_t; - -typedef struct stc_usb_ep4c_field -{ - __IO uint16_t PKS40 : 1; - __IO uint16_t PKS41 : 1; - __IO uint16_t PKS42 : 1; - __IO uint16_t PKS43 : 1; - __IO uint16_t PKS44 : 1; - __IO uint16_t PKS45 : 1; - __IO uint16_t PKS46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep4c_field_t; - -typedef struct stc_usb_ep5c_field -{ - __IO uint16_t PKS50 : 1; - __IO uint16_t PKS51 : 1; - __IO uint16_t PKS52 : 1; - __IO uint16_t PKS53 : 1; - __IO uint16_t PKS54 : 1; - __IO uint16_t PKS55 : 1; - __IO uint16_t PKS56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep5c_field_t; - -typedef struct stc_usb_tmsp_field -{ - __IO uint16_t TMSP0 : 1; - __IO uint16_t TMSP1 : 1; - __IO uint16_t TMSP2 : 1; - __IO uint16_t TMSP3 : 1; - __IO uint16_t TMSP4 : 1; - __IO uint16_t TMSP5 : 1; - __IO uint16_t TMSP6 : 1; - __IO uint16_t TMSP7 : 1; - __IO uint16_t TMSP8 : 1; - __IO uint16_t TMSP9 : 1; - __IO uint16_t TMSP10 : 1; -} stc_usb_tmsp_field_t; - -typedef struct stc_usb_udcs_field -{ - __IO uint8_t CONF : 1; - __IO uint8_t SETP : 1; - __IO uint8_t WKUP : 1; - __IO uint8_t BRST : 1; - __IO uint8_t SOF : 1; - __IO uint8_t SUSP : 1; -} stc_usb_udcs_field_t; - -typedef struct stc_usb_udcie_field -{ - __IO uint8_t CONFIE : 1; - __IO uint8_t CONFN : 1; - __IO uint8_t WKUPIE : 1; - __IO uint8_t BRSTIE : 1; - __IO uint8_t SOFIE : 1; - __IO uint8_t SUSPIE : 1; -} stc_usb_udcie_field_t; - -typedef struct stc_usb_ep0is_field -{ - uint16_t RESERVED1 : 10; - __IO uint16_t DRQI : 1; - uint16_t RESERVED2 : 3; - __IO uint16_t DRQIIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0is_field_t; - -typedef struct stc_usb_ep0os_field -{ - __IO uint16_t SIZE0 : 1; - __IO uint16_t SIZE1 : 1; - __IO uint16_t SIZE2 : 1; - __IO uint16_t SIZE3 : 1; - __IO uint16_t SIZE4 : 1; - __IO uint16_t SIZE5 : 1; - __IO uint16_t SIZE6 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQO : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQOIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0os_field_t; - -typedef struct stc_usb_ep1s_field -{ - __IO uint16_t SIZE10 : 1; - __IO uint16_t SIZE11 : 1; - __IO uint16_t SIZE12 : 1; - __IO uint16_t SIZE13 : 1; - __IO uint16_t SIZE14 : 1; - __IO uint16_t SIZE15 : 1; - __IO uint16_t SIZE16 : 1; - __IO uint16_t SIZE17 : 1; - __IO uint16_t SIZE18 : 1; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep1s_field_t; - -typedef struct stc_usb_ep2s_field -{ - __IO uint16_t SIZE20 : 1; - __IO uint16_t SIZE21 : 1; - __IO uint16_t SIZE22 : 1; - __IO uint16_t SIZE23 : 1; - __IO uint16_t SIZE24 : 1; - __IO uint16_t SIZE25 : 1; - __IO uint16_t SIZE26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep2s_field_t; - -typedef struct stc_usb_ep4s_field -{ - __IO uint16_t SIZE40 : 1; - __IO uint16_t SIZE41 : 1; - __IO uint16_t SIZE42 : 1; - __IO uint16_t SIZE43 : 1; - __IO uint16_t SIZE44 : 1; - __IO uint16_t SIZE45 : 1; - __IO uint16_t SIZE46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep4s_field_t; - -typedef struct stc_usb_ep5s_field -{ - __IO uint16_t SIZE50 : 1; - __IO uint16_t SIZE51 : 1; - __IO uint16_t SIZE52 : 1; - __IO uint16_t SIZE53 : 1; - __IO uint16_t SIZE54 : 1; - __IO uint16_t SIZE55 : 1; - __IO uint16_t SIZE56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep5s_field_t; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMAC_MODULE register bit fields */ -typedef struct stc_dmac_dmacr_field -{ - uint32_t RESERVED1 : 24; - __IO uint32_t DH0 : 1; - __IO uint32_t DH1 : 1; - __IO uint32_t DH2 : 1; - __IO uint32_t DH3 : 1; - __IO uint32_t PR : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t DS : 1; - __IO uint32_t DE : 1; -} stc_dmac_dmacr_field_t; - -typedef struct stc_dmac_dmaca0_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca0_field_t; - -typedef struct stc_dmac_dmacb0_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb0_field_t; - -typedef struct stc_dmac_dmaca1_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca1_field_t; - -typedef struct stc_dmac_dmacb1_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb1_field_t; - -typedef struct stc_dmac_dmaca2_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca2_field_t; - -typedef struct stc_dmac_dmacb2_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb2_field_t; - -typedef struct stc_dmac_dmaca3_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca3_field_t; - -typedef struct stc_dmac_dmacb3_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb3_field_t; - -typedef struct stc_dmac_dmaca4_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca4_field_t; - -typedef struct stc_dmac_dmacb4_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb4_field_t; - -typedef struct stc_dmac_dmaca5_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca5_field_t; - -typedef struct stc_dmac_dmacb5_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb5_field_t; - -typedef struct stc_dmac_dmaca6_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca6_field_t; - -typedef struct stc_dmac_dmacb6_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb6_field_t; - -typedef struct stc_dmac_dmaca7_field -{ - __IO uint32_t TC : 16; - __IO uint32_t BC : 4; - uint32_t RESERVED1 : 3; - __IO uint32_t IS : 6; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca7_field_t; - -typedef struct stc_dmac_dmacb7_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS : 3; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW : 2; - __IO uint32_t MS : 2; -} stc_dmac_dmacb7_field_t; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN_MODULE register bit fields */ -typedef struct stc_can_ctrlr_field -{ - __IO uint16_t INIT : 1; - __IO uint16_t IE : 1; - __IO uint16_t SIE : 1; - __IO uint16_t EIE : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t DAR : 1; - __IO uint16_t CCE : 1; - __IO uint16_t TEST : 1; -} stc_can_ctrlr_field_t; - -typedef struct stc_can_statr_field -{ - __IO uint16_t LEC : 3; - __IO uint16_t TXOK : 1; - __IO uint16_t RXOK : 1; - __IO uint16_t EPASS : 1; - __IO uint16_t EWARN : 1; - __IO uint16_t BOFF : 1; -} stc_can_statr_field_t; - -typedef struct stc_can_errcnt_field -{ - __IO uint16_t TEC0 : 1; - __IO uint16_t TEC1 : 1; - __IO uint16_t TEC2 : 1; - __IO uint16_t TEC3 : 1; - __IO uint16_t TEC4 : 1; - __IO uint16_t TEC5 : 1; - __IO uint16_t TEC6 : 1; - __IO uint16_t TEC7 : 1; - __IO uint16_t REC0 : 1; - __IO uint16_t REC1 : 1; - __IO uint16_t REC2 : 1; - __IO uint16_t REC3 : 1; - __IO uint16_t REC4 : 1; - __IO uint16_t REC5 : 1; - __IO uint16_t REC6 : 1; - __IO uint16_t RP : 1; -} stc_can_errcnt_field_t; - -typedef struct stc_can_btr_field -{ - __IO uint16_t BRP : 6; - __IO uint16_t SJW : 2; - __IO uint16_t TSEG1 : 4; - __IO uint16_t TSEG2 : 3; -} stc_can_btr_field_t; - -typedef struct stc_can_intr_field -{ - __IO uint16_t INTID0 : 1; - __IO uint16_t INTID1 : 1; - __IO uint16_t INTID2 : 1; - __IO uint16_t INTID3 : 1; - __IO uint16_t INTID4 : 1; - __IO uint16_t INTID5 : 1; - __IO uint16_t INTID6 : 1; - __IO uint16_t INTID7 : 1; - __IO uint16_t INTID8 : 1; - __IO uint16_t INTID9 : 1; - __IO uint16_t INTID10 : 1; - __IO uint16_t INTID11 : 1; - __IO uint16_t INTID12 : 1; - __IO uint16_t INTID13 : 1; - __IO uint16_t INTID14 : 1; - __IO uint16_t INTID15 : 1; -} stc_can_intr_field_t; - -typedef struct stc_can_testr_field -{ - uint16_t RESERVED1 : 2; - __IO uint16_t BASIC : 1; - __IO uint16_t SILENT : 1; - __IO uint16_t LBACK : 1; - __IO uint16_t TX0 : 1; - __IO uint16_t TX1 : 1; - __IO uint16_t RX : 1; -} stc_can_testr_field_t; - -typedef struct stc_can_brper_field -{ - __IO uint16_t BRPE0 : 1; - __IO uint16_t BRPE1 : 1; - __IO uint16_t BRPE2 : 1; - __IO uint16_t BRPE3 : 1; -} stc_can_brper_field_t; - -typedef struct stc_can_if1creq_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t BUSY : 1; -} stc_can_if1creq_field_t; - -typedef struct stc_can_if1cmsk_field -{ - __IO uint16_t DATAB : 1; - __IO uint16_t DATAA : 1; - __IO uint16_t NEWDAT : 1; - __IO uint16_t CIP : 1; - __IO uint16_t CONTROL : 1; - __IO uint16_t ARB : 1; - __IO uint16_t MASK : 1; - __IO uint16_t WRRD : 1; -} stc_can_if1cmsk_field_t; - -typedef struct stc_can_if1msk_field -{ - __IO uint32_t MSK : 29; - uint32_t RESERVED1 : 1; - __IO uint32_t MDIR : 1; - __IO uint32_t MXTD : 1; -} stc_can_if1msk_field_t; - -typedef struct stc_can_if1msk2_field -{ - uint16_t RESERVED1 : 14; - __IO uint16_t MDIR : 1; - __IO uint16_t MXTD : 1; -} stc_can_if1msk2_field_t; - -typedef struct stc_can_if1arb_field -{ - __IO uint32_t ID : 29; - __IO uint32_t DIR : 1; - __IO uint32_t XTD : 1; - __IO uint32_t MSGVAL : 1; -} stc_can_if1arb_field_t; - -typedef struct stc_can_if1arb2_field -{ - uint16_t RESERVED1 : 13; - __IO uint16_t DIR : 1; - __IO uint16_t XTD : 1; - __IO uint16_t MSGVAL : 1; -} stc_can_if1arb2_field_t; - -typedef struct stc_can_if1mctr_field -{ - __IO uint16_t DLC : 4; - uint16_t RESERVED1 : 3; - __IO uint16_t EOB : 1; - __IO uint16_t TXRQST : 1; - __IO uint16_t RMTEN : 1; - __IO uint16_t RXIE : 1; - __IO uint16_t TXIE : 1; - __IO uint16_t UMASK : 1; - __IO uint16_t INTPND : 1; - __IO uint16_t MSGLST : 1; - __IO uint16_t NEWDAT : 1; -} stc_can_if1mctr_field_t; - -typedef struct stc_can_if2creq_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t BUSY : 1; -} stc_can_if2creq_field_t; - -typedef struct stc_can_if2cmsk_field -{ - __IO uint16_t DATAB : 1; - __IO uint16_t DATAA : 1; - __IO uint16_t NEWDAT : 1; - __IO uint16_t CIP : 1; - __IO uint16_t CONTROL : 1; - __IO uint16_t ARB : 1; - __IO uint16_t MASK : 1; - __IO uint16_t WRRD : 1; -} stc_can_if2cmsk_field_t; - -typedef struct stc_can_if2msk_field -{ - uint32_t RESERVED1 : 30; - __IO uint32_t MDIR : 1; - __IO uint32_t MXTD : 1; -} stc_can_if2msk_field_t; - -typedef struct stc_can_if2msk2_field -{ - uint16_t RESERVED1 : 14; - __IO uint16_t MDIR : 1; - __IO uint16_t MXTD : 1; -} stc_can_if2msk2_field_t; - -typedef struct stc_can_if2arb2_field -{ - uint16_t RESERVED1 : 13; - __IO uint16_t DIR : 1; - __IO uint16_t XTD : 1; - __IO uint16_t MSGVAL : 1; -} stc_can_if2arb2_field_t; - -typedef struct stc_can_if2mctr_field -{ - __IO uint16_t DLC : 4; - uint16_t RESERVED1 : 3; - __IO uint16_t EOB : 1; - __IO uint16_t TXRQST : 1; - __IO uint16_t RMTEN : 1; - __IO uint16_t RXIE : 1; - __IO uint16_t TXIE : 1; - __IO uint16_t UMASK : 1; - __IO uint16_t INTPND : 1; - __IO uint16_t MSGLST : 1; - __IO uint16_t NEWDAT : 1; -} stc_can_if2mctr_field_t; - -typedef struct stc_can_treqr_field -{ - __IO uint32_t TXRQST1 : 1; - __IO uint32_t TXRQST2 : 1; - __IO uint32_t TXRQST3 : 1; - __IO uint32_t TXRQST4 : 1; - __IO uint32_t TXRQST5 : 1; - __IO uint32_t TXRQST6 : 1; - __IO uint32_t TXRQST7 : 1; - __IO uint32_t TXRQST8 : 1; - __IO uint32_t TXRQST9 : 1; - __IO uint32_t TXRQST10 : 1; - __IO uint32_t TXRQST11 : 1; - __IO uint32_t TXRQST12 : 1; - __IO uint32_t TXRQST13 : 1; - __IO uint32_t TXRQST14 : 1; - __IO uint32_t TXRQST15 : 1; - __IO uint32_t TXRQST16 : 1; - __IO uint32_t TXRQST17 : 1; - __IO uint32_t TXRQST18 : 1; - __IO uint32_t TXRQST19 : 1; - __IO uint32_t TXRQST20 : 1; - __IO uint32_t TXRQST21 : 1; - __IO uint32_t TXRQST22 : 1; - __IO uint32_t TXRQST23 : 1; - __IO uint32_t TXRQST24 : 1; - __IO uint32_t TXRQST25 : 1; - __IO uint32_t TXRQST26 : 1; - __IO uint32_t TXRQST27 : 1; - __IO uint32_t TXRQST28 : 1; - __IO uint32_t TXRQST29 : 1; - __IO uint32_t TXRQST30 : 1; - __IO uint32_t TXRQST31 : 1; - __IO uint32_t TXRQST32 : 1; -} stc_can_treqr_field_t; - -typedef struct stc_can_treqr1_field -{ - __IO uint16_t TXRQST1 : 1; - __IO uint16_t TXRQST2 : 1; - __IO uint16_t TXRQST3 : 1; - __IO uint16_t TXRQST4 : 1; - __IO uint16_t TXRQST5 : 1; - __IO uint16_t TXRQST6 : 1; - __IO uint16_t TXRQST7 : 1; - __IO uint16_t TXRQST8 : 1; - __IO uint16_t TXRQST9 : 1; - __IO uint16_t TXRQST10 : 1; - __IO uint16_t TXRQST11 : 1; - __IO uint16_t TXRQST12 : 1; - __IO uint16_t TXRQST13 : 1; - __IO uint16_t TXRQST14 : 1; - __IO uint16_t TXRQST15 : 1; - __IO uint16_t TXRQST16 : 1; -} stc_can_treqr1_field_t; - -typedef struct stc_can_treqr2_field -{ - __IO uint16_t TXRQST17 : 1; - __IO uint16_t TXRQST18 : 1; - __IO uint16_t TXRQST19 : 1; - __IO uint16_t TXRQST20 : 1; - __IO uint16_t TXRQST21 : 1; - __IO uint16_t TXRQST22 : 1; - __IO uint16_t TXRQST23 : 1; - __IO uint16_t TXRQST24 : 1; - __IO uint16_t TXRQST25 : 1; - __IO uint16_t TXRQST26 : 1; - __IO uint16_t TXRQST27 : 1; - __IO uint16_t TXRQST28 : 1; - __IO uint16_t TXRQST29 : 1; - __IO uint16_t TXRQST30 : 1; - __IO uint16_t TXRQST31 : 1; - __IO uint16_t TXRQST32 : 1; -} stc_can_treqr2_field_t; - -typedef struct stc_can_newdt_field -{ - __IO uint32_t NEWDAT1 : 1; - __IO uint32_t NEWDAT2 : 1; - __IO uint32_t NEWDAT3 : 1; - __IO uint32_t NEWDAT4 : 1; - __IO uint32_t NEWDAT5 : 1; - __IO uint32_t NEWDAT6 : 1; - __IO uint32_t NEWDAT7 : 1; - __IO uint32_t NEWDAT8 : 1; - __IO uint32_t NEWDAT9 : 1; - __IO uint32_t NEWDAT10 : 1; - __IO uint32_t NEWDAT11 : 1; - __IO uint32_t NEWDAT12 : 1; - __IO uint32_t NEWDAT13 : 1; - __IO uint32_t NEWDAT14 : 1; - __IO uint32_t NEWDAT15 : 1; - __IO uint32_t NEWDAT16 : 1; - __IO uint32_t NEWDAT17 : 1; - __IO uint32_t NEWDAT18 : 1; - __IO uint32_t NEWDAT19 : 1; - __IO uint32_t NEWDAT20 : 1; - __IO uint32_t NEWDAT21 : 1; - __IO uint32_t NEWDAT22 : 1; - __IO uint32_t NEWDAT23 : 1; - __IO uint32_t NEWDAT24 : 1; - __IO uint32_t NEWDAT25 : 1; - __IO uint32_t NEWDAT26 : 1; - __IO uint32_t NEWDAT27 : 1; - __IO uint32_t NEWDAT28 : 1; - __IO uint32_t NEWDAT29 : 1; - __IO uint32_t NEWDAT30 : 1; - __IO uint32_t NEWDAT31 : 1; - __IO uint32_t NEWDAT32 : 1; -} stc_can_newdt_field_t; - -typedef struct stc_can_newdt1_field -{ - __IO uint16_t NEWDAT1 : 1; - __IO uint16_t NEWDAT2 : 1; - __IO uint16_t NEWDAT3 : 1; - __IO uint16_t NEWDAT4 : 1; - __IO uint16_t NEWDAT5 : 1; - __IO uint16_t NEWDAT6 : 1; - __IO uint16_t NEWDAT7 : 1; - __IO uint16_t NEWDAT8 : 1; - __IO uint16_t NEWDAT9 : 1; - __IO uint16_t NEWDAT10 : 1; - __IO uint16_t NEWDAT11 : 1; - __IO uint16_t NEWDAT12 : 1; - __IO uint16_t NEWDAT13 : 1; - __IO uint16_t NEWDAT14 : 1; - __IO uint16_t NEWDAT15 : 1; - __IO uint16_t NEWDAT16 : 1; -} stc_can_newdt1_field_t; - -typedef struct stc_can_intpnd_field -{ - __IO uint32_t INTPND1 : 1; - __IO uint32_t INTPND2 : 1; - __IO uint32_t INTPND3 : 1; - __IO uint32_t INTPND4 : 1; - __IO uint32_t INTPND5 : 1; - __IO uint32_t INTPND6 : 1; - __IO uint32_t INTPND7 : 1; - __IO uint32_t INTPND8 : 1; - __IO uint32_t INTPND9 : 1; - __IO uint32_t INTPND10 : 1; - __IO uint32_t INTPND11 : 1; - __IO uint32_t INTPND12 : 1; - __IO uint32_t INTPND13 : 1; - __IO uint32_t INTPND14 : 1; - __IO uint32_t INTPND15 : 1; - __IO uint32_t INTPND16 : 1; - __IO uint32_t INTPND17 : 1; - __IO uint32_t INTPND18 : 1; - __IO uint32_t INTPND19 : 1; - __IO uint32_t INTPND20 : 1; - __IO uint32_t INTPND21 : 1; - __IO uint32_t INTPND22 : 1; - __IO uint32_t INTPND23 : 1; - __IO uint32_t INTPND24 : 1; - __IO uint32_t INTPND25 : 1; - __IO uint32_t INTPND26 : 1; - __IO uint32_t INTPND27 : 1; - __IO uint32_t INTPND28 : 1; - __IO uint32_t INTPND29 : 1; - __IO uint32_t INTPND30 : 1; - __IO uint32_t INTPND31 : 1; - __IO uint32_t INTPND32 : 1; -} stc_can_intpnd_field_t; - -typedef struct stc_can_intpnd1_field -{ - __IO uint16_t INTPND1 : 1; - __IO uint16_t INTPND2 : 1; - __IO uint16_t INTPND3 : 1; - __IO uint16_t INTPND4 : 1; - __IO uint16_t INTPND5 : 1; - __IO uint16_t INTPND6 : 1; - __IO uint16_t INTPND7 : 1; - __IO uint16_t INTPND8 : 1; - __IO uint16_t INTPND9 : 1; - __IO uint16_t INTPND10 : 1; - __IO uint16_t INTPND11 : 1; - __IO uint16_t INTPND12 : 1; - __IO uint16_t INTPND13 : 1; - __IO uint16_t INTPND14 : 1; - __IO uint16_t INTPND15 : 1; - __IO uint16_t INTPND16 : 1; -} stc_can_intpnd1_field_t; - -typedef struct stc_can_intpnd2_field -{ - __IO uint16_t INTPND17 : 1; - __IO uint16_t INTPND18 : 1; - __IO uint16_t INTPND19 : 1; - __IO uint16_t INTPND20 : 1; - __IO uint16_t INTPND21 : 1; - __IO uint16_t INTPND22 : 1; - __IO uint16_t INTPND23 : 1; - __IO uint16_t INTPND24 : 1; - __IO uint16_t INTPND25 : 1; - __IO uint16_t INTPND26 : 1; - __IO uint16_t INTPND27 : 1; - __IO uint16_t INTPND28 : 1; - __IO uint16_t INTPND29 : 1; - __IO uint16_t INTPND30 : 1; - __IO uint16_t INTPND31 : 1; - __IO uint16_t INTPND32 : 1; -} stc_can_intpnd2_field_t; - -typedef struct stc_can_msgval_field -{ - __IO uint32_t MSGVAL1 : 1; - __IO uint32_t MSGVAL2 : 1; - __IO uint32_t MSGVAL3 : 1; - __IO uint32_t MSGVAL4 : 1; - __IO uint32_t MSGVAL5 : 1; - __IO uint32_t MSGVAL6 : 1; - __IO uint32_t MSGVAL7 : 1; - __IO uint32_t MSGVAL8 : 1; - __IO uint32_t MSGVAL9 : 1; - __IO uint32_t MSGVAL10 : 1; - __IO uint32_t MSGVAL11 : 1; - __IO uint32_t MSGVAL12 : 1; - __IO uint32_t MSGVAL13 : 1; - __IO uint32_t MSGVAL14 : 1; - __IO uint32_t MSGVAL15 : 1; - __IO uint32_t MSGVAL16 : 1; - __IO uint32_t MSGVAL17 : 1; - __IO uint32_t MSGVAL18 : 1; - __IO uint32_t MSGVAL19 : 1; - __IO uint32_t MSGVAL20 : 1; - __IO uint32_t MSGVAL21 : 1; - __IO uint32_t MSGVAL22 : 1; - __IO uint32_t MSGVAL23 : 1; - __IO uint32_t MSGVAL24 : 1; - __IO uint32_t MSGVAL25 : 1; - __IO uint32_t MSGVAL26 : 1; - __IO uint32_t MSGVAL27 : 1; - __IO uint32_t MSGVAL28 : 1; - __IO uint32_t MSGVAL29 : 1; - __IO uint32_t MSGVAL30 : 1; - __IO uint32_t MSGVAL31 : 1; - __IO uint32_t MSGVAL32 : 1; -} stc_can_msgval_field_t; - -typedef struct stc_can_msgval1_field -{ - __IO uint16_t MSGVAL1 : 1; - __IO uint16_t MSGVAL2 : 1; - __IO uint16_t MSGVAL3 : 1; - __IO uint16_t MSGVAL4 : 1; - __IO uint16_t MSGVAL5 : 1; - __IO uint16_t MSGVAL6 : 1; - __IO uint16_t MSGVAL7 : 1; - __IO uint16_t MSGVAL8 : 1; - __IO uint16_t MSGVAL9 : 1; - __IO uint16_t MSGVAL10 : 1; - __IO uint16_t MSGVAL11 : 1; - __IO uint16_t MSGVAL12 : 1; - __IO uint16_t MSGVAL13 : 1; - __IO uint16_t MSGVAL14 : 1; - __IO uint16_t MSGVAL15 : 1; - __IO uint16_t MSGVAL16 : 1; -} stc_can_msgval1_field_t; - -typedef struct stc_can_msgval2_field -{ - __IO uint16_t MSGVAL17 : 1; - __IO uint16_t MSGVAL18 : 1; - __IO uint16_t MSGVAL19 : 1; - __IO uint16_t MSGVAL20 : 1; - __IO uint16_t MSGVAL21 : 1; - __IO uint16_t MSGVAL22 : 1; - __IO uint16_t MSGVAL23 : 1; - __IO uint16_t MSGVAL24 : 1; - __IO uint16_t MSGVAL25 : 1; - __IO uint16_t MSGVAL26 : 1; - __IO uint16_t MSGVAL27 : 1; - __IO uint16_t MSGVAL28 : 1; - __IO uint16_t MSGVAL29 : 1; - __IO uint16_t MSGVAL30 : 1; - __IO uint16_t MSGVAL31 : 1; - __IO uint16_t MSGVAL32 : 1; -} stc_can_msgval2_field_t; - -/****************************************************************************** - * SDIF_MODULE - ******************************************************************************/ -/* SDIF_MODULE register bit fields */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/****************************************************************************** - * Peripheral register structures - ******************************************************************************/ - -/****************************************************************************** - * WorkFlash_IF_MODULE - ******************************************************************************/ -/* WorkFlash interface registers */ -typedef struct -{ - union { - __IO uint32_t WFASZR; - stc_workflash_if_wfaszr_field_t WFASZR_f; - }; - union { - __IO uint32_t WFRWTR; - stc_workflash_if_wfrwtr_field_t WFRWTR_f; - }; - union { - __IO uint32_t WFSTR; - stc_workflash_if_wfstr_field_t WFSTR_f; - }; -}FM4_WORKFLASH_IF_TypeDef; - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - union { - __IO uint32_t FASZR; - stc_flash_if_faszr_field_t FASZR_f; - }; - union { - __IO uint32_t FRWTR; - stc_flash_if_frwtr_field_t FRWTR_f; - }; - union { - __IO uint32_t FSTR; - stc_flash_if_fstr_field_t FSTR_f; - }; - uint8_t RESERVED2[4]; - union { - __IO uint32_t FSYNDN; - stc_flash_if_fsyndn_field_t FSYNDN_f; - }; - union { - __IO uint32_t FBFCR; - stc_flash_if_fbfcr_field_t FBFCR_f; - }; - uint8_t RESERVED4[8]; - union { - __IO uint32_t FICR; - stc_flash_if_ficr_field_t FICR_f; - }; - union { - __IO uint32_t FISR; - stc_flash_if_fisr_field_t FISR_f; - }; - union { - __IO uint32_t FICLR; - stc_flash_if_ficlr_field_t FICLR_f; - }; - uint8_t RESERVED7[212]; - union { - __IO uint32_t CRTRMM; - stc_flash_if_crtrmm_field_t CRTRMM_f; - }; -}FM4_FLASH_IF_TypeDef; - -/****************************************************************************** - * UNIQUE_ID_MODULE - ******************************************************************************/ -/* Unique ID registers */ -typedef struct -{ - union { - __IO uint32_t UIDR0; - stc_unique_id_uidr0_field_t UIDR0_f; - }; - union { - __IO uint32_t UIDR1; - stc_unique_id_uidr1_field_t UIDR1_f; - }; -}FM4_UNIQUE_ID_TypeDef; - -/****************************************************************************** - * ECC_CAPTURE_MODULE - ******************************************************************************/ -/* ECC Capture address registers */ -typedef struct -{ - union { - __IO uint32_t FERRAD; - stc_ecc_capture_ferrad_field_t FERRAD_f; - }; -}FM4_ECC_CAPTURE_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - union { - __IO uint8_t SCM_CTL; - stc_crg_scm_ctl_field_t SCM_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t SCM_STR; - stc_crg_scm_str_field_t SCM_STR_f; - }; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - union { - __IO uint16_t RST_STR; - stc_crg_rst_str_field_t RST_STR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t BSC_PSR; - stc_crg_bsc_psr_field_t BSC_PSR_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t APBC0_PSR; - stc_crg_apbc0_psr_field_t APBC0_PSR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t APBC1_PSR; - stc_crg_apbc1_psr_field_t APBC1_PSR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t APBC2_PSR; - stc_crg_apbc2_psr_field_t APBC2_PSR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t SWC_PSR; - stc_crg_swc_psr_field_t SWC_PSR_f; - }; - uint8_t RESERVED7[7]; - union { - __IO uint8_t TTC_PSR; - stc_crg_ttc_psr_field_t TTC_PSR_f; - }; - uint8_t RESERVED8[7]; - union { - __IO uint8_t CSW_TMR; - stc_crg_csw_tmr_field_t CSW_TMR_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t PSW_TMR; - stc_crg_psw_tmr_field_t PSW_TMR_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PLL_CTL1; - stc_crg_pll_ctl1_field_t PLL_CTL1_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t PLL_CTL2; - stc_crg_pll_ctl2_field_t PLL_CTL2_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint16_t CSV_CTL; - stc_crg_csv_ctl_field_t CSV_CTL_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint8_t CSV_STR; - stc_crg_csv_str_field_t CSV_STR_f; - }; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - union { - __IO uint8_t DBWDT_CTL; - stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; - }; - uint8_t RESERVED18[11]; - union { - __IO uint8_t INT_ENR; - stc_crg_int_enr_field_t INT_ENR_f; - }; - uint8_t RESERVED19[3]; - union { - __IO uint8_t INT_STR; - stc_crg_int_str_field_t INT_STR_f; - }; - uint8_t RESERVED20[3]; - union { - __IO uint8_t INT_CLR; - stc_crg_int_clr_field_t INT_CLR_f; - }; -}FM4_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - union { - __IO uint8_t WDG_CTL; - stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; - }; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WDG_RIS; - stc_hwwdt_wdg_ris_field_t WDG_RIS_f; - }; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM4_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - union { - __IO uint8_t WDOGCONTROL; - stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - union { - __IO uint8_t WDOGRIS; - stc_swwdt_wdogris_field_t WDOGRIS_f; - }; - uint8_t RESERVED1[7]; - union { - __IO uint8_t WDOGSPMC; - stc_swwdt_wdogspmc_field_t WDOGSPMC_f; - }; - uint8_t RESERVED2[3047]; - __IO uint32_t WDOGLOCK; -}FM4_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMERXLOAD; - __IO uint32_t TIMERXVALUE; - union { - __IO uint32_t TIMERXCONTROL; - stc_dtim_timerXcontrol_field_t TIMERXCONTROL_f; - }; - __IO uint32_t TIMERXINTCLR; - union { - __IO uint32_t TIMERXRIS; - stc_dtim_timerXris_field_t TIMERXRIS_f; - }; - union { - __IO uint32_t TIMERXMIS; - stc_dtim_timerXmis_field_t TIMERXMIS_f; - }; - __IO uint32_t TIMERXBGLOAD; - uint8_t RESERVED0[4]; -}FM4_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[66]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - union { - __IO uint16_t TCSA0; - stc_mft_frt_tcsa0_field_t TCSA0_f; - }; - union { - __IO uint16_t TCSC0; - stc_mft_frt_tcsc0_field_t TCSC0_f; - }; - uint8_t RESERVED2[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED3[2]; - __IO uint16_t TCDT1; - union { - __IO uint16_t TCSA1; - stc_mft_frt_tcsa1_field_t TCSA1_f; - }; - union { - __IO uint16_t TCSC1; - stc_mft_frt_tcsc1_field_t TCSC1_f; - }; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT2; - union { - __IO uint16_t TCSA2; - stc_mft_frt_tcsa2_field_t TCSA2_f; - }; - union { - __IO uint16_t TCSC2; - stc_mft_frt_tcsc2_field_t TCSC2_f; - }; - union { - __IO uint32_t TCAL; - stc_mft_frt_tcal_field_t TCAL_f; - }; -}FM4_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[2]; - __IO uint16_t OCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED5[2]; - __IO uint16_t OCCP5; - union { - __IO uint8_t OCSA10; - stc_mft_ocu_ocsa10_field_t OCSA10_f; - }; - union { - __IO uint8_t OCSB10; - stc_mft_ocu_ocsb10_field_t OCSB10_f; - }; - union { - __IO uint8_t OCSD10; - stc_mft_ocu_ocsd10_field_t OCSD10_f; - }; - uint8_t RESERVED6; - union { - __IO uint8_t OCSA32; - stc_mft_ocu_ocsa32_field_t OCSA32_f; - }; - union { - __IO uint8_t OCSB32; - stc_mft_ocu_ocsb32_field_t OCSB32_f; - }; - union { - __IO uint8_t OCSD32; - stc_mft_ocu_ocsd32_field_t OCSD32_f; - }; - uint8_t RESERVED7; - union { - __IO uint8_t OCSA54; - stc_mft_ocu_ocsa54_field_t OCSA54_f; - }; - union { - __IO uint8_t OCSB54; - stc_mft_ocu_ocsb54_field_t OCSB54_f; - }; - union { - __IO uint8_t OCSD54; - stc_mft_ocu_ocsd54_field_t OCSD54_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint8_t OCSC; - stc_mft_ocu_ocsc_field_t OCSC_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t OCSE0; - stc_mft_ocu_ocse0_field_t OCSE0_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint32_t OCSE1; - stc_mft_ocu_ocse1_field_t OCSE1_f; - }; - union { - __IO uint16_t OCSE2; - stc_mft_ocu_ocse2_field_t OCSE2_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint32_t OCSE3; - stc_mft_ocu_ocse3_field_t OCSE3_f; - }; - union { - __IO uint16_t OCSE4; - stc_mft_ocu_ocse4_field_t OCSE4_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint32_t OCSE5; - stc_mft_ocu_ocse5_field_t OCSE5_f; - }; - uint8_t RESERVED13[40]; - union { - __IO uint8_t OCFS10; - stc_mft_ocu_ocfs10_field_t OCFS10_f; - }; - union { - __IO uint8_t OCFS32; - stc_mft_ocu_ocfs32_field_t OCFS32_f; - }; - union { - __IO uint8_t OCFS54; - stc_mft_ocu_ocfs54_field_t OCFS54_f; - }; -}FM4_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[142]; - __IO uint16_t WFTF10; - __IO uint16_t WFTA10; - __IO uint16_t WFTB10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTF32; - __IO uint16_t WFTA32; - __IO uint16_t WFTB32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTF54; - __IO uint16_t WFTA54; - __IO uint16_t WFTB54; - union { - __IO uint16_t WFSA10; - stc_mft_wfg_wfsa10_field_t WFSA10_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t WFSA32; - stc_mft_wfg_wfsa32_field_t WFSA32_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t WFSA54; - stc_mft_wfg_wfsa54_field_t WFSA54_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t WFIR; - stc_mft_wfg_wfir_field_t WFIR_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t NZCL; - stc_mft_wfg_nzcl_field_t NZCL_f; - }; -}FM4_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[108]; - union { - __IO uint8_t ICFS10; - stc_mft_icu_icfs10_field_t ICFS10_f; - }; - union { - __IO uint8_t ICFS32; - stc_mft_icu_icfs32_field_t ICFS32_f; - }; - uint8_t RESERVED1[8]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - union { - __IO uint8_t ICSA10; - stc_mft_icu_icsa10_field_t ICSA10_f; - }; - union { - __IO uint8_t ICSB10; - stc_mft_icu_icsb10_field_t ICSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ICSA32; - stc_mft_icu_icsa32_field_t ICSA32_f; - }; - union { - __IO uint8_t ICSB32; - stc_mft_icu_icsb32_field_t ICSB32_f; - }; -}FM4_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[112]; - union { - __IO uint8_t ACFS10; - stc_mft_adcmp_acfs10_field_t ACFS10_f; - }; - union { - __IO uint8_t ACFS32; - stc_mft_adcmp_acfs32_field_t ACFS32_f; - }; - union { - __IO uint8_t ACFS54; - stc_mft_adcmp_acfs54_field_t ACFS54_f; - }; - uint8_t RESERVED1[71]; - __IO uint16_t ACMP0; - uint8_t RESERVED2[2]; - __IO uint16_t ACMP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACMP2; - uint8_t RESERVED4[2]; - __IO uint16_t ACMP3; - uint8_t RESERVED5[2]; - __IO uint16_t ACMP4; - uint8_t RESERVED6[2]; - __IO uint16_t ACMP5; - union { - __IO uint16_t ACSA; - stc_mft_adcmp_acsa_field_t ACSA_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint8_t ACSC0; - stc_mft_adcmp_acsc_field_t ACSC0_f; - }; - union { - __IO uint8_t ACSD0; - stc_mft_adcmp_acsd_field_t ACSD0_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint8_t ACSC1; - stc_mft_adcmp_acsc_field_t ACSC1_f; - }; - union { - __IO uint8_t ACSD1; - stc_mft_adcmp_acsd_field_t ACSD1_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint8_t ACSC2; - stc_mft_adcmp_acsc_field_t ACSC2_f; - }; - union { - __IO uint8_t ACSD2; - stc_mft_adcmp_acsd_field_t ACSD2_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint8_t ACSC3; - stc_mft_adcmp_acsc_field_t ACSC3_f; - }; - union { - __IO uint8_t ACSD3; - stc_mft_adcmp_acsd_field_t ACSD3_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint8_t ACSC4; - stc_mft_adcmp_acsc_field_t ACSC4_f; - }; - union { - __IO uint8_t ACSD4; - stc_mft_adcmp_acsd_field_t ACSD4_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint8_t ACSC5; - stc_mft_adcmp_acsc_field_t ACSC5_f; - }; - union { - __IO uint8_t ACSD5; - stc_mft_adcmp_acsd_field_t ACSD5_f; - }; - uint8_t RESERVED13[2]; -}FM4_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t TTCR0; - stc_mft_ppg_ttcr0_field_t TTCR0_f; - }; - uint8_t RESERVED1[2]; - __IO uint8_t TSTPR0; - uint8_t RESERVED3[4]; - __IO uint8_t COMP0; - uint8_t RESERVED4[2]; - __IO uint8_t COMP2; - uint8_t RESERVED5[4]; - __IO uint8_t COMP4; - uint8_t RESERVED6[2]; - __IO uint8_t COMP6; - uint8_t RESERVED7[12]; - union { - __IO uint8_t TTCR1; - stc_mft_ppg_ttcr1_field_t TTCR1_f; - }; - uint8_t RESERVED8[2]; - __IO uint8_t TSTPR1; - uint8_t RESERVED9[4]; - __IO uint8_t COMP1; - uint8_t RESERVED10[2]; - __IO uint8_t COMP3; - uint8_t RESERVED11[4]; - __IO uint8_t COMP5; - uint8_t RESERVED12[2]; - __IO uint8_t COMP7; - uint8_t RESERVED13[12]; - union { - __IO uint8_t TTCR2; - stc_mft_ppg_ttcr2_field_t TTCR2_f; - }; - uint8_t RESERVED14[2]; - __IO uint8_t TSTPR2; - uint8_t RESERVED15[4]; - __IO uint8_t COMP8; - uint8_t RESERVED16[2]; - __IO uint8_t COMP10; - uint8_t RESERVED17[4]; - __IO uint8_t COMP12; - uint8_t RESERVED18[2]; - __IO uint8_t COMP14; - uint8_t RESERVED19[171]; - union { - __IO uint16_t TRG0; - stc_mft_ppg_trg0_field_t TRG0_f; - }; - uint8_t RESERVED20[2]; - union { - __IO uint16_t REVC0; - stc_mft_ppg_revc0_field_t REVC0_f; - }; - uint8_t RESERVED21[58]; - union { - __IO uint16_t TRG1; - stc_mft_ppg_trg1_field_t TRG1_f; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t REVC1; - stc_mft_ppg_revc1_field_t REVC1_f; - }; - uint8_t RESERVED23[186]; - union { - __IO uint8_t PPGC1; - stc_mft_ppg_ppgc1_field_t PPGC1_f; - }; - union { - __IO uint8_t PPGC0; - stc_mft_ppg_ppgc0_field_t PPGC0_f; - }; - uint8_t RESERVED24[2]; - union { - __IO uint8_t PPGC3; - stc_mft_ppg_ppgc3_field_t PPGC3_f; - }; - union { - __IO uint8_t PPGC2; - stc_mft_ppg_ppgc2_field_t PPGC2_f; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint8_t GATEC0; - stc_mft_ppg_gatec0_field_t GATEC0_f; - }; - uint8_t RESERVED30[39]; - union { - __IO uint8_t PPGC5; - stc_mft_ppg_ppgc5_field_t PPGC5_f; - }; - union { - __IO uint8_t PPGC4; - stc_mft_ppg_ppgc4_field_t PPGC4_f; - }; - uint8_t RESERVED31[2]; - union { - __IO uint8_t PPGC7; - stc_mft_ppg_ppgc7_field_t PPGC7_f; - }; - union { - __IO uint8_t PPGC6; - stc_mft_ppg_ppgc6_field_t PPGC6_f; - }; - uint8_t RESERVED32[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED33[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED34[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint8_t GATEC4; - stc_mft_ppg_gatec4_field_t GATEC4_f; - }; - uint8_t RESERVED37[39]; - union { - __IO uint8_t PPGC9; - stc_mft_ppg_ppgc9_field_t PPGC9_f; - }; - union { - __IO uint8_t PPGC8; - stc_mft_ppg_ppgc8_field_t PPGC8_f; - }; - uint8_t RESERVED38[2]; - union { - __IO uint8_t PPGC11; - stc_mft_ppg_ppgc11_field_t PPGC11_f; - }; - union { - __IO uint8_t PPGC10; - stc_mft_ppg_ppgc10_field_t PPGC10_f; - }; - uint8_t RESERVED39[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED40[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED41[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED42[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED43[2]; - union { - __IO uint8_t GATEC8; - stc_mft_ppg_gatec8_field_t GATEC8_f; - }; - uint8_t RESERVED44[39]; - union { - __IO uint8_t PPGC13; - stc_mft_ppg_ppgc13_field_t PPGC13_f; - }; - union { - __IO uint8_t PPGC12; - stc_mft_ppg_ppgc12_field_t PPGC12_f; - }; - uint8_t RESERVED45[2]; - union { - __IO uint8_t PPGC15; - stc_mft_ppg_ppgc15_field_t PPGC15_f; - }; - union { - __IO uint8_t PPGC14; - stc_mft_ppg_ppgc14_field_t PPGC14_f; - }; - uint8_t RESERVED46[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED47[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED48[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED49[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED50[2]; - union { - __IO uint8_t GATEC12; - stc_mft_ppg_gatec12_field_t GATEC12_f; - }; - uint8_t RESERVED51[39]; - union { - __IO uint8_t PPGC17; - stc_mft_ppg_ppgc17_field_t PPGC17_f; - }; - union { - __IO uint8_t PPGC16; - stc_mft_ppg_ppgc16_field_t PPGC16_f; - }; - uint8_t RESERVED52[2]; - union { - __IO uint8_t PPGC19; - stc_mft_ppg_ppgc19_field_t PPGC19_f; - }; - union { - __IO uint8_t PPGC18; - stc_mft_ppg_ppgc18_field_t PPGC18_f; - }; - uint8_t RESERVED53[2]; - union { - __IO uint16_t PRL16; - struct { - __IO uint8_t PRLL16; - __IO uint8_t PRLH16; - }; - }; - uint8_t RESERVED54[2]; - union { - __IO uint16_t PRL17; - struct { - __IO uint8_t PRLL17; - __IO uint8_t PRLH17; - }; - }; - uint8_t RESERVED55[2]; - union { - __IO uint16_t PRL18; - struct { - __IO uint8_t PRLL18; - __IO uint8_t PRLH18; - }; - }; - uint8_t RESERVED56[2]; - union { - __IO uint16_t PRL19; - struct { - __IO uint8_t PRLL19; - __IO uint8_t PRLH19; - }; - }; - uint8_t RESERVED57[2]; - union { - __IO uint8_t GATEC16; - stc_mft_ppg_gatec16_field_t GATEC16_f; - }; - uint8_t RESERVED58[39]; - union { - __IO uint8_t PPGC21; - stc_mft_ppg_ppgc21_field_t PPGC21_f; - }; - union { - __IO uint8_t PPGC20; - stc_mft_ppg_ppgc20_field_t PPGC20_f; - }; - uint8_t RESERVED59[2]; - union { - __IO uint8_t PPGC23; - stc_mft_ppg_ppgc23_field_t PPGC23_f; - }; - union { - __IO uint8_t PPGC22; - stc_mft_ppg_ppgc22_field_t PPGC22_f; - }; - uint8_t RESERVED60[2]; - union { - __IO uint16_t PRL20; - struct { - __IO uint8_t PRLL20; - __IO uint8_t PRLH20; - }; - }; - uint8_t RESERVED61[2]; - union { - __IO uint16_t PRL21; - struct { - __IO uint8_t PRLL21; - __IO uint8_t PRLH21; - }; - }; - uint8_t RESERVED62[2]; - union { - __IO uint16_t PRL22; - struct { - __IO uint8_t PRLL22; - __IO uint8_t PRLH22; - }; - }; - uint8_t RESERVED63[2]; - union { - __IO uint16_t PRL23; - struct { - __IO uint8_t PRLL23; - __IO uint8_t PRLH23; - }; - }; - uint8_t RESERVED64[2]; - union { - __IO uint8_t GATEC20; - stc_mft_ppg_gatec20_field_t GATEC20_f; - }; - uint8_t RESERVED65[39]; - __IO uint8_t IGBTC; - uint8_t RESERVED66[39]; -}FM4_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_ppg_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_ppg_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_ppg_tmcr2_field_t TMCR2_f; - }; -}FM4_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_pwm_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_pwm_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwm_tmcr2_field_t TMCR2_f; - }; -}FM4_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t TMCR; - stc_bt_rt_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_rt_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_rt_tmcr2_field_t TMCR2_f; - }; -}FM4_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - union { - __IO uint16_t TMCR; - stc_bt_pwc_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_pwc_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwc_tmcr2_field_t TMCR2_f; - }; -}FM4_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL0123; - stc_btiosel03_btsel0123_field_t BTSEL0123_f; - }; -}FM4_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL4567; - stc_btiosel47_btsel4567_field_t BTSEL4567_f; - }; -}FM4_BTIOSEL47_TypeDef; - -/****************************************************************************** - * BTIOSEL8B_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 8 - channel 11 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL89AB; - stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; - }; -}FM4_BTIOSEL8B_TypeDef; - -/****************************************************************************** - * BTIOSELCF_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 12 - channel 15 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSELCDEF; - stc_btioselcf_btselcdef_field_t BTSELCDEF_f; - }; -}FM4_BTIOSELCF_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - union { - __IO uint16_t BTSSSR; - stc_sbssr_btsssr_field_t BTSSSR_f; - }; -}FM4_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t QICR; - stc_qprc_qicr_field_t QICR_f; - }; - struct { - union { - __IO uint8_t QICRL; - stc_qprc_qicrl_field_t QICRL_f; - }; - union { - __IO uint8_t QICRH; - stc_qprc_qicrh_field_t QICRH_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t QCR; - stc_qprc_qcr_field_t QCR_f; - }; - struct { - union { - __IO uint8_t QCRL; - stc_qprc_qcrl_field_t QCRL_f; - }; - union { - __IO uint8_t QCRH; - stc_qprc_qcrh_field_t QCRH_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t QECR; - stc_qprc_qecr_field_t QECR_f; - }; -}FM4_QPRC_TypeDef; - -/****************************************************************************** - * QPRC_NF_MODULE - ******************************************************************************/ -/* Quad position and revolution counter noise filter registers */ -typedef struct -{ - union { - __IO uint8_t NFCTLA; - stc_qprc_nf_nfctla_field_t NFCTLA_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t NFCTLB; - stc_qprc_nf_nfctlb_field_t NFCTLB_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t NFRCTLZ; - stc_qprc_nf_nfrctlz_field_t NFRCTLZ_f; - }; - uint8_t RESERVED2[7]; -}FM4_QPRC_NF_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - union { - __IO uint8_t ADSR; - stc_adc_adsr_field_t ADSR_f; - }; - union { - __IO uint8_t ADCR; - stc_adc_adcr_field_t ADCR_f; - }; - uint8_t RESERVED0[6]; - union { - __IO uint8_t SFNS; - stc_adc_sfns_field_t SFNS_f; - }; - union { - __IO uint8_t SCCR; - stc_adc_sccr_field_t SCCR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint32_t SCFD; - stc_adc_scfd_field_t SCFD_f; - }; - struct { - union { - __IO uint16_t SCFDL; - stc_adc_scfdl_field_t SCFDL_f; - }; - union { - __IO uint16_t SCFDH; - stc_adc_scfdh_field_t SCFDH_f; - }; - }; - }; - union { - union { - __IO uint16_t SCIS23; - stc_adc_scis23_field_t SCIS23_f; - }; - struct { - union { - __IO uint8_t SCIS2; - stc_adc_scis2_field_t SCIS2_f; - }; - union { - __IO uint8_t SCIS3; - stc_adc_scis3_field_t SCIS3_f; - }; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t SCIS01; - stc_adc_scis01_field_t SCIS01_f; - }; - struct { - union { - __IO uint8_t SCIS0; - stc_adc_scis0_field_t SCIS0_f; - }; - union { - __IO uint8_t SCIS1; - stc_adc_scis1_field_t SCIS1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t PFNS; - stc_adc_pfns_field_t PFNS_f; - }; - union { - __IO uint8_t PCCR; - stc_adc_pccr_field_t PCCR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint32_t PCFD; - stc_adc_pcfd_field_t PCFD_f; - }; - struct { - union { - __IO uint16_t PCFDL; - stc_adc_pcfdl_field_t PCFDL_f; - }; - union { - __IO uint16_t PCFDH; - stc_adc_pcfdh_field_t PCFDH_f; - }; - }; - }; - union { - __IO uint8_t PCIS; - stc_adc_pcis_field_t PCIS_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t CMPCR; - stc_adc_cmpcr_field_t CMPCR_f; - }; - uint8_t RESERVED6; - union { - __IO uint16_t CMPD; - stc_adc_cmpd_field_t CMPD_f; - }; - union { - union { - __IO uint16_t ADSS23; - stc_adc_adss23_field_t ADSS23_f; - }; - struct { - union { - __IO uint8_t ADSS2; - stc_adc_adss2_field_t ADSS2_f; - }; - union { - __IO uint8_t ADSS3; - stc_adc_adss3_field_t ADSS3_f; - }; - }; - }; - uint8_t RESERVED7[2]; - union { - union { - __IO uint16_t ADSS01; - stc_adc_adss01_field_t ADSS01_f; - }; - struct { - union { - __IO uint8_t ADSS0; - stc_adc_adss0_field_t ADSS0_f; - }; - union { - __IO uint8_t ADSS1; - stc_adc_adss1_field_t ADSS1_f; - }; - }; - }; - uint8_t RESERVED8[2]; - union { - union { - __IO uint16_t ADST01; - stc_adc_adst01_field_t ADST01_f; - }; - struct { - union { - __IO uint8_t ADST1; - stc_adc_adst1_field_t ADST1_f; - }; - union { - __IO uint8_t ADST0; - stc_adc_adst0_field_t ADST0_f; - }; - }; - }; - uint8_t RESERVED9[2]; - union { - __IO uint8_t ADCT; - stc_adc_adct_field_t ADCT_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PRTSL; - stc_adc_prtsl_field_t PRTSL_f; - }; - union { - __IO uint8_t SCTSL; - stc_adc_sctsl_field_t SCTSL_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t ADCEN; - stc_adc_adcen_field_t ADCEN_f; - }; - uint8_t RESERVED12[2]; - uint32_t OFFESET; - union { - __IO uint8_t WCMRCOT; - stc_adc_wcmrcot_field_t WCMRCOT_f; - }; - uint8_t RESERVED13[3]; - union { - __IO uint8_t WCMRCIF; - stc_adc_wcmrcif_field_t WCMRCIF_f; - }; - uint8_t RESERVED14[3]; - union { - __IO uint8_t WCMPCR; - stc_adc_wcmpcr_field_t WCMPCR_f; - }; - union { - __IO uint8_t WCMPSR; - stc_adc_wcmpsr_field_t WCMPSR_f; - }; - uint8_t RESERVED15[2]; - union { - __IO uint16_t WCMPDL; - stc_adc_wcmpdl_field_t WCMPDL_f; - }; - union { - __IO uint16_t WCMPDH; - stc_adc_wcmpdh_field_t WCMPDH_f; - }; -}FM4_ADC_TypeDef; - -/****************************************************************************** - * DAC_MODULE - ******************************************************************************/ - -typedef struct -{ - union { - __IO uint8_t DACR; - stc_dacr_field_t DACR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint16_t DADR; - stc_dadr_field_t DADR_f; - }; -}FM4_DAC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - union { - __IO uint8_t MCR_PSR; - stc_crtrim_mcr_psr_field_t MCR_PSR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint16_t MCR_FTRM; - stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t MCR_TTRM; - stc_crtrim_mcr_ttrm_field_t MCR_TTRM_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint32_t MCR_RLR; - stc_crtrim_mcr_rlr_field_t MCR_RLR_f; - }; -}FM4_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - union { - __IO uint32_t ENIR; - stc_exti_enir_field_t ENIR_f; - }; - union { - __IO uint32_t EIRR; - stc_exti_eirr_field_t EIRR_f; - }; - union { - __IO uint32_t EICL; - stc_exti_eicl_field_t EICL_f; - }; - union { - __IO uint32_t ELVR; - stc_exti_elvr_field_t ELVR_f; - }; - union { - __IO uint32_t ELVR1; - stc_exti_elvr1_field_t ELVR1_f; - }; - union { - __IO uint8_t NMIRR; - stc_exti_nmirr_field_t NMIRR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t NMICL; - stc_exti_nmicl_field_t NMICL_f; - }; -}FM4_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - union { - __IO uint32_t DRQSEL; - stc_intreq_drqsel_field_t DRQSEL_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint8_t ODDPKS; - stc_intreq_oddpks_field_t ODDPKS_f; - }; - uint8_t RESERVED1[255]; - union { - __IO uint32_t IRQ003SEL; - stc_intreq_irq003sel_field_t IRQ003SEL_f; - }; - union { - __IO uint32_t IRQ004SEL; - stc_intreq_irq004sel_field_t IRQ004SEL_f; - }; - union { - __IO uint32_t IRQ005SEL; - stc_intreq_irq005sel_field_t IRQ005SEL_f; - }; - union { - __IO uint32_t IRQ006SEL; - stc_intreq_irq006sel_field_t IRQ006SEL_f; - }; - union { - __IO uint32_t IRQ007SEL; - stc_intreq_irq007sel_field_t IRQ007SEL_f; - }; - union { - __IO uint32_t IRQ008SEL; - stc_intreq_irq008sel_field_t IRQ008SEL_f; - }; - union { - __IO uint32_t IRQ009SEL; - stc_intreq_irq009sel_field_t IRQ009SEL_f; - }; - union { - __IO uint32_t IRQ010SEL; - stc_intreq_irq010sel_field_t IRQ010SEL_f; - }; - uint8_t RESERVED9[208]; - union { - __IO uint32_t EXC02MON; - stc_intreq_exc02mon_field_t EXC02MON_f; - }; - union { - __IO uint32_t IRQ000MON; - stc_intreq_irq000mon_field_t IRQ000MON_f; - }; - union { - __IO uint32_t IRQ001MON; - stc_intreq_irq001mon_field_t IRQ001MON_f; - }; - union { - __IO uint32_t IRQ002MON; - stc_intreq_irq002mon_field_t IRQ002MON_f; - }; - union { - __IO uint32_t IRQ003MON; - stc_intreq_irq003mon_field_t IRQ003MON_f; - }; - union { - __IO uint32_t IRQ004MON; - stc_intreq_irq004mon_field_t IRQ004MON_f; - }; - union { - __IO uint32_t IRQ005MON; - stc_intreq_irq005mon_field_t IRQ005MON_f; - }; - union { - __IO uint32_t IRQ006MON; - stc_intreq_irq006mon_field_t IRQ006MON_f; - }; - union { - __IO uint32_t IRQ007MON; - stc_intreq_irq007mon_field_t IRQ007MON_f; - }; - union { - __IO uint32_t IRQ008MON; - stc_intreq_irq008mon_field_t IRQ008MON_f; - }; - union { - __IO uint32_t IRQ009MON; - stc_intreq_irq009mon_field_t IRQ009MON_f; - }; - union { - __IO uint32_t IRQ010MON; - stc_intreq_irq010mon_field_t IRQ010MON_f; - }; - union { - __IO uint32_t IRQ011MON; - stc_intreq_irq011mon_field_t IRQ011MON_f; - }; - union { - __IO uint32_t IRQ012MON; - stc_intreq_irq012mon_field_t IRQ012MON_f; - }; - union { - __IO uint32_t IRQ013MON; - stc_intreq_irq013mon_field_t IRQ013MON_f; - }; - union { - __IO uint32_t IRQ014MON; - stc_intreq_irq014mon_field_t IRQ014MON_f; - }; - union { - __IO uint32_t IRQ015MON; - stc_intreq_irq015mon_field_t IRQ015MON_f; - }; - union { - __IO uint32_t IRQ016MON; - stc_intreq_irq016mon_field_t IRQ016MON_f; - }; - union { - __IO uint32_t IRQ017MON; - stc_intreq_irq017mon_field_t IRQ017MON_f; - }; - union { - __IO uint32_t IRQ018MON; - stc_intreq_irq018mon_field_t IRQ018MON_f; - }; - union { - __IO uint32_t IRQ019MON; - stc_intreq_irq019mon_field_t IRQ019MON_f; - }; - union { - __IO uint32_t IRQ020MON; - stc_intreq_irq020mon_field_t IRQ020MON_f; - }; - union { - __IO uint32_t IRQ021MON; - stc_intreq_irq021mon_field_t IRQ021MON_f; - }; - union { - __IO uint32_t IRQ022MON; - stc_intreq_irq022mon_field_t IRQ022MON_f; - }; - union { - __IO uint32_t IRQ023MON; - stc_intreq_irq023mon_field_t IRQ023MON_f; - }; - union { - __IO uint32_t IRQ024MON; - stc_intreq_irq024mon_field_t IRQ024MON_f; - }; - union { - __IO uint32_t IRQ025MON; - stc_intreq_irq025mon_field_t IRQ025MON_f; - }; - union { - __IO uint32_t IRQ026MON; - stc_intreq_irq026mon_field_t IRQ026MON_f; - }; - union { - __IO uint32_t IRQ027MON; - stc_intreq_irq027mon_field_t IRQ027MON_f; - }; - union { - __IO uint32_t IRQ028MON; - stc_intreq_irq028mon_field_t IRQ028MON_f; - }; - union { - __IO uint32_t IRQ029MON; - stc_intreq_irq029mon_field_t IRQ029MON_f; - }; - union { - __IO uint32_t IRQ030MON; - stc_intreq_irq030mon_field_t IRQ030MON_f; - }; - union { - __IO uint32_t IRQ031MON; - stc_intreq_irq031mon_field_t IRQ031MON_f; - }; - union { - __IO uint32_t IRQ032MON; - stc_intreq_irq032mon_field_t IRQ032MON_f; - }; - union { - __IO uint32_t IRQ033MON; - stc_intreq_irq033mon_field_t IRQ033MON_f; - }; - union { - __IO uint32_t IRQ034MON; - stc_intreq_irq034mon_field_t IRQ034MON_f; - }; - union { - __IO uint32_t IRQ035MON; - stc_intreq_irq035mon_field_t IRQ035MON_f; - }; - union { - __IO uint32_t IRQ036MON; - stc_intreq_irq036mon_field_t IRQ036MON_f; - }; - union { - __IO uint32_t IRQ037MON; - stc_intreq_irq037mon_field_t IRQ037MON_f; - }; - union { - __IO uint32_t IRQ038MON; - stc_intreq_irq038mon_field_t IRQ038MON_f; - }; - union { - __IO uint32_t IRQ039MON; - stc_intreq_irq039mon_field_t IRQ039MON_f; - }; - union { - __IO uint32_t IRQ040MON; - stc_intreq_irq040mon_field_t IRQ040MON_f; - }; - union { - __IO uint32_t IRQ041MON; - stc_intreq_irq041mon_field_t IRQ041MON_f; - }; - union { - __IO uint32_t IRQ042MON; - stc_intreq_irq042mon_field_t IRQ042MON_f; - }; - union { - __IO uint32_t IRQ043MON; - stc_intreq_irq043mon_field_t IRQ043MON_f; - }; - union { - __IO uint32_t IRQ044MON; - stc_intreq_irq044mon_field_t IRQ044MON_f; - }; - union { - __IO uint32_t IRQ045MON; - stc_intreq_irq045mon_field_t IRQ045MON_f; - }; - union { - __IO uint32_t IRQ046MON; - stc_intreq_irq046mon_field_t IRQ046MON_f; - }; - union { - __IO uint32_t IRQ047MON; - stc_intreq_irq047mon_field_t IRQ047MON_f; - }; - union { - __IO uint32_t IRQ048MON; - stc_intreq_irq048mon_field_t IRQ048MON_f; - }; - union { - __IO uint32_t IRQ049MON; - stc_intreq_irq049mon_field_t IRQ049MON_f; - }; - union { - __IO uint32_t IRQ050MON; - stc_intreq_irq050mon_field_t IRQ050MON_f; - }; - union { - __IO uint32_t IRQ051MON; - stc_intreq_irq051mon_field_t IRQ051MON_f; - }; - union { - __IO uint32_t IRQ052MON; - stc_intreq_irq052mon_field_t IRQ052MON_f; - }; - union { - __IO uint32_t IRQ053MON; - stc_intreq_irq053mon_field_t IRQ053MON_f; - }; - union { - __IO uint32_t IRQ054MON; - stc_intreq_irq054mon_field_t IRQ054MON_f; - }; - union { - __IO uint32_t IRQ055MON; - stc_intreq_irq055mon_field_t IRQ055MON_f; - }; - union { - __IO uint32_t IRQ056MON; - stc_intreq_irq056mon_field_t IRQ056MON_f; - }; - union { - __IO uint32_t IRQ057MON; - stc_intreq_irq057mon_field_t IRQ057MON_f; - }; - union { - __IO uint32_t IRQ058MON; - stc_intreq_irq058mon_field_t IRQ058MON_f; - }; - union { - __IO uint32_t IRQ059MON; - stc_intreq_irq059mon_field_t IRQ059MON_f; - }; - union { - __IO uint32_t IRQ060MON; - stc_intreq_irq060mon_field_t IRQ060MON_f; - }; - union { - __IO uint32_t IRQ061MON; - stc_intreq_irq061mon_field_t IRQ061MON_f; - }; - union { - __IO uint32_t IRQ062MON; - stc_intreq_irq062mon_field_t IRQ062MON_f; - }; - union { - __IO uint32_t IRQ063MON; - stc_intreq_irq063mon_field_t IRQ063MON_f; - }; - union { - __IO uint32_t IRQ064MON; - stc_intreq_irq064mon_field_t IRQ064MON_f; - }; - union { - __IO uint32_t IRQ065MON; - stc_intreq_irq065mon_field_t IRQ065MON_f; - }; - union { - __IO uint32_t IRQ066MON; - stc_intreq_irq066mon_field_t IRQ066MON_f; - }; - union { - __IO uint32_t IRQ067MON; - stc_intreq_irq067mon_field_t IRQ067MON_f; - }; - union { - __IO uint32_t IRQ068MON; - stc_intreq_irq068mon_field_t IRQ068MON_f; - }; - union { - __IO uint32_t IRQ069MON; - stc_intreq_irq069mon_field_t IRQ069MON_f; - }; - union { - __IO uint32_t IRQ070MON; - stc_intreq_irq070mon_field_t IRQ070MON_f; - }; - union { - __IO uint32_t IRQ071MON; - stc_intreq_irq071mon_field_t IRQ071MON_f; - }; - union { - __IO uint32_t IRQ072MON; - stc_intreq_irq072mon_field_t IRQ072MON_f; - }; - union { - __IO uint32_t IRQ073MON; - stc_intreq_irq073mon_field_t IRQ073MON_f; - }; - union { - __IO uint32_t IRQ074MON; - stc_intreq_irq074mon_field_t IRQ074MON_f; - }; - union { - __IO uint32_t IRQ075MON; - stc_intreq_irq075mon_field_t IRQ075MON_f; - }; - union { - __IO uint32_t IRQ076MON; - stc_intreq_irq076mon_field_t IRQ076MON_f; - }; - union { - __IO uint32_t IRQ077MON; - stc_intreq_irq077mon_field_t IRQ077MON_f; - }; - union { - __IO uint32_t IRQ078MON; - stc_intreq_irq078mon_field_t IRQ078MON_f; - }; - union { - __IO uint32_t IRQ079MON; - stc_intreq_irq079mon_field_t IRQ079MON_f; - }; - union { - __IO uint32_t IRQ080MON; - stc_intreq_irq080mon_field_t IRQ080MON_f; - }; - union { - __IO uint32_t IRQ081MON; - stc_intreq_irq081mon_field_t IRQ081MON_f; - }; - union { - __IO uint32_t IRQ082MON; - stc_intreq_irq082mon_field_t IRQ082MON_f; - }; - union { - __IO uint32_t IRQ083MON; - stc_intreq_irq083mon_field_t IRQ083MON_f; - }; - union { - __IO uint32_t IRQ084MON; - stc_intreq_irq084mon_field_t IRQ084MON_f; - }; - union { - __IO uint32_t IRQ085MON; - stc_intreq_irq085mon_field_t IRQ085MON_f; - }; - union { - __IO uint32_t IRQ086MON; - stc_intreq_irq086mon_field_t IRQ086MON_f; - }; - union { - __IO uint32_t IRQ087MON; - stc_intreq_irq087mon_field_t IRQ087MON_f; - }; - union { - __IO uint32_t IRQ088MON; - stc_intreq_irq088mon_field_t IRQ088MON_f; - }; - union { - __IO uint32_t IRQ089MON; - stc_intreq_irq089mon_field_t IRQ089MON_f; - }; - union { - __IO uint32_t IRQ090MON; - stc_intreq_irq090mon_field_t IRQ090MON_f; - }; - union { - __IO uint32_t IRQ091MON; - stc_intreq_irq091mon_field_t IRQ091MON_f; - }; - union { - __IO uint32_t IRQ092MON; - stc_intreq_irq092mon_field_t IRQ092MON_f; - }; - union { - __IO uint32_t IRQ093MON; - stc_intreq_irq093mon_field_t IRQ093MON_f; - }; - union { - __IO uint32_t IRQ094MON; - stc_intreq_irq094mon_field_t IRQ094MON_f; - }; - union { - __IO uint32_t IRQ095MON; - stc_intreq_irq095mon_field_t IRQ095MON_f; - }; - union { - __IO uint32_t IRQ096MON; - stc_intreq_irq096mon_field_t IRQ096MON_f; - }; - union { - __IO uint32_t IRQ097MON; - stc_intreq_irq097mon_field_t IRQ097MON_f; - }; - union { - __IO uint32_t IRQ098MON; - stc_intreq_irq098mon_field_t IRQ098MON_f; - }; - union { - __IO uint32_t IRQ099MON; - stc_intreq_irq099mon_field_t IRQ099MON_f; - }; - union { - __IO uint32_t IRQ100MON; - stc_intreq_irq100mon_field_t IRQ100MON_f; - }; - union { - __IO uint32_t IRQ101MON; - stc_intreq_irq101mon_field_t IRQ101MON_f; - }; - union { - __IO uint32_t IRQ102MON; - stc_intreq_irq102mon_field_t IRQ102MON_f; - }; - union { - __IO uint32_t IRQ103MON; - stc_intreq_irq103mon_field_t IRQ103MON_f; - }; - union { - __IO uint32_t IRQ104MON; - stc_intreq_irq104mon_field_t IRQ104MON_f; - }; - union { - __IO uint32_t IRQ105MON; - stc_intreq_irq105mon_field_t IRQ105MON_f; - }; - union { - __IO uint32_t IRQ106MON; - stc_intreq_irq106mon_field_t IRQ106MON_f; - }; - union { - __IO uint32_t IRQ107MON; - stc_intreq_irq107mon_field_t IRQ107MON_f; - }; - union { - __IO uint32_t IRQ108MON; - stc_intreq_irq108mon_field_t IRQ108MON_f; - }; - union { - __IO uint32_t IRQ109MON; - stc_intreq_irq109mon_field_t IRQ109MON_f; - }; - union { - __IO uint32_t IRQ110MON; - stc_intreq_irq110mon_field_t IRQ110MON_f; - }; - union { - __IO uint32_t IRQ111MON; - stc_intreq_irq111mon_field_t IRQ111MON_f; - }; - __IO uint32_t IRQ112MON; - union { - __IO uint32_t IRQ113MON; - stc_intreq_irq113mon_field_t IRQ113MON_f; - }; - union { - __IO uint32_t IRQ114MON; - stc_intreq_irq114mon_field_t IRQ114MON_f; - }; - __IO uint32_t IRQ115MON; - __IO uint32_t IRQ116MON; - __IO uint32_t IRQ117MON; - union { - __IO uint32_t IRQ118MON; - stc_intreq_irq118mon_field_t IRQ118MON_f; - }; - union { - __IO uint32_t IRQ119MON; - stc_intreq_irq119mon_field_t IRQ119MON_f; - }; - union { - __IO uint32_t IRQ120MON; - stc_intreq_irq120mon_field_t IRQ120MON_f; - }; - union { - __IO uint32_t IRQ121MON; - stc_intreq_irq121mon_field_t IRQ121MON_f; - }; - union { - __IO uint32_t IRQ122MON; - stc_intreq_irq122mon_field_t IRQ122MON_f; - }; - union { - __IO uint32_t IRQ123MON; - stc_intreq_irq123mon_field_t IRQ123MON_f; - }; - union { - __IO uint32_t IRQ124MON; - stc_intreq_irq124mon_field_t IRQ124MON_f; - }; - union { - __IO uint32_t IRQ125MON; - stc_intreq_irq125mon_field_t IRQ125MON_f; - }; - union { - __IO uint32_t IRQ126MON; - stc_intreq_irq126mon_field_t IRQ126MON_f; - }; - union { - __IO uint32_t IRQ127MON; - stc_intreq_irq127mon_field_t IRQ127MON_f; - }; -}FM4_INTREQ_TypeDef; - -/****************************************************************************** - * IRQSEL_MODULE -******************************************************************************/ -typedef struct -{ - union { - __IO uint32_t IRQ03SEL; - stc_irqsel_field_t IRQ03SEL_f; - }; - union { - __IO uint32_t IRQ04SEL; - stc_irqsel_field_t IRQ04SEL_f; - }; - union { - __IO uint32_t IRQ05SEL; - stc_irqsel_field_t IRQ05SEL_f; - }; - union { - __IO uint32_t IRQ06SEL; - stc_irqsel_field_t IRQ06SEL_f; - }; - union { - __IO uint32_t IRQ07SEL; - stc_irqsel_field_t IRQ07SEL_f; - }; - union { - __IO uint32_t IRQ08SEL; - stc_irqsel_field_t IRQ08SEL_f; - }; - union { - __IO uint32_t IRQ09SEL; - stc_irqsel_field_t IRQ09SEL_f; - }; - union { - __IO uint32_t IRQ10SEL; - stc_irqsel_field_t IRQ10SEL_f; - }; -} FM4_IRQSEL_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - union { - __IO uint32_t PFR0; - stc_gpio_pfr0_field_t PFR0_f; - }; - union { - __IO uint32_t PFR1; - stc_gpio_pfr1_field_t PFR1_f; - }; - union { - __IO uint32_t PFR2; - stc_gpio_pfr2_field_t PFR2_f; - }; - union { - __IO uint32_t PFR3; - stc_gpio_pfr3_field_t PFR3_f; - }; - union { - __IO uint32_t PFR4; - stc_gpio_pfr4_field_t PFR4_f; - }; - union { - __IO uint32_t PFR5; - stc_gpio_pfr5_field_t PFR5_f; - }; - union { - __IO uint32_t PFR6; - stc_gpio_pfr6_field_t PFR6_f; - }; - union { - __IO uint32_t PFR7; - stc_gpio_pfr7_field_t PFR7_f; - }; - union { - __IO uint32_t PFR8; - stc_gpio_pfr8_field_t PFR8_f; - }; - uint8_t RESERVED8[20]; - union { - __IO uint32_t PFRE; - stc_gpio_pfre_field_t PFRE_f; - }; - uint8_t RESERVED9[196]; - union { - __IO uint32_t PCR0; - stc_gpio_pcr0_field_t PCR0_f; - }; - union { - __IO uint32_t PCR1; - stc_gpio_pcr1_field_t PCR1_f; - }; - union { - __IO uint32_t PCR2; - stc_gpio_pcr2_field_t PCR2_f; - }; - union { - __IO uint32_t PCR3; - stc_gpio_pcr3_field_t PCR3_f; - }; - union { - __IO uint32_t PCR4; - stc_gpio_pcr4_field_t PCR4_f; - }; - union { - __IO uint32_t PCR5; - stc_gpio_pcr5_field_t PCR5_f; - }; - union { - __IO uint32_t PCR6; - stc_gpio_pcr6_field_t PCR6_f; - }; - union { - __IO uint32_t PCR7; - stc_gpio_pcr7_field_t PCR7_f; - }; - union { - __IO uint32_t PCR8; - stc_gpio_pcr8_field_t PCR8_f; - }; - uint8_t RESERVED18[20]; - union { - __IO uint32_t PCRE; - stc_gpio_pcre_field_t PCRE_f; - }; - uint8_t RESERVED19[196]; - union { - __IO uint32_t DDR0; - stc_gpio_ddr0_field_t DDR0_f; - }; - union { - __IO uint32_t DDR1; - stc_gpio_ddr1_field_t DDR1_f; - }; - union { - __IO uint32_t DDR2; - stc_gpio_ddr2_field_t DDR2_f; - }; - union { - __IO uint32_t DDR3; - stc_gpio_ddr3_field_t DDR3_f; - }; - union { - __IO uint32_t DDR4; - stc_gpio_ddr4_field_t DDR4_f; - }; - union { - __IO uint32_t DDR5; - stc_gpio_ddr5_field_t DDR5_f; - }; - union { - __IO uint32_t DDR6; - stc_gpio_ddr6_field_t DDR6_f; - }; - union { - __IO uint32_t DDR7; - stc_gpio_ddr7_field_t DDR7_f; - }; - union { - __IO uint32_t DDR8; - stc_gpio_ddr8_field_t DDR8_f; - }; - uint8_t RESERVED28[20]; - union { - __IO uint32_t DDRE; - stc_gpio_ddre_field_t DDRE_f; - }; - uint8_t RESERVED29[196]; - union { - __IO uint32_t PDIR0; - stc_gpio_pdir0_field_t PDIR0_f; - }; - union { - __IO uint32_t PDIR1; - stc_gpio_pdir1_field_t PDIR1_f; - }; - union { - __IO uint32_t PDIR2; - stc_gpio_pdir2_field_t PDIR2_f; - }; - union { - __IO uint32_t PDIR3; - stc_gpio_pdir3_field_t PDIR3_f; - }; - union { - __IO uint32_t PDIR4; - stc_gpio_pdir4_field_t PDIR4_f; - }; - union { - __IO uint32_t PDIR5; - stc_gpio_pdir5_field_t PDIR5_f; - }; - union { - __IO uint32_t PDIR6; - stc_gpio_pdir6_field_t PDIR6_f; - }; - union { - __IO uint32_t PDIR7; - stc_gpio_pdir7_field_t PDIR7_f; - }; - union { - __IO uint32_t PDIR8; - stc_gpio_pdir8_field_t PDIR8_f; - }; - uint8_t RESERVED38[20]; - union { - __IO uint32_t PDIRE; - stc_gpio_pdire_field_t PDIRE_f; - }; - uint8_t RESERVED39[196]; - union { - __IO uint32_t PDOR0; - stc_gpio_pdor0_field_t PDOR0_f; - }; - union { - __IO uint32_t PDOR1; - stc_gpio_pdor1_field_t PDOR1_f; - }; - union { - __IO uint32_t PDOR2; - stc_gpio_pdor2_field_t PDOR2_f; - }; - union { - __IO uint32_t PDOR3; - stc_gpio_pdor3_field_t PDOR3_f; - }; - union { - __IO uint32_t PDOR4; - stc_gpio_pdor4_field_t PDOR4_f; - }; - union { - __IO uint32_t PDOR5; - stc_gpio_pdor5_field_t PDOR5_f; - }; - union { - __IO uint32_t PDOR6; - stc_gpio_pdor6_field_t PDOR6_f; - }; - union { - __IO uint32_t PDOR7; - stc_gpio_pdor7_field_t PDOR7_f; - }; - union { - __IO uint32_t PDOR8; - stc_gpio_pdor8_field_t PDOR8_f; - }; - uint8_t RESERVED48[20]; - union { - __IO uint32_t PDORE; - stc_gpio_pdore_field_t PDORE_f; - }; - uint8_t RESERVED49[196]; - union { - __IO uint32_t ADE; - stc_gpio_ade_field_t ADE_f; - }; - uint8_t RESERVED50[124]; - union { - __IO uint32_t SPSR; - stc_gpio_spsr_field_t SPSR_f; - }; - uint8_t RESERVED51[124]; - union { - __IO uint32_t EPFR00; - stc_gpio_epfr00_field_t EPFR00_f; - }; - union { - __IO uint32_t EPFR01; - stc_gpio_epfr01_field_t EPFR01_f; - }; - union { - __IO uint32_t EPFR02; - stc_gpio_epfr02_field_t EPFR02_f; - }; - union { - __IO uint32_t EPFR03; - stc_gpio_epfr03_field_t EPFR03_f; - }; - union { - __IO uint32_t EPFR04; - stc_gpio_epfr04_field_t EPFR04_f; - }; - union { - __IO uint32_t EPFR05; - stc_gpio_epfr05_field_t EPFR05_f; - }; - union { - __IO uint32_t EPFR06; - stc_gpio_epfr06_field_t EPFR06_f; - }; - union { - __IO uint32_t EPFR07; - stc_gpio_epfr07_field_t EPFR07_f; - }; - union { - __IO uint32_t EPFR08; - stc_gpio_epfr08_field_t EPFR08_f; - }; - union { - __IO uint32_t EPFR09; - stc_gpio_epfr09_field_t EPFR09_f; - }; - union { - __IO uint32_t EPFR10; - stc_gpio_epfr10_field_t EPFR10_f; - }; - union { - __IO uint32_t EPFR11; - stc_gpio_epfr11_field_t EPFR11_f; - }; - union { - __IO uint32_t EPFR12; - stc_gpio_epfr12_field_t EPFR12_f; - }; - union { - __IO uint32_t EPFR13; - stc_gpio_epfr13_field_t EPFR13_f; - }; - union { - __IO uint32_t EPFR14; - stc_gpio_epfr14_field_t EPFR14_f; - }; - union { - __IO uint32_t EPFR15; - stc_gpio_epfr15_field_t EPFR15_f; - }; - union { - __IO uint32_t EPFR16; - stc_gpio_epfr16_field_t EPFR16_f; - }; - union { - __IO uint32_t EPFR17; - stc_gpio_epfr17_field_t EPFR17_f; - }; - union { - __IO uint32_t EPFR18; - stc_gpio_epfr18_field_t EPFR18_f; - }; - __IO uint32_t EPFR19; - union { - __IO uint32_t EPFR20; - stc_gpio_epfr20_field_t EPFR20_f; - }; - uint8_t RESERVED72[172]; - union { - __IO uint32_t PZR0; - stc_gpio_pzr0_field_t PZR0_f; - }; - union { - __IO uint32_t PZR1; - stc_gpio_pzr1_field_t PZR1_f; - }; - union { - __IO uint32_t PZR2; - stc_gpio_pzr2_field_t PZR2_f; - }; - union { - __IO uint32_t PZR3; - stc_gpio_pzr3_field_t PZR3_f; - }; - union { - __IO uint32_t PZR4; - stc_gpio_pzr4_field_t PZR4_f; - }; - union { - __IO uint32_t PZR5; - stc_gpio_pzr5_field_t PZR5_f; - }; - union { - __IO uint32_t PZR6; - stc_gpio_pzr6_field_t PZR6_f; - }; - union { - __IO uint32_t PZR7; - stc_gpio_pzr7_field_t PZR7_f; - }; - union { - __IO uint32_t PZR8; - stc_gpio_pzr8_field_t PZR8_f; - }; - uint8_t RESERVED81[20]; - union { - __IO uint32_t PZRE; - stc_gpio_pzre_field_t PZRE_f; - }; -}FM4_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - union { - __IO uint8_t LVD_CTL; - stc_lvd_lvd_ctl_field_t LVD_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t LVD_STR; - stc_lvd_lvd_str_field_t LVD_STR_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t LVD_CLR; - stc_lvd_lvd_clr_field_t LVD_CLR_f; - }; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - union { - __IO uint8_t LVD_STR2; - stc_lvd_lvd_str2_field_t LVD_STR2_f; - }; -}FM4_LVD_TypeDef; - -/****************************************************************************** - * DS_MODULE - ******************************************************************************/ -/* Deep standby mode registers */ -typedef struct -{ - uint8_t RESERVED10[4]; - union { - __IO uint8_t RCK_CTL; - stc_ds_rck_ctl_field_t RCK_CTL_f; - }; - uint8_t RESERVED0[1787]; - union { - __IO uint8_t PMD_CTL; - stc_ds_pmd_ctl_field_t PMD_CTL_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WRFSR; - stc_ds_wrfsr_field_t WRFSR_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint16_t WIFSR; - stc_ds_wifsr_field_t WIFSR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t WIER; - stc_ds_wier_field_t WIER_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint8_t WILVR; - stc_ds_wilvr_field_t WILVR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t DSRAMR; - stc_ds_dsramr_field_t DSRAMR_f; - }; - uint8_t RESERVED6[235]; - __IO uint8_t BUR01; - __IO uint8_t BUR02; - __IO uint8_t BUR03; - __IO uint8_t BUR04; - __IO uint8_t BUR05; - __IO uint8_t BUR06; - __IO uint8_t BUR07; - __IO uint8_t BUR08; - __IO uint8_t BUR09; - __IO uint8_t BUR10; - __IO uint8_t BUR11; - __IO uint8_t BUR12; - __IO uint8_t BUR13; - __IO uint8_t BUR14; - __IO uint8_t BUR15; - __IO uint8_t BUR16; -}FM4_DS_TypeDef; - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USB clock registers */ -/* -typedef struct -{ - union { - __IO uint8_t UCCR; - stc_usbclk_uccr_field_t UCCR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t UPCR1; - stc_usbclk_upcr1_field_t UPCR1_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t UPCR2; - stc_usbclk_upcr2_field_t UPCR2_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t UPCR3; - stc_usbclk_upcr3_field_t UPCR3_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t UPCR4; - stc_usbclk_upcr4_field_t UPCR4_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t UP_STR; - stc_usbclk_up_str_field_t UP_STR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t UPINT_ENR; - stc_usbclk_upint_enr_field_t UPINT_ENR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t UPINT_CLR; - stc_usbclk_upint_clr_field_t UPINT_CLR_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint8_t UPINT_STR; - stc_usbclk_upint_str_field_t UPINT_STR_f; - }; - uint8_t RESERVED8[15]; - union { - __IO uint8_t USBEN; - stc_usbclk_usben_field_t USBEN_f; - }; -}FM4_USBCLK_TypeDef; -*/ - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CAN prescaler register */ -typedef struct -{ - union { - __IO uint8_t CANPRE; - stc_canpre_canpre_field_t CANPRE_f; - }; -}FM4_CANPRE_TypeDef; - -/****************************************************************************** - * USBETHERNETCLK - ******************************************************************************/ -/* USB Ethernet clock registers */ -typedef struct -{ - union { - __IO uint8_t UCCR; - stc_usbethernetclk_uccr_field_t UCCR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t UPCR1; - stc_usbethernetclk_upcr1_field_t UPCR1_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t UPCR2; - stc_usbethernetclk_upcr2_field_t UPCR2_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t UPCR3; - stc_usbethernetclk_upcr3_field_t UPCR3_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t UPCR4; - stc_usbethernetclk_upcr4_field_t UPCR4_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t UP_STR; - stc_usbethernetclk_up_str_field_t UP_STR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t UPINT_ENR; - stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t UPINT_CLR; - stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint8_t UPINT_STR; - stc_usbethernetclk_upint_str_field_t UPINT_STR_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t UPCR5; - stc_usbethernetclk_upcr5_field_t UPCR5_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t UPCR6; - stc_usbethernetclk_upcr6_field_t UPCR6_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t UPCR7; - stc_usbethernetclk_upcr7_field_t UPCR7_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t USBEN0; - stc_usbethernetclk_usben0_field_t USBEN0_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint8_t USBEN1; - stc_usbethernetclk_usben1_field_t USBEN1_f; - }; -}FM4_USBETHERNETCLK_TypeDef; - -/****************************************************************************** - * MFS_MODULE - ******************************************************************************/ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs_scr_field_t SCR_f; - __IO uint8_t IBCR; - stc_mfs_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs_escr_field_t ESCR_f; - __IO uint8_t IBSR; - stc_mfs_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint32_t RDR32; - __IO uint32_t TDR32; - struct { - union { - __IO uint16_t RDR; - stc_mfs_uart_rdr_field_t RDR_f; - }; - uint8_t RESERVED2[2]; - }; - struct { - union { - __IO uint16_t TDR; - stc_mfs_uart_tdr_field_t TDR_f; - }; - uint8_t RESERVED3[2]; - }; - }; - union { - union { - __IO uint16_t BGR; - stc_mfs_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint8_t ISBA; - stc_mfs_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs_i2c_ismk_field_t ISMK_f; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t FCR; - stc_mfs_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs_fbyte2_field_t FBYTE2_f; - }; - }; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t SCSTR10; - stc_mfs_csio_scstr10_field_t SCSTR10_f; - struct { - union { - __IO uint8_t SCSTR0; - stc_mfs_csio_scstr0_field_t SCSTR0_f; - __IO uint8_t NFCR; - stc_mfs_i2c_nfcr_field_t NFCR_f; - }; - union { - __IO uint8_t SCSTR1; - stc_mfs_csio_scstr1_field_t SCSTR1_f; - __IO uint8_t EIBCR; - stc_mfs_i2c_eibcr_field_t EIBCR_f; - }; - }; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t SCSTR32; - stc_mfs_csio_scstr32_field_t SCSTR32_f; - struct { - union { - __IO uint8_t SCSTR2; - stc_mfs_csio_scstr2_field_t SCSTR2_f; - }; - union { - __IO uint8_t SCSTR3; - stc_mfs_csio_scstr3_field_t SCSTR3_f; - }; - }; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t SACSR; - stc_mfs_csio_sacsr_field_t SACSR_f; - struct { - union { - __IO uint8_t SACSR0; - stc_mfs_csio_sacsr0_field_t SACSR0_f; - }; - union { - __IO uint8_t SACSR1; - stc_mfs_csio_sacsr1_field_t SACSR1_f; - }; - }; - }; - uint8_t RESERVED10[2]; - union { - __IO uint16_t STMR; - stc_mfs_csio_stmr_field_t STMR_f; - struct { - union { - __IO uint8_t STMR0; - stc_mfs_csio_stmr0_field_t STMR0_f; - }; - union { - __IO uint8_t STMR1; - stc_mfs_csio_stmr1_field_t STMR1_f; - }; - }; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t STMCR; - stc_mfs_csio_stmcr_field_t STMCR_f; - struct { - union { - __IO uint8_t STMCR0; - stc_mfs_csio_stmcr0_field_t STMCR0_f; - }; - union { - __IO uint8_t STMCR1; - stc_mfs_csio_stmcr1_field_t STMCR1_f; - }; - }; - }; - uint8_t RESERVED12[2]; - union { - __IO uint16_t SCSCR; - stc_mfs_csio_scscr_field_t SCSCR_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint16_t SCSFR; - struct { - __IO uint8_t SCSFR0; - __IO uint8_t SCSFR1; - }; - }; - uint8_t RESERVED14[2]; - __IO uint8_t SCSFR2; - uint8_t RESERVED15[3]; - union { - __IO uint16_t TBYTE10; - struct { - __IO uint8_t TBYTE0; - __IO uint8_t TBYTE1; - }; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t TBYTE32; - struct { - __IO uint8_t TBYTE2; - __IO uint8_t TBYTE3; - }; - }; -}FM4_MFS_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - union { - __IO uint8_t CRCCR; - stc_crc_crccr_field_t CRCCR_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM4_CRC_TypeDef; - -/****************************************************************************** - * DSTC_MODULE - ******************************************************************************/ -/* DSTC registers */ -typedef struct -{ - __IO uint32_t DESTP; - union { - __IO uint32_t HWDESP; - stc_dstc_hwdesp_field_t HWDESP_f; - }; - __IO uint8_t CMD; - union { - __IO uint8_t CFG; - stc_dstc_cfg_field_t CFG_f; - }; - union { - __IO uint16_t SWTR; - stc_dstc_swtr_field_t SWTR_f; - }; - union { - __IO uint32_t MONERS; - stc_dstc_moners_field_t MONERS_f; - }; - __IO uint32_t DREQENB0; - __IO uint32_t DREQENB1; - __IO uint32_t DREQENB2; - __IO uint32_t DREQENB3; - __IO uint32_t DREQENB4; - __IO uint32_t DREQENB5; - __IO uint32_t DREQENB6; - __IO uint32_t DREQENB7; - __IO uint32_t HWINT0; - __IO uint32_t HWINT1; - __IO uint32_t HWINT2; - __IO uint32_t HWINT3; - __IO uint32_t HWINT4; - __IO uint32_t HWINT5; - __IO uint32_t HWINT6; - __IO uint32_t HWINT7; - __IO uint32_t HWINTCLR0; - __IO uint32_t HWINTCLR1; - __IO uint32_t HWINTCLR2; - __IO uint32_t HWINTCLR3; - __IO uint32_t HWINTCLR4; - __IO uint32_t HWINTCLR5; - __IO uint32_t HWINTCLR6; - __IO uint32_t HWINTCLR7; - __IO uint32_t DQMSK0; - __IO uint32_t DQMSK1; - __IO uint32_t DQMSK2; - __IO uint32_t DQMSK3; - __IO uint32_t DQMSK4; - __IO uint32_t DQMSK5; - __IO uint32_t DQMSK6; - __IO uint32_t DQMSK7; - __IO uint32_t DQMSKCLR0; - __IO uint32_t DQMSKCLR1; - __IO uint32_t DQMSKCLR2; - __IO uint32_t DQMSKCLR3; - __IO uint32_t DQMSKCLR4; - __IO uint32_t DQMSKCLR5; - __IO uint32_t DQMSKCLR6; - __IO uint32_t DQMSKCLR7; -}FM4_DSTC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - union { - __IO uint8_t WCRD; - stc_wc_wcrd_field_t WCRD_f; - }; - union { - __IO uint8_t WCRL; - stc_wc_wcrl_field_t WCRL_f; - }; - union { - __IO uint8_t WCCR; - stc_wc_wccr_field_t WCCR_f; - }; - uint8_t RESERVED0[13]; - union { - __IO uint16_t CLK_SEL; - stc_wc_clk_sel_field_t CLK_SEL_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t CLK_EN; - stc_wc_clk_en_field_t CLK_EN_f; - }; -}FM4_WC_TypeDef; - -/****************************************************************************** - * RTC_MODULE - ******************************************************************************/ -/* Real time clock registers */ -typedef struct -{ - union { - __IO uint8_t WTCR10; - stc_rtc_wtcr10_field_t WTCR10_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WTCR11; - stc_rtc_wtcr11_field_t WTCR11_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t WTCR12; - stc_rtc_wtcr12_field_t WTCR12_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t WTCR13; - stc_rtc_wtcr13_field_t WTCR13_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t WTCR20; - stc_rtc_wtcr20_field_t WTCR20_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t WTCR21; - stc_rtc_wtcr21_field_t WTCR21_f; - }; - uint8_t RESERVED6[3]; - __IO uint8_t WTCR22; - uint8_t RESERVED7[3]; - union { - __IO uint8_t WTSR; - stc_rtc_wtsr_field_t WTSR_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t WTMIR; - stc_rtc_wtmir_field_t WTMIR_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t WTHR; - stc_rtc_wthr_field_t WTHR_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t WTDR; - stc_rtc_wtdr_field_t WTDR_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t WTDW; - stc_rtc_wtdw_field_t WTDW_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint8_t WTMOR; - stc_rtc_wtmor_field_t WTMOR_f; - }; - uint8_t RESERVED13[3]; - union { - __IO uint8_t WTYR; - stc_rtc_wtyr_field_t WTYR_f; - }; - uint8_t RESERVED14[3]; - union { - __IO uint8_t ALMIR; - stc_rtc_almir_field_t ALMIR_f; - }; - uint8_t RESERVED15[3]; - union { - __IO uint8_t ALHR; - stc_rtc_alhr_field_t ALHR_f; - }; - uint8_t RESERVED16[3]; - union { - __IO uint8_t ALDR; - stc_rtc_aldr_field_t ALDR_f; - }; - uint8_t RESERVED17[3]; - union { - __IO uint8_t ALMOR; - stc_rtc_almor_field_t ALMOR_f; - }; - uint8_t RESERVED18[3]; - union { - __IO uint8_t ALYR; - stc_rtc_alyr_field_t ALYR_f; - }; - uint8_t RESERVED19[3]; - union { - __IO uint8_t WTTR0; - stc_rtc_wttr0_field_t WTTR0_f; - }; - uint8_t RESERVED20[3]; - union { - __IO uint8_t WTTR1; - stc_rtc_wttr1_field_t WTTR1_f; - }; - uint8_t RESERVED21[3]; - union { - __IO uint8_t WTTR2; - stc_rtc_wttr2_field_t WTTR2_f; - }; - uint8_t RESERVED22[3]; - __IO uint8_t WTCAL0; - uint8_t RESERVED23[3]; - union { - __IO uint8_t WTCAL1; - stc_rtc_wtcal1_field_t WTCAL1_f; - }; - uint8_t RESERVED24[3]; - union { - __IO uint8_t WTCALEN; - stc_rtc_wtcalen_field_t WTCALEN_f; - }; - uint8_t RESERVED25[3]; - union { - __IO uint8_t WTDIV; - stc_rtc_wtdiv_field_t WTDIV_f; - }; - uint8_t RESERVED26[3]; - union { - __IO uint8_t WTDIVEN; - stc_rtc_wtdiven_field_t WTDIVEN_f; - }; - uint8_t RESERVED27[3]; - union { - __IO uint8_t WTCALPRD; - stc_rtc_wtcalprd_field_t WTCALPRD_f; - }; - uint8_t RESERVED28[3]; - union { - __IO uint8_t WTCOSEL; - stc_rtc_wtcosel_field_t WTCOSEL_f; - }; - uint8_t RESERVED29[3]; - union { - __IO uint8_t VB_CLKDIV; - stc_rtc_vb_clkdiv_field_t VB_CLKDIV_f; - }; - uint8_t RESERVED30[3]; - union { - __IO uint8_t WTOSCCNT; - stc_rtc_wtosccnt_field_t WTOSCCNT_f; - }; - uint8_t RESERVED31[3]; - __IO uint8_t CCS; - uint8_t RESERVED32[3]; - __IO uint8_t CCB; - uint8_t RESERVED33[3]; - /* Don't exist on peripheral manual */ - __IO uint8_t TRIM; - uint8_t RESERVED34[3]; - union { - __IO uint8_t BOOST; - stc_rtc_boost_field_t BOOST_f; - }; - uint8_t RESERVED35[3]; - union { - __IO uint8_t EWKUP; - stc_rtc_ewkup_field_t EWKUP_f; - }; - uint8_t RESERVED36[3]; - union { - __IO uint8_t VDET; - stc_rtc_vdet_field_t VDET_f; - }; - uint8_t RESERVED37[3]; - /* Don't exist on peripheral manual */ - __IO uint8_t FDET; - uint8_t RESERVED38[3]; - union { - __IO uint8_t HIBRST; - stc_rtc_hibrst_field_t HIBRST_f; - }; - uint8_t RESERVED39[3]; - union { - __IO uint8_t VBPFR; - stc_rtc_vbpfr_field_t VBPFR_f; - }; - uint8_t RESERVED40[3]; - union { - __IO uint8_t VBPCR; - stc_rtc_vbpcr_field_t VBPCR_f; - }; - uint8_t RESERVED41[3]; - union { - __IO uint8_t VBDDR; - stc_rtc_vbddr_field_t VBDDR_f; - }; - uint8_t RESERVED42[3]; - union { - __IO uint8_t VBDIR; - stc_rtc_vbdir_field_t VBDIR_f; - }; - uint8_t RESERVED43[3]; - union { - __IO uint8_t VBDOR; - stc_rtc_vbdor_field_t VBDOR_f; - }; - uint8_t RESERVED44[3]; - union { - __IO uint8_t VBPZR; - stc_rtc_vbpzr_field_t VBPZR_f; - }; - uint8_t RESERVED45[87]; - union { - __IO uint32_t BREG00_03; - struct { - __IO uint16_t BREG00_01; - __IO uint16_t BREG02_03; - }; - struct { - __IO uint8_t BREG00; - __IO uint8_t BREG01; - __IO uint8_t BREG02; - __IO uint8_t BREG03; - }; - }; - union { - __IO uint32_t BREG04_07; - struct { - __IO uint16_t BREG04_05; - __IO uint16_t BREG06_07; - }; - struct { - __IO uint8_t BREG04; - __IO uint8_t BREG05; - __IO uint8_t BREG06; - __IO uint8_t BREG07; - }; - }; - union { - __IO uint32_t BREG08_0B; - struct { - __IO uint16_t BREG08_09; - __IO uint16_t BREG0A_0B; - }; - struct { - __IO uint8_t BREG08; - __IO uint8_t BREG09; - __IO uint8_t BREG0A; - __IO uint8_t BREG0B; - }; - }; - union { - __IO uint32_t BREG0C_0F; - struct { - __IO uint16_t BREG0C_0D; - __IO uint16_t BREG0E_0F; - }; - struct { - __IO uint8_t BREG0C; - __IO uint8_t BREG0D; - __IO uint8_t BREG0E; - __IO uint8_t BREG0F; - }; - }; - union { - __IO uint32_t BREG10_13; - struct { - __IO uint16_t BREG10_11; - __IO uint16_t BREG12_13; - }; - struct { - __IO uint8_t BREG10; - __IO uint8_t BREG11; - __IO uint8_t BREG12; - __IO uint8_t BREG13; - }; - }; - union { - __IO uint32_t BREG14_17; - struct { - __IO uint16_t BREG14_15; - __IO uint16_t BREG16_17; - }; - struct { - __IO uint8_t BREG14; - __IO uint8_t BREG15; - __IO uint8_t BREG16; - __IO uint8_t BREG17; - }; - }; - union { - __IO uint32_t BREG18_1B; - struct { - __IO uint16_t BREG18_19; - __IO uint16_t BREG1A_1B; - }; - struct { - __IO uint8_t BREG18; - __IO uint8_t BREG19; - __IO uint8_t BREG1A; - __IO uint8_t BREG1B; - }; - }; - union { - __IO uint32_t BREG1C_1F; - struct { - __IO uint16_t BREG1C_1D; - __IO uint16_t BREG1E_1F; - }; - struct { - __IO uint8_t BREG1C; - __IO uint8_t BREG1D; - __IO uint8_t BREG1E; - __IO uint8_t BREG1F; - }; - }; - union { - __IO uint32_t BREG20_23; - struct { - __IO uint16_t BREG20_21; - __IO uint16_t BREG22_23; - }; - struct { - __IO uint8_t BREG20; - __IO uint8_t BREG21; - __IO uint8_t BREG22; - __IO uint8_t BREG23; - }; - }; - union { - __IO uint32_t BREG24_27; - struct { - __IO uint16_t BREG24_25; - __IO uint16_t BREG26_27; - }; - struct { - __IO uint8_t BREG24; - __IO uint8_t BREG25; - __IO uint8_t BREG26; - __IO uint8_t BREG27; - }; - }; - union { - __IO uint32_t BREG28_2B; - struct { - __IO uint16_t BREG28_29; - __IO uint16_t BREG2A_2B; - }; - struct { - __IO uint8_t BREG28; - __IO uint8_t BREG29; - __IO uint8_t BREG2A; - __IO uint8_t BREG2B; - }; - }; - union { - __IO uint32_t BREG2C_2F; - struct { - __IO uint16_t BREG2C_2D; - __IO uint16_t BREG2E_2F; - }; - struct { - __IO uint8_t BREG2C; - __IO uint8_t BREG2D; - __IO uint8_t BREG2E; - __IO uint8_t BREG2F; - }; - }; - union { - __IO uint32_t BREG30_33; - struct { - __IO uint16_t BREG30_31; - __IO uint16_t BREG32_33; - }; - struct { - __IO uint8_t BREG30; - __IO uint8_t BREG31; - __IO uint8_t BREG32; - __IO uint8_t BREG33; - }; - }; - union { - __IO uint32_t BREG34_37; - struct { - __IO uint16_t BREG34_35; - __IO uint16_t BREG36_37; - }; - struct { - __IO uint8_t BREG34; - __IO uint8_t BREG35; - __IO uint8_t BREG36; - __IO uint8_t BREG37; - }; - }; - union { - __IO uint32_t BREG38_3B; - struct { - __IO uint16_t BREG38_39; - __IO uint16_t BREG3A_3B; - }; - struct { - __IO uint8_t BREG38; - __IO uint8_t BREG39; - __IO uint8_t BREG3A; - __IO uint8_t BREG3B; - }; - }; - union { - __IO uint32_t BREG3C_3F; - struct { - __IO uint16_t BREG3C_3D; - __IO uint16_t BREG3E_3F; - }; - struct { - __IO uint8_t BREG3C; - __IO uint8_t BREG3D; - __IO uint8_t BREG3E; - __IO uint8_t BREG3F; - }; - }; - union { - __IO uint32_t BREG40_43; - struct { - __IO uint16_t BREG40_41; - __IO uint16_t BREG42_43; - }; - struct { - __IO uint8_t BREG40; - __IO uint8_t BREG41; - __IO uint8_t BREG42; - __IO uint8_t BREG43; - }; - }; - union { - __IO uint32_t BREG44_47; - struct { - __IO uint16_t BREG44_45; - __IO uint16_t BREG46_47; - }; - struct { - __IO uint8_t BREG44; - __IO uint8_t BREG45; - __IO uint8_t BREG46; - __IO uint8_t BREG47; - }; - }; - union { - __IO uint32_t BREG48_4B; - struct { - __IO uint16_t BREG48_49; - __IO uint16_t BREG4A_4B; - }; - struct { - __IO uint8_t BREG48; - __IO uint8_t BREG49; - __IO uint8_t BREG4A; - __IO uint8_t BREG4B; - }; - }; - union { - __IO uint32_t BREG4C_4F; - struct { - __IO uint16_t BREG4C_4D; - __IO uint16_t BREG4E_4F; - }; - struct { - __IO uint8_t BREG4C; - __IO uint8_t BREG4D; - __IO uint8_t BREG4E; - __IO uint8_t BREG4F; - }; - }; - union { - __IO uint32_t BREG50_53; - struct { - __IO uint16_t BREG50_51; - __IO uint16_t BREG52_53; - }; - struct { - __IO uint8_t BREG50; - __IO uint8_t BREG51; - __IO uint8_t BREG52; - __IO uint8_t BREG53; - }; - }; - union { - __IO uint32_t BREG54_57; - struct { - __IO uint16_t BREG54_55; - __IO uint16_t BREG56_57; - }; - struct { - __IO uint8_t BREG54; - __IO uint8_t BREG55; - __IO uint8_t BREG56; - __IO uint8_t BREG57; - }; - }; - union { - __IO uint32_t BREG58_5B; - struct { - __IO uint16_t BREG58_59; - __IO uint16_t BREG5A_5B; - }; - struct { - __IO uint8_t BREG58; - __IO uint8_t BREG59; - __IO uint8_t BREG5A; - __IO uint8_t BREG5B; - }; - }; - union { - __IO uint32_t BREG5C_5F; - struct { - __IO uint16_t BREG5C_5D; - __IO uint16_t BREG5E_5F; - }; - struct { - __IO uint8_t BREG5C; - __IO uint8_t BREG5D; - __IO uint8_t BREG5E; - __IO uint8_t BREG5F; - }; - }; - union { - __IO uint32_t BREG60_63; - struct { - __IO uint16_t BREG60_61; - __IO uint16_t BREG62_63; - }; - struct { - __IO uint8_t BREG60; - __IO uint8_t BREG61; - __IO uint8_t BREG62; - __IO uint8_t BREG63; - }; - }; - union { - __IO uint32_t BREG64_67; - struct { - __IO uint16_t BREG64_65; - __IO uint16_t BREG66_67; - }; - struct { - __IO uint8_t BREG64; - __IO uint8_t BREG65; - __IO uint8_t BREG66; - __IO uint8_t BREG67; - }; - }; - union { - __IO uint32_t BREG68_6B; - struct { - __IO uint16_t BREG68_69; - __IO uint16_t BREG6A_6B; - }; - struct { - __IO uint8_t BREG68; - __IO uint8_t BREG69; - __IO uint8_t BREG6A; - __IO uint8_t BREG6B; - }; - }; - union { - __IO uint32_t BREG6C_6F; - struct { - __IO uint16_t BREG6C_6D; - __IO uint16_t BREG6E_6F; - }; - struct { - __IO uint8_t BREG6C; - __IO uint8_t BREG6D; - __IO uint8_t BREG6E; - __IO uint8_t BREG6F; - }; - }; - union { - __IO uint32_t BREG70_73; - struct { - __IO uint16_t BREG70_71; - __IO uint16_t BREG72_73; - }; - struct { - __IO uint8_t BREG70; - __IO uint8_t BREG71; - __IO uint8_t BREG72; - __IO uint8_t BREG73; - }; - }; - union { - __IO uint32_t BREG74_77; - struct { - __IO uint16_t BREG74_75; - __IO uint16_t BREG76_77; - }; - struct { - __IO uint8_t BREG74; - __IO uint8_t BREG75; - __IO uint8_t BREG76; - __IO uint8_t BREG77; - }; - }; - union { - __IO uint32_t BREG78_7B; - struct { - __IO uint16_t BREG78_79; - __IO uint16_t BREG7A_7B; - }; - struct { - __IO uint8_t BREG78; - __IO uint8_t BREG79; - __IO uint8_t BREG7A; - __IO uint8_t BREG7B; - }; - }; - union { - __IO uint32_t BREG7C_7F; - struct { - __IO uint16_t BREG7C_7D; - __IO uint16_t BREG7E_7F; - }; - struct { - __IO uint8_t BREG7C; - __IO uint8_t BREG7D; - __IO uint8_t BREG7E; - __IO uint8_t BREG7F; - }; - }; -}FM4_RTC_TypeDef; - -/****************************************************************************** - * LCR_MODULE - ******************************************************************************/ -/* Low-speed CR prescaler registers */ -typedef struct -{ - union { - __IO uint8_t LCR_PRSLD; - stc_lcr_lcr_prsld_field_t LCR_PRSLD_f; - }; -}FM4_LCR_TypeDef; - -/****************************************************************************** - * CLK_GATING_MODULE - ******************************************************************************/ -/* CLK_GATING registers */ -typedef struct -{ - union { - __IO uint32_t CKEN0; - stc_clk_gating_cken0_field_t CKEN0_f; - }; - union { - __IO uint32_t MRST0; - stc_clk_gating_mrst0_field_t MRST0_f; - }; - uint8_t RESERVED1[8]; - union { - __IO uint32_t CKEN1; - stc_clk_gating_cken1_field_t CKEN1_f; - }; - union { - __IO uint32_t MRST1; - stc_clk_gating_mrst1_field_t MRST1_f; - }; - uint8_t RESERVED3[8]; - union { - __IO uint32_t CKEN2; - stc_clk_gating_cken2_field_t CKEN2_f; - }; - union { - __IO uint32_t MRST2; - stc_clk_gating_mrst2_field_t MRST2_f; - }; -}FM4_CLK_GATING_TypeDef; - -/****************************************************************************** - * PLL_CONTROL_MODULE - ******************************************************************************/ -/* PLL_CONTROL registers */ -typedef struct -{ - __IO uint32_t SSCTL1; - __IO uint32_t SSCTL2; -}FM4_PLL_CONTROL_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - union { - __IO uint32_t MODE0; - stc_exbus_mode_field_t MODE0_f; - }; - union { - __IO uint32_t MODE1; - stc_exbus_mode_field_t MODE1_f; - }; - union { - __IO uint32_t MODE2; - stc_exbus_mode_field_t MODE2_f; - }; - union { - __IO uint32_t MODE3; - stc_exbus_mode_field_t MODE3_f; - }; - union { - __IO uint32_t MODE4; - stc_exbus_mode_field_t MODE4_f; - }; - union { - __IO uint32_t MODE5; - stc_exbus_mode_field_t MODE5_f; - }; - union { - __IO uint32_t MODE6; - stc_exbus_mode_field_t MODE6_f; - }; - union { - __IO uint32_t MODE7; - stc_exbus_mode_field_t MODE7_f; - }; - union { - __IO uint32_t TIM0; - stc_exbus_tim_field_t TIM0_f; - }; - __IO uint32_t TIM1; - union { - __IO uint32_t TIM2; - stc_exbus_tim_field_t TIM2_f; - }; - union { - __IO uint32_t TIM3; - stc_exbus_tim_field_t TIM3_f; - }; - union { - __IO uint32_t TIM4; - stc_exbus_tim_field_t TIM4_f; - }; - union { - __IO uint32_t TIM5; - stc_exbus_tim_field_t TIM5_f; - }; - union { - __IO uint32_t TIM6; - stc_exbus_tim_field_t TIM6_f; - }; - union { - __IO uint32_t TIM7; - stc_exbus_tim_field_t TIM7_f; - }; - union { - __IO uint32_t AREA0; - stc_exbus_area_field_t AREA0_f; - }; - union { - __IO uint32_t AREA1; - stc_exbus_area_field_t AREA1_f; - }; - union { - __IO uint32_t AREA2; - stc_exbus_area_field_t AREA2_f; - }; - union { - __IO uint32_t AREA3; - stc_exbus_area_field_t AREA3_f; - }; - union { - __IO uint32_t AREA4; - stc_exbus_area_field_t AREA4_f; - }; - union { - __IO uint32_t AREA5; - stc_exbus_area_field_t AREA5_f; - }; - union { - __IO uint32_t AREA6; - stc_exbus_area_field_t AREA6_f; - }; - union { - __IO uint32_t AREA7; - stc_exbus_area_field_t AREA7_f; - }; - union { - __IO uint32_t ATIM0; - stc_exbus_atim_field_t ATIM0_f; - }; - union { - __IO uint32_t ATIM1; - stc_exbus_atim_field_t ATIM1_f; - }; - union { - __IO uint32_t ATIM2; - stc_exbus_atim_field_t ATIM2_f; - }; - union { - __IO uint32_t ATIM3; - stc_exbus_atim_field_t ATIM3_f; - }; - union { - __IO uint32_t ATIM4; - stc_exbus_atim_field_t ATIM4_f; - }; - union { - __IO uint32_t ATIM5; - stc_exbus_atim_field_t ATIM5_f; - }; - union { - __IO uint32_t ATIM6; - stc_exbus_atim_field_t ATIM6_f; - }; - union { - __IO uint32_t ATIM7; - stc_exbus_atim_field_t ATIM7_f; - }; - uint8_t RESERVED1[128]; - union { - __IO uint32_t SDMODE; - stc_exbus_sdmode_field_t SDMODE_f; - }; - union { - __IO uint32_t REFTIM; - stc_exbus_reftim_field_t REFTIM_f; - }; - union { - __IO uint32_t PWRDWN; - stc_exbus_pwrdwn_field_t PWRDWN_f; - }; - union { - __IO uint32_t SDTIM; - stc_exbus_sdtim_field_t SDTIM_f; - }; - union { - __IO uint32_t SDCMD; - stc_exbus_sdcmd_field_t SDCMD_f; - }; - uint8_t RESERVED2[236]; - union { - __IO uint32_t MEMCERR; - stc_exbus_memcerr_field_t MEMCERR_f; - }; - uint8_t RESERVED3[252]; - union { - __IO uint32_t DCLKR; - stc_exbus_dclkr_field_t DCLKR_f; - }; - union { - __IO uint32_t EST; - stc_exbus_est_field_t EST_f; - }; - union { - __IO uint32_t WEAD; - stc_exbus_wead_field_t WEAD_f; - }; - union { - __IO uint32_t ESCLR; - stc_exbus_esclr_field_t ESCLR_f; - }; - union { - __IO uint32_t AMODE; - stc_exbus_amode_field_t AMODE_f; - }; -}FM4_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - union { - __IO uint16_t HCNT; - stc_usb_hcnt_field_t HCNT_f; - }; - struct { - union { - __IO uint8_t HCNT0; - stc_usb_hcnt0_field_t HCNT0_f; - }; - union { - __IO uint8_t HCNT1; - stc_usb_hcnt1_field_t HCNT1_f; - }; - }; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t HIRQ; - stc_usb_hirq_field_t HIRQ_f; - }; - union { - __IO uint8_t HERR; - stc_usb_herr_field_t HERR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t HSTATE; - stc_usb_hstate_field_t HSTATE_f; - }; - union { - __IO uint8_t HFCOMP; - stc_usb_hfcomp_field_t HFCOMP_f; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t HRTIMER; - stc_usb_hrtimer_field_t HRTIMER_f; - }; - struct { - union { - __IO uint8_t HRTIMER0; - stc_usb_hrtimer0_field_t HRTIMER0_f; - }; - union { - __IO uint8_t HRTIMER1; - stc_usb_hrtimer1_field_t HRTIMER1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t HRTIMER2; - stc_usb_hrtimer2_field_t HRTIMER2_f; - }; - union { - __IO uint8_t HADR; - stc_usb_hadr_field_t HADR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t HEOF; - stc_usb_heof_field_t HEOF_f; - }; - struct { - union { - __IO uint8_t HEOF0; - stc_usb_heof0_field_t HEOF0_f; - }; - union { - __IO uint8_t HEOF1; - stc_usb_heof1_field_t HEOF1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t HFRAME; - stc_usb_hframe_field_t HFRAME_f; - }; - struct { - union { - __IO uint8_t HFRAME0; - stc_usb_hframe0_field_t HFRAME0_f; - }; - union { - __IO uint8_t HFRAME1; - stc_usb_hframe1_field_t HFRAME1_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t HTOKEN; - stc_usb_htoken_field_t HTOKEN_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t UDCC; - stc_usb_udcc_field_t UDCC_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t EP0C; - stc_usb_ep0c_field_t EP0C_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t EP1C; - stc_usb_ep1c_field_t EP1C_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint16_t EP2C; - stc_usb_ep2c_field_t EP2C_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t EP3C; - stc_usb_ep3c_field_t EP3C_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint16_t EP4C; - stc_usb_ep4c_field_t EP4C_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint16_t EP5C; - stc_usb_ep5c_field_t EP5C_f; - }; - uint8_t RESERVED14[2]; - union { - __IO uint16_t TMSP; - stc_usb_tmsp_field_t TMSP_f; - }; - uint8_t RESERVED15[2]; - union { - __IO uint8_t UDCS; - stc_usb_udcs_field_t UDCS_f; - }; - union { - __IO uint8_t UDCIE; - stc_usb_udcie_field_t UDCIE_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t EP0IS; - stc_usb_ep0is_field_t EP0IS_f; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t EP0OS; - stc_usb_ep0os_field_t EP0OS_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t EP1S; - stc_usb_ep1s_field_t EP1S_f; - }; - uint8_t RESERVED19[2]; - union { - __IO uint16_t EP2S; - stc_usb_ep2s_field_t EP2S_f; - }; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - union { - __IO uint16_t EP4S; - stc_usb_ep4s_field_t EP4S_f; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t EP5S; - stc_usb_ep5s_field_t EP5S_f; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM4_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - union { - __IO uint32_t DMACR; - stc_dmac_dmacr_field_t DMACR_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint32_t DMACA0; - stc_dmac_dmaca0_field_t DMACA0_f; - }; - union { - __IO uint32_t DMACB0; - stc_dmac_dmacb0_field_t DMACB0_f; - }; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - union { - __IO uint32_t DMACA1; - stc_dmac_dmaca1_field_t DMACA1_f; - }; - union { - __IO uint32_t DMACB1; - stc_dmac_dmacb1_field_t DMACB1_f; - }; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - union { - __IO uint32_t DMACA2; - stc_dmac_dmaca2_field_t DMACA2_f; - }; - union { - __IO uint32_t DMACB2; - stc_dmac_dmacb2_field_t DMACB2_f; - }; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - union { - __IO uint32_t DMACA3; - stc_dmac_dmaca3_field_t DMACA3_f; - }; - union { - __IO uint32_t DMACB3; - stc_dmac_dmacb3_field_t DMACB3_f; - }; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - union { - __IO uint32_t DMACA4; - stc_dmac_dmaca4_field_t DMACA4_f; - }; - union { - __IO uint32_t DMACB4; - stc_dmac_dmacb4_field_t DMACB4_f; - }; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - union { - __IO uint32_t DMACA5; - stc_dmac_dmaca5_field_t DMACA5_f; - }; - union { - __IO uint32_t DMACB5; - stc_dmac_dmacb5_field_t DMACB5_f; - }; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - union { - __IO uint32_t DMACA6; - stc_dmac_dmaca6_field_t DMACA6_f; - }; - union { - __IO uint32_t DMACB6; - stc_dmac_dmacb6_field_t DMACB6_f; - }; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - union { - __IO uint32_t DMACA7; - stc_dmac_dmaca7_field_t DMACA7_f; - }; - union { - __IO uint32_t DMACB7; - stc_dmac_dmacb7_field_t DMACB7_f; - }; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM4_DMAC_TypeDef; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN channel 0 registers */ -typedef struct -{ - union { - __IO uint16_t CTRLR; - stc_can_ctrlr_field_t CTRLR_f; - }; - union { - __IO uint16_t STATR; - stc_can_statr_field_t STATR_f; - }; - union { - __IO uint16_t ERRCNT; - stc_can_errcnt_field_t ERRCNT_f; - }; - union { - __IO uint16_t BTR; - stc_can_btr_field_t BTR_f; - }; - union { - __IO uint16_t INTR; - stc_can_intr_field_t INTR_f; - }; - union { - __IO uint16_t TESTR; - stc_can_testr_field_t TESTR_f; - }; - union { - __IO uint16_t BRPER; - stc_can_brper_field_t BRPER_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint16_t IF1CREQ; - stc_can_if1creq_field_t IF1CREQ_f; - }; - union { - __IO uint16_t IF1CMSK; - stc_can_if1cmsk_field_t IF1CMSK_f; - }; - union { - union { - __IO uint32_t IF1MSK; - stc_can_if1msk_field_t IF1MSK_f; - }; - struct { - __IO uint16_t IF1MSK1; - union { - __IO uint16_t IF1MSK2; - stc_can_if1msk2_field_t IF1MSK2_f; - }; - }; - }; - union { - union { - __IO uint32_t IF1ARB; - stc_can_if1arb_field_t IF1ARB_f; - }; - struct { - __IO uint16_t IF1ARB1; - union { - __IO uint16_t IF1ARB2; - stc_can_if1arb2_field_t IF1ARB2_f; - }; - }; - }; - union { - __IO uint16_t IF1MCTR; - stc_can_if1mctr_field_t IF1MCTR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint32_t IF1DTA_L; - struct { - __IO uint16_t IF1DTA1_L; - __IO uint16_t IF1DTA2_L; - }; - }; - union { - __IO uint32_t IF1DTB_L; - struct { - __IO uint16_t IF1DTB1_L; - __IO uint16_t IF1DTB2_L; - }; - }; - uint8_t RESERVED2[8]; - union { - __IO uint32_t IF1DTA_B; - struct { - __IO uint16_t IF1DTA2_B; - __IO uint16_t IF1DTA1_B; - }; - }; - union { - __IO uint32_t IF1DTB_B; - struct { - __IO uint16_t IF1DTB2_B; - __IO uint16_t IF1DTB1_B; - }; - }; - uint8_t RESERVED3[8]; - union { - __IO uint16_t IF2CREQ; - stc_can_if2creq_field_t IF2CREQ_f; - }; - union { - __IO uint16_t IF2CMSK; - stc_can_if2cmsk_field_t IF2CMSK_f; - }; - union { - union { - __IO uint32_t IF2MSK; - stc_can_if2msk_field_t IF2MSK_f; - }; - struct { - __IO uint16_t IF2MSK1; - union { - __IO uint16_t IF2MSK2; - stc_can_if2msk2_field_t IF2MSK2_f; - }; - }; - }; - union { - __IO uint32_t IF2ARB; - struct { - __IO uint16_t IF2ARB1; - union { - __IO uint16_t IF2ARB2; - stc_can_if2arb2_field_t IF2ARB2_f; - }; - }; - }; - union { - __IO uint16_t IF2MCTR; - stc_can_if2mctr_field_t IF2MCTR_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint32_t IF2DTA_L; - struct { - __IO uint16_t IF2DTA1_L; - __IO uint16_t IF2DTA2_L; - }; - }; - union { - __IO uint32_t IF2DTB_L; - struct { - __IO uint16_t IF2DTB1_L; - __IO uint16_t IF2DTB2_L; - }; - }; - uint8_t RESERVED5[8]; - union { - __IO uint32_t IF2DTA_B; - struct { - __IO uint16_t IF2DTA2_B; - __IO uint16_t IF2DTA1_B; - }; - }; - union { - __IO uint32_t IF2DTB_B; - struct { - __IO uint16_t IF2DTB2_B; - __IO uint16_t IF2DTB1_B; - }; - }; - uint8_t RESERVED6[24]; - union { - union { - __IO uint32_t TREQR; - stc_can_treqr_field_t TREQR_f; - }; - struct { - union { - __IO uint16_t TREQR1; - stc_can_treqr1_field_t TREQR1_f; - }; - union { - __IO uint16_t TREQR2; - stc_can_treqr2_field_t TREQR2_f; - }; - }; - }; - uint8_t RESERVED7[12]; - union { - union { - __IO uint32_t NEWDT; - stc_can_newdt_field_t NEWDT_f; - }; - struct { - union { - __IO uint16_t NEWDT1; - stc_can_newdt1_field_t NEWDT1_f; - }; - __IO uint16_t NEWDT2; - }; - }; - uint8_t RESERVED8[12]; - union { - union { - __IO uint32_t INTPND; - stc_can_intpnd_field_t INTPND_f; - }; - struct { - union { - __IO uint16_t INTPND1; - stc_can_intpnd1_field_t INTPND1_f; - }; - union { - __IO uint16_t INTPND2; - stc_can_intpnd2_field_t INTPND2_f; - }; - }; - }; - uint8_t RESERVED9[12]; - union { - union { - __IO uint32_t MSGVAL; - stc_can_msgval_field_t MSGVAL_f; - }; - struct { - union { - __IO uint16_t MSGVAL1; - stc_can_msgval1_field_t MSGVAL1_f; - }; - union { - __IO uint16_t MSGVAL2; - stc_can_msgval2_field_t MSGVAL2_f; - }; - }; - }; -}FM4_CAN_TypeDef; - -/****************************************************************************** - * SDIF_MODULE - ******************************************************************************/ -/* SD interface registers */ - - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM4_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM4_WORKFLASH_BASE (0x200C0000UL) /* Work Flash Base */ -#define FM4_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM4_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM4_WORKFLASH_IF_BASE (FM4_WORKFLASH_BASE + 0x20000UL) /* Work Flash interface registers */ -#define FM4_FLASH_IF_BASE (FM4_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM4_UNIQUE_ID_BASE (FM4_PERIPH_BASE + 0x00200UL) /* Unique ID registers */ -#define FM4_ECC_CAPTURE_BASE (FM4_PERIPH_BASE + 0x00300UL) /* ECC Capture address registers */ -#define FM4_CRG_BASE (FM4_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM4_HWWDT_BASE (FM4_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM4_SWWDT_BASE (FM4_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM4_DTIM_BASE (FM4_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM4_MFT0_FRT_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM4_MFT0_OCU_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM4_MFT0_WFG_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM4_MFT0_ICU_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM4_MFT0_ADCMP_BASE (FM4_PERIPH_BASE + 0x20100UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM4_MFT1_FRT_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM4_MFT1_OCU_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM4_MFT1_WFG_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM4_MFT1_ICU_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM4_MFT1_ADCMP_BASE (FM4_PERIPH_BASE + 0x21100UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM4_MFT2_FRT_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Free Running Timer registers */ -#define FM4_MFT2_OCU_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ -#define FM4_MFT2_WFG_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define FM4_MFT2_ICU_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ -#define FM4_MFT2_ADCMP_BASE (FM4_PERIPH_BASE + 0x22100UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define FM4_MFT_PPG_BASE (FM4_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM4_BT0_PPG_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM4_BT0_PWM_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM4_BT0_RT_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM4_BT0_PWC_BASE (FM4_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM4_BT1_PPG_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM4_BT1_PWM_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM4_BT1_RT_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM4_BT1_PWC_BASE (FM4_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM4_BT2_PPG_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM4_BT2_PWM_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM4_BT2_RT_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM4_BT2_PWC_BASE (FM4_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM4_BT3_PPG_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM4_BT3_PWM_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM4_BT3_RT_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM4_BT3_PWC_BASE (FM4_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM4_BT4_PPG_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM4_BT4_PWM_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM4_BT4_RT_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM4_BT4_PWC_BASE (FM4_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM4_BT5_PPG_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM4_BT5_PWM_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM4_BT5_RT_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM4_BT5_PWC_BASE (FM4_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM4_BT6_PPG_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM4_BT6_PWM_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM4_BT6_RT_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM4_BT6_PWC_BASE (FM4_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM4_BT7_PPG_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM4_BT7_PWM_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM4_BT7_RT_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM4_BT7_PWC_BASE (FM4_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM4_BTIOSEL03_BASE (FM4_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM4_BTIOSEL47_BASE (FM4_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM4_BT8_PPG_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ -#define FM4_BT8_PWM_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ -#define FM4_BT8_RT_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ -#define FM4_BT8_PWC_BASE (FM4_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ -#define FM4_BT9_PPG_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ -#define FM4_BT9_PWM_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ -#define FM4_BT9_RT_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ -#define FM4_BT9_PWC_BASE (FM4_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ -#define FM4_BT10_PPG_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ -#define FM4_BT10_PWM_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ -#define FM4_BT10_RT_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ -#define FM4_BT10_PWC_BASE (FM4_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ -#define FM4_BT11_PPG_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ -#define FM4_BT11_PWM_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ -#define FM4_BT11_RT_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ -#define FM4_BT11_PWC_BASE (FM4_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ -#define FM4_BT12_PPG_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ -#define FM4_BT12_PWM_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ -#define FM4_BT12_RT_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ -#define FM4_BT12_PWC_BASE (FM4_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ -#define FM4_BT13_PPG_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ -#define FM4_BT13_PWM_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ -#define FM4_BT13_RT_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ -#define FM4_BT13_PWC_BASE (FM4_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ -#define FM4_BT14_PPG_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ -#define FM4_BT14_PWM_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ -#define FM4_BT14_RT_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ -#define FM4_BT14_PWC_BASE (FM4_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ -#define FM4_BT15_PPG_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ -#define FM4_BT15_PWM_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ -#define FM4_BT15_RT_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ -#define FM4_BT15_PWC_BASE (FM4_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ -#define FM4_BTIOSEL8B_BASE (FM4_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ -#define FM4_BTIOSELCF_BASE (FM4_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ -#define FM4_SBSSR_BASE (FM4_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM4_QPRC0_BASE (FM4_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM4_QPRC1_BASE (FM4_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM4_QPRC2_BASE (FM4_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ -#define FM4_QPRC3_BASE (FM4_PERIPH_BASE + 0x260C0UL) /* Quad position and revolution counter channel 3 registers */ -#define FM4_QPRC0_NF_BASE (FM4_PERIPH_BASE + 0x26100UL) /* Quad position and revolution counter channel 0 noise filter registers */ -#define FM4_QPRC1_NF_BASE (FM4_PERIPH_BASE + 0x26110UL) /* Quad position and revolution counter channel 0 noise filter registers */ -#define FM4_QPRC2_NF_BASE (FM4_PERIPH_BASE + 0x26120UL) /* Quad position and revolution counter channel 0 noise filter registers */ -#define FM4_QPRC3_NF_BASE (FM4_PERIPH_BASE + 0x26130UL) /* Quad position and revolution counter channel 0 noise filter registers */ -#define FM4_ADC0_BASE (FM4_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM4_ADC1_BASE (FM4_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM4_ADC2_BASE (FM4_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM4_DAC0_BASE (FM4_PERIPH_BASE + 0x33000UL) /* 12-bit DAC uint 0 registers */ -#define FM4_DAC1_BASE (FM4_PERIPH_BASE + 0x33008UL) /* 12-bit DAC uint 1 registers */ -#define FM4_CRTRIM_BASE (FM4_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM4_EXTI_BASE (FM4_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM4_INTREQ_BASE (FM4_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM4_IRQSEL_BASE (FM4_PERIPH_BASE + 0x31110UL) /* Interrupt Selector */ -#define FM4_GPIO_BASE (FM4_PERIPH_BASE + 0x6F000UL) /* General purpose I/O registers */ -#define FM4_LVD_BASE (FM4_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM4_DS_BASE (FM4_PERIPH_BASE + 0x35100UL) /* Deep standby mode registers */ -#define FM4_USBCLK_BASE (FM4_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM4_CANPRES_BASE (FM4_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ -#define FM4_MFS0_BASE (FM4_PERIPH_BASE + 0x38000UL) /* MFS channel 0 registers */ -#define FM4_MFS1_BASE (FM4_PERIPH_BASE + 0x38100UL) /* MFS channel 1 registers */ -#define FM4_MFS2_BASE (FM4_PERIPH_BASE + 0x38200UL) /* MFS channel 2 registers */ -#define FM4_MFS3_BASE (FM4_PERIPH_BASE + 0x38300UL) /* MFS channel 3 registers */ -#define FM4_MFS4_BASE (FM4_PERIPH_BASE + 0x38400UL) /* MFS channel 4 registers */ -#define FM4_MFS5_BASE (FM4_PERIPH_BASE + 0x38500UL) /* MFS channel 5 registers */ -#define FM4_MFS6_BASE (FM4_PERIPH_BASE + 0x38600UL) /* MFS channel 6 registers */ -#define FM4_MFS7_BASE (FM4_PERIPH_BASE + 0x38700UL) /* MFS channel 7 registers */ -#define FM4_MFS8_BASE (FM4_PERIPH_BASE + 0x38800UL) /* MFS channel 8 registers */ -#define FM4_MFS9_BASE (FM4_PERIPH_BASE + 0x38900UL) /* MFS channel 9 registers */ -#define FM4_MFS10_BASE (FM4_PERIPH_BASE + 0x38A00UL) /* MFS channel 10 registers */ -#define FM4_MFS11_BASE (FM4_PERIPH_BASE + 0x38B00UL) /* MFS channel 11 registers */ -#define FM4_MFS12_BASE (FM4_PERIPH_BASE + 0x38C00UL) /* MFS channel 12 registers */ -#define FM4_MFS13_BASE (FM4_PERIPH_BASE + 0x38D00UL) /* MFS channel 13 registers */ -#define FM4_MFS14_BASE (FM4_PERIPH_BASE + 0x38E00UL) /* MFS channel 14 registers */ -#define FM4_MFS15_BASE (FM4_PERIPH_BASE + 0x38F00UL) /* MFS channel 15 registers */ -#define FM4_MFS_NFC_BASE (FM4_PERIPH_BASE + 0x38FFFF0) /* JUST A RANDOM ADDRESS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ -#define FM4_CRC_BASE (FM4_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM4_WC_BASE (FM4_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM4_RTC_BASE (FM4_PERIPH_BASE + 0x3B100UL) /* RTC registers */ -#define FM4_LCR_BASE (FM4_PERIPH_BASE + 0x3C000UL) /* Low-speed CR prescaler registers */ -#define FM4_CLK_GATING_BASE (FM4_PERIPH_BASE + 0x3C100UL) /* Peripheral Clock Gating registers */ -#define FM4_PLL_CONTROL_BASE (FM4_PERIPH_BASE + 0x3C800UL) /* Main PLL Control registers */ -#define FM4_EXBUS_BASE (FM4_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM4_USB0_BASE (FM4_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM4_DMAC_BASE (FM4_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM4_DSTC_BASE (FM4_PERIPH_BASE + 0x61000UL) /* DSTC controller */ -#define FM4_CAN0_BASE (FM4_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ -#define FM4_CAN1_BASE (FM4_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ -#define FM4_SDIF_BASE (FM4_PERIPH_BASE + 0x6E000UL) /* SDIF registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM4_WORKFLASH_IF ((FM4_WORKFLASH_IF_TypeDef *)FM4_WORKFLASH_IF_BASE) -#define FM4_FLASH_IF ((FM4_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) -#define FM4_UNIQUE_ID ((FM4_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) -#define FM4_ECC_CAPTURE ((FM4_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) -#define FM4_CRG ((FM4_CRG_TypeDef *)FM4_CRG_BASE) -#define FM4_HWWDT ((FM4_HWWDT_TypeDef *)FM4_HWWDT_BASE) -#define FM4_SWWDT ((FM4_SWWDT_TypeDef *)FM4_SWWDT_BASE) -#define FM4_DTIM ((FM4_DTIM_TypeDef *)FM4_DTIM_BASE) -#define FM4_MFT0_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT0_FRT_BASE) -#define FM4_MFT0_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT0_OCU_BASE) -#define FM4_MFT0_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT0_WFG_BASE) -#define FM4_MFT0_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT0_ICU_BASE) -#define FM4_MFT0_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT0_ADCMP_BASE) -#define FM4_MFT1_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT1_FRT_BASE) -#define FM4_MFT1_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT1_OCU_BASE) -#define FM4_MFT1_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT1_WFG_BASE) -#define FM4_MFT1_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT1_ICU_BASE) -#define FM4_MFT1_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT1_ADCMP_BASE) -#define FM4_MFT2_FRT ((FM4_MFT_FRT_TypeDef *)FM4_MFT2_FRT_BASE) -#define FM4_MFT2_OCU ((FM4_MFT_OCU_TypeDef *)FM4_MFT2_OCU_BASE) -#define FM4_MFT2_WFG ((FM4_MFT_WFG_TypeDef *)FM4_MFT2_WFG_BASE) -#define FM4_MFT2_ICU ((FM4_MFT_ICU_TypeDef *)FM4_MFT2_ICU_BASE) -#define FM4_MFT2_ADCMP ((FM4_MFT_ADCMP_TypeDef *)FM4_MFT2_ADCMP_BASE) -#define FM4_MFT_PPG ((FM4_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) -#define FM4_BT0_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT0_PPG_BASE) -#define FM4_BT0_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT0_PWM_BASE) -#define FM4_BT0_RT ((FM4_BT_RT_TypeDef *)FM4_BT0_RT_BASE) -#define FM4_BT0_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT0_PWC_BASE) -#define FM4_BT1_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT1_PPG_BASE) -#define FM4_BT1_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT1_PWM_BASE) -#define FM4_BT1_RT ((FM4_BT_RT_TypeDef *)FM4_BT1_RT_BASE) -#define FM4_BT1_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT1_PWC_BASE) -#define FM4_BT2_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT2_PPG_BASE) -#define FM4_BT2_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT2_PWM_BASE) -#define FM4_BT2_RT ((FM4_BT_RT_TypeDef *)FM4_BT2_RT_BASE) -#define FM4_BT2_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT2_PWC_BASE) -#define FM4_BT3_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT3_PPG_BASE) -#define FM4_BT3_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT3_PWM_BASE) -#define FM4_BT3_RT ((FM4_BT_RT_TypeDef *)FM4_BT3_RT_BASE) -#define FM4_BT3_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT3_PWC_BASE) -#define FM4_BT4_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT4_PPG_BASE) -#define FM4_BT4_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT4_PWM_BASE) -#define FM4_BT4_RT ((FM4_BT_RT_TypeDef *)FM4_BT4_RT_BASE) -#define FM4_BT4_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT4_PWC_BASE) -#define FM4_BT5_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT5_PPG_BASE) -#define FM4_BT5_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT5_PWM_BASE) -#define FM4_BT5_RT ((FM4_BT_RT_TypeDef *)FM4_BT5_RT_BASE) -#define FM4_BT5_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT5_PWC_BASE) -#define FM4_BT6_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT6_PPG_BASE) -#define FM4_BT6_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT6_PWM_BASE) -#define FM4_BT6_RT ((FM4_BT_RT_TypeDef *)FM4_BT6_RT_BASE) -#define FM4_BT6_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT6_PWC_BASE) -#define FM4_BT7_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT7_PPG_BASE) -#define FM4_BT7_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT7_PWM_BASE) -#define FM4_BT7_RT ((FM4_BT_RT_TypeDef *)FM4_BT7_RT_BASE) -#define FM4_BT7_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT7_PWC_BASE) -#define FM4_BTIOSEL03 ((FM4_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) -#define FM4_BTIOSEL47 ((FM4_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) -#define FM4_BT8_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT8_PPG_BASE) -#define FM4_BT8_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT8_PWM_BASE) -#define FM4_BT8_RT ((FM4_BT_RT_TypeDef *)FM4_BT8_RT_BASE) -#define FM4_BT8_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT8_PWC_BASE) -#define FM4_BT9_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT9_PPG_BASE) -#define FM4_BT9_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT9_PWM_BASE) -#define FM4_BT9_RT ((FM4_BT_RT_TypeDef *)FM4_BT9_RT_BASE) -#define FM4_BT9_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT9_PWC_BASE) -#define FM4_BT10_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT10_PPG_BASE) -#define FM4_BT10_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT10_PWM_BASE) -#define FM4_BT10_RT ((FM4_BT_RT_TypeDef *)FM4_BT10_RT_BASE) -#define FM4_BT10_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT10_PWC_BASE) -#define FM4_BT11_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT11_PPG_BASE) -#define FM4_BT11_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT11_PWM_BASE) -#define FM4_BT11_RT ((FM4_BT_RT_TypeDef *)FM4_BT11_RT_BASE) -#define FM4_BT11_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT11_PWC_BASE) -#define FM4_BT12_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT12_PPG_BASE) -#define FM4_BT12_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT12_PWM_BASE) -#define FM4_BT12_RT ((FM4_BT_RT_TypeDef *)FM4_BT12_RT_BASE) -#define FM4_BT12_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT12_PWC_BASE) -#define FM4_BT13_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT13_PPG_BASE) -#define FM4_BT13_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT13_PWM_BASE) -#define FM4_BT13_RT ((FM4_BT_RT_TypeDef *)FM4_BT13_RT_BASE) -#define FM4_BT13_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT13_PWC_BASE) -#define FM4_BT14_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT14_PPG_BASE) -#define FM4_BT14_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT14_PWM_BASE) -#define FM4_BT14_RT ((FM4_BT_RT_TypeDef *)FM4_BT14_RT_BASE) -#define FM4_BT14_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT14_PWC_BASE) -#define FM4_BT15_PPG ((FM4_BT_PPG_TypeDef *)FM4_BT15_PPG_BASE) -#define FM4_BT15_PWM ((FM4_BT_PWM_TypeDef *)FM4_BT15_PWM_BASE) -#define FM4_BT15_RT ((FM4_BT_RT_TypeDef *)FM4_BT15_RT_BASE) -#define FM4_BT15_PWC ((FM4_BT_PWC_TypeDef *)FM4_BT15_PWC_BASE) -#define FM4_BTIOSEL8B ((FM4_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) -#define FM4_BTIOSELCF ((FM4_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) -#define FM4_SBSSR ((FM4_SBSSR_TypeDef *)FM4_SBSSR_BASE) -#define FM4_QPRC0 ((FM4_QPRC_TypeDef *)FM4_QPRC0_BASE) -#define FM4_QPRC1 ((FM4_QPRC_TypeDef *)FM4_QPRC1_BASE) -#define FM4_QPRC2 ((FM4_QPRC_TypeDef *)FM4_QPRC2_BASE) -#define FM4_QPRC3 ((FM4_QPRC_TypeDef *)FM4_QPRC3_BASE) -#define FM4_QPRC0_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) -#define FM4_QPRC1_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) -#define FM4_QPRC2_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) -#define FM4_QPRC3_NF ((FM4_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) -#define FM4_ADC0 ((FM4_ADC_TypeDef *)FM4_ADC0_BASE) -#define FM4_ADC1 ((FM4_ADC_TypeDef *)FM4_ADC1_BASE) -#define FM4_ADC2 ((FM4_ADC_TypeDef *)FM4_ADC2_BASE) -#define FM4_DAC0 ((FM4_DAC_TypeDef *)FM4_DAC0_BASE) -#define FM4_DAC1 ((FM4_DAC_TypeDef *)FM4_DAC1_BASE) -#define FM4_CRTRIM ((FM4_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) -#define FM4_EXTI ((FM4_EXTI_TypeDef *)FM4_EXTI_BASE) -#define FM4_INTREQ ((FM4_INTREQ_TypeDef *)FM4_INTREQ_BASE) -#define FM4_IRQSEL ((FM4_IRQSEL_TypeDef *)FM4_IRQSEL_BASE) -#define FM4_GPIO ((FM4_GPIO_TypeDef *)FM4_GPIO_BASE) -#define FM4_LVD ((FM4_LVD_TypeDef *)FM4_LVD_BASE) -#define FM4_DS ((FM4_DS_TypeDef *)FM4_DS_BASE) -#define FM4_USBCLK ((FM4_USBCLK_TypeDef *)FM4_USBCLK_BASE) -#define FM4_CANPRES ((FM4_CANPRE_TypeDef *)FM4_CANPRES_BASE) -#define FM4_MFS0 ((FM4_MFS_TypeDef *)FM4_MFS0_BASE) -#define FM4_MFS1 ((FM4_MFS_TypeDef *)FM4_MFS1_BASE) -#define FM4_MFS2 ((FM4_MFS_TypeDef *)FM4_MFS2_BASE) -#define FM4_MFS3 ((FM4_MFS_TypeDef *)FM4_MFS3_BASE) -#define FM4_MFS4 ((FM4_MFS_TypeDef *)FM4_MFS4_BASE) -#define FM4_MFS5 ((FM4_MFS_TypeDef *)FM4_MFS5_BASE) -#define FM4_MFS6 ((FM4_MFS_TypeDef *)FM4_MFS6_BASE) -#define FM4_MFS7 ((FM4_MFS_TypeDef *)FM4_MFS7_BASE) -#define FM4_MFS8 ((FM4_MFS_TypeDef *)FM4_MFS8_BASE) -#define FM4_MFS9 ((FM4_MFS_TypeDef *)FM4_MFS9_BASE) -#define FM4_MFS10 ((FM4_MFS_TypeDef *)FM4_MFS10_BASE) -#define FM4_MFS11 ((FM4_MFS_TypeDef *)FM4_MFS11_BASE) -#define FM4_MFS12 ((FM4_MFS_TypeDef *)FM4_MFS12_BASE) -#define FM4_MFS13 ((FM4_MFS_TypeDef *)FM4_MFS13_BASE) -#define FM4_MFS14 ((FM4_MFS_TypeDef *)FM4_MFS14_BASE) -#define FM4_MFS15 ((FM4_MFS_TypeDef *)FM4_MFS15_BASE) -#define FM4_CRC ((FM4_CRC_TypeDef *)FM4_CRC_BASE) -#define FM4_WC ((FM4_WC_TypeDef *)FM4_WC_BASE) -#define FM4_RTC ((FM4_RTC_TypeDef *)FM4_RTC_BASE) -#define FM4_LCR ((FM4_LCR_TypeDef *)FM4_LCR_BASE) -#define FM4_CLK_GATING ((FM4_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) -#define FM4_PLL_CONTROL ((FM4_PLL_CONTROL_TypeDef *)FM4_PLL_CONTROL_BASE) -#define FM4_EXBUS ((FM4_EXBUS_TypeDef *)FM4_EXBUS_BASE) -#define FM4_USB0 ((FM4_USB_TypeDef *)FM4_USB0_BASE) -#define FM4_DMAC ((FM4_DMAC_TypeDef *)FM4_DMAC_BASE) -#define FM4_DSTC ((FM4_DSTC_TypeDef *)FM4_DSTC_BASE) -#define FM4_CAN0 ((FM4_CAN_TypeDef *)FM4_CAN0_BASE) -#define FM4_CAN1 ((FM4_CAN_TypeDef *)FM4_CAN1_BASE) -#define FM4_SDIF ((FM4_SDIF_TypeDef *)FM4_SDIF_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Work Flash interface registers */ -#define bFM4_WORKFLASH_IF_WFASZR_ASZ *((volatile unsigned int*)(0x23C00000UL)) -#define bFM4_WORKFLASH_IF_WFRWTR_RWT0 *((volatile unsigned int*)(0x23C00080UL)) -#define bFM4_WORKFLASH_IF_WFRWTR_RWT1 *((volatile unsigned int*)(0x23C00084UL)) -#define bFM4_WORKFLASH_IF_WFRWTR_RWT2 *((volatile unsigned int*)(0x23C00088UL)) -#define bFM4_WORKFLASH_IF_WFSTR_RDY *((volatile unsigned int*)(0x23C00100UL)) -#define bFM4_WORKFLASH_IF_WFSTR_HNG *((volatile unsigned int*)(0x23C00104UL)) - -/* Flash interface registers */ -#define bFM4_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM4_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM4_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM4_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM4_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM4_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM4_FLASH_IF_FSTR_ERR *((volatile unsigned int*)(0x42000108UL)) -#define bFM4_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM4_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM4_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM4_FLASH_IF_FBFCR_BE *((volatile unsigned int*)(0x42000280UL)) -#define bFM4_FLASH_IF_FBFCR_BS *((volatile unsigned int*)(0x42000284UL)) -#define bFM4_FLASH_IF_FICR_RDYIE *((volatile unsigned int*)(0x42000400UL)) -#define bFM4_FLASH_IF_FICR_HANGIE *((volatile unsigned int*)(0x42000404UL)) -#define bFM4_FLASH_IF_FICR_ERRIE *((volatile unsigned int*)(0x42000408UL)) -#define bFM4_FLASH_IF_FISR_RDYIF *((volatile unsigned int*)(0x42000480UL)) -#define bFM4_FLASH_IF_FISR_HANGIF *((volatile unsigned int*)(0x42000484UL)) -#define bFM4_FLASH_IF_FISR_ERRIF *((volatile unsigned int*)(0x42000488UL)) -#define bFM4_FLASH_IF_FICLR_RDYIC *((volatile unsigned int*)(0x42000500UL)) -#define bFM4_FLASH_IF_FICLR_HANGIC *((volatile unsigned int*)(0x42000504UL)) -#define bFM4_FLASH_IF_FICLR_ERRIC *((volatile unsigned int*)(0x42000508UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM4_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) -#define bFM4_FLASH_IF_CRTRMM_TTRMM0 *((volatile unsigned int*)(0x42002040UL)) -#define bFM4_FLASH_IF_CRTRMM_TTRMM1 *((volatile unsigned int*)(0x42002044UL)) -#define bFM4_FLASH_IF_CRTRMM_TTRMM2 *((volatile unsigned int*)(0x42002048UL)) -#define bFM4_FLASH_IF_CRTRMM_TTRMM3 *((volatile unsigned int*)(0x4200204CUL)) -#define bFM4_FLASH_IF_CRTRMM_TTRMM4 *((volatile unsigned int*)(0x42002050UL)) - -/* Unique ID registers */ -#define bFM4_UNIQUE_ID_UIDR0_UID0 *((volatile unsigned int*)(0x42004010UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID1 *((volatile unsigned int*)(0x42004014UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID2 *((volatile unsigned int*)(0x42004018UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID3 *((volatile unsigned int*)(0x4200401CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID4 *((volatile unsigned int*)(0x42004020UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID5 *((volatile unsigned int*)(0x42004024UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID6 *((volatile unsigned int*)(0x42004028UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID7 *((volatile unsigned int*)(0x4200402CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID8 *((volatile unsigned int*)(0x42004030UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID9 *((volatile unsigned int*)(0x42004034UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID10 *((volatile unsigned int*)(0x42004038UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID11 *((volatile unsigned int*)(0x4200403CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID12 *((volatile unsigned int*)(0x42004040UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID13 *((volatile unsigned int*)(0x42004044UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID14 *((volatile unsigned int*)(0x42004048UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID15 *((volatile unsigned int*)(0x4200404CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID16 *((volatile unsigned int*)(0x42004050UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID17 *((volatile unsigned int*)(0x42004054UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID18 *((volatile unsigned int*)(0x42004058UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID19 *((volatile unsigned int*)(0x4200405CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID20 *((volatile unsigned int*)(0x42004060UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID21 *((volatile unsigned int*)(0x42004064UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID22 *((volatile unsigned int*)(0x42004068UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID23 *((volatile unsigned int*)(0x4200406CUL)) -#define bFM4_UNIQUE_ID_UIDR0_UID24 *((volatile unsigned int*)(0x42004070UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID25 *((volatile unsigned int*)(0x42004074UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID26 *((volatile unsigned int*)(0x42004078UL)) -#define bFM4_UNIQUE_ID_UIDR0_UID27 *((volatile unsigned int*)(0x4200407CUL)) -#define bFM4_UNIQUE_ID_UIDR1_UID28 *((volatile unsigned int*)(0x42004080UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID29 *((volatile unsigned int*)(0x42004084UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID30 *((volatile unsigned int*)(0x42004088UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID31 *((volatile unsigned int*)(0x4200408CUL)) -#define bFM4_UNIQUE_ID_UIDR1_UID32 *((volatile unsigned int*)(0x42004090UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID33 *((volatile unsigned int*)(0x42004094UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID34 *((volatile unsigned int*)(0x42004098UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID35 *((volatile unsigned int*)(0x4200409CUL)) -#define bFM4_UNIQUE_ID_UIDR1_UID36 *((volatile unsigned int*)(0x420040A0UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID37 *((volatile unsigned int*)(0x420040A4UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID38 *((volatile unsigned int*)(0x420040A8UL)) -#define bFM4_UNIQUE_ID_UIDR1_UID39 *((volatile unsigned int*)(0x420040ACUL)) -#define bFM4_UNIQUE_ID_UIDR1_UID40 *((volatile unsigned int*)(0x420040B0UL)) - -/* ECC_CAPTURE registers */ -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD0 *((volatile unsigned int*)(0x42006000UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD1 *((volatile unsigned int*)(0x42006004UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD2 *((volatile unsigned int*)(0x42006008UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD3 *((volatile unsigned int*)(0x4200600CUL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD4 *((volatile unsigned int*)(0x42006010UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD5 *((volatile unsigned int*)(0x42006014UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD6 *((volatile unsigned int*)(0x42006018UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD7 *((volatile unsigned int*)(0x4200601CUL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD8 *((volatile unsigned int*)(0x42006020UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD9 *((volatile unsigned int*)(0x42006024UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD10 *((volatile unsigned int*)(0x42006028UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD11 *((volatile unsigned int*)(0x4200602CUL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD12 *((volatile unsigned int*)(0x42006030UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD13 *((volatile unsigned int*)(0x42006034UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD14 *((volatile unsigned int*)(0x42006038UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD15 *((volatile unsigned int*)(0x4200603CUL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD16 *((volatile unsigned int*)(0x42006040UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD17 *((volatile unsigned int*)(0x42006044UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD18 *((volatile unsigned int*)(0x42006048UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD19 *((volatile unsigned int*)(0x4200604CUL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD20 *((volatile unsigned int*)(0x42006050UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD21 *((volatile unsigned int*)(0x42006054UL)) -#define bFM4_ECC_CAPTURE_FERRAD_ERRAD22 *((volatile unsigned int*)(0x42006058UL)) - -/* Clock and reset registers */ -#define bFM4_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM4_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM4_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM4_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM4_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM4_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM4_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM4_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM4_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM4_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM4_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM4_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM4_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM4_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM4_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM4_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM4_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM4_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM4_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM4_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM4_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM4_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM4_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM4_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM4_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM4_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM4_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM4_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM4_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM4_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM4_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM4_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM4_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM4_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM4_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM4_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) -#define bFM4_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) -#define bFM4_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM4_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM4_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM4_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM4_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM4_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM4_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM4_CRG_CSW_TMR_SOWT3 *((volatile unsigned int*)(0x4220061CUL)) -#define bFM4_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM4_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM4_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM4_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM4_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM4_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM4_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM4_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM4_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM4_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM4_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM4_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM4_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM4_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM4_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM4_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM4_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM4_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) -#define bFM4_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM4_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM4_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM4_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM4_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM4_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM4_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM4_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM4_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM4_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM4_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM4_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM4_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM4_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM4_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM4_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM4_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM4_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM4_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM4_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM4_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM4_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM4_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM4_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM4_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM4_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM4_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM4_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM4_SWWDT_WDOGCONTROL_TWD0 *((volatile unsigned int*)(0x42240108UL)) -#define bFM4_SWWDT_WDOGCONTROL_TWD1 *((volatile unsigned int*)(0x4224010CUL)) -#define bFM4_SWWDT_WDOGCONTROL_SPM *((volatile unsigned int*)(0x42240110UL)) -#define bFM4_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) -#define bFM4_SWWDT_WDOGSPMC_TGR *((volatile unsigned int*)(0x42240300UL)) - -/* Dual timer 1/2 registers */ -#define bFM4_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM4_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM4_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM4_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM4_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM4_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM4_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM4_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM4_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM4_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM4_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM4_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM4_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM4_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM4_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM4_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM4_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM4_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM4_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42402900UL)) -#define bFM4_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42402904UL)) -#define bFM4_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42402908UL)) -#define bFM4_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240290cUL)) -#define bFM4_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42402910UL)) -#define bFM4_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42402914UL)) -#define bFM4_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42402918UL)) -#define bFM4_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240291cUL)) -#define bFM4_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42402920UL)) -#define bFM4_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42402924UL)) -#define bFM4_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42402934UL)) -#define bFM4_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42402938UL)) -#define bFM4_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240293cUL)) -#define bFM4_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42402a80UL)) -#define bFM4_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42402a84UL)) -#define bFM4_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42402a88UL)) -#define bFM4_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42402a8cUL)) -#define bFM4_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42402a90UL)) -#define bFM4_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42402a94UL)) -#define bFM4_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42402a98UL)) -#define bFM4_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42402a9cUL)) -#define bFM4_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42402aa0UL)) -#define bFM4_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42402aa4UL)) -#define bFM4_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42402ab4UL)) -#define bFM4_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42402ab8UL)) -#define bFM4_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42402abcUL)) -#define bFM4_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42402c00UL)) -#define bFM4_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42402c04UL)) -#define bFM4_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42402c08UL)) -#define bFM4_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42402c0cUL)) -#define bFM4_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42402c10UL)) -#define bFM4_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42402c14UL)) -#define bFM4_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42402c18UL)) -#define bFM4_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42402c1cUL)) -#define bFM4_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42402c20UL)) -#define bFM4_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42402c24UL)) -#define bFM4_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42402c34UL)) -#define bFM4_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42402c38UL)) -#define bFM4_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42402c3cUL)) -#define bFM4_MFT0_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42402c80UL)) -#define bFM4_MFT0_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42402c84UL)) -#define bFM4_MFT0_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42402c88UL)) -#define bFM4_MFT0_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42402c8cUL)) -#define bFM4_MFT0_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42402c90UL)) -#define bFM4_MFT0_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42402c94UL)) -#define bFM4_MFT0_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42402c98UL)) -#define bFM4_MFT0_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42402c9cUL)) -#define bFM4_MFT0_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42402ca0UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42402cc0UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42402cc4UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42402cc8UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42402cccUL)) -#define bFM4_MFT0_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42402cd0UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42402cd4UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42402cd8UL)) -#define bFM4_MFT0_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42402cdcUL)) -#define bFM4_MFT0_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42402ce0UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM4_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42402300UL)) -#define bFM4_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42402304UL)) -#define bFM4_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42402310UL)) -#define bFM4_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42402314UL)) -#define bFM4_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42402318UL)) -#define bFM4_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240231cUL)) -#define bFM4_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42402320UL)) -#define bFM4_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42402324UL)) -#define bFM4_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42402330UL)) -#define bFM4_MFT0_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4240233cUL)) -#define bFM4_MFT0_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42402380UL)) -#define bFM4_MFT0_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42402384UL)) -#define bFM4_MFT0_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42402390UL)) -#define bFM4_MFT0_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42402394UL)) -#define bFM4_MFT0_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42402398UL)) -#define bFM4_MFT0_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4240239cUL)) -#define bFM4_MFT0_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424023a0UL)) -#define bFM4_MFT0_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424023a4UL)) -#define bFM4_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424023b0UL)) -#define bFM4_MFT0_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424023bcUL)) -#define bFM4_MFT0_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42402400UL)) -#define bFM4_MFT0_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42402404UL)) -#define bFM4_MFT0_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42402410UL)) -#define bFM4_MFT0_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42402414UL)) -#define bFM4_MFT0_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42402418UL)) -#define bFM4_MFT0_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4240241cUL)) -#define bFM4_MFT0_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42402420UL)) -#define bFM4_MFT0_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42402424UL)) -#define bFM4_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42402430UL)) -#define bFM4_MFT0_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4240243cUL)) -#define bFM4_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424024a0UL)) -#define bFM4_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424024a4UL)) -#define bFM4_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424024a8UL)) -#define bFM4_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424024acUL)) -#define bFM4_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424024b0UL)) -#define bFM4_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424024b4UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42402d00UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42402d04UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42402d08UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42402d0cUL)) -#define bFM4_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42402d10UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42402d14UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42402d18UL)) -#define bFM4_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42402d1cUL)) -#define bFM4_MFT0_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42402d20UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42402d24UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42402d28UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42402d2cUL)) -#define bFM4_MFT0_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42402d30UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42402d34UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42402d38UL)) -#define bFM4_MFT0_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42402d3cUL)) -#define bFM4_MFT0_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42402d40UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42402d44UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42402d48UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42402d4cUL)) -#define bFM4_MFT0_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42402d50UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42402d54UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42402d58UL)) -#define bFM4_MFT0_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42402d5cUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM4_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42403480UL)) -#define bFM4_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42403484UL)) -#define bFM4_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42403488UL)) -#define bFM4_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42403498UL)) -#define bFM4_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240349cUL)) -#define bFM4_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424034a0UL)) -#define bFM4_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424034a4UL)) -#define bFM4_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424034a8UL)) -#define bFM4_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424034acUL)) -#define bFM4_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42403500UL)) -#define bFM4_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42403504UL)) -#define bFM4_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42403508UL)) -#define bFM4_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42403518UL)) -#define bFM4_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240351cUL)) -#define bFM4_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42403520UL)) -#define bFM4_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42403524UL)) -#define bFM4_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42403528UL)) -#define bFM4_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240352cUL)) -#define bFM4_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42403580UL)) -#define bFM4_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42403584UL)) -#define bFM4_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42403588UL)) -#define bFM4_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42403598UL)) -#define bFM4_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240359cUL)) -#define bFM4_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424035a0UL)) -#define bFM4_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424035a4UL)) -#define bFM4_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424035a8UL)) -#define bFM4_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424035acUL)) -#define bFM4_MFT0_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42403600UL)) -#define bFM4_MFT0_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42403604UL)) -#define bFM4_MFT0_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42403608UL)) -#define bFM4_MFT0_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4240360cUL)) -#define bFM4_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42403610UL)) -#define bFM4_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42403614UL)) -#define bFM4_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42403618UL)) -#define bFM4_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240361cUL)) -#define bFM4_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42403620UL)) -#define bFM4_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42403624UL)) -#define bFM4_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42403628UL)) -#define bFM4_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240362cUL)) -#define bFM4_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42403630UL)) -#define bFM4_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42403634UL)) -#define bFM4_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42403638UL)) -#define bFM4_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240363cUL)) -#define bFM4_MFT0_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42403680UL)) -#define bFM4_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42403684UL)) -#define bFM4_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42403688UL)) -#define bFM4_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240368cUL)) -#define bFM4_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42403690UL)) -#define bFM4_MFT0_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42403694UL)) -#define bFM4_MFT0_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424036a0UL)) -#define bFM4_MFT0_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424036a4UL)) -#define bFM4_MFT0_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424036b0UL)) -#define bFM4_MFT0_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424036b4UL)) -#define bFM4_MFT0_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424036b8UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM4_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42402d80UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42402d84UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42402d88UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42402d8cUL)) -#define bFM4_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42402d90UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42402d94UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42402d98UL)) -#define bFM4_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42402d9cUL)) -#define bFM4_MFT0_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42402da0UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42402da4UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42402da8UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42402dacUL)) -#define bFM4_MFT0_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42402db0UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42402db4UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42402db8UL)) -#define bFM4_MFT0_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42402dbcUL)) -#define bFM4_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42403080UL)) -#define bFM4_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42403084UL)) -#define bFM4_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42403088UL)) -#define bFM4_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4240308cUL)) -#define bFM4_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42403090UL)) -#define bFM4_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42403094UL)) -#define bFM4_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42403098UL)) -#define bFM4_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4240309cUL)) -#define bFM4_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424030a0UL)) -#define bFM4_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424030a4UL)) -#define bFM4_MFT0_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42403100UL)) -#define bFM4_MFT0_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42403104UL)) -#define bFM4_MFT0_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42403108UL)) -#define bFM4_MFT0_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4240310cUL)) -#define bFM4_MFT0_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42403110UL)) -#define bFM4_MFT0_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42403114UL)) -#define bFM4_MFT0_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42403118UL)) -#define bFM4_MFT0_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4240311cUL)) -#define bFM4_MFT0_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42403120UL)) -#define bFM4_MFT0_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42403124UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM4_MFT0_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42403aa0UL)) -#define bFM4_MFT0_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42403aa4UL)) -#define bFM4_MFT0_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42403ab0UL)) -#define bFM4_MFT0_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42403ab4UL)) -#define bFM4_MFT0_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42403ab8UL)) -#define bFM4_MFT0_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42403abcUL)) -#define bFM4_MFT0_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42403b20UL)) -#define bFM4_MFT0_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42403b24UL)) -#define bFM4_MFT0_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42403b30UL)) -#define bFM4_MFT0_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42403b34UL)) -#define bFM4_MFT0_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42403b38UL)) -#define bFM4_MFT0_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42403b3cUL)) -#define bFM4_MFT0_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42403ba0UL)) -#define bFM4_MFT0_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42403ba4UL)) -#define bFM4_MFT0_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42403bb0UL)) -#define bFM4_MFT0_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42403bb4UL)) -#define bFM4_MFT0_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42403bb8UL)) -#define bFM4_MFT0_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42403bbcUL)) -#define bFM4_MFT0_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42403c20UL)) -#define bFM4_MFT0_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42403c24UL)) -#define bFM4_MFT0_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42403c30UL)) -#define bFM4_MFT0_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42403c34UL)) -#define bFM4_MFT0_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42403c38UL)) -#define bFM4_MFT0_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42403c3cUL)) -#define bFM4_MFT0_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42403ca0UL)) -#define bFM4_MFT0_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42403ca4UL)) -#define bFM4_MFT0_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42403cb0UL)) -#define bFM4_MFT0_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42403cb4UL)) -#define bFM4_MFT0_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42403cb8UL)) -#define bFM4_MFT0_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42403cbcUL)) -#define bFM4_MFT0_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42403d20UL)) -#define bFM4_MFT0_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42403d24UL)) -#define bFM4_MFT0_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42403d30UL)) -#define bFM4_MFT0_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42403d34UL)) -#define bFM4_MFT0_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42403d38UL)) -#define bFM4_MFT0_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42403d3cUL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM4_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42422900UL)) -#define bFM4_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42422904UL)) -#define bFM4_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42422908UL)) -#define bFM4_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242290cUL)) -#define bFM4_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42422910UL)) -#define bFM4_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42422914UL)) -#define bFM4_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42422918UL)) -#define bFM4_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242291cUL)) -#define bFM4_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42422920UL)) -#define bFM4_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42422924UL)) -#define bFM4_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42422934UL)) -#define bFM4_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42422938UL)) -#define bFM4_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242293cUL)) -#define bFM4_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42422a80UL)) -#define bFM4_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42422a84UL)) -#define bFM4_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42422a88UL)) -#define bFM4_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42422a8cUL)) -#define bFM4_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42422a90UL)) -#define bFM4_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42422a94UL)) -#define bFM4_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42422a98UL)) -#define bFM4_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42422a9cUL)) -#define bFM4_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42422aa0UL)) -#define bFM4_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42422aa4UL)) -#define bFM4_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42422ab4UL)) -#define bFM4_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42422ab8UL)) -#define bFM4_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42422abcUL)) -#define bFM4_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42422c00UL)) -#define bFM4_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42422c04UL)) -#define bFM4_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42422c08UL)) -#define bFM4_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42422c0cUL)) -#define bFM4_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42422c10UL)) -#define bFM4_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42422c14UL)) -#define bFM4_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42422c18UL)) -#define bFM4_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42422c1cUL)) -#define bFM4_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42422c20UL)) -#define bFM4_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42422c24UL)) -#define bFM4_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42422c34UL)) -#define bFM4_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42422c38UL)) -#define bFM4_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42422c3cUL)) -#define bFM4_MFT1_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42422c80UL)) -#define bFM4_MFT1_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42422c84UL)) -#define bFM4_MFT1_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42422c88UL)) -#define bFM4_MFT1_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42422c8cUL)) -#define bFM4_MFT1_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42422c90UL)) -#define bFM4_MFT1_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42422c94UL)) -#define bFM4_MFT1_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42422c98UL)) -#define bFM4_MFT1_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42422c9cUL)) -#define bFM4_MFT1_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42422ca0UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42422cc0UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42422cc4UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42422cc8UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42422cccUL)) -#define bFM4_MFT1_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42422cd0UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42422cd4UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42422cd8UL)) -#define bFM4_MFT1_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42422cdcUL)) -#define bFM4_MFT1_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42422ce0UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM4_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42422300UL)) -#define bFM4_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42422304UL)) -#define bFM4_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42422310UL)) -#define bFM4_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42422314UL)) -#define bFM4_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42422318UL)) -#define bFM4_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242231cUL)) -#define bFM4_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42422320UL)) -#define bFM4_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42422324UL)) -#define bFM4_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42422330UL)) -#define bFM4_MFT1_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4242233cUL)) -#define bFM4_MFT1_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42422380UL)) -#define bFM4_MFT1_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42422384UL)) -#define bFM4_MFT1_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42422390UL)) -#define bFM4_MFT1_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42422394UL)) -#define bFM4_MFT1_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42422398UL)) -#define bFM4_MFT1_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4242239cUL)) -#define bFM4_MFT1_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424223a0UL)) -#define bFM4_MFT1_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424223a4UL)) -#define bFM4_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424223b0UL)) -#define bFM4_MFT1_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424223bcUL)) -#define bFM4_MFT1_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42422400UL)) -#define bFM4_MFT1_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42422404UL)) -#define bFM4_MFT1_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42422410UL)) -#define bFM4_MFT1_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42422414UL)) -#define bFM4_MFT1_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42422418UL)) -#define bFM4_MFT1_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4242241cUL)) -#define bFM4_MFT1_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42422420UL)) -#define bFM4_MFT1_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42422424UL)) -#define bFM4_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42422430UL)) -#define bFM4_MFT1_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4242243cUL)) -#define bFM4_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424224a0UL)) -#define bFM4_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424224a4UL)) -#define bFM4_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424224a8UL)) -#define bFM4_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424224acUL)) -#define bFM4_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424224b0UL)) -#define bFM4_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424224b4UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42422d00UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42422d04UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42422d08UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42422d0cUL)) -#define bFM4_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42422d10UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42422d14UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42422d18UL)) -#define bFM4_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42422d1cUL)) -#define bFM4_MFT1_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42422d20UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42422d24UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42422d28UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42422d2cUL)) -#define bFM4_MFT1_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42422d30UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42422d34UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42422d38UL)) -#define bFM4_MFT1_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42422d3cUL)) -#define bFM4_MFT1_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42422d40UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42422d44UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42422d48UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42422d4cUL)) -#define bFM4_MFT1_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42422d50UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42422d54UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42422d58UL)) -#define bFM4_MFT1_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42422d5cUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM4_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42423480UL)) -#define bFM4_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42423484UL)) -#define bFM4_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42423488UL)) -#define bFM4_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42423498UL)) -#define bFM4_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242349cUL)) -#define bFM4_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424234a0UL)) -#define bFM4_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424234a4UL)) -#define bFM4_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424234a8UL)) -#define bFM4_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424234acUL)) -#define bFM4_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42423500UL)) -#define bFM4_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42423504UL)) -#define bFM4_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42423508UL)) -#define bFM4_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42423518UL)) -#define bFM4_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242351cUL)) -#define bFM4_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42423520UL)) -#define bFM4_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42423524UL)) -#define bFM4_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42423528UL)) -#define bFM4_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242352cUL)) -#define bFM4_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42423580UL)) -#define bFM4_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42423584UL)) -#define bFM4_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42423588UL)) -#define bFM4_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42423598UL)) -#define bFM4_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242359cUL)) -#define bFM4_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424235a0UL)) -#define bFM4_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424235a4UL)) -#define bFM4_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424235a8UL)) -#define bFM4_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424235acUL)) -#define bFM4_MFT1_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42423600UL)) -#define bFM4_MFT1_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42423604UL)) -#define bFM4_MFT1_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42423608UL)) -#define bFM4_MFT1_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4242360cUL)) -#define bFM4_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42423610UL)) -#define bFM4_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42423614UL)) -#define bFM4_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42423618UL)) -#define bFM4_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242361cUL)) -#define bFM4_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42423620UL)) -#define bFM4_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42423624UL)) -#define bFM4_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42423628UL)) -#define bFM4_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242362cUL)) -#define bFM4_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42423630UL)) -#define bFM4_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42423634UL)) -#define bFM4_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42423638UL)) -#define bFM4_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242363cUL)) -#define bFM4_MFT1_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42423680UL)) -#define bFM4_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42423684UL)) -#define bFM4_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42423688UL)) -#define bFM4_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242368cUL)) -#define bFM4_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42423690UL)) -#define bFM4_MFT1_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42423694UL)) -#define bFM4_MFT1_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424236a0UL)) -#define bFM4_MFT1_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424236a4UL)) -#define bFM4_MFT1_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424236b0UL)) -#define bFM4_MFT1_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424236b4UL)) -#define bFM4_MFT1_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424236b8UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM4_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42422d80UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42422d84UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42422d88UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42422d8cUL)) -#define bFM4_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42422d90UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42422d94UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42422d98UL)) -#define bFM4_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42422d9cUL)) -#define bFM4_MFT1_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42422da0UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42422da4UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42422da8UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42422dacUL)) -#define bFM4_MFT1_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42422db0UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42422db4UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42422db8UL)) -#define bFM4_MFT1_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42422dbcUL)) -#define bFM4_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42423080UL)) -#define bFM4_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42423084UL)) -#define bFM4_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42423088UL)) -#define bFM4_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4242308cUL)) -#define bFM4_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42423090UL)) -#define bFM4_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42423094UL)) -#define bFM4_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42423098UL)) -#define bFM4_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4242309cUL)) -#define bFM4_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424230a0UL)) -#define bFM4_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424230a4UL)) -#define bFM4_MFT1_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42423100UL)) -#define bFM4_MFT1_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42423104UL)) -#define bFM4_MFT1_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42423108UL)) -#define bFM4_MFT1_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4242310cUL)) -#define bFM4_MFT1_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42423110UL)) -#define bFM4_MFT1_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42423114UL)) -#define bFM4_MFT1_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42423118UL)) -#define bFM4_MFT1_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4242311cUL)) -#define bFM4_MFT1_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42423120UL)) -#define bFM4_MFT1_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42423124UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM4_MFT1_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42423aa0UL)) -#define bFM4_MFT1_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42423aa4UL)) -#define bFM4_MFT1_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42423ab0UL)) -#define bFM4_MFT1_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42423ab4UL)) -#define bFM4_MFT1_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42423ab8UL)) -#define bFM4_MFT1_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42423abcUL)) -#define bFM4_MFT1_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42423b20UL)) -#define bFM4_MFT1_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42423b24UL)) -#define bFM4_MFT1_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42423b30UL)) -#define bFM4_MFT1_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42423b34UL)) -#define bFM4_MFT1_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42423b38UL)) -#define bFM4_MFT1_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42423b3cUL)) -#define bFM4_MFT1_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42423ba0UL)) -#define bFM4_MFT1_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42423ba4UL)) -#define bFM4_MFT1_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42423bb0UL)) -#define bFM4_MFT1_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42423bb4UL)) -#define bFM4_MFT1_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42423bb8UL)) -#define bFM4_MFT1_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42423bbcUL)) -#define bFM4_MFT1_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42423c20UL)) -#define bFM4_MFT1_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42423c24UL)) -#define bFM4_MFT1_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42423c30UL)) -#define bFM4_MFT1_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42423c34UL)) -#define bFM4_MFT1_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42423c38UL)) -#define bFM4_MFT1_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42423c3cUL)) -#define bFM4_MFT1_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42423ca0UL)) -#define bFM4_MFT1_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42423ca4UL)) -#define bFM4_MFT1_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42423cb0UL)) -#define bFM4_MFT1_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42423cb4UL)) -#define bFM4_MFT1_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42423cb8UL)) -#define bFM4_MFT1_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42423cbcUL)) -#define bFM4_MFT1_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42423d20UL)) -#define bFM4_MFT1_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42423d24UL)) -#define bFM4_MFT1_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42423d30UL)) -#define bFM4_MFT1_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42423d34UL)) -#define bFM4_MFT1_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42423d38UL)) -#define bFM4_MFT1_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42423d3cUL)) - -/* Multifunction Timer unit 2 Free Running Timer registers */ -#define bFM4_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42442900UL)) -#define bFM4_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42442904UL)) -#define bFM4_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42442908UL)) -#define bFM4_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244290cUL)) -#define bFM4_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42442910UL)) -#define bFM4_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42442914UL)) -#define bFM4_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42442918UL)) -#define bFM4_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244291cUL)) -#define bFM4_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42442920UL)) -#define bFM4_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42442924UL)) -#define bFM4_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42442934UL)) -#define bFM4_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42442938UL)) -#define bFM4_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244293cUL)) -#define bFM4_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42442a80UL)) -#define bFM4_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42442a84UL)) -#define bFM4_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42442a88UL)) -#define bFM4_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x42442a8cUL)) -#define bFM4_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42442a90UL)) -#define bFM4_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42442a94UL)) -#define bFM4_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42442a98UL)) -#define bFM4_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x42442a9cUL)) -#define bFM4_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42442aa0UL)) -#define bFM4_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42442aa4UL)) -#define bFM4_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42442ab4UL)) -#define bFM4_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42442ab8UL)) -#define bFM4_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x42442abcUL)) -#define bFM4_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42442c00UL)) -#define bFM4_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42442c04UL)) -#define bFM4_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42442c08UL)) -#define bFM4_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42442c0cUL)) -#define bFM4_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42442c10UL)) -#define bFM4_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42442c14UL)) -#define bFM4_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42442c18UL)) -#define bFM4_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42442c1cUL)) -#define bFM4_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42442c20UL)) -#define bFM4_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42442c24UL)) -#define bFM4_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42442c34UL)) -#define bFM4_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42442c38UL)) -#define bFM4_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42442c3cUL)) -#define bFM4_MFT2_FRT_TCAL_STOP00 *((volatile unsigned int*)(0x42442c80UL)) -#define bFM4_MFT2_FRT_TCAL_STOP01 *((volatile unsigned int*)(0x42442c84UL)) -#define bFM4_MFT2_FRT_TCAL_STOP02 *((volatile unsigned int*)(0x42442c88UL)) -#define bFM4_MFT2_FRT_TCAL_STOP10 *((volatile unsigned int*)(0x42442c8cUL)) -#define bFM4_MFT2_FRT_TCAL_STOP11 *((volatile unsigned int*)(0x42442c90UL)) -#define bFM4_MFT2_FRT_TCAL_STOP12 *((volatile unsigned int*)(0x42442c94UL)) -#define bFM4_MFT2_FRT_TCAL_STOP20 *((volatile unsigned int*)(0x42442c98UL)) -#define bFM4_MFT2_FRT_TCAL_STOP21 *((volatile unsigned int*)(0x42442c9cUL)) -#define bFM4_MFT2_FRT_TCAL_STOP22 *((volatile unsigned int*)(0x42442ca0UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR00 *((volatile unsigned int*)(0x42442cc0UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR01 *((volatile unsigned int*)(0x42442cc4UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR02 *((volatile unsigned int*)(0x42442cc8UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR10 *((volatile unsigned int*)(0x42442cccUL)) -#define bFM4_MFT2_FRT_TCAL_SCLR11 *((volatile unsigned int*)(0x42442cd0UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR12 *((volatile unsigned int*)(0x42442cd4UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR20 *((volatile unsigned int*)(0x42442cd8UL)) -#define bFM4_MFT2_FRT_TCAL_SCLR21 *((volatile unsigned int*)(0x42442cdcUL)) -#define bFM4_MFT2_FRT_TCAL_SCLR22 *((volatile unsigned int*)(0x42442ce0UL)) - -/* Multifunction Timer unit 2 Output Compare Unit registers */ -#define bFM4_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42442300UL)) -#define bFM4_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42442304UL)) -#define bFM4_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42442310UL)) -#define bFM4_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42442314UL)) -#define bFM4_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42442318UL)) -#define bFM4_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244231cUL)) -#define bFM4_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42442320UL)) -#define bFM4_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42442324UL)) -#define bFM4_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42442330UL)) -#define bFM4_MFT2_OCU_OCSB10_FM4 *((volatile unsigned int*)(0x4244233cUL)) -#define bFM4_MFT2_OCU_OCSA32_CST0 *((volatile unsigned int*)(0x42442380UL)) -#define bFM4_MFT2_OCU_OCSA32_CST1 *((volatile unsigned int*)(0x42442384UL)) -#define bFM4_MFT2_OCU_OCSA32_IOE0 *((volatile unsigned int*)(0x42442390UL)) -#define bFM4_MFT2_OCU_OCSA32_IOE1 *((volatile unsigned int*)(0x42442394UL)) -#define bFM4_MFT2_OCU_OCSA32_IOP0 *((volatile unsigned int*)(0x42442398UL)) -#define bFM4_MFT2_OCU_OCSA32_IOP1 *((volatile unsigned int*)(0x4244239cUL)) -#define bFM4_MFT2_OCU_OCSB32_OTD0 *((volatile unsigned int*)(0x424423a0UL)) -#define bFM4_MFT2_OCU_OCSB32_OTD1 *((volatile unsigned int*)(0x424423a4UL)) -#define bFM4_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424423b0UL)) -#define bFM4_MFT2_OCU_OCSB32_FM4 *((volatile unsigned int*)(0x424423bcUL)) -#define bFM4_MFT2_OCU_OCSA54_CST0 *((volatile unsigned int*)(0x42442400UL)) -#define bFM4_MFT2_OCU_OCSA54_CST1 *((volatile unsigned int*)(0x42442404UL)) -#define bFM4_MFT2_OCU_OCSA54_IOE0 *((volatile unsigned int*)(0x42442410UL)) -#define bFM4_MFT2_OCU_OCSA54_IOE1 *((volatile unsigned int*)(0x42442414UL)) -#define bFM4_MFT2_OCU_OCSA54_IOP0 *((volatile unsigned int*)(0x42442418UL)) -#define bFM4_MFT2_OCU_OCSA54_IOP1 *((volatile unsigned int*)(0x4244241cUL)) -#define bFM4_MFT2_OCU_OCSB54_OTD0 *((volatile unsigned int*)(0x42442420UL)) -#define bFM4_MFT2_OCU_OCSB54_OTD1 *((volatile unsigned int*)(0x42442424UL)) -#define bFM4_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42442430UL)) -#define bFM4_MFT2_OCU_OCSB54_FM4 *((volatile unsigned int*)(0x4244243cUL)) -#define bFM4_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424424a0UL)) -#define bFM4_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424424a4UL)) -#define bFM4_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424424a8UL)) -#define bFM4_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424424acUL)) -#define bFM4_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424424b0UL)) -#define bFM4_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424424b4UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42442d00UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42442d04UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42442d08UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42442d0cUL)) -#define bFM4_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42442d10UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42442d14UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42442d18UL)) -#define bFM4_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42442d1cUL)) -#define bFM4_MFT2_OCU_OCFS32_FSO00 *((volatile unsigned int*)(0x42442d20UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO01 *((volatile unsigned int*)(0x42442d24UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO02 *((volatile unsigned int*)(0x42442d28UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO03 *((volatile unsigned int*)(0x42442d2cUL)) -#define bFM4_MFT2_OCU_OCFS32_FSO10 *((volatile unsigned int*)(0x42442d30UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO11 *((volatile unsigned int*)(0x42442d34UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO12 *((volatile unsigned int*)(0x42442d38UL)) -#define bFM4_MFT2_OCU_OCFS32_FSO13 *((volatile unsigned int*)(0x42442d3cUL)) -#define bFM4_MFT2_OCU_OCFS54_FSO00 *((volatile unsigned int*)(0x42442d40UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO01 *((volatile unsigned int*)(0x42442d44UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO02 *((volatile unsigned int*)(0x42442d48UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO03 *((volatile unsigned int*)(0x42442d4cUL)) -#define bFM4_MFT2_OCU_OCFS54_FSO10 *((volatile unsigned int*)(0x42442d50UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO11 *((volatile unsigned int*)(0x42442d54UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO12 *((volatile unsigned int*)(0x42442d58UL)) -#define bFM4_MFT2_OCU_OCFS54_FSO13 *((volatile unsigned int*)(0x42442d5cUL)) - -/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define bFM4_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42443480UL)) -#define bFM4_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42443484UL)) -#define bFM4_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42443488UL)) -#define bFM4_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42443498UL)) -#define bFM4_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244349cUL)) -#define bFM4_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424434a0UL)) -#define bFM4_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424434a4UL)) -#define bFM4_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424434a8UL)) -#define bFM4_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424434acUL)) -#define bFM4_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42443500UL)) -#define bFM4_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42443504UL)) -#define bFM4_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42443508UL)) -#define bFM4_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42443518UL)) -#define bFM4_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244351cUL)) -#define bFM4_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42443520UL)) -#define bFM4_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42443524UL)) -#define bFM4_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42443528UL)) -#define bFM4_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244352cUL)) -#define bFM4_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42443580UL)) -#define bFM4_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42443584UL)) -#define bFM4_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42443588UL)) -#define bFM4_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42443598UL)) -#define bFM4_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244359cUL)) -#define bFM4_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424435a0UL)) -#define bFM4_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424435a4UL)) -#define bFM4_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424435a8UL)) -#define bFM4_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424435acUL)) -#define bFM4_MFT2_WFG_WFIR_DTIFA *((volatile unsigned int*)(0x42443600UL)) -#define bFM4_MFT2_WFG_WFIR_DTICA *((volatile unsigned int*)(0x42443604UL)) -#define bFM4_MFT2_WFG_WFIR_DTIFB *((volatile unsigned int*)(0x42443608UL)) -#define bFM4_MFT2_WFG_WFIR_DTICB *((volatile unsigned int*)(0x4244360cUL)) -#define bFM4_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42443610UL)) -#define bFM4_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42443614UL)) -#define bFM4_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42443618UL)) -#define bFM4_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244361cUL)) -#define bFM4_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42443620UL)) -#define bFM4_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42443624UL)) -#define bFM4_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42443628UL)) -#define bFM4_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244362cUL)) -#define bFM4_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42443630UL)) -#define bFM4_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42443634UL)) -#define bFM4_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42443638UL)) -#define bFM4_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244363cUL)) -#define bFM4_MFT2_WFG_NZCL_DTIEA *((volatile unsigned int*)(0x42443680UL)) -#define bFM4_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42443684UL)) -#define bFM4_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42443688UL)) -#define bFM4_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244368cUL)) -#define bFM4_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42443690UL)) -#define bFM4_MFT2_WFG_NZCL_DTIEB *((volatile unsigned int*)(0x42443694UL)) -#define bFM4_MFT2_WFG_NZCL_DIMA *((volatile unsigned int*)(0x424436a0UL)) -#define bFM4_MFT2_WFG_NZCL_DIMB *((volatile unsigned int*)(0x424436a4UL)) -#define bFM4_MFT2_WFG_NZCL_WIM10 *((volatile unsigned int*)(0x424436b0UL)) -#define bFM4_MFT2_WFG_NZCL_WIM32 *((volatile unsigned int*)(0x424436b4UL)) -#define bFM4_MFT2_WFG_NZCL_WIM54 *((volatile unsigned int*)(0x424436b8UL)) - -/* Multifunction Timer unit 2 Input Capture Unit registers */ -#define bFM4_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42442d80UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42442d84UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42442d88UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42442d8cUL)) -#define bFM4_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42442d90UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42442d94UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42442d98UL)) -#define bFM4_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42442d9cUL)) -#define bFM4_MFT2_ICU_ICFS32_FSI00 *((volatile unsigned int*)(0x42442da0UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI01 *((volatile unsigned int*)(0x42442da4UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI02 *((volatile unsigned int*)(0x42442da8UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI03 *((volatile unsigned int*)(0x42442dacUL)) -#define bFM4_MFT2_ICU_ICFS32_FSI10 *((volatile unsigned int*)(0x42442db0UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI11 *((volatile unsigned int*)(0x42442db4UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI12 *((volatile unsigned int*)(0x42442db8UL)) -#define bFM4_MFT2_ICU_ICFS32_FSI13 *((volatile unsigned int*)(0x42442dbcUL)) -#define bFM4_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42443080UL)) -#define bFM4_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42443084UL)) -#define bFM4_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42443088UL)) -#define bFM4_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x4244308cUL)) -#define bFM4_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42443090UL)) -#define bFM4_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42443094UL)) -#define bFM4_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42443098UL)) -#define bFM4_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x4244309cUL)) -#define bFM4_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x424430a0UL)) -#define bFM4_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x424430a4UL)) -#define bFM4_MFT2_ICU_ICSA32_EG00 *((volatile unsigned int*)(0x42443100UL)) -#define bFM4_MFT2_ICU_ICSA32_EG01 *((volatile unsigned int*)(0x42443104UL)) -#define bFM4_MFT2_ICU_ICSA32_EG10 *((volatile unsigned int*)(0x42443108UL)) -#define bFM4_MFT2_ICU_ICSA32_EG11 *((volatile unsigned int*)(0x4244310cUL)) -#define bFM4_MFT2_ICU_ICSA32_ICE0 *((volatile unsigned int*)(0x42443110UL)) -#define bFM4_MFT2_ICU_ICSA32_ICE1 *((volatile unsigned int*)(0x42443114UL)) -#define bFM4_MFT2_ICU_ICSA32_ICP0 *((volatile unsigned int*)(0x42443118UL)) -#define bFM4_MFT2_ICU_ICSA32_ICP1 *((volatile unsigned int*)(0x4244311cUL)) -#define bFM4_MFT2_ICU_ICSB32_IEI0 *((volatile unsigned int*)(0x42443120UL)) -#define bFM4_MFT2_ICU_ICSB32_IEI1 *((volatile unsigned int*)(0x42443124UL)) - -/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define bFM4_MFT2_ADCMP_ACSD0_AMOD *((volatile unsigned int*)(0x42443aa0UL)) -#define bFM4_MFT2_ADCMP_ACSD0_OCUS *((volatile unsigned int*)(0x42443aa4UL)) -#define bFM4_MFT2_ADCMP_ACSD0_DE *((volatile unsigned int*)(0x42443ab0UL)) -#define bFM4_MFT2_ADCMP_ACSD0_PE *((volatile unsigned int*)(0x42443ab4UL)) -#define bFM4_MFT2_ADCMP_ACSD0_UE *((volatile unsigned int*)(0x42443ab8UL)) -#define bFM4_MFT2_ADCMP_ACSD0_ZE *((volatile unsigned int*)(0x42443abcUL)) -#define bFM4_MFT2_ADCMP_ACSD1_AMOD *((volatile unsigned int*)(0x42443b20UL)) -#define bFM4_MFT2_ADCMP_ACSD1_OCUS *((volatile unsigned int*)(0x42443b24UL)) -#define bFM4_MFT2_ADCMP_ACSD1_DE *((volatile unsigned int*)(0x42443b30UL)) -#define bFM4_MFT2_ADCMP_ACSD1_PE *((volatile unsigned int*)(0x42443b34UL)) -#define bFM4_MFT2_ADCMP_ACSD1_UE *((volatile unsigned int*)(0x42443b38UL)) -#define bFM4_MFT2_ADCMP_ACSD1_ZE *((volatile unsigned int*)(0x42443b3cUL)) -#define bFM4_MFT2_ADCMP_ACSD2_AMOD *((volatile unsigned int*)(0x42443ba0UL)) -#define bFM4_MFT2_ADCMP_ACSD2_OCUS *((volatile unsigned int*)(0x42443ba4UL)) -#define bFM4_MFT2_ADCMP_ACSD2_DE *((volatile unsigned int*)(0x42443bb0UL)) -#define bFM4_MFT2_ADCMP_ACSD2_PE *((volatile unsigned int*)(0x42443bb4UL)) -#define bFM4_MFT2_ADCMP_ACSD2_UE *((volatile unsigned int*)(0x42443bb8UL)) -#define bFM4_MFT2_ADCMP_ACSD2_ZE *((volatile unsigned int*)(0x42443bbcUL)) -#define bFM4_MFT2_ADCMP_ACSD3_AMOD *((volatile unsigned int*)(0x42443c20UL)) -#define bFM4_MFT2_ADCMP_ACSD3_OCUS *((volatile unsigned int*)(0x42443c24UL)) -#define bFM4_MFT2_ADCMP_ACSD3_DE *((volatile unsigned int*)(0x42443c30UL)) -#define bFM4_MFT2_ADCMP_ACSD3_PE *((volatile unsigned int*)(0x42443c34UL)) -#define bFM4_MFT2_ADCMP_ACSD3_UE *((volatile unsigned int*)(0x42443c38UL)) -#define bFM4_MFT2_ADCMP_ACSD3_ZE *((volatile unsigned int*)(0x42443c3cUL)) -#define bFM4_MFT2_ADCMP_ACSD4_AMOD *((volatile unsigned int*)(0x42443ca0UL)) -#define bFM4_MFT2_ADCMP_ACSD4_OCUS *((volatile unsigned int*)(0x42443ca4UL)) -#define bFM4_MFT2_ADCMP_ACSD4_DE *((volatile unsigned int*)(0x42443cb0UL)) -#define bFM4_MFT2_ADCMP_ACSD4_PE *((volatile unsigned int*)(0x42443cb4UL)) -#define bFM4_MFT2_ADCMP_ACSD4_UE *((volatile unsigned int*)(0x42443cb8UL)) -#define bFM4_MFT2_ADCMP_ACSD4_ZE *((volatile unsigned int*)(0x42443cbcUL)) -#define bFM4_MFT2_ADCMP_ACSD5_AMOD *((volatile unsigned int*)(0x42443d20UL)) -#define bFM4_MFT2_ADCMP_ACSD5_OCUS *((volatile unsigned int*)(0x42443d24UL)) -#define bFM4_MFT2_ADCMP_ACSD5_DE *((volatile unsigned int*)(0x42443d30UL)) -#define bFM4_MFT2_ADCMP_ACSD5_PE *((volatile unsigned int*)(0x42443d34UL)) -#define bFM4_MFT2_ADCMP_ACSD5_UE *((volatile unsigned int*)(0x42443d38UL)) -#define bFM4_MFT2_ADCMP_ACSD5_ZE *((volatile unsigned int*)(0x42443d3cUL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) -#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) -#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) -#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) -#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) -#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) -#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) -#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) -#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) -#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) -#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) -#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) -#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) -#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) -#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) -#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) -#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) -#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) -#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) -#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) -#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) -#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) -#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) -#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) -#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) -#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) -#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) -#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) -#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) -#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) -#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) -#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) -#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) -#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) -#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) -#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) -#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) -#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) -#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) -#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) -#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) -#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) -#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) -#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) -#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) -#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) -#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) -#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) -#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) -#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) -#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) -#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) -#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) -#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) -#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) -#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) -#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) -#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) -#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) -#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) -#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) -#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) -#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) -#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) -#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) -#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) -#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) -#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) -#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) -#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) -#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) -#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) -#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) -#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) -#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) -#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) -#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) -#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) -#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM4_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM4_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM4_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM4_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM4_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM4_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM4_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM4_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM4_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM4_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM4_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM4_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM4_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM4_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM4_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM4_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM4_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM4_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM4_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM4_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM4_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM4_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM4_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM4_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM4_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM4_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM4_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM4_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM4_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM4_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM4_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM4_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM4_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM4_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM4_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM4_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM4_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM4_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM4_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM4_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM4_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM4_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM4_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM4_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM4_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM4_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM4_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM4_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM4_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM4_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM4_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM4_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM4_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM4_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM4_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM4_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM4_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM4_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM4_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM4_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM4_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM4_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM4_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM4_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM4_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM4_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM4_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM4_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM4_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM4_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM4_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM4_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM4_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM4_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM4_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM4_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM4_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM4_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM4_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM4_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM4_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM4_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM4_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM4_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM4_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM4_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM4_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM4_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM4_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM4_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM4_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM4_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM4_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM4_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM4_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM4_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM4_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM4_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM4_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM4_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM4_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM4_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM4_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM4_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM4_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM4_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM4_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM4_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM4_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM4_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM4_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM4_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM4_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM4_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM4_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM4_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM4_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM4_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM4_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM4_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM4_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM4_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM4_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM4_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM4_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM4_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM4_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM4_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM4_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM4_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM4_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM4_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM4_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM4_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM4_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM4_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM4_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM4_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM4_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM4_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM4_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM4_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM4_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM4_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM4_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM4_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM4_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM4_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM4_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM4_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM4_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM4_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM4_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM4_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM4_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM4_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM4_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM4_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM4_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM4_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM4_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM4_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM4_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM4_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM4_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM4_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM4_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM4_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM4_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM4_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM4_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM4_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM4_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM4_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM4_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM4_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM4_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM4_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM4_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM4_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM4_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM4_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM4_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM4_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM4_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM4_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM4_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM4_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM4_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM4_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM4_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM4_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM4_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM4_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM4_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM4_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM4_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM4_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM4_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM4_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM4_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM4_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM4_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM4_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM4_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM4_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM4_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM4_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM4_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM4_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM4_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM4_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM4_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM4_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM4_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM4_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM4_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM4_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM4_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM4_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM4_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM4_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM4_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM4_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM4_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM4_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM4_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM4_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM4_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM4_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM4_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM4_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM4_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM4_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM4_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM4_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM4_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM4_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM4_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM4_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM4_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM4_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM4_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM4_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM4_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM4_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM4_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM4_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM4_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM4_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM4_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM4_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM4_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM4_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM4_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM4_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM4_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM4_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM4_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM4_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM4_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM4_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM4_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM4_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM4_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM4_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM4_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM4_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM4_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM4_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM4_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM4_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM4_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM4_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM4_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM4_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM4_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM4_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM4_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM4_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM4_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM4_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM4_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM4_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM4_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM4_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM4_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM4_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM4_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM4_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM4_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM4_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM4_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM4_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM4_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM4_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM4_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM4_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM4_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM4_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM4_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM4_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM4_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM4_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM4_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM4_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM4_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM4_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM4_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM4_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM4_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM4_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM4_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM4_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM4_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM4_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM4_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM4_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM4_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM4_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM4_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM4_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM4_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM4_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM4_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM4_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM4_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM4_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM4_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM4_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM4_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM4_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM4_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM4_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM4_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM4_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM4_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM4_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM4_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM4_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM4_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM4_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM4_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM4_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM4_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM4_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM4_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM4_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM4_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM4_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM4_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM4_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM4_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM4_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM4_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM4_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM4_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM4_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM4_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM4_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM4_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM4_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM4_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM4_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM4_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM4_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM4_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM4_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM4_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM4_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM4_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM4_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM4_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM4_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM4_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM4_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM4_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM4_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM4_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM4_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM4_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM4_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM4_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM4_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM4_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM4_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM4_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM4_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM4_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM4_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM4_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM4_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM4_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM4_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM4_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM4_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM4_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM4_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM4_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM4_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM4_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM4_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM4_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM4_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM4_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM4_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM4_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM4_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM4_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM4_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM4_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM4_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM4_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM4_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM4_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM4_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM4_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM4_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM4_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM4_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM4_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM4_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM4_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM4_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM4_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM4_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM4_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM4_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM4_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM4_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM4_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM4_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM4_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM4_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM4_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM4_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM4_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM4_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM4_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM4_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM4_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM4_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM4_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM4_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM4_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM4_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM4_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM4_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM4_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM4_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM4_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM4_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM4_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM4_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM4_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM4_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM4_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM4_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM4_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM4_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM4_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM4_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM4_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM4_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM4_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM4_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM4_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM4_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM4_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM4_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM4_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM4_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM4_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM4_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM4_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM4_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM4_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM4_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM4_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM4_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM4_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM4_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM4_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM4_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM4_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM4_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM4_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM4_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM4_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM4_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM4_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM4_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM4_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM4_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM4_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM4_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM4_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM4_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM4_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM4_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM4_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM4_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM4_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM4_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM4_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM4_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM4_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM4_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM4_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM4_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM4_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM4_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM4_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM4_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM4_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM4_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM4_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM4_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM4_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM4_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM4_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM4_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM4_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM4_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM4_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM4_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM4_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM4_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM4_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM4_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM4_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM4_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM4_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM4_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM4_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM4_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM4_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM4_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM4_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM4_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM4_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM4_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM4_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM4_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM4_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM4_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM4_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM4_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM4_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM4_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM4_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM4_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM4_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM4_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM4_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM4_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM4_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM4_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM4_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM4_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM4_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM4_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM4_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM4_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM4_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM4_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM4_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM4_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM4_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM4_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM4_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM4_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM4_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM4_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM4_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM4_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM4_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM4_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM4_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM4_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM4_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM4_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM4_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM4_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM4_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM4_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM4_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM4_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM4_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM4_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM4_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM4_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM4_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM4_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM4_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM4_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM4_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM4_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM4_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM4_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM4_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM4_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM4_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM4_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM4_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM4_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM4_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM4_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM4_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM4_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM4_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM4_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Base Timer 8 PPG registers */ -#define bFM4_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM4_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM4_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM4_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM4_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM4_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM4_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM4_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM4_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM4_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM4_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM4_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM4_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM4_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM4_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM4_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWM registers */ -#define bFM4_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM4_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM4_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM4_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM4_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM4_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM4_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM4_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM4_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM4_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM4_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM4_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM4_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) -#define bFM4_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM4_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM4_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) -#define bFM4_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM4_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 RT registers */ -#define bFM4_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM4_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM4_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM4_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM4_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM4_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM4_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM4_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM4_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM4_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM4_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM4_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM4_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM4_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM4_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWC registers */ -#define bFM4_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM4_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM4_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM4_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM4_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM4_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM4_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM4_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM4_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM4_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM4_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM4_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM4_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM4_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) -#define bFM4_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 9 PPG registers */ -#define bFM4_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM4_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM4_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM4_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM4_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM4_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM4_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM4_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM4_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM4_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM4_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM4_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM4_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM4_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM4_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM4_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWM registers */ -#define bFM4_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM4_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM4_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM4_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM4_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM4_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM4_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM4_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM4_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM4_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM4_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM4_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM4_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) -#define bFM4_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM4_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM4_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) -#define bFM4_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM4_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 RT registers */ -#define bFM4_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM4_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM4_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM4_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM4_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM4_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM4_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM4_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM4_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM4_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM4_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM4_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM4_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM4_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM4_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWC registers */ -#define bFM4_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM4_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM4_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM4_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM4_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM4_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM4_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM4_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM4_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM4_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM4_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM4_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM4_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM4_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) -#define bFM4_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 10 PPG registers */ -#define bFM4_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM4_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM4_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM4_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM4_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM4_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM4_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM4_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM4_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM4_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM4_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM4_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM4_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM4_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM4_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM4_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWM registers */ -#define bFM4_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM4_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM4_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM4_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM4_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM4_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM4_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM4_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM4_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM4_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM4_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM4_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM4_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) -#define bFM4_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM4_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM4_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) -#define bFM4_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM4_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 RT registers */ -#define bFM4_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM4_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM4_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM4_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM4_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM4_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM4_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM4_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM4_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM4_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM4_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM4_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM4_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM4_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM4_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWC registers */ -#define bFM4_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM4_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM4_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM4_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM4_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM4_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM4_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM4_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM4_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM4_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM4_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM4_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM4_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM4_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) -#define bFM4_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 11 PPG registers */ -#define bFM4_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM4_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM4_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM4_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM4_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM4_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM4_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM4_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM4_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM4_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM4_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM4_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM4_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM4_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM4_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM4_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWM registers */ -#define bFM4_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM4_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM4_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM4_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM4_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM4_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM4_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM4_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM4_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM4_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM4_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM4_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM4_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) -#define bFM4_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM4_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM4_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) -#define bFM4_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM4_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 RT registers */ -#define bFM4_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM4_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM4_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM4_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM4_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM4_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM4_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM4_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM4_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM4_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM4_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM4_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM4_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM4_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM4_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWC registers */ -#define bFM4_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM4_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM4_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM4_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM4_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM4_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM4_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM4_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM4_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM4_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM4_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM4_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM4_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM4_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) -#define bFM4_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 12 PPG registers */ -#define bFM4_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM4_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM4_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM4_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM4_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM4_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM4_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM4_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM4_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM4_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM4_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM4_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM4_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM4_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM4_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM4_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWM registers */ -#define bFM4_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM4_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM4_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM4_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM4_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM4_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM4_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM4_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM4_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM4_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM4_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM4_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM4_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) -#define bFM4_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM4_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM4_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) -#define bFM4_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM4_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 RT registers */ -#define bFM4_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM4_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM4_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM4_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM4_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM4_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM4_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM4_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM4_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM4_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM4_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM4_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM4_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM4_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM4_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWC registers */ -#define bFM4_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM4_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM4_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM4_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM4_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM4_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM4_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM4_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM4_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM4_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM4_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM4_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM4_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM4_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) -#define bFM4_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 13 PPG registers */ -#define bFM4_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM4_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM4_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM4_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM4_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM4_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM4_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM4_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM4_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM4_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM4_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM4_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM4_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM4_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM4_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM4_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWM registers */ -#define bFM4_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM4_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM4_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM4_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM4_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM4_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM4_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM4_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM4_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM4_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM4_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM4_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM4_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) -#define bFM4_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM4_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM4_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) -#define bFM4_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM4_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 RT registers */ -#define bFM4_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM4_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM4_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM4_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM4_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM4_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM4_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM4_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM4_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM4_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM4_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM4_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM4_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM4_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM4_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWC registers */ -#define bFM4_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM4_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM4_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM4_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM4_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM4_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM4_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM4_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM4_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM4_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM4_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM4_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM4_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM4_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) -#define bFM4_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 14 PPG registers */ -#define bFM4_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM4_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM4_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM4_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM4_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM4_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM4_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM4_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM4_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM4_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM4_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM4_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM4_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM4_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM4_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM4_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWM registers */ -#define bFM4_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM4_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM4_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM4_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM4_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM4_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM4_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM4_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM4_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM4_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM4_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM4_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM4_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) -#define bFM4_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM4_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM4_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) -#define bFM4_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM4_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 RT registers */ -#define bFM4_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM4_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM4_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM4_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM4_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM4_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM4_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM4_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM4_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM4_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM4_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM4_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM4_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM4_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM4_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWC registers */ -#define bFM4_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM4_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM4_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM4_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM4_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM4_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM4_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM4_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM4_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM4_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM4_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM4_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM4_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM4_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) -#define bFM4_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 15 PPG registers */ -#define bFM4_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM4_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM4_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM4_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM4_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM4_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM4_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM4_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM4_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM4_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM4_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM4_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM4_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM4_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM4_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM4_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWM registers */ -#define bFM4_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM4_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM4_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM4_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM4_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM4_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM4_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM4_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM4_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM4_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM4_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM4_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM4_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) -#define bFM4_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM4_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM4_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) -#define bFM4_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM4_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 RT registers */ -#define bFM4_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM4_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM4_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM4_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM4_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM4_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM4_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM4_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM4_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM4_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM4_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM4_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM4_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM4_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM4_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWC registers */ -#define bFM4_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM4_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM4_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM4_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM4_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM4_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM4_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM4_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM4_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM4_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM4_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM4_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM4_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM4_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) -#define bFM4_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer I/O selector channel 8 - channel 11 registers */ -#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) -#define bFM4_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) - -/* Base Timer I/O selector channel 12 - channel 15 registers */ -#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) -#define bFM4_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM4_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM4_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM4_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM4_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM4_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM4_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM4_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM4_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM4_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM4_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM4_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM4_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM4_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM4_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM4_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM4_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM4_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM4_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM4_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM4_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM4_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM4_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM4_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM4_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM4_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM4_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM4_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM4_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM4_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM4_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM4_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM4_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM4_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM4_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM4_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM4_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM4_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM4_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM4_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM4_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM4_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM4_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM4_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM4_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM4_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM4_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM4_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM4_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM4_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM4_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM4_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM4_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM4_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM4_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM4_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM4_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM4_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM4_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM4_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM4_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM4_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM4_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM4_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM4_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM4_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM4_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM4_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM4_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM4_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM4_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM4_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM4_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM4_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM4_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM4_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM4_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM4_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM4_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM4_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM4_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM4_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM4_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM4_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM4_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM4_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM4_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM4_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM4_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM4_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM4_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM4_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM4_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM4_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM4_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM4_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM4_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM4_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM4_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM4_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM4_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM4_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM4_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM4_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM4_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM4_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM4_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM4_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM4_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM4_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM4_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM4_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM4_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM4_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM4_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM4_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM4_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM4_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM4_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM4_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM4_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM4_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM4_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM4_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM4_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM4_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM4_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM4_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM4_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM4_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM4_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM4_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM4_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM4_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM4_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM4_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM4_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM4_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM4_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM4_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM4_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM4_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM4_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* Quad position and revolution counter channel 2 registers */ -#define bFM4_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM4_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM4_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM4_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM4_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM4_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM4_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM4_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM4_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM4_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM4_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM4_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM4_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM4_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM4_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM4_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM4_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM4_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM4_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM4_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM4_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM4_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM4_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM4_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM4_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM4_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM4_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM4_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM4_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM4_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM4_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM4_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM4_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM4_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM4_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM4_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM4_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM4_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM4_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM4_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM4_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM4_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM4_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM4_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM4_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM4_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM4_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM4_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM4_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM4_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM4_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM4_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM4_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM4_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM4_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM4_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM4_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM4_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM4_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM4_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM4_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) -#define bFM4_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) -#define bFM4_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) - -/* Quad position and revolution counter channel 3 registers */ -#define bFM4_QPRC3_QICR_QPCMIE *((volatile unsigned int*)(0x424c1a80UL)) -#define bFM4_QPRC3_QICR_QPCMF *((volatile unsigned int*)(0x424c1a84UL)) -#define bFM4_QPRC3_QICR_QPRCMIE *((volatile unsigned int*)(0x424c1a88UL)) -#define bFM4_QPRC3_QICR_QPRCMF *((volatile unsigned int*)(0x424c1a8cUL)) -#define bFM4_QPRC3_QICR_OUZIE *((volatile unsigned int*)(0x424c1a90UL)) -#define bFM4_QPRC3_QICR_UFDF *((volatile unsigned int*)(0x424c1a94UL)) -#define bFM4_QPRC3_QICR_OFDF *((volatile unsigned int*)(0x424c1a98UL)) -#define bFM4_QPRC3_QICR_ZIIF *((volatile unsigned int*)(0x424c1a9cUL)) -#define bFM4_QPRC3_QICR_CDCIE *((volatile unsigned int*)(0x424c1aa0UL)) -#define bFM4_QPRC3_QICR_CDCF *((volatile unsigned int*)(0x424c1aa4UL)) -#define bFM4_QPRC3_QICR_DIRPC *((volatile unsigned int*)(0x424c1aa8UL)) -#define bFM4_QPRC3_QICR_DIROU *((volatile unsigned int*)(0x424c1aacUL)) -#define bFM4_QPRC3_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424c1ab0UL)) -#define bFM4_QPRC3_QICR_QPCNRCMF *((volatile unsigned int*)(0x424c1ab4UL)) -#define bFM4_QPRC3_QCR_PCM0 *((volatile unsigned int*)(0x424c1b00UL)) -#define bFM4_QPRC3_QCR_PCM1 *((volatile unsigned int*)(0x424c1b04UL)) -#define bFM4_QPRC3_QCR_RCM0 *((volatile unsigned int*)(0x424c1b08UL)) -#define bFM4_QPRC3_QCR_RCM1 *((volatile unsigned int*)(0x424c1b0cUL)) -#define bFM4_QPRC3_QCR_PSTP *((volatile unsigned int*)(0x424c1b10UL)) -#define bFM4_QPRC3_QCR_CGSC *((volatile unsigned int*)(0x424c1b14UL)) -#define bFM4_QPRC3_QCR_RSEL *((volatile unsigned int*)(0x424c1b18UL)) -#define bFM4_QPRC3_QCR_SWAP *((volatile unsigned int*)(0x424c1b1cUL)) -#define bFM4_QPRC3_QCR_PCRM0 *((volatile unsigned int*)(0x424c1b20UL)) -#define bFM4_QPRC3_QCR_PCRM1 *((volatile unsigned int*)(0x424c1b24UL)) -#define bFM4_QPRC3_QCR_AES0 *((volatile unsigned int*)(0x424c1b28UL)) -#define bFM4_QPRC3_QCR_AES1 *((volatile unsigned int*)(0x424c1b2cUL)) -#define bFM4_QPRC3_QCR_BES0 *((volatile unsigned int*)(0x424c1b30UL)) -#define bFM4_QPRC3_QCR_BES1 *((volatile unsigned int*)(0x424c1b34UL)) -#define bFM4_QPRC3_QCR_CGE0 *((volatile unsigned int*)(0x424c1b38UL)) -#define bFM4_QPRC3_QCR_CGE1 *((volatile unsigned int*)(0x424c1b3cUL)) -#define bFM4_QPRC3_QECR_ORNGMD *((volatile unsigned int*)(0x424c1b80UL)) -#define bFM4_QPRC3_QECR_ORNGF *((volatile unsigned int*)(0x424c1b84UL)) -#define bFM4_QPRC3_QECR_ORNGIE *((volatile unsigned int*)(0x424c1b88UL)) - -/* QPRC NF channel 0 registers */ -#define bFM4_QPRC0_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2010UL)) -#define bFM4_QPRC0_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2014UL)) -#define bFM4_QPRC0_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2090UL)) -#define bFM4_QPRC0_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2094UL)) -#define bFM4_QPRC0_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2110UL)) -#define bFM4_QPRC0_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2114UL)) - -/* QPRC NF channel 1 registers */ -#define bFM4_QPRC1_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2210UL)) -#define bFM4_QPRC1_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2214UL)) -#define bFM4_QPRC1_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2290UL)) -#define bFM4_QPRC1_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2294UL)) -#define bFM4_QPRC1_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2310UL)) -#define bFM4_QPRC1_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2314UL)) - -/* QPRC NF channel 2 registers */ -#define bFM4_QPRC2_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2410UL)) -#define bFM4_QPRC2_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2414UL)) -#define bFM4_QPRC2_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2490UL)) -#define bFM4_QPRC2_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2494UL)) -#define bFM4_QPRC2_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2510UL)) -#define bFM4_QPRC2_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2514UL)) - -/* QPRC NF channel 3 registers */ -#define bFM4_QPRC3_NF_NFCTLA_AINLV *((volatile unsigned int*)(0x424c2610UL)) -#define bFM4_QPRC3_NF_NFCTLA_AINMD *((volatile unsigned int*)(0x424c2614UL)) -#define bFM4_QPRC3_NF_NFCTLB_BINLV *((volatile unsigned int*)(0x424c2690UL)) -#define bFM4_QPRC3_NF_NFCTLB_BINMD *((volatile unsigned int*)(0x424c2694UL)) -#define bFM4_QPRC3_NF_NFRCTLZ_ZINLV *((volatile unsigned int*)(0x424c2710UL)) -#define bFM4_QPRC3_NF_NFRCTLZ_ZINMD *((volatile unsigned int*)(0x424c2714UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM4_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM4_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM4_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM4_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM4_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM4_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM4_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM4_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM4_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM4_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM4_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM4_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM4_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM4_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM4_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM4_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM4_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM4_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM4_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM4_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM4_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM4_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM4_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM4_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM4_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM4_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM4_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM4_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM4_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM4_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM4_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM4_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM4_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM4_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM4_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM4_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM4_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM4_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM4_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM4_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM4_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM4_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM4_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM4_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM4_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM4_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM4_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM4_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM4_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM4_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM4_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM4_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM4_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM4_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM4_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM4_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM4_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM4_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM4_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM4_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM4_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM4_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM4_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM4_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM4_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM4_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM4_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM4_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM4_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM4_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM4_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM4_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM4_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM4_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM4_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM4_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM4_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM4_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM4_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM4_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM4_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM4_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM4_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM4_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM4_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM4_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM4_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM4_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM4_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM4_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM4_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM4_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM4_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM4_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM4_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM4_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM4_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM4_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM4_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM4_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM4_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM4_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM4_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM4_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM4_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM4_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM4_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM4_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM4_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM4_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM4_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM4_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM4_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM4_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM4_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM4_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM4_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM4_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM4_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM4_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM4_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM4_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM4_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM4_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM4_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM4_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM4_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM4_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM4_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM4_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM4_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM4_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM4_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM4_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM4_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM4_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM4_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM4_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM4_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM4_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM4_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM4_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM4_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM4_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM4_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM4_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM4_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM4_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM4_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM4_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM4_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM4_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM4_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM4_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM4_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM4_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM4_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM4_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM4_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM4_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM4_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM4_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM4_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM4_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM4_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM4_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM4_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM4_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM4_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM4_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM4_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM4_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM4_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM4_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM4_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM4_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM4_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM4_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM4_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM4_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM4_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM4_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM4_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM4_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM4_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM4_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM4_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM4_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM4_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM4_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM4_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM4_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM4_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM4_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM4_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM4_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM4_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM4_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM4_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM4_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM4_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM4_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM4_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM4_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM4_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM4_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM4_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM4_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM4_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM4_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM4_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM4_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM4_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM4_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM4_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM4_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM4_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM4_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM4_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM4_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM4_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM4_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM4_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM4_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM4_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM4_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM4_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM4_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM4_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM4_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM4_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM4_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM4_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM4_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM4_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM4_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM4_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM4_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM4_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM4_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM4_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM4_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM4_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM4_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM4_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM4_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM4_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM4_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM4_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM4_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM4_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM4_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM4_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM4_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM4_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM4_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM4_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM4_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM4_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM4_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM4_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM4_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM4_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM4_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM4_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM4_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM4_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM4_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM4_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM4_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM4_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM4_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM4_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM4_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM4_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM4_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM4_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM4_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM4_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM4_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM4_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM4_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM4_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM4_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM4_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM4_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM4_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM4_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM4_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM4_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM4_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM4_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM4_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM4_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM4_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM4_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM4_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM4_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM4_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM4_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM4_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM4_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM4_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM4_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM4_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM4_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM4_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM4_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM4_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM4_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM4_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM4_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM4_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM4_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM4_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM4_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM4_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM4_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM4_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM4_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM4_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM4_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM4_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM4_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM4_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM4_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM4_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM4_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM4_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM4_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM4_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM4_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM4_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM4_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM4_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM4_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM4_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM4_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM4_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM4_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM4_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM4_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM4_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM4_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM4_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM4_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM4_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM4_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM4_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM4_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM4_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM4_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM4_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM4_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM4_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM4_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM4_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM4_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM4_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM4_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM4_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM4_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM4_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM4_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM4_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM4_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM4_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM4_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM4_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM4_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM4_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM4_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM4_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM4_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM4_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM4_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM4_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM4_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM4_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM4_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM4_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM4_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM4_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM4_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM4_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM4_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM4_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM4_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM4_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM4_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM4_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM4_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM4_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM4_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM4_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM4_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM4_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM4_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM4_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM4_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM4_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM4_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM4_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM4_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM4_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM4_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM4_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM4_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM4_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM4_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM4_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM4_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM4_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM4_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM4_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM4_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM4_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM4_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM4_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM4_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM4_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM4_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM4_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM4_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM4_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM4_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM4_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM4_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM4_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM4_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM4_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM4_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM4_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM4_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM4_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM4_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM4_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM4_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM4_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM4_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM4_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM4_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM4_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM4_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM4_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM4_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM4_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM4_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM4_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM4_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM4_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM4_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM4_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM4_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM4_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM4_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM4_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM4_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM4_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM4_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM4_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM4_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM4_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM4_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM4_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM4_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM4_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM4_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM4_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM4_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM4_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM4_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM4_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM4_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM4_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM4_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM4_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM4_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM4_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM4_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM4_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM4_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM4_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM4_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM4_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM4_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM4_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM4_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM4_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM4_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM4_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM4_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM4_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM4_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM4_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM4_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM4_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM4_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM4_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM4_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM4_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM4_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM4_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM4_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM4_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM4_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM4_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM4_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM4_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM4_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM4_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM4_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM4_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM4_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM4_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM4_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM4_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM4_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM4_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM4_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM4_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM4_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM4_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM4_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM4_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM4_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM4_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM4_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM4_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM4_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM4_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM4_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM4_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM4_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM4_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM4_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM4_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM4_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM4_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM4_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM4_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM4_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM4_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM4_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM4_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM4_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM4_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM4_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM4_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM4_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM4_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM4_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM4_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM4_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM4_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM4_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM4_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM4_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM4_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM4_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM4_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM4_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM4_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM4_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM4_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM4_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM4_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM4_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM4_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM4_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM4_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM4_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM4_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM4_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM4_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM4_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM4_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM4_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM4_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM4_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM4_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM4_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM4_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM4_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM4_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM4_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM4_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM4_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM4_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM4_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM4_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM4_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM4_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM4_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM4_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM4_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM4_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM4_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM4_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM4_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM4_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM4_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM4_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM4_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM4_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM4_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM4_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM4_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM4_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM4_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM4_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM4_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM4_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM4_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM4_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM4_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM4_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM4_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM4_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM4_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM4_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM4_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM4_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM4_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM4_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM4_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM4_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM4_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM4_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM4_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM4_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM4_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM4_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM4_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM4_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM4_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM4_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM4_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM4_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM4_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM4_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM4_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM4_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM4_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM4_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM4_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM4_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM4_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM4_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM4_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM4_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM4_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM4_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM4_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM4_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM4_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM4_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM4_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM4_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM4_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM4_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM4_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM4_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM4_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM4_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM4_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM4_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM4_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM4_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM4_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM4_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM4_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM4_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM4_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM4_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM4_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM4_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM4_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM4_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM4_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM4_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM4_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM4_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM4_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM4_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM4_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM4_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM4_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM4_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM4_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM4_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM4_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM4_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM4_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM4_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM4_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM4_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM4_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM4_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM4_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM4_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM4_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM4_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM4_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM4_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM4_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM4_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM4_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM4_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM4_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM4_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM4_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM4_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM4_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM4_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM4_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM4_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM4_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM4_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM4_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM4_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM4_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM4_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM4_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM4_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM4_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM4_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM4_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM4_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM4_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM4_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM4_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM4_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM4_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM4_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM4_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM4_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM4_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM4_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM4_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM4_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM4_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM4_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM4_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM4_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM4_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM4_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM4_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM4_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM4_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM4_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM4_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM4_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM4_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM4_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM4_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM4_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM4_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM4_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM4_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM4_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM4_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM4_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM4_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM4_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM4_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM4_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM4_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM4_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM4_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM4_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM4_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM4_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM4_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM4_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM4_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM4_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM4_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM4_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM4_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM4_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM4_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM4_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM4_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM4_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM4_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM4_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM4_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM4_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM4_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM4_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM4_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM4_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM4_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM4_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM4_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM4_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM4_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM4_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM4_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM4_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM4_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM4_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM4_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM4_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM4_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM4_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM4_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM4_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM4_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM4_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM4_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM4_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM4_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM4_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM4_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM4_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM4_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM4_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM4_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM4_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM4_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM4_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM4_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM4_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM4_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM4_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM4_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM4_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM4_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM4_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM4_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM4_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM4_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM4_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM4_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM4_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM4_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM4_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM4_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM4_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM4_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM4_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM4_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM4_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM4_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM4_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM4_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM4_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM4_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM4_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM4_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM4_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM4_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM4_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM4_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM4_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM4_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM4_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM4_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM4_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM4_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM4_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM4_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM4_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM4_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM4_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM4_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM4_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM4_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM4_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM4_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM4_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM4_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM4_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM4_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM4_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM4_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM4_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM4_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM4_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM4_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM4_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM4_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM4_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM4_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM4_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM4_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM4_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM4_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM4_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM4_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM4_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM4_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM4_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM4_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM4_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM4_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM4_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM4_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM4_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM4_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM4_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM4_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM4_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM4_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM4_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM4_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM4_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM4_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM4_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM4_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM4_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM4_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM4_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM4_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM4_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM4_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM4_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM4_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM4_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM4_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM4_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM4_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM4_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM4_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM4_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM4_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM4_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM4_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM4_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM4_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM4_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM4_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM4_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM4_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM4_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM4_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM4_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM4_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM4_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM4_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM4_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM4_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM4_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM4_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM4_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM4_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) - -/* CR trimming registers */ -#define bFM4_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM4_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM4_CRTRIM_MCR_PSR_CSR2 *((volatile unsigned int*)(0x425C0008UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) -#define bFM4_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) -#define bFM4_CRTRIM_MCR_TTRM_TRT0 *((volatile unsigned int*)(0x425C0100UL)) -#define bFM4_CRTRIM_MCR_TTRM_TRT1 *((volatile unsigned int*)(0x425C0104UL)) -#define bFM4_CRTRIM_MCR_TTRM_TRT2 *((volatile unsigned int*)(0x425C0108UL)) -#define bFM4_CRTRIM_MCR_TTRM_TRT3 *((volatile unsigned int*)(0x425C010CUL)) -#define bFM4_CRTRIM_MCR_TTRM_TRT4 *((volatile unsigned int*)(0x425C0110UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK0 *((volatile unsigned int*)(0x425C0180UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK1 *((volatile unsigned int*)(0x425C0184UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK2 *((volatile unsigned int*)(0x425C0188UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK3 *((volatile unsigned int*)(0x425C018CUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK4 *((volatile unsigned int*)(0x425C0190UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK5 *((volatile unsigned int*)(0x425C0194UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK6 *((volatile unsigned int*)(0x425C0198UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK7 *((volatile unsigned int*)(0x425C019CUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK8 *((volatile unsigned int*)(0x425C01A0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK9 *((volatile unsigned int*)(0x425C01A4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK10 *((volatile unsigned int*)(0x425C01A8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK11 *((volatile unsigned int*)(0x425C01ACUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK12 *((volatile unsigned int*)(0x425C01B0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK13 *((volatile unsigned int*)(0x425C01B4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK14 *((volatile unsigned int*)(0x425C01B8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK15 *((volatile unsigned int*)(0x425C01BCUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK16 *((volatile unsigned int*)(0x425C01C0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK17 *((volatile unsigned int*)(0x425C01C4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK18 *((volatile unsigned int*)(0x425C01C8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK19 *((volatile unsigned int*)(0x425C01CCUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK20 *((volatile unsigned int*)(0x425C01D0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK21 *((volatile unsigned int*)(0x425C01D4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK22 *((volatile unsigned int*)(0x425C01D8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK23 *((volatile unsigned int*)(0x425C01DCUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK24 *((volatile unsigned int*)(0x425C01E0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK25 *((volatile unsigned int*)(0x425C01E4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK26 *((volatile unsigned int*)(0x425C01E8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK27 *((volatile unsigned int*)(0x425C01ECUL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK28 *((volatile unsigned int*)(0x425C01F0UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK29 *((volatile unsigned int*)(0x425C01F4UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK30 *((volatile unsigned int*)(0x425C01F8UL)) -#define bFM4_CRTRIM_MCR_RLR_TRMLCK31 *((volatile unsigned int*)(0x425C01FCUL)) - -/* External interrupt registers */ -#define bFM4_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM4_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM4_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM4_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM4_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM4_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM4_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM4_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM4_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM4_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM4_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM4_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM4_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM4_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM4_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM4_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM4_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) -#define bFM4_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) -#define bFM4_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) -#define bFM4_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) -#define bFM4_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) -#define bFM4_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) -#define bFM4_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) -#define bFM4_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) -#define bFM4_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) -#define bFM4_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) -#define bFM4_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) -#define bFM4_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) -#define bFM4_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) -#define bFM4_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) -#define bFM4_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) -#define bFM4_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) -#define bFM4_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM4_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM4_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM4_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM4_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM4_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM4_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM4_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM4_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM4_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM4_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM4_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM4_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM4_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM4_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM4_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM4_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) -#define bFM4_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) -#define bFM4_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) -#define bFM4_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) -#define bFM4_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) -#define bFM4_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) -#define bFM4_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) -#define bFM4_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) -#define bFM4_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) -#define bFM4_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) -#define bFM4_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) -#define bFM4_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) -#define bFM4_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) -#define bFM4_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) -#define bFM4_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) -#define bFM4_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) -#define bFM4_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM4_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM4_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM4_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM4_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM4_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM4_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM4_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM4_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM4_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM4_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM4_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM4_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM4_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM4_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM4_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM4_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) -#define bFM4_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) -#define bFM4_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) -#define bFM4_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) -#define bFM4_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) -#define bFM4_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) -#define bFM4_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) -#define bFM4_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) -#define bFM4_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) -#define bFM4_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) -#define bFM4_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) -#define bFM4_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) -#define bFM4_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) -#define bFM4_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) -#define bFM4_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) -#define bFM4_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) -#define bFM4_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM4_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM4_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM4_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM4_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM4_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM4_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM4_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM4_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM4_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM4_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM4_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM4_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM4_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM4_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM4_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM4_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM4_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM4_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM4_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM4_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM4_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM4_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM4_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM4_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM4_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM4_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM4_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM4_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM4_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM4_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM4_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM4_EXTI_ELVR1_LA16 *((volatile unsigned int*)(0x42600200UL)) -#define bFM4_EXTI_ELVR1_LB16 *((volatile unsigned int*)(0x42600204UL)) -#define bFM4_EXTI_ELVR1_LA17 *((volatile unsigned int*)(0x42600208UL)) -#define bFM4_EXTI_ELVR1_LB17 *((volatile unsigned int*)(0x4260020CUL)) -#define bFM4_EXTI_ELVR1_LA18 *((volatile unsigned int*)(0x42600210UL)) -#define bFM4_EXTI_ELVR1_LB18 *((volatile unsigned int*)(0x42600214UL)) -#define bFM4_EXTI_ELVR1_LA19 *((volatile unsigned int*)(0x42600218UL)) -#define bFM4_EXTI_ELVR1_LB19 *((volatile unsigned int*)(0x4260021CUL)) -#define bFM4_EXTI_ELVR1_LA20 *((volatile unsigned int*)(0x42600220UL)) -#define bFM4_EXTI_ELVR1_LB20 *((volatile unsigned int*)(0x42600224UL)) -#define bFM4_EXTI_ELVR1_LA21 *((volatile unsigned int*)(0x42600228UL)) -#define bFM4_EXTI_ELVR1_LB21 *((volatile unsigned int*)(0x4260022CUL)) -#define bFM4_EXTI_ELVR1_LA22 *((volatile unsigned int*)(0x42600230UL)) -#define bFM4_EXTI_ELVR1_LB22 *((volatile unsigned int*)(0x42600234UL)) -#define bFM4_EXTI_ELVR1_LA23 *((volatile unsigned int*)(0x42600238UL)) -#define bFM4_EXTI_ELVR1_LB23 *((volatile unsigned int*)(0x4260023CUL)) -#define bFM4_EXTI_ELVR1_LA24 *((volatile unsigned int*)(0x42600240UL)) -#define bFM4_EXTI_ELVR1_LB24 *((volatile unsigned int*)(0x42600244UL)) -#define bFM4_EXTI_ELVR1_LA25 *((volatile unsigned int*)(0x42600248UL)) -#define bFM4_EXTI_ELVR1_LB25 *((volatile unsigned int*)(0x4260024CUL)) -#define bFM4_EXTI_ELVR1_LA26 *((volatile unsigned int*)(0x42600250UL)) -#define bFM4_EXTI_ELVR1_LB26 *((volatile unsigned int*)(0x42600254UL)) -#define bFM4_EXTI_ELVR1_LA27 *((volatile unsigned int*)(0x42600258UL)) -#define bFM4_EXTI_ELVR1_LB27 *((volatile unsigned int*)(0x4260025CUL)) -#define bFM4_EXTI_ELVR1_LA28 *((volatile unsigned int*)(0x42600260UL)) -#define bFM4_EXTI_ELVR1_LB28 *((volatile unsigned int*)(0x42600264UL)) -#define bFM4_EXTI_ELVR1_LA29 *((volatile unsigned int*)(0x42600268UL)) -#define bFM4_EXTI_ELVR1_LB29 *((volatile unsigned int*)(0x4260026CUL)) -#define bFM4_EXTI_ELVR1_LA30 *((volatile unsigned int*)(0x42600270UL)) -#define bFM4_EXTI_ELVR1_LB30 *((volatile unsigned int*)(0x42600274UL)) -#define bFM4_EXTI_ELVR1_LA31 *((volatile unsigned int*)(0x42600278UL)) -#define bFM4_EXTI_ELVR1_LB31 *((volatile unsigned int*)(0x4260027CUL)) -#define bFM4_EXTI_NMIRR_NR *((volatile unsigned int*)(0x42600280UL)) -#define bFM4_EXTI_NMICL_NCL *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM4_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM4_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM4_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned int*)(0x42620200UL)) -#define bFM4_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned int*)(0x42620204UL)) -#define bFM4_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned int*)(0x42620208UL)) -#define bFM4_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned int*)(0x4262020CUL)) -#define bFM4_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned int*)(0x42620210UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ0 *((volatile unsigned int*)(0x42622200UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ1 *((volatile unsigned int*)(0x42622204UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ2 *((volatile unsigned int*)(0x42622208UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ3 *((volatile unsigned int*)(0x4262220CUL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ4 *((volatile unsigned int*)(0x42622210UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ5 *((volatile unsigned int*)(0x42622214UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ6 *((volatile unsigned int*)(0x42622218UL)) -#define bFM4_INTREQ_IRQ003SEL_SELIRQ7 *((volatile unsigned int*)(0x4262221CUL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT0 *((volatile unsigned int*)(0x42622240UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT1 *((volatile unsigned int*)(0x42622244UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT2 *((volatile unsigned int*)(0x42622248UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT3 *((volatile unsigned int*)(0x4262224CUL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT4 *((volatile unsigned int*)(0x42622250UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT5 *((volatile unsigned int*)(0x42622254UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT6 *((volatile unsigned int*)(0x42622258UL)) -#define bFM4_INTREQ_IRQ003SEL_SELBIT7 *((volatile unsigned int*)(0x4262225CUL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ0 *((volatile unsigned int*)(0x42622280UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ1 *((volatile unsigned int*)(0x42622284UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ2 *((volatile unsigned int*)(0x42622288UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ3 *((volatile unsigned int*)(0x4262228CUL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ4 *((volatile unsigned int*)(0x42622290UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ5 *((volatile unsigned int*)(0x42622294UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ6 *((volatile unsigned int*)(0x42622298UL)) -#define bFM4_INTREQ_IRQ004SEL_SELIRQ7 *((volatile unsigned int*)(0x4262229CUL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT0 *((volatile unsigned int*)(0x426222C0UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT1 *((volatile unsigned int*)(0x426222C4UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT2 *((volatile unsigned int*)(0x426222C8UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT3 *((volatile unsigned int*)(0x426222CCUL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT4 *((volatile unsigned int*)(0x426222D0UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT5 *((volatile unsigned int*)(0x426222D4UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT6 *((volatile unsigned int*)(0x426222D8UL)) -#define bFM4_INTREQ_IRQ004SEL_SELBIT7 *((volatile unsigned int*)(0x426222DCUL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ0 *((volatile unsigned int*)(0x42622300UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ1 *((volatile unsigned int*)(0x42622304UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ2 *((volatile unsigned int*)(0x42622308UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ3 *((volatile unsigned int*)(0x4262230CUL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ4 *((volatile unsigned int*)(0x42622310UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ5 *((volatile unsigned int*)(0x42622314UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ6 *((volatile unsigned int*)(0x42622318UL)) -#define bFM4_INTREQ_IRQ005SEL_SELIRQ7 *((volatile unsigned int*)(0x4262231CUL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT0 *((volatile unsigned int*)(0x42622340UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT1 *((volatile unsigned int*)(0x42622344UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT2 *((volatile unsigned int*)(0x42622348UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT3 *((volatile unsigned int*)(0x4262234CUL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT4 *((volatile unsigned int*)(0x42622350UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT5 *((volatile unsigned int*)(0x42622354UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT6 *((volatile unsigned int*)(0x42622358UL)) -#define bFM4_INTREQ_IRQ005SEL_SELBIT7 *((volatile unsigned int*)(0x4262235CUL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ0 *((volatile unsigned int*)(0x42622380UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ1 *((volatile unsigned int*)(0x42622384UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ2 *((volatile unsigned int*)(0x42622388UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ3 *((volatile unsigned int*)(0x4262238CUL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ4 *((volatile unsigned int*)(0x42622390UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ5 *((volatile unsigned int*)(0x42622394UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ6 *((volatile unsigned int*)(0x42622398UL)) -#define bFM4_INTREQ_IRQ006SEL_SELIRQ7 *((volatile unsigned int*)(0x4262239CUL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT0 *((volatile unsigned int*)(0x426223C0UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT1 *((volatile unsigned int*)(0x426223C4UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT2 *((volatile unsigned int*)(0x426223C8UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT3 *((volatile unsigned int*)(0x426223CCUL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT4 *((volatile unsigned int*)(0x426223D0UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT5 *((volatile unsigned int*)(0x426223D4UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT6 *((volatile unsigned int*)(0x426223D8UL)) -#define bFM4_INTREQ_IRQ006SEL_SELBIT7 *((volatile unsigned int*)(0x426223DCUL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ0 *((volatile unsigned int*)(0x42622400UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ1 *((volatile unsigned int*)(0x42622404UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ2 *((volatile unsigned int*)(0x42622408UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ3 *((volatile unsigned int*)(0x4262240CUL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ4 *((volatile unsigned int*)(0x42622410UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ5 *((volatile unsigned int*)(0x42622414UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ6 *((volatile unsigned int*)(0x42622418UL)) -#define bFM4_INTREQ_IRQ007SEL_SELIRQ7 *((volatile unsigned int*)(0x4262241CUL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT0 *((volatile unsigned int*)(0x42622440UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT1 *((volatile unsigned int*)(0x42622444UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT2 *((volatile unsigned int*)(0x42622448UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT3 *((volatile unsigned int*)(0x4262244CUL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT4 *((volatile unsigned int*)(0x42622450UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT5 *((volatile unsigned int*)(0x42622454UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT6 *((volatile unsigned int*)(0x42622458UL)) -#define bFM4_INTREQ_IRQ007SEL_SELBIT7 *((volatile unsigned int*)(0x4262245CUL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ0 *((volatile unsigned int*)(0x42622480UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ1 *((volatile unsigned int*)(0x42622484UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ2 *((volatile unsigned int*)(0x42622488UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ3 *((volatile unsigned int*)(0x4262248CUL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ4 *((volatile unsigned int*)(0x42622490UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ5 *((volatile unsigned int*)(0x42622494UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ6 *((volatile unsigned int*)(0x42622498UL)) -#define bFM4_INTREQ_IRQ008SEL_SELIRQ7 *((volatile unsigned int*)(0x4262249CUL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT0 *((volatile unsigned int*)(0x426224C0UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT1 *((volatile unsigned int*)(0x426224C4UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT2 *((volatile unsigned int*)(0x426224C8UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT3 *((volatile unsigned int*)(0x426224CCUL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT4 *((volatile unsigned int*)(0x426224D0UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT5 *((volatile unsigned int*)(0x426224D4UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT6 *((volatile unsigned int*)(0x426224D8UL)) -#define bFM4_INTREQ_IRQ008SEL_SELBIT7 *((volatile unsigned int*)(0x426224DCUL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ0 *((volatile unsigned int*)(0x42622500UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ1 *((volatile unsigned int*)(0x42622504UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ2 *((volatile unsigned int*)(0x42622508UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ3 *((volatile unsigned int*)(0x4262250CUL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ4 *((volatile unsigned int*)(0x42622510UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ5 *((volatile unsigned int*)(0x42622514UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ6 *((volatile unsigned int*)(0x42622518UL)) -#define bFM4_INTREQ_IRQ009SEL_SELIRQ7 *((volatile unsigned int*)(0x4262251CUL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT0 *((volatile unsigned int*)(0x42622540UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT1 *((volatile unsigned int*)(0x42622544UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT2 *((volatile unsigned int*)(0x42622548UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT3 *((volatile unsigned int*)(0x4262254CUL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT4 *((volatile unsigned int*)(0x42622550UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT5 *((volatile unsigned int*)(0x42622554UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT6 *((volatile unsigned int*)(0x42622558UL)) -#define bFM4_INTREQ_IRQ009SEL_SELBIT7 *((volatile unsigned int*)(0x4262255CUL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ0 *((volatile unsigned int*)(0x42622580UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ1 *((volatile unsigned int*)(0x42622584UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ2 *((volatile unsigned int*)(0x42622588UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ3 *((volatile unsigned int*)(0x4262258CUL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ4 *((volatile unsigned int*)(0x42622590UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ5 *((volatile unsigned int*)(0x42622594UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ6 *((volatile unsigned int*)(0x42622598UL)) -#define bFM4_INTREQ_IRQ010SEL_SELIRQ7 *((volatile unsigned int*)(0x4262259CUL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT0 *((volatile unsigned int*)(0x426225C0UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT1 *((volatile unsigned int*)(0x426225C4UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT2 *((volatile unsigned int*)(0x426225C8UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT3 *((volatile unsigned int*)(0x426225CCUL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT4 *((volatile unsigned int*)(0x426225D0UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT5 *((volatile unsigned int*)(0x426225D4UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT6 *((volatile unsigned int*)(0x426225D8UL)) -#define bFM4_INTREQ_IRQ010SEL_SELBIT7 *((volatile unsigned int*)(0x426225DCUL)) -#define bFM4_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42624000UL)) -#define bFM4_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42624004UL)) -#define bFM4_INTREQ_IRQ000MON_FCSINT *((volatile unsigned int*)(0x42624080UL)) -#define bFM4_INTREQ_IRQ001MON_SWWDTINT *((volatile unsigned int*)(0x42624100UL)) -#define bFM4_INTREQ_IRQ002MON_LVDINT *((volatile unsigned int*)(0x42624180UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT0 *((volatile unsigned int*)(0x42624200UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT1 *((volatile unsigned int*)(0x42624204UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT2 *((volatile unsigned int*)(0x42624208UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT3 *((volatile unsigned int*)(0x4262420CUL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT4 *((volatile unsigned int*)(0x42624210UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT5 *((volatile unsigned int*)(0x42624214UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT6 *((volatile unsigned int*)(0x42624218UL)) -#define bFM4_INTREQ_IRQ003MON_IRQBIT7 *((volatile unsigned int*)(0x4262421CUL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT0 *((volatile unsigned int*)(0x42624280UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT1 *((volatile unsigned int*)(0x42624284UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT2 *((volatile unsigned int*)(0x42624288UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT3 *((volatile unsigned int*)(0x4262428CUL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT4 *((volatile unsigned int*)(0x42624290UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT5 *((volatile unsigned int*)(0x42624294UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT6 *((volatile unsigned int*)(0x42624298UL)) -#define bFM4_INTREQ_IRQ004MON_IRQBIT7 *((volatile unsigned int*)(0x4262429CUL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT0 *((volatile unsigned int*)(0x42624300UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT1 *((volatile unsigned int*)(0x42624304UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT2 *((volatile unsigned int*)(0x42624308UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT3 *((volatile unsigned int*)(0x4262430CUL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT4 *((volatile unsigned int*)(0x42624310UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT5 *((volatile unsigned int*)(0x42624314UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT6 *((volatile unsigned int*)(0x42624318UL)) -#define bFM4_INTREQ_IRQ005MON_IRQBIT7 *((volatile unsigned int*)(0x4262431CUL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT0 *((volatile unsigned int*)(0x42624380UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT1 *((volatile unsigned int*)(0x42624384UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT2 *((volatile unsigned int*)(0x42624388UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT3 *((volatile unsigned int*)(0x4262438CUL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT4 *((volatile unsigned int*)(0x42624390UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT5 *((volatile unsigned int*)(0x42624394UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT6 *((volatile unsigned int*)(0x42624398UL)) -#define bFM4_INTREQ_IRQ006MON_IRQBIT7 *((volatile unsigned int*)(0x4262439CUL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT0 *((volatile unsigned int*)(0x42624400UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT1 *((volatile unsigned int*)(0x42624404UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT2 *((volatile unsigned int*)(0x42624408UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT3 *((volatile unsigned int*)(0x4262440CUL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT4 *((volatile unsigned int*)(0x42624410UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT5 *((volatile unsigned int*)(0x42624414UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT6 *((volatile unsigned int*)(0x42624418UL)) -#define bFM4_INTREQ_IRQ007MON_IRQBIT7 *((volatile unsigned int*)(0x4262441CUL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT0 *((volatile unsigned int*)(0x42624480UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT1 *((volatile unsigned int*)(0x42624484UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT2 *((volatile unsigned int*)(0x42624488UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT3 *((volatile unsigned int*)(0x4262448CUL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT4 *((volatile unsigned int*)(0x42624490UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT5 *((volatile unsigned int*)(0x42624494UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT6 *((volatile unsigned int*)(0x42624498UL)) -#define bFM4_INTREQ_IRQ008MON_IRQBIT7 *((volatile unsigned int*)(0x4262449CUL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT0 *((volatile unsigned int*)(0x42624500UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT1 *((volatile unsigned int*)(0x42624504UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT2 *((volatile unsigned int*)(0x42624508UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT3 *((volatile unsigned int*)(0x4262450CUL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT4 *((volatile unsigned int*)(0x42624510UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT5 *((volatile unsigned int*)(0x42624514UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT6 *((volatile unsigned int*)(0x42624518UL)) -#define bFM4_INTREQ_IRQ009MON_IRQBIT7 *((volatile unsigned int*)(0x4262451CUL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT0 *((volatile unsigned int*)(0x42624580UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT1 *((volatile unsigned int*)(0x42624584UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT2 *((volatile unsigned int*)(0x42624588UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT3 *((volatile unsigned int*)(0x4262458CUL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT4 *((volatile unsigned int*)(0x42624590UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT5 *((volatile unsigned int*)(0x42624594UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT6 *((volatile unsigned int*)(0x42624598UL)) -#define bFM4_INTREQ_IRQ010MON_IRQBIT7 *((volatile unsigned int*)(0x4262459CUL)) -#define bFM4_INTREQ_IRQ011MON_EXTINT *((volatile unsigned int*)(0x42624600UL)) -#define bFM4_INTREQ_IRQ012MON_EXTINT *((volatile unsigned int*)(0x42624680UL)) -#define bFM4_INTREQ_IRQ013MON_EXTINT *((volatile unsigned int*)(0x42624700UL)) -#define bFM4_INTREQ_IRQ014MON_EXTINT *((volatile unsigned int*)(0x42624780UL)) -#define bFM4_INTREQ_IRQ015MON_EXTINT *((volatile unsigned int*)(0x42624800UL)) -#define bFM4_INTREQ_IRQ016MON_EXTINT *((volatile unsigned int*)(0x42624880UL)) -#define bFM4_INTREQ_IRQ017MON_EXTINT *((volatile unsigned int*)(0x42624900UL)) -#define bFM4_INTREQ_IRQ018MON_EXTINT *((volatile unsigned int*)(0x42624980UL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT0 *((volatile unsigned int*)(0x42624A00UL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT1 *((volatile unsigned int*)(0x42624A04UL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT2 *((volatile unsigned int*)(0x42624A08UL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT3 *((volatile unsigned int*)(0x42624A0CUL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT4 *((volatile unsigned int*)(0x42624A10UL)) -#define bFM4_INTREQ_IRQ019MON_QUDINT5 *((volatile unsigned int*)(0x42624A14UL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT0 *((volatile unsigned int*)(0x42624A80UL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT1 *((volatile unsigned int*)(0x42624A84UL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT2 *((volatile unsigned int*)(0x42624A88UL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT3 *((volatile unsigned int*)(0x42624A8CUL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT4 *((volatile unsigned int*)(0x42624A90UL)) -#define bFM4_INTREQ_IRQ020MON_QUDINT5 *((volatile unsigned int*)(0x42624A94UL)) -#define bFM4_INTREQ_IRQ021MON_WAVEINT0 *((volatile unsigned int*)(0x42624B00UL)) -#define bFM4_INTREQ_IRQ021MON_WAVEINT1 *((volatile unsigned int*)(0x42624B04UL)) -#define bFM4_INTREQ_IRQ021MON_WAVEINT2 *((volatile unsigned int*)(0x42624B08UL)) -#define bFM4_INTREQ_IRQ021MON_WAVEINT3 *((volatile unsigned int*)(0x42624B0CUL)) -#define bFM4_INTREQ_IRQ022MON_WAVEINT0 *((volatile unsigned int*)(0x42624B80UL)) -#define bFM4_INTREQ_IRQ022MON_WAVEINT1 *((volatile unsigned int*)(0x42624B84UL)) -#define bFM4_INTREQ_IRQ022MON_WAVEINT2 *((volatile unsigned int*)(0x42624B88UL)) -#define bFM4_INTREQ_IRQ022MON_WAVEINT3 *((volatile unsigned int*)(0x42624B8CUL)) -#define bFM4_INTREQ_IRQ023MON_WAVEINT0 *((volatile unsigned int*)(0x42624C00UL)) -#define bFM4_INTREQ_IRQ023MON_WAVEINT1 *((volatile unsigned int*)(0x42624C04UL)) -#define bFM4_INTREQ_IRQ023MON_WAVEINT2 *((volatile unsigned int*)(0x42624C08UL)) -#define bFM4_INTREQ_IRQ023MON_WAVEINT3 *((volatile unsigned int*)(0x42624C0CUL)) -#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42624C80UL)) -#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42624C84UL)) -#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42624C88UL)) -#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42624D00UL)) -#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42624D04UL)) -#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42624D08UL)) -#define bFM4_INTREQ_IRQ026MON_ICUINT0 *((volatile unsigned int*)(0x42624D80UL)) -#define bFM4_INTREQ_IRQ026MON_ICUINT1 *((volatile unsigned int*)(0x42624D84UL)) -#define bFM4_INTREQ_IRQ026MON_ICUINT2 *((volatile unsigned int*)(0x42624D88UL)) -#define bFM4_INTREQ_IRQ026MON_ICUINT3 *((volatile unsigned int*)(0x42624D8CUL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT0 *((volatile unsigned int*)(0x42624E00UL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT1 *((volatile unsigned int*)(0x42624E04UL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT2 *((volatile unsigned int*)(0x42624E08UL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT3 *((volatile unsigned int*)(0x42624E0CUL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT4 *((volatile unsigned int*)(0x42624E10UL)) -#define bFM4_INTREQ_IRQ027MON_OCUINT5 *((volatile unsigned int*)(0x42624E14UL)) -#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42624E80UL)) -#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42624E84UL)) -#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42624E88UL)) -#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42624F00UL)) -#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42624F04UL)) -#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42624F08UL)) -#define bFM4_INTREQ_IRQ030MON_ICUINT0 *((volatile unsigned int*)(0x42624F80UL)) -#define bFM4_INTREQ_IRQ030MON_ICUINT1 *((volatile unsigned int*)(0x42624F84UL)) -#define bFM4_INTREQ_IRQ030MON_ICUINT2 *((volatile unsigned int*)(0x42624F88UL)) -#define bFM4_INTREQ_IRQ030MON_ICUINT3 *((volatile unsigned int*)(0x42624F8CUL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT0 *((volatile unsigned int*)(0x42625000UL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT1 *((volatile unsigned int*)(0x42625004UL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT2 *((volatile unsigned int*)(0x42625008UL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT3 *((volatile unsigned int*)(0x4262500CUL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT4 *((volatile unsigned int*)(0x42625010UL)) -#define bFM4_INTREQ_IRQ031MON_OCUINT5 *((volatile unsigned int*)(0x42625014UL)) -#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile unsigned int*)(0x42625080UL)) -#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile unsigned int*)(0x42625084UL)) -#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile unsigned int*)(0x42625088UL)) -#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile unsigned int*)(0x42625100UL)) -#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile unsigned int*)(0x42625104UL)) -#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile unsigned int*)(0x42625108UL)) -#define bFM4_INTREQ_IRQ034MON_ICUINT0 *((volatile unsigned int*)(0x42625180UL)) -#define bFM4_INTREQ_IRQ034MON_ICUINT1 *((volatile unsigned int*)(0x42625184UL)) -#define bFM4_INTREQ_IRQ034MON_ICUINT2 *((volatile unsigned int*)(0x42625188UL)) -#define bFM4_INTREQ_IRQ034MON_ICUINT3 *((volatile unsigned int*)(0x4262518CUL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT0 *((volatile unsigned int*)(0x42625200UL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT1 *((volatile unsigned int*)(0x42625204UL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT2 *((volatile unsigned int*)(0x42625208UL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT3 *((volatile unsigned int*)(0x4262520CUL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT4 *((volatile unsigned int*)(0x42625210UL)) -#define bFM4_INTREQ_IRQ035MON_OCUINT5 *((volatile unsigned int*)(0x42625214UL)) -#define bFM4_INTREQ_IRQ036MON_PPGINT0 *((volatile unsigned int*)(0x42625280UL)) -#define bFM4_INTREQ_IRQ036MON_PPGINT1 *((volatile unsigned int*)(0x42625284UL)) -#define bFM4_INTREQ_IRQ036MON_PPGINT2 *((volatile unsigned int*)(0x42625288UL)) -#define bFM4_INTREQ_IRQ037MON_PPGINT0 *((volatile unsigned int*)(0x42625300UL)) -#define bFM4_INTREQ_IRQ037MON_PPGINT1 *((volatile unsigned int*)(0x42625304UL)) -#define bFM4_INTREQ_IRQ037MON_PPGINT2 *((volatile unsigned int*)(0x42625308UL)) -#define bFM4_INTREQ_IRQ038MON_PPGINT0 *((volatile unsigned int*)(0x42625380UL)) -#define bFM4_INTREQ_IRQ038MON_PPGINT1 *((volatile unsigned int*)(0x42625384UL)) -#define bFM4_INTREQ_IRQ038MON_PPGINT2 *((volatile unsigned int*)(0x42625388UL)) -#define bFM4_INTREQ_IRQ039MON_BTINT0 *((volatile unsigned int*)(0x42625400UL)) -#define bFM4_INTREQ_IRQ039MON_BTINT1 *((volatile unsigned int*)(0x42625404UL)) -#define bFM4_INTREQ_IRQ040MON_BTINT0 *((volatile unsigned int*)(0x42625480UL)) -#define bFM4_INTREQ_IRQ040MON_BTINT1 *((volatile unsigned int*)(0x42625484UL)) -#define bFM4_INTREQ_IRQ041MON_BTINT0 *((volatile unsigned int*)(0x42625500UL)) -#define bFM4_INTREQ_IRQ041MON_BTINT1 *((volatile unsigned int*)(0x42625504UL)) -#define bFM4_INTREQ_IRQ042MON_BTINT0 *((volatile unsigned int*)(0x42625580UL)) -#define bFM4_INTREQ_IRQ042MON_BTINT1 *((volatile unsigned int*)(0x42625584UL)) -#define bFM4_INTREQ_IRQ043MON_BTINT0 *((volatile unsigned int*)(0x42625600UL)) -#define bFM4_INTREQ_IRQ043MON_BTINT1 *((volatile unsigned int*)(0x42625604UL)) -#define bFM4_INTREQ_IRQ044MON_BTINT0 *((volatile unsigned int*)(0x42625680UL)) -#define bFM4_INTREQ_IRQ044MON_BTINT1 *((volatile unsigned int*)(0x42625684UL)) -#define bFM4_INTREQ_IRQ045MON_BTINT0 *((volatile unsigned int*)(0x42625700UL)) -#define bFM4_INTREQ_IRQ045MON_BTINT1 *((volatile unsigned int*)(0x42625704UL)) -#define bFM4_INTREQ_IRQ046MON_BTINT0 *((volatile unsigned int*)(0x42625780UL)) -#define bFM4_INTREQ_IRQ046MON_BTINT1 *((volatile unsigned int*)(0x42625784UL)) -#define bFM4_INTREQ_IRQ047MON_TIMINT1 *((volatile unsigned int*)(0x42625800UL)) -#define bFM4_INTREQ_IRQ047MON_TIMINT2 *((volatile unsigned int*)(0x42625804UL)) -#define bFM4_INTREQ_IRQ048MON_WCINT *((volatile unsigned int*)(0x42625880UL)) -#define bFM4_INTREQ_IRQ049MON_BMEMCS *((volatile unsigned int*)(0x42625900UL)) -#define bFM4_INTREQ_IRQ050MON_RTCINT *((volatile unsigned int*)(0x42625980UL)) -#define bFM4_INTREQ_IRQ051MON_EXTINT *((volatile unsigned int*)(0x42625A00UL)) -#define bFM4_INTREQ_IRQ052MON_EXTINT *((volatile unsigned int*)(0x42625A80UL)) -#define bFM4_INTREQ_IRQ053MON_EXTINT *((volatile unsigned int*)(0x42625B00UL)) -#define bFM4_INTREQ_IRQ054MON_EXTINT *((volatile unsigned int*)(0x42625B80UL)) -#define bFM4_INTREQ_IRQ055MON_EXTINT *((volatile unsigned int*)(0x42625C00UL)) -#define bFM4_INTREQ_IRQ056MON_EXTINT *((volatile unsigned int*)(0x42625C80UL)) -#define bFM4_INTREQ_IRQ057MON_EXTINT *((volatile unsigned int*)(0x42625D00UL)) -#define bFM4_INTREQ_IRQ058MON_EXTINT *((volatile unsigned int*)(0x42625D80UL)) -#define bFM4_INTREQ_IRQ059MON_MOSCINT *((volatile unsigned int*)(0x42625E00UL)) -#define bFM4_INTREQ_IRQ059MON_SOSCINT *((volatile unsigned int*)(0x42625E04UL)) -#define bFM4_INTREQ_IRQ059MON_MPLLINT *((volatile unsigned int*)(0x42625E08UL)) -#define bFM4_INTREQ_IRQ059MON_UPLLINT *((volatile unsigned int*)(0x42625E0CUL)) -#define bFM4_INTREQ_IRQ060MON_MFSRINT *((volatile unsigned int*)(0x42625E80UL)) -#define bFM4_INTREQ_IRQ061MON_MFSINT0 *((volatile unsigned int*)(0x42625F00UL)) -#define bFM4_INTREQ_IRQ061MON_MFSINT1 *((volatile unsigned int*)(0x42625F04UL)) -#define bFM4_INTREQ_IRQ062MON_MFSRINT *((volatile unsigned int*)(0x42625F80UL)) -#define bFM4_INTREQ_IRQ063MON_MFSINT0 *((volatile unsigned int*)(0x42626000UL)) -#define bFM4_INTREQ_IRQ063MON_MFSINT1 *((volatile unsigned int*)(0x42626004UL)) -#define bFM4_INTREQ_IRQ064MON_MFSRINT *((volatile unsigned int*)(0x42626080UL)) -#define bFM4_INTREQ_IRQ065MON_MFSINT0 *((volatile unsigned int*)(0x42626100UL)) -#define bFM4_INTREQ_IRQ065MON_MFSINT1 *((volatile unsigned int*)(0x42626104UL)) -#define bFM4_INTREQ_IRQ066MON_MFSRINT *((volatile unsigned int*)(0x42626180UL)) -#define bFM4_INTREQ_IRQ067MON_MFSINT0 *((volatile unsigned int*)(0x42626200UL)) -#define bFM4_INTREQ_IRQ067MON_MFSINT1 *((volatile unsigned int*)(0x42626204UL)) -#define bFM4_INTREQ_IRQ068MON_MFSRINT *((volatile unsigned int*)(0x42626280UL)) -#define bFM4_INTREQ_IRQ069MON_MFSINT0 *((volatile unsigned int*)(0x42626300UL)) -#define bFM4_INTREQ_IRQ069MON_MFSINT1 *((volatile unsigned int*)(0x42626304UL)) -#define bFM4_INTREQ_IRQ070MON_MFSRINT *((volatile unsigned int*)(0x42626380UL)) -#define bFM4_INTREQ_IRQ071MON_MFSINT0 *((volatile unsigned int*)(0x42626400UL)) -#define bFM4_INTREQ_IRQ071MON_MFSINT1 *((volatile unsigned int*)(0x42626404UL)) -#define bFM4_INTREQ_IRQ072MON_MFSRINT *((volatile unsigned int*)(0x42626480UL)) -#define bFM4_INTREQ_IRQ073MON_MFSINT0 *((volatile unsigned int*)(0x42626500UL)) -#define bFM4_INTREQ_IRQ073MON_MFSINT1 *((volatile unsigned int*)(0x42626504UL)) -#define bFM4_INTREQ_IRQ074MON_MFSRINT *((volatile unsigned int*)(0x42626580UL)) -#define bFM4_INTREQ_IRQ075MON_MFSINT0 *((volatile unsigned int*)(0x42626600UL)) -#define bFM4_INTREQ_IRQ075MON_MFSINT1 *((volatile unsigned int*)(0x42626604UL)) -#define bFM4_INTREQ_IRQ076MON_ADCINT0 *((volatile unsigned int*)(0x42626680UL)) -#define bFM4_INTREQ_IRQ076MON_ADCINT1 *((volatile unsigned int*)(0x42626684UL)) -#define bFM4_INTREQ_IRQ076MON_ADCINT2 *((volatile unsigned int*)(0x42626688UL)) -#define bFM4_INTREQ_IRQ076MON_ADCINT3 *((volatile unsigned int*)(0x4262668CUL)) -#define bFM4_INTREQ_IRQ076MON_ADCINT4 *((volatile unsigned int*)(0x42626690UL)) -#define bFM4_INTREQ_IRQ077MON_ADCINT0 *((volatile unsigned int*)(0x42626700UL)) -#define bFM4_INTREQ_IRQ077MON_ADCINT1 *((volatile unsigned int*)(0x42626704UL)) -#define bFM4_INTREQ_IRQ077MON_ADCINT2 *((volatile unsigned int*)(0x42626708UL)) -#define bFM4_INTREQ_IRQ077MON_ADCINT3 *((volatile unsigned int*)(0x4262670CUL)) -#define bFM4_INTREQ_IRQ077MON_ADCINT4 *((volatile unsigned int*)(0x42626710UL)) -#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile unsigned int*)(0x42626780UL)) -#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile unsigned int*)(0x42626784UL)) -#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile unsigned int*)(0x42626788UL)) -#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile unsigned int*)(0x4262678CUL)) -#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile unsigned int*)(0x42626790UL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT0 *((volatile unsigned int*)(0x42626800UL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT1 *((volatile unsigned int*)(0x42626804UL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT2 *((volatile unsigned int*)(0x42626808UL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT3 *((volatile unsigned int*)(0x4262680CUL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT4 *((volatile unsigned int*)(0x42626810UL)) -#define bFM4_INTREQ_IRQ079MON_USB_INT5 *((volatile unsigned int*)(0x42626814UL)) -#define bFM4_INTREQ_IRQ080MON_CANINT *((volatile unsigned int*)(0x42626880UL)) -#define bFM4_INTREQ_IRQ081MON_CANINT *((volatile unsigned int*)(0x42626900UL)) -#define bFM4_INTREQ_IRQ082MON_MACSBD *((volatile unsigned int*)(0x42626980UL)) -#define bFM4_INTREQ_IRQ082MON_MACPMT *((volatile unsigned int*)(0x42626984UL)) -#define bFM4_INTREQ_IRQ082MON_MACLPI *((volatile unsigned int*)(0x42626988UL)) -#define bFM4_INTREQ_IRQ083MON_DMACINT *((volatile unsigned int*)(0x42626A00UL)) -#define bFM4_INTREQ_IRQ084MON_DMACINT *((volatile unsigned int*)(0x42626A80UL)) -#define bFM4_INTREQ_IRQ085MON_DMACINT *((volatile unsigned int*)(0x42626B00UL)) -#define bFM4_INTREQ_IRQ086MON_DMACINT *((volatile unsigned int*)(0x42626B80UL)) -#define bFM4_INTREQ_IRQ087MON_DMACINT *((volatile unsigned int*)(0x42626C00UL)) -#define bFM4_INTREQ_IRQ088MON_DMACINT *((volatile unsigned int*)(0x42626C80UL)) -#define bFM4_INTREQ_IRQ089MON_DMACINT *((volatile unsigned int*)(0x42626D00UL)) -#define bFM4_INTREQ_IRQ090MON_DMACINT *((volatile unsigned int*)(0x42626D80UL)) -#define bFM4_INTREQ_IRQ091MON_DSTCINT0 *((volatile unsigned int*)(0x42626E00UL)) -#define bFM4_INTREQ_IRQ091MON_DSTCINT1 *((volatile unsigned int*)(0x42626E04UL)) -#define bFM4_INTREQ_IRQ092MON_EXTINT0 *((volatile unsigned int*)(0x42626E80UL)) -#define bFM4_INTREQ_IRQ092MON_EXTINT1 *((volatile unsigned int*)(0x42626E84UL)) -#define bFM4_INTREQ_IRQ092MON_EXTINT2 *((volatile unsigned int*)(0x42626E88UL)) -#define bFM4_INTREQ_IRQ092MON_EXTINT3 *((volatile unsigned int*)(0x42626E8CUL)) -#define bFM4_INTREQ_IRQ093MON_EXTINT0 *((volatile unsigned int*)(0x42626F00UL)) -#define bFM4_INTREQ_IRQ093MON_EXTINT1 *((volatile unsigned int*)(0x42626F04UL)) -#define bFM4_INTREQ_IRQ093MON_EXTINT2 *((volatile unsigned int*)(0x42626F08UL)) -#define bFM4_INTREQ_IRQ093MON_EXTINT3 *((volatile unsigned int*)(0x42626F0CUL)) -#define bFM4_INTREQ_IRQ094MON_EXTINT0 *((volatile unsigned int*)(0x42626F80UL)) -#define bFM4_INTREQ_IRQ094MON_EXTINT1 *((volatile unsigned int*)(0x42626F84UL)) -#define bFM4_INTREQ_IRQ094MON_EXTINT2 *((volatile unsigned int*)(0x42626F88UL)) -#define bFM4_INTREQ_IRQ094MON_EXTINT3 *((volatile unsigned int*)(0x42626F8CUL)) -#define bFM4_INTREQ_IRQ095MON_EXTINT0 *((volatile unsigned int*)(0x42627000UL)) -#define bFM4_INTREQ_IRQ095MON_EXTINT1 *((volatile unsigned int*)(0x42627004UL)) -#define bFM4_INTREQ_IRQ095MON_EXTINT2 *((volatile unsigned int*)(0x42627008UL)) -#define bFM4_INTREQ_IRQ095MON_EXTINT3 *((volatile unsigned int*)(0x4262700CUL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT0 *((volatile unsigned int*)(0x42627080UL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT1 *((volatile unsigned int*)(0x42627084UL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT2 *((volatile unsigned int*)(0x42627088UL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT3 *((volatile unsigned int*)(0x4262708CUL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT4 *((volatile unsigned int*)(0x42627090UL)) -#define bFM4_INTREQ_IRQ096MON_QUDINT5 *((volatile unsigned int*)(0x42627094UL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT0 *((volatile unsigned int*)(0x42627100UL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT1 *((volatile unsigned int*)(0x42627104UL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT2 *((volatile unsigned int*)(0x42627108UL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT3 *((volatile unsigned int*)(0x4262710CUL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT4 *((volatile unsigned int*)(0x42627110UL)) -#define bFM4_INTREQ_IRQ097MON_QUDINT5 *((volatile unsigned int*)(0x42627114UL)) -#define bFM4_INTREQ_IRQ098MON_BTINT0 *((volatile unsigned int*)(0x42627180UL)) -#define bFM4_INTREQ_IRQ098MON_BTINT1 *((volatile unsigned int*)(0x42627184UL)) -#define bFM4_INTREQ_IRQ099MON_BTINT0 *((volatile unsigned int*)(0x42627200UL)) -#define bFM4_INTREQ_IRQ099MON_BTINT1 *((volatile unsigned int*)(0x42627204UL)) -#define bFM4_INTREQ_IRQ100MON_BTINT0 *((volatile unsigned int*)(0x42627280UL)) -#define bFM4_INTREQ_IRQ100MON_BTINT1 *((volatile unsigned int*)(0x42627284UL)) -#define bFM4_INTREQ_IRQ101MON_BTINT0 *((volatile unsigned int*)(0x42627300UL)) -#define bFM4_INTREQ_IRQ101MON_BTINT1 *((volatile unsigned int*)(0x42627304UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT0 *((volatile unsigned int*)(0x42627380UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT1 *((volatile unsigned int*)(0x42627384UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT2 *((volatile unsigned int*)(0x42627388UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT3 *((volatile unsigned int*)(0x4262738CUL)) -#define bFM4_INTREQ_IRQ102MON_BTINT4 *((volatile unsigned int*)(0x42627390UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT5 *((volatile unsigned int*)(0x42627394UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT6 *((volatile unsigned int*)(0x42627398UL)) -#define bFM4_INTREQ_IRQ102MON_BTINT7 *((volatile unsigned int*)(0x4262739CUL)) -#define bFM4_INTREQ_IRQ103MON_MFSRINT *((volatile unsigned int*)(0x42627400UL)) -#define bFM4_INTREQ_IRQ104MON_MFSINT0 *((volatile unsigned int*)(0x42627480UL)) -#define bFM4_INTREQ_IRQ104MON_MFSINT1 *((volatile unsigned int*)(0x42627484UL)) -#define bFM4_INTREQ_IRQ105MON_MFSRINT *((volatile unsigned int*)(0x42627500UL)) -#define bFM4_INTREQ_IRQ106MON_MFSINT0 *((volatile unsigned int*)(0x42627580UL)) -#define bFM4_INTREQ_IRQ106MON_MFSINT1 *((volatile unsigned int*)(0x42627584UL)) -#define bFM4_INTREQ_IRQ107MON_MFSRINT *((volatile unsigned int*)(0x42627600UL)) -#define bFM4_INTREQ_IRQ108MON_MFSINT0 *((volatile unsigned int*)(0x42627680UL)) -#define bFM4_INTREQ_IRQ108MON_MFSINT1 *((volatile unsigned int*)(0x42627684UL)) -#define bFM4_INTREQ_IRQ109MON_MFSRINT *((volatile unsigned int*)(0x42627700UL)) -#define bFM4_INTREQ_IRQ110MON_MFSINT0 *((volatile unsigned int*)(0x42627780UL)) -#define bFM4_INTREQ_IRQ110MON_MFSINT1 *((volatile unsigned int*)(0x42627784UL)) -#define bFM4_INTREQ_IRQ111MON_ADCINT0 *((volatile unsigned int*)(0x42627800UL)) -#define bFM4_INTREQ_IRQ111MON_ADCINT1 *((volatile unsigned int*)(0x42627804UL)) -#define bFM4_INTREQ_IRQ111MON_ADCINT2 *((volatile unsigned int*)(0x42627808UL)) -#define bFM4_INTREQ_IRQ111MON_ADCINT3 *((volatile unsigned int*)(0x4262780CUL)) -#define bFM4_INTREQ_IRQ111MON_ADCINT4 *((volatile unsigned int*)(0x42627810UL)) -#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile unsigned int*)(0x42627900UL)) -#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile unsigned int*)(0x42627904UL)) -#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile unsigned int*)(0x42627908UL)) -#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile unsigned int*)(0x4262790CUL)) -#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile unsigned int*)(0x42627910UL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT0 *((volatile unsigned int*)(0x42627980UL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT1 *((volatile unsigned int*)(0x42627984UL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT2 *((volatile unsigned int*)(0x42627988UL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT3 *((volatile unsigned int*)(0x4262798CUL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT4 *((volatile unsigned int*)(0x42627990UL)) -#define bFM4_INTREQ_IRQ114MON_USB_INT5 *((volatile unsigned int*)(0x42627994UL)) -#define bFM4_INTREQ_IRQ118MON_SDINT0 *((volatile unsigned int*)(0x42627B80UL)) -#define bFM4_INTREQ_IRQ118MON_SDINT1 *((volatile unsigned int*)(0x42627B84UL)) -#define bFM4_INTREQ_IRQ119MON_FLINT *((volatile unsigned int*)(0x42627C00UL)) -#define bFM4_INTREQ_IRQ120MON_MFSRINT *((volatile unsigned int*)(0x42627C80UL)) -#define bFM4_INTREQ_IRQ121MON_MFSINT0 *((volatile unsigned int*)(0x42627D00UL)) -#define bFM4_INTREQ_IRQ121MON_MFSINT1 *((volatile unsigned int*)(0x42627D04UL)) -#define bFM4_INTREQ_IRQ122MON_MFSRINT *((volatile unsigned int*)(0x42627D80UL)) -#define bFM4_INTREQ_IRQ123MON_MFSINT0 *((volatile unsigned int*)(0x42627E00UL)) -#define bFM4_INTREQ_IRQ123MON_MFSINT1 *((volatile unsigned int*)(0x42627E04UL)) -#define bFM4_INTREQ_IRQ124MON_MFSRINT *((volatile unsigned int*)(0x42627E80UL)) -#define bFM4_INTREQ_IRQ125MON_MFSINT0 *((volatile unsigned int*)(0x42627F00UL)) -#define bFM4_INTREQ_IRQ125MON_MFSINT1 *((volatile unsigned int*)(0x42627F04UL)) -#define bFM4_INTREQ_IRQ126MON_MFSRINT *((volatile unsigned int*)(0x42627F80UL)) -#define bFM4_INTREQ_IRQ127MON_MFSINT0 *((volatile unsigned int*)(0x42628000UL)) -#define bFM4_INTREQ_IRQ127MON_MFSINT1 *((volatile unsigned int*)(0x42628004UL)) - -/* 12-bit DAC unit 0 registers */ -#define bFM4_DAC0_DACR_DAE *((volatile unsigned int*)(0x42660000UL)) -#define bFM4_DAC0_DACR_DRDY *((volatile unsigned int*)(0x42660004UL)) -#define bFM4_DAC0_DACR_DAC10 *((volatile unsigned int*)(0x42660010UL)) -#define bFM4_DAC0_DACR_DDAS *((volatile unsigned int*)(0x42660014UL)) -#define bFM4_DAC0_DADR_DA0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM4_DAC0_DADR_DA1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM4_DAC0_DADR_DA2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM4_DAC0_DADR_DA3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM4_DAC0_DADR_DA4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM4_DAC0_DADR_DA5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM4_DAC0_DADR_DA6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM4_DAC0_DADR_DA7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM4_DAC0_DADR_DA8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM4_DAC0_DADR_DA9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM4_DAC0_DADR_DA10 *((volatile unsigned int*)(0x426600A8UL)) -#define bFM4_DAC0_DADR_DA11 *((volatile unsigned int*)(0x426600ACUL)) - -/* 12-bit DAC unit 1 registers */ -#define bFM4_DAC1_DACR_DAE *((volatile unsigned int*)(0x42660100UL)) -#define bFM4_DAC1_DACR_DRDY *((volatile unsigned int*)(0x42660104UL)) -#define bFM4_DAC1_DACR_DAC10 *((volatile unsigned int*)(0x42660110UL)) -#define bFM4_DAC1_DACR_DDAS *((volatile unsigned int*)(0x42660114UL)) -#define bFM4_DAC1_DADR_DA0 *((volatile unsigned int*)(0x42660180UL)) -#define bFM4_DAC1_DADR_DA1 *((volatile unsigned int*)(0x42660184UL)) -#define bFM4_DAC1_DADR_DA2 *((volatile unsigned int*)(0x42660188UL)) -#define bFM4_DAC1_DADR_DA3 *((volatile unsigned int*)(0x4266018CUL)) -#define bFM4_DAC1_DADR_DA4 *((volatile unsigned int*)(0x42660190UL)) -#define bFM4_DAC1_DADR_DA5 *((volatile unsigned int*)(0x42660194UL)) -#define bFM4_DAC1_DADR_DA6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM4_DAC1_DADR_DA7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM4_DAC1_DADR_DA8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM4_DAC1_DADR_DA9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM4_DAC1_DADR_DA10 *((volatile unsigned int*)(0x426601A8UL)) -#define bFM4_DAC1_DADR_DA11 *((volatile unsigned int*)(0x426601ACUL)) - -/* General purpose I/O registers */ -#define bFM4_GPIO_PFR0_P00 *((volatile unsigned int*)(0x42DE0000UL)) -#define bFM4_GPIO_PFR0_P01 *((volatile unsigned int*)(0x42DE0004UL)) -#define bFM4_GPIO_PFR0_P02 *((volatile unsigned int*)(0x42DE0008UL)) -#define bFM4_GPIO_PFR0_P03 *((volatile unsigned int*)(0x42DE000CUL)) -#define bFM4_GPIO_PFR0_P04 *((volatile unsigned int*)(0x42DE0010UL)) -#define bFM4_GPIO_PFR0_P05 *((volatile unsigned int*)(0x42DE0014UL)) -#define bFM4_GPIO_PFR0_P06 *((volatile unsigned int*)(0x42DE0018UL)) -#define bFM4_GPIO_PFR0_P07 *((volatile unsigned int*)(0x42DE001CUL)) -#define bFM4_GPIO_PFR0_P08 *((volatile unsigned int*)(0x42DE0020UL)) -#define bFM4_GPIO_PFR0_P09 *((volatile unsigned int*)(0x42DE0024UL)) -#define bFM4_GPIO_PFR0_P0A *((volatile unsigned int*)(0x42DE0028UL)) -#define bFM4_GPIO_PFR0_P0B *((volatile unsigned int*)(0x42DE002CUL)) -#define bFM4_GPIO_PFR0_P0C *((volatile unsigned int*)(0x42DE0030UL)) -#define bFM4_GPIO_PFR0_P0D *((volatile unsigned int*)(0x42DE0034UL)) -#define bFM4_GPIO_PFR0_P0E *((volatile unsigned int*)(0x42DE0038UL)) -#define bFM4_GPIO_PFR1_P10 *((volatile unsigned int*)(0x42DE0080UL)) -#define bFM4_GPIO_PFR1_P11 *((volatile unsigned int*)(0x42DE0084UL)) -#define bFM4_GPIO_PFR1_P12 *((volatile unsigned int*)(0x42DE0088UL)) -#define bFM4_GPIO_PFR1_P13 *((volatile unsigned int*)(0x42DE008CUL)) -#define bFM4_GPIO_PFR1_P14 *((volatile unsigned int*)(0x42DE0090UL)) -#define bFM4_GPIO_PFR1_P15 *((volatile unsigned int*)(0x42DE0094UL)) -#define bFM4_GPIO_PFR1_P16 *((volatile unsigned int*)(0x42DE0098UL)) -#define bFM4_GPIO_PFR1_P17 *((volatile unsigned int*)(0x42DE009CUL)) -#define bFM4_GPIO_PFR1_P18 *((volatile unsigned int*)(0x42DE00A0UL)) -#define bFM4_GPIO_PFR1_P19 *((volatile unsigned int*)(0x42DE00A4UL)) -#define bFM4_GPIO_PFR1_P1A *((volatile unsigned int*)(0x42DE00A8UL)) -#define bFM4_GPIO_PFR1_P1B *((volatile unsigned int*)(0x42DE00ACUL)) -#define bFM4_GPIO_PFR1_P1C *((volatile unsigned int*)(0x42DE00B0UL)) -#define bFM4_GPIO_PFR1_P1D *((volatile unsigned int*)(0x42DE00B4UL)) -#define bFM4_GPIO_PFR1_P1E *((volatile unsigned int*)(0x42DE00B8UL)) -#define bFM4_GPIO_PFR1_P1F *((volatile unsigned int*)(0x42DE00BCUL)) -#define bFM4_GPIO_PFR2_P20 *((volatile unsigned int*)(0x42DE0100UL)) -#define bFM4_GPIO_PFR2_P21 *((volatile unsigned int*)(0x42DE0104UL)) -#define bFM4_GPIO_PFR2_P22 *((volatile unsigned int*)(0x42DE0108UL)) -#define bFM4_GPIO_PFR2_P23 *((volatile unsigned int*)(0x42DE010CUL)) -#define bFM4_GPIO_PFR2_P24 *((volatile unsigned int*)(0x42DE0110UL)) -#define bFM4_GPIO_PFR2_P25 *((volatile unsigned int*)(0x42DE0114UL)) -#define bFM4_GPIO_PFR2_P26 *((volatile unsigned int*)(0x42DE0118UL)) -#define bFM4_GPIO_PFR2_P27 *((volatile unsigned int*)(0x42DE011CUL)) -#define bFM4_GPIO_PFR3_P30 *((volatile unsigned int*)(0x42DE0180UL)) -#define bFM4_GPIO_PFR3_P31 *((volatile unsigned int*)(0x42DE0184UL)) -#define bFM4_GPIO_PFR3_P32 *((volatile unsigned int*)(0x42DE0188UL)) -#define bFM4_GPIO_PFR3_P33 *((volatile unsigned int*)(0x42DE018CUL)) -#define bFM4_GPIO_PFR3_P34 *((volatile unsigned int*)(0x42DE0190UL)) -#define bFM4_GPIO_PFR3_P35 *((volatile unsigned int*)(0x42DE0194UL)) -#define bFM4_GPIO_PFR3_P36 *((volatile unsigned int*)(0x42DE0198UL)) -#define bFM4_GPIO_PFR3_P37 *((volatile unsigned int*)(0x42DE019CUL)) -#define bFM4_GPIO_PFR3_P38 *((volatile unsigned int*)(0x42DE01A0UL)) -#define bFM4_GPIO_PFR3_P39 *((volatile unsigned int*)(0x42DE01A4UL)) -#define bFM4_GPIO_PFR3_P3A *((volatile unsigned int*)(0x42DE01A8UL)) -#define bFM4_GPIO_PFR3_P3B *((volatile unsigned int*)(0x42DE01ACUL)) -#define bFM4_GPIO_PFR3_P3C *((volatile unsigned int*)(0x42DE01B0UL)) -#define bFM4_GPIO_PFR3_P3D *((volatile unsigned int*)(0x42DE01B4UL)) -#define bFM4_GPIO_PFR3_P3E *((volatile unsigned int*)(0x42DE01B8UL)) -#define bFM4_GPIO_PFR3_P3F *((volatile unsigned int*)(0x42DE01BCUL)) -#define bFM4_GPIO_PFR4_P40 *((volatile unsigned int*)(0x42DE0200UL)) -#define bFM4_GPIO_PFR4_P41 *((volatile unsigned int*)(0x42DE0204UL)) -#define bFM4_GPIO_PFR4_P42 *((volatile unsigned int*)(0x42DE0208UL)) -#define bFM4_GPIO_PFR4_P43 *((volatile unsigned int*)(0x42DE020CUL)) -#define bFM4_GPIO_PFR4_P44 *((volatile unsigned int*)(0x42DE0210UL)) -#define bFM4_GPIO_PFR4_P45 *((volatile unsigned int*)(0x42DE0214UL)) -#define bFM4_GPIO_PFR4_P46 *((volatile unsigned int*)(0x42DE0218UL)) -#define bFM4_GPIO_PFR4_P47 *((volatile unsigned int*)(0x42DE021CUL)) -#define bFM4_GPIO_PFR4_P48 *((volatile unsigned int*)(0x42DE0220UL)) -#define bFM4_GPIO_PFR4_P49 *((volatile unsigned int*)(0x42DE0224UL)) -#define bFM4_GPIO_PFR4_P4A *((volatile unsigned int*)(0x42DE0228UL)) -#define bFM4_GPIO_PFR4_P4B *((volatile unsigned int*)(0x42DE022CUL)) -#define bFM4_GPIO_PFR4_P4C *((volatile unsigned int*)(0x42DE0230UL)) -#define bFM4_GPIO_PFR4_P4D *((volatile unsigned int*)(0x42DE0234UL)) -#define bFM4_GPIO_PFR4_P4E *((volatile unsigned int*)(0x42DE0238UL)) -#define bFM4_GPIO_PFR5_P50 *((volatile unsigned int*)(0x42DE0280UL)) -#define bFM4_GPIO_PFR5_P51 *((volatile unsigned int*)(0x42DE0284UL)) -#define bFM4_GPIO_PFR5_P52 *((volatile unsigned int*)(0x42DE0288UL)) -#define bFM4_GPIO_PFR5_P53 *((volatile unsigned int*)(0x42DE028CUL)) -#define bFM4_GPIO_PFR5_P54 *((volatile unsigned int*)(0x42DE0290UL)) -#define bFM4_GPIO_PFR5_P55 *((volatile unsigned int*)(0x42DE0294UL)) -#define bFM4_GPIO_PFR5_P56 *((volatile unsigned int*)(0x42DE0298UL)) -#define bFM4_GPIO_PFR5_P57 *((volatile unsigned int*)(0x42DE029CUL)) -#define bFM4_GPIO_PFR5_P58 *((volatile unsigned int*)(0x42DE02A0UL)) -#define bFM4_GPIO_PFR5_P59 *((volatile unsigned int*)(0x42DE02A4UL)) -#define bFM4_GPIO_PFR5_P5A *((volatile unsigned int*)(0x42DE02A8UL)) -#define bFM4_GPIO_PFR5_P5B *((volatile unsigned int*)(0x42DE02ACUL)) -#define bFM4_GPIO_PFR6_P60 *((volatile unsigned int*)(0x42DE0300UL)) -#define bFM4_GPIO_PFR6_P61 *((volatile unsigned int*)(0x42DE0304UL)) -#define bFM4_GPIO_PFR6_P62 *((volatile unsigned int*)(0x42DE0308UL)) -#define bFM4_GPIO_PFR6_P63 *((volatile unsigned int*)(0x42DE030CUL)) -#define bFM4_GPIO_PFR6_P64 *((volatile unsigned int*)(0x42DE0310UL)) -#define bFM4_GPIO_PFR6_P65 *((volatile unsigned int*)(0x42DE0314UL)) -#define bFM4_GPIO_PFR6_P66 *((volatile unsigned int*)(0x42DE0318UL)) -#define bFM4_GPIO_PFR6_P67 *((volatile unsigned int*)(0x42DE031CUL)) -#define bFM4_GPIO_PFR6_P68 *((volatile unsigned int*)(0x42DE0320UL)) -#define bFM4_GPIO_PFR7_P70 *((volatile unsigned int*)(0x42DE0380UL)) -#define bFM4_GPIO_PFR7_P71 *((volatile unsigned int*)(0x42DE0384UL)) -#define bFM4_GPIO_PFR7_P72 *((volatile unsigned int*)(0x42DE0388UL)) -#define bFM4_GPIO_PFR7_P73 *((volatile unsigned int*)(0x42DE038CUL)) -#define bFM4_GPIO_PFR7_P74 *((volatile unsigned int*)(0x42DE0390UL)) -#define bFM4_GPIO_PFR8_P80 *((volatile unsigned int*)(0x42DE0400UL)) -#define bFM4_GPIO_PFR8_P81 *((volatile unsigned int*)(0x42DE0404UL)) -#define bFM4_GPIO_PFRE_PE0 *((volatile unsigned int*)(0x42DE0700UL)) -#define bFM4_GPIO_PFRE_PE2 *((volatile unsigned int*)(0x42DE0708UL)) -#define bFM4_GPIO_PFRE_PE3 *((volatile unsigned int*)(0x42DE070CUL)) -#define bFM4_GPIO_PCR0_P00 *((volatile unsigned int*)(0x42DE2000UL)) -#define bFM4_GPIO_PCR0_P01 *((volatile unsigned int*)(0x42DE2004UL)) -#define bFM4_GPIO_PCR0_P02 *((volatile unsigned int*)(0x42DE2008UL)) -#define bFM4_GPIO_PCR0_P03 *((volatile unsigned int*)(0x42DE200CUL)) -#define bFM4_GPIO_PCR0_P04 *((volatile unsigned int*)(0x42DE2010UL)) -#define bFM4_GPIO_PCR0_P05 *((volatile unsigned int*)(0x42DE2014UL)) -#define bFM4_GPIO_PCR0_P06 *((volatile unsigned int*)(0x42DE2018UL)) -#define bFM4_GPIO_PCR0_P07 *((volatile unsigned int*)(0x42DE201CUL)) -#define bFM4_GPIO_PCR0_P08 *((volatile unsigned int*)(0x42DE2020UL)) -#define bFM4_GPIO_PCR0_P09 *((volatile unsigned int*)(0x42DE2024UL)) -#define bFM4_GPIO_PCR0_P0A *((volatile unsigned int*)(0x42DE2028UL)) -#define bFM4_GPIO_PCR0_P0B *((volatile unsigned int*)(0x42DE202CUL)) -#define bFM4_GPIO_PCR0_P0C *((volatile unsigned int*)(0x42DE2030UL)) -#define bFM4_GPIO_PCR0_P0D *((volatile unsigned int*)(0x42DE2034UL)) -#define bFM4_GPIO_PCR0_P0E *((volatile unsigned int*)(0x42DE2038UL)) -#define bFM4_GPIO_PCR1_P10 *((volatile unsigned int*)(0x42DE2080UL)) -#define bFM4_GPIO_PCR1_P11 *((volatile unsigned int*)(0x42DE2084UL)) -#define bFM4_GPIO_PCR1_P12 *((volatile unsigned int*)(0x42DE2088UL)) -#define bFM4_GPIO_PCR1_P13 *((volatile unsigned int*)(0x42DE208CUL)) -#define bFM4_GPIO_PCR1_P14 *((volatile unsigned int*)(0x42DE2090UL)) -#define bFM4_GPIO_PCR1_P15 *((volatile unsigned int*)(0x42DE2094UL)) -#define bFM4_GPIO_PCR1_P16 *((volatile unsigned int*)(0x42DE2098UL)) -#define bFM4_GPIO_PCR1_P17 *((volatile unsigned int*)(0x42DE209CUL)) -#define bFM4_GPIO_PCR1_P18 *((volatile unsigned int*)(0x42DE20A0UL)) -#define bFM4_GPIO_PCR1_P19 *((volatile unsigned int*)(0x42DE20A4UL)) -#define bFM4_GPIO_PCR1_P1A *((volatile unsigned int*)(0x42DE20A8UL)) -#define bFM4_GPIO_PCR1_P1B *((volatile unsigned int*)(0x42DE20ACUL)) -#define bFM4_GPIO_PCR1_P1C *((volatile unsigned int*)(0x42DE20B0UL)) -#define bFM4_GPIO_PCR1_P1D *((volatile unsigned int*)(0x42DE20B4UL)) -#define bFM4_GPIO_PCR1_P1E *((volatile unsigned int*)(0x42DE20B8UL)) -#define bFM4_GPIO_PCR1_P1F *((volatile unsigned int*)(0x42DE20BCUL)) -#define bFM4_GPIO_PCR2_P20 *((volatile unsigned int*)(0x42DE2100UL)) -#define bFM4_GPIO_PCR2_P21 *((volatile unsigned int*)(0x42DE2104UL)) -#define bFM4_GPIO_PCR2_P22 *((volatile unsigned int*)(0x42DE2108UL)) -#define bFM4_GPIO_PCR2_P23 *((volatile unsigned int*)(0x42DE210CUL)) -#define bFM4_GPIO_PCR2_P24 *((volatile unsigned int*)(0x42DE2110UL)) -#define bFM4_GPIO_PCR2_P25 *((volatile unsigned int*)(0x42DE2114UL)) -#define bFM4_GPIO_PCR2_P26 *((volatile unsigned int*)(0x42DE2118UL)) -#define bFM4_GPIO_PCR2_P27 *((volatile unsigned int*)(0x42DE211CUL)) -#define bFM4_GPIO_PCR3_P30 *((volatile unsigned int*)(0x42DE2180UL)) -#define bFM4_GPIO_PCR3_P31 *((volatile unsigned int*)(0x42DE2184UL)) -#define bFM4_GPIO_PCR3_P32 *((volatile unsigned int*)(0x42DE2188UL)) -#define bFM4_GPIO_PCR3_P33 *((volatile unsigned int*)(0x42DE218CUL)) -#define bFM4_GPIO_PCR3_P34 *((volatile unsigned int*)(0x42DE2190UL)) -#define bFM4_GPIO_PCR3_P35 *((volatile unsigned int*)(0x42DE2194UL)) -#define bFM4_GPIO_PCR3_P36 *((volatile unsigned int*)(0x42DE2198UL)) -#define bFM4_GPIO_PCR3_P37 *((volatile unsigned int*)(0x42DE219CUL)) -#define bFM4_GPIO_PCR3_P38 *((volatile unsigned int*)(0x42DE21A0UL)) -#define bFM4_GPIO_PCR3_P39 *((volatile unsigned int*)(0x42DE21A4UL)) -#define bFM4_GPIO_PCR3_P3A *((volatile unsigned int*)(0x42DE21A8UL)) -#define bFM4_GPIO_PCR3_P3B *((volatile unsigned int*)(0x42DE21ACUL)) -#define bFM4_GPIO_PCR3_P3C *((volatile unsigned int*)(0x42DE21B0UL)) -#define bFM4_GPIO_PCR3_P3D *((volatile unsigned int*)(0x42DE21B4UL)) -#define bFM4_GPIO_PCR3_P3E *((volatile unsigned int*)(0x42DE21B8UL)) -#define bFM4_GPIO_PCR3_P3F *((volatile unsigned int*)(0x42DE21BCUL)) -#define bFM4_GPIO_PCR4_P40 *((volatile unsigned int*)(0x42DE2200UL)) -#define bFM4_GPIO_PCR4_P41 *((volatile unsigned int*)(0x42DE2204UL)) -#define bFM4_GPIO_PCR4_P42 *((volatile unsigned int*)(0x42DE2208UL)) -#define bFM4_GPIO_PCR4_P43 *((volatile unsigned int*)(0x42DE220CUL)) -#define bFM4_GPIO_PCR4_P44 *((volatile unsigned int*)(0x42DE2210UL)) -#define bFM4_GPIO_PCR4_P45 *((volatile unsigned int*)(0x42DE2214UL)) -#define bFM4_GPIO_PCR4_P46 *((volatile unsigned int*)(0x42DE2218UL)) -#define bFM4_GPIO_PCR4_P47 *((volatile unsigned int*)(0x42DE221CUL)) -#define bFM4_GPIO_PCR4_P48 *((volatile unsigned int*)(0x42DE2220UL)) -#define bFM4_GPIO_PCR4_P49 *((volatile unsigned int*)(0x42DE2224UL)) -#define bFM4_GPIO_PCR4_P4A *((volatile unsigned int*)(0x42DE2228UL)) -#define bFM4_GPIO_PCR4_P4B *((volatile unsigned int*)(0x42DE222CUL)) -#define bFM4_GPIO_PCR4_P4C *((volatile unsigned int*)(0x42DE2230UL)) -#define bFM4_GPIO_PCR4_P4D *((volatile unsigned int*)(0x42DE2234UL)) -#define bFM4_GPIO_PCR4_P4E *((volatile unsigned int*)(0x42DE2238UL)) -#define bFM4_GPIO_PCR5_P50 *((volatile unsigned int*)(0x42DE2280UL)) -#define bFM4_GPIO_PCR5_P51 *((volatile unsigned int*)(0x42DE2284UL)) -#define bFM4_GPIO_PCR5_P52 *((volatile unsigned int*)(0x42DE2288UL)) -#define bFM4_GPIO_PCR5_P53 *((volatile unsigned int*)(0x42DE228CUL)) -#define bFM4_GPIO_PCR5_P54 *((volatile unsigned int*)(0x42DE2290UL)) -#define bFM4_GPIO_PCR5_P55 *((volatile unsigned int*)(0x42DE2294UL)) -#define bFM4_GPIO_PCR5_P56 *((volatile unsigned int*)(0x42DE2298UL)) -#define bFM4_GPIO_PCR5_P57 *((volatile unsigned int*)(0x42DE229CUL)) -#define bFM4_GPIO_PCR5_P58 *((volatile unsigned int*)(0x42DE22A0UL)) -#define bFM4_GPIO_PCR5_P59 *((volatile unsigned int*)(0x42DE22A4UL)) -#define bFM4_GPIO_PCR5_P5A *((volatile unsigned int*)(0x42DE22A8UL)) -#define bFM4_GPIO_PCR5_P5B *((volatile unsigned int*)(0x42DE22ACUL)) -#define bFM4_GPIO_PCR6_P60 *((volatile unsigned int*)(0x42DE2300UL)) -#define bFM4_GPIO_PCR6_P61 *((volatile unsigned int*)(0x42DE2304UL)) -#define bFM4_GPIO_PCR6_P62 *((volatile unsigned int*)(0x42DE2308UL)) -#define bFM4_GPIO_PCR6_P63 *((volatile unsigned int*)(0x42DE230CUL)) -#define bFM4_GPIO_PCR6_P64 *((volatile unsigned int*)(0x42DE2310UL)) -#define bFM4_GPIO_PCR6_P65 *((volatile unsigned int*)(0x42DE2314UL)) -#define bFM4_GPIO_PCR6_P66 *((volatile unsigned int*)(0x42DE2318UL)) -#define bFM4_GPIO_PCR6_P67 *((volatile unsigned int*)(0x42DE231CUL)) -#define bFM4_GPIO_PCR6_P68 *((volatile unsigned int*)(0x42DE2320UL)) -#define bFM4_GPIO_PCR7_P70 *((volatile unsigned int*)(0x42DE2380UL)) -#define bFM4_GPIO_PCR7_P71 *((volatile unsigned int*)(0x42DE2384UL)) -#define bFM4_GPIO_PCR7_P72 *((volatile unsigned int*)(0x42DE2388UL)) -#define bFM4_GPIO_PCR7_P73 *((volatile unsigned int*)(0x42DE238CUL)) -#define bFM4_GPIO_PCR7_P74 *((volatile unsigned int*)(0x42DE2390UL)) -#define bFM4_GPIO_PCR8_P80 *((volatile unsigned int*)(0x42DE2400UL)) -#define bFM4_GPIO_PCR8_P81 *((volatile unsigned int*)(0x42DE2404UL)) -#define bFM4_GPIO_PCRE_PE0 *((volatile unsigned int*)(0x42DE2700UL)) -#define bFM4_GPIO_PCRE_PE2 *((volatile unsigned int*)(0x42DE2708UL)) -#define bFM4_GPIO_PCRE_PE3 *((volatile unsigned int*)(0x42DE270CUL)) -#define bFM4_GPIO_DDR0_P00 *((volatile unsigned int*)(0x42DE4000UL)) -#define bFM4_GPIO_DDR0_P01 *((volatile unsigned int*)(0x42DE4004UL)) -#define bFM4_GPIO_DDR0_P02 *((volatile unsigned int*)(0x42DE4008UL)) -#define bFM4_GPIO_DDR0_P03 *((volatile unsigned int*)(0x42DE400CUL)) -#define bFM4_GPIO_DDR0_P04 *((volatile unsigned int*)(0x42DE4010UL)) -#define bFM4_GPIO_DDR0_P05 *((volatile unsigned int*)(0x42DE4014UL)) -#define bFM4_GPIO_DDR0_P06 *((volatile unsigned int*)(0x42DE4018UL)) -#define bFM4_GPIO_DDR0_P07 *((volatile unsigned int*)(0x42DE401CUL)) -#define bFM4_GPIO_DDR0_P08 *((volatile unsigned int*)(0x42DE4020UL)) -#define bFM4_GPIO_DDR0_P09 *((volatile unsigned int*)(0x42DE4024UL)) -#define bFM4_GPIO_DDR0_P0A *((volatile unsigned int*)(0x42DE4028UL)) -#define bFM4_GPIO_DDR0_P0B *((volatile unsigned int*)(0x42DE402CUL)) -#define bFM4_GPIO_DDR0_P0C *((volatile unsigned int*)(0x42DE4030UL)) -#define bFM4_GPIO_DDR0_P0D *((volatile unsigned int*)(0x42DE4034UL)) -#define bFM4_GPIO_DDR0_P0E *((volatile unsigned int*)(0x42DE4038UL)) -#define bFM4_GPIO_DDR0_P0F *((volatile unsigned int*)(0x42DE403CUL)) -#define bFM4_GPIO_DDR1_P10 *((volatile unsigned int*)(0x42DE4080UL)) -#define bFM4_GPIO_DDR1_P11 *((volatile unsigned int*)(0x42DE4084UL)) -#define bFM4_GPIO_DDR1_P12 *((volatile unsigned int*)(0x42DE4088UL)) -#define bFM4_GPIO_DDR1_P13 *((volatile unsigned int*)(0x42DE408CUL)) -#define bFM4_GPIO_DDR1_P14 *((volatile unsigned int*)(0x42DE4090UL)) -#define bFM4_GPIO_DDR1_P15 *((volatile unsigned int*)(0x42DE4094UL)) -#define bFM4_GPIO_DDR1_P16 *((volatile unsigned int*)(0x42DE4098UL)) -#define bFM4_GPIO_DDR1_P17 *((volatile unsigned int*)(0x42DE409CUL)) -#define bFM4_GPIO_DDR1_P18 *((volatile unsigned int*)(0x42DE40A0UL)) -#define bFM4_GPIO_DDR1_P19 *((volatile unsigned int*)(0x42DE40A4UL)) -#define bFM4_GPIO_DDR1_P1A *((volatile unsigned int*)(0x42DE40A8UL)) -#define bFM4_GPIO_DDR1_P1B *((volatile unsigned int*)(0x42DE40ACUL)) -#define bFM4_GPIO_DDR1_P1C *((volatile unsigned int*)(0x42DE40B0UL)) -#define bFM4_GPIO_DDR1_P1D *((volatile unsigned int*)(0x42DE40B4UL)) -#define bFM4_GPIO_DDR1_P1E *((volatile unsigned int*)(0x42DE40B8UL)) -#define bFM4_GPIO_DDR1_P1F *((volatile unsigned int*)(0x42DE40BCUL)) -#define bFM4_GPIO_DDR2_P20 *((volatile unsigned int*)(0x42DE4100UL)) -#define bFM4_GPIO_DDR2_P21 *((volatile unsigned int*)(0x42DE4104UL)) -#define bFM4_GPIO_DDR2_P22 *((volatile unsigned int*)(0x42DE4108UL)) -#define bFM4_GPIO_DDR2_P23 *((volatile unsigned int*)(0x42DE410CUL)) -#define bFM4_GPIO_DDR2_P24 *((volatile unsigned int*)(0x42DE4110UL)) -#define bFM4_GPIO_DDR2_P25 *((volatile unsigned int*)(0x42DE4114UL)) -#define bFM4_GPIO_DDR2_P26 *((volatile unsigned int*)(0x42DE4118UL)) -#define bFM4_GPIO_DDR2_P27 *((volatile unsigned int*)(0x42DE411CUL)) -#define bFM4_GPIO_DDR3_P30 *((volatile unsigned int*)(0x42DE4180UL)) -#define bFM4_GPIO_DDR3_P31 *((volatile unsigned int*)(0x42DE4184UL)) -#define bFM4_GPIO_DDR3_P32 *((volatile unsigned int*)(0x42DE4188UL)) -#define bFM4_GPIO_DDR3_P33 *((volatile unsigned int*)(0x42DE418CUL)) -#define bFM4_GPIO_DDR3_P34 *((volatile unsigned int*)(0x42DE4190UL)) -#define bFM4_GPIO_DDR3_P35 *((volatile unsigned int*)(0x42DE4194UL)) -#define bFM4_GPIO_DDR3_P36 *((volatile unsigned int*)(0x42DE4198UL)) -#define bFM4_GPIO_DDR3_P37 *((volatile unsigned int*)(0x42DE419CUL)) -#define bFM4_GPIO_DDR3_P38 *((volatile unsigned int*)(0x42DE41A0UL)) -#define bFM4_GPIO_DDR3_P39 *((volatile unsigned int*)(0x42DE41A4UL)) -#define bFM4_GPIO_DDR3_P3A *((volatile unsigned int*)(0x42DE41A8UL)) -#define bFM4_GPIO_DDR3_P3B *((volatile unsigned int*)(0x42DE41ACUL)) -#define bFM4_GPIO_DDR3_P3C *((volatile unsigned int*)(0x42DE41B0UL)) -#define bFM4_GPIO_DDR3_P3D *((volatile unsigned int*)(0x42DE41B4UL)) -#define bFM4_GPIO_DDR3_P3E *((volatile unsigned int*)(0x42DE41B8UL)) -#define bFM4_GPIO_DDR3_P3F *((volatile unsigned int*)(0x42DE41BCUL)) -#define bFM4_GPIO_DDR4_P40 *((volatile unsigned int*)(0x42DE4200UL)) -#define bFM4_GPIO_DDR4_P41 *((volatile unsigned int*)(0x42DE4204UL)) -#define bFM4_GPIO_DDR4_P42 *((volatile unsigned int*)(0x42DE4208UL)) -#define bFM4_GPIO_DDR4_P43 *((volatile unsigned int*)(0x42DE420CUL)) -#define bFM4_GPIO_DDR4_P44 *((volatile unsigned int*)(0x42DE4210UL)) -#define bFM4_GPIO_DDR4_P45 *((volatile unsigned int*)(0x42DE4214UL)) -#define bFM4_GPIO_DDR4_P46 *((volatile unsigned int*)(0x42DE4218UL)) -#define bFM4_GPIO_DDR4_P47 *((volatile unsigned int*)(0x42DE421CUL)) -#define bFM4_GPIO_DDR4_P48 *((volatile unsigned int*)(0x42DE4220UL)) -#define bFM4_GPIO_DDR4_P49 *((volatile unsigned int*)(0x42DE4224UL)) -#define bFM4_GPIO_DDR4_P4A *((volatile unsigned int*)(0x42DE4228UL)) -#define bFM4_GPIO_DDR4_P4B *((volatile unsigned int*)(0x42DE422CUL)) -#define bFM4_GPIO_DDR4_P4C *((volatile unsigned int*)(0x42DE4230UL)) -#define bFM4_GPIO_DDR4_P4D *((volatile unsigned int*)(0x42DE4234UL)) -#define bFM4_GPIO_DDR4_P4E *((volatile unsigned int*)(0x42DE4238UL)) -#define bFM4_GPIO_DDR5_P50 *((volatile unsigned int*)(0x42DE4280UL)) -#define bFM4_GPIO_DDR5_P51 *((volatile unsigned int*)(0x42DE4284UL)) -#define bFM4_GPIO_DDR5_P52 *((volatile unsigned int*)(0x42DE4288UL)) -#define bFM4_GPIO_DDR5_P53 *((volatile unsigned int*)(0x42DE428CUL)) -#define bFM4_GPIO_DDR5_P54 *((volatile unsigned int*)(0x42DE4290UL)) -#define bFM4_GPIO_DDR5_P55 *((volatile unsigned int*)(0x42DE4294UL)) -#define bFM4_GPIO_DDR5_P56 *((volatile unsigned int*)(0x42DE4298UL)) -#define bFM4_GPIO_DDR5_P57 *((volatile unsigned int*)(0x42DE429CUL)) -#define bFM4_GPIO_DDR5_P58 *((volatile unsigned int*)(0x42DE42A0UL)) -#define bFM4_GPIO_DDR5_P59 *((volatile unsigned int*)(0x42DE42A4UL)) -#define bFM4_GPIO_DDR5_P5A *((volatile unsigned int*)(0x42DE42A8UL)) -#define bFM4_GPIO_DDR5_P5B *((volatile unsigned int*)(0x42DE42ACUL)) -#define bFM4_GPIO_DDR6_P60 *((volatile unsigned int*)(0x42DE4300UL)) -#define bFM4_GPIO_DDR6_P61 *((volatile unsigned int*)(0x42DE4304UL)) -#define bFM4_GPIO_DDR6_P62 *((volatile unsigned int*)(0x42DE4308UL)) -#define bFM4_GPIO_DDR6_P63 *((volatile unsigned int*)(0x42DE430CUL)) -#define bFM4_GPIO_DDR6_P64 *((volatile unsigned int*)(0x42DE4310UL)) -#define bFM4_GPIO_DDR6_P65 *((volatile unsigned int*)(0x42DE4314UL)) -#define bFM4_GPIO_DDR6_P66 *((volatile unsigned int*)(0x42DE4318UL)) -#define bFM4_GPIO_DDR6_P67 *((volatile unsigned int*)(0x42DE431CUL)) -#define bFM4_GPIO_DDR6_P68 *((volatile unsigned int*)(0x42DE4320UL)) -#define bFM4_GPIO_DDR7_P70 *((volatile unsigned int*)(0x42DE4380UL)) -#define bFM4_GPIO_DDR7_P71 *((volatile unsigned int*)(0x42DE4384UL)) -#define bFM4_GPIO_DDR7_P72 *((volatile unsigned int*)(0x42DE4388UL)) -#define bFM4_GPIO_DDR7_P73 *((volatile unsigned int*)(0x42DE438CUL)) -#define bFM4_GPIO_DDR7_P74 *((volatile unsigned int*)(0x42DE4390UL)) -#define bFM4_GPIO_DDR8_P80 *((volatile unsigned int*)(0x42DE4400UL)) -#define bFM4_GPIO_DDR8_P81 *((volatile unsigned int*)(0x42DE4404UL)) -#define bFM4_GPIO_DDRE_PE0 *((volatile unsigned int*)(0x42DE4700UL)) -#define bFM4_GPIO_DDRE_PE2 *((volatile unsigned int*)(0x42DE4708UL)) -#define bFM4_GPIO_DDRE_PE3 *((volatile unsigned int*)(0x42DE470CUL)) -#define bFM4_GPIO_PDIR0_P00 *((volatile unsigned int*)(0x42DE6000UL)) -#define bFM4_GPIO_PDIR0_P01 *((volatile unsigned int*)(0x42DE6004UL)) -#define bFM4_GPIO_PDIR0_P02 *((volatile unsigned int*)(0x42DE6008UL)) -#define bFM4_GPIO_PDIR0_P03 *((volatile unsigned int*)(0x42DE600CUL)) -#define bFM4_GPIO_PDIR0_P04 *((volatile unsigned int*)(0x42DE6010UL)) -#define bFM4_GPIO_PDIR0_P05 *((volatile unsigned int*)(0x42DE6014UL)) -#define bFM4_GPIO_PDIR0_P06 *((volatile unsigned int*)(0x42DE6018UL)) -#define bFM4_GPIO_PDIR0_P07 *((volatile unsigned int*)(0x42DE601CUL)) -#define bFM4_GPIO_PDIR0_P08 *((volatile unsigned int*)(0x42DE6020UL)) -#define bFM4_GPIO_PDIR0_P09 *((volatile unsigned int*)(0x42DE6024UL)) -#define bFM4_GPIO_PDIR0_P0A *((volatile unsigned int*)(0x42DE6028UL)) -#define bFM4_GPIO_PDIR0_P0B *((volatile unsigned int*)(0x42DE602CUL)) -#define bFM4_GPIO_PDIR0_P0C *((volatile unsigned int*)(0x42DE6030UL)) -#define bFM4_GPIO_PDIR0_P0D *((volatile unsigned int*)(0x42DE6034UL)) -#define bFM4_GPIO_PDIR0_P0E *((volatile unsigned int*)(0x42DE6038UL)) -#define bFM4_GPIO_PDIR0_P0F *((volatile unsigned int*)(0x42DE603CUL)) -#define bFM4_GPIO_PDIR1_P10 *((volatile unsigned int*)(0x42DE6080UL)) -#define bFM4_GPIO_PDIR1_P11 *((volatile unsigned int*)(0x42DE6084UL)) -#define bFM4_GPIO_PDIR1_P12 *((volatile unsigned int*)(0x42DE6088UL)) -#define bFM4_GPIO_PDIR1_P13 *((volatile unsigned int*)(0x42DE608CUL)) -#define bFM4_GPIO_PDIR1_P14 *((volatile unsigned int*)(0x42DE6090UL)) -#define bFM4_GPIO_PDIR1_P15 *((volatile unsigned int*)(0x42DE6094UL)) -#define bFM4_GPIO_PDIR1_P16 *((volatile unsigned int*)(0x42DE6098UL)) -#define bFM4_GPIO_PDIR1_P17 *((volatile unsigned int*)(0x42DE609CUL)) -#define bFM4_GPIO_PDIR1_P18 *((volatile unsigned int*)(0x42DE60A0UL)) -#define bFM4_GPIO_PDIR1_P19 *((volatile unsigned int*)(0x42DE60A4UL)) -#define bFM4_GPIO_PDIR1_P1A *((volatile unsigned int*)(0x42DE60A8UL)) -#define bFM4_GPIO_PDIR1_P1B *((volatile unsigned int*)(0x42DE60ACUL)) -#define bFM4_GPIO_PDIR1_P1C *((volatile unsigned int*)(0x42DE60B0UL)) -#define bFM4_GPIO_PDIR1_P1D *((volatile unsigned int*)(0x42DE60B4UL)) -#define bFM4_GPIO_PDIR1_P1E *((volatile unsigned int*)(0x42DE60B8UL)) -#define bFM4_GPIO_PDIR1_P1F *((volatile unsigned int*)(0x42DE60BCUL)) -#define bFM4_GPIO_PDIR2_P20 *((volatile unsigned int*)(0x42DE6100UL)) -#define bFM4_GPIO_PDIR2_P21 *((volatile unsigned int*)(0x42DE6104UL)) -#define bFM4_GPIO_PDIR2_P22 *((volatile unsigned int*)(0x42DE6108UL)) -#define bFM4_GPIO_PDIR2_P23 *((volatile unsigned int*)(0x42DE610CUL)) -#define bFM4_GPIO_PDIR2_P24 *((volatile unsigned int*)(0x42DE6110UL)) -#define bFM4_GPIO_PDIR2_P25 *((volatile unsigned int*)(0x42DE6114UL)) -#define bFM4_GPIO_PDIR2_P26 *((volatile unsigned int*)(0x42DE6118UL)) -#define bFM4_GPIO_PDIR2_P27 *((volatile unsigned int*)(0x42DE611CUL)) -#define bFM4_GPIO_PDIR3_P30 *((volatile unsigned int*)(0x42DE6180UL)) -#define bFM4_GPIO_PDIR3_P31 *((volatile unsigned int*)(0x42DE6184UL)) -#define bFM4_GPIO_PDIR3_P32 *((volatile unsigned int*)(0x42DE6188UL)) -#define bFM4_GPIO_PDIR3_P33 *((volatile unsigned int*)(0x42DE618CUL)) -#define bFM4_GPIO_PDIR3_P34 *((volatile unsigned int*)(0x42DE6190UL)) -#define bFM4_GPIO_PDIR3_P35 *((volatile unsigned int*)(0x42DE6194UL)) -#define bFM4_GPIO_PDIR3_P36 *((volatile unsigned int*)(0x42DE6198UL)) -#define bFM4_GPIO_PDIR3_P37 *((volatile unsigned int*)(0x42DE619CUL)) -#define bFM4_GPIO_PDIR3_P38 *((volatile unsigned int*)(0x42DE61A0UL)) -#define bFM4_GPIO_PDIR3_P39 *((volatile unsigned int*)(0x42DE61A4UL)) -#define bFM4_GPIO_PDIR3_P3A *((volatile unsigned int*)(0x42DE61A8UL)) -#define bFM4_GPIO_PDIR3_P3B *((volatile unsigned int*)(0x42DE61ACUL)) -#define bFM4_GPIO_PDIR3_P3C *((volatile unsigned int*)(0x42DE61B0UL)) -#define bFM4_GPIO_PDIR3_P3D *((volatile unsigned int*)(0x42DE61B4UL)) -#define bFM4_GPIO_PDIR3_P3E *((volatile unsigned int*)(0x42DE61B8UL)) -#define bFM4_GPIO_PDIR3_P3F *((volatile unsigned int*)(0x42DE61BCUL)) -#define bFM4_GPIO_PDIR4_P40 *((volatile unsigned int*)(0x42DE6200UL)) -#define bFM4_GPIO_PDIR4_P41 *((volatile unsigned int*)(0x42DE6204UL)) -#define bFM4_GPIO_PDIR4_P42 *((volatile unsigned int*)(0x42DE6208UL)) -#define bFM4_GPIO_PDIR4_P43 *((volatile unsigned int*)(0x42DE620CUL)) -#define bFM4_GPIO_PDIR4_P44 *((volatile unsigned int*)(0x42DE6210UL)) -#define bFM4_GPIO_PDIR4_P45 *((volatile unsigned int*)(0x42DE6214UL)) -#define bFM4_GPIO_PDIR4_P46 *((volatile unsigned int*)(0x42DE6218UL)) -#define bFM4_GPIO_PDIR4_P47 *((volatile unsigned int*)(0x42DE621CUL)) -#define bFM4_GPIO_PDIR4_P48 *((volatile unsigned int*)(0x42DE6220UL)) -#define bFM4_GPIO_PDIR4_P49 *((volatile unsigned int*)(0x42DE6224UL)) -#define bFM4_GPIO_PDIR4_P4A *((volatile unsigned int*)(0x42DE6228UL)) -#define bFM4_GPIO_PDIR4_P4B *((volatile unsigned int*)(0x42DE622CUL)) -#define bFM4_GPIO_PDIR4_P4C *((volatile unsigned int*)(0x42DE6230UL)) -#define bFM4_GPIO_PDIR4_P4D *((volatile unsigned int*)(0x42DE6234UL)) -#define bFM4_GPIO_PDIR4_P4E *((volatile unsigned int*)(0x42DE6238UL)) -#define bFM4_GPIO_PDIR5_P50 *((volatile unsigned int*)(0x42DE6280UL)) -#define bFM4_GPIO_PDIR5_P51 *((volatile unsigned int*)(0x42DE6284UL)) -#define bFM4_GPIO_PDIR5_P52 *((volatile unsigned int*)(0x42DE6288UL)) -#define bFM4_GPIO_PDIR5_P53 *((volatile unsigned int*)(0x42DE628CUL)) -#define bFM4_GPIO_PDIR5_P54 *((volatile unsigned int*)(0x42DE6290UL)) -#define bFM4_GPIO_PDIR5_P55 *((volatile unsigned int*)(0x42DE6294UL)) -#define bFM4_GPIO_PDIR5_P56 *((volatile unsigned int*)(0x42DE6298UL)) -#define bFM4_GPIO_PDIR5_P57 *((volatile unsigned int*)(0x42DE629CUL)) -#define bFM4_GPIO_PDIR5_P58 *((volatile unsigned int*)(0x42DE62A0UL)) -#define bFM4_GPIO_PDIR5_P59 *((volatile unsigned int*)(0x42DE62A4UL)) -#define bFM4_GPIO_PDIR5_P5A *((volatile unsigned int*)(0x42DE62A8UL)) -#define bFM4_GPIO_PDIR5_P5B *((volatile unsigned int*)(0x42DE62ACUL)) -#define bFM4_GPIO_PDIR6_P60 *((volatile unsigned int*)(0x42DE6300UL)) -#define bFM4_GPIO_PDIR6_P61 *((volatile unsigned int*)(0x42DE6304UL)) -#define bFM4_GPIO_PDIR6_P62 *((volatile unsigned int*)(0x42DE6308UL)) -#define bFM4_GPIO_PDIR6_P63 *((volatile unsigned int*)(0x42DE630CUL)) -#define bFM4_GPIO_PDIR6_P64 *((volatile unsigned int*)(0x42DE6310UL)) -#define bFM4_GPIO_PDIR6_P65 *((volatile unsigned int*)(0x42DE6314UL)) -#define bFM4_GPIO_PDIR6_P66 *((volatile unsigned int*)(0x42DE6318UL)) -#define bFM4_GPIO_PDIR6_P67 *((volatile unsigned int*)(0x42DE631CUL)) -#define bFM4_GPIO_PDIR6_P68 *((volatile unsigned int*)(0x42DE6320UL)) -#define bFM4_GPIO_PDIR7_P70 *((volatile unsigned int*)(0x42DE6380UL)) -#define bFM4_GPIO_PDIR7_P71 *((volatile unsigned int*)(0x42DE6384UL)) -#define bFM4_GPIO_PDIR7_P72 *((volatile unsigned int*)(0x42DE6388UL)) -#define bFM4_GPIO_PDIR7_P73 *((volatile unsigned int*)(0x42DE638CUL)) -#define bFM4_GPIO_PDIR7_P74 *((volatile unsigned int*)(0x42DE6390UL)) -#define bFM4_GPIO_PDIR8_P80 *((volatile unsigned int*)(0x42DE6400UL)) -#define bFM4_GPIO_PDIR8_P81 *((volatile unsigned int*)(0x42DE6404UL)) -#define bFM4_GPIO_PDIRE_PE0 *((volatile unsigned int*)(0x42DE6700UL)) -#define bFM4_GPIO_PDIRE_PE2 *((volatile unsigned int*)(0x42DE6708UL)) -#define bFM4_GPIO_PDIRE_PE3 *((volatile unsigned int*)(0x42DE670CUL)) -#define bFM4_GPIO_PDOR0_P00 *((volatile unsigned int*)(0x42DE8000UL)) -#define bFM4_GPIO_PDOR0_P01 *((volatile unsigned int*)(0x42DE8004UL)) -#define bFM4_GPIO_PDOR0_P02 *((volatile unsigned int*)(0x42DE8008UL)) -#define bFM4_GPIO_PDOR0_P03 *((volatile unsigned int*)(0x42DE800CUL)) -#define bFM4_GPIO_PDOR0_P04 *((volatile unsigned int*)(0x42DE8010UL)) -#define bFM4_GPIO_PDOR0_P05 *((volatile unsigned int*)(0x42DE8014UL)) -#define bFM4_GPIO_PDOR0_P06 *((volatile unsigned int*)(0x42DE8018UL)) -#define bFM4_GPIO_PDOR0_P07 *((volatile unsigned int*)(0x42DE801CUL)) -#define bFM4_GPIO_PDOR0_P08 *((volatile unsigned int*)(0x42DE8020UL)) -#define bFM4_GPIO_PDOR0_P09 *((volatile unsigned int*)(0x42DE8024UL)) -#define bFM4_GPIO_PDOR0_P0A *((volatile unsigned int*)(0x42DE8028UL)) -#define bFM4_GPIO_PDOR0_P0B *((volatile unsigned int*)(0x42DE802CUL)) -#define bFM4_GPIO_PDOR0_P0C *((volatile unsigned int*)(0x42DE8030UL)) -#define bFM4_GPIO_PDOR0_P0D *((volatile unsigned int*)(0x42DE8034UL)) -#define bFM4_GPIO_PDOR0_P0E *((volatile unsigned int*)(0x42DE8038UL)) -#define bFM4_GPIO_PDOR0_P0F *((volatile unsigned int*)(0x42DE803CUL)) -#define bFM4_GPIO_PDOR1_P10 *((volatile unsigned int*)(0x42DE8080UL)) -#define bFM4_GPIO_PDOR1_P11 *((volatile unsigned int*)(0x42DE8084UL)) -#define bFM4_GPIO_PDOR1_P12 *((volatile unsigned int*)(0x42DE8088UL)) -#define bFM4_GPIO_PDOR1_P13 *((volatile unsigned int*)(0x42DE808CUL)) -#define bFM4_GPIO_PDOR1_P14 *((volatile unsigned int*)(0x42DE8090UL)) -#define bFM4_GPIO_PDOR1_P15 *((volatile unsigned int*)(0x42DE8094UL)) -#define bFM4_GPIO_PDOR1_P16 *((volatile unsigned int*)(0x42DE8098UL)) -#define bFM4_GPIO_PDOR1_P17 *((volatile unsigned int*)(0x42DE809CUL)) -#define bFM4_GPIO_PDOR1_P18 *((volatile unsigned int*)(0x42DE80A0UL)) -#define bFM4_GPIO_PDOR1_P19 *((volatile unsigned int*)(0x42DE80A4UL)) -#define bFM4_GPIO_PDOR1_P1A *((volatile unsigned int*)(0x42DE80A8UL)) -#define bFM4_GPIO_PDOR1_P1B *((volatile unsigned int*)(0x42DE80ACUL)) -#define bFM4_GPIO_PDOR1_P1C *((volatile unsigned int*)(0x42DE80B0UL)) -#define bFM4_GPIO_PDOR1_P1D *((volatile unsigned int*)(0x42DE80B4UL)) -#define bFM4_GPIO_PDOR1_P1E *((volatile unsigned int*)(0x42DE80B8UL)) -#define bFM4_GPIO_PDOR1_P1F *((volatile unsigned int*)(0x42DE80BCUL)) -#define bFM4_GPIO_PDOR2_P20 *((volatile unsigned int*)(0x42DE8100UL)) -#define bFM4_GPIO_PDOR2_P21 *((volatile unsigned int*)(0x42DE8104UL)) -#define bFM4_GPIO_PDOR2_P22 *((volatile unsigned int*)(0x42DE8108UL)) -#define bFM4_GPIO_PDOR2_P23 *((volatile unsigned int*)(0x42DE810CUL)) -#define bFM4_GPIO_PDOR2_P24 *((volatile unsigned int*)(0x42DE8110UL)) -#define bFM4_GPIO_PDOR2_P25 *((volatile unsigned int*)(0x42DE8114UL)) -#define bFM4_GPIO_PDOR2_P26 *((volatile unsigned int*)(0x42DE8118UL)) -#define bFM4_GPIO_PDOR2_P27 *((volatile unsigned int*)(0x42DE811CUL)) -#define bFM4_GPIO_PDOR3_P30 *((volatile unsigned int*)(0x42DE8180UL)) -#define bFM4_GPIO_PDOR3_P31 *((volatile unsigned int*)(0x42DE8184UL)) -#define bFM4_GPIO_PDOR3_P32 *((volatile unsigned int*)(0x42DE8188UL)) -#define bFM4_GPIO_PDOR3_P33 *((volatile unsigned int*)(0x42DE818CUL)) -#define bFM4_GPIO_PDOR3_P34 *((volatile unsigned int*)(0x42DE8190UL)) -#define bFM4_GPIO_PDOR3_P35 *((volatile unsigned int*)(0x42DE8194UL)) -#define bFM4_GPIO_PDOR3_P36 *((volatile unsigned int*)(0x42DE8198UL)) -#define bFM4_GPIO_PDOR3_P37 *((volatile unsigned int*)(0x42DE819CUL)) -#define bFM4_GPIO_PDOR3_P38 *((volatile unsigned int*)(0x42DE81A0UL)) -#define bFM4_GPIO_PDOR3_P39 *((volatile unsigned int*)(0x42DE81A4UL)) -#define bFM4_GPIO_PDOR3_P3A *((volatile unsigned int*)(0x42DE81A8UL)) -#define bFM4_GPIO_PDOR3_P3B *((volatile unsigned int*)(0x42DE81ACUL)) -#define bFM4_GPIO_PDOR3_P3C *((volatile unsigned int*)(0x42DE81B0UL)) -#define bFM4_GPIO_PDOR3_P3D *((volatile unsigned int*)(0x42DE81B4UL)) -#define bFM4_GPIO_PDOR3_P3E *((volatile unsigned int*)(0x42DE81B8UL)) -#define bFM4_GPIO_PDOR3_P3F *((volatile unsigned int*)(0x42DE81BCUL)) -#define bFM4_GPIO_PDOR4_P40 *((volatile unsigned int*)(0x42DE8200UL)) -#define bFM4_GPIO_PDOR4_P41 *((volatile unsigned int*)(0x42DE8204UL)) -#define bFM4_GPIO_PDOR4_P42 *((volatile unsigned int*)(0x42DE8208UL)) -#define bFM4_GPIO_PDOR4_P43 *((volatile unsigned int*)(0x42DE820CUL)) -#define bFM4_GPIO_PDOR4_P44 *((volatile unsigned int*)(0x42DE8210UL)) -#define bFM4_GPIO_PDOR4_P45 *((volatile unsigned int*)(0x42DE8214UL)) -#define bFM4_GPIO_PDOR4_P46 *((volatile unsigned int*)(0x42DE8218UL)) -#define bFM4_GPIO_PDOR4_P47 *((volatile unsigned int*)(0x42DE821CUL)) -#define bFM4_GPIO_PDOR4_P48 *((volatile unsigned int*)(0x42DE8220UL)) -#define bFM4_GPIO_PDOR4_P49 *((volatile unsigned int*)(0x42DE8224UL)) -#define bFM4_GPIO_PDOR4_P4A *((volatile unsigned int*)(0x42DE8228UL)) -#define bFM4_GPIO_PDOR4_P4B *((volatile unsigned int*)(0x42DE822CUL)) -#define bFM4_GPIO_PDOR4_P4C *((volatile unsigned int*)(0x42DE8230UL)) -#define bFM4_GPIO_PDOR4_P4D *((volatile unsigned int*)(0x42DE8234UL)) -#define bFM4_GPIO_PDOR4_P4E *((volatile unsigned int*)(0x42DE8238UL)) -#define bFM4_GPIO_PDOR5_P50 *((volatile unsigned int*)(0x42DE8280UL)) -#define bFM4_GPIO_PDOR5_P51 *((volatile unsigned int*)(0x42DE8284UL)) -#define bFM4_GPIO_PDOR5_P52 *((volatile unsigned int*)(0x42DE8288UL)) -#define bFM4_GPIO_PDOR5_P53 *((volatile unsigned int*)(0x42DE828CUL)) -#define bFM4_GPIO_PDOR5_P54 *((volatile unsigned int*)(0x42DE8290UL)) -#define bFM4_GPIO_PDOR5_P55 *((volatile unsigned int*)(0x42DE8294UL)) -#define bFM4_GPIO_PDOR5_P56 *((volatile unsigned int*)(0x42DE8298UL)) -#define bFM4_GPIO_PDOR5_P57 *((volatile unsigned int*)(0x42DE829CUL)) -#define bFM4_GPIO_PDOR5_P58 *((volatile unsigned int*)(0x42DE82A0UL)) -#define bFM4_GPIO_PDOR5_P59 *((volatile unsigned int*)(0x42DE82A4UL)) -#define bFM4_GPIO_PDOR5_P5A *((volatile unsigned int*)(0x42DE82A8UL)) -#define bFM4_GPIO_PDOR5_P5B *((volatile unsigned int*)(0x42DE82ACUL)) -#define bFM4_GPIO_PDOR6_P60 *((volatile unsigned int*)(0x42DE8300UL)) -#define bFM4_GPIO_PDOR6_P61 *((volatile unsigned int*)(0x42DE8304UL)) -#define bFM4_GPIO_PDOR6_P62 *((volatile unsigned int*)(0x42DE8308UL)) -#define bFM4_GPIO_PDOR6_P63 *((volatile unsigned int*)(0x42DE830CUL)) -#define bFM4_GPIO_PDOR6_P64 *((volatile unsigned int*)(0x42DE8310UL)) -#define bFM4_GPIO_PDOR6_P65 *((volatile unsigned int*)(0x42DE8314UL)) -#define bFM4_GPIO_PDOR6_P66 *((volatile unsigned int*)(0x42DE8318UL)) -#define bFM4_GPIO_PDOR6_P67 *((volatile unsigned int*)(0x42DE831CUL)) -#define bFM4_GPIO_PDOR6_P68 *((volatile unsigned int*)(0x42DE8320UL)) -#define bFM4_GPIO_PDOR7_P70 *((volatile unsigned int*)(0x42DE8380UL)) -#define bFM4_GPIO_PDOR7_P71 *((volatile unsigned int*)(0x42DE8384UL)) -#define bFM4_GPIO_PDOR7_P72 *((volatile unsigned int*)(0x42DE8388UL)) -#define bFM4_GPIO_PDOR7_P73 *((volatile unsigned int*)(0x42DE838CUL)) -#define bFM4_GPIO_PDOR7_P74 *((volatile unsigned int*)(0x42DE8390UL)) -#define bFM4_GPIO_PDOR8_P80 *((volatile unsigned int*)(0x42DE8400UL)) -#define bFM4_GPIO_PDOR8_P81 *((volatile unsigned int*)(0x42DE8404UL)) -#define bFM4_GPIO_PDORE_PE0 *((volatile unsigned int*)(0x42DE8700UL)) -#define bFM4_GPIO_PDORE_PE2 *((volatile unsigned int*)(0x42DE8708UL)) -#define bFM4_GPIO_PDORE_PE3 *((volatile unsigned int*)(0x42DE870CUL)) -#define bFM4_GPIO_ADE_AN00 *((volatile unsigned int*)(0x42DEA000UL)) -#define bFM4_GPIO_ADE_AN01 *((volatile unsigned int*)(0x42DEA004UL)) -#define bFM4_GPIO_ADE_AN02 *((volatile unsigned int*)(0x42DEA008UL)) -#define bFM4_GPIO_ADE_AN03 *((volatile unsigned int*)(0x42DEA00CUL)) -#define bFM4_GPIO_ADE_AN04 *((volatile unsigned int*)(0x42DEA010UL)) -#define bFM4_GPIO_ADE_AN05 *((volatile unsigned int*)(0x42DEA014UL)) -#define bFM4_GPIO_ADE_AN06 *((volatile unsigned int*)(0x42DEA018UL)) -#define bFM4_GPIO_ADE_AN07 *((volatile unsigned int*)(0x42DEA01CUL)) -#define bFM4_GPIO_ADE_AN08 *((volatile unsigned int*)(0x42DEA020UL)) -#define bFM4_GPIO_ADE_AN09 *((volatile unsigned int*)(0x42DEA024UL)) -#define bFM4_GPIO_ADE_AN10 *((volatile unsigned int*)(0x42DEA028UL)) -#define bFM4_GPIO_ADE_AN11 *((volatile unsigned int*)(0x42DEA02CUL)) -#define bFM4_GPIO_ADE_AN12 *((volatile unsigned int*)(0x42DEA030UL)) -#define bFM4_GPIO_ADE_AN13 *((volatile unsigned int*)(0x42DEA034UL)) -#define bFM4_GPIO_ADE_AN14 *((volatile unsigned int*)(0x42DEA038UL)) -#define bFM4_GPIO_ADE_AN15 *((volatile unsigned int*)(0x42DEA03CUL)) -#define bFM4_GPIO_ADE_AN16 *((volatile unsigned int*)(0x42DEA040UL)) -#define bFM4_GPIO_ADE_AN17 *((volatile unsigned int*)(0x42DEA044UL)) -#define bFM4_GPIO_ADE_AN18 *((volatile unsigned int*)(0x42DEA048UL)) -#define bFM4_GPIO_ADE_AN19 *((volatile unsigned int*)(0x42DEA04CUL)) -#define bFM4_GPIO_ADE_AN20 *((volatile unsigned int*)(0x42DEA050UL)) -#define bFM4_GPIO_ADE_AN21 *((volatile unsigned int*)(0x42DEA054UL)) -#define bFM4_GPIO_ADE_AN22 *((volatile unsigned int*)(0x42DEA058UL)) -#define bFM4_GPIO_ADE_AN23 *((volatile unsigned int*)(0x42DEA05CUL)) -#define bFM4_GPIO_ADE_AN24 *((volatile unsigned int*)(0x42DEA060UL)) -#define bFM4_GPIO_ADE_AN25 *((volatile unsigned int*)(0x42DEA064UL)) -#define bFM4_GPIO_ADE_AN26 *((volatile unsigned int*)(0x42DEA068UL)) -#define bFM4_GPIO_ADE_AN27 *((volatile unsigned int*)(0x42DEA06CUL)) -#define bFM4_GPIO_ADE_AN28 *((volatile unsigned int*)(0x42DEA070UL)) -#define bFM4_GPIO_ADE_AN29 *((volatile unsigned int*)(0x42DEA074UL)) -#define bFM4_GPIO_ADE_AN30 *((volatile unsigned int*)(0x42DEA078UL)) -#define bFM4_GPIO_ADE_AN31 *((volatile unsigned int*)(0x42DEA07CUL)) -#define bFM4_GPIO_SPSR_MAINXC0 *((volatile unsigned int*)(0x42DEB008UL)) -#define bFM4_GPIO_SPSR_MAINXC1 *((volatile unsigned int*)(0x42DEB00CUL)) -#define bFM4_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x42DEB010UL)) -#define bFM4_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x42DEB014UL)) -#define bFM4_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x42DEC000UL)) -#define bFM4_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x42DEC004UL)) -#define bFM4_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x42DEC008UL)) -#define bFM4_GPIO_EPFR00_RTCCOE0 *((volatile unsigned int*)(0x42DEC010UL)) -#define bFM4_GPIO_EPFR00_RTCCOE1 *((volatile unsigned int*)(0x42DEC014UL)) -#define bFM4_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x42DEC018UL)) -#define bFM4_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x42DEC01CUL)) -#define bFM4_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x42DEC024UL)) -#define bFM4_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x42DEC034UL)) -#define bFM4_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x42DEC040UL)) -#define bFM4_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x42DEC044UL)) -#define bFM4_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x42DEC060UL)) -#define bFM4_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x42DEC064UL)) -#define bFM4_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x42DEC080UL)) -#define bFM4_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x42DEC084UL)) -#define bFM4_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x42DEC088UL)) -#define bFM4_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x42DEC08CUL)) -#define bFM4_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x42DEC090UL)) -#define bFM4_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x42DEC094UL)) -#define bFM4_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x42DEC098UL)) -#define bFM4_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x42DEC09CUL)) -#define bFM4_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x42DEC0A0UL)) -#define bFM4_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x42DEC0A4UL)) -#define bFM4_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x42DEC0A8UL)) -#define bFM4_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x42DEC0ACUL)) -#define bFM4_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x42DEC0B0UL)) -#define bFM4_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x42DEC0C0UL)) -#define bFM4_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x42DEC0C4UL)) -#define bFM4_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x42DEC0C8UL)) -#define bFM4_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x42DEC0CCUL)) -#define bFM4_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x42DEC0D0UL)) -#define bFM4_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x42DEC0D4UL)) -#define bFM4_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x42DEC0D8UL)) -#define bFM4_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x42DEC0DCUL)) -#define bFM4_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x42DEC0E0UL)) -#define bFM4_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x42DEC0E4UL)) -#define bFM4_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x42DEC0E8UL)) -#define bFM4_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x42DEC0ECUL)) -#define bFM4_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x42DEC0F0UL)) -#define bFM4_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x42DEC0F4UL)) -#define bFM4_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x42DEC0F8UL)) -#define bFM4_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x42DEC0FCUL)) -#define bFM4_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x42DEC100UL)) -#define bFM4_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x42DEC104UL)) -#define bFM4_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x42DEC108UL)) -#define bFM4_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x42DEC10CUL)) -#define bFM4_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x42DEC110UL)) -#define bFM4_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x42DEC114UL)) -#define bFM4_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x42DEC118UL)) -#define bFM4_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x42DEC11CUL)) -#define bFM4_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x42DEC120UL)) -#define bFM4_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x42DEC124UL)) -#define bFM4_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x42DEC128UL)) -#define bFM4_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x42DEC12CUL)) -#define bFM4_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x42DEC130UL)) -#define bFM4_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x42DEC140UL)) -#define bFM4_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x42DEC144UL)) -#define bFM4_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x42DEC148UL)) -#define bFM4_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x42DEC14CUL)) -#define bFM4_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x42DEC150UL)) -#define bFM4_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x42DEC154UL)) -#define bFM4_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x42DEC158UL)) -#define bFM4_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x42DEC15CUL)) -#define bFM4_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x42DEC160UL)) -#define bFM4_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x42DEC164UL)) -#define bFM4_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x42DEC168UL)) -#define bFM4_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x42DEC16CUL)) -#define bFM4_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x42DEC170UL)) -#define bFM4_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x42DEC174UL)) -#define bFM4_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x42DEC178UL)) -#define bFM4_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x42DEC17CUL)) -#define bFM4_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x42DEC180UL)) -#define bFM4_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x42DEC184UL)) -#define bFM4_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x42DEC188UL)) -#define bFM4_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x42DEC18CUL)) -#define bFM4_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x42DEC190UL)) -#define bFM4_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x42DEC194UL)) -#define bFM4_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x42DEC198UL)) -#define bFM4_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x42DEC19CUL)) -#define bFM4_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x42DEC1A0UL)) -#define bFM4_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x42DEC1A4UL)) -#define bFM4_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x42DEC1A8UL)) -#define bFM4_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x42DEC1ACUL)) -#define bFM4_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x42DEC1B0UL)) -#define bFM4_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x42DEC1C0UL)) -#define bFM4_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x42DEC1C4UL)) -#define bFM4_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x42DEC1C8UL)) -#define bFM4_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x42DEC1CCUL)) -#define bFM4_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x42DEC1D0UL)) -#define bFM4_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x42DEC1D4UL)) -#define bFM4_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x42DEC1D8UL)) -#define bFM4_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x42DEC1DCUL)) -#define bFM4_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x42DEC1E0UL)) -#define bFM4_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x42DEC1E4UL)) -#define bFM4_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x42DEC1E8UL)) -#define bFM4_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x42DEC1ECUL)) -#define bFM4_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x42DEC1F0UL)) -#define bFM4_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x42DEC1F4UL)) -#define bFM4_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x42DEC1F8UL)) -#define bFM4_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x42DEC1FCUL)) -#define bFM4_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x42DEC208UL)) -#define bFM4_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x42DEC20CUL)) -#define bFM4_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x42DEC210UL)) -#define bFM4_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x42DEC214UL)) -#define bFM4_GPIO_EPFR04_TIOB0S2 *((volatile unsigned int*)(0x42DEC218UL)) -#define bFM4_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x42DEC220UL)) -#define bFM4_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x42DEC224UL)) -#define bFM4_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x42DEC228UL)) -#define bFM4_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x42DEC22CUL)) -#define bFM4_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x42DEC230UL)) -#define bFM4_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x42DEC234UL)) -#define bFM4_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x42DEC248UL)) -#define bFM4_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x42DEC24CUL)) -#define bFM4_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x42DEC250UL)) -#define bFM4_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x42DEC254UL)) -#define bFM4_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x42DEC260UL)) -#define bFM4_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x42DEC264UL)) -#define bFM4_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x42DEC268UL)) -#define bFM4_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x42DEC26CUL)) -#define bFM4_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x42DEC270UL)) -#define bFM4_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x42DEC274UL)) -#define bFM4_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x42DEC288UL)) -#define bFM4_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x42DEC28CUL)) -#define bFM4_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x42DEC290UL)) -#define bFM4_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x42DEC294UL)) -#define bFM4_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x42DEC2A0UL)) -#define bFM4_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x42DEC2A4UL)) -#define bFM4_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x42DEC2A8UL)) -#define bFM4_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x42DEC2ACUL)) -#define bFM4_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x42DEC2B0UL)) -#define bFM4_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x42DEC2B4UL)) -#define bFM4_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x42DEC2C8UL)) -#define bFM4_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x42DEC2CCUL)) -#define bFM4_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x42DEC2D0UL)) -#define bFM4_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x42DEC2D4UL)) -#define bFM4_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x42DEC2E0UL)) -#define bFM4_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x42DEC2E4UL)) -#define bFM4_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x42DEC2E8UL)) -#define bFM4_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x42DEC2ECUL)) -#define bFM4_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x42DEC2F0UL)) -#define bFM4_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x42DEC2F4UL)) -#define bFM4_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x42DEC300UL)) -#define bFM4_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x42DEC304UL)) -#define bFM4_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x42DEC308UL)) -#define bFM4_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x42DEC30CUL)) -#define bFM4_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x42DEC310UL)) -#define bFM4_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x42DEC314UL)) -#define bFM4_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x42DEC318UL)) -#define bFM4_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x42DEC31CUL)) -#define bFM4_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x42DEC320UL)) -#define bFM4_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x42DEC324UL)) -#define bFM4_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x42DEC328UL)) -#define bFM4_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x42DEC32CUL)) -#define bFM4_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x42DEC330UL)) -#define bFM4_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x42DEC334UL)) -#define bFM4_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x42DEC338UL)) -#define bFM4_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x42DEC33CUL)) -#define bFM4_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x42DEC340UL)) -#define bFM4_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x42DEC344UL)) -#define bFM4_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x42DEC348UL)) -#define bFM4_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x42DEC34CUL)) -#define bFM4_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x42DEC350UL)) -#define bFM4_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x42DEC354UL)) -#define bFM4_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x42DEC358UL)) -#define bFM4_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x42DEC35CUL)) -#define bFM4_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x42DEC360UL)) -#define bFM4_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x42DEC364UL)) -#define bFM4_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x42DEC368UL)) -#define bFM4_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x42DEC36CUL)) -#define bFM4_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x42DEC370UL)) -#define bFM4_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x42DEC374UL)) -#define bFM4_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x42DEC378UL)) -#define bFM4_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x42DEC37CUL)) -#define bFM4_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x42DEC390UL)) -#define bFM4_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x42DEC394UL)) -#define bFM4_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x42DEC398UL)) -#define bFM4_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x42DEC39CUL)) -#define bFM4_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x42DEC3A0UL)) -#define bFM4_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x42DEC3A4UL)) -#define bFM4_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x42DEC3A8UL)) -#define bFM4_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x42DEC3ACUL)) -#define bFM4_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x42DEC3B0UL)) -#define bFM4_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x42DEC3B4UL)) -#define bFM4_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x42DEC3B8UL)) -#define bFM4_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x42DEC3BCUL)) -#define bFM4_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x42DEC3C0UL)) -#define bFM4_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x42DEC3C4UL)) -#define bFM4_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x42DEC3C8UL)) -#define bFM4_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x42DEC3CCUL)) -#define bFM4_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x42DEC3D0UL)) -#define bFM4_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x42DEC3D4UL)) -#define bFM4_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x42DEC3D8UL)) -#define bFM4_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x42DEC3DCUL)) -#define bFM4_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x42DEC3E0UL)) -#define bFM4_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x42DEC3E4UL)) -#define bFM4_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x42DEC3E8UL)) -#define bFM4_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x42DEC3ECUL)) -#define bFM4_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x42DEC400UL)) -#define bFM4_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x42DEC404UL)) -#define bFM4_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x42DEC408UL)) -#define bFM4_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x42DEC40CUL)) -#define bFM4_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x42DEC410UL)) -#define bFM4_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x42DEC414UL)) -#define bFM4_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x42DEC418UL)) -#define bFM4_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x42DEC41CUL)) -#define bFM4_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x42DEC420UL)) -#define bFM4_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x42DEC424UL)) -#define bFM4_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x42DEC428UL)) -#define bFM4_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x42DEC42CUL)) -#define bFM4_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x42DEC430UL)) -#define bFM4_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x42DEC434UL)) -#define bFM4_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x42DEC438UL)) -#define bFM4_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x42DEC43CUL)) -#define bFM4_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x42DEC440UL)) -#define bFM4_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x42DEC444UL)) -#define bFM4_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x42DEC448UL)) -#define bFM4_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x42DEC44CUL)) -#define bFM4_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x42DEC450UL)) -#define bFM4_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x42DEC454UL)) -#define bFM4_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x42DEC458UL)) -#define bFM4_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x42DEC45CUL)) -#define bFM4_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x42DEC460UL)) -#define bFM4_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x42DEC464UL)) -#define bFM4_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x42DEC468UL)) -#define bFM4_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x42DEC46CUL)) -#define bFM4_GPIO_EPFR08_RTS5E0 *((volatile unsigned int*)(0x42DEC470UL)) -#define bFM4_GPIO_EPFR08_RTS5E1 *((volatile unsigned int*)(0x42DEC474UL)) -#define bFM4_GPIO_EPFR08_CTS5S0 *((volatile unsigned int*)(0x42DEC478UL)) -#define bFM4_GPIO_EPFR08_CTS5S1 *((volatile unsigned int*)(0x42DEC47CUL)) -#define bFM4_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x42DEC480UL)) -#define bFM4_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x42DEC484UL)) -#define bFM4_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x42DEC488UL)) -#define bFM4_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x42DEC48CUL)) -#define bFM4_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x42DEC490UL)) -#define bFM4_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x42DEC494UL)) -#define bFM4_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x42DEC498UL)) -#define bFM4_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x42DEC49CUL)) -#define bFM4_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x42DEC4A0UL)) -#define bFM4_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x42DEC4A4UL)) -#define bFM4_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x42DEC4A8UL)) -#define bFM4_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x42DEC4ACUL)) -#define bFM4_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x42DEC4B0UL)) -#define bFM4_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x42DEC4B4UL)) -#define bFM4_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x42DEC4B8UL)) -#define bFM4_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x42DEC4BCUL)) -#define bFM4_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x42DEC4C0UL)) -#define bFM4_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x42DEC4C4UL)) -#define bFM4_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x42DEC4C8UL)) -#define bFM4_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x42DEC4CCUL)) -#define bFM4_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x42DEC4D0UL)) -#define bFM4_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x42DEC4D4UL)) -#define bFM4_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x42DEC4D8UL)) -#define bFM4_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x42DEC4DCUL)) -#define bFM4_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x42DEC4E0UL)) -#define bFM4_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x42DEC4E4UL)) -#define bFM4_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x42DEC4E8UL)) -#define bFM4_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x42DEC4ECUL)) -#define bFM4_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x42DEC4F0UL)) -#define bFM4_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x42DEC4F4UL)) -#define bFM4_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x42DEC4F8UL)) -#define bFM4_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x42DEC4FCUL)) -#define bFM4_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x42DEC500UL)) -#define bFM4_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x42DEC504UL)) -#define bFM4_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x42DEC508UL)) -#define bFM4_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x42DEC50CUL)) -#define bFM4_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x42DEC510UL)) -#define bFM4_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x42DEC514UL)) -#define bFM4_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x42DEC518UL)) -#define bFM4_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x42DEC51CUL)) -#define bFM4_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x42DEC520UL)) -#define bFM4_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x42DEC524UL)) -#define bFM4_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x42DEC528UL)) -#define bFM4_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x42DEC52CUL)) -#define bFM4_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x42DEC530UL)) -#define bFM4_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x42DEC534UL)) -#define bFM4_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x42DEC538UL)) -#define bFM4_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x42DEC53CUL)) -#define bFM4_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x42DEC540UL)) -#define bFM4_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x42DEC544UL)) -#define bFM4_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x42DEC548UL)) -#define bFM4_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x42DEC54CUL)) -#define bFM4_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x42DEC550UL)) -#define bFM4_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x42DEC554UL)) -#define bFM4_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x42DEC558UL)) -#define bFM4_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x42DEC55CUL)) -#define bFM4_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x42DEC560UL)) -#define bFM4_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x42DEC564UL)) -#define bFM4_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x42DEC568UL)) -#define bFM4_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x42DEC56CUL)) -#define bFM4_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x42DEC570UL)) -#define bFM4_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x42DEC574UL)) -#define bFM4_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x42DEC578UL)) -#define bFM4_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x42DEC57CUL)) -#define bFM4_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x42DEC580UL)) -#define bFM4_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x42DEC584UL)) -#define bFM4_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x42DEC588UL)) -#define bFM4_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x42DEC58CUL)) -#define bFM4_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x42DEC590UL)) -#define bFM4_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x42DEC594UL)) -#define bFM4_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x42DEC598UL)) -#define bFM4_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x42DEC59CUL)) -#define bFM4_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x42DEC5A0UL)) -#define bFM4_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x42DEC5A4UL)) -#define bFM4_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x42DEC5A8UL)) -#define bFM4_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x42DEC5ACUL)) -#define bFM4_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x42DEC5B0UL)) -#define bFM4_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x42DEC5B4UL)) -#define bFM4_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x42DEC5B8UL)) -#define bFM4_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x42DEC5BCUL)) -#define bFM4_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x42DEC5C0UL)) -#define bFM4_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x42DEC5C4UL)) -#define bFM4_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x42DEC5C8UL)) -#define bFM4_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x42DEC5CCUL)) -#define bFM4_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x42DEC5D0UL)) -#define bFM4_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x42DEC5D4UL)) -#define bFM4_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x42DEC5D8UL)) -#define bFM4_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x42DEC5DCUL)) -#define bFM4_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x42DEC5E0UL)) -#define bFM4_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x42DEC5E4UL)) -#define bFM4_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x42DEC608UL)) -#define bFM4_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x42DEC60CUL)) -#define bFM4_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x42DEC610UL)) -#define bFM4_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x42DEC614UL)) -#define bFM4_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x42DEC620UL)) -#define bFM4_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x42DEC624UL)) -#define bFM4_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x42DEC628UL)) -#define bFM4_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x42DEC62CUL)) -#define bFM4_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x42DEC630UL)) -#define bFM4_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x42DEC634UL)) -#define bFM4_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x42DEC648UL)) -#define bFM4_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x42DEC64CUL)) -#define bFM4_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x42DEC650UL)) -#define bFM4_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x42DEC654UL)) -#define bFM4_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x42DEC660UL)) -#define bFM4_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x42DEC664UL)) -#define bFM4_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x42DEC668UL)) -#define bFM4_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x42DEC66CUL)) -#define bFM4_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x42DEC670UL)) -#define bFM4_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x42DEC674UL)) -#define bFM4_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x42DEC688UL)) -#define bFM4_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x42DEC68CUL)) -#define bFM4_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x42DEC690UL)) -#define bFM4_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x42DEC694UL)) -#define bFM4_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x42DEC6A0UL)) -#define bFM4_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x42DEC6A4UL)) -#define bFM4_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x42DEC6A8UL)) -#define bFM4_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x42DEC6ACUL)) -#define bFM4_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x42DEC6B0UL)) -#define bFM4_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x42DEC6B4UL)) -#define bFM4_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x42DEC6C8UL)) -#define bFM4_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x42DEC6CCUL)) -#define bFM4_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x42DEC6D0UL)) -#define bFM4_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x42DEC6D4UL)) -#define bFM4_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x42DEC6E0UL)) -#define bFM4_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x42DEC6E4UL)) -#define bFM4_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x42DEC6E8UL)) -#define bFM4_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x42DEC6ECUL)) -#define bFM4_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x42DEC6F0UL)) -#define bFM4_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x42DEC6F4UL)) -#define bFM4_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x42DEC700UL)) -#define bFM4_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x42DEC704UL)) -#define bFM4_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x42DEC708UL)) -#define bFM4_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x42DEC70CUL)) -#define bFM4_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x42DEC710UL)) -#define bFM4_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x42DEC714UL)) -#define bFM4_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x42DEC748UL)) -#define bFM4_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x42DEC74CUL)) -#define bFM4_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x42DEC750UL)) -#define bFM4_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x42DEC754UL)) -#define bFM4_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x42DEC758UL)) -#define bFM4_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x42DEC75CUL)) -#define bFM4_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x42DEC760UL)) -#define bFM4_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x42DEC764UL)) -#define bFM4_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x42DEC768UL)) -#define bFM4_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x42DEC76CUL)) -#define bFM4_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x42DEC770UL)) -#define bFM4_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x42DEC774UL)) -#define bFM4_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x42DEC780UL)) -#define bFM4_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x42DEC784UL)) -#define bFM4_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x42DEC788UL)) -#define bFM4_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x42DEC78CUL)) -#define bFM4_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x42DEC790UL)) -#define bFM4_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x42DEC794UL)) -#define bFM4_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x42DEC798UL)) -#define bFM4_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x42DEC79CUL)) -#define bFM4_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x42DEC7A0UL)) -#define bFM4_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x42DEC7A4UL)) -#define bFM4_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x42DEC7A8UL)) -#define bFM4_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x42DEC7ACUL)) -#define bFM4_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x42DEC7B0UL)) -#define bFM4_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x42DEC7B4UL)) -#define bFM4_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x42DEC7B8UL)) -#define bFM4_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x42DEC7BCUL)) -#define bFM4_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x42DEC7C0UL)) -#define bFM4_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x42DEC7C4UL)) -#define bFM4_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x42DEC7C8UL)) -#define bFM4_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x42DEC7CCUL)) -#define bFM4_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x42DEC7D0UL)) -#define bFM4_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x42DEC7D4UL)) -#define bFM4_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x42DEC7D8UL)) -#define bFM4_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x42DEC7DCUL)) -#define bFM4_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x42DEC7E0UL)) -#define bFM4_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x42DEC7E4UL)) -#define bFM4_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x42DEC7E8UL)) -#define bFM4_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x42DEC7ECUL)) -#define bFM4_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x42DEC7F0UL)) -#define bFM4_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x42DEC7F4UL)) -#define bFM4_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x42DEC7F8UL)) -#define bFM4_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x42DEC7FCUL)) -#define bFM4_GPIO_EPFR16_SCS6B0 *((volatile unsigned int*)(0x42DEC800UL)) -#define bFM4_GPIO_EPFR16_SCS6B1 *((volatile unsigned int*)(0x42DEC804UL)) -#define bFM4_GPIO_EPFR16_SCS7B0 *((volatile unsigned int*)(0x42DEC808UL)) -#define bFM4_GPIO_EPFR16_SCS7B1 *((volatile unsigned int*)(0x42DEC80CUL)) -#define bFM4_GPIO_EPFR16_SIN8S0 *((volatile unsigned int*)(0x42DEC810UL)) -#define bFM4_GPIO_EPFR16_SIN8S1 *((volatile unsigned int*)(0x42DEC814UL)) -#define bFM4_GPIO_EPFR16_SOT8B0 *((volatile unsigned int*)(0x42DEC818UL)) -#define bFM4_GPIO_EPFR16_SOT8B1 *((volatile unsigned int*)(0x42DEC81CUL)) -#define bFM4_GPIO_EPFR16_SCK8B0 *((volatile unsigned int*)(0x42DEC820UL)) -#define bFM4_GPIO_EPFR16_SCK8B1 *((volatile unsigned int*)(0x42DEC824UL)) -#define bFM4_GPIO_EPFR16_SIN9S0 *((volatile unsigned int*)(0x42DEC828UL)) -#define bFM4_GPIO_EPFR16_SIN9S1 *((volatile unsigned int*)(0x42DEC82CUL)) -#define bFM4_GPIO_EPFR16_SOT9B0 *((volatile unsigned int*)(0x42DEC830UL)) -#define bFM4_GPIO_EPFR16_SOT9B1 *((volatile unsigned int*)(0x42DEC834UL)) -#define bFM4_GPIO_EPFR16_SCK9B0 *((volatile unsigned int*)(0x42DEC838UL)) -#define bFM4_GPIO_EPFR16_SCK9B1 *((volatile unsigned int*)(0x42DEC83CUL)) -#define bFM4_GPIO_EPFR16_SIN10S0 *((volatile unsigned int*)(0x42DEC840UL)) -#define bFM4_GPIO_EPFR16_SIN10S1 *((volatile unsigned int*)(0x42DEC844UL)) -#define bFM4_GPIO_EPFR16_SOT10B0 *((volatile unsigned int*)(0x42DEC848UL)) -#define bFM4_GPIO_EPFR16_SOT10B1 *((volatile unsigned int*)(0x42DEC84CUL)) -#define bFM4_GPIO_EPFR16_SCK10B0 *((volatile unsigned int*)(0x42DEC850UL)) -#define bFM4_GPIO_EPFR16_SCK10B1 *((volatile unsigned int*)(0x42DEC854UL)) -#define bFM4_GPIO_EPFR16_SIN11S0 *((volatile unsigned int*)(0x42DEC858UL)) -#define bFM4_GPIO_EPFR16_SIN11S1 *((volatile unsigned int*)(0x42DEC85CUL)) -#define bFM4_GPIO_EPFR16_SOT11B0 *((volatile unsigned int*)(0x42DEC860UL)) -#define bFM4_GPIO_EPFR16_SOT11B1 *((volatile unsigned int*)(0x42DEC864UL)) -#define bFM4_GPIO_EPFR16_SCK11B0 *((volatile unsigned int*)(0x42DEC868UL)) -#define bFM4_GPIO_EPFR16_SCK11B1 *((volatile unsigned int*)(0x42DEC86CUL)) -#define bFM4_GPIO_EPFR16_SFMPAC *((volatile unsigned int*)(0x42DEC870UL)) -#define bFM4_GPIO_EPFR16_SFMPBC *((volatile unsigned int*)(0x42DEC874UL)) -#define bFM4_GPIO_EPFR17_SIN12S0 *((volatile unsigned int*)(0x42DEC890UL)) -#define bFM4_GPIO_EPFR17_SIN12S1 *((volatile unsigned int*)(0x42DEC894UL)) -#define bFM4_GPIO_EPFR17_SOT12B0 *((volatile unsigned int*)(0x42DEC898UL)) -#define bFM4_GPIO_EPFR17_SOT12B1 *((volatile unsigned int*)(0x42DEC89CUL)) -#define bFM4_GPIO_EPFR17_SCK12B0 *((volatile unsigned int*)(0x42DEC8A0UL)) -#define bFM4_GPIO_EPFR17_SCK12B1 *((volatile unsigned int*)(0x42DEC8A4UL)) -#define bFM4_GPIO_EPFR17_SIN13S0 *((volatile unsigned int*)(0x42DEC8A8UL)) -#define bFM4_GPIO_EPFR17_SIN13S1 *((volatile unsigned int*)(0x42DEC8ACUL)) -#define bFM4_GPIO_EPFR17_SOT13B0 *((volatile unsigned int*)(0x42DEC8B0UL)) -#define bFM4_GPIO_EPFR17_SOT13B1 *((volatile unsigned int*)(0x42DEC8B4UL)) -#define bFM4_GPIO_EPFR17_SCK13B0 *((volatile unsigned int*)(0x42DEC8B8UL)) -#define bFM4_GPIO_EPFR17_SCK13B1 *((volatile unsigned int*)(0x42DEC8BCUL)) -#define bFM4_GPIO_EPFR17_SIN14S0 *((volatile unsigned int*)(0x42DEC8C0UL)) -#define bFM4_GPIO_EPFR17_SIN14S1 *((volatile unsigned int*)(0x42DEC8C4UL)) -#define bFM4_GPIO_EPFR17_SOT14B0 *((volatile unsigned int*)(0x42DEC8C8UL)) -#define bFM4_GPIO_EPFR17_SOT14B1 *((volatile unsigned int*)(0x42DEC8CCUL)) -#define bFM4_GPIO_EPFR17_SCK14B0 *((volatile unsigned int*)(0x42DEC8D0UL)) -#define bFM4_GPIO_EPFR17_SCK14B1 *((volatile unsigned int*)(0x42DEC8D4UL)) -#define bFM4_GPIO_EPFR17_SIN15S0 *((volatile unsigned int*)(0x42DEC8D8UL)) -#define bFM4_GPIO_EPFR17_SIN15S1 *((volatile unsigned int*)(0x42DEC8DCUL)) -#define bFM4_GPIO_EPFR17_SOT15B0 *((volatile unsigned int*)(0x42DEC8E0UL)) -#define bFM4_GPIO_EPFR17_SOT15B1 *((volatile unsigned int*)(0x42DEC8E4UL)) -#define bFM4_GPIO_EPFR17_SCK15B0 *((volatile unsigned int*)(0x42DEC8E8UL)) -#define bFM4_GPIO_EPFR17_SCK15B1 *((volatile unsigned int*)(0x42DEC8ECUL)) -#define bFM4_GPIO_EPFR18_QAIN3S0 *((volatile unsigned int*)(0x42DEC910UL)) -#define bFM4_GPIO_EPFR18_QAIN3S1 *((volatile unsigned int*)(0x42DEC914UL)) -#define bFM4_GPIO_EPFR18_QBIN3S0 *((volatile unsigned int*)(0x42DEC918UL)) -#define bFM4_GPIO_EPFR18_QBIN3S1 *((volatile unsigned int*)(0x42DEC91CUL)) -#define bFM4_GPIO_EPFR18_QZIN3S0 *((volatile unsigned int*)(0x42DEC920UL)) -#define bFM4_GPIO_EPFR18_QZIN3S1 *((volatile unsigned int*)(0x42DEC924UL)) -#define bFM4_GPIO_EPFR18_SDCLKE0 *((volatile unsigned int*)(0x42DEC938UL)) -#define bFM4_GPIO_EPFR18_SDCLKE1 *((volatile unsigned int*)(0x42DEC93CUL)) -#define bFM4_GPIO_EPFR18_SDCMDB0 *((volatile unsigned int*)(0x42DEC940UL)) -#define bFM4_GPIO_EPFR18_SDCMDB1 *((volatile unsigned int*)(0x42DEC944UL)) -#define bFM4_GPIO_EPFR18_SDDATA0B0 *((volatile unsigned int*)(0x42DEC948UL)) -#define bFM4_GPIO_EPFR18_SDDATA0B1 *((volatile unsigned int*)(0x42DEC94CUL)) -#define bFM4_GPIO_EPFR18_SDDATA1B0 *((volatile unsigned int*)(0x42DEC950UL)) -#define bFM4_GPIO_EPFR18_SDDATA1B1 *((volatile unsigned int*)(0x42DEC954UL)) -#define bFM4_GPIO_EPFR18_SDDATA2B0 *((volatile unsigned int*)(0x42DEC958UL)) -#define bFM4_GPIO_EPFR18_SDDATA2B1 *((volatile unsigned int*)(0x42DEC95CUL)) -#define bFM4_GPIO_EPFR18_SDDATA3B0 *((volatile unsigned int*)(0x42DEC960UL)) -#define bFM4_GPIO_EPFR18_SDDATA3B1 *((volatile unsigned int*)(0x42DEC964UL)) -#define bFM4_GPIO_EPFR18_SDCDS0 *((volatile unsigned int*)(0x42DEC968UL)) -#define bFM4_GPIO_EPFR18_SDCDS1 *((volatile unsigned int*)(0x42DEC96CUL)) -#define bFM4_GPIO_EPFR18_SDWPS0 *((volatile unsigned int*)(0x42DEC970UL)) -#define bFM4_GPIO_EPFR18_SDWPS1 *((volatile unsigned int*)(0x42DEC974UL)) -#define bFM4_GPIO_EPFR20_UESMCKE *((volatile unsigned int*)(0x42DECA00UL)) -#define bFM4_GPIO_EPFR20_UESMCEE *((volatile unsigned int*)(0x42DECA04UL)) -#define bFM4_GPIO_EPFR20_UERASE *((volatile unsigned int*)(0x42DECA08UL)) -#define bFM4_GPIO_EPFR20_UECASE *((volatile unsigned int*)(0x42DECA0CUL)) -#define bFM4_GPIO_EPFR20_UEDWEXE *((volatile unsigned int*)(0x42DECA10UL)) -#define bFM4_GPIO_EPFR20_UECSXE *((volatile unsigned int*)(0x42DECA14UL)) -#define bFM4_GPIO_EPFR20_UEDQM2E *((volatile unsigned int*)(0x42DECA18UL)) -#define bFM4_GPIO_EPFR20_UEDQM3E *((volatile unsigned int*)(0x42DECA1CUL)) -#define bFM4_GPIO_EPFR20_UEDTHHB *((volatile unsigned int*)(0x42DECA20UL)) -#define bFM4_GPIO_EPFR20_UED16B *((volatile unsigned int*)(0x42DECA24UL)) -#define bFM4_GPIO_EPFR20_UED17B *((volatile unsigned int*)(0x42DECA28UL)) -#define bFM4_GPIO_EPFR20_UED18B *((volatile unsigned int*)(0x42DECA2CUL)) -#define bFM4_GPIO_EPFR20_UED19B *((volatile unsigned int*)(0x42DECA30UL)) -#define bFM4_GPIO_EPFR20_UED20B *((volatile unsigned int*)(0x42DECA34UL)) -#define bFM4_GPIO_EPFR20_UED21B *((volatile unsigned int*)(0x42DECA38UL)) -#define bFM4_GPIO_EPFR20_UED22B *((volatile unsigned int*)(0x42DECA3CUL)) -#define bFM4_GPIO_EPFR20_UED23B *((volatile unsigned int*)(0x42DECA40UL)) -#define bFM4_GPIO_EPFR20_UED24B *((volatile unsigned int*)(0x42DECA44UL)) -#define bFM4_GPIO_EPFR20_UED25B *((volatile unsigned int*)(0x42DECA48UL)) -#define bFM4_GPIO_EPFR20_UED26B *((volatile unsigned int*)(0x42DECA4CUL)) -#define bFM4_GPIO_EPFR20_UED27B *((volatile unsigned int*)(0x42DECA50UL)) -#define bFM4_GPIO_EPFR20_UED28B *((volatile unsigned int*)(0x42DECA54UL)) -#define bFM4_GPIO_EPFR20_UED29B *((volatile unsigned int*)(0x42DECA58UL)) -#define bFM4_GPIO_EPFR20_UED30B *((volatile unsigned int*)(0x42DECA5CUL)) -#define bFM4_GPIO_EPFR20_UED31B *((volatile unsigned int*)(0x42DECA60UL)) -#define bFM4_GPIO_PZR0_P00 *((volatile unsigned int*)(0x42DEE000UL)) -#define bFM4_GPIO_PZR0_P01 *((volatile unsigned int*)(0x42DEE004UL)) -#define bFM4_GPIO_PZR0_P02 *((volatile unsigned int*)(0x42DEE008UL)) -#define bFM4_GPIO_PZR0_P03 *((volatile unsigned int*)(0x42DEE00CUL)) -#define bFM4_GPIO_PZR0_P04 *((volatile unsigned int*)(0x42DEE010UL)) -#define bFM4_GPIO_PZR0_P05 *((volatile unsigned int*)(0x42DEE014UL)) -#define bFM4_GPIO_PZR0_P06 *((volatile unsigned int*)(0x42DEE018UL)) -#define bFM4_GPIO_PZR0_P07 *((volatile unsigned int*)(0x42DEE01CUL)) -#define bFM4_GPIO_PZR0_P08 *((volatile unsigned int*)(0x42DEE020UL)) -#define bFM4_GPIO_PZR0_P09 *((volatile unsigned int*)(0x42DEE024UL)) -#define bFM4_GPIO_PZR0_P0A *((volatile unsigned int*)(0x42DEE028UL)) -#define bFM4_GPIO_PZR0_P0B *((volatile unsigned int*)(0x42DEE02CUL)) -#define bFM4_GPIO_PZR0_P0C *((volatile unsigned int*)(0x42DEE030UL)) -#define bFM4_GPIO_PZR0_P0D *((volatile unsigned int*)(0x42DEE034UL)) -#define bFM4_GPIO_PZR0_P0E *((volatile unsigned int*)(0x42DEE038UL)) -#define bFM4_GPIO_PZR0_P0F *((volatile unsigned int*)(0x42DEE03CUL)) -#define bFM4_GPIO_PZR1_P10 *((volatile unsigned int*)(0x42DEE080UL)) -#define bFM4_GPIO_PZR1_P11 *((volatile unsigned int*)(0x42DEE084UL)) -#define bFM4_GPIO_PZR1_P12 *((volatile unsigned int*)(0x42DEE088UL)) -#define bFM4_GPIO_PZR1_P13 *((volatile unsigned int*)(0x42DEE08CUL)) -#define bFM4_GPIO_PZR1_P14 *((volatile unsigned int*)(0x42DEE090UL)) -#define bFM4_GPIO_PZR1_P15 *((volatile unsigned int*)(0x42DEE094UL)) -#define bFM4_GPIO_PZR1_P16 *((volatile unsigned int*)(0x42DEE098UL)) -#define bFM4_GPIO_PZR1_P17 *((volatile unsigned int*)(0x42DEE09CUL)) -#define bFM4_GPIO_PZR1_P18 *((volatile unsigned int*)(0x42DEE0A0UL)) -#define bFM4_GPIO_PZR1_P19 *((volatile unsigned int*)(0x42DEE0A4UL)) -#define bFM4_GPIO_PZR1_P1A *((volatile unsigned int*)(0x42DEE0A8UL)) -#define bFM4_GPIO_PZR1_P1B *((volatile unsigned int*)(0x42DEE0ACUL)) -#define bFM4_GPIO_PZR1_P1C *((volatile unsigned int*)(0x42DEE0B0UL)) -#define bFM4_GPIO_PZR1_P1D *((volatile unsigned int*)(0x42DEE0B4UL)) -#define bFM4_GPIO_PZR1_P1E *((volatile unsigned int*)(0x42DEE0B8UL)) -#define bFM4_GPIO_PZR1_P1F *((volatile unsigned int*)(0x42DEE0BCUL)) -#define bFM4_GPIO_PZR2_P20 *((volatile unsigned int*)(0x42DEE100UL)) -#define bFM4_GPIO_PZR2_P21 *((volatile unsigned int*)(0x42DEE104UL)) -#define bFM4_GPIO_PZR2_P22 *((volatile unsigned int*)(0x42DEE108UL)) -#define bFM4_GPIO_PZR2_P23 *((volatile unsigned int*)(0x42DEE10CUL)) -#define bFM4_GPIO_PZR2_P24 *((volatile unsigned int*)(0x42DEE110UL)) -#define bFM4_GPIO_PZR2_P25 *((volatile unsigned int*)(0x42DEE114UL)) -#define bFM4_GPIO_PZR2_P26 *((volatile unsigned int*)(0x42DEE118UL)) -#define bFM4_GPIO_PZR2_P27 *((volatile unsigned int*)(0x42DEE11CUL)) -#define bFM4_GPIO_PZR3_P30 *((volatile unsigned int*)(0x42DEE180UL)) -#define bFM4_GPIO_PZR3_P31 *((volatile unsigned int*)(0x42DEE184UL)) -#define bFM4_GPIO_PZR3_P32 *((volatile unsigned int*)(0x42DEE188UL)) -#define bFM4_GPIO_PZR3_P33 *((volatile unsigned int*)(0x42DEE18CUL)) -#define bFM4_GPIO_PZR3_P34 *((volatile unsigned int*)(0x42DEE190UL)) -#define bFM4_GPIO_PZR3_P35 *((volatile unsigned int*)(0x42DEE194UL)) -#define bFM4_GPIO_PZR3_P36 *((volatile unsigned int*)(0x42DEE198UL)) -#define bFM4_GPIO_PZR3_P37 *((volatile unsigned int*)(0x42DEE19CUL)) -#define bFM4_GPIO_PZR3_P38 *((volatile unsigned int*)(0x42DEE1A0UL)) -#define bFM4_GPIO_PZR3_P39 *((volatile unsigned int*)(0x42DEE1A4UL)) -#define bFM4_GPIO_PZR3_P3A *((volatile unsigned int*)(0x42DEE1A8UL)) -#define bFM4_GPIO_PZR3_P3B *((volatile unsigned int*)(0x42DEE1ACUL)) -#define bFM4_GPIO_PZR3_P3C *((volatile unsigned int*)(0x42DEE1B0UL)) -#define bFM4_GPIO_PZR3_P3D *((volatile unsigned int*)(0x42DEE1B4UL)) -#define bFM4_GPIO_PZR3_P3E *((volatile unsigned int*)(0x42DEE1B8UL)) -#define bFM4_GPIO_PZR3_P3F *((volatile unsigned int*)(0x42DEE1BCUL)) -#define bFM4_GPIO_PZR4_P40 *((volatile unsigned int*)(0x42DEE200UL)) -#define bFM4_GPIO_PZR4_P41 *((volatile unsigned int*)(0x42DEE204UL)) -#define bFM4_GPIO_PZR4_P42 *((volatile unsigned int*)(0x42DEE208UL)) -#define bFM4_GPIO_PZR4_P43 *((volatile unsigned int*)(0x42DEE20CUL)) -#define bFM4_GPIO_PZR4_P44 *((volatile unsigned int*)(0x42DEE210UL)) -#define bFM4_GPIO_PZR4_P45 *((volatile unsigned int*)(0x42DEE214UL)) -#define bFM4_GPIO_PZR4_P46 *((volatile unsigned int*)(0x42DEE218UL)) -#define bFM4_GPIO_PZR4_P47 *((volatile unsigned int*)(0x42DEE21CUL)) -#define bFM4_GPIO_PZR4_P48 *((volatile unsigned int*)(0x42DEE220UL)) -#define bFM4_GPIO_PZR4_P49 *((volatile unsigned int*)(0x42DEE224UL)) -#define bFM4_GPIO_PZR4_P4A *((volatile unsigned int*)(0x42DEE228UL)) -#define bFM4_GPIO_PZR4_P4B *((volatile unsigned int*)(0x42DEE22CUL)) -#define bFM4_GPIO_PZR4_P4C *((volatile unsigned int*)(0x42DEE230UL)) -#define bFM4_GPIO_PZR4_P4D *((volatile unsigned int*)(0x42DEE234UL)) -#define bFM4_GPIO_PZR4_P4E *((volatile unsigned int*)(0x42DEE238UL)) -#define bFM4_GPIO_PZR5_P50 *((volatile unsigned int*)(0x42DEE280UL)) -#define bFM4_GPIO_PZR5_P51 *((volatile unsigned int*)(0x42DEE284UL)) -#define bFM4_GPIO_PZR5_P52 *((volatile unsigned int*)(0x42DEE288UL)) -#define bFM4_GPIO_PZR5_P53 *((volatile unsigned int*)(0x42DEE28CUL)) -#define bFM4_GPIO_PZR5_P54 *((volatile unsigned int*)(0x42DEE290UL)) -#define bFM4_GPIO_PZR5_P55 *((volatile unsigned int*)(0x42DEE294UL)) -#define bFM4_GPIO_PZR5_P56 *((volatile unsigned int*)(0x42DEE298UL)) -#define bFM4_GPIO_PZR5_P57 *((volatile unsigned int*)(0x42DEE29CUL)) -#define bFM4_GPIO_PZR5_P58 *((volatile unsigned int*)(0x42DEE2A0UL)) -#define bFM4_GPIO_PZR5_P59 *((volatile unsigned int*)(0x42DEE2A4UL)) -#define bFM4_GPIO_PZR5_P5A *((volatile unsigned int*)(0x42DEE2A8UL)) -#define bFM4_GPIO_PZR5_P5B *((volatile unsigned int*)(0x42DEE2ACUL)) -#define bFM4_GPIO_PZR6_P60 *((volatile unsigned int*)(0x42DEE300UL)) -#define bFM4_GPIO_PZR6_P61 *((volatile unsigned int*)(0x42DEE304UL)) -#define bFM4_GPIO_PZR6_P62 *((volatile unsigned int*)(0x42DEE308UL)) -#define bFM4_GPIO_PZR6_P63 *((volatile unsigned int*)(0x42DEE30CUL)) -#define bFM4_GPIO_PZR6_P64 *((volatile unsigned int*)(0x42DEE310UL)) -#define bFM4_GPIO_PZR6_P65 *((volatile unsigned int*)(0x42DEE314UL)) -#define bFM4_GPIO_PZR6_P66 *((volatile unsigned int*)(0x42DEE318UL)) -#define bFM4_GPIO_PZR6_P67 *((volatile unsigned int*)(0x42DEE31CUL)) -#define bFM4_GPIO_PZR6_P68 *((volatile unsigned int*)(0x42DEE320UL)) -#define bFM4_GPIO_PZR7_P70 *((volatile unsigned int*)(0x42DEE380UL)) -#define bFM4_GPIO_PZR7_P71 *((volatile unsigned int*)(0x42DEE384UL)) -#define bFM4_GPIO_PZR7_P72 *((volatile unsigned int*)(0x42DEE388UL)) -#define bFM4_GPIO_PZR7_P73 *((volatile unsigned int*)(0x42DEE38CUL)) -#define bFM4_GPIO_PZR7_P74 *((volatile unsigned int*)(0x42DEE390UL)) -#define bFM4_GPIO_PZR8_P80 *((volatile unsigned int*)(0x42DEE400UL)) -#define bFM4_GPIO_PZR8_P81 *((volatile unsigned int*)(0x42DEE404UL)) -#define bFM4_GPIO_PZRE_PE0 *((volatile unsigned int*)(0x42DEE700UL)) -#define bFM4_GPIO_PZRE_PE2 *((volatile unsigned int*)(0x42DEE708UL)) -#define bFM4_GPIO_PZRE_PE3 *((volatile unsigned int*)(0x42DEE70CUL)) - -/* Low voltage detection registers */ -#define bFM4_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM4_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM4_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM4_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM4_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM4_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM4_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM4_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* DS mode registers */ -#define bFM4_DS_RCK_CTL_RTCCKE *((volatile unsigned int*)(0x426A2080UL)) -#define bFM4_DS_PMD_CTL_RTCE *((volatile unsigned int*)(0x426B0000UL)) -#define bFM4_DS_WRFSR_WINITX *((volatile unsigned int*)(0x426B0080UL)) -#define bFM4_DS_WRFSR_WLVDH *((volatile unsigned int*)(0x426B0084UL)) -#define bFM4_DS_WIFSR_WRTCI *((volatile unsigned int*)(0x426B0100UL)) -#define bFM4_DS_WIFSR_WLVDI *((volatile unsigned int*)(0x426B0104UL)) -#define bFM4_DS_WIFSR_WUI0 *((volatile unsigned int*)(0x426B0108UL)) -#define bFM4_DS_WIFSR_WUI1 *((volatile unsigned int*)(0x426B010CUL)) -#define bFM4_DS_WIFSR_WUI2 *((volatile unsigned int*)(0x426B0110UL)) -#define bFM4_DS_WIFSR_WUI3 *((volatile unsigned int*)(0x426B0114UL)) -#define bFM4_DS_WIFSR_WUI4 *((volatile unsigned int*)(0x426B0118UL)) -#define bFM4_DS_WIFSR_WUI5 *((volatile unsigned int*)(0x426B011CUL)) -#define bFM4_DS_WIER_WRTCE *((volatile unsigned int*)(0x426B0180UL)) -#define bFM4_DS_WIER_WLVDE *((volatile unsigned int*)(0x426B0184UL)) -#define bFM4_DS_WIER_WUI1E *((volatile unsigned int*)(0x426B018CUL)) -#define bFM4_DS_WIER_WUI2E *((volatile unsigned int*)(0x426B0190UL)) -#define bFM4_DS_WIER_WUI3E *((volatile unsigned int*)(0x426B0194UL)) -#define bFM4_DS_WIER_WUI4E *((volatile unsigned int*)(0x426B0198UL)) -#define bFM4_DS_WIER_WUI5E *((volatile unsigned int*)(0x426B019CUL)) -#define bFM4_DS_WILVR_WUI1LV *((volatile unsigned int*)(0x426B0200UL)) -#define bFM4_DS_WILVR_WUI2LV *((volatile unsigned int*)(0x426B0204UL)) -#define bFM4_DS_WILVR_WUI3LV *((volatile unsigned int*)(0x426B0208UL)) -#define bFM4_DS_WILVR_WUI4LV *((volatile unsigned int*)(0x426B020CUL)) -#define bFM4_DS_WILVR_WUI5LV *((volatile unsigned int*)(0x426B0210UL)) -#define bFM4_DS_DSRAMR_SRAMR0 *((volatile unsigned int*)(0x426B0280UL)) -#define bFM4_DS_DSRAMR_SRAMR1 *((volatile unsigned int*)(0x426B0284UL)) - -/* USB clock registers */ -#define bFM4_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) -#define bFM4_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) -#define bFM4_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM4_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM4_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM4_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM4_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM4_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM4_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM4_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM4_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM4_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM4_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM4_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM4_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM4_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM4_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM4_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM4_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM4_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM4_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM4_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) - -/* CAN prescaler register */ -#define bFM4_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) -#define bFM4_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) -#define bFM4_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) -#define bFM4_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) - -/* MFS UART channel 0 registers */ -#define bFM4_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM4_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM4_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM4_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM4_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM4_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM4_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM4_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM4_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM4_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM4_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM4_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM4_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM4_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM4_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM4_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM4_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM4_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM4_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM4_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM4_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM4_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM4_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM4_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM4_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM4_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM4_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM4_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM4_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM4_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM4_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM4_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM4_MFS0_UART_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_UART_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_UART_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_UART_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_UART_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_UART_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_UART_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_UART_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_UART_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_UART_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_UART_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_UART_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_UART_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_UART_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_UART_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_UART_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_UART_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_UART_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) -#define bFM4_MFS0_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) - -/* MFS CSIO channel 0 registers */ -#define bFM4_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM4_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM4_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM4_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM4_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM4_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM4_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM4_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM4_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM4_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM4_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM4_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM4_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM4_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM4_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM4_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM4_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM4_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM4_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM4_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM4_MFS0_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42700098UL)) -#define bFM4_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM4_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM4_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM4_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM4_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM4_MFS0_CSIO_SSR_AWC *((volatile unsigned int*)(0x427000B0UL)) -#define bFM4_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM4_MFS0_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_CSIO_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_CSIO_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_CSIO_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42700380UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42700384UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42700388UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270038CUL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42700390UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42700394UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42700398UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270039CUL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427003A0UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427003A4UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427003A8UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427003ACUL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427003B0UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427003B4UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427003B8UL)) -#define bFM4_MFS0_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427003BCUL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42700400UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42700404UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42700408UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270040CUL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42700410UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42700414UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42700418UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270041CUL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42700420UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42700424UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42700428UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270042CUL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42700430UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42700434UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42700438UL)) -#define bFM4_MFS0_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270043CUL)) -#define bFM4_MFS0_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42700480UL)) -#define bFM4_MFS0_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42700484UL)) -#define bFM4_MFS0_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42700488UL)) -#define bFM4_MFS0_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270048CUL)) -#define bFM4_MFS0_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42700490UL)) -#define bFM4_MFS0_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42700498UL)) -#define bFM4_MFS0_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270049CUL)) -#define bFM4_MFS0_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427004A0UL)) -#define bFM4_MFS0_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427004ACUL)) -#define bFM4_MFS0_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427004B0UL)) -#define bFM4_MFS0_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427004B4UL)) -#define bFM4_MFS0_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42700500UL)) -#define bFM4_MFS0_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42700504UL)) -#define bFM4_MFS0_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42700508UL)) -#define bFM4_MFS0_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270050CUL)) -#define bFM4_MFS0_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42700510UL)) -#define bFM4_MFS0_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42700514UL)) -#define bFM4_MFS0_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42700518UL)) -#define bFM4_MFS0_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270051CUL)) -#define bFM4_MFS0_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42700520UL)) -#define bFM4_MFS0_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42700524UL)) -#define bFM4_MFS0_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42700528UL)) -#define bFM4_MFS0_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270052CUL)) -#define bFM4_MFS0_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42700530UL)) -#define bFM4_MFS0_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42700534UL)) -#define bFM4_MFS0_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42700538UL)) -#define bFM4_MFS0_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270053CUL)) -#define bFM4_MFS0_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42700580UL)) -#define bFM4_MFS0_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42700584UL)) -#define bFM4_MFS0_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42700588UL)) -#define bFM4_MFS0_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270058CUL)) -#define bFM4_MFS0_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42700590UL)) -#define bFM4_MFS0_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42700594UL)) -#define bFM4_MFS0_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42700598UL)) -#define bFM4_MFS0_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270059CUL)) -#define bFM4_MFS0_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427005A0UL)) -#define bFM4_MFS0_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427005A4UL)) -#define bFM4_MFS0_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427005A8UL)) -#define bFM4_MFS0_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427005ACUL)) -#define bFM4_MFS0_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427005B0UL)) -#define bFM4_MFS0_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427005B4UL)) -#define bFM4_MFS0_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427005B8UL)) -#define bFM4_MFS0_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427005BCUL)) -#define bFM4_MFS0_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42700600UL)) -#define bFM4_MFS0_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42700604UL)) -#define bFM4_MFS0_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42700614UL)) -#define bFM4_MFS0_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42700618UL)) -#define bFM4_MFS0_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270061CUL)) -#define bFM4_MFS0_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42700620UL)) -#define bFM4_MFS0_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42700624UL)) - -/* MFS LIN channel 0 registers */ -#define bFM4_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM4_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM4_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM4_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM4_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM4_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM4_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM4_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM4_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM4_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM4_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM4_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM4_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM4_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM4_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM4_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM4_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM4_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM4_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM4_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM4_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM4_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM4_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM4_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM4_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM4_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM4_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM4_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM4_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM4_MFS0_LIN_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_LIN_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_LIN_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_LIN_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_LIN_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_LIN_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_LIN_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_LIN_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_LIN_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_LIN_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) -#define bFM4_MFS0_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) - -/* MFS I2C channel 0 registers */ -#define bFM4_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM4_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM4_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM4_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM4_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM4_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM4_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM4_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM4_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM4_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM4_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM4_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM4_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM4_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM4_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM4_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM4_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM4_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM4_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM4_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM4_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM4_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM4_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM4_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM4_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM4_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM4_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM4_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM4_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM4_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM4_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM4_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM4_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM4_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM4_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM4_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM4_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM4_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM4_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM4_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM4_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM4_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM4_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM4_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM4_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM4_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) -#define bFM4_MFS0_I2C_FCR_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_I2C_FCR_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_I2C_FCR_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_I2C_FCR_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_I2C_FCR_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_I2C_FCR_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_I2C_FCR_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42700280UL)) -#define bFM4_MFS0_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42700284UL)) -#define bFM4_MFS0_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42700288UL)) -#define bFM4_MFS0_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270028CUL)) -#define bFM4_MFS0_I2C_FCR0_FSET *((volatile unsigned int*)(0x42700290UL)) -#define bFM4_MFS0_I2C_FCR0_FLD *((volatile unsigned int*)(0x42700294UL)) -#define bFM4_MFS0_I2C_FCR0_FLST *((volatile unsigned int*)(0x42700298UL)) -#define bFM4_MFS0_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427002A0UL)) -#define bFM4_MFS0_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427002A4UL)) -#define bFM4_MFS0_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427002A8UL)) -#define bFM4_MFS0_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427002ACUL)) -#define bFM4_MFS0_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427002B0UL)) -#define bFM4_MFS0_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270033CUL)) -#define bFM4_MFS0_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42700300UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42700304UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42700308UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270030CUL)) -#define bFM4_MFS0_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42700310UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42700314UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42700318UL)) -#define bFM4_MFS0_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270031CUL)) -#define bFM4_MFS0_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42700320UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42700324UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42700328UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270032CUL)) -#define bFM4_MFS0_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42700330UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42700334UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42700338UL)) -#define bFM4_MFS0_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270033CUL)) - -/* MFS UART channel 1 registers */ -#define bFM4_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM4_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM4_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM4_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM4_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM4_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM4_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM4_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM4_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM4_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM4_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM4_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM4_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM4_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM4_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM4_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM4_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM4_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM4_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM4_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM4_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM4_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM4_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM4_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM4_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM4_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM4_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM4_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM4_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM4_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM4_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM4_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM4_MFS1_UART_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_UART_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_UART_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_UART_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_UART_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_UART_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_UART_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_UART_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_UART_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_UART_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_UART_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_UART_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_UART_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_UART_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_UART_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_UART_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_UART_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_UART_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) -#define bFM4_MFS1_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) - -/* MFS CSIO channel 1 registers */ -#define bFM4_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM4_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM4_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM4_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM4_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM4_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM4_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM4_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM4_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM4_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM4_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM4_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM4_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM4_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM4_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM4_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM4_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM4_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM4_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM4_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM4_MFS1_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42702098UL)) -#define bFM4_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM4_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM4_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM4_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM4_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM4_MFS1_CSIO_SSR_AWC *((volatile unsigned int*)(0x427020B0UL)) -#define bFM4_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM4_MFS1_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_CSIO_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_CSIO_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_CSIO_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42702380UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42702384UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42702388UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270238CUL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42702390UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42702394UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42702398UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270239CUL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427023A0UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427023A4UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427023A8UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427023ACUL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427023B0UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427023B4UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427023B8UL)) -#define bFM4_MFS1_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427023BCUL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42702400UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42702404UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42702408UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270240CUL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42702410UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42702414UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42702418UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270241CUL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42702420UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42702424UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42702428UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270242CUL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42702430UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42702434UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42702438UL)) -#define bFM4_MFS1_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270243CUL)) -#define bFM4_MFS1_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42702480UL)) -#define bFM4_MFS1_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42702484UL)) -#define bFM4_MFS1_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42702488UL)) -#define bFM4_MFS1_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270248CUL)) -#define bFM4_MFS1_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42702490UL)) -#define bFM4_MFS1_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42702498UL)) -#define bFM4_MFS1_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270249CUL)) -#define bFM4_MFS1_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427024A0UL)) -#define bFM4_MFS1_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427024ACUL)) -#define bFM4_MFS1_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427024B0UL)) -#define bFM4_MFS1_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427024B4UL)) -#define bFM4_MFS1_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42702500UL)) -#define bFM4_MFS1_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42702504UL)) -#define bFM4_MFS1_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42702508UL)) -#define bFM4_MFS1_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270250CUL)) -#define bFM4_MFS1_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42702510UL)) -#define bFM4_MFS1_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42702514UL)) -#define bFM4_MFS1_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42702518UL)) -#define bFM4_MFS1_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270251CUL)) -#define bFM4_MFS1_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42702520UL)) -#define bFM4_MFS1_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42702524UL)) -#define bFM4_MFS1_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42702528UL)) -#define bFM4_MFS1_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270252CUL)) -#define bFM4_MFS1_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42702530UL)) -#define bFM4_MFS1_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42702534UL)) -#define bFM4_MFS1_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42702538UL)) -#define bFM4_MFS1_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270253CUL)) -#define bFM4_MFS1_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42702580UL)) -#define bFM4_MFS1_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42702584UL)) -#define bFM4_MFS1_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42702588UL)) -#define bFM4_MFS1_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270258CUL)) -#define bFM4_MFS1_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42702590UL)) -#define bFM4_MFS1_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42702594UL)) -#define bFM4_MFS1_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42702598UL)) -#define bFM4_MFS1_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270259CUL)) -#define bFM4_MFS1_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427025A0UL)) -#define bFM4_MFS1_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427025A4UL)) -#define bFM4_MFS1_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427025A8UL)) -#define bFM4_MFS1_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427025ACUL)) -#define bFM4_MFS1_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427025B0UL)) -#define bFM4_MFS1_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427025B4UL)) -#define bFM4_MFS1_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427025B8UL)) -#define bFM4_MFS1_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427025BCUL)) -#define bFM4_MFS1_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42702600UL)) -#define bFM4_MFS1_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42702604UL)) -#define bFM4_MFS1_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42702614UL)) -#define bFM4_MFS1_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42702618UL)) -#define bFM4_MFS1_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270261CUL)) -#define bFM4_MFS1_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42702620UL)) -#define bFM4_MFS1_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42702624UL)) - -/* MFS LIN channel 1 registers */ -#define bFM4_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM4_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM4_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM4_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM4_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM4_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM4_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM4_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM4_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM4_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM4_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM4_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM4_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM4_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM4_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM4_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM4_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM4_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM4_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM4_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM4_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM4_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM4_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM4_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM4_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM4_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM4_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM4_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM4_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM4_MFS1_LIN_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_LIN_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_LIN_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_LIN_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_LIN_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_LIN_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_LIN_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_LIN_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_LIN_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_LIN_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) -#define bFM4_MFS1_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) - -/* MFS I2C channel 1 registers */ -#define bFM4_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM4_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM4_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM4_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM4_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM4_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM4_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM4_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM4_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM4_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM4_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM4_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM4_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM4_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM4_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM4_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM4_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM4_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM4_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM4_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM4_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM4_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM4_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM4_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM4_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM4_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM4_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM4_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM4_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM4_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM4_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM4_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM4_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM4_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM4_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM4_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM4_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM4_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM4_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM4_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM4_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM4_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM4_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM4_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM4_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM4_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) -#define bFM4_MFS1_I2C_FCR_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_I2C_FCR_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_I2C_FCR_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_I2C_FCR_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_I2C_FCR_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_I2C_FCR_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_I2C_FCR_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42702280UL)) -#define bFM4_MFS1_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42702284UL)) -#define bFM4_MFS1_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42702288UL)) -#define bFM4_MFS1_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270228CUL)) -#define bFM4_MFS1_I2C_FCR0_FSET *((volatile unsigned int*)(0x42702290UL)) -#define bFM4_MFS1_I2C_FCR0_FLD *((volatile unsigned int*)(0x42702294UL)) -#define bFM4_MFS1_I2C_FCR0_FLST *((volatile unsigned int*)(0x42702298UL)) -#define bFM4_MFS1_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427022A0UL)) -#define bFM4_MFS1_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427022A4UL)) -#define bFM4_MFS1_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427022A8UL)) -#define bFM4_MFS1_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427022ACUL)) -#define bFM4_MFS1_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427022B0UL)) -#define bFM4_MFS1_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270233CUL)) -#define bFM4_MFS1_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42702300UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42702304UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42702308UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270230CUL)) -#define bFM4_MFS1_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42702310UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42702314UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42702318UL)) -#define bFM4_MFS1_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270231CUL)) -#define bFM4_MFS1_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42702320UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42702324UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42702328UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270232CUL)) -#define bFM4_MFS1_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42702330UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42702334UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42702338UL)) -#define bFM4_MFS1_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270233CUL)) - -/* MFS UART channel 2 registers */ -#define bFM4_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM4_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM4_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM4_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM4_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM4_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM4_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM4_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM4_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM4_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM4_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM4_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM4_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM4_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM4_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM4_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM4_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM4_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM4_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM4_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM4_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM4_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM4_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM4_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM4_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM4_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM4_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM4_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM4_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM4_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM4_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM4_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM4_MFS2_UART_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_UART_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_UART_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_UART_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_UART_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_UART_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_UART_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_UART_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_UART_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_UART_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_UART_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_UART_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_UART_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_UART_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_UART_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_UART_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_UART_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_UART_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) -#define bFM4_MFS2_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) - -/* MFS CSIO channel 2 registers */ -#define bFM4_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM4_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM4_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM4_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM4_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM4_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM4_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM4_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM4_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM4_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM4_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM4_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM4_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM4_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM4_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM4_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM4_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM4_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM4_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM4_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM4_MFS2_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42704098UL)) -#define bFM4_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM4_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM4_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM4_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM4_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM4_MFS2_CSIO_SSR_AWC *((volatile unsigned int*)(0x427040B0UL)) -#define bFM4_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM4_MFS2_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_CSIO_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_CSIO_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_CSIO_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42704380UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42704384UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42704388UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270438CUL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42704390UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42704394UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42704398UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270439CUL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427043A0UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427043A4UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427043A8UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427043ACUL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427043B0UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427043B4UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427043B8UL)) -#define bFM4_MFS2_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427043BCUL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42704400UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42704404UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42704408UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270440CUL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42704410UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42704414UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42704418UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270441CUL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42704420UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42704424UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42704428UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270442CUL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42704430UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42704434UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42704438UL)) -#define bFM4_MFS2_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270443CUL)) -#define bFM4_MFS2_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42704480UL)) -#define bFM4_MFS2_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42704484UL)) -#define bFM4_MFS2_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42704488UL)) -#define bFM4_MFS2_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270448CUL)) -#define bFM4_MFS2_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42704490UL)) -#define bFM4_MFS2_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42704498UL)) -#define bFM4_MFS2_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270449CUL)) -#define bFM4_MFS2_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427044A0UL)) -#define bFM4_MFS2_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427044ACUL)) -#define bFM4_MFS2_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427044B0UL)) -#define bFM4_MFS2_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427044B4UL)) -#define bFM4_MFS2_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42704500UL)) -#define bFM4_MFS2_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42704504UL)) -#define bFM4_MFS2_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42704508UL)) -#define bFM4_MFS2_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270450CUL)) -#define bFM4_MFS2_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42704510UL)) -#define bFM4_MFS2_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42704514UL)) -#define bFM4_MFS2_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42704518UL)) -#define bFM4_MFS2_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270451CUL)) -#define bFM4_MFS2_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42704520UL)) -#define bFM4_MFS2_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42704524UL)) -#define bFM4_MFS2_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42704528UL)) -#define bFM4_MFS2_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270452CUL)) -#define bFM4_MFS2_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42704530UL)) -#define bFM4_MFS2_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42704534UL)) -#define bFM4_MFS2_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42704538UL)) -#define bFM4_MFS2_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270453CUL)) -#define bFM4_MFS2_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42704580UL)) -#define bFM4_MFS2_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42704584UL)) -#define bFM4_MFS2_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42704588UL)) -#define bFM4_MFS2_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270458CUL)) -#define bFM4_MFS2_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42704590UL)) -#define bFM4_MFS2_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42704594UL)) -#define bFM4_MFS2_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42704598UL)) -#define bFM4_MFS2_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270459CUL)) -#define bFM4_MFS2_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427045A0UL)) -#define bFM4_MFS2_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427045A4UL)) -#define bFM4_MFS2_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427045A8UL)) -#define bFM4_MFS2_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427045ACUL)) -#define bFM4_MFS2_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427045B0UL)) -#define bFM4_MFS2_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427045B4UL)) -#define bFM4_MFS2_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427045B8UL)) -#define bFM4_MFS2_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427045BCUL)) -#define bFM4_MFS2_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42704600UL)) -#define bFM4_MFS2_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42704604UL)) -#define bFM4_MFS2_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42704614UL)) -#define bFM4_MFS2_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42704618UL)) -#define bFM4_MFS2_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270461CUL)) -#define bFM4_MFS2_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42704620UL)) -#define bFM4_MFS2_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42704624UL)) - -/* MFS LIN channel 2 registers */ -#define bFM4_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM4_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM4_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM4_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM4_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM4_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM4_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM4_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM4_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM4_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM4_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM4_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM4_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM4_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM4_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM4_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM4_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM4_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM4_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM4_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM4_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM4_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM4_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM4_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM4_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM4_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM4_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM4_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM4_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM4_MFS2_LIN_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_LIN_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_LIN_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_LIN_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_LIN_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_LIN_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_LIN_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_LIN_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_LIN_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_LIN_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) -#define bFM4_MFS2_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) - -/* MFS I2C channel 2 registers */ -#define bFM4_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM4_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM4_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM4_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM4_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM4_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM4_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM4_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM4_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM4_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM4_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM4_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM4_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM4_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM4_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM4_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM4_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM4_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM4_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM4_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM4_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM4_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM4_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM4_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM4_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM4_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM4_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM4_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM4_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM4_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM4_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM4_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM4_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM4_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM4_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM4_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM4_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM4_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM4_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM4_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM4_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM4_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM4_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM4_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM4_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM4_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) -#define bFM4_MFS2_I2C_FCR_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_I2C_FCR_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_I2C_FCR_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_I2C_FCR_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_I2C_FCR_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_I2C_FCR_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_I2C_FCR_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42704280UL)) -#define bFM4_MFS2_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42704284UL)) -#define bFM4_MFS2_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42704288UL)) -#define bFM4_MFS2_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270428CUL)) -#define bFM4_MFS2_I2C_FCR0_FSET *((volatile unsigned int*)(0x42704290UL)) -#define bFM4_MFS2_I2C_FCR0_FLD *((volatile unsigned int*)(0x42704294UL)) -#define bFM4_MFS2_I2C_FCR0_FLST *((volatile unsigned int*)(0x42704298UL)) -#define bFM4_MFS2_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427042A0UL)) -#define bFM4_MFS2_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427042A4UL)) -#define bFM4_MFS2_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427042A8UL)) -#define bFM4_MFS2_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427042ACUL)) -#define bFM4_MFS2_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427042B0UL)) -#define bFM4_MFS2_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270433CUL)) -#define bFM4_MFS2_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42704300UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42704304UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42704308UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270430CUL)) -#define bFM4_MFS2_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42704310UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42704314UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42704318UL)) -#define bFM4_MFS2_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270431CUL)) -#define bFM4_MFS2_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42704320UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42704324UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42704328UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270432CUL)) -#define bFM4_MFS2_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42704330UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42704334UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42704338UL)) -#define bFM4_MFS2_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270433CUL)) - -/* MFS UART channel 3 registers */ -#define bFM4_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM4_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM4_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM4_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM4_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM4_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM4_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM4_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM4_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM4_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM4_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM4_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM4_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM4_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM4_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM4_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM4_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM4_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM4_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM4_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM4_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM4_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM4_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM4_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM4_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM4_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM4_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM4_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM4_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM4_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM4_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM4_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM4_MFS3_UART_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_UART_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_UART_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_UART_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_UART_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_UART_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_UART_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_UART_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_UART_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_UART_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_UART_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_UART_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_UART_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_UART_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_UART_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_UART_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_UART_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_UART_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) -#define bFM4_MFS3_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) - -/* MFS CSIO channel 3 registers */ -#define bFM4_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM4_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM4_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM4_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM4_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM4_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM4_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM4_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM4_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM4_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM4_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM4_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM4_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM4_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM4_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM4_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM4_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM4_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM4_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM4_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM4_MFS3_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42706098UL)) -#define bFM4_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM4_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM4_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM4_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM4_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM4_MFS3_CSIO_SSR_AWC *((volatile unsigned int*)(0x427060B0UL)) -#define bFM4_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM4_MFS3_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_CSIO_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_CSIO_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_CSIO_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42706380UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42706384UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42706388UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270638CUL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42706390UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42706394UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42706398UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270639CUL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427063A0UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427063A4UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427063A8UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427063ACUL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427063B0UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427063B4UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427063B8UL)) -#define bFM4_MFS3_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427063BCUL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42706400UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42706404UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42706408UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270640CUL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42706410UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42706414UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42706418UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270641CUL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42706420UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42706424UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42706428UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270642CUL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42706430UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42706434UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42706438UL)) -#define bFM4_MFS3_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270643CUL)) -#define bFM4_MFS3_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42706480UL)) -#define bFM4_MFS3_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42706484UL)) -#define bFM4_MFS3_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42706488UL)) -#define bFM4_MFS3_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270648CUL)) -#define bFM4_MFS3_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42706490UL)) -#define bFM4_MFS3_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42706498UL)) -#define bFM4_MFS3_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270649CUL)) -#define bFM4_MFS3_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427064A0UL)) -#define bFM4_MFS3_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427064ACUL)) -#define bFM4_MFS3_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427064B0UL)) -#define bFM4_MFS3_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427064B4UL)) -#define bFM4_MFS3_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42706500UL)) -#define bFM4_MFS3_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42706504UL)) -#define bFM4_MFS3_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42706508UL)) -#define bFM4_MFS3_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270650CUL)) -#define bFM4_MFS3_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42706510UL)) -#define bFM4_MFS3_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42706514UL)) -#define bFM4_MFS3_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42706518UL)) -#define bFM4_MFS3_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270651CUL)) -#define bFM4_MFS3_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42706520UL)) -#define bFM4_MFS3_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42706524UL)) -#define bFM4_MFS3_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42706528UL)) -#define bFM4_MFS3_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270652CUL)) -#define bFM4_MFS3_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42706530UL)) -#define bFM4_MFS3_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42706534UL)) -#define bFM4_MFS3_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42706538UL)) -#define bFM4_MFS3_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270653CUL)) -#define bFM4_MFS3_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42706580UL)) -#define bFM4_MFS3_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42706584UL)) -#define bFM4_MFS3_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42706588UL)) -#define bFM4_MFS3_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270658CUL)) -#define bFM4_MFS3_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42706590UL)) -#define bFM4_MFS3_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42706594UL)) -#define bFM4_MFS3_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42706598UL)) -#define bFM4_MFS3_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270659CUL)) -#define bFM4_MFS3_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427065A0UL)) -#define bFM4_MFS3_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427065A4UL)) -#define bFM4_MFS3_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427065A8UL)) -#define bFM4_MFS3_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427065ACUL)) -#define bFM4_MFS3_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427065B0UL)) -#define bFM4_MFS3_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427065B4UL)) -#define bFM4_MFS3_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427065B8UL)) -#define bFM4_MFS3_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427065BCUL)) -#define bFM4_MFS3_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42706600UL)) -#define bFM4_MFS3_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42706604UL)) -#define bFM4_MFS3_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42706614UL)) -#define bFM4_MFS3_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42706618UL)) -#define bFM4_MFS3_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270661CUL)) -#define bFM4_MFS3_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42706620UL)) -#define bFM4_MFS3_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42706624UL)) - -/* MFS LIN channel 3 registers */ -#define bFM4_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM4_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM4_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM4_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM4_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM4_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM4_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM4_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM4_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM4_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM4_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM4_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM4_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM4_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM4_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM4_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM4_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM4_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM4_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM4_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM4_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM4_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM4_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM4_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM4_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM4_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM4_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM4_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM4_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM4_MFS3_LIN_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_LIN_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_LIN_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_LIN_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_LIN_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_LIN_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_LIN_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_LIN_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_LIN_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_LIN_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) -#define bFM4_MFS3_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) - -/* MFS I2C channel 3 registers */ -#define bFM4_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM4_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM4_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM4_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM4_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM4_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM4_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM4_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM4_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM4_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM4_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM4_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM4_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM4_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM4_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM4_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM4_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM4_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM4_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM4_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM4_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM4_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM4_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM4_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM4_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM4_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM4_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM4_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM4_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM4_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM4_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM4_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM4_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM4_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM4_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM4_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM4_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM4_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM4_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM4_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM4_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM4_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM4_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM4_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM4_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM4_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) -#define bFM4_MFS3_I2C_FCR_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_I2C_FCR_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_I2C_FCR_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_I2C_FCR_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_I2C_FCR_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_I2C_FCR_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_I2C_FCR_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42706280UL)) -#define bFM4_MFS3_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42706284UL)) -#define bFM4_MFS3_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42706288UL)) -#define bFM4_MFS3_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270628CUL)) -#define bFM4_MFS3_I2C_FCR0_FSET *((volatile unsigned int*)(0x42706290UL)) -#define bFM4_MFS3_I2C_FCR0_FLD *((volatile unsigned int*)(0x42706294UL)) -#define bFM4_MFS3_I2C_FCR0_FLST *((volatile unsigned int*)(0x42706298UL)) -#define bFM4_MFS3_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427062A0UL)) -#define bFM4_MFS3_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427062A4UL)) -#define bFM4_MFS3_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427062A8UL)) -#define bFM4_MFS3_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427062ACUL)) -#define bFM4_MFS3_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427062B0UL)) -#define bFM4_MFS3_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270633CUL)) -#define bFM4_MFS3_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42706300UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42706304UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42706308UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270630CUL)) -#define bFM4_MFS3_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42706310UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42706314UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42706318UL)) -#define bFM4_MFS3_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270631CUL)) -#define bFM4_MFS3_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42706320UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42706324UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42706328UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270632CUL)) -#define bFM4_MFS3_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42706330UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42706334UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42706338UL)) -#define bFM4_MFS3_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270633CUL)) - -/* MFS UART channel 4 registers */ -#define bFM4_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM4_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM4_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM4_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM4_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM4_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM4_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM4_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM4_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM4_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM4_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM4_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM4_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM4_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM4_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM4_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM4_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM4_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM4_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM4_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM4_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM4_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM4_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM4_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM4_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM4_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM4_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM4_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM4_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM4_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM4_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM4_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM4_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_UART_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM4_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* MFS CSIO channel 4 registers */ -#define bFM4_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM4_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM4_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM4_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM4_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM4_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM4_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM4_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM4_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM4_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM4_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM4_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM4_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM4_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM4_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM4_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM4_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM4_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM4_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM4_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM4_MFS4_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42708098UL)) -#define bFM4_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM4_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM4_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM4_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM4_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM4_MFS4_CSIO_SSR_AWC *((volatile unsigned int*)(0x427080B0UL)) -#define bFM4_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM4_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42708380UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42708384UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42708388UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270838CUL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42708390UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42708394UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42708398UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270839CUL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427083A0UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427083A4UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427083A8UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427083ACUL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427083B0UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427083B4UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427083B8UL)) -#define bFM4_MFS4_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427083BCUL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42708400UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42708404UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42708408UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270840CUL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42708410UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42708414UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42708418UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270841CUL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42708420UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42708424UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42708428UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270842CUL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42708430UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42708434UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42708438UL)) -#define bFM4_MFS4_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270843CUL)) -#define bFM4_MFS4_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42708480UL)) -#define bFM4_MFS4_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42708484UL)) -#define bFM4_MFS4_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42708488UL)) -#define bFM4_MFS4_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270848CUL)) -#define bFM4_MFS4_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42708490UL)) -#define bFM4_MFS4_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42708498UL)) -#define bFM4_MFS4_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270849CUL)) -#define bFM4_MFS4_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427084A0UL)) -#define bFM4_MFS4_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427084ACUL)) -#define bFM4_MFS4_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427084B0UL)) -#define bFM4_MFS4_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427084B4UL)) -#define bFM4_MFS4_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42708500UL)) -#define bFM4_MFS4_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42708504UL)) -#define bFM4_MFS4_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42708508UL)) -#define bFM4_MFS4_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270850CUL)) -#define bFM4_MFS4_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42708510UL)) -#define bFM4_MFS4_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42708514UL)) -#define bFM4_MFS4_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42708518UL)) -#define bFM4_MFS4_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270851CUL)) -#define bFM4_MFS4_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42708520UL)) -#define bFM4_MFS4_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42708524UL)) -#define bFM4_MFS4_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42708528UL)) -#define bFM4_MFS4_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270852CUL)) -#define bFM4_MFS4_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42708530UL)) -#define bFM4_MFS4_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42708534UL)) -#define bFM4_MFS4_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42708538UL)) -#define bFM4_MFS4_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270853CUL)) -#define bFM4_MFS4_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42708580UL)) -#define bFM4_MFS4_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42708584UL)) -#define bFM4_MFS4_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42708588UL)) -#define bFM4_MFS4_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270858CUL)) -#define bFM4_MFS4_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42708590UL)) -#define bFM4_MFS4_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42708594UL)) -#define bFM4_MFS4_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42708598UL)) -#define bFM4_MFS4_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270859CUL)) -#define bFM4_MFS4_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427085A0UL)) -#define bFM4_MFS4_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427085A4UL)) -#define bFM4_MFS4_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427085A8UL)) -#define bFM4_MFS4_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427085ACUL)) -#define bFM4_MFS4_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427085B0UL)) -#define bFM4_MFS4_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427085B4UL)) -#define bFM4_MFS4_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427085B8UL)) -#define bFM4_MFS4_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427085BCUL)) -#define bFM4_MFS4_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42708600UL)) -#define bFM4_MFS4_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42708604UL)) -#define bFM4_MFS4_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42708614UL)) -#define bFM4_MFS4_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42708618UL)) -#define bFM4_MFS4_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270861CUL)) -#define bFM4_MFS4_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42708620UL)) -#define bFM4_MFS4_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42708624UL)) - -/* MFS LIN channel 4 registers */ -#define bFM4_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM4_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM4_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM4_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM4_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM4_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM4_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM4_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM4_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM4_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM4_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM4_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM4_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM4_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM4_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM4_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM4_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM4_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM4_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM4_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM4_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM4_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM4_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM4_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM4_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM4_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM4_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM4_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM4_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM4_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM4_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* MFS I2C channel 4 registers */ -#define bFM4_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM4_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM4_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM4_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM4_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM4_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM4_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM4_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM4_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM4_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM4_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM4_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM4_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM4_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM4_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM4_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM4_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM4_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM4_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM4_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM4_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM4_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM4_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM4_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM4_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM4_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM4_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM4_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM4_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM4_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM4_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM4_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM4_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM4_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM4_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM4_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM4_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM4_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM4_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM4_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM4_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM4_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM4_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM4_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM4_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM4_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM4_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM4_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM4_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM4_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM4_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM4_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM4_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM4_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM4_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM4_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM4_MFS4_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM4_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM4_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM4_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM4_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM4_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM4_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM4_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM4_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* MFS UART channel 5 registers */ -#define bFM4_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM4_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM4_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM4_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM4_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM4_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM4_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM4_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM4_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM4_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM4_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM4_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM4_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM4_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM4_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM4_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM4_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM4_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM4_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM4_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM4_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM4_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM4_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM4_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM4_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM4_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM4_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM4_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM4_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM4_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM4_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM4_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM4_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM4_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* MFS CSIO channel 5 registers */ -#define bFM4_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM4_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM4_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM4_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM4_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM4_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM4_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM4_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM4_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM4_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM4_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM4_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM4_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM4_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM4_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM4_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM4_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM4_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM4_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM4_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM4_MFS5_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270A098UL)) -#define bFM4_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM4_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM4_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM4_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM4_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM4_MFS5_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM4_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM4_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270A380UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270A384UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270A388UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270A38CUL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270A390UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270A394UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270A398UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270A39CUL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270A3A0UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270A3A4UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270A3A8UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270A3ACUL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270A3B0UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270A3B4UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270A3B8UL)) -#define bFM4_MFS5_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270A3BCUL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270A400UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270A404UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270A408UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270A40CUL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270A410UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270A414UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270A418UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270A41CUL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270A420UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270A424UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270A428UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270A42CUL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270A430UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270A434UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270A438UL)) -#define bFM4_MFS5_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270A43CUL)) -#define bFM4_MFS5_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270A480UL)) -#define bFM4_MFS5_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270A484UL)) -#define bFM4_MFS5_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270A488UL)) -#define bFM4_MFS5_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270A48CUL)) -#define bFM4_MFS5_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270A490UL)) -#define bFM4_MFS5_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270A498UL)) -#define bFM4_MFS5_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270A49CUL)) -#define bFM4_MFS5_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270A4A0UL)) -#define bFM4_MFS5_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270A4ACUL)) -#define bFM4_MFS5_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270A4B0UL)) -#define bFM4_MFS5_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270A4B4UL)) -#define bFM4_MFS5_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270A500UL)) -#define bFM4_MFS5_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270A504UL)) -#define bFM4_MFS5_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270A508UL)) -#define bFM4_MFS5_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270A50CUL)) -#define bFM4_MFS5_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270A510UL)) -#define bFM4_MFS5_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270A514UL)) -#define bFM4_MFS5_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270A518UL)) -#define bFM4_MFS5_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270A51CUL)) -#define bFM4_MFS5_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270A520UL)) -#define bFM4_MFS5_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270A524UL)) -#define bFM4_MFS5_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270A528UL)) -#define bFM4_MFS5_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270A52CUL)) -#define bFM4_MFS5_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270A530UL)) -#define bFM4_MFS5_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270A534UL)) -#define bFM4_MFS5_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270A538UL)) -#define bFM4_MFS5_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270A53CUL)) -#define bFM4_MFS5_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270A580UL)) -#define bFM4_MFS5_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270A584UL)) -#define bFM4_MFS5_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270A588UL)) -#define bFM4_MFS5_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270A58CUL)) -#define bFM4_MFS5_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270A590UL)) -#define bFM4_MFS5_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270A594UL)) -#define bFM4_MFS5_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270A598UL)) -#define bFM4_MFS5_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270A59CUL)) -#define bFM4_MFS5_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270A5A0UL)) -#define bFM4_MFS5_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270A5A4UL)) -#define bFM4_MFS5_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270A5A8UL)) -#define bFM4_MFS5_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270A5ACUL)) -#define bFM4_MFS5_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270A5B0UL)) -#define bFM4_MFS5_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270A5B4UL)) -#define bFM4_MFS5_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270A5B8UL)) -#define bFM4_MFS5_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270A5BCUL)) -#define bFM4_MFS5_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270A600UL)) -#define bFM4_MFS5_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270A604UL)) -#define bFM4_MFS5_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270A614UL)) -#define bFM4_MFS5_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270A618UL)) -#define bFM4_MFS5_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270A61CUL)) -#define bFM4_MFS5_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270A620UL)) -#define bFM4_MFS5_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270A624UL)) - -/* MFS LIN channel 5 registers */ -#define bFM4_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM4_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM4_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM4_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM4_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM4_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM4_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM4_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM4_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM4_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM4_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM4_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM4_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM4_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM4_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM4_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM4_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM4_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM4_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM4_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM4_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM4_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM4_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM4_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM4_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM4_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM4_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM4_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM4_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM4_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM4_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* MFS I2C channel 5 registers */ -#define bFM4_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM4_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM4_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM4_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM4_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM4_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM4_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM4_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM4_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM4_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM4_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM4_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM4_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM4_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM4_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM4_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM4_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM4_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM4_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM4_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM4_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM4_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM4_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM4_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM4_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM4_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM4_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM4_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM4_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM4_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM4_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM4_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM4_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM4_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM4_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM4_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM4_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM4_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM4_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM4_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM4_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM4_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM4_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM4_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM4_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM4_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM4_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM4_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM4_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM4_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM4_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM4_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM4_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM4_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM4_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM4_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM4_MFS5_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM4_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM4_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM4_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM4_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM4_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM4_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM4_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM4_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* MFS UART channel 6 registers */ -#define bFM4_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM4_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM4_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM4_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM4_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM4_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM4_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM4_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM4_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM4_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM4_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM4_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM4_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM4_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM4_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM4_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM4_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM4_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM4_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM4_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM4_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM4_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM4_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM4_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM4_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM4_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM4_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM4_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM4_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM4_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM4_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM4_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM4_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM4_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* MFS CSIO channel 6 registers */ -#define bFM4_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM4_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM4_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM4_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM4_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM4_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM4_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM4_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM4_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM4_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM4_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM4_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM4_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM4_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM4_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM4_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM4_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM4_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM4_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM4_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM4_MFS6_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270C098UL)) -#define bFM4_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM4_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM4_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM4_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM4_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM4_MFS6_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM4_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM4_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270C380UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270C384UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270C388UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270C38CUL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270C390UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270C394UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270C398UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270C39CUL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270C3A0UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270C3A4UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270C3A8UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270C3ACUL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270C3B0UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270C3B4UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270C3B8UL)) -#define bFM4_MFS6_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270C3BCUL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270C400UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270C404UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270C408UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270C40CUL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270C410UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270C414UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270C418UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270C41CUL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270C420UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270C424UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270C428UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270C42CUL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270C430UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270C434UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270C438UL)) -#define bFM4_MFS6_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270C43CUL)) -#define bFM4_MFS6_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270C480UL)) -#define bFM4_MFS6_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270C484UL)) -#define bFM4_MFS6_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270C488UL)) -#define bFM4_MFS6_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270C48CUL)) -#define bFM4_MFS6_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270C490UL)) -#define bFM4_MFS6_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270C498UL)) -#define bFM4_MFS6_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270C49CUL)) -#define bFM4_MFS6_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270C4A0UL)) -#define bFM4_MFS6_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270C4ACUL)) -#define bFM4_MFS6_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270C4B0UL)) -#define bFM4_MFS6_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270C4B4UL)) -#define bFM4_MFS6_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270C500UL)) -#define bFM4_MFS6_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270C504UL)) -#define bFM4_MFS6_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270C508UL)) -#define bFM4_MFS6_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270C50CUL)) -#define bFM4_MFS6_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270C510UL)) -#define bFM4_MFS6_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270C514UL)) -#define bFM4_MFS6_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270C518UL)) -#define bFM4_MFS6_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270C51CUL)) -#define bFM4_MFS6_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270C520UL)) -#define bFM4_MFS6_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270C524UL)) -#define bFM4_MFS6_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270C528UL)) -#define bFM4_MFS6_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270C52CUL)) -#define bFM4_MFS6_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270C530UL)) -#define bFM4_MFS6_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270C534UL)) -#define bFM4_MFS6_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270C538UL)) -#define bFM4_MFS6_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270C53CUL)) -#define bFM4_MFS6_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270C580UL)) -#define bFM4_MFS6_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270C584UL)) -#define bFM4_MFS6_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270C588UL)) -#define bFM4_MFS6_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270C58CUL)) -#define bFM4_MFS6_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270C590UL)) -#define bFM4_MFS6_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270C594UL)) -#define bFM4_MFS6_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270C598UL)) -#define bFM4_MFS6_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270C59CUL)) -#define bFM4_MFS6_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270C5A0UL)) -#define bFM4_MFS6_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270C5A4UL)) -#define bFM4_MFS6_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270C5A8UL)) -#define bFM4_MFS6_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270C5ACUL)) -#define bFM4_MFS6_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270C5B0UL)) -#define bFM4_MFS6_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270C5B4UL)) -#define bFM4_MFS6_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270C5B8UL)) -#define bFM4_MFS6_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270C5BCUL)) -#define bFM4_MFS6_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270C600UL)) -#define bFM4_MFS6_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270C604UL)) -#define bFM4_MFS6_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270C614UL)) -#define bFM4_MFS6_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270C618UL)) -#define bFM4_MFS6_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270C61CUL)) -#define bFM4_MFS6_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270C620UL)) -#define bFM4_MFS6_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270C624UL)) - -/* MFS LIN channel 6 registers */ -#define bFM4_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM4_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM4_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM4_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM4_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM4_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM4_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM4_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM4_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM4_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM4_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM4_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM4_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM4_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM4_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM4_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM4_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM4_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM4_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM4_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM4_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM4_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM4_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM4_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM4_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM4_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM4_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM4_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM4_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM4_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM4_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* MFS I2C channel 6 registers */ -#define bFM4_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM4_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM4_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM4_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM4_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM4_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM4_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM4_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM4_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM4_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM4_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM4_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM4_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM4_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM4_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM4_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM4_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM4_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM4_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM4_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM4_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM4_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM4_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM4_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM4_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM4_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM4_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM4_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM4_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM4_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM4_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM4_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM4_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM4_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM4_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM4_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM4_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM4_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM4_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM4_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM4_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM4_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM4_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM4_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM4_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM4_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM4_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM4_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM4_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM4_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM4_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM4_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM4_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM4_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM4_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM4_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM4_MFS6_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM4_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM4_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM4_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM4_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM4_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM4_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM4_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM4_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* MFS UART channel 7 registers */ -#define bFM4_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM4_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM4_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM4_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM4_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM4_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM4_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM4_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM4_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM4_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM4_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM4_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM4_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM4_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM4_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM4_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM4_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM4_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM4_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM4_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM4_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM4_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM4_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM4_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM4_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM4_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM4_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM4_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM4_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM4_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM4_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM4_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM4_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_UART_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM4_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* MFS CSIO channel 7 registers */ -#define bFM4_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM4_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM4_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM4_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM4_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM4_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM4_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM4_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM4_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM4_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM4_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM4_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM4_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM4_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM4_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM4_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM4_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM4_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM4_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM4_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM4_MFS7_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4270E098UL)) -#define bFM4_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM4_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM4_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM4_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM4_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM4_MFS7_CSIO_SSR_AWC *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM4_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM4_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4270E380UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4270E384UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4270E388UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4270E38CUL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4270E390UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4270E394UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4270E398UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4270E39CUL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4270E3A0UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4270E3A4UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4270E3A8UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4270E3ACUL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4270E3B0UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4270E3B4UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4270E3B8UL)) -#define bFM4_MFS7_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4270E3BCUL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4270E400UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4270E404UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4270E408UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4270E40CUL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4270E410UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4270E414UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4270E418UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4270E41CUL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4270E420UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4270E424UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4270E428UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4270E42CUL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4270E430UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4270E434UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4270E438UL)) -#define bFM4_MFS7_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4270E43CUL)) -#define bFM4_MFS7_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4270E480UL)) -#define bFM4_MFS7_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4270E484UL)) -#define bFM4_MFS7_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4270E488UL)) -#define bFM4_MFS7_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4270E48CUL)) -#define bFM4_MFS7_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4270E490UL)) -#define bFM4_MFS7_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4270E498UL)) -#define bFM4_MFS7_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4270E49CUL)) -#define bFM4_MFS7_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4270E4A0UL)) -#define bFM4_MFS7_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4270E4ACUL)) -#define bFM4_MFS7_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4270E4B0UL)) -#define bFM4_MFS7_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4270E4B4UL)) -#define bFM4_MFS7_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4270E500UL)) -#define bFM4_MFS7_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4270E504UL)) -#define bFM4_MFS7_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4270E508UL)) -#define bFM4_MFS7_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4270E50CUL)) -#define bFM4_MFS7_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4270E510UL)) -#define bFM4_MFS7_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4270E514UL)) -#define bFM4_MFS7_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4270E518UL)) -#define bFM4_MFS7_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4270E51CUL)) -#define bFM4_MFS7_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4270E520UL)) -#define bFM4_MFS7_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4270E524UL)) -#define bFM4_MFS7_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4270E528UL)) -#define bFM4_MFS7_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4270E52CUL)) -#define bFM4_MFS7_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4270E530UL)) -#define bFM4_MFS7_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4270E534UL)) -#define bFM4_MFS7_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4270E538UL)) -#define bFM4_MFS7_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4270E53CUL)) -#define bFM4_MFS7_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4270E580UL)) -#define bFM4_MFS7_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4270E584UL)) -#define bFM4_MFS7_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4270E588UL)) -#define bFM4_MFS7_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4270E58CUL)) -#define bFM4_MFS7_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4270E590UL)) -#define bFM4_MFS7_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4270E594UL)) -#define bFM4_MFS7_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4270E598UL)) -#define bFM4_MFS7_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4270E59CUL)) -#define bFM4_MFS7_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4270E5A0UL)) -#define bFM4_MFS7_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4270E5A4UL)) -#define bFM4_MFS7_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4270E5A8UL)) -#define bFM4_MFS7_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4270E5ACUL)) -#define bFM4_MFS7_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4270E5B0UL)) -#define bFM4_MFS7_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4270E5B4UL)) -#define bFM4_MFS7_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4270E5B8UL)) -#define bFM4_MFS7_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4270E5BCUL)) -#define bFM4_MFS7_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4270E600UL)) -#define bFM4_MFS7_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4270E604UL)) -#define bFM4_MFS7_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4270E614UL)) -#define bFM4_MFS7_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4270E618UL)) -#define bFM4_MFS7_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4270E61CUL)) -#define bFM4_MFS7_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4270E620UL)) -#define bFM4_MFS7_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4270E624UL)) - -/* MFS LIN channel 7 registers */ -#define bFM4_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM4_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM4_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM4_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM4_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM4_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM4_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM4_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM4_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM4_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM4_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM4_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM4_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM4_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM4_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM4_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM4_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM4_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM4_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM4_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM4_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM4_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM4_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM4_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM4_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM4_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM4_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM4_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM4_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM4_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM4_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* MFS I2C channel 7 registers */ -#define bFM4_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM4_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM4_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM4_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM4_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM4_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM4_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM4_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM4_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM4_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM4_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM4_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM4_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM4_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM4_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM4_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM4_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM4_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM4_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM4_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM4_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM4_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM4_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM4_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM4_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM4_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM4_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM4_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM4_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM4_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM4_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM4_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM4_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM4_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM4_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM4_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM4_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM4_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM4_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM4_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM4_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM4_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM4_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM4_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM4_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM4_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM4_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM4_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM4_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM4_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM4_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM4_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM4_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM4_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM4_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM4_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM4_MFS7_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM4_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM4_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM4_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM4_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM4_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM4_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM4_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM4_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* MFS UART channel 8 registers */ -#define bFM4_MFS8_UART_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) -#define bFM4_MFS8_UART_SMR_BDS *((volatile unsigned int*)(0x42710008UL)) -#define bFM4_MFS8_UART_SMR_SBL *((volatile unsigned int*)(0x4271000CUL)) -#define bFM4_MFS8_UART_SMR_WUCR *((volatile unsigned int*)(0x42710010UL)) -#define bFM4_MFS8_UART_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) -#define bFM4_MFS8_UART_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) -#define bFM4_MFS8_UART_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM4_MFS8_UART_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) -#define bFM4_MFS8_UART_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) -#define bFM4_MFS8_UART_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) -#define bFM4_MFS8_UART_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) -#define bFM4_MFS8_UART_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) -#define bFM4_MFS8_UART_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) -#define bFM4_MFS8_UART_ESCR_L0 *((volatile unsigned int*)(0x42710080UL)) -#define bFM4_MFS8_UART_ESCR_L1 *((volatile unsigned int*)(0x42710084UL)) -#define bFM4_MFS8_UART_ESCR_L2 *((volatile unsigned int*)(0x42710088UL)) -#define bFM4_MFS8_UART_ESCR_P *((volatile unsigned int*)(0x4271008CUL)) -#define bFM4_MFS8_UART_ESCR_PEN *((volatile unsigned int*)(0x42710090UL)) -#define bFM4_MFS8_UART_ESCR_INV *((volatile unsigned int*)(0x42710094UL)) -#define bFM4_MFS8_UART_ESCR_ESBL *((volatile unsigned int*)(0x42710098UL)) -#define bFM4_MFS8_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271009CUL)) -#define bFM4_MFS8_UART_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) -#define bFM4_MFS8_UART_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) -#define bFM4_MFS8_UART_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) -#define bFM4_MFS8_UART_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) -#define bFM4_MFS8_UART_SSR_FRE *((volatile unsigned int*)(0x427100B0UL)) -#define bFM4_MFS8_UART_SSR_PE *((volatile unsigned int*)(0x427100B4UL)) -#define bFM4_MFS8_UART_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) -#define bFM4_MFS8_UART_RDR_AD *((volatile unsigned int*)(0x42710120UL)) -#define bFM4_MFS8_UART_TDR_AD *((volatile unsigned int*)(0x42710120UL)) -#define bFM4_MFS8_UART_BGR_EXT *((volatile unsigned int*)(0x427101BCUL)) -#define bFM4_MFS8_UART_BGR1_EXT *((volatile unsigned int*)(0x427101BCUL)) -#define bFM4_MFS8_UART_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_UART_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_UART_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_UART_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_UART_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_UART_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_UART_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_UART_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_UART_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_UART_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_UART_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_UART_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_UART_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_UART_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_UART_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_UART_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_UART_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_UART_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) -#define bFM4_MFS8_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) - -/* MFS CSIO channel 8 registers */ -#define bFM4_MFS8_CSIO_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) -#define bFM4_MFS8_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42710004UL)) -#define bFM4_MFS8_CSIO_SMR_BDS *((volatile unsigned int*)(0x42710008UL)) -#define bFM4_MFS8_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271000CUL)) -#define bFM4_MFS8_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) -#define bFM4_MFS8_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) -#define bFM4_MFS8_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM4_MFS8_CSIO_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) -#define bFM4_MFS8_CSIO_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) -#define bFM4_MFS8_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) -#define bFM4_MFS8_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) -#define bFM4_MFS8_CSIO_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) -#define bFM4_MFS8_CSIO_SCR_SPI *((volatile unsigned int*)(0x42710034UL)) -#define bFM4_MFS8_CSIO_SCR_MS *((volatile unsigned int*)(0x42710038UL)) -#define bFM4_MFS8_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) -#define bFM4_MFS8_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42710080UL)) -#define bFM4_MFS8_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42710084UL)) -#define bFM4_MFS8_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42710088UL)) -#define bFM4_MFS8_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271008CUL)) -#define bFM4_MFS8_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42710090UL)) -#define bFM4_MFS8_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42710098UL)) -#define bFM4_MFS8_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271009CUL)) -#define bFM4_MFS8_CSIO_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) -#define bFM4_MFS8_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) -#define bFM4_MFS8_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) -#define bFM4_MFS8_CSIO_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) -#define bFM4_MFS8_CSIO_SSR_AWC *((volatile unsigned int*)(0x427100B0UL)) -#define bFM4_MFS8_CSIO_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) -#define bFM4_MFS8_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_CSIO_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_CSIO_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_CSIO_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42710380UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42710384UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42710388UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271038CUL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42710390UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42710394UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42710398UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271039CUL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427103A0UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427103A4UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427103A8UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427103ACUL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427103B0UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427103B4UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427103B8UL)) -#define bFM4_MFS8_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427103BCUL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42710400UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42710404UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42710408UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271040CUL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42710410UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42710414UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42710418UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271041CUL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42710420UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42710424UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42710428UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271042CUL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42710430UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42710434UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42710438UL)) -#define bFM4_MFS8_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271043CUL)) -#define bFM4_MFS8_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42710480UL)) -#define bFM4_MFS8_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42710484UL)) -#define bFM4_MFS8_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42710488UL)) -#define bFM4_MFS8_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271048CUL)) -#define bFM4_MFS8_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42710490UL)) -#define bFM4_MFS8_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42710498UL)) -#define bFM4_MFS8_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271049CUL)) -#define bFM4_MFS8_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427104A0UL)) -#define bFM4_MFS8_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427104ACUL)) -#define bFM4_MFS8_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427104B0UL)) -#define bFM4_MFS8_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427104B4UL)) -#define bFM4_MFS8_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42710500UL)) -#define bFM4_MFS8_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42710504UL)) -#define bFM4_MFS8_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42710508UL)) -#define bFM4_MFS8_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271050CUL)) -#define bFM4_MFS8_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42710510UL)) -#define bFM4_MFS8_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42710514UL)) -#define bFM4_MFS8_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42710518UL)) -#define bFM4_MFS8_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271051CUL)) -#define bFM4_MFS8_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42710520UL)) -#define bFM4_MFS8_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42710524UL)) -#define bFM4_MFS8_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42710528UL)) -#define bFM4_MFS8_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271052CUL)) -#define bFM4_MFS8_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42710530UL)) -#define bFM4_MFS8_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42710534UL)) -#define bFM4_MFS8_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42710538UL)) -#define bFM4_MFS8_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271053CUL)) -#define bFM4_MFS8_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42710580UL)) -#define bFM4_MFS8_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42710584UL)) -#define bFM4_MFS8_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42710588UL)) -#define bFM4_MFS8_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271058CUL)) -#define bFM4_MFS8_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42710590UL)) -#define bFM4_MFS8_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42710594UL)) -#define bFM4_MFS8_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42710598UL)) -#define bFM4_MFS8_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271059CUL)) -#define bFM4_MFS8_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427105A0UL)) -#define bFM4_MFS8_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427105A4UL)) -#define bFM4_MFS8_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427105A8UL)) -#define bFM4_MFS8_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427105ACUL)) -#define bFM4_MFS8_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427105B0UL)) -#define bFM4_MFS8_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427105B4UL)) -#define bFM4_MFS8_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427105B8UL)) -#define bFM4_MFS8_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427105BCUL)) -#define bFM4_MFS8_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42710600UL)) -#define bFM4_MFS8_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42710604UL)) -#define bFM4_MFS8_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42710614UL)) -#define bFM4_MFS8_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42710618UL)) -#define bFM4_MFS8_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271061CUL)) -#define bFM4_MFS8_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42710620UL)) -#define bFM4_MFS8_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42710624UL)) - -/* MFS LIN channel 8 registers */ -#define bFM4_MFS8_LIN_SMR_SOE *((volatile unsigned int*)(0x42710000UL)) -#define bFM4_MFS8_LIN_SMR_SBL *((volatile unsigned int*)(0x4271000CUL)) -#define bFM4_MFS8_LIN_SMR_WUCR *((volatile unsigned int*)(0x42710010UL)) -#define bFM4_MFS8_LIN_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) -#define bFM4_MFS8_LIN_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) -#define bFM4_MFS8_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM4_MFS8_LIN_SCR_TXE *((volatile unsigned int*)(0x42710020UL)) -#define bFM4_MFS8_LIN_SCR_RXE *((volatile unsigned int*)(0x42710024UL)) -#define bFM4_MFS8_LIN_SCR_TBIE *((volatile unsigned int*)(0x42710028UL)) -#define bFM4_MFS8_LIN_SCR_TIE *((volatile unsigned int*)(0x4271002CUL)) -#define bFM4_MFS8_LIN_SCR_RIE *((volatile unsigned int*)(0x42710030UL)) -#define bFM4_MFS8_LIN_SCR_LBR *((volatile unsigned int*)(0x42710034UL)) -#define bFM4_MFS8_LIN_SCR_MS *((volatile unsigned int*)(0x42710038UL)) -#define bFM4_MFS8_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271003CUL)) -#define bFM4_MFS8_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42710080UL)) -#define bFM4_MFS8_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42710084UL)) -#define bFM4_MFS8_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42710088UL)) -#define bFM4_MFS8_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271008CUL)) -#define bFM4_MFS8_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42710090UL)) -#define bFM4_MFS8_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42710098UL)) -#define bFM4_MFS8_LIN_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) -#define bFM4_MFS8_LIN_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) -#define bFM4_MFS8_LIN_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) -#define bFM4_MFS8_LIN_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) -#define bFM4_MFS8_LIN_SSR_FRE *((volatile unsigned int*)(0x427100B0UL)) -#define bFM4_MFS8_LIN_SSR_LBD *((volatile unsigned int*)(0x427100B4UL)) -#define bFM4_MFS8_LIN_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) -#define bFM4_MFS8_LIN_BGR_EXT *((volatile unsigned int*)(0x427101BCUL)) -#define bFM4_MFS8_LIN_BGR1_EXT *((volatile unsigned int*)(0x427101BCUL)) -#define bFM4_MFS8_LIN_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_LIN_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_LIN_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_LIN_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_LIN_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_LIN_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_LIN_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_LIN_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_LIN_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_LIN_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) -#define bFM4_MFS8_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) - -/* MFS I2C channel 8 registers */ -#define bFM4_MFS8_I2C_SMR_TIE *((volatile unsigned int*)(0x42710008UL)) -#define bFM4_MFS8_I2C_SMR_RIE *((volatile unsigned int*)(0x4271000CUL)) -#define bFM4_MFS8_I2C_SMR_MD0 *((volatile unsigned int*)(0x42710014UL)) -#define bFM4_MFS8_I2C_SMR_MD1 *((volatile unsigned int*)(0x42710018UL)) -#define bFM4_MFS8_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM4_MFS8_I2C_IBCR_INT *((volatile unsigned int*)(0x42710020UL)) -#define bFM4_MFS8_I2C_IBCR_BER *((volatile unsigned int*)(0x42710024UL)) -#define bFM4_MFS8_I2C_IBCR_INTE *((volatile unsigned int*)(0x42710028UL)) -#define bFM4_MFS8_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271002CUL)) -#define bFM4_MFS8_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42710030UL)) -#define bFM4_MFS8_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42710034UL)) -#define bFM4_MFS8_I2C_IBCR_ACT *((volatile unsigned int*)(0x42710038UL)) -#define bFM4_MFS8_I2C_IBCR_SCC *((volatile unsigned int*)(0x42710038UL)) -#define bFM4_MFS8_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271003CUL)) -#define bFM4_MFS8_I2C_IBSR_BB *((volatile unsigned int*)(0x42710080UL)) -#define bFM4_MFS8_I2C_IBSR_SPC *((volatile unsigned int*)(0x42710084UL)) -#define bFM4_MFS8_I2C_IBSR_RSC *((volatile unsigned int*)(0x42710088UL)) -#define bFM4_MFS8_I2C_IBSR_AL *((volatile unsigned int*)(0x4271008CUL)) -#define bFM4_MFS8_I2C_IBSR_TRX *((volatile unsigned int*)(0x42710090UL)) -#define bFM4_MFS8_I2C_IBSR_RSA *((volatile unsigned int*)(0x42710094UL)) -#define bFM4_MFS8_I2C_IBSR_RACK *((volatile unsigned int*)(0x42710098UL)) -#define bFM4_MFS8_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271009CUL)) -#define bFM4_MFS8_I2C_SSR_TBI *((volatile unsigned int*)(0x427100A0UL)) -#define bFM4_MFS8_I2C_SSR_TDRE *((volatile unsigned int*)(0x427100A4UL)) -#define bFM4_MFS8_I2C_SSR_RDRF *((volatile unsigned int*)(0x427100A8UL)) -#define bFM4_MFS8_I2C_SSR_ORE *((volatile unsigned int*)(0x427100ACUL)) -#define bFM4_MFS8_I2C_SSR_TBIE *((volatile unsigned int*)(0x427100B0UL)) -#define bFM4_MFS8_I2C_SSR_DMA *((volatile unsigned int*)(0x427100B4UL)) -#define bFM4_MFS8_I2C_SSR_TSET *((volatile unsigned int*)(0x427100B8UL)) -#define bFM4_MFS8_I2C_SSR_REC *((volatile unsigned int*)(0x427100BCUL)) -#define bFM4_MFS8_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42710200UL)) -#define bFM4_MFS8_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42710204UL)) -#define bFM4_MFS8_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42710208UL)) -#define bFM4_MFS8_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271020CUL)) -#define bFM4_MFS8_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42710210UL)) -#define bFM4_MFS8_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42710214UL)) -#define bFM4_MFS8_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42710218UL)) -#define bFM4_MFS8_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271021CUL)) -#define bFM4_MFS8_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42710220UL)) -#define bFM4_MFS8_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42710224UL)) -#define bFM4_MFS8_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42710228UL)) -#define bFM4_MFS8_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271022CUL)) -#define bFM4_MFS8_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42710230UL)) -#define bFM4_MFS8_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42710234UL)) -#define bFM4_MFS8_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42710238UL)) -#define bFM4_MFS8_I2C_ISMK_EN *((volatile unsigned int*)(0x4271023CUL)) -#define bFM4_MFS8_I2C_FCR_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_I2C_FCR_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_I2C_FCR_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_I2C_FCR_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_I2C_FCR_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_I2C_FCR_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_I2C_FCR_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42710280UL)) -#define bFM4_MFS8_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42710284UL)) -#define bFM4_MFS8_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42710288UL)) -#define bFM4_MFS8_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271028CUL)) -#define bFM4_MFS8_I2C_FCR0_FSET *((volatile unsigned int*)(0x42710290UL)) -#define bFM4_MFS8_I2C_FCR0_FLD *((volatile unsigned int*)(0x42710294UL)) -#define bFM4_MFS8_I2C_FCR0_FLST *((volatile unsigned int*)(0x42710298UL)) -#define bFM4_MFS8_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427102A0UL)) -#define bFM4_MFS8_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427102A4UL)) -#define bFM4_MFS8_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427102A8UL)) -#define bFM4_MFS8_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427102ACUL)) -#define bFM4_MFS8_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427102B0UL)) -#define bFM4_MFS8_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271033CUL)) -#define bFM4_MFS8_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42710300UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42710304UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42710308UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271030CUL)) -#define bFM4_MFS8_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42710310UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42710314UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42710318UL)) -#define bFM4_MFS8_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271031CUL)) -#define bFM4_MFS8_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42710320UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42710324UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42710328UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271032CUL)) -#define bFM4_MFS8_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42710330UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42710334UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42710338UL)) -#define bFM4_MFS8_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271033CUL)) - -/* MFS UART channel 9 registers */ -#define bFM4_MFS9_UART_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) -#define bFM4_MFS9_UART_SMR_BDS *((volatile unsigned int*)(0x42712008UL)) -#define bFM4_MFS9_UART_SMR_SBL *((volatile unsigned int*)(0x4271200CUL)) -#define bFM4_MFS9_UART_SMR_WUCR *((volatile unsigned int*)(0x42712010UL)) -#define bFM4_MFS9_UART_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) -#define bFM4_MFS9_UART_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) -#define bFM4_MFS9_UART_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) -#define bFM4_MFS9_UART_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) -#define bFM4_MFS9_UART_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) -#define bFM4_MFS9_UART_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) -#define bFM4_MFS9_UART_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) -#define bFM4_MFS9_UART_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) -#define bFM4_MFS9_UART_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) -#define bFM4_MFS9_UART_ESCR_L0 *((volatile unsigned int*)(0x42712080UL)) -#define bFM4_MFS9_UART_ESCR_L1 *((volatile unsigned int*)(0x42712084UL)) -#define bFM4_MFS9_UART_ESCR_L2 *((volatile unsigned int*)(0x42712088UL)) -#define bFM4_MFS9_UART_ESCR_P *((volatile unsigned int*)(0x4271208CUL)) -#define bFM4_MFS9_UART_ESCR_PEN *((volatile unsigned int*)(0x42712090UL)) -#define bFM4_MFS9_UART_ESCR_INV *((volatile unsigned int*)(0x42712094UL)) -#define bFM4_MFS9_UART_ESCR_ESBL *((volatile unsigned int*)(0x42712098UL)) -#define bFM4_MFS9_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271209CUL)) -#define bFM4_MFS9_UART_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) -#define bFM4_MFS9_UART_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) -#define bFM4_MFS9_UART_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) -#define bFM4_MFS9_UART_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) -#define bFM4_MFS9_UART_SSR_FRE *((volatile unsigned int*)(0x427120B0UL)) -#define bFM4_MFS9_UART_SSR_PE *((volatile unsigned int*)(0x427120B4UL)) -#define bFM4_MFS9_UART_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) -#define bFM4_MFS9_UART_RDR_AD *((volatile unsigned int*)(0x42712120UL)) -#define bFM4_MFS9_UART_TDR_AD *((volatile unsigned int*)(0x42712120UL)) -#define bFM4_MFS9_UART_BGR_EXT *((volatile unsigned int*)(0x427121BCUL)) -#define bFM4_MFS9_UART_BGR1_EXT *((volatile unsigned int*)(0x427121BCUL)) -#define bFM4_MFS9_UART_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_UART_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_UART_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_UART_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_UART_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_UART_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_UART_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_UART_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_UART_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_UART_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_UART_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_UART_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_UART_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_UART_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_UART_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_UART_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_UART_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_UART_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) -#define bFM4_MFS9_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) - -/* MFS CSIO channel 9 registers */ -#define bFM4_MFS9_CSIO_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) -#define bFM4_MFS9_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42712004UL)) -#define bFM4_MFS9_CSIO_SMR_BDS *((volatile unsigned int*)(0x42712008UL)) -#define bFM4_MFS9_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271200CUL)) -#define bFM4_MFS9_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) -#define bFM4_MFS9_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) -#define bFM4_MFS9_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) -#define bFM4_MFS9_CSIO_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) -#define bFM4_MFS9_CSIO_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) -#define bFM4_MFS9_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) -#define bFM4_MFS9_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) -#define bFM4_MFS9_CSIO_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) -#define bFM4_MFS9_CSIO_SCR_SPI *((volatile unsigned int*)(0x42712034UL)) -#define bFM4_MFS9_CSIO_SCR_MS *((volatile unsigned int*)(0x42712038UL)) -#define bFM4_MFS9_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) -#define bFM4_MFS9_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42712080UL)) -#define bFM4_MFS9_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42712084UL)) -#define bFM4_MFS9_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42712088UL)) -#define bFM4_MFS9_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271208CUL)) -#define bFM4_MFS9_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42712090UL)) -#define bFM4_MFS9_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42712098UL)) -#define bFM4_MFS9_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271209CUL)) -#define bFM4_MFS9_CSIO_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) -#define bFM4_MFS9_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) -#define bFM4_MFS9_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) -#define bFM4_MFS9_CSIO_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) -#define bFM4_MFS9_CSIO_SSR_AWC *((volatile unsigned int*)(0x427120B0UL)) -#define bFM4_MFS9_CSIO_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) -#define bFM4_MFS9_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_CSIO_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_CSIO_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_CSIO_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42712380UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42712384UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42712388UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271238CUL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42712390UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42712394UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42712398UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271239CUL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427123A0UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427123A4UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427123A8UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427123ACUL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427123B0UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427123B4UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427123B8UL)) -#define bFM4_MFS9_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427123BCUL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42712400UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42712404UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42712408UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271240CUL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42712410UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42712414UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42712418UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271241CUL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42712420UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42712424UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42712428UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271242CUL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42712430UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42712434UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42712438UL)) -#define bFM4_MFS9_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271243CUL)) -#define bFM4_MFS9_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42712480UL)) -#define bFM4_MFS9_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42712484UL)) -#define bFM4_MFS9_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42712488UL)) -#define bFM4_MFS9_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271248CUL)) -#define bFM4_MFS9_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42712490UL)) -#define bFM4_MFS9_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42712498UL)) -#define bFM4_MFS9_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271249CUL)) -#define bFM4_MFS9_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427124A0UL)) -#define bFM4_MFS9_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427124ACUL)) -#define bFM4_MFS9_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427124B0UL)) -#define bFM4_MFS9_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427124B4UL)) -#define bFM4_MFS9_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42712500UL)) -#define bFM4_MFS9_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42712504UL)) -#define bFM4_MFS9_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42712508UL)) -#define bFM4_MFS9_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271250CUL)) -#define bFM4_MFS9_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42712510UL)) -#define bFM4_MFS9_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42712514UL)) -#define bFM4_MFS9_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42712518UL)) -#define bFM4_MFS9_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271251CUL)) -#define bFM4_MFS9_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42712520UL)) -#define bFM4_MFS9_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42712524UL)) -#define bFM4_MFS9_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42712528UL)) -#define bFM4_MFS9_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271252CUL)) -#define bFM4_MFS9_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42712530UL)) -#define bFM4_MFS9_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42712534UL)) -#define bFM4_MFS9_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42712538UL)) -#define bFM4_MFS9_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271253CUL)) -#define bFM4_MFS9_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42712580UL)) -#define bFM4_MFS9_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42712584UL)) -#define bFM4_MFS9_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42712588UL)) -#define bFM4_MFS9_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271258CUL)) -#define bFM4_MFS9_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42712590UL)) -#define bFM4_MFS9_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42712594UL)) -#define bFM4_MFS9_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42712598UL)) -#define bFM4_MFS9_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271259CUL)) -#define bFM4_MFS9_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427125A0UL)) -#define bFM4_MFS9_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427125A4UL)) -#define bFM4_MFS9_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427125A8UL)) -#define bFM4_MFS9_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427125ACUL)) -#define bFM4_MFS9_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427125B0UL)) -#define bFM4_MFS9_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427125B4UL)) -#define bFM4_MFS9_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427125B8UL)) -#define bFM4_MFS9_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427125BCUL)) -#define bFM4_MFS9_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42712600UL)) -#define bFM4_MFS9_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42712604UL)) -#define bFM4_MFS9_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42712614UL)) -#define bFM4_MFS9_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42712618UL)) -#define bFM4_MFS9_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271261CUL)) -#define bFM4_MFS9_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42712620UL)) -#define bFM4_MFS9_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42712624UL)) - -/* MFS LIN channel 9 registers */ -#define bFM4_MFS9_LIN_SMR_SOE *((volatile unsigned int*)(0x42712000UL)) -#define bFM4_MFS9_LIN_SMR_SBL *((volatile unsigned int*)(0x4271200CUL)) -#define bFM4_MFS9_LIN_SMR_WUCR *((volatile unsigned int*)(0x42712010UL)) -#define bFM4_MFS9_LIN_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) -#define bFM4_MFS9_LIN_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) -#define bFM4_MFS9_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) -#define bFM4_MFS9_LIN_SCR_TXE *((volatile unsigned int*)(0x42712020UL)) -#define bFM4_MFS9_LIN_SCR_RXE *((volatile unsigned int*)(0x42712024UL)) -#define bFM4_MFS9_LIN_SCR_TBIE *((volatile unsigned int*)(0x42712028UL)) -#define bFM4_MFS9_LIN_SCR_TIE *((volatile unsigned int*)(0x4271202CUL)) -#define bFM4_MFS9_LIN_SCR_RIE *((volatile unsigned int*)(0x42712030UL)) -#define bFM4_MFS9_LIN_SCR_LBR *((volatile unsigned int*)(0x42712034UL)) -#define bFM4_MFS9_LIN_SCR_MS *((volatile unsigned int*)(0x42712038UL)) -#define bFM4_MFS9_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271203CUL)) -#define bFM4_MFS9_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42712080UL)) -#define bFM4_MFS9_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42712084UL)) -#define bFM4_MFS9_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42712088UL)) -#define bFM4_MFS9_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271208CUL)) -#define bFM4_MFS9_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42712090UL)) -#define bFM4_MFS9_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42712098UL)) -#define bFM4_MFS9_LIN_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) -#define bFM4_MFS9_LIN_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) -#define bFM4_MFS9_LIN_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) -#define bFM4_MFS9_LIN_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) -#define bFM4_MFS9_LIN_SSR_FRE *((volatile unsigned int*)(0x427120B0UL)) -#define bFM4_MFS9_LIN_SSR_LBD *((volatile unsigned int*)(0x427120B4UL)) -#define bFM4_MFS9_LIN_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) -#define bFM4_MFS9_LIN_BGR_EXT *((volatile unsigned int*)(0x427121BCUL)) -#define bFM4_MFS9_LIN_BGR1_EXT *((volatile unsigned int*)(0x427121BCUL)) -#define bFM4_MFS9_LIN_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_LIN_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_LIN_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_LIN_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_LIN_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_LIN_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_LIN_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_LIN_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_LIN_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_LIN_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) -#define bFM4_MFS9_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) - -/* MFS I2C channel 9 registers */ -#define bFM4_MFS9_I2C_SMR_TIE *((volatile unsigned int*)(0x42712008UL)) -#define bFM4_MFS9_I2C_SMR_RIE *((volatile unsigned int*)(0x4271200CUL)) -#define bFM4_MFS9_I2C_SMR_MD0 *((volatile unsigned int*)(0x42712014UL)) -#define bFM4_MFS9_I2C_SMR_MD1 *((volatile unsigned int*)(0x42712018UL)) -#define bFM4_MFS9_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271201CUL)) -#define bFM4_MFS9_I2C_IBCR_INT *((volatile unsigned int*)(0x42712020UL)) -#define bFM4_MFS9_I2C_IBCR_BER *((volatile unsigned int*)(0x42712024UL)) -#define bFM4_MFS9_I2C_IBCR_INTE *((volatile unsigned int*)(0x42712028UL)) -#define bFM4_MFS9_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271202CUL)) -#define bFM4_MFS9_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42712030UL)) -#define bFM4_MFS9_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42712034UL)) -#define bFM4_MFS9_I2C_IBCR_ACT *((volatile unsigned int*)(0x42712038UL)) -#define bFM4_MFS9_I2C_IBCR_SCC *((volatile unsigned int*)(0x42712038UL)) -#define bFM4_MFS9_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271203CUL)) -#define bFM4_MFS9_I2C_IBSR_BB *((volatile unsigned int*)(0x42712080UL)) -#define bFM4_MFS9_I2C_IBSR_SPC *((volatile unsigned int*)(0x42712084UL)) -#define bFM4_MFS9_I2C_IBSR_RSC *((volatile unsigned int*)(0x42712088UL)) -#define bFM4_MFS9_I2C_IBSR_AL *((volatile unsigned int*)(0x4271208CUL)) -#define bFM4_MFS9_I2C_IBSR_TRX *((volatile unsigned int*)(0x42712090UL)) -#define bFM4_MFS9_I2C_IBSR_RSA *((volatile unsigned int*)(0x42712094UL)) -#define bFM4_MFS9_I2C_IBSR_RACK *((volatile unsigned int*)(0x42712098UL)) -#define bFM4_MFS9_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271209CUL)) -#define bFM4_MFS9_I2C_SSR_TBI *((volatile unsigned int*)(0x427120A0UL)) -#define bFM4_MFS9_I2C_SSR_TDRE *((volatile unsigned int*)(0x427120A4UL)) -#define bFM4_MFS9_I2C_SSR_RDRF *((volatile unsigned int*)(0x427120A8UL)) -#define bFM4_MFS9_I2C_SSR_ORE *((volatile unsigned int*)(0x427120ACUL)) -#define bFM4_MFS9_I2C_SSR_TBIE *((volatile unsigned int*)(0x427120B0UL)) -#define bFM4_MFS9_I2C_SSR_DMA *((volatile unsigned int*)(0x427120B4UL)) -#define bFM4_MFS9_I2C_SSR_TSET *((volatile unsigned int*)(0x427120B8UL)) -#define bFM4_MFS9_I2C_SSR_REC *((volatile unsigned int*)(0x427120BCUL)) -#define bFM4_MFS9_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42712200UL)) -#define bFM4_MFS9_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42712204UL)) -#define bFM4_MFS9_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42712208UL)) -#define bFM4_MFS9_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271220CUL)) -#define bFM4_MFS9_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42712210UL)) -#define bFM4_MFS9_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42712214UL)) -#define bFM4_MFS9_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42712218UL)) -#define bFM4_MFS9_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271221CUL)) -#define bFM4_MFS9_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42712220UL)) -#define bFM4_MFS9_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42712224UL)) -#define bFM4_MFS9_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42712228UL)) -#define bFM4_MFS9_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271222CUL)) -#define bFM4_MFS9_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42712230UL)) -#define bFM4_MFS9_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42712234UL)) -#define bFM4_MFS9_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42712238UL)) -#define bFM4_MFS9_I2C_ISMK_EN *((volatile unsigned int*)(0x4271223CUL)) -#define bFM4_MFS9_I2C_FCR_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_I2C_FCR_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_I2C_FCR_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_I2C_FCR_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_I2C_FCR_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_I2C_FCR_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_I2C_FCR_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42712280UL)) -#define bFM4_MFS9_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42712284UL)) -#define bFM4_MFS9_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42712288UL)) -#define bFM4_MFS9_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271228CUL)) -#define bFM4_MFS9_I2C_FCR0_FSET *((volatile unsigned int*)(0x42712290UL)) -#define bFM4_MFS9_I2C_FCR0_FLD *((volatile unsigned int*)(0x42712294UL)) -#define bFM4_MFS9_I2C_FCR0_FLST *((volatile unsigned int*)(0x42712298UL)) -#define bFM4_MFS9_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427122A0UL)) -#define bFM4_MFS9_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427122A4UL)) -#define bFM4_MFS9_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427122A8UL)) -#define bFM4_MFS9_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427122ACUL)) -#define bFM4_MFS9_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427122B0UL)) -#define bFM4_MFS9_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271233CUL)) -#define bFM4_MFS9_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42712300UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42712304UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42712308UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271230CUL)) -#define bFM4_MFS9_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42712310UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42712314UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42712318UL)) -#define bFM4_MFS9_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271231CUL)) -#define bFM4_MFS9_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42712320UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42712324UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42712328UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271232CUL)) -#define bFM4_MFS9_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42712330UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42712334UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42712338UL)) -#define bFM4_MFS9_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271233CUL)) - -/* MFS UART channel 10 registers */ -#define bFM4_MFS10_UART_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) -#define bFM4_MFS10_UART_SMR_BDS *((volatile unsigned int*)(0x42714008UL)) -#define bFM4_MFS10_UART_SMR_SBL *((volatile unsigned int*)(0x4271400CUL)) -#define bFM4_MFS10_UART_SMR_WUCR *((volatile unsigned int*)(0x42714010UL)) -#define bFM4_MFS10_UART_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) -#define bFM4_MFS10_UART_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) -#define bFM4_MFS10_UART_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) -#define bFM4_MFS10_UART_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) -#define bFM4_MFS10_UART_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) -#define bFM4_MFS10_UART_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) -#define bFM4_MFS10_UART_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) -#define bFM4_MFS10_UART_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) -#define bFM4_MFS10_UART_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) -#define bFM4_MFS10_UART_ESCR_L0 *((volatile unsigned int*)(0x42714080UL)) -#define bFM4_MFS10_UART_ESCR_L1 *((volatile unsigned int*)(0x42714084UL)) -#define bFM4_MFS10_UART_ESCR_L2 *((volatile unsigned int*)(0x42714088UL)) -#define bFM4_MFS10_UART_ESCR_P *((volatile unsigned int*)(0x4271408CUL)) -#define bFM4_MFS10_UART_ESCR_PEN *((volatile unsigned int*)(0x42714090UL)) -#define bFM4_MFS10_UART_ESCR_INV *((volatile unsigned int*)(0x42714094UL)) -#define bFM4_MFS10_UART_ESCR_ESBL *((volatile unsigned int*)(0x42714098UL)) -#define bFM4_MFS10_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271409CUL)) -#define bFM4_MFS10_UART_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) -#define bFM4_MFS10_UART_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) -#define bFM4_MFS10_UART_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) -#define bFM4_MFS10_UART_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) -#define bFM4_MFS10_UART_SSR_FRE *((volatile unsigned int*)(0x427140B0UL)) -#define bFM4_MFS10_UART_SSR_PE *((volatile unsigned int*)(0x427140B4UL)) -#define bFM4_MFS10_UART_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) -#define bFM4_MFS10_UART_RDR_AD *((volatile unsigned int*)(0x42714120UL)) -#define bFM4_MFS10_UART_TDR_AD *((volatile unsigned int*)(0x42714120UL)) -#define bFM4_MFS10_UART_BGR_EXT *((volatile unsigned int*)(0x427141BCUL)) -#define bFM4_MFS10_UART_BGR1_EXT *((volatile unsigned int*)(0x427141BCUL)) -#define bFM4_MFS10_UART_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_UART_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_UART_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_UART_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_UART_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_UART_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_UART_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_UART_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_UART_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_UART_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_UART_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_UART_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_UART_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_UART_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_UART_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_UART_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_UART_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_UART_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) -#define bFM4_MFS10_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) - -/* MFS CSIO channel 10 registers */ -#define bFM4_MFS10_CSIO_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) -#define bFM4_MFS10_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42714004UL)) -#define bFM4_MFS10_CSIO_SMR_BDS *((volatile unsigned int*)(0x42714008UL)) -#define bFM4_MFS10_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271400CUL)) -#define bFM4_MFS10_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) -#define bFM4_MFS10_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) -#define bFM4_MFS10_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) -#define bFM4_MFS10_CSIO_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) -#define bFM4_MFS10_CSIO_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) -#define bFM4_MFS10_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) -#define bFM4_MFS10_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) -#define bFM4_MFS10_CSIO_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) -#define bFM4_MFS10_CSIO_SCR_SPI *((volatile unsigned int*)(0x42714034UL)) -#define bFM4_MFS10_CSIO_SCR_MS *((volatile unsigned int*)(0x42714038UL)) -#define bFM4_MFS10_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) -#define bFM4_MFS10_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42714080UL)) -#define bFM4_MFS10_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42714084UL)) -#define bFM4_MFS10_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42714088UL)) -#define bFM4_MFS10_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271408CUL)) -#define bFM4_MFS10_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42714090UL)) -#define bFM4_MFS10_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42714098UL)) -#define bFM4_MFS10_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271409CUL)) -#define bFM4_MFS10_CSIO_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) -#define bFM4_MFS10_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) -#define bFM4_MFS10_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) -#define bFM4_MFS10_CSIO_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) -#define bFM4_MFS10_CSIO_SSR_AWC *((volatile unsigned int*)(0x427140B0UL)) -#define bFM4_MFS10_CSIO_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) -#define bFM4_MFS10_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_CSIO_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_CSIO_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_CSIO_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42714380UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42714384UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42714388UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271438CUL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42714390UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42714394UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42714398UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271439CUL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427143A0UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427143A4UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427143A8UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427143ACUL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427143B0UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427143B4UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427143B8UL)) -#define bFM4_MFS10_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427143BCUL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42714400UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42714404UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42714408UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271440CUL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42714410UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42714414UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42714418UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271441CUL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42714420UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42714424UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42714428UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271442CUL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42714430UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42714434UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42714438UL)) -#define bFM4_MFS10_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271443CUL)) -#define bFM4_MFS10_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42714480UL)) -#define bFM4_MFS10_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42714484UL)) -#define bFM4_MFS10_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42714488UL)) -#define bFM4_MFS10_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271448CUL)) -#define bFM4_MFS10_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42714490UL)) -#define bFM4_MFS10_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42714498UL)) -#define bFM4_MFS10_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271449CUL)) -#define bFM4_MFS10_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427144A0UL)) -#define bFM4_MFS10_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427144ACUL)) -#define bFM4_MFS10_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427144B0UL)) -#define bFM4_MFS10_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427144B4UL)) -#define bFM4_MFS10_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42714500UL)) -#define bFM4_MFS10_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42714504UL)) -#define bFM4_MFS10_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42714508UL)) -#define bFM4_MFS10_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271450CUL)) -#define bFM4_MFS10_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42714510UL)) -#define bFM4_MFS10_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42714514UL)) -#define bFM4_MFS10_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42714518UL)) -#define bFM4_MFS10_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271451CUL)) -#define bFM4_MFS10_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42714520UL)) -#define bFM4_MFS10_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42714524UL)) -#define bFM4_MFS10_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42714528UL)) -#define bFM4_MFS10_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271452CUL)) -#define bFM4_MFS10_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42714530UL)) -#define bFM4_MFS10_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42714534UL)) -#define bFM4_MFS10_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42714538UL)) -#define bFM4_MFS10_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271453CUL)) -#define bFM4_MFS10_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42714580UL)) -#define bFM4_MFS10_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42714584UL)) -#define bFM4_MFS10_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42714588UL)) -#define bFM4_MFS10_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271458CUL)) -#define bFM4_MFS10_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42714590UL)) -#define bFM4_MFS10_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42714594UL)) -#define bFM4_MFS10_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42714598UL)) -#define bFM4_MFS10_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271459CUL)) -#define bFM4_MFS10_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427145A0UL)) -#define bFM4_MFS10_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427145A4UL)) -#define bFM4_MFS10_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427145A8UL)) -#define bFM4_MFS10_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427145ACUL)) -#define bFM4_MFS10_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427145B0UL)) -#define bFM4_MFS10_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427145B4UL)) -#define bFM4_MFS10_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427145B8UL)) -#define bFM4_MFS10_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427145BCUL)) -#define bFM4_MFS10_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42714600UL)) -#define bFM4_MFS10_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42714604UL)) -#define bFM4_MFS10_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42714614UL)) -#define bFM4_MFS10_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42714618UL)) -#define bFM4_MFS10_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271461CUL)) -#define bFM4_MFS10_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42714620UL)) -#define bFM4_MFS10_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42714624UL)) - -/* MFS LIN channel 10 registers */ -#define bFM4_MFS10_LIN_SMR_SOE *((volatile unsigned int*)(0x42714000UL)) -#define bFM4_MFS10_LIN_SMR_SBL *((volatile unsigned int*)(0x4271400CUL)) -#define bFM4_MFS10_LIN_SMR_WUCR *((volatile unsigned int*)(0x42714010UL)) -#define bFM4_MFS10_LIN_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) -#define bFM4_MFS10_LIN_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) -#define bFM4_MFS10_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) -#define bFM4_MFS10_LIN_SCR_TXE *((volatile unsigned int*)(0x42714020UL)) -#define bFM4_MFS10_LIN_SCR_RXE *((volatile unsigned int*)(0x42714024UL)) -#define bFM4_MFS10_LIN_SCR_TBIE *((volatile unsigned int*)(0x42714028UL)) -#define bFM4_MFS10_LIN_SCR_TIE *((volatile unsigned int*)(0x4271402CUL)) -#define bFM4_MFS10_LIN_SCR_RIE *((volatile unsigned int*)(0x42714030UL)) -#define bFM4_MFS10_LIN_SCR_LBR *((volatile unsigned int*)(0x42714034UL)) -#define bFM4_MFS10_LIN_SCR_MS *((volatile unsigned int*)(0x42714038UL)) -#define bFM4_MFS10_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271403CUL)) -#define bFM4_MFS10_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42714080UL)) -#define bFM4_MFS10_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42714084UL)) -#define bFM4_MFS10_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42714088UL)) -#define bFM4_MFS10_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271408CUL)) -#define bFM4_MFS10_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42714090UL)) -#define bFM4_MFS10_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42714098UL)) -#define bFM4_MFS10_LIN_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) -#define bFM4_MFS10_LIN_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) -#define bFM4_MFS10_LIN_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) -#define bFM4_MFS10_LIN_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) -#define bFM4_MFS10_LIN_SSR_FRE *((volatile unsigned int*)(0x427140B0UL)) -#define bFM4_MFS10_LIN_SSR_LBD *((volatile unsigned int*)(0x427140B4UL)) -#define bFM4_MFS10_LIN_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) -#define bFM4_MFS10_LIN_BGR_EXT *((volatile unsigned int*)(0x427141BCUL)) -#define bFM4_MFS10_LIN_BGR1_EXT *((volatile unsigned int*)(0x427141BCUL)) -#define bFM4_MFS10_LIN_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_LIN_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_LIN_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_LIN_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_LIN_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_LIN_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_LIN_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_LIN_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_LIN_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_LIN_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) -#define bFM4_MFS10_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) - -/* MFS I2C channel 10 registers */ -#define bFM4_MFS10_I2C_SMR_TIE *((volatile unsigned int*)(0x42714008UL)) -#define bFM4_MFS10_I2C_SMR_RIE *((volatile unsigned int*)(0x4271400CUL)) -#define bFM4_MFS10_I2C_SMR_MD0 *((volatile unsigned int*)(0x42714014UL)) -#define bFM4_MFS10_I2C_SMR_MD1 *((volatile unsigned int*)(0x42714018UL)) -#define bFM4_MFS10_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271401CUL)) -#define bFM4_MFS10_I2C_IBCR_INT *((volatile unsigned int*)(0x42714020UL)) -#define bFM4_MFS10_I2C_IBCR_BER *((volatile unsigned int*)(0x42714024UL)) -#define bFM4_MFS10_I2C_IBCR_INTE *((volatile unsigned int*)(0x42714028UL)) -#define bFM4_MFS10_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271402CUL)) -#define bFM4_MFS10_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42714030UL)) -#define bFM4_MFS10_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42714034UL)) -#define bFM4_MFS10_I2C_IBCR_ACT *((volatile unsigned int*)(0x42714038UL)) -#define bFM4_MFS10_I2C_IBCR_SCC *((volatile unsigned int*)(0x42714038UL)) -#define bFM4_MFS10_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271403CUL)) -#define bFM4_MFS10_I2C_IBSR_BB *((volatile unsigned int*)(0x42714080UL)) -#define bFM4_MFS10_I2C_IBSR_SPC *((volatile unsigned int*)(0x42714084UL)) -#define bFM4_MFS10_I2C_IBSR_RSC *((volatile unsigned int*)(0x42714088UL)) -#define bFM4_MFS10_I2C_IBSR_AL *((volatile unsigned int*)(0x4271408CUL)) -#define bFM4_MFS10_I2C_IBSR_TRX *((volatile unsigned int*)(0x42714090UL)) -#define bFM4_MFS10_I2C_IBSR_RSA *((volatile unsigned int*)(0x42714094UL)) -#define bFM4_MFS10_I2C_IBSR_RACK *((volatile unsigned int*)(0x42714098UL)) -#define bFM4_MFS10_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271409CUL)) -#define bFM4_MFS10_I2C_SSR_TBI *((volatile unsigned int*)(0x427140A0UL)) -#define bFM4_MFS10_I2C_SSR_TDRE *((volatile unsigned int*)(0x427140A4UL)) -#define bFM4_MFS10_I2C_SSR_RDRF *((volatile unsigned int*)(0x427140A8UL)) -#define bFM4_MFS10_I2C_SSR_ORE *((volatile unsigned int*)(0x427140ACUL)) -#define bFM4_MFS10_I2C_SSR_TBIE *((volatile unsigned int*)(0x427140B0UL)) -#define bFM4_MFS10_I2C_SSR_DMA *((volatile unsigned int*)(0x427140B4UL)) -#define bFM4_MFS10_I2C_SSR_TSET *((volatile unsigned int*)(0x427140B8UL)) -#define bFM4_MFS10_I2C_SSR_REC *((volatile unsigned int*)(0x427140BCUL)) -#define bFM4_MFS10_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42714200UL)) -#define bFM4_MFS10_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42714204UL)) -#define bFM4_MFS10_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42714208UL)) -#define bFM4_MFS10_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271420CUL)) -#define bFM4_MFS10_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42714210UL)) -#define bFM4_MFS10_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42714214UL)) -#define bFM4_MFS10_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42714218UL)) -#define bFM4_MFS10_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271421CUL)) -#define bFM4_MFS10_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42714220UL)) -#define bFM4_MFS10_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42714224UL)) -#define bFM4_MFS10_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42714228UL)) -#define bFM4_MFS10_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271422CUL)) -#define bFM4_MFS10_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42714230UL)) -#define bFM4_MFS10_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42714234UL)) -#define bFM4_MFS10_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42714238UL)) -#define bFM4_MFS10_I2C_ISMK_EN *((volatile unsigned int*)(0x4271423CUL)) -#define bFM4_MFS10_I2C_FCR_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_I2C_FCR_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_I2C_FCR_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_I2C_FCR_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_I2C_FCR_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_I2C_FCR_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_I2C_FCR_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42714280UL)) -#define bFM4_MFS10_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42714284UL)) -#define bFM4_MFS10_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42714288UL)) -#define bFM4_MFS10_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271428CUL)) -#define bFM4_MFS10_I2C_FCR0_FSET *((volatile unsigned int*)(0x42714290UL)) -#define bFM4_MFS10_I2C_FCR0_FLD *((volatile unsigned int*)(0x42714294UL)) -#define bFM4_MFS10_I2C_FCR0_FLST *((volatile unsigned int*)(0x42714298UL)) -#define bFM4_MFS10_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427142A0UL)) -#define bFM4_MFS10_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427142A4UL)) -#define bFM4_MFS10_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427142A8UL)) -#define bFM4_MFS10_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427142ACUL)) -#define bFM4_MFS10_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427142B0UL)) -#define bFM4_MFS10_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271433CUL)) -#define bFM4_MFS10_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42714300UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42714304UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42714308UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271430CUL)) -#define bFM4_MFS10_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42714310UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42714314UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42714318UL)) -#define bFM4_MFS10_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271431CUL)) -#define bFM4_MFS10_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42714320UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42714324UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42714328UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271432CUL)) -#define bFM4_MFS10_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42714330UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42714334UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42714338UL)) -#define bFM4_MFS10_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271433CUL)) - -/* MFS UART channel 11 registers */ -#define bFM4_MFS11_UART_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) -#define bFM4_MFS11_UART_SMR_BDS *((volatile unsigned int*)(0x42716008UL)) -#define bFM4_MFS11_UART_SMR_SBL *((volatile unsigned int*)(0x4271600CUL)) -#define bFM4_MFS11_UART_SMR_WUCR *((volatile unsigned int*)(0x42716010UL)) -#define bFM4_MFS11_UART_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) -#define bFM4_MFS11_UART_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) -#define bFM4_MFS11_UART_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) -#define bFM4_MFS11_UART_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) -#define bFM4_MFS11_UART_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) -#define bFM4_MFS11_UART_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) -#define bFM4_MFS11_UART_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) -#define bFM4_MFS11_UART_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) -#define bFM4_MFS11_UART_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) -#define bFM4_MFS11_UART_ESCR_L0 *((volatile unsigned int*)(0x42716080UL)) -#define bFM4_MFS11_UART_ESCR_L1 *((volatile unsigned int*)(0x42716084UL)) -#define bFM4_MFS11_UART_ESCR_L2 *((volatile unsigned int*)(0x42716088UL)) -#define bFM4_MFS11_UART_ESCR_P *((volatile unsigned int*)(0x4271608CUL)) -#define bFM4_MFS11_UART_ESCR_PEN *((volatile unsigned int*)(0x42716090UL)) -#define bFM4_MFS11_UART_ESCR_INV *((volatile unsigned int*)(0x42716094UL)) -#define bFM4_MFS11_UART_ESCR_ESBL *((volatile unsigned int*)(0x42716098UL)) -#define bFM4_MFS11_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271609CUL)) -#define bFM4_MFS11_UART_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) -#define bFM4_MFS11_UART_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) -#define bFM4_MFS11_UART_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) -#define bFM4_MFS11_UART_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) -#define bFM4_MFS11_UART_SSR_FRE *((volatile unsigned int*)(0x427160B0UL)) -#define bFM4_MFS11_UART_SSR_PE *((volatile unsigned int*)(0x427160B4UL)) -#define bFM4_MFS11_UART_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) -#define bFM4_MFS11_UART_RDR_AD *((volatile unsigned int*)(0x42716120UL)) -#define bFM4_MFS11_UART_TDR_AD *((volatile unsigned int*)(0x42716120UL)) -#define bFM4_MFS11_UART_BGR_EXT *((volatile unsigned int*)(0x427161BCUL)) -#define bFM4_MFS11_UART_BGR1_EXT *((volatile unsigned int*)(0x427161BCUL)) -#define bFM4_MFS11_UART_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_UART_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_UART_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_UART_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_UART_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_UART_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_UART_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_UART_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_UART_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_UART_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_UART_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_UART_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_UART_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_UART_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_UART_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_UART_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_UART_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_UART_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) -#define bFM4_MFS11_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) - -/* MFS CSIO channel 11 registers */ -#define bFM4_MFS11_CSIO_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) -#define bFM4_MFS11_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42716004UL)) -#define bFM4_MFS11_CSIO_SMR_BDS *((volatile unsigned int*)(0x42716008UL)) -#define bFM4_MFS11_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271600CUL)) -#define bFM4_MFS11_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) -#define bFM4_MFS11_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) -#define bFM4_MFS11_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) -#define bFM4_MFS11_CSIO_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) -#define bFM4_MFS11_CSIO_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) -#define bFM4_MFS11_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) -#define bFM4_MFS11_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) -#define bFM4_MFS11_CSIO_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) -#define bFM4_MFS11_CSIO_SCR_SPI *((volatile unsigned int*)(0x42716034UL)) -#define bFM4_MFS11_CSIO_SCR_MS *((volatile unsigned int*)(0x42716038UL)) -#define bFM4_MFS11_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) -#define bFM4_MFS11_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42716080UL)) -#define bFM4_MFS11_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42716084UL)) -#define bFM4_MFS11_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42716088UL)) -#define bFM4_MFS11_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271608CUL)) -#define bFM4_MFS11_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42716090UL)) -#define bFM4_MFS11_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42716098UL)) -#define bFM4_MFS11_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271609CUL)) -#define bFM4_MFS11_CSIO_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) -#define bFM4_MFS11_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) -#define bFM4_MFS11_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) -#define bFM4_MFS11_CSIO_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) -#define bFM4_MFS11_CSIO_SSR_AWC *((volatile unsigned int*)(0x427160B0UL)) -#define bFM4_MFS11_CSIO_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) -#define bFM4_MFS11_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_CSIO_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_CSIO_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_CSIO_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42716380UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42716384UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42716388UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271638CUL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42716390UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42716394UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42716398UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271639CUL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427163A0UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427163A4UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427163A8UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427163ACUL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427163B0UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427163B4UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427163B8UL)) -#define bFM4_MFS11_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427163BCUL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42716400UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42716404UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42716408UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271640CUL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42716410UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42716414UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42716418UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271641CUL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42716420UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42716424UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42716428UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271642CUL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42716430UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42716434UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42716438UL)) -#define bFM4_MFS11_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271643CUL)) -#define bFM4_MFS11_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42716480UL)) -#define bFM4_MFS11_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42716484UL)) -#define bFM4_MFS11_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42716488UL)) -#define bFM4_MFS11_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271648CUL)) -#define bFM4_MFS11_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42716490UL)) -#define bFM4_MFS11_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42716498UL)) -#define bFM4_MFS11_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271649CUL)) -#define bFM4_MFS11_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427164A0UL)) -#define bFM4_MFS11_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427164ACUL)) -#define bFM4_MFS11_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427164B0UL)) -#define bFM4_MFS11_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427164B4UL)) -#define bFM4_MFS11_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42716500UL)) -#define bFM4_MFS11_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42716504UL)) -#define bFM4_MFS11_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42716508UL)) -#define bFM4_MFS11_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271650CUL)) -#define bFM4_MFS11_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42716510UL)) -#define bFM4_MFS11_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42716514UL)) -#define bFM4_MFS11_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42716518UL)) -#define bFM4_MFS11_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271651CUL)) -#define bFM4_MFS11_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42716520UL)) -#define bFM4_MFS11_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42716524UL)) -#define bFM4_MFS11_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42716528UL)) -#define bFM4_MFS11_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271652CUL)) -#define bFM4_MFS11_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42716530UL)) -#define bFM4_MFS11_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42716534UL)) -#define bFM4_MFS11_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42716538UL)) -#define bFM4_MFS11_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271653CUL)) -#define bFM4_MFS11_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42716580UL)) -#define bFM4_MFS11_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42716584UL)) -#define bFM4_MFS11_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42716588UL)) -#define bFM4_MFS11_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271658CUL)) -#define bFM4_MFS11_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42716590UL)) -#define bFM4_MFS11_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42716594UL)) -#define bFM4_MFS11_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42716598UL)) -#define bFM4_MFS11_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271659CUL)) -#define bFM4_MFS11_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427165A0UL)) -#define bFM4_MFS11_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427165A4UL)) -#define bFM4_MFS11_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427165A8UL)) -#define bFM4_MFS11_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427165ACUL)) -#define bFM4_MFS11_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427165B0UL)) -#define bFM4_MFS11_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427165B4UL)) -#define bFM4_MFS11_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427165B8UL)) -#define bFM4_MFS11_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427165BCUL)) -#define bFM4_MFS11_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42716600UL)) -#define bFM4_MFS11_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42716604UL)) -#define bFM4_MFS11_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42716614UL)) -#define bFM4_MFS11_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42716618UL)) -#define bFM4_MFS11_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271661CUL)) -#define bFM4_MFS11_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42716620UL)) -#define bFM4_MFS11_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42716624UL)) - -/* MFS LIN channel 11 registers */ -#define bFM4_MFS11_LIN_SMR_SOE *((volatile unsigned int*)(0x42716000UL)) -#define bFM4_MFS11_LIN_SMR_SBL *((volatile unsigned int*)(0x4271600CUL)) -#define bFM4_MFS11_LIN_SMR_WUCR *((volatile unsigned int*)(0x42716010UL)) -#define bFM4_MFS11_LIN_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) -#define bFM4_MFS11_LIN_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) -#define bFM4_MFS11_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) -#define bFM4_MFS11_LIN_SCR_TXE *((volatile unsigned int*)(0x42716020UL)) -#define bFM4_MFS11_LIN_SCR_RXE *((volatile unsigned int*)(0x42716024UL)) -#define bFM4_MFS11_LIN_SCR_TBIE *((volatile unsigned int*)(0x42716028UL)) -#define bFM4_MFS11_LIN_SCR_TIE *((volatile unsigned int*)(0x4271602CUL)) -#define bFM4_MFS11_LIN_SCR_RIE *((volatile unsigned int*)(0x42716030UL)) -#define bFM4_MFS11_LIN_SCR_LBR *((volatile unsigned int*)(0x42716034UL)) -#define bFM4_MFS11_LIN_SCR_MS *((volatile unsigned int*)(0x42716038UL)) -#define bFM4_MFS11_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271603CUL)) -#define bFM4_MFS11_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42716080UL)) -#define bFM4_MFS11_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42716084UL)) -#define bFM4_MFS11_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42716088UL)) -#define bFM4_MFS11_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271608CUL)) -#define bFM4_MFS11_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42716090UL)) -#define bFM4_MFS11_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42716098UL)) -#define bFM4_MFS11_LIN_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) -#define bFM4_MFS11_LIN_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) -#define bFM4_MFS11_LIN_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) -#define bFM4_MFS11_LIN_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) -#define bFM4_MFS11_LIN_SSR_FRE *((volatile unsigned int*)(0x427160B0UL)) -#define bFM4_MFS11_LIN_SSR_LBD *((volatile unsigned int*)(0x427160B4UL)) -#define bFM4_MFS11_LIN_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) -#define bFM4_MFS11_LIN_BGR_EXT *((volatile unsigned int*)(0x427161BCUL)) -#define bFM4_MFS11_LIN_BGR1_EXT *((volatile unsigned int*)(0x427161BCUL)) -#define bFM4_MFS11_LIN_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_LIN_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_LIN_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_LIN_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_LIN_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_LIN_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_LIN_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_LIN_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_LIN_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_LIN_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) -#define bFM4_MFS11_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) - -/* MFS I2C channel 11 registers */ -#define bFM4_MFS11_I2C_SMR_TIE *((volatile unsigned int*)(0x42716008UL)) -#define bFM4_MFS11_I2C_SMR_RIE *((volatile unsigned int*)(0x4271600CUL)) -#define bFM4_MFS11_I2C_SMR_MD0 *((volatile unsigned int*)(0x42716014UL)) -#define bFM4_MFS11_I2C_SMR_MD1 *((volatile unsigned int*)(0x42716018UL)) -#define bFM4_MFS11_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271601CUL)) -#define bFM4_MFS11_I2C_IBCR_INT *((volatile unsigned int*)(0x42716020UL)) -#define bFM4_MFS11_I2C_IBCR_BER *((volatile unsigned int*)(0x42716024UL)) -#define bFM4_MFS11_I2C_IBCR_INTE *((volatile unsigned int*)(0x42716028UL)) -#define bFM4_MFS11_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271602CUL)) -#define bFM4_MFS11_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42716030UL)) -#define bFM4_MFS11_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42716034UL)) -#define bFM4_MFS11_I2C_IBCR_ACT *((volatile unsigned int*)(0x42716038UL)) -#define bFM4_MFS11_I2C_IBCR_SCC *((volatile unsigned int*)(0x42716038UL)) -#define bFM4_MFS11_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271603CUL)) -#define bFM4_MFS11_I2C_IBSR_BB *((volatile unsigned int*)(0x42716080UL)) -#define bFM4_MFS11_I2C_IBSR_SPC *((volatile unsigned int*)(0x42716084UL)) -#define bFM4_MFS11_I2C_IBSR_RSC *((volatile unsigned int*)(0x42716088UL)) -#define bFM4_MFS11_I2C_IBSR_AL *((volatile unsigned int*)(0x4271608CUL)) -#define bFM4_MFS11_I2C_IBSR_TRX *((volatile unsigned int*)(0x42716090UL)) -#define bFM4_MFS11_I2C_IBSR_RSA *((volatile unsigned int*)(0x42716094UL)) -#define bFM4_MFS11_I2C_IBSR_RACK *((volatile unsigned int*)(0x42716098UL)) -#define bFM4_MFS11_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271609CUL)) -#define bFM4_MFS11_I2C_SSR_TBI *((volatile unsigned int*)(0x427160A0UL)) -#define bFM4_MFS11_I2C_SSR_TDRE *((volatile unsigned int*)(0x427160A4UL)) -#define bFM4_MFS11_I2C_SSR_RDRF *((volatile unsigned int*)(0x427160A8UL)) -#define bFM4_MFS11_I2C_SSR_ORE *((volatile unsigned int*)(0x427160ACUL)) -#define bFM4_MFS11_I2C_SSR_TBIE *((volatile unsigned int*)(0x427160B0UL)) -#define bFM4_MFS11_I2C_SSR_DMA *((volatile unsigned int*)(0x427160B4UL)) -#define bFM4_MFS11_I2C_SSR_TSET *((volatile unsigned int*)(0x427160B8UL)) -#define bFM4_MFS11_I2C_SSR_REC *((volatile unsigned int*)(0x427160BCUL)) -#define bFM4_MFS11_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42716200UL)) -#define bFM4_MFS11_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42716204UL)) -#define bFM4_MFS11_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42716208UL)) -#define bFM4_MFS11_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271620CUL)) -#define bFM4_MFS11_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42716210UL)) -#define bFM4_MFS11_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42716214UL)) -#define bFM4_MFS11_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42716218UL)) -#define bFM4_MFS11_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271621CUL)) -#define bFM4_MFS11_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42716220UL)) -#define bFM4_MFS11_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42716224UL)) -#define bFM4_MFS11_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42716228UL)) -#define bFM4_MFS11_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271622CUL)) -#define bFM4_MFS11_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42716230UL)) -#define bFM4_MFS11_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42716234UL)) -#define bFM4_MFS11_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42716238UL)) -#define bFM4_MFS11_I2C_ISMK_EN *((volatile unsigned int*)(0x4271623CUL)) -#define bFM4_MFS11_I2C_FCR_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_I2C_FCR_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_I2C_FCR_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_I2C_FCR_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_I2C_FCR_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_I2C_FCR_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_I2C_FCR_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42716280UL)) -#define bFM4_MFS11_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42716284UL)) -#define bFM4_MFS11_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42716288UL)) -#define bFM4_MFS11_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271628CUL)) -#define bFM4_MFS11_I2C_FCR0_FSET *((volatile unsigned int*)(0x42716290UL)) -#define bFM4_MFS11_I2C_FCR0_FLD *((volatile unsigned int*)(0x42716294UL)) -#define bFM4_MFS11_I2C_FCR0_FLST *((volatile unsigned int*)(0x42716298UL)) -#define bFM4_MFS11_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427162A0UL)) -#define bFM4_MFS11_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427162A4UL)) -#define bFM4_MFS11_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427162A8UL)) -#define bFM4_MFS11_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427162ACUL)) -#define bFM4_MFS11_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427162B0UL)) -#define bFM4_MFS11_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271633CUL)) -#define bFM4_MFS11_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42716300UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42716304UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42716308UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271630CUL)) -#define bFM4_MFS11_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42716310UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42716314UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42716318UL)) -#define bFM4_MFS11_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271631CUL)) -#define bFM4_MFS11_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42716320UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42716324UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42716328UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271632CUL)) -#define bFM4_MFS11_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42716330UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42716334UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42716338UL)) -#define bFM4_MFS11_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271633CUL)) - -/* MFS UART channel 12 registers */ -#define bFM4_MFS12_UART_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) -#define bFM4_MFS12_UART_SMR_BDS *((volatile unsigned int*)(0x42718008UL)) -#define bFM4_MFS12_UART_SMR_SBL *((volatile unsigned int*)(0x4271800CUL)) -#define bFM4_MFS12_UART_SMR_WUCR *((volatile unsigned int*)(0x42718010UL)) -#define bFM4_MFS12_UART_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) -#define bFM4_MFS12_UART_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) -#define bFM4_MFS12_UART_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) -#define bFM4_MFS12_UART_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) -#define bFM4_MFS12_UART_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) -#define bFM4_MFS12_UART_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) -#define bFM4_MFS12_UART_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) -#define bFM4_MFS12_UART_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) -#define bFM4_MFS12_UART_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) -#define bFM4_MFS12_UART_ESCR_L0 *((volatile unsigned int*)(0x42718080UL)) -#define bFM4_MFS12_UART_ESCR_L1 *((volatile unsigned int*)(0x42718084UL)) -#define bFM4_MFS12_UART_ESCR_L2 *((volatile unsigned int*)(0x42718088UL)) -#define bFM4_MFS12_UART_ESCR_P *((volatile unsigned int*)(0x4271808CUL)) -#define bFM4_MFS12_UART_ESCR_PEN *((volatile unsigned int*)(0x42718090UL)) -#define bFM4_MFS12_UART_ESCR_INV *((volatile unsigned int*)(0x42718094UL)) -#define bFM4_MFS12_UART_ESCR_ESBL *((volatile unsigned int*)(0x42718098UL)) -#define bFM4_MFS12_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271809CUL)) -#define bFM4_MFS12_UART_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) -#define bFM4_MFS12_UART_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) -#define bFM4_MFS12_UART_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) -#define bFM4_MFS12_UART_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) -#define bFM4_MFS12_UART_SSR_FRE *((volatile unsigned int*)(0x427180B0UL)) -#define bFM4_MFS12_UART_SSR_PE *((volatile unsigned int*)(0x427180B4UL)) -#define bFM4_MFS12_UART_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) -#define bFM4_MFS12_UART_RDR_AD *((volatile unsigned int*)(0x42718120UL)) -#define bFM4_MFS12_UART_TDR_AD *((volatile unsigned int*)(0x42718120UL)) -#define bFM4_MFS12_UART_BGR_EXT *((volatile unsigned int*)(0x427181BCUL)) -#define bFM4_MFS12_UART_BGR1_EXT *((volatile unsigned int*)(0x427181BCUL)) -#define bFM4_MFS12_UART_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_UART_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_UART_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_UART_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_UART_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_UART_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_UART_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_UART_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_UART_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_UART_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_UART_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_UART_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_UART_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_UART_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_UART_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_UART_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_UART_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_UART_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_UART_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) -#define bFM4_MFS12_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) - -/* MFS CSIO channel 12 registers */ -#define bFM4_MFS12_CSIO_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) -#define bFM4_MFS12_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42718004UL)) -#define bFM4_MFS12_CSIO_SMR_BDS *((volatile unsigned int*)(0x42718008UL)) -#define bFM4_MFS12_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271800CUL)) -#define bFM4_MFS12_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) -#define bFM4_MFS12_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) -#define bFM4_MFS12_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) -#define bFM4_MFS12_CSIO_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) -#define bFM4_MFS12_CSIO_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) -#define bFM4_MFS12_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) -#define bFM4_MFS12_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) -#define bFM4_MFS12_CSIO_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) -#define bFM4_MFS12_CSIO_SCR_SPI *((volatile unsigned int*)(0x42718034UL)) -#define bFM4_MFS12_CSIO_SCR_MS *((volatile unsigned int*)(0x42718038UL)) -#define bFM4_MFS12_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) -#define bFM4_MFS12_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42718080UL)) -#define bFM4_MFS12_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42718084UL)) -#define bFM4_MFS12_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42718088UL)) -#define bFM4_MFS12_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271808CUL)) -#define bFM4_MFS12_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42718090UL)) -#define bFM4_MFS12_CSIO_ESCR_L3 *((volatile unsigned int*)(0x42718098UL)) -#define bFM4_MFS12_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271809CUL)) -#define bFM4_MFS12_CSIO_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) -#define bFM4_MFS12_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) -#define bFM4_MFS12_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) -#define bFM4_MFS12_CSIO_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) -#define bFM4_MFS12_CSIO_SSR_AWC *((volatile unsigned int*)(0x427180B0UL)) -#define bFM4_MFS12_CSIO_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) -#define bFM4_MFS12_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_CSIO_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_CSIO_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_CSIO_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x42718380UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x42718384UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x42718388UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271838CUL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x42718390UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x42718394UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x42718398UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271839CUL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x427183A0UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x427183A4UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x427183A8UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x427183ACUL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x427183B0UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x427183B4UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x427183B8UL)) -#define bFM4_MFS12_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x427183BCUL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x42718400UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x42718404UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x42718408UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271840CUL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x42718410UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x42718414UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x42718418UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271841CUL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x42718420UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x42718424UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x42718428UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271842CUL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x42718430UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x42718434UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x42718438UL)) -#define bFM4_MFS12_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271843CUL)) -#define bFM4_MFS12_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x42718480UL)) -#define bFM4_MFS12_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x42718484UL)) -#define bFM4_MFS12_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x42718488UL)) -#define bFM4_MFS12_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271848CUL)) -#define bFM4_MFS12_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x42718490UL)) -#define bFM4_MFS12_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x42718498UL)) -#define bFM4_MFS12_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271849CUL)) -#define bFM4_MFS12_CSIO_SACSR_TINT *((volatile unsigned int*)(0x427184A0UL)) -#define bFM4_MFS12_CSIO_SACSR_CSE *((volatile unsigned int*)(0x427184ACUL)) -#define bFM4_MFS12_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x427184B0UL)) -#define bFM4_MFS12_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x427184B4UL)) -#define bFM4_MFS12_CSIO_STMR_TM0 *((volatile unsigned int*)(0x42718500UL)) -#define bFM4_MFS12_CSIO_STMR_TM1 *((volatile unsigned int*)(0x42718504UL)) -#define bFM4_MFS12_CSIO_STMR_TM2 *((volatile unsigned int*)(0x42718508UL)) -#define bFM4_MFS12_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271850CUL)) -#define bFM4_MFS12_CSIO_STMR_TM4 *((volatile unsigned int*)(0x42718510UL)) -#define bFM4_MFS12_CSIO_STMR_TM5 *((volatile unsigned int*)(0x42718514UL)) -#define bFM4_MFS12_CSIO_STMR_TM6 *((volatile unsigned int*)(0x42718518UL)) -#define bFM4_MFS12_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271851CUL)) -#define bFM4_MFS12_CSIO_STMR_TM8 *((volatile unsigned int*)(0x42718520UL)) -#define bFM4_MFS12_CSIO_STMR_TM9 *((volatile unsigned int*)(0x42718524UL)) -#define bFM4_MFS12_CSIO_STMR_TM10 *((volatile unsigned int*)(0x42718528UL)) -#define bFM4_MFS12_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271852CUL)) -#define bFM4_MFS12_CSIO_STMR_TM12 *((volatile unsigned int*)(0x42718530UL)) -#define bFM4_MFS12_CSIO_STMR_TM13 *((volatile unsigned int*)(0x42718534UL)) -#define bFM4_MFS12_CSIO_STMR_TM14 *((volatile unsigned int*)(0x42718538UL)) -#define bFM4_MFS12_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271853CUL)) -#define bFM4_MFS12_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x42718580UL)) -#define bFM4_MFS12_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x42718584UL)) -#define bFM4_MFS12_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x42718588UL)) -#define bFM4_MFS12_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271858CUL)) -#define bFM4_MFS12_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x42718590UL)) -#define bFM4_MFS12_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x42718594UL)) -#define bFM4_MFS12_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x42718598UL)) -#define bFM4_MFS12_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271859CUL)) -#define bFM4_MFS12_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x427185A0UL)) -#define bFM4_MFS12_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x427185A4UL)) -#define bFM4_MFS12_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x427185A8UL)) -#define bFM4_MFS12_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x427185ACUL)) -#define bFM4_MFS12_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x427185B0UL)) -#define bFM4_MFS12_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x427185B4UL)) -#define bFM4_MFS12_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x427185B8UL)) -#define bFM4_MFS12_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x427185BCUL)) -#define bFM4_MFS12_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x42718600UL)) -#define bFM4_MFS12_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x42718604UL)) -#define bFM4_MFS12_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x42718614UL)) -#define bFM4_MFS12_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x42718618UL)) -#define bFM4_MFS12_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271861CUL)) -#define bFM4_MFS12_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x42718620UL)) -#define bFM4_MFS12_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x42718624UL)) - -/* MFS LIN channel 12 registers */ -#define bFM4_MFS12_LIN_SMR_SOE *((volatile unsigned int*)(0x42718000UL)) -#define bFM4_MFS12_LIN_SMR_SBL *((volatile unsigned int*)(0x4271800CUL)) -#define bFM4_MFS12_LIN_SMR_WUCR *((volatile unsigned int*)(0x42718010UL)) -#define bFM4_MFS12_LIN_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) -#define bFM4_MFS12_LIN_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) -#define bFM4_MFS12_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) -#define bFM4_MFS12_LIN_SCR_TXE *((volatile unsigned int*)(0x42718020UL)) -#define bFM4_MFS12_LIN_SCR_RXE *((volatile unsigned int*)(0x42718024UL)) -#define bFM4_MFS12_LIN_SCR_TBIE *((volatile unsigned int*)(0x42718028UL)) -#define bFM4_MFS12_LIN_SCR_TIE *((volatile unsigned int*)(0x4271802CUL)) -#define bFM4_MFS12_LIN_SCR_RIE *((volatile unsigned int*)(0x42718030UL)) -#define bFM4_MFS12_LIN_SCR_LBR *((volatile unsigned int*)(0x42718034UL)) -#define bFM4_MFS12_LIN_SCR_MS *((volatile unsigned int*)(0x42718038UL)) -#define bFM4_MFS12_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271803CUL)) -#define bFM4_MFS12_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42718080UL)) -#define bFM4_MFS12_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42718084UL)) -#define bFM4_MFS12_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42718088UL)) -#define bFM4_MFS12_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271808CUL)) -#define bFM4_MFS12_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42718090UL)) -#define bFM4_MFS12_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42718098UL)) -#define bFM4_MFS12_LIN_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) -#define bFM4_MFS12_LIN_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) -#define bFM4_MFS12_LIN_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) -#define bFM4_MFS12_LIN_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) -#define bFM4_MFS12_LIN_SSR_FRE *((volatile unsigned int*)(0x427180B0UL)) -#define bFM4_MFS12_LIN_SSR_LBD *((volatile unsigned int*)(0x427180B4UL)) -#define bFM4_MFS12_LIN_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) -#define bFM4_MFS12_LIN_BGR_EXT *((volatile unsigned int*)(0x427181BCUL)) -#define bFM4_MFS12_LIN_BGR1_EXT *((volatile unsigned int*)(0x427181BCUL)) -#define bFM4_MFS12_LIN_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_LIN_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_LIN_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_LIN_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_LIN_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_LIN_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_LIN_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_LIN_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_LIN_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_LIN_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_LIN_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) -#define bFM4_MFS12_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) - -/* MFS I2C channel 12 registers */ -#define bFM4_MFS12_I2C_SMR_TIE *((volatile unsigned int*)(0x42718008UL)) -#define bFM4_MFS12_I2C_SMR_RIE *((volatile unsigned int*)(0x4271800CUL)) -#define bFM4_MFS12_I2C_SMR_MD0 *((volatile unsigned int*)(0x42718014UL)) -#define bFM4_MFS12_I2C_SMR_MD1 *((volatile unsigned int*)(0x42718018UL)) -#define bFM4_MFS12_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271801CUL)) -#define bFM4_MFS12_I2C_IBCR_INT *((volatile unsigned int*)(0x42718020UL)) -#define bFM4_MFS12_I2C_IBCR_BER *((volatile unsigned int*)(0x42718024UL)) -#define bFM4_MFS12_I2C_IBCR_INTE *((volatile unsigned int*)(0x42718028UL)) -#define bFM4_MFS12_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271802CUL)) -#define bFM4_MFS12_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42718030UL)) -#define bFM4_MFS12_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42718034UL)) -#define bFM4_MFS12_I2C_IBCR_ACT *((volatile unsigned int*)(0x42718038UL)) -#define bFM4_MFS12_I2C_IBCR_SCC *((volatile unsigned int*)(0x42718038UL)) -#define bFM4_MFS12_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271803CUL)) -#define bFM4_MFS12_I2C_IBSR_BB *((volatile unsigned int*)(0x42718080UL)) -#define bFM4_MFS12_I2C_IBSR_SPC *((volatile unsigned int*)(0x42718084UL)) -#define bFM4_MFS12_I2C_IBSR_RSC *((volatile unsigned int*)(0x42718088UL)) -#define bFM4_MFS12_I2C_IBSR_AL *((volatile unsigned int*)(0x4271808CUL)) -#define bFM4_MFS12_I2C_IBSR_TRX *((volatile unsigned int*)(0x42718090UL)) -#define bFM4_MFS12_I2C_IBSR_RSA *((volatile unsigned int*)(0x42718094UL)) -#define bFM4_MFS12_I2C_IBSR_RACK *((volatile unsigned int*)(0x42718098UL)) -#define bFM4_MFS12_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271809CUL)) -#define bFM4_MFS12_I2C_SSR_TBI *((volatile unsigned int*)(0x427180A0UL)) -#define bFM4_MFS12_I2C_SSR_TDRE *((volatile unsigned int*)(0x427180A4UL)) -#define bFM4_MFS12_I2C_SSR_RDRF *((volatile unsigned int*)(0x427180A8UL)) -#define bFM4_MFS12_I2C_SSR_ORE *((volatile unsigned int*)(0x427180ACUL)) -#define bFM4_MFS12_I2C_SSR_TBIE *((volatile unsigned int*)(0x427180B0UL)) -#define bFM4_MFS12_I2C_SSR_DMA *((volatile unsigned int*)(0x427180B4UL)) -#define bFM4_MFS12_I2C_SSR_TSET *((volatile unsigned int*)(0x427180B8UL)) -#define bFM4_MFS12_I2C_SSR_REC *((volatile unsigned int*)(0x427180BCUL)) -#define bFM4_MFS12_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42718200UL)) -#define bFM4_MFS12_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42718204UL)) -#define bFM4_MFS12_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42718208UL)) -#define bFM4_MFS12_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271820CUL)) -#define bFM4_MFS12_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42718210UL)) -#define bFM4_MFS12_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42718214UL)) -#define bFM4_MFS12_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42718218UL)) -#define bFM4_MFS12_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271821CUL)) -#define bFM4_MFS12_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42718220UL)) -#define bFM4_MFS12_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42718224UL)) -#define bFM4_MFS12_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42718228UL)) -#define bFM4_MFS12_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271822CUL)) -#define bFM4_MFS12_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42718230UL)) -#define bFM4_MFS12_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42718234UL)) -#define bFM4_MFS12_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42718238UL)) -#define bFM4_MFS12_I2C_ISMK_EN *((volatile unsigned int*)(0x4271823CUL)) -#define bFM4_MFS12_I2C_FCR_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_I2C_FCR_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_I2C_FCR_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_I2C_FCR_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_I2C_FCR_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_I2C_FCR_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_I2C_FCR_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_I2C_FCR_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42718280UL)) -#define bFM4_MFS12_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42718284UL)) -#define bFM4_MFS12_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42718288UL)) -#define bFM4_MFS12_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271828CUL)) -#define bFM4_MFS12_I2C_FCR0_FSET *((volatile unsigned int*)(0x42718290UL)) -#define bFM4_MFS12_I2C_FCR0_FLD *((volatile unsigned int*)(0x42718294UL)) -#define bFM4_MFS12_I2C_FCR0_FLST *((volatile unsigned int*)(0x42718298UL)) -#define bFM4_MFS12_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427182A0UL)) -#define bFM4_MFS12_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427182A4UL)) -#define bFM4_MFS12_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427182A8UL)) -#define bFM4_MFS12_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x427182ACUL)) -#define bFM4_MFS12_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427182B0UL)) -#define bFM4_MFS12_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271833CUL)) -#define bFM4_MFS12_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42718300UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42718304UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42718308UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271830CUL)) -#define bFM4_MFS12_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42718310UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42718314UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42718318UL)) -#define bFM4_MFS12_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271831CUL)) -#define bFM4_MFS12_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42718320UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42718324UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42718328UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271832CUL)) -#define bFM4_MFS12_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42718330UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42718334UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42718338UL)) -#define bFM4_MFS12_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271833CUL)) - -/* MFS UART channel 13 registers */ -#define bFM4_MFS13_UART_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) -#define bFM4_MFS13_UART_SMR_BDS *((volatile unsigned int*)(0x4271A008UL)) -#define bFM4_MFS13_UART_SMR_SBL *((volatile unsigned int*)(0x4271A00CUL)) -#define bFM4_MFS13_UART_SMR_WUCR *((volatile unsigned int*)(0x4271A010UL)) -#define bFM4_MFS13_UART_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) -#define bFM4_MFS13_UART_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) -#define bFM4_MFS13_UART_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) -#define bFM4_MFS13_UART_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) -#define bFM4_MFS13_UART_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) -#define bFM4_MFS13_UART_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) -#define bFM4_MFS13_UART_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) -#define bFM4_MFS13_UART_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) -#define bFM4_MFS13_UART_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) -#define bFM4_MFS13_UART_ESCR_L0 *((volatile unsigned int*)(0x4271A080UL)) -#define bFM4_MFS13_UART_ESCR_L1 *((volatile unsigned int*)(0x4271A084UL)) -#define bFM4_MFS13_UART_ESCR_L2 *((volatile unsigned int*)(0x4271A088UL)) -#define bFM4_MFS13_UART_ESCR_P *((volatile unsigned int*)(0x4271A08CUL)) -#define bFM4_MFS13_UART_ESCR_PEN *((volatile unsigned int*)(0x4271A090UL)) -#define bFM4_MFS13_UART_ESCR_INV *((volatile unsigned int*)(0x4271A094UL)) -#define bFM4_MFS13_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271A098UL)) -#define bFM4_MFS13_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271A09CUL)) -#define bFM4_MFS13_UART_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) -#define bFM4_MFS13_UART_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) -#define bFM4_MFS13_UART_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) -#define bFM4_MFS13_UART_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) -#define bFM4_MFS13_UART_SSR_FRE *((volatile unsigned int*)(0x4271A0B0UL)) -#define bFM4_MFS13_UART_SSR_PE *((volatile unsigned int*)(0x4271A0B4UL)) -#define bFM4_MFS13_UART_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) -#define bFM4_MFS13_UART_RDR_AD *((volatile unsigned int*)(0x4271A120UL)) -#define bFM4_MFS13_UART_TDR_AD *((volatile unsigned int*)(0x4271A120UL)) -#define bFM4_MFS13_UART_BGR_EXT *((volatile unsigned int*)(0x4271A1BCUL)) -#define bFM4_MFS13_UART_BGR1_EXT *((volatile unsigned int*)(0x4271A1BCUL)) -#define bFM4_MFS13_UART_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_UART_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_UART_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_UART_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_UART_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_UART_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_UART_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_UART_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_UART_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_UART_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) -#define bFM4_MFS13_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) - -/* MFS CSIO channel 13 registers */ -#define bFM4_MFS13_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) -#define bFM4_MFS13_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271A004UL)) -#define bFM4_MFS13_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271A008UL)) -#define bFM4_MFS13_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271A00CUL)) -#define bFM4_MFS13_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) -#define bFM4_MFS13_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) -#define bFM4_MFS13_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) -#define bFM4_MFS13_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) -#define bFM4_MFS13_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) -#define bFM4_MFS13_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) -#define bFM4_MFS13_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) -#define bFM4_MFS13_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) -#define bFM4_MFS13_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271A034UL)) -#define bFM4_MFS13_CSIO_SCR_MS *((volatile unsigned int*)(0x4271A038UL)) -#define bFM4_MFS13_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) -#define bFM4_MFS13_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271A080UL)) -#define bFM4_MFS13_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271A084UL)) -#define bFM4_MFS13_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271A088UL)) -#define bFM4_MFS13_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271A08CUL)) -#define bFM4_MFS13_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271A090UL)) -#define bFM4_MFS13_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271A098UL)) -#define bFM4_MFS13_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271A09CUL)) -#define bFM4_MFS13_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) -#define bFM4_MFS13_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) -#define bFM4_MFS13_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) -#define bFM4_MFS13_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) -#define bFM4_MFS13_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271A0B0UL)) -#define bFM4_MFS13_CSIO_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) -#define bFM4_MFS13_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271A380UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271A384UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271A388UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271A38CUL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271A390UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271A394UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271A398UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271A39CUL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271A3A0UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271A3A4UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271A3A8UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271A3ACUL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271A3B0UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271A3B4UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271A3B8UL)) -#define bFM4_MFS13_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271A3BCUL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271A400UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271A404UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271A408UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271A40CUL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271A410UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271A414UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271A418UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271A41CUL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271A420UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271A424UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271A428UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271A42CUL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271A430UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271A434UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271A438UL)) -#define bFM4_MFS13_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271A43CUL)) -#define bFM4_MFS13_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271A480UL)) -#define bFM4_MFS13_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271A484UL)) -#define bFM4_MFS13_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271A488UL)) -#define bFM4_MFS13_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271A48CUL)) -#define bFM4_MFS13_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271A490UL)) -#define bFM4_MFS13_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271A498UL)) -#define bFM4_MFS13_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271A49CUL)) -#define bFM4_MFS13_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271A4A0UL)) -#define bFM4_MFS13_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271A4ACUL)) -#define bFM4_MFS13_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271A4B0UL)) -#define bFM4_MFS13_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271A4B4UL)) -#define bFM4_MFS13_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271A500UL)) -#define bFM4_MFS13_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271A504UL)) -#define bFM4_MFS13_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271A508UL)) -#define bFM4_MFS13_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271A50CUL)) -#define bFM4_MFS13_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271A510UL)) -#define bFM4_MFS13_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271A514UL)) -#define bFM4_MFS13_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271A518UL)) -#define bFM4_MFS13_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271A51CUL)) -#define bFM4_MFS13_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271A520UL)) -#define bFM4_MFS13_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271A524UL)) -#define bFM4_MFS13_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271A528UL)) -#define bFM4_MFS13_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271A52CUL)) -#define bFM4_MFS13_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271A530UL)) -#define bFM4_MFS13_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271A534UL)) -#define bFM4_MFS13_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271A538UL)) -#define bFM4_MFS13_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271A53CUL)) -#define bFM4_MFS13_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271A580UL)) -#define bFM4_MFS13_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271A584UL)) -#define bFM4_MFS13_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271A588UL)) -#define bFM4_MFS13_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271A58CUL)) -#define bFM4_MFS13_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271A590UL)) -#define bFM4_MFS13_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271A594UL)) -#define bFM4_MFS13_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271A598UL)) -#define bFM4_MFS13_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271A59CUL)) -#define bFM4_MFS13_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271A5A0UL)) -#define bFM4_MFS13_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271A5A4UL)) -#define bFM4_MFS13_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271A5A8UL)) -#define bFM4_MFS13_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271A5ACUL)) -#define bFM4_MFS13_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271A5B0UL)) -#define bFM4_MFS13_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271A5B4UL)) -#define bFM4_MFS13_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271A5B8UL)) -#define bFM4_MFS13_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271A5BCUL)) -#define bFM4_MFS13_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271A600UL)) -#define bFM4_MFS13_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271A604UL)) -#define bFM4_MFS13_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271A614UL)) -#define bFM4_MFS13_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271A618UL)) -#define bFM4_MFS13_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271A61CUL)) -#define bFM4_MFS13_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271A620UL)) -#define bFM4_MFS13_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271A624UL)) - -/* MFS LIN channel 13 registers */ -#define bFM4_MFS13_LIN_SMR_SOE *((volatile unsigned int*)(0x4271A000UL)) -#define bFM4_MFS13_LIN_SMR_SBL *((volatile unsigned int*)(0x4271A00CUL)) -#define bFM4_MFS13_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271A010UL)) -#define bFM4_MFS13_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) -#define bFM4_MFS13_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) -#define bFM4_MFS13_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) -#define bFM4_MFS13_LIN_SCR_TXE *((volatile unsigned int*)(0x4271A020UL)) -#define bFM4_MFS13_LIN_SCR_RXE *((volatile unsigned int*)(0x4271A024UL)) -#define bFM4_MFS13_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271A028UL)) -#define bFM4_MFS13_LIN_SCR_TIE *((volatile unsigned int*)(0x4271A02CUL)) -#define bFM4_MFS13_LIN_SCR_RIE *((volatile unsigned int*)(0x4271A030UL)) -#define bFM4_MFS13_LIN_SCR_LBR *((volatile unsigned int*)(0x4271A034UL)) -#define bFM4_MFS13_LIN_SCR_MS *((volatile unsigned int*)(0x4271A038UL)) -#define bFM4_MFS13_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271A03CUL)) -#define bFM4_MFS13_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271A080UL)) -#define bFM4_MFS13_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271A084UL)) -#define bFM4_MFS13_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271A088UL)) -#define bFM4_MFS13_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271A08CUL)) -#define bFM4_MFS13_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271A090UL)) -#define bFM4_MFS13_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271A098UL)) -#define bFM4_MFS13_LIN_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) -#define bFM4_MFS13_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) -#define bFM4_MFS13_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) -#define bFM4_MFS13_LIN_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) -#define bFM4_MFS13_LIN_SSR_FRE *((volatile unsigned int*)(0x4271A0B0UL)) -#define bFM4_MFS13_LIN_SSR_LBD *((volatile unsigned int*)(0x4271A0B4UL)) -#define bFM4_MFS13_LIN_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) -#define bFM4_MFS13_LIN_BGR_EXT *((volatile unsigned int*)(0x4271A1BCUL)) -#define bFM4_MFS13_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271A1BCUL)) -#define bFM4_MFS13_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_LIN_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_LIN_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_LIN_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) -#define bFM4_MFS13_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) - -/* MFS I2C channel 13 registers */ -#define bFM4_MFS13_I2C_SMR_TIE *((volatile unsigned int*)(0x4271A008UL)) -#define bFM4_MFS13_I2C_SMR_RIE *((volatile unsigned int*)(0x4271A00CUL)) -#define bFM4_MFS13_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271A014UL)) -#define bFM4_MFS13_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271A018UL)) -#define bFM4_MFS13_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271A01CUL)) -#define bFM4_MFS13_I2C_IBCR_INT *((volatile unsigned int*)(0x4271A020UL)) -#define bFM4_MFS13_I2C_IBCR_BER *((volatile unsigned int*)(0x4271A024UL)) -#define bFM4_MFS13_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271A028UL)) -#define bFM4_MFS13_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271A02CUL)) -#define bFM4_MFS13_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271A030UL)) -#define bFM4_MFS13_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271A034UL)) -#define bFM4_MFS13_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271A038UL)) -#define bFM4_MFS13_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271A038UL)) -#define bFM4_MFS13_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271A03CUL)) -#define bFM4_MFS13_I2C_IBSR_BB *((volatile unsigned int*)(0x4271A080UL)) -#define bFM4_MFS13_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271A084UL)) -#define bFM4_MFS13_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271A088UL)) -#define bFM4_MFS13_I2C_IBSR_AL *((volatile unsigned int*)(0x4271A08CUL)) -#define bFM4_MFS13_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271A090UL)) -#define bFM4_MFS13_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271A094UL)) -#define bFM4_MFS13_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271A098UL)) -#define bFM4_MFS13_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271A09CUL)) -#define bFM4_MFS13_I2C_SSR_TBI *((volatile unsigned int*)(0x4271A0A0UL)) -#define bFM4_MFS13_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271A0A4UL)) -#define bFM4_MFS13_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271A0A8UL)) -#define bFM4_MFS13_I2C_SSR_ORE *((volatile unsigned int*)(0x4271A0ACUL)) -#define bFM4_MFS13_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271A0B0UL)) -#define bFM4_MFS13_I2C_SSR_DMA *((volatile unsigned int*)(0x4271A0B4UL)) -#define bFM4_MFS13_I2C_SSR_TSET *((volatile unsigned int*)(0x4271A0B8UL)) -#define bFM4_MFS13_I2C_SSR_REC *((volatile unsigned int*)(0x4271A0BCUL)) -#define bFM4_MFS13_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271A200UL)) -#define bFM4_MFS13_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271A204UL)) -#define bFM4_MFS13_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271A208UL)) -#define bFM4_MFS13_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271A20CUL)) -#define bFM4_MFS13_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271A210UL)) -#define bFM4_MFS13_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271A214UL)) -#define bFM4_MFS13_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271A218UL)) -#define bFM4_MFS13_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271A21CUL)) -#define bFM4_MFS13_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271A220UL)) -#define bFM4_MFS13_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271A224UL)) -#define bFM4_MFS13_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271A228UL)) -#define bFM4_MFS13_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271A22CUL)) -#define bFM4_MFS13_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271A230UL)) -#define bFM4_MFS13_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271A234UL)) -#define bFM4_MFS13_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271A238UL)) -#define bFM4_MFS13_I2C_ISMK_EN *((volatile unsigned int*)(0x4271A23CUL)) -#define bFM4_MFS13_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_I2C_FCR_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_I2C_FCR_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_I2C_FCR_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271A280UL)) -#define bFM4_MFS13_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271A284UL)) -#define bFM4_MFS13_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271A288UL)) -#define bFM4_MFS13_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271A28CUL)) -#define bFM4_MFS13_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271A290UL)) -#define bFM4_MFS13_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271A294UL)) -#define bFM4_MFS13_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271A298UL)) -#define bFM4_MFS13_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271A2A0UL)) -#define bFM4_MFS13_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271A2A4UL)) -#define bFM4_MFS13_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271A2A8UL)) -#define bFM4_MFS13_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271A2ACUL)) -#define bFM4_MFS13_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271A2B0UL)) -#define bFM4_MFS13_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271A33CUL)) -#define bFM4_MFS13_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271A300UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271A304UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271A308UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271A30CUL)) -#define bFM4_MFS13_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271A310UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271A314UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271A318UL)) -#define bFM4_MFS13_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271A31CUL)) -#define bFM4_MFS13_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271A320UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271A324UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271A328UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271A32CUL)) -#define bFM4_MFS13_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271A330UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271A334UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271A338UL)) -#define bFM4_MFS13_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271A33CUL)) - -/* MFS UART channel 14 registers */ -#define bFM4_MFS14_UART_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) -#define bFM4_MFS14_UART_SMR_BDS *((volatile unsigned int*)(0x4271C008UL)) -#define bFM4_MFS14_UART_SMR_SBL *((volatile unsigned int*)(0x4271C00CUL)) -#define bFM4_MFS14_UART_SMR_WUCR *((volatile unsigned int*)(0x4271C010UL)) -#define bFM4_MFS14_UART_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) -#define bFM4_MFS14_UART_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) -#define bFM4_MFS14_UART_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) -#define bFM4_MFS14_UART_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) -#define bFM4_MFS14_UART_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) -#define bFM4_MFS14_UART_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) -#define bFM4_MFS14_UART_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) -#define bFM4_MFS14_UART_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) -#define bFM4_MFS14_UART_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) -#define bFM4_MFS14_UART_ESCR_L0 *((volatile unsigned int*)(0x4271C080UL)) -#define bFM4_MFS14_UART_ESCR_L1 *((volatile unsigned int*)(0x4271C084UL)) -#define bFM4_MFS14_UART_ESCR_L2 *((volatile unsigned int*)(0x4271C088UL)) -#define bFM4_MFS14_UART_ESCR_P *((volatile unsigned int*)(0x4271C08CUL)) -#define bFM4_MFS14_UART_ESCR_PEN *((volatile unsigned int*)(0x4271C090UL)) -#define bFM4_MFS14_UART_ESCR_INV *((volatile unsigned int*)(0x4271C094UL)) -#define bFM4_MFS14_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271C098UL)) -#define bFM4_MFS14_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271C09CUL)) -#define bFM4_MFS14_UART_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) -#define bFM4_MFS14_UART_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) -#define bFM4_MFS14_UART_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) -#define bFM4_MFS14_UART_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) -#define bFM4_MFS14_UART_SSR_FRE *((volatile unsigned int*)(0x4271C0B0UL)) -#define bFM4_MFS14_UART_SSR_PE *((volatile unsigned int*)(0x4271C0B4UL)) -#define bFM4_MFS14_UART_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) -#define bFM4_MFS14_UART_RDR_AD *((volatile unsigned int*)(0x4271C120UL)) -#define bFM4_MFS14_UART_TDR_AD *((volatile unsigned int*)(0x4271C120UL)) -#define bFM4_MFS14_UART_BGR_EXT *((volatile unsigned int*)(0x4271C1BCUL)) -#define bFM4_MFS14_UART_BGR1_EXT *((volatile unsigned int*)(0x4271C1BCUL)) -#define bFM4_MFS14_UART_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_UART_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_UART_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_UART_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_UART_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_UART_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_UART_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_UART_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_UART_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_UART_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) -#define bFM4_MFS14_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) - -/* MFS CSIO channel 14 registers */ -#define bFM4_MFS14_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) -#define bFM4_MFS14_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271C004UL)) -#define bFM4_MFS14_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271C008UL)) -#define bFM4_MFS14_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271C00CUL)) -#define bFM4_MFS14_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) -#define bFM4_MFS14_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) -#define bFM4_MFS14_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) -#define bFM4_MFS14_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) -#define bFM4_MFS14_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) -#define bFM4_MFS14_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) -#define bFM4_MFS14_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) -#define bFM4_MFS14_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) -#define bFM4_MFS14_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271C034UL)) -#define bFM4_MFS14_CSIO_SCR_MS *((volatile unsigned int*)(0x4271C038UL)) -#define bFM4_MFS14_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) -#define bFM4_MFS14_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271C080UL)) -#define bFM4_MFS14_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271C084UL)) -#define bFM4_MFS14_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271C088UL)) -#define bFM4_MFS14_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271C08CUL)) -#define bFM4_MFS14_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271C090UL)) -#define bFM4_MFS14_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271C098UL)) -#define bFM4_MFS14_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271C09CUL)) -#define bFM4_MFS14_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) -#define bFM4_MFS14_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) -#define bFM4_MFS14_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) -#define bFM4_MFS14_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) -#define bFM4_MFS14_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271C0B0UL)) -#define bFM4_MFS14_CSIO_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) -#define bFM4_MFS14_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271C380UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271C384UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271C388UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271C38CUL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271C390UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271C394UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271C398UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271C39CUL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271C3A0UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271C3A4UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271C3A8UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271C3ACUL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271C3B0UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271C3B4UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271C3B8UL)) -#define bFM4_MFS14_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271C3BCUL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271C400UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271C404UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271C408UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271C40CUL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271C410UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271C414UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271C418UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271C41CUL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271C420UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271C424UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271C428UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271C42CUL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271C430UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271C434UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271C438UL)) -#define bFM4_MFS14_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271C43CUL)) -#define bFM4_MFS14_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271C480UL)) -#define bFM4_MFS14_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271C484UL)) -#define bFM4_MFS14_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271C488UL)) -#define bFM4_MFS14_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271C48CUL)) -#define bFM4_MFS14_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271C490UL)) -#define bFM4_MFS14_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271C498UL)) -#define bFM4_MFS14_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271C49CUL)) -#define bFM4_MFS14_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271C4A0UL)) -#define bFM4_MFS14_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271C4ACUL)) -#define bFM4_MFS14_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271C4B0UL)) -#define bFM4_MFS14_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271C4B4UL)) -#define bFM4_MFS14_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271C500UL)) -#define bFM4_MFS14_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271C504UL)) -#define bFM4_MFS14_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271C508UL)) -#define bFM4_MFS14_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271C50CUL)) -#define bFM4_MFS14_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271C510UL)) -#define bFM4_MFS14_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271C514UL)) -#define bFM4_MFS14_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271C518UL)) -#define bFM4_MFS14_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271C51CUL)) -#define bFM4_MFS14_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271C520UL)) -#define bFM4_MFS14_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271C524UL)) -#define bFM4_MFS14_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271C528UL)) -#define bFM4_MFS14_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271C52CUL)) -#define bFM4_MFS14_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271C530UL)) -#define bFM4_MFS14_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271C534UL)) -#define bFM4_MFS14_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271C538UL)) -#define bFM4_MFS14_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271C53CUL)) -#define bFM4_MFS14_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271C580UL)) -#define bFM4_MFS14_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271C584UL)) -#define bFM4_MFS14_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271C588UL)) -#define bFM4_MFS14_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271C58CUL)) -#define bFM4_MFS14_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271C590UL)) -#define bFM4_MFS14_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271C594UL)) -#define bFM4_MFS14_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271C598UL)) -#define bFM4_MFS14_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271C59CUL)) -#define bFM4_MFS14_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271C5A0UL)) -#define bFM4_MFS14_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271C5A4UL)) -#define bFM4_MFS14_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271C5A8UL)) -#define bFM4_MFS14_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271C5ACUL)) -#define bFM4_MFS14_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271C5B0UL)) -#define bFM4_MFS14_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271C5B4UL)) -#define bFM4_MFS14_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271C5B8UL)) -#define bFM4_MFS14_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271C5BCUL)) -#define bFM4_MFS14_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271C600UL)) -#define bFM4_MFS14_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271C604UL)) -#define bFM4_MFS14_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271C614UL)) -#define bFM4_MFS14_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271C618UL)) -#define bFM4_MFS14_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271C61CUL)) -#define bFM4_MFS14_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271C620UL)) -#define bFM4_MFS14_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271C624UL)) - -/* MFS LIN channel 14 registers */ -#define bFM4_MFS14_LIN_SMR_SOE *((volatile unsigned int*)(0x4271C000UL)) -#define bFM4_MFS14_LIN_SMR_SBL *((volatile unsigned int*)(0x4271C00CUL)) -#define bFM4_MFS14_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271C010UL)) -#define bFM4_MFS14_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) -#define bFM4_MFS14_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) -#define bFM4_MFS14_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) -#define bFM4_MFS14_LIN_SCR_TXE *((volatile unsigned int*)(0x4271C020UL)) -#define bFM4_MFS14_LIN_SCR_RXE *((volatile unsigned int*)(0x4271C024UL)) -#define bFM4_MFS14_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271C028UL)) -#define bFM4_MFS14_LIN_SCR_TIE *((volatile unsigned int*)(0x4271C02CUL)) -#define bFM4_MFS14_LIN_SCR_RIE *((volatile unsigned int*)(0x4271C030UL)) -#define bFM4_MFS14_LIN_SCR_LBR *((volatile unsigned int*)(0x4271C034UL)) -#define bFM4_MFS14_LIN_SCR_MS *((volatile unsigned int*)(0x4271C038UL)) -#define bFM4_MFS14_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271C03CUL)) -#define bFM4_MFS14_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271C080UL)) -#define bFM4_MFS14_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271C084UL)) -#define bFM4_MFS14_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271C088UL)) -#define bFM4_MFS14_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271C08CUL)) -#define bFM4_MFS14_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271C090UL)) -#define bFM4_MFS14_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271C098UL)) -#define bFM4_MFS14_LIN_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) -#define bFM4_MFS14_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) -#define bFM4_MFS14_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) -#define bFM4_MFS14_LIN_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) -#define bFM4_MFS14_LIN_SSR_FRE *((volatile unsigned int*)(0x4271C0B0UL)) -#define bFM4_MFS14_LIN_SSR_LBD *((volatile unsigned int*)(0x4271C0B4UL)) -#define bFM4_MFS14_LIN_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) -#define bFM4_MFS14_LIN_BGR_EXT *((volatile unsigned int*)(0x4271C1BCUL)) -#define bFM4_MFS14_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271C1BCUL)) -#define bFM4_MFS14_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_LIN_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_LIN_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_LIN_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) -#define bFM4_MFS14_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) - -/* MFS I2C channel 14 registers */ -#define bFM4_MFS14_I2C_SMR_TIE *((volatile unsigned int*)(0x4271C008UL)) -#define bFM4_MFS14_I2C_SMR_RIE *((volatile unsigned int*)(0x4271C00CUL)) -#define bFM4_MFS14_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271C014UL)) -#define bFM4_MFS14_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271C018UL)) -#define bFM4_MFS14_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271C01CUL)) -#define bFM4_MFS14_I2C_IBCR_INT *((volatile unsigned int*)(0x4271C020UL)) -#define bFM4_MFS14_I2C_IBCR_BER *((volatile unsigned int*)(0x4271C024UL)) -#define bFM4_MFS14_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271C028UL)) -#define bFM4_MFS14_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271C02CUL)) -#define bFM4_MFS14_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271C030UL)) -#define bFM4_MFS14_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271C034UL)) -#define bFM4_MFS14_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271C038UL)) -#define bFM4_MFS14_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271C038UL)) -#define bFM4_MFS14_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271C03CUL)) -#define bFM4_MFS14_I2C_IBSR_BB *((volatile unsigned int*)(0x4271C080UL)) -#define bFM4_MFS14_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271C084UL)) -#define bFM4_MFS14_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271C088UL)) -#define bFM4_MFS14_I2C_IBSR_AL *((volatile unsigned int*)(0x4271C08CUL)) -#define bFM4_MFS14_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271C090UL)) -#define bFM4_MFS14_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271C094UL)) -#define bFM4_MFS14_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271C098UL)) -#define bFM4_MFS14_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271C09CUL)) -#define bFM4_MFS14_I2C_SSR_TBI *((volatile unsigned int*)(0x4271C0A0UL)) -#define bFM4_MFS14_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271C0A4UL)) -#define bFM4_MFS14_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271C0A8UL)) -#define bFM4_MFS14_I2C_SSR_ORE *((volatile unsigned int*)(0x4271C0ACUL)) -#define bFM4_MFS14_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271C0B0UL)) -#define bFM4_MFS14_I2C_SSR_DMA *((volatile unsigned int*)(0x4271C0B4UL)) -#define bFM4_MFS14_I2C_SSR_TSET *((volatile unsigned int*)(0x4271C0B8UL)) -#define bFM4_MFS14_I2C_SSR_REC *((volatile unsigned int*)(0x4271C0BCUL)) -#define bFM4_MFS14_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271C200UL)) -#define bFM4_MFS14_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271C204UL)) -#define bFM4_MFS14_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271C208UL)) -#define bFM4_MFS14_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271C20CUL)) -#define bFM4_MFS14_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271C210UL)) -#define bFM4_MFS14_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271C214UL)) -#define bFM4_MFS14_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271C218UL)) -#define bFM4_MFS14_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271C21CUL)) -#define bFM4_MFS14_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271C220UL)) -#define bFM4_MFS14_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271C224UL)) -#define bFM4_MFS14_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271C228UL)) -#define bFM4_MFS14_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271C22CUL)) -#define bFM4_MFS14_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271C230UL)) -#define bFM4_MFS14_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271C234UL)) -#define bFM4_MFS14_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271C238UL)) -#define bFM4_MFS14_I2C_ISMK_EN *((volatile unsigned int*)(0x4271C23CUL)) -#define bFM4_MFS14_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_I2C_FCR_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_I2C_FCR_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_I2C_FCR_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271C280UL)) -#define bFM4_MFS14_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271C284UL)) -#define bFM4_MFS14_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271C288UL)) -#define bFM4_MFS14_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271C28CUL)) -#define bFM4_MFS14_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271C290UL)) -#define bFM4_MFS14_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271C294UL)) -#define bFM4_MFS14_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271C298UL)) -#define bFM4_MFS14_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271C2A0UL)) -#define bFM4_MFS14_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271C2A4UL)) -#define bFM4_MFS14_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271C2A8UL)) -#define bFM4_MFS14_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271C2ACUL)) -#define bFM4_MFS14_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271C2B0UL)) -#define bFM4_MFS14_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271C33CUL)) -#define bFM4_MFS14_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271C300UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271C304UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271C308UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271C30CUL)) -#define bFM4_MFS14_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271C310UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271C314UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271C318UL)) -#define bFM4_MFS14_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271C31CUL)) -#define bFM4_MFS14_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271C320UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271C324UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271C328UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271C32CUL)) -#define bFM4_MFS14_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271C330UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271C334UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271C338UL)) -#define bFM4_MFS14_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271C33CUL)) - -/* MFS UART channel 15 registers */ -#define bFM4_MFS15_UART_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) -#define bFM4_MFS15_UART_SMR_BDS *((volatile unsigned int*)(0x4271E008UL)) -#define bFM4_MFS15_UART_SMR_SBL *((volatile unsigned int*)(0x4271E00CUL)) -#define bFM4_MFS15_UART_SMR_WUCR *((volatile unsigned int*)(0x4271E010UL)) -#define bFM4_MFS15_UART_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) -#define bFM4_MFS15_UART_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) -#define bFM4_MFS15_UART_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) -#define bFM4_MFS15_UART_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) -#define bFM4_MFS15_UART_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) -#define bFM4_MFS15_UART_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) -#define bFM4_MFS15_UART_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) -#define bFM4_MFS15_UART_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) -#define bFM4_MFS15_UART_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) -#define bFM4_MFS15_UART_ESCR_L0 *((volatile unsigned int*)(0x4271E080UL)) -#define bFM4_MFS15_UART_ESCR_L1 *((volatile unsigned int*)(0x4271E084UL)) -#define bFM4_MFS15_UART_ESCR_L2 *((volatile unsigned int*)(0x4271E088UL)) -#define bFM4_MFS15_UART_ESCR_P *((volatile unsigned int*)(0x4271E08CUL)) -#define bFM4_MFS15_UART_ESCR_PEN *((volatile unsigned int*)(0x4271E090UL)) -#define bFM4_MFS15_UART_ESCR_INV *((volatile unsigned int*)(0x4271E094UL)) -#define bFM4_MFS15_UART_ESCR_ESBL *((volatile unsigned int*)(0x4271E098UL)) -#define bFM4_MFS15_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4271E09CUL)) -#define bFM4_MFS15_UART_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) -#define bFM4_MFS15_UART_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) -#define bFM4_MFS15_UART_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) -#define bFM4_MFS15_UART_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) -#define bFM4_MFS15_UART_SSR_FRE *((volatile unsigned int*)(0x4271E0B0UL)) -#define bFM4_MFS15_UART_SSR_PE *((volatile unsigned int*)(0x4271E0B4UL)) -#define bFM4_MFS15_UART_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) -#define bFM4_MFS15_UART_RDR_AD *((volatile unsigned int*)(0x4271E120UL)) -#define bFM4_MFS15_UART_TDR_AD *((volatile unsigned int*)(0x4271E120UL)) -#define bFM4_MFS15_UART_BGR_EXT *((volatile unsigned int*)(0x4271E1BCUL)) -#define bFM4_MFS15_UART_BGR1_EXT *((volatile unsigned int*)(0x4271E1BCUL)) -#define bFM4_MFS15_UART_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_UART_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_UART_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_UART_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_UART_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_UART_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_UART_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_UART_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_UART_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_UART_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_UART_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_UART_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_UART_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_UART_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_UART_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_UART_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_UART_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_UART_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_UART_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_UART_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) -#define bFM4_MFS15_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) - -/* MFS CSIO channel 15 registers */ -#define bFM4_MFS15_CSIO_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) -#define bFM4_MFS15_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4271E004UL)) -#define bFM4_MFS15_CSIO_SMR_BDS *((volatile unsigned int*)(0x4271E008UL)) -#define bFM4_MFS15_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4271E00CUL)) -#define bFM4_MFS15_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) -#define bFM4_MFS15_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) -#define bFM4_MFS15_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) -#define bFM4_MFS15_CSIO_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) -#define bFM4_MFS15_CSIO_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) -#define bFM4_MFS15_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) -#define bFM4_MFS15_CSIO_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) -#define bFM4_MFS15_CSIO_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) -#define bFM4_MFS15_CSIO_SCR_SPI *((volatile unsigned int*)(0x4271E034UL)) -#define bFM4_MFS15_CSIO_SCR_MS *((volatile unsigned int*)(0x4271E038UL)) -#define bFM4_MFS15_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) -#define bFM4_MFS15_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4271E080UL)) -#define bFM4_MFS15_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4271E084UL)) -#define bFM4_MFS15_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4271E088UL)) -#define bFM4_MFS15_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4271E08CUL)) -#define bFM4_MFS15_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4271E090UL)) -#define bFM4_MFS15_CSIO_ESCR_L3 *((volatile unsigned int*)(0x4271E098UL)) -#define bFM4_MFS15_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4271E09CUL)) -#define bFM4_MFS15_CSIO_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) -#define bFM4_MFS15_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) -#define bFM4_MFS15_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) -#define bFM4_MFS15_CSIO_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) -#define bFM4_MFS15_CSIO_SSR_AWC *((volatile unsigned int*)(0x4271E0B0UL)) -#define bFM4_MFS15_CSIO_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) -#define bFM4_MFS15_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_CSIO_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_CSIO_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_CSIO_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_CSIO_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_CSIO_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD0 *((volatile unsigned int*)(0x4271E380UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD1 *((volatile unsigned int*)(0x4271E384UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD2 *((volatile unsigned int*)(0x4271E388UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD3 *((volatile unsigned int*)(0x4271E38CUL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD4 *((volatile unsigned int*)(0x4271E390UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD5 *((volatile unsigned int*)(0x4271E394UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD6 *((volatile unsigned int*)(0x4271E398UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSHD7 *((volatile unsigned int*)(0x4271E39CUL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU0 *((volatile unsigned int*)(0x4271E3A0UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU1 *((volatile unsigned int*)(0x4271E3A4UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU2 *((volatile unsigned int*)(0x4271E3A8UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU3 *((volatile unsigned int*)(0x4271E3ACUL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU4 *((volatile unsigned int*)(0x4271E3B0UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU5 *((volatile unsigned int*)(0x4271E3B4UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU6 *((volatile unsigned int*)(0x4271E3B8UL)) -#define bFM4_MFS15_CSIO_SCSTR10_CSSU7 *((volatile unsigned int*)(0x4271E3BCUL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS0 *((volatile unsigned int*)(0x4271E400UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS1 *((volatile unsigned int*)(0x4271E404UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS2 *((volatile unsigned int*)(0x4271E408UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS3 *((volatile unsigned int*)(0x4271E40CUL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS4 *((volatile unsigned int*)(0x4271E410UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS5 *((volatile unsigned int*)(0x4271E414UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS6 *((volatile unsigned int*)(0x4271E418UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS7 *((volatile unsigned int*)(0x4271E41CUL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS8 *((volatile unsigned int*)(0x4271E420UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS9 *((volatile unsigned int*)(0x4271E424UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS10 *((volatile unsigned int*)(0x4271E428UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS11 *((volatile unsigned int*)(0x4271E42CUL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS12 *((volatile unsigned int*)(0x4271E430UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS13 *((volatile unsigned int*)(0x4271E434UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS14 *((volatile unsigned int*)(0x4271E438UL)) -#define bFM4_MFS15_CSIO_SCSTR32_CSDS15 *((volatile unsigned int*)(0x4271E43CUL)) -#define bFM4_MFS15_CSIO_SACSR_TMRE *((volatile unsigned int*)(0x4271E480UL)) -#define bFM4_MFS15_CSIO_SACSR_TDIV0 *((volatile unsigned int*)(0x4271E484UL)) -#define bFM4_MFS15_CSIO_SACSR_TDIV1 *((volatile unsigned int*)(0x4271E488UL)) -#define bFM4_MFS15_CSIO_SACSR_TDIV2 *((volatile unsigned int*)(0x4271E48CUL)) -#define bFM4_MFS15_CSIO_SACSR_TDIV3 *((volatile unsigned int*)(0x4271E490UL)) -#define bFM4_MFS15_CSIO_SACSR_TSYNE *((volatile unsigned int*)(0x4271E498UL)) -#define bFM4_MFS15_CSIO_SACSR_TINTE *((volatile unsigned int*)(0x4271E49CUL)) -#define bFM4_MFS15_CSIO_SACSR_TINT *((volatile unsigned int*)(0x4271E4A0UL)) -#define bFM4_MFS15_CSIO_SACSR_CSE *((volatile unsigned int*)(0x4271E4ACUL)) -#define bFM4_MFS15_CSIO_SACSR_CSEIE *((volatile unsigned int*)(0x4271E4B0UL)) -#define bFM4_MFS15_CSIO_SACSR_TBEEN *((volatile unsigned int*)(0x4271E4B4UL)) -#define bFM4_MFS15_CSIO_STMR_TM0 *((volatile unsigned int*)(0x4271E500UL)) -#define bFM4_MFS15_CSIO_STMR_TM1 *((volatile unsigned int*)(0x4271E504UL)) -#define bFM4_MFS15_CSIO_STMR_TM2 *((volatile unsigned int*)(0x4271E508UL)) -#define bFM4_MFS15_CSIO_STMR_TM3 *((volatile unsigned int*)(0x4271E50CUL)) -#define bFM4_MFS15_CSIO_STMR_TM4 *((volatile unsigned int*)(0x4271E510UL)) -#define bFM4_MFS15_CSIO_STMR_TM5 *((volatile unsigned int*)(0x4271E514UL)) -#define bFM4_MFS15_CSIO_STMR_TM6 *((volatile unsigned int*)(0x4271E518UL)) -#define bFM4_MFS15_CSIO_STMR_TM7 *((volatile unsigned int*)(0x4271E51CUL)) -#define bFM4_MFS15_CSIO_STMR_TM8 *((volatile unsigned int*)(0x4271E520UL)) -#define bFM4_MFS15_CSIO_STMR_TM9 *((volatile unsigned int*)(0x4271E524UL)) -#define bFM4_MFS15_CSIO_STMR_TM10 *((volatile unsigned int*)(0x4271E528UL)) -#define bFM4_MFS15_CSIO_STMR_TM11 *((volatile unsigned int*)(0x4271E52CUL)) -#define bFM4_MFS15_CSIO_STMR_TM12 *((volatile unsigned int*)(0x4271E530UL)) -#define bFM4_MFS15_CSIO_STMR_TM13 *((volatile unsigned int*)(0x4271E534UL)) -#define bFM4_MFS15_CSIO_STMR_TM14 *((volatile unsigned int*)(0x4271E538UL)) -#define bFM4_MFS15_CSIO_STMR_TM15 *((volatile unsigned int*)(0x4271E53CUL)) -#define bFM4_MFS15_CSIO_STMCR_TC0 *((volatile unsigned int*)(0x4271E580UL)) -#define bFM4_MFS15_CSIO_STMCR_TC1 *((volatile unsigned int*)(0x4271E584UL)) -#define bFM4_MFS15_CSIO_STMCR_TC2 *((volatile unsigned int*)(0x4271E588UL)) -#define bFM4_MFS15_CSIO_STMCR_TC3 *((volatile unsigned int*)(0x4271E58CUL)) -#define bFM4_MFS15_CSIO_STMCR_TC4 *((volatile unsigned int*)(0x4271E590UL)) -#define bFM4_MFS15_CSIO_STMCR_TC5 *((volatile unsigned int*)(0x4271E594UL)) -#define bFM4_MFS15_CSIO_STMCR_TC6 *((volatile unsigned int*)(0x4271E598UL)) -#define bFM4_MFS15_CSIO_STMCR_TC7 *((volatile unsigned int*)(0x4271E59CUL)) -#define bFM4_MFS15_CSIO_STMCR_TC8 *((volatile unsigned int*)(0x4271E5A0UL)) -#define bFM4_MFS15_CSIO_STMCR_TC9 *((volatile unsigned int*)(0x4271E5A4UL)) -#define bFM4_MFS15_CSIO_STMCR_TC10 *((volatile unsigned int*)(0x4271E5A8UL)) -#define bFM4_MFS15_CSIO_STMCR_TC11 *((volatile unsigned int*)(0x4271E5ACUL)) -#define bFM4_MFS15_CSIO_STMCR_TC12 *((volatile unsigned int*)(0x4271E5B0UL)) -#define bFM4_MFS15_CSIO_STMCR_TC13 *((volatile unsigned int*)(0x4271E5B4UL)) -#define bFM4_MFS15_CSIO_STMCR_TC14 *((volatile unsigned int*)(0x4271E5B8UL)) -#define bFM4_MFS15_CSIO_STMCR_TC15 *((volatile unsigned int*)(0x4271E5BCUL)) -#define bFM4_MFS15_CSIO_SCSCR_CSOE *((volatile unsigned int*)(0x4271E600UL)) -#define bFM4_MFS15_CSIO_SCSCR_CSEN0 *((volatile unsigned int*)(0x4271E604UL)) -#define bFM4_MFS15_CSIO_SCSCR_CSLVL *((volatile unsigned int*)(0x4271E614UL)) -#define bFM4_MFS15_CSIO_SCSCR_CDIV0 *((volatile unsigned int*)(0x4271E618UL)) -#define bFM4_MFS15_CSIO_SCSCR_CDIV1 *((volatile unsigned int*)(0x4271E61CUL)) -#define bFM4_MFS15_CSIO_SCSCR_CDIV2 *((volatile unsigned int*)(0x4271E620UL)) -#define bFM4_MFS15_CSIO_SCSCR_SCAM *((volatile unsigned int*)(0x4271E624UL)) - -/* MFS LIN channel 15 registers */ -#define bFM4_MFS15_LIN_SMR_SOE *((volatile unsigned int*)(0x4271E000UL)) -#define bFM4_MFS15_LIN_SMR_SBL *((volatile unsigned int*)(0x4271E00CUL)) -#define bFM4_MFS15_LIN_SMR_WUCR *((volatile unsigned int*)(0x4271E010UL)) -#define bFM4_MFS15_LIN_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) -#define bFM4_MFS15_LIN_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) -#define bFM4_MFS15_LIN_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) -#define bFM4_MFS15_LIN_SCR_TXE *((volatile unsigned int*)(0x4271E020UL)) -#define bFM4_MFS15_LIN_SCR_RXE *((volatile unsigned int*)(0x4271E024UL)) -#define bFM4_MFS15_LIN_SCR_TBIE *((volatile unsigned int*)(0x4271E028UL)) -#define bFM4_MFS15_LIN_SCR_TIE *((volatile unsigned int*)(0x4271E02CUL)) -#define bFM4_MFS15_LIN_SCR_RIE *((volatile unsigned int*)(0x4271E030UL)) -#define bFM4_MFS15_LIN_SCR_LBR *((volatile unsigned int*)(0x4271E034UL)) -#define bFM4_MFS15_LIN_SCR_MS *((volatile unsigned int*)(0x4271E038UL)) -#define bFM4_MFS15_LIN_SCR_UPCL *((volatile unsigned int*)(0x4271E03CUL)) -#define bFM4_MFS15_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4271E080UL)) -#define bFM4_MFS15_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4271E084UL)) -#define bFM4_MFS15_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4271E088UL)) -#define bFM4_MFS15_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4271E08CUL)) -#define bFM4_MFS15_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4271E090UL)) -#define bFM4_MFS15_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4271E098UL)) -#define bFM4_MFS15_LIN_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) -#define bFM4_MFS15_LIN_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) -#define bFM4_MFS15_LIN_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) -#define bFM4_MFS15_LIN_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) -#define bFM4_MFS15_LIN_SSR_FRE *((volatile unsigned int*)(0x4271E0B0UL)) -#define bFM4_MFS15_LIN_SSR_LBD *((volatile unsigned int*)(0x4271E0B4UL)) -#define bFM4_MFS15_LIN_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) -#define bFM4_MFS15_LIN_BGR_EXT *((volatile unsigned int*)(0x4271E1BCUL)) -#define bFM4_MFS15_LIN_BGR1_EXT *((volatile unsigned int*)(0x4271E1BCUL)) -#define bFM4_MFS15_LIN_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_LIN_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_LIN_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_LIN_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_LIN_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_LIN_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_LIN_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_LIN_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_LIN_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_LIN_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_LIN_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_LIN_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) -#define bFM4_MFS15_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) - -/* MFS I2C channel 15 registers */ -#define bFM4_MFS15_I2C_SMR_TIE *((volatile unsigned int*)(0x4271E008UL)) -#define bFM4_MFS15_I2C_SMR_RIE *((volatile unsigned int*)(0x4271E00CUL)) -#define bFM4_MFS15_I2C_SMR_MD0 *((volatile unsigned int*)(0x4271E014UL)) -#define bFM4_MFS15_I2C_SMR_MD1 *((volatile unsigned int*)(0x4271E018UL)) -#define bFM4_MFS15_I2C_SMR_MD2 *((volatile unsigned int*)(0x4271E01CUL)) -#define bFM4_MFS15_I2C_IBCR_INT *((volatile unsigned int*)(0x4271E020UL)) -#define bFM4_MFS15_I2C_IBCR_BER *((volatile unsigned int*)(0x4271E024UL)) -#define bFM4_MFS15_I2C_IBCR_INTE *((volatile unsigned int*)(0x4271E028UL)) -#define bFM4_MFS15_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4271E02CUL)) -#define bFM4_MFS15_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4271E030UL)) -#define bFM4_MFS15_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4271E034UL)) -#define bFM4_MFS15_I2C_IBCR_ACT *((volatile unsigned int*)(0x4271E038UL)) -#define bFM4_MFS15_I2C_IBCR_SCC *((volatile unsigned int*)(0x4271E038UL)) -#define bFM4_MFS15_I2C_IBCR_MSS *((volatile unsigned int*)(0x4271E03CUL)) -#define bFM4_MFS15_I2C_IBSR_BB *((volatile unsigned int*)(0x4271E080UL)) -#define bFM4_MFS15_I2C_IBSR_SPC *((volatile unsigned int*)(0x4271E084UL)) -#define bFM4_MFS15_I2C_IBSR_RSC *((volatile unsigned int*)(0x4271E088UL)) -#define bFM4_MFS15_I2C_IBSR_AL *((volatile unsigned int*)(0x4271E08CUL)) -#define bFM4_MFS15_I2C_IBSR_TRX *((volatile unsigned int*)(0x4271E090UL)) -#define bFM4_MFS15_I2C_IBSR_RSA *((volatile unsigned int*)(0x4271E094UL)) -#define bFM4_MFS15_I2C_IBSR_RACK *((volatile unsigned int*)(0x4271E098UL)) -#define bFM4_MFS15_I2C_IBSR_FBT *((volatile unsigned int*)(0x4271E09CUL)) -#define bFM4_MFS15_I2C_SSR_TBI *((volatile unsigned int*)(0x4271E0A0UL)) -#define bFM4_MFS15_I2C_SSR_TDRE *((volatile unsigned int*)(0x4271E0A4UL)) -#define bFM4_MFS15_I2C_SSR_RDRF *((volatile unsigned int*)(0x4271E0A8UL)) -#define bFM4_MFS15_I2C_SSR_ORE *((volatile unsigned int*)(0x4271E0ACUL)) -#define bFM4_MFS15_I2C_SSR_TBIE *((volatile unsigned int*)(0x4271E0B0UL)) -#define bFM4_MFS15_I2C_SSR_DMA *((volatile unsigned int*)(0x4271E0B4UL)) -#define bFM4_MFS15_I2C_SSR_TSET *((volatile unsigned int*)(0x4271E0B8UL)) -#define bFM4_MFS15_I2C_SSR_REC *((volatile unsigned int*)(0x4271E0BCUL)) -#define bFM4_MFS15_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4271E200UL)) -#define bFM4_MFS15_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4271E204UL)) -#define bFM4_MFS15_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4271E208UL)) -#define bFM4_MFS15_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4271E20CUL)) -#define bFM4_MFS15_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4271E210UL)) -#define bFM4_MFS15_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4271E214UL)) -#define bFM4_MFS15_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4271E218UL)) -#define bFM4_MFS15_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4271E21CUL)) -#define bFM4_MFS15_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4271E220UL)) -#define bFM4_MFS15_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4271E224UL)) -#define bFM4_MFS15_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4271E228UL)) -#define bFM4_MFS15_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4271E22CUL)) -#define bFM4_MFS15_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4271E230UL)) -#define bFM4_MFS15_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4271E234UL)) -#define bFM4_MFS15_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4271E238UL)) -#define bFM4_MFS15_I2C_ISMK_EN *((volatile unsigned int*)(0x4271E23CUL)) -#define bFM4_MFS15_I2C_FCR_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_I2C_FCR_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_I2C_FCR_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_I2C_FCR_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_I2C_FCR_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_I2C_FCR_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_I2C_FCR_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_I2C_FCR_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4271E280UL)) -#define bFM4_MFS15_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4271E284UL)) -#define bFM4_MFS15_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4271E288UL)) -#define bFM4_MFS15_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4271E28CUL)) -#define bFM4_MFS15_I2C_FCR0_FSET *((volatile unsigned int*)(0x4271E290UL)) -#define bFM4_MFS15_I2C_FCR0_FLD *((volatile unsigned int*)(0x4271E294UL)) -#define bFM4_MFS15_I2C_FCR0_FLST *((volatile unsigned int*)(0x4271E298UL)) -#define bFM4_MFS15_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4271E2A0UL)) -#define bFM4_MFS15_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4271E2A4UL)) -#define bFM4_MFS15_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4271E2A8UL)) -#define bFM4_MFS15_I2C_FCR1_FRIIE *((volatile unsigned int*)(0x4271E2ACUL)) -#define bFM4_MFS15_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4271E2B0UL)) -#define bFM4_MFS15_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4271E33CUL)) -#define bFM4_MFS15_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4271E300UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4271E304UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4271E308UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4271E30CUL)) -#define bFM4_MFS15_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4271E310UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4271E314UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4271E318UL)) -#define bFM4_MFS15_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4271E31CUL)) -#define bFM4_MFS15_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4271E320UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4271E324UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4271E328UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4271E32CUL)) -#define bFM4_MFS15_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4271E330UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4271E334UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4271E338UL)) -#define bFM4_MFS15_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4271E33CUL)) - -/* CRC registers */ -#define bFM4_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM4_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM4_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM4_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM4_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM4_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM4_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM4_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM4_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM4_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM4_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM4_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM4_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM4_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM4_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM4_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM4_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM4_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM4_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM4_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM4_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM4_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM4_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM4_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM4_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM4_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM4_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM4_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM4_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* Real time clock registers */ -#define bFM4_RTC_WTCR10_ST *((volatile unsigned int*)(0x42762000UL)) -#define bFM4_RTC_WTCR10_RUN *((volatile unsigned int*)(0x42762008UL)) -#define bFM4_RTC_WTCR10_SRST *((volatile unsigned int*)(0x4276200CUL)) -#define bFM4_RTC_WTCR10_SCST *((volatile unsigned int*)(0x42762010UL)) -#define bFM4_RTC_WTCR10_SCRST *((volatile unsigned int*)(0x42762014UL)) -#define bFM4_RTC_WTCR10_BUSY *((volatile unsigned int*)(0x42762018UL)) -#define bFM4_RTC_WTCR10_TRANS *((volatile unsigned int*)(0x4276201CUL)) -#define bFM4_RTC_WTCR11_MIEN *((volatile unsigned int*)(0x42762080UL)) -#define bFM4_RTC_WTCR11_HEN *((volatile unsigned int*)(0x42762084UL)) -#define bFM4_RTC_WTCR11_DEN *((volatile unsigned int*)(0x42762088UL)) -#define bFM4_RTC_WTCR11_MOEN *((volatile unsigned int*)(0x4276208CUL)) -#define bFM4_RTC_WTCR11_YEN *((volatile unsigned int*)(0x42762090UL)) -#define bFM4_RTC_WTCR12_INTSSI *((volatile unsigned int*)(0x42762100UL)) -#define bFM4_RTC_WTCR12_INTSI *((volatile unsigned int*)(0x42762104UL)) -#define bFM4_RTC_WTCR12_INTMI *((volatile unsigned int*)(0x42762108UL)) -#define bFM4_RTC_WTCR12_INTHI *((volatile unsigned int*)(0x4276210CUL)) -#define bFM4_RTC_WTCR12_INTTMI *((volatile unsigned int*)(0x42762110UL)) -#define bFM4_RTC_WTCR12_INTALI *((volatile unsigned int*)(0x42762114UL)) -#define bFM4_RTC_WTCR12_INTERI *((volatile unsigned int*)(0x42762118UL)) -#define bFM4_RTC_WTCR12_INTCRI *((volatile unsigned int*)(0x4276211CUL)) -#define bFM4_RTC_WTCR13_INTSSIE *((volatile unsigned int*)(0x42762180UL)) -#define bFM4_RTC_WTCR13_INTSIE *((volatile unsigned int*)(0x42762184UL)) -#define bFM4_RTC_WTCR13_INTMIE *((volatile unsigned int*)(0x42762188UL)) -#define bFM4_RTC_WTCR13_INTHIE *((volatile unsigned int*)(0x4276218CUL)) -#define bFM4_RTC_WTCR13_INTTMIE *((volatile unsigned int*)(0x42762190UL)) -#define bFM4_RTC_WTCR13_INTALIE *((volatile unsigned int*)(0x42762194UL)) -#define bFM4_RTC_WTCR13_INTERIE *((volatile unsigned int*)(0x42762198UL)) -#define bFM4_RTC_WTCR13_INTCRIE *((volatile unsigned int*)(0x4276219CUL)) -#define bFM4_RTC_WTCR20_CREAD *((volatile unsigned int*)(0x42762200UL)) -#define bFM4_RTC_WTCR20_CWRITE *((volatile unsigned int*)(0x42762204UL)) -#define bFM4_RTC_WTCR20_BREAD *((volatile unsigned int*)(0x42762208UL)) -#define bFM4_RTC_WTCR20_BWRITE *((volatile unsigned int*)(0x4276220CUL)) -#define bFM4_RTC_WTCR20_PREAD *((volatile unsigned int*)(0x42762210UL)) -#define bFM4_RTC_WTCR20_PWRITE *((volatile unsigned int*)(0x42762214UL)) -#define bFM4_RTC_WTCR21_TMST *((volatile unsigned int*)(0x42762280UL)) -#define bFM4_RTC_WTCR21_TMEN *((volatile unsigned int*)(0x42762284UL)) -#define bFM4_RTC_WTCR21_TMRUN *((volatile unsigned int*)(0x42762288UL)) -#define bFM4_RTC_WTSR_S0 *((volatile unsigned int*)(0x42762380UL)) -#define bFM4_RTC_WTSR_S1 *((volatile unsigned int*)(0x42762384UL)) -#define bFM4_RTC_WTSR_S2 *((volatile unsigned int*)(0x42762388UL)) -#define bFM4_RTC_WTSR_S3 *((volatile unsigned int*)(0x4276238CUL)) -#define bFM4_RTC_WTSR_TS0 *((volatile unsigned int*)(0x42762390UL)) -#define bFM4_RTC_WTSR_TS1 *((volatile unsigned int*)(0x42762394UL)) -#define bFM4_RTC_WTSR_TS2 *((volatile unsigned int*)(0x42762398UL)) -#define bFM4_RTC_WTMIR_MI0 *((volatile unsigned int*)(0x42762400UL)) -#define bFM4_RTC_WTMIR_MI1 *((volatile unsigned int*)(0x42762404UL)) -#define bFM4_RTC_WTMIR_MI2 *((volatile unsigned int*)(0x42762408UL)) -#define bFM4_RTC_WTMIR_MI3 *((volatile unsigned int*)(0x4276240CUL)) -#define bFM4_RTC_WTMIR_TMI0 *((volatile unsigned int*)(0x42762410UL)) -#define bFM4_RTC_WTMIR_TMI1 *((volatile unsigned int*)(0x42762414UL)) -#define bFM4_RTC_WTMIR_TMI2 *((volatile unsigned int*)(0x42762418UL)) -#define bFM4_RTC_WTHR_H0 *((volatile unsigned int*)(0x42762480UL)) -#define bFM4_RTC_WTHR_H1 *((volatile unsigned int*)(0x42762484UL)) -#define bFM4_RTC_WTHR_H2 *((volatile unsigned int*)(0x42762488UL)) -#define bFM4_RTC_WTHR_H3 *((volatile unsigned int*)(0x4276248CUL)) -#define bFM4_RTC_WTHR_TH0 *((volatile unsigned int*)(0x42762490UL)) -#define bFM4_RTC_WTHR_TH1 *((volatile unsigned int*)(0x42762494UL)) -#define bFM4_RTC_WTDR_D0 *((volatile unsigned int*)(0x42762500UL)) -#define bFM4_RTC_WTDR_D1 *((volatile unsigned int*)(0x42762504UL)) -#define bFM4_RTC_WTDR_D2 *((volatile unsigned int*)(0x42762508UL)) -#define bFM4_RTC_WTDR_D3 *((volatile unsigned int*)(0x4276250CUL)) -#define bFM4_RTC_WTDR_TD0 *((volatile unsigned int*)(0x42762510UL)) -#define bFM4_RTC_WTDR_TD1 *((volatile unsigned int*)(0x42762514UL)) -#define bFM4_RTC_WTDW_DW0 *((volatile unsigned int*)(0x42762580UL)) -#define bFM4_RTC_WTDW_DW1 *((volatile unsigned int*)(0x42762584UL)) -#define bFM4_RTC_WTDW_DW2 *((volatile unsigned int*)(0x42762588UL)) -#define bFM4_RTC_WTMOR_MO0 *((volatile unsigned int*)(0x42762600UL)) -#define bFM4_RTC_WTMOR_MO1 *((volatile unsigned int*)(0x42762604UL)) -#define bFM4_RTC_WTMOR_MO2 *((volatile unsigned int*)(0x42762608UL)) -#define bFM4_RTC_WTMOR_MO3 *((volatile unsigned int*)(0x4276260CUL)) -#define bFM4_RTC_WTMOR_TMO *((volatile unsigned int*)(0x42762610UL)) -#define bFM4_RTC_WTYR_Y0 *((volatile unsigned int*)(0x42762680UL)) -#define bFM4_RTC_WTYR_Y1 *((volatile unsigned int*)(0x42762684UL)) -#define bFM4_RTC_WTYR_Y2 *((volatile unsigned int*)(0x42762688UL)) -#define bFM4_RTC_WTYR_Y3 *((volatile unsigned int*)(0x4276268CUL)) -#define bFM4_RTC_WTYR_TY0 *((volatile unsigned int*)(0x42762690UL)) -#define bFM4_RTC_WTYR_TY1 *((volatile unsigned int*)(0x42762694UL)) -#define bFM4_RTC_WTYR_TY2 *((volatile unsigned int*)(0x42762698UL)) -#define bFM4_RTC_WTYR_TY3 *((volatile unsigned int*)(0x4276269CUL)) -#define bFM4_RTC_ALMIR_AMI0 *((volatile unsigned int*)(0x42762700UL)) -#define bFM4_RTC_ALMIR_AMI1 *((volatile unsigned int*)(0x42762704UL)) -#define bFM4_RTC_ALMIR_AMI2 *((volatile unsigned int*)(0x42762708UL)) -#define bFM4_RTC_ALMIR_AMI3 *((volatile unsigned int*)(0x4276270CUL)) -#define bFM4_RTC_ALMIR_TAMI0 *((volatile unsigned int*)(0x42762710UL)) -#define bFM4_RTC_ALMIR_TAMI1 *((volatile unsigned int*)(0x42762714UL)) -#define bFM4_RTC_ALMIR_TAMI2 *((volatile unsigned int*)(0x42762718UL)) -#define bFM4_RTC_ALHR_AH0 *((volatile unsigned int*)(0x42762780UL)) -#define bFM4_RTC_ALHR_AH1 *((volatile unsigned int*)(0x42762784UL)) -#define bFM4_RTC_ALHR_AH2 *((volatile unsigned int*)(0x42762788UL)) -#define bFM4_RTC_ALHR_AH3 *((volatile unsigned int*)(0x4276278CUL)) -#define bFM4_RTC_ALHR_TAH0 *((volatile unsigned int*)(0x42762790UL)) -#define bFM4_RTC_ALHR_TAH1 *((volatile unsigned int*)(0x42762794UL)) -#define bFM4_RTC_ALDR_AD0 *((volatile unsigned int*)(0x42762800UL)) -#define bFM4_RTC_ALDR_AD1 *((volatile unsigned int*)(0x42762804UL)) -#define bFM4_RTC_ALDR_AD2 *((volatile unsigned int*)(0x42762808UL)) -#define bFM4_RTC_ALDR_AD3 *((volatile unsigned int*)(0x4276280CUL)) -#define bFM4_RTC_ALDR_TAD0 *((volatile unsigned int*)(0x42762810UL)) -#define bFM4_RTC_ALDR_TAD1 *((volatile unsigned int*)(0x42762814UL)) -#define bFM4_RTC_ALMOR_AMO0 *((volatile unsigned int*)(0x42762880UL)) -#define bFM4_RTC_ALMOR_AMO1 *((volatile unsigned int*)(0x42762884UL)) -#define bFM4_RTC_ALMOR_AMO2 *((volatile unsigned int*)(0x42762888UL)) -#define bFM4_RTC_ALMOR_AMO3 *((volatile unsigned int*)(0x4276288CUL)) -#define bFM4_RTC_ALMOR_TAMO *((volatile unsigned int*)(0x42762890UL)) -#define bFM4_RTC_ALYR_AY0 *((volatile unsigned int*)(0x42762900UL)) -#define bFM4_RTC_ALYR_AY1 *((volatile unsigned int*)(0x42762904UL)) -#define bFM4_RTC_ALYR_AY2 *((volatile unsigned int*)(0x42762908UL)) -#define bFM4_RTC_ALYR_AY3 *((volatile unsigned int*)(0x4276290CUL)) -#define bFM4_RTC_ALYR_TAY0 *((volatile unsigned int*)(0x42762910UL)) -#define bFM4_RTC_ALYR_TAY1 *((volatile unsigned int*)(0x42762914UL)) -#define bFM4_RTC_ALYR_TAY2 *((volatile unsigned int*)(0x42762918UL)) -#define bFM4_RTC_ALYR_TAY3 *((volatile unsigned int*)(0x4276291CUL)) -#define bFM4_RTC_WTTR0_TM0 *((volatile unsigned int*)(0x42762980UL)) -#define bFM4_RTC_WTTR0_TM1 *((volatile unsigned int*)(0x42762984UL)) -#define bFM4_RTC_WTTR0_TM2 *((volatile unsigned int*)(0x42762988UL)) -#define bFM4_RTC_WTTR0_TM3 *((volatile unsigned int*)(0x4276298CUL)) -#define bFM4_RTC_WTTR0_TM4 *((volatile unsigned int*)(0x42762990UL)) -#define bFM4_RTC_WTTR0_TM5 *((volatile unsigned int*)(0x42762994UL)) -#define bFM4_RTC_WTTR0_TM6 *((volatile unsigned int*)(0x42762998UL)) -#define bFM4_RTC_WTTR0_TM7 *((volatile unsigned int*)(0x4276299CUL)) -#define bFM4_RTC_WTTR1_TM8 *((volatile unsigned int*)(0x42762A00UL)) -#define bFM4_RTC_WTTR1_TM9 *((volatile unsigned int*)(0x42762A04UL)) -#define bFM4_RTC_WTTR1_TM10 *((volatile unsigned int*)(0x42762A08UL)) -#define bFM4_RTC_WTTR1_TM11 *((volatile unsigned int*)(0x42762A0CUL)) -#define bFM4_RTC_WTTR1_TM12 *((volatile unsigned int*)(0x42762A10UL)) -#define bFM4_RTC_WTTR1_TM13 *((volatile unsigned int*)(0x42762A14UL)) -#define bFM4_RTC_WTTR1_TM14 *((volatile unsigned int*)(0x42762A18UL)) -#define bFM4_RTC_WTTR1_TM15 *((volatile unsigned int*)(0x42762A1CUL)) -#define bFM4_RTC_WTTR2_TM16 *((volatile unsigned int*)(0x42762A80UL)) -#define bFM4_RTC_WTTR2_TM17 *((volatile unsigned int*)(0x42762A84UL)) -#define bFM4_RTC_WTCAL1_WTCAL10 *((volatile unsigned int*)(0x42762B80UL)) -#define bFM4_RTC_WTCAL1_WTCAL11 *((volatile unsigned int*)(0x42762B84UL)) -#define bFM4_RTC_WTCALEN_WTCALEN *((volatile unsigned int*)(0x42762C00UL)) -#define bFM4_RTC_WTDIV_WTDIV0 *((volatile unsigned int*)(0x42762C80UL)) -#define bFM4_RTC_WTDIV_WTDIV1 *((volatile unsigned int*)(0x42762C84UL)) -#define bFM4_RTC_WTDIV_WTDIV2 *((volatile unsigned int*)(0x42762C88UL)) -#define bFM4_RTC_WTDIV_WTDIV3 *((volatile unsigned int*)(0x42762C8CUL)) -#define bFM4_RTC_WTDIVEN_WTDIVEN *((volatile unsigned int*)(0x42762D00UL)) -#define bFM4_RTC_WTDIVEN_WTDIVRDY *((volatile unsigned int*)(0x42762D04UL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD0 *((volatile unsigned int*)(0x42762D80UL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD1 *((volatile unsigned int*)(0x42762D84UL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD2 *((volatile unsigned int*)(0x42762D88UL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD3 *((volatile unsigned int*)(0x42762D8CUL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD4 *((volatile unsigned int*)(0x42762D90UL)) -#define bFM4_RTC_WTCALPRD_WTCALPRD5 *((volatile unsigned int*)(0x42762D94UL)) -#define bFM4_RTC_WTCOSEL_WTCOSEL *((volatile unsigned int*)(0x42762E00UL)) -#define bFM4_RTC_VB_CLKDIV_DIV0 *((volatile unsigned int*)(0x42762E80UL)) -#define bFM4_RTC_VB_CLKDIV_DIV1 *((volatile unsigned int*)(0x42762E84UL)) -#define bFM4_RTC_VB_CLKDIV_DIV2 *((volatile unsigned int*)(0x42762E88UL)) -#define bFM4_RTC_VB_CLKDIV_DIV3 *((volatile unsigned int*)(0x42762E8CUL)) -#define bFM4_RTC_VB_CLKDIV_DIV4 *((volatile unsigned int*)(0x42762E90UL)) -#define bFM4_RTC_VB_CLKDIV_DIV5 *((volatile unsigned int*)(0x42762E94UL)) -#define bFM4_RTC_VB_CLKDIV_DIV6 *((volatile unsigned int*)(0x42762E98UL)) -#define bFM4_RTC_VB_CLKDIV_DIV7 *((volatile unsigned int*)(0x42762E9CUL)) -#define bFM4_RTC_WTOSCCNT_SOSCEX *((volatile unsigned int*)(0x42762F00UL)) -#define bFM4_RTC_WTOSCCNT_SOSCNTL *((volatile unsigned int*)(0x42762F04UL)) -#define bFM4_RTC_BOOST_BOOST0 *((volatile unsigned int*)(0x42763100UL)) -#define bFM4_RTC_BOOST_BOOST1 *((volatile unsigned int*)(0x42763104UL)) -#define bFM4_RTC_EWKUP_WUP0 *((volatile unsigned int*)(0x42763180UL)) -#define bFM4_RTC_VDET_PON *((volatile unsigned int*)(0x4276321CUL)) -#define bFM4_RTC_HIBRST_HIBRST *((volatile unsigned int*)(0x42763300UL)) -#define bFM4_RTC_VBPFR_VPFR0 *((volatile unsigned int*)(0x42763380UL)) -#define bFM4_RTC_VBPFR_VPFR1 *((volatile unsigned int*)(0x42763384UL)) -#define bFM4_RTC_VBPFR_VPFR2 *((volatile unsigned int*)(0x42763388UL)) -#define bFM4_RTC_VBPFR_VPFR3 *((volatile unsigned int*)(0x4276338CUL)) -#define bFM4_RTC_VBPFR_SPSR0 *((volatile unsigned int*)(0x42763390UL)) -#define bFM4_RTC_VBPFR_SPSR1 *((volatile unsigned int*)(0x42763394UL)) -#define bFM4_RTC_VBPCR_VPCR0 *((volatile unsigned int*)(0x42763400UL)) -#define bFM4_RTC_VBPCR_VPCR1 *((volatile unsigned int*)(0x42763404UL)) -#define bFM4_RTC_VBPCR_VPCR2 *((volatile unsigned int*)(0x42763408UL)) -#define bFM4_RTC_VBPCR_VPCR3 *((volatile unsigned int*)(0x4276340CUL)) -#define bFM4_RTC_VBDDR_VDDR0 *((volatile unsigned int*)(0x42763480UL)) -#define bFM4_RTC_VBDDR_VDDR1 *((volatile unsigned int*)(0x42763484UL)) -#define bFM4_RTC_VBDDR_VDDR2 *((volatile unsigned int*)(0x42763488UL)) -#define bFM4_RTC_VBDDR_VDDR3 *((volatile unsigned int*)(0x4276348CUL)) -#define bFM4_RTC_VBDIR_VDIR0 *((volatile unsigned int*)(0x42763500UL)) -#define bFM4_RTC_VBDIR_VDIR1 *((volatile unsigned int*)(0x42763504UL)) -#define bFM4_RTC_VBDIR_VDIR2 *((volatile unsigned int*)(0x42763508UL)) -#define bFM4_RTC_VBDIR_VDIR3 *((volatile unsigned int*)(0x4276350CUL)) -#define bFM4_RTC_VBDOR_VDOR0 *((volatile unsigned int*)(0x42763580UL)) -#define bFM4_RTC_VBDOR_VDOR1 *((volatile unsigned int*)(0x42763584UL)) -#define bFM4_RTC_VBDOR_VDOR2 *((volatile unsigned int*)(0x42763588UL)) -#define bFM4_RTC_VBDOR_VDOR3 *((volatile unsigned int*)(0x4276358CUL)) -#define bFM4_RTC_VBPZR_VPZR0 *((volatile unsigned int*)(0x42763600UL)) -#define bFM4_RTC_VBPZR_VPZR1 *((volatile unsigned int*)(0x42763604UL)) - -/* Low-speed CR prescaler registers */ -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD0 *((volatile unsigned int*)(0x42780000UL)) -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD1 *((volatile unsigned int*)(0x42780004UL)) -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD2 *((volatile unsigned int*)(0x42780008UL)) -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD3 *((volatile unsigned int*)(0x4278000CUL)) -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD4 *((volatile unsigned int*)(0x42780010UL)) -#define bFM4_LCR_LCR_PRSLD_LCR_PRSLD5 *((volatile unsigned int*)(0x42780014UL)) - -/* Peripheral Clock Gating registers */ -#define bFM4_CLK_GATING_CKEN0_MFSCK0 *((volatile unsigned int*)(0x42782000UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK1 *((volatile unsigned int*)(0x42782004UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK2 *((volatile unsigned int*)(0x42782008UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK3 *((volatile unsigned int*)(0x4278200CUL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK4 *((volatile unsigned int*)(0x42782010UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK5 *((volatile unsigned int*)(0x42782014UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK6 *((volatile unsigned int*)(0x42782018UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK7 *((volatile unsigned int*)(0x4278201CUL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK8 *((volatile unsigned int*)(0x42782020UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK9 *((volatile unsigned int*)(0x42782024UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK10 *((volatile unsigned int*)(0x42782028UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK11 *((volatile unsigned int*)(0x4278202CUL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK12 *((volatile unsigned int*)(0x42782030UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK13 *((volatile unsigned int*)(0x42782034UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK14 *((volatile unsigned int*)(0x42782038UL)) -#define bFM4_CLK_GATING_CKEN0_MFSCK15 *((volatile unsigned int*)(0x4278203CUL)) -#define bFM4_CLK_GATING_CKEN0_ADCCK0 *((volatile unsigned int*)(0x42782040UL)) -#define bFM4_CLK_GATING_CKEN0_ADCCK1 *((volatile unsigned int*)(0x42782044UL)) -#define bFM4_CLK_GATING_CKEN0_ADCCK2 *((volatile unsigned int*)(0x42782048UL)) -#define bFM4_CLK_GATING_CKEN0_ADCCK3 *((volatile unsigned int*)(0x4278204CUL)) -#define bFM4_CLK_GATING_CKEN0_DMACK *((volatile unsigned int*)(0x42782060UL)) -#define bFM4_CLK_GATING_CKEN0_EXBCK *((volatile unsigned int*)(0x42782068UL)) -#define bFM4_CLK_GATING_CKEN0_GIOCK *((volatile unsigned int*)(0x42782070UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST0 *((volatile unsigned int*)(0x42782080UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST1 *((volatile unsigned int*)(0x42782084UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST2 *((volatile unsigned int*)(0x42782088UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST3 *((volatile unsigned int*)(0x4278208CUL)) -#define bFM4_CLK_GATING_MRST0_MFSRST4 *((volatile unsigned int*)(0x42782090UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST5 *((volatile unsigned int*)(0x42782094UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST6 *((volatile unsigned int*)(0x42782098UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST7 *((volatile unsigned int*)(0x4278209CUL)) -#define bFM4_CLK_GATING_MRST0_MFSRST8 *((volatile unsigned int*)(0x427820A0UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST9 *((volatile unsigned int*)(0x427820A4UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST10 *((volatile unsigned int*)(0x427820A8UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST11 *((volatile unsigned int*)(0x427820ACUL)) -#define bFM4_CLK_GATING_MRST0_MFSRST12 *((volatile unsigned int*)(0x427820B0UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST13 *((volatile unsigned int*)(0x427820B4UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST14 *((volatile unsigned int*)(0x427820B8UL)) -#define bFM4_CLK_GATING_MRST0_MFSRST15 *((volatile unsigned int*)(0x427820BCUL)) -#define bFM4_CLK_GATING_MRST0_ADCRST0 *((volatile unsigned int*)(0x427820C0UL)) -#define bFM4_CLK_GATING_MRST0_ADCRST1 *((volatile unsigned int*)(0x427820C4UL)) -#define bFM4_CLK_GATING_MRST0_ADCRST2 *((volatile unsigned int*)(0x427820C8UL)) -#define bFM4_CLK_GATING_MRST0_ADCRST3 *((volatile unsigned int*)(0x427820CCUL)) -#define bFM4_CLK_GATING_MRST0_DMARST *((volatile unsigned int*)(0x427820E0UL)) -#define bFM4_CLK_GATING_MRST0_EXBRST *((volatile unsigned int*)(0x427820E8UL)) -#define bFM4_CLK_GATING_CKEN1_BTMCK0 *((volatile unsigned int*)(0x42782200UL)) -#define bFM4_CLK_GATING_CKEN1_BTMCK1 *((volatile unsigned int*)(0x42782204UL)) -#define bFM4_CLK_GATING_CKEN1_BTMCK2 *((volatile unsigned int*)(0x42782208UL)) -#define bFM4_CLK_GATING_CKEN1_BTMCK3 *((volatile unsigned int*)(0x4278220CUL)) -#define bFM4_CLK_GATING_CKEN1_MFTCK0 *((volatile unsigned int*)(0x42782220UL)) -#define bFM4_CLK_GATING_CKEN1_MFTCK1 *((volatile unsigned int*)(0x42782224UL)) -#define bFM4_CLK_GATING_CKEN1_MFTCK2 *((volatile unsigned int*)(0x42782228UL)) -#define bFM4_CLK_GATING_CKEN1_MFTCK3 *((volatile unsigned int*)(0x4278222CUL)) -#define bFM4_CLK_GATING_CKEN1_QDUCK0 *((volatile unsigned int*)(0x42782240UL)) -#define bFM4_CLK_GATING_CKEN1_QDUCK1 *((volatile unsigned int*)(0x42782244UL)) -#define bFM4_CLK_GATING_CKEN1_QDUCK2 *((volatile unsigned int*)(0x42782248UL)) -#define bFM4_CLK_GATING_CKEN1_QDUCK3 *((volatile unsigned int*)(0x4278224CUL)) -#define bFM4_CLK_GATING_MRST1_BTMRST0 *((volatile unsigned int*)(0x42782280UL)) -#define bFM4_CLK_GATING_MRST1_BTMRST1 *((volatile unsigned int*)(0x42782284UL)) -#define bFM4_CLK_GATING_MRST1_BTMRST2 *((volatile unsigned int*)(0x42782288UL)) -#define bFM4_CLK_GATING_MRST1_BTMRST3 *((volatile unsigned int*)(0x4278228CUL)) -#define bFM4_CLK_GATING_MRST1_MFTRST0 *((volatile unsigned int*)(0x427822A0UL)) -#define bFM4_CLK_GATING_MRST1_MFTRST1 *((volatile unsigned int*)(0x427822A4UL)) -#define bFM4_CLK_GATING_MRST1_MFTRST2 *((volatile unsigned int*)(0x427822A8UL)) -#define bFM4_CLK_GATING_MRST1_MFTRST3 *((volatile unsigned int*)(0x427822ACUL)) -#define bFM4_CLK_GATING_MRST1_QDURST0 *((volatile unsigned int*)(0x427822C0UL)) -#define bFM4_CLK_GATING_MRST1_QDURST1 *((volatile unsigned int*)(0x427822C4UL)) -#define bFM4_CLK_GATING_MRST1_QDURST2 *((volatile unsigned int*)(0x427822C8UL)) -#define bFM4_CLK_GATING_MRST1_QDURST3 *((volatile unsigned int*)(0x427822CCUL)) -#define bFM4_CLK_GATING_CKEN2_USBCK0 *((volatile unsigned int*)(0x42782400UL)) -#define bFM4_CLK_GATING_CKEN2_USBCK1 *((volatile unsigned int*)(0x42782404UL)) -#define bFM4_CLK_GATING_CKEN2_CANCK0 *((volatile unsigned int*)(0x42782410UL)) -#define bFM4_CLK_GATING_CKEN2_CANCK1 *((volatile unsigned int*)(0x42782414UL)) -#define bFM4_CLK_GATING_CKEN2_SDCCK *((volatile unsigned int*)(0x42782420UL)) -#define bFM4_CLK_GATING_MRST2_USBRST0 *((volatile unsigned int*)(0x42782480UL)) -#define bFM4_CLK_GATING_MRST2_USBRST1 *((volatile unsigned int*)(0x42782484UL)) -#define bFM4_CLK_GATING_MRST2_CANRST0 *((volatile unsigned int*)(0x42782490UL)) -#define bFM4_CLK_GATING_MRST2_CANRST1 *((volatile unsigned int*)(0x42782494UL)) -#define bFM4_CLK_GATING_MRST2_SDCRST *((volatile unsigned int*)(0x427824A0UL)) - -/* External bus interface registers */ -#define bFM4_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM4_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM4_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM4_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM4_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM4_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) -#define bFM4_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM4_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM4_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM4_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM4_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM4_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) -#define bFM4_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM4_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM4_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM4_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM4_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM4_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) -#define bFM4_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM4_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM4_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM4_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM4_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM4_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) -#define bFM4_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM4_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM4_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM4_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM4_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM4_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) -#define bFM4_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM4_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM4_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM4_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM4_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM4_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM4_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM4_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM4_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM4_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM4_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM4_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM4_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM4_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM4_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM4_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM4_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM4_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM4_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM4_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM4_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM4_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM4_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM4_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM4_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM4_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM4_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM4_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM4_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM4_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM4_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM4_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM4_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM4_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM4_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM4_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM4_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM4_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM4_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM4_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM4_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM4_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM4_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM4_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM4_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM4_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM4_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM4_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM4_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM4_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM4_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM4_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM4_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM4_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM4_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM4_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM4_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM4_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM4_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM4_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM4_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM4_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM4_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM4_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM4_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM4_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM4_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM4_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM4_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM4_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM4_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM4_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM4_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM4_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM4_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM4_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM4_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM4_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM4_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM4_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM4_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM4_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM4_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM4_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM4_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM4_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM4_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM4_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM4_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM4_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM4_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM4_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM4_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM4_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM4_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM4_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM4_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM4_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM4_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM4_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM4_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM4_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM4_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM4_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM4_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM4_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM4_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM4_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM4_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM4_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM4_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM4_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM4_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM4_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM4_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM4_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM4_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM4_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM4_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM4_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM4_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM4_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM4_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM4_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM4_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM4_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM4_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM4_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM4_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM4_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM4_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM4_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM4_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM4_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM4_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM4_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM4_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM4_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM4_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM4_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM4_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM4_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM4_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM4_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM4_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM4_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM4_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM4_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM4_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM4_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM4_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM4_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM4_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM4_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM4_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM4_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM4_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM4_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM4_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM4_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM4_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM4_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM4_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM4_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM4_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM4_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM4_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM4_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM4_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM4_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM4_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM4_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM4_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM4_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM4_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM4_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM4_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM4_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM4_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM4_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM4_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM4_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM4_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM4_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM4_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM4_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM4_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM4_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM4_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM4_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM4_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM4_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM4_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM4_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM4_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM4_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM4_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM4_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM4_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM4_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM4_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM4_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM4_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM4_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM4_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM4_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM4_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM4_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM4_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM4_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM4_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM4_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM4_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM4_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM4_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM4_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM4_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM4_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM4_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM4_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM4_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM4_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM4_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM4_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM4_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM4_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM4_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM4_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM4_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM4_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM4_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM4_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM4_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM4_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM4_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) - -/* USB channel 0 registers */ -#define bFM4_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM4_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM4_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM4_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM4_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM4_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM4_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM4_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM4_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM4_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM4_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM4_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM4_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM4_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM4_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM4_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM4_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM4_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM4_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM4_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM4_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM4_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM4_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM4_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM4_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM4_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM4_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM4_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM4_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM4_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM4_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM4_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM4_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM4_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM4_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM4_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM4_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM4_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM4_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM4_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM4_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM4_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM4_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM4_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM4_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM4_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM4_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM4_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM4_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM4_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM4_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM4_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM4_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM4_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM4_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM4_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM4_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM4_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM4_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM4_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM4_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM4_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM4_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM4_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM4_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM4_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM4_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM4_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM4_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM4_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM4_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM4_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM4_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM4_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM4_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM4_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM4_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM4_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM4_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM4_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM4_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM4_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM4_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM4_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM4_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM4_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM4_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM4_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM4_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM4_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM4_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM4_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM4_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM4_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM4_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM4_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM4_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM4_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM4_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM4_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM4_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM4_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM4_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM4_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM4_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM4_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM4_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM4_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM4_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM4_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM4_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM4_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM4_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM4_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM4_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM4_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM4_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM4_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM4_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM4_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM4_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM4_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM4_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM4_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM4_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM4_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM4_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM4_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM4_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM4_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM4_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM4_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM4_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM4_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM4_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM4_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM4_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM4_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM4_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM4_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM4_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM4_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM4_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM4_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM4_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM4_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM4_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM4_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM4_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM4_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM4_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM4_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM4_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM4_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM4_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM4_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM4_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM4_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM4_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM4_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM4_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM4_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM4_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM4_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM4_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM4_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM4_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM4_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM4_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM4_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM4_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM4_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM4_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM4_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM4_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM4_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM4_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM4_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM4_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM4_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM4_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM4_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM4_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM4_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM4_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM4_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM4_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM4_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM4_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM4_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM4_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM4_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM4_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM4_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM4_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM4_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM4_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM4_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM4_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM4_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM4_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM4_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM4_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM4_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM4_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM4_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM4_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM4_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM4_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM4_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM4_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM4_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM4_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM4_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM4_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM4_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM4_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM4_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM4_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM4_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM4_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM4_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM4_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM4_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM4_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM4_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM4_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM4_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM4_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM4_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM4_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM4_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM4_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM4_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM4_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM4_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM4_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM4_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM4_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM4_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM4_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM4_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM4_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM4_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM4_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM4_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM4_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM4_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM4_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM4_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM4_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM4_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM4_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM4_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM4_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM4_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM4_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM4_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM4_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM4_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM4_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM4_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM4_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM4_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM4_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM4_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM4_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM4_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM4_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM4_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM4_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM4_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM4_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM4_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM4_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM4_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM4_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM4_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM4_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM4_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM4_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) -#define bFM4_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM4_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM4_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM4_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM4_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM4_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM4_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM4_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM4_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM4_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM4_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM4_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM4_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM4_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM4_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM4_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM4_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM4_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM4_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM4_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM4_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM4_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM4_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM4_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM4_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM4_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM4_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM4_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM4_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM4_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM4_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM4_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM4_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM4_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM4_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM4_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM4_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM4_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM4_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM4_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM4_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM4_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM4_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM4_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM4_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM4_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM4_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM4_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM4_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM4_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM4_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM4_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM4_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM4_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM4_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM4_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM4_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM4_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* DMA controller */ -#define bFM4_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM4_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM4_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM4_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM4_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM4_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM4_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM4_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM4_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM4_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM4_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM4_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM4_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM4_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM4_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM4_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM4_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM4_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM4_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM4_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM4_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM4_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM4_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM4_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM4_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM4_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM4_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM4_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM4_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM4_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM4_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM4_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM4_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM4_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM4_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM4_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM4_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM4_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM4_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM4_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM4_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM4_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM4_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM4_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM4_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM4_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM4_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM4_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM4_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM4_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM4_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM4_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM4_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM4_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM4_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM4_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM4_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM4_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM4_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM4_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM4_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM4_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM4_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM4_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM4_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM4_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM4_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM4_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM4_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM4_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM4_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM4_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM4_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM4_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM4_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM4_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM4_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM4_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM4_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM4_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM4_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM4_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM4_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM4_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM4_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM4_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM4_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM4_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM4_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM4_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM4_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM4_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM4_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM4_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM4_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM4_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM4_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM4_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM4_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM4_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM4_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM4_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM4_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM4_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM4_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM4_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM4_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM4_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM4_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM4_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM4_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM4_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM4_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM4_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM4_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM4_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM4_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM4_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM4_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM4_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM4_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM4_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM4_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM4_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM4_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM4_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM4_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM4_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM4_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM4_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM4_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM4_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM4_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM4_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM4_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM4_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM4_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM4_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM4_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM4_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM4_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM4_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM4_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM4_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM4_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM4_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM4_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM4_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM4_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM4_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM4_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM4_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM4_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM4_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM4_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM4_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM4_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM4_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM4_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM4_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM4_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM4_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM4_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM4_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM4_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM4_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM4_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM4_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM4_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM4_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM4_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM4_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM4_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM4_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM4_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM4_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM4_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM4_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM4_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM4_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM4_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM4_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM4_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM4_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM4_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM4_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM4_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM4_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM4_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM4_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM4_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM4_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM4_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM4_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM4_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM4_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM4_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM4_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM4_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM4_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM4_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM4_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM4_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM4_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM4_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM4_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM4_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM4_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM4_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM4_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM4_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM4_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM4_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM4_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM4_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM4_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM4_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM4_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM4_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM4_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM4_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM4_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM4_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM4_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM4_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM4_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM4_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM4_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM4_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM4_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM4_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM4_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM4_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM4_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM4_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM4_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM4_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM4_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM4_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM4_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM4_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM4_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM4_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM4_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM4_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM4_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM4_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM4_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM4_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM4_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM4_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM4_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM4_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM4_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM4_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM4_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM4_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM4_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM4_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM4_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM4_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM4_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM4_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM4_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM4_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM4_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM4_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM4_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM4_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM4_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM4_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM4_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM4_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM4_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM4_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM4_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM4_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM4_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM4_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM4_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM4_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM4_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM4_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM4_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM4_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM4_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM4_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM4_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM4_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM4_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM4_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM4_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM4_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM4_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM4_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM4_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM4_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM4_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM4_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM4_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM4_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM4_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM4_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM4_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM4_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM4_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM4_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM4_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM4_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM4_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM4_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM4_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM4_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM4_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM4_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM4_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM4_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM4_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM4_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM4_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM4_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM4_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM4_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM4_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM4_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM4_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM4_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM4_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM4_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM4_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM4_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM4_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM4_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM4_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM4_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM4_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM4_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM4_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM4_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM4_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM4_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM4_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM4_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM4_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM4_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM4_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM4_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM4_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM4_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM4_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM4_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM4_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM4_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM4_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM4_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM4_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM4_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM4_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM4_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* CAN channel 0 registers */ -#define bFM4_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) -#define bFM4_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) -#define bFM4_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) -#define bFM4_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) -#define bFM4_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) -#define bFM4_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) -#define bFM4_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) -#define bFM4_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) -#define bFM4_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) -#define bFM4_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) -#define bFM4_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) -#define bFM4_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) -#define bFM4_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) -#define bFM4_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) -#define bFM4_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) -#define bFM4_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) -#define bFM4_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) -#define bFM4_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) -#define bFM4_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) -#define bFM4_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) -#define bFM4_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) -#define bFM4_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) -#define bFM4_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) -#define bFM4_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) -#define bFM4_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) -#define bFM4_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) -#define bFM4_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) -#define bFM4_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) -#define bFM4_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) -#define bFM4_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) -#define bFM4_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) -#define bFM4_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) -#define bFM4_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) -#define bFM4_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) -#define bFM4_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) -#define bFM4_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) -#define bFM4_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) -#define bFM4_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) -#define bFM4_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) -#define bFM4_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) -#define bFM4_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) -#define bFM4_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) -#define bFM4_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) -#define bFM4_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) -#define bFM4_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) -#define bFM4_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) -#define bFM4_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) -#define bFM4_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) -#define bFM4_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) -#define bFM4_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) -#define bFM4_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) -#define bFM4_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) -#define bFM4_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) -#define bFM4_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) -#define bFM4_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) -#define bFM4_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) -#define bFM4_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) -#define bFM4_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) -#define bFM4_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) -#define bFM4_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) -#define bFM4_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) -#define bFM4_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) -#define bFM4_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) -#define bFM4_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) -#define bFM4_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) -#define bFM4_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) -#define bFM4_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) -#define bFM4_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) -#define bFM4_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) -#define bFM4_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) -#define bFM4_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) -#define bFM4_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) -#define bFM4_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) -#define bFM4_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) -#define bFM4_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) -#define bFM4_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) -#define bFM4_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) -#define bFM4_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) -#define bFM4_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) -#define bFM4_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) -#define bFM4_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) -#define bFM4_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) -#define bFM4_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM4_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM4_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM4_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM4_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM4_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM4_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM4_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM4_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM4_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM4_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) -#define bFM4_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) -#define bFM4_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) -#define bFM4_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) -#define bFM4_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) -#define bFM4_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) -#define bFM4_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) -#define bFM4_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) -#define bFM4_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) -#define bFM4_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) -#define bFM4_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) -#define bFM4_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) -#define bFM4_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) -#define bFM4_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) -#define bFM4_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) -#define bFM4_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) -#define bFM4_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) -#define bFM4_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) -#define bFM4_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) -#define bFM4_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) -#define bFM4_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) -#define bFM4_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) -#define bFM4_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) -#define bFM4_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM4_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM4_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM4_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM4_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM4_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM4_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM4_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM4_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM4_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM4_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) -#define bFM4_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) -#define bFM4_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) -#define bFM4_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) -#define bFM4_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) -#define bFM4_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) -#define bFM4_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) -#define bFM4_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) -#define bFM4_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) -#define bFM4_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) -#define bFM4_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) -#define bFM4_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) -#define bFM4_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) -#define bFM4_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM4_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM4_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM4_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM4_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM4_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM4_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM4_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM4_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM4_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM4_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM4_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM4_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM4_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM4_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM4_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM4_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM4_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM4_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM4_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM4_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM4_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM4_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM4_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM4_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM4_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM4_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM4_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM4_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM4_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM4_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM4_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM4_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM4_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM4_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM4_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM4_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM4_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM4_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM4_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM4_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM4_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM4_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM4_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM4_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM4_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM4_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM4_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM4_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM4_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM4_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM4_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM4_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM4_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM4_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM4_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM4_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM4_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM4_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM4_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM4_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM4_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM4_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM4_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM4_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM4_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM4_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM4_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM4_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM4_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM4_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM4_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM4_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM4_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM4_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM4_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM4_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM4_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM4_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM4_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM4_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM4_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM4_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM4_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM4_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM4_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM4_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM4_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM4_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM4_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM4_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM4_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM4_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM4_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM4_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM4_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM4_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM4_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM4_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM4_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM4_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM4_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM4_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM4_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM4_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM4_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM4_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM4_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM4_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM4_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM4_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM4_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM4_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM4_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM4_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM4_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM4_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM4_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM4_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM4_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM4_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM4_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM4_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM4_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM4_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM4_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM4_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM4_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM4_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM4_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM4_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM4_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM4_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM4_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM4_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM4_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM4_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM4_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM4_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM4_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM4_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM4_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM4_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM4_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM4_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM4_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM4_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM4_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM4_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM4_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM4_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM4_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM4_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM4_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM4_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM4_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM4_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM4_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM4_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM4_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM4_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM4_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM4_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM4_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM4_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM4_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM4_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) - -/* CAN channel 1 registers */ -#define bFM4_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) -#define bFM4_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) -#define bFM4_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) -#define bFM4_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) -#define bFM4_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) -#define bFM4_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) -#define bFM4_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) -#define bFM4_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) -#define bFM4_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) -#define bFM4_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) -#define bFM4_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) -#define bFM4_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) -#define bFM4_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) -#define bFM4_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) -#define bFM4_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) -#define bFM4_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) -#define bFM4_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) -#define bFM4_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) -#define bFM4_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) -#define bFM4_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) -#define bFM4_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) -#define bFM4_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) -#define bFM4_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) -#define bFM4_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) -#define bFM4_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) -#define bFM4_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) -#define bFM4_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) -#define bFM4_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) -#define bFM4_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) -#define bFM4_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) -#define bFM4_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) -#define bFM4_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) -#define bFM4_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) -#define bFM4_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) -#define bFM4_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) -#define bFM4_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) -#define bFM4_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) -#define bFM4_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) -#define bFM4_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) -#define bFM4_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) -#define bFM4_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) -#define bFM4_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) -#define bFM4_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) -#define bFM4_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) -#define bFM4_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) -#define bFM4_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) -#define bFM4_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) -#define bFM4_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) -#define bFM4_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) -#define bFM4_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) -#define bFM4_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) -#define bFM4_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) -#define bFM4_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) -#define bFM4_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) -#define bFM4_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) -#define bFM4_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) -#define bFM4_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) -#define bFM4_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) -#define bFM4_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) -#define bFM4_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) -#define bFM4_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) -#define bFM4_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) -#define bFM4_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) -#define bFM4_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) -#define bFM4_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) -#define bFM4_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) -#define bFM4_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) -#define bFM4_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) -#define bFM4_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) -#define bFM4_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) -#define bFM4_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) -#define bFM4_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) -#define bFM4_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) -#define bFM4_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) -#define bFM4_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) -#define bFM4_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) -#define bFM4_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) -#define bFM4_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) -#define bFM4_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) -#define bFM4_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) -#define bFM4_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) -#define bFM4_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) -#define bFM4_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM4_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM4_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM4_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM4_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM4_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM4_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM4_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM4_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM4_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM4_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) -#define bFM4_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) -#define bFM4_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) -#define bFM4_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) -#define bFM4_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) -#define bFM4_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) -#define bFM4_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) -#define bFM4_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) -#define bFM4_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) -#define bFM4_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) -#define bFM4_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) -#define bFM4_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) -#define bFM4_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) -#define bFM4_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) -#define bFM4_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) -#define bFM4_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) -#define bFM4_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) -#define bFM4_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) -#define bFM4_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) -#define bFM4_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) -#define bFM4_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) -#define bFM4_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) -#define bFM4_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) -#define bFM4_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM4_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM4_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM4_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM4_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM4_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM4_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM4_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM4_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM4_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM4_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) -#define bFM4_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) -#define bFM4_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) -#define bFM4_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) -#define bFM4_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) -#define bFM4_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) -#define bFM4_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) -#define bFM4_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) -#define bFM4_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) -#define bFM4_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) -#define bFM4_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) -#define bFM4_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) -#define bFM4_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) -#define bFM4_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM4_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM4_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM4_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM4_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM4_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM4_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM4_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM4_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM4_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM4_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM4_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM4_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM4_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM4_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM4_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM4_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM4_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM4_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM4_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM4_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM4_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM4_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM4_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM4_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM4_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM4_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM4_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM4_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM4_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM4_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM4_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM4_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM4_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM4_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM4_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM4_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM4_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM4_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM4_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM4_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM4_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM4_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM4_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM4_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM4_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM4_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM4_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM4_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM4_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM4_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM4_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM4_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM4_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM4_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM4_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM4_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM4_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM4_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM4_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM4_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM4_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM4_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM4_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM4_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM4_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM4_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM4_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM4_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM4_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM4_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM4_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM4_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM4_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM4_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM4_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM4_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM4_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM4_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM4_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM4_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM4_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM4_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM4_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM4_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM4_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM4_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM4_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM4_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM4_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM4_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM4_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM4_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM4_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM4_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM4_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM4_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM4_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM4_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM4_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM4_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM4_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM4_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM4_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM4_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM4_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM4_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM4_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM4_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM4_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM4_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM4_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM4_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM4_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM4_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM4_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM4_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM4_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM4_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM4_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM4_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM4_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM4_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM4_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM4_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM4_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM4_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM4_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM4_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM4_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM4_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM4_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM4_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM4_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM4_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM4_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM4_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM4_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM4_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM4_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM4_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM4_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM4_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM4_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM4_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM4_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM4_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM4_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM4_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM4_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM4_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM4_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM4_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM4_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM4_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM4_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM4_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM4_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM4_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM4_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM4_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM4_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM4_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM4_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM4_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM4_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM4_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) - -/* SD IF registers */ - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9B560R_H_ */ - diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c b/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c deleted file mode 100644 index f58f1ac2ad..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c +++ /dev/null @@ -1,240 +0,0 @@ -/******************************************************************************* -* Copyright (C) 2013 Spansion LLC. All Rights Reserved. -* -* This software is owned and published by: -* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). -* -* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND -* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. -* -* This software contains source code for use with Spansion -* components. This software is licensed by Spansion to be adapted only -* for use in systems utilizing Spansion components. Spansion shall not be -* responsible for misuse or illegal use of this software for devices not -* supported herein. Spansion is providing this software "AS IS" and will -* not be responsible for issues arising from incorrect user implementation -* of the software. -* -* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, -* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), -* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, -* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED -* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED -* WARRANTY OF NONINFRINGEMENT. -* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, -* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT -* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, -* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR -* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, -* SAVINGS OR PROFITS, -* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR -* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED -* FROM, THE SOFTWARE. -* -* This software may be replicated in part or whole for the licensed use, -* with the restriction that this Disclaimer and Copyright notice must be -* included with each copy of this software, whether used in part or whole, -* at all times. -*/ -/** - ****************************************************************************** - ** \file system_mb9abxxx.c - ** - ** FM3 system initialization functions - ** All adjustments can be done in belonging header file. - ** - ** History: - ** 2013-01-21 0.1 MWi AI: Unification to be done - ** 2013-01-23 0.2 MWi mcu.h inclusion changed to pdl.h - ** 2013-06-28 0.3 EH Added Trace Buffer enable - ******************************************************************************/ - -#include "mcu.h" - -/** - ****************************************************************************** - ** System Clock Frequency (Core Clock) Variable according CMSIS - ******************************************************************************/ -uint32_t SystemCoreClock = __HCLK; - -/** - ****************************************************************************** - ** \brief Update the System Core Clock with current core Clock retrieved from - ** cpu registers. - ** \param none - ** \return none - ******************************************************************************/ -void SystemCoreClockUpdate (void) { - uint32_t masterClk; - uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance - - switch ((FM4_CRG->SCM_CTL >> 5U) & 0x07U) { - case 0u: /* internal High-speed Cr osc. */ - masterClk = __CLKHC; - break; - - case 1u: /* external main osc. */ - masterClk = __CLKMO; - break; - - case 2u: /* PLL clock */ - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violation: - // "Unordered accesses to a volatile location" - u32RegisterRead = (__CLKMO * (((uint32_t)(FM4_CRG->PLL_CTL2) & 0x3Fu) + 1u)); - masterClk = (u32RegisterRead / ((((uint32_t)(FM4_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u)); - break; - - case 4u: /* internal Low-speed CR osc. */ - masterClk = __CLKLC; - break; - - case 5u: /* external Sub osc. */ - masterClk = __CLKSO; - break; - - default: - masterClk = 0ul; - break; - } - - switch (FM4_CRG->BSC_PSR & 0x07u) { - case 0u: - SystemCoreClock = masterClk; - break; - - case 1u: - SystemCoreClock = masterClk / 2u; - break; - - case 2u: - SystemCoreClock = masterClk / 3u; - break; - - case 3u: - SystemCoreClock = masterClk / 4u; - break; - - case 4u: - SystemCoreClock = masterClk / 6u; - break; - - case 5u: - SystemCoreClock = masterClk /8u; - break; - - case 6u: - SystemCoreClock = masterClk /16u; - break; - - default: - SystemCoreClock = 0ul; - break; - } - -} - -/** - ****************************************************************************** - ** \brief Setup the microcontroller system. Initialize the System and update - ** the SystemCoreClock variable. - ** - ** \param none - ** \return none - ******************************************************************************/ -void SystemInit (void) { - - static uint8_t u8IoRegisterRead; // Workaround variable for MISRA C rule conformance - -#if (HWWD_DISABLE) /* HW Watchdog Disable */ - FM4_HWWDT->WDG_LCK = 0x1ACCE551u; /* HW Watchdog Unlock */ - FM4_HWWDT->WDG_LCK = 0xE5331AAEu; - FM4_HWWDT->WDG_CTL = 0u; /* HW Watchdog stop */ -#endif - -#if (TRACE_BUFFER_ENABLE) - FM4_FLASH_IF->FBFCR = 0x01; /* Trace Buffer enable */ -#endif - -#if (CLOCK_SETUP) /* Clock Setup */ - FM4_CRG->BSC_PSR = (uint8_t)BSC_PSR_Val; /* set System Clock presacaler */ - FM4_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val; /* set APB0 presacaler */ - FM4_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val; /* set APB1 presacaler */ - FM4_CRG->APBC2_PSR = (uint8_t)APBC2_PSR_Val; /* set APB2 presacaler */ - FM4_CRG->SWC_PSR = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */ - FM4_CRG->TTC_PSR = (uint8_t)TTC_PSR_Val; /* set Trace Clock presacaler */ - - FM4_CRG->CSW_TMR = (uint8_t)CSW_TMR_Val; /* set oscillation stabilization wait time */ - - if (SCM_CTL_Val & (1ul << 1u)) { /* Main clock oscillator enabled ? */ - FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 1u); /* enable main oscillator */ - - while (!((FM4_CRG->SCM_STR) & (uint8_t)(1ul << 1u))) /* wait for Main clock oscillation stable */ - {} - } - - if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ - // Initialize VBAT (Temporary process) - FM4_RTC->VDET = 0x00; - FM4_RTC->VBPFR = 0x1C; - FM4_RTC->CCB = 0x10; - FM4_RTC->CCS = 0x08; - - // VB_CLK is less or equal to 1MHz (Temporary process) - FM4_RTC->VB_CLKDIV = 0x4E; - FM4_RTC->BOOST = 0x03; - - // Enable SUB CLK oscilation (Temporary process) - FM4_RTC->WTOSCCNT_f.SOSCEX = 0; - FM4_RTC->WTOSCCNT_f.SOSCNTL = 1; - - // Transmit to VBAT domain (Temporary process) - FM4_RTC->WTCR20_f.PWRITE = 1; - - // Wait to complete transmission - while(0 != FM4_RTC->WTCR10_f.TRANS) - - FM4_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ - while (!(FM4_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ - } - - FM4_CRG->PSW_TMR = (uint8_t)PSW_TMR_Val; /* set PLL stabilization wait time */ - FM4_CRG->PLL_CTL1 = (uint8_t) PLL_CTL1_Val; /* set PLLM and PLLK */ - FM4_CRG->PLL_CTL2 = (uint8_t)PLL_CTL2_Val; /* set PLLN */ - - if (SCM_CTL_Val & (uint8_t)(1ul << 4u)) { /* PLL enabled ? */ - FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 4u); /* enable PLL */ - while (!(FM4_CRG->SCM_STR & (uint8_t)(1ul << 4u))) /* wait for PLL stable */ - {} - } - - FM4_CRG->SCM_CTL |= (uint8_t)(SCM_CTL_Val & 0xE0u); /* Set Master Clock switch */ - - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violations: - // "Unordered reads and writes to or from same location" and - // "Unordered accesses to a volatile location" - do - { - u8IoRegisterRead = (FM4_CRG->SCM_CTL & 0xE0u); - }while ((FM4_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead); -#endif // (CLOCK_SETUP) - -#if (CR_TRIM_SETUP) - /* CR Trimming Data */ - if( 0x000003FFu != (FM4_FLASH_IF->CRTRMM & 0x000003FFu) ) - { - /* UnLock (MCR_FTRM) */ - FM4_CRTRIM->MCR_RLR = (uint32_t)0x1ACCE554u; - /* Set MCR_FTRM */ - FM4_CRTRIM->MCR_FTRM = (uint16_t)FM4_FLASH_IF->CRTRMM; - /* Lock (MCR_FTRM) */ - FM4_CRTRIM->MCR_RLR = (uint32_t)0x00000000u; - } -#endif // (CR_TRIM_SETUP) -} - - - diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h b/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h deleted file mode 100644 index 23cd07d188..0000000000 --- a/bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h +++ /dev/null @@ -1,674 +0,0 @@ -/******************************************************************************* -* Copyright (C) 2013 Spansion LLC. All Rights Reserved. -* -* This software is owned and published by: -* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). -* -* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND -* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. -* -* This software contains source code for use with Spansion -* components. This software is licensed by Spansion to be adapted only -* for use in systems utilizing Spansion components. Spansion shall not be -* responsible for misuse or illegal use of this software for devices not -* supported herein. Spansion is providing this software "AS IS" and will -* not be responsible for issues arising from incorrect user implementation -* of the software. -* -* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, -* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), -* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, -* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED -* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED -* WARRANTY OF NONINFRINGEMENT. -* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, -* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT -* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, -* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR -* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, -* SAVINGS OR PROFITS, -* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR -* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED -* FROM, THE SOFTWARE. -* -* This software may be replicated in part or whole for the licensed use, -* with the restriction that this Disclaimer and Copyright notice must be -* included with each copy of this software, whether used in part or whole, -* at all times. -*/ - -/******************************************************************************/ -/** \file system_mb9bf56xr.h - ** - ** Headerfile for FM4 system parameters - ** - ** History: - ** 2013-01-21 0.1 MWi AI: Unification to be done - ** 2013-02-06 0.2 MWi CMSIS coding restored; unifying still to be done - ** 2013-06-28 0.3 EH Added Trace Buffer enable definition - ** 2013-08-15 0.4 EH Changed APB1 Prescaler value - ******************************************************************************/ - -#ifndef _SYSTEM_MB9ABXXX_H_ -#define _SYSTEM_MB9ABXXX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************/ -/* Include files */ -/******************************************************************************/ -#include - -/******************************************************************************/ -/* Global pre-processor symbols/macros ('define') */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* START OF USER SETTINGS HERE */ -/* =========================== */ -/* */ -/* All lines with '<<<' can be set by user. */ -/* */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Clock Setup Enable - ** (USER SETTING) - ** - ** - 0 = No clock setup done by system_mb9xfxxx.c - ** - 1 = Clock setup done by system_mb9xfxxx.c - ******************************************************************************/ -#define CLOCK_SETUP 1 // <<< Define clock setup here - -/** - ****************************************************************************** - ** \brief External Main Clock Frequency (in Hz, [value]ul) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKMO ( 4000000ul) // <<< External 4MHz Crystal - -/** - ****************************************************************************** - ** \brief External Sub Clock Frequency (in Hz, [value]ul) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKSO ( 32768ul) // <<< External 32KHz Crystal - -/** - ****************************************************************************** - ** \brief System Clock Mode Control Register value definition - ** (USER SETTING) - ** - ** SCM_CTL - ** - ** Bit#7-5 : RCS[2:0] - ** - 0 = Internal high-speed CR oscillation (default) - ** - 1 = Main oscillation clock - ** - 2 = PLL oscillation clock - ** - 3 = (not allowed) - ** - 4 = Internal low-speed CR oscillation - ** - 5 = Sub clock oscillation - ** - 6 = (not allowed) - ** - 7 = (not allowed) - ** - ** Bit#4 : PLLE - ** - 0 = Disable PLL (default) - ** - 1 = Enable PLL - ** - ** Bit#3 : SOSCE - ** - 0 = Disable sub oscillation (default) - ** - 1 = Enable sub oscillation - ** - ** Bit#2 : (reserved) - ** - ** Bit#1 : MOSCE - ** - 0 = Disable main oscillation (default) - ** - 1 = Enable main oscillation - ** - ** Bit#0 : (reserved) - ******************************************************************************/ -#define SCM_CTL_Val 0x00000052ul // <<< Define SCM_CTL here - -/** - ****************************************************************************** - ** \brief Base Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** BSC_PSR - ** - ** Bit#7-3 : (reserved) - ** - ** Bit#2-0 : BSR[2:0] - ** - 0 = HCLK = Master Clock - ** - 1 = HCLK = Master Clock / 2 - ** - 2 = HCLK = Master Clock / 3 - ** - 3 = HCLK = Master Clock / 4 - ** - 4 = HCLK = Master Clock / 6 - ** - 5 = HCLK = Master Clock / 8 - ** - 6 = HCLK = Master Clock / 16 - ** - 7 = (reserved) - ******************************************************************************/ -#define BSC_PSR_Val 0x00000000ul // <<< Define BSC_PSR here - -/** - ****************************************************************************** - ** \brief APB0 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC0_PSR - ** - ** Bit#7-2 : (reserved) - ** - ** Bit#1-0 : BSR[2:0] - ** - 0 = PCLK0 = HCLK - ** - 1 = PCLK0 = HCLK / 2 - ** - 2 = PCLK0 = HCLK / 4 - ** - 3 = PCLK0 = HCLK / 8 - ******************************************************************************/ -#define APBC0_PSR_Val 0x00000001UL // <<< Define APBC0_PSR here - -/** - ****************************************************************************** - ** \brief APB1 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC1_PSR - ** - ** Bit#7 : APBC1EN - ** - 0 = Disable PCLK1 output - ** - 1 = Enables PCLK1 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC1RST - ** - 0 = APB1 bus reset, inactive (default) - ** - 1 = APB1 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC1[2:0] - ** - 0 = PCLK1 = HCLK - ** - 1 = PCLK1 = HCLK / 2 - ** - 2 = PCLK1 = HCLK / 4 - ** - 3 = PCLK1 = HCLK / 8 - ******************************************************************************/ -#define APBC1_PSR_Val 0x00000080ul // <<< Define APBC1_PSR here - -/** - ****************************************************************************** - ** \brief APB2 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC2_PSR - ** - ** Bit#7 : APBC2EN - ** - 0 = Disable PCLK2 output - ** - 1 = Enables PCLK2 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC2RST - ** - 0 = APB2 bus reset, inactive (default) - ** - 1 = APB2 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC2[1:0] - ** - 0 = PCLK2 = HCLK - ** - 1 = PCLK2 = HCLK / 2 - ** - 2 = PCLK2 = HCLK / 4 - ** - 3 = PCLK2 = HCLK / 8 - ******************************************************************************/ -#define APBC2_PSR_Val 0x00000081ul // <<< Define APBC2_PSR here - -/** - ****************************************************************************** - ** \brief Software Watchdog Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** SWC_PSR - ** - ** Bit#7 : TESTB - ** - 0 = (not allowed) - ** - 1 = (always write "1" to this bit) - ** - ** Bit#6-2 : (reserved) - ** - ** Bit#1-0 : SWDS[2:0] - ** - 0 = SWDGOGCLK = PCLK0 - ** - 1 = SWDGOGCLK = PCLK0 / 2 - ** - 2 = SWDGOGCLK = PCLK0 / 4 - ** - 3 = SWDGOGCLK = PCLK0 / 8 - ******************************************************************************/ -#define SWC_PSR_Val 0x00000003ul // <<< Define SWC_PSR here - -/** - ****************************************************************************** - ** \brief Trace Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** TTC_PSR - ** - ** Bit#7-1 : (reserved) - ** - ** Bit#0 : TTC - ** - 0 = TPIUCLK = HCLK - ** - 1 = TPIUCLK = HCLK / 2 - ******************************************************************************/ -#define TTC_PSR_Val 0x00000000ul // <<< Define TTC_PSR here - -/** - ****************************************************************************** - ** \brief Clock Stabilization Wait Time Register value definition - ** (USER SETTING) - ** - ** CSW_TMR - ** - ** Bit#7 : (reserved) - ** - ** Bit#6-4 : SOWT[2:0] - ** - 0 = ~10.3 ms (default) - ** - 1 = ~20.5 ms - ** - 2 = ~41 ms - ** - 3 = ~82 ms - ** - 4 = ~164 ms - ** - 5 = ~327 ms - ** - 6 = ~655 ms - ** - 7 = ~1.31 s - ** - ** Bit#3-0 : MOWT[3:0] - ** - 0 = ~500 ns (default) - ** - 1 = ~8 us - ** - 2 = ~16 us - ** - 3 = ~32 us - ** - 4 = ~64 us - ** - 5 = ~128 us - ** - 6 = ~256 us - ** - 7 = ~512 us - ** - 8 = ~1.0 ms - ** - 9 = ~2.0 ms - ** - 10 = ~4.0 ms - ** - 11 = ~8.0 ms - ** - 12 = ~33.0 ms - ** - 13 = ~131 ms - ** - 14 = ~524 ms - ** - 15 = ~2.0 s - ******************************************************************************/ -#define CSW_TMR_Val 0x0000005Cul // <<< Define CSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Clock Stabilization Wait Time Setup Register value definition - ** (USER SETTING) - ** - ** PSW_TMR - ** - ** Bit#7-5 : (reserved) - ** - ** Bit#4 : PINC - ** - 0 = Selects CLKMO (main oscillation) (default) - ** - 1 = (setting diabled) - ** - ** Bit#3 : (reserved) - ** - ** Bit#2-0 : POWT[2:0] - ** - 0 = ~128 us (default) - ** - 1 = ~256 us - ** - 2 = ~512 us - ** - 3 = ~1.02 ms - ** - 4 = ~2.05 ms - ** - 5 = ~4.10 ms - ** - 6 = ~8.20 ms - ** - 7 = ~16.40 ms - ******************************************************************************/ -#define PSW_TMR_Val 0x00000000ul // <<< Define PSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Control Register 1 value definition - ** (USER SETTING) - ** - ** PLL_CTL1 - ** - ** Bit#7-4 : PLLK[3:0] - ** - 0 = Division(PLLK) = 1/1 (default) - ** - 1 = Division(PLLK) = 1/2 - ** - 2 = Division(PLLK) = 1/3 - ** - . . . - ** - 15 = Division(PLLK) = 1/16 - ** - ** Bit#3-0 : PLLM[3:0] - ** - 0 = Division(PLLM) = 1/1 (default) - ** - 1 = Division(PLLM) = 1/2 - ** - 2 = Division(PLLM) = 1/3 - ** - . . . - ** - 15 = Division(PLLM) = 1/16 - ******************************************************************************/ -#define PLL_CTL1_Val 0x00000001ul // <<< Define PLL_CTL1 here - -/** - ****************************************************************************** - ** \brief PLL Control Register 2 value definition - ** (USER SETTING) - ** - ** PLL_CTL2 - ** - ** Bit#7-6 : (reserved) - ** - ** Bit#5-0 : PLLN[5:0] - ** - 0 = Division(PLLN) = 1/1 (default) - ** - 1 = Division(PLLN) = 1/2 - ** - 2 = Division(PLLN) = 1/3 - ** - . . . - ** - 63 = Division(PLLN) = 1/64 - ******************************************************************************/ -#define PLL_CTL2_Val 0x00000027ul // <<< Define PLL_CTL2 here - -/** - ****************************************************************************** - ** \brief Hardware Watchdog disable definition - ** (USER SETTING) - ** - ** - 0 = Hardware Watchdog enable - ** - 1 = Hardware Watchdog disable - ******************************************************************************/ -#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here - -/** - ****************************************************************************** - ** \brief Trimming CR - ** (USER SETTING) - ** - ** - 0 = CR is not trimmed at startup - ** - 1 = CR is trimmed at startup - ******************************************************************************/ -#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here - -/** - ****************************************************************************** - ** brief Trace Buffer enable definition - ** (USER SETTING) - ** - ** - 0 = Trace Buffer disable - ** - 1 = Trace Buffer enable - ******************************************************************************/ -#define TRACE_BUFFER_ENABLE 1 // <<< Define Trace Buffer enable here - - -/******************************************************************************/ -/* */ -/* END OF USER SETTINGS HERE */ -/* ========================= */ -/* */ -/******************************************************************************/ - -/******************************************************************************/ -/* Device dependent System Clock absolute maximum ranges */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]ul) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKHC ( 4000000ul) /* Internal 4MHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]ul) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKLC ( 100000ul) /* Internal 100KHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Any case minimum Main Clock frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMIN ( 4000000ul) - -/** - ****************************************************************************** - ** \brief Maximum Main Clock frequency using external clock (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMAX ( 48000000ul) - -/** - ****************************************************************************** - ** \brief Any case minimum Sub Clock frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMIN ( 32000ul) - -/** - ****************************************************************************** - ** \brief Maximum Sub Clock frequency using external clock (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMAX ( 100000ul) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL input frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMIN ( 4000000ul) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL input frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMAX ( 16000000ul) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL oscillation frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMIN (200000000ul) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL oscillation frequency (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMAX (320000000ul) - -/** - ****************************************************************************** - ** \brief Absolute maximum System Clock frequency (HCLK) (in Hz, [value]ul) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __HCLKMAX (160000000ul) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking range (clock settings). - ** - ** \return 0 Within range - ** \return 1 Out of range - ******************************************************************************/ -#define CHECK_RANGE(val, min, max) (((val) < (min)) || ((val) > (max))) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking bits with mask (clock settings). - ** Prevents from setting reserved bits by mistake. - ** - ** \return 0 All bits within mask - ** \return 1 One or more bits out of mask - ******************************************************************************/ -#define CHECK_RSVD(val, mask) ((val) & (mask)) - - -/******************************************************************************/ -/* Check register settings */ -/******************************************************************************/ -#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FAul)) - #error "SCM_CTL: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x10ul) != 0x10ul) - #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" -#endif - -#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007Ful)) - #error "CSW_TMR: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0x10ul)) /* if PLL is used */ - #if (CHECK_RSVD((PSW_TMR_Val), ~0x00000017ul)) - #error "PSW_TMR: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FFul)) - #error "PLL_CTL1: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003Ful)) - #error "PLL_CTL2: Invalid values of reserved bits!" - #endif -#endif - -#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007ul)) - #error "BSC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003ul)) - #error "APBC0_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000093ul)) - #error "APBC1_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000093ul)) - #error "APBC2_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003ul)) - #error "SWC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000003ul)) - #error "TTC_PSR: Invalid values of reserved bits!" -#endif - -/******************************************************************************/ -/* Define clocks with checking settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Calculate PLL K factor from settings - ******************************************************************************/ -#define __PLLK (((PLL_CTL1_Val >> 4ul) & 0x0Ful) + 1ul) - -/** - ****************************************************************************** - ** \brief Calculate PLL N factor from settings - ******************************************************************************/ -#define __PLLN (((PLL_CTL2_Val ) & 0x3Ful) + 1ul) - -/** - ****************************************************************************** - ** \brief Calculate PLL M factor from settings - ******************************************************************************/ -#define __PLLM (((PLL_CTL1_Val ) & 0x0Ful) + 1ul) - -/** - ****************************************************************************** - ** \brief Calculate PLL output frequency from settings - ******************************************************************************/ -#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) - -/******************************************************************************/ -/* Determine core clock frequency according to settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Define Master Clock from settings - ******************************************************************************/ -#if (((SCM_CTL_Val >> 5ul) & 0x07UL) == 0ul) - #define __MASTERCLK (__CLKHC) -#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 1ul) - #define __MASTERCLK (__CLKMO) -#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 2ul) - #define __MASTERCLK (__PLLCLK) -#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 4ul) - #define __MASTERCLK (__CLKLC) -#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 5ul) - #define __MASTERCLK (__CLKSO) -#else - #define __MASTERCLK (0UL) -#endif - -/** - ****************************************************************************** - ** \brief Define System Clock Frequency (Core Clock) from settings - ******************************************************************************/ -#if ((BSC_PSR_Val & 0x07UL) == 0ul) - #define __HCLK (__MASTERCLK / 1ul) -#elif ((BSC_PSR_Val & 0x07UL) == 1ul) - #define __HCLK (__MASTERCLK / 2ul) -#elif ((BSC_PSR_Val & 0x07UL) == 2ul) - #define __HCLK (__MASTERCLK / 3ul) -#elif ((BSC_PSR_Val & 0x07UL) == 3ul) - #define __HCLK (__MASTERCLK / 4ul) -#elif ((BSC_PSR_Val & 0x07UL) == 4ul) - #define __HCLK (__MASTERCLK / 6ul) -#elif ((BSC_PSR_Val & 0x07UL) == 5ul) - #define __HCLK (__MASTERCLK / 8ul) -#elif ((BSC_PSR_Val & 0x07UL) == 6ul) - #define __HCLK (__MASTERCLK /16ul) -#else - #define __HCLK (0ul) -#endif - -/******************************************************************************/ -/* HCLK range check */ -/******************************************************************************/ -#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX)) - #error "Main Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX)) - #error "Sub Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX)) - #error "PLL input frequency out of range!" -#endif - -#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX)) - #error "PLL oscillation frequency out of range!" -#endif - -#if (CHECK_RANGE(__HCLK, 0UL, __HCLKMAX)) - #error "System Clock (HCLK) out of range!" -#endif - -/******************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/******************************************************************************/ - -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) - -extern void SystemInit (void); // Initialize the system - -extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MB9ABXXX_H_ */ diff --git a/bsp/mb9bf568r/CMSIS/Include/arm_common_tables.h b/bsp/mb9bf568r/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7245c4f12b..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,35 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/mb9bf568r/CMSIS/Include/arm_math.h b/bsp/mb9bf568r/CMSIS/Include/arm_math.h deleted file mode 100644 index ffa03b6fd1..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7051 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the #define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ(q31_t data); - - - static __INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; - float32_t x1; - float32_t xSpacing; - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cm0.h b/bsp/mb9bf568r/CMSIS/Include/core_cm0.h deleted file mode 100644 index 9d7a19f9ae..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,665 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - - -/** \mainpage CMSIS Cortex-M0 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP - and not via processor. Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cm3.h b/bsp/mb9bf568r/CMSIS/Include/core_cm3.h deleted file mode 100644 index 1c688181af..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1236 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cm4.h b/bsp/mb9bf568r/CMSIS/Include/core_cm4.h deleted file mode 100644 index bf022ba67f..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1378 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - - -/** \mainpage CMSIS Cortex-M4 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - Cortex-M SIMD instructions - - The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /*!< standard types definitions */ -#include /*!< Core Instruction Access */ -#include /*!< Core Function Access */ -#include /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU CMSIS FPU - Type definitions for the Cortex-M Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cm4_simd.h b/bsp/mb9bf568r/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index e7b6765225..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,701 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ -/* intrinsic __SADD8 see intrinsics.h */ -/* intrinsic __QADD8 see intrinsics.h */ -/* intrinsic __SHADD8 see intrinsics.h */ -/* intrinsic __UADD8 see intrinsics.h */ -/* intrinsic __UQADD8 see intrinsics.h */ -/* intrinsic __UHADD8 see intrinsics.h */ -/* intrinsic __SSUB8 see intrinsics.h */ -/* intrinsic __QSUB8 see intrinsics.h */ -/* intrinsic __SHSUB8 see intrinsics.h */ -/* intrinsic __USUB8 see intrinsics.h */ -/* intrinsic __UQSUB8 see intrinsics.h */ -/* intrinsic __UHSUB8 see intrinsics.h */ -/* intrinsic __SADD16 see intrinsics.h */ -/* intrinsic __QADD16 see intrinsics.h */ -/* intrinsic __SHADD16 see intrinsics.h */ -/* intrinsic __UADD16 see intrinsics.h */ -/* intrinsic __UQADD16 see intrinsics.h */ -/* intrinsic __UHADD16 see intrinsics.h */ -/* intrinsic __SSUB16 see intrinsics.h */ -/* intrinsic __QSUB16 see intrinsics.h */ -/* intrinsic __SHSUB16 see intrinsics.h */ -/* intrinsic __USUB16 see intrinsics.h */ -/* intrinsic __UQSUB16 see intrinsics.h */ -/* intrinsic __UHSUB16 see intrinsics.h */ -/* intrinsic __SASX see intrinsics.h */ -/* intrinsic __QASX see intrinsics.h */ -/* intrinsic __SHASX see intrinsics.h */ -/* intrinsic __UASX see intrinsics.h */ -/* intrinsic __UQASX see intrinsics.h */ -/* intrinsic __UHASX see intrinsics.h */ -/* intrinsic __SSAX see intrinsics.h */ -/* intrinsic __QSAX see intrinsics.h */ -/* intrinsic __SHSAX see intrinsics.h */ -/* intrinsic __USAX see intrinsics.h */ -/* intrinsic __UQSAX see intrinsics.h */ -/* intrinsic __UHSAX see intrinsics.h */ -/* intrinsic __USAD8 see intrinsics.h */ -/* intrinsic __USADA8 see intrinsics.h */ -/* intrinsic __SSAT16 see intrinsics.h */ -/* intrinsic __USAT16 see intrinsics.h */ -/* intrinsic __UXTB16 see intrinsics.h */ -/* intrinsic __SXTB16 see intrinsics.h */ -/* intrinsic __UXTAB16 see intrinsics.h */ -/* intrinsic __SXTAB16 see intrinsics.h */ -/* intrinsic __SMUAD see intrinsics.h */ -/* intrinsic __SMUADX see intrinsics.h */ -/* intrinsic __SMLAD see intrinsics.h */ -/* intrinsic __SMLADX see intrinsics.h */ -/* intrinsic __SMLALD see intrinsics.h */ -/* intrinsic __SMLALDX see intrinsics.h */ -/* intrinsic __SMUSD see intrinsics.h */ -/* intrinsic __SMUSDX see intrinsics.h */ -/* intrinsic __SMLSD see intrinsics.h */ -/* intrinsic __SMLSDX see intrinsics.h */ -/* intrinsic __SMLSLD see intrinsics.h */ -/* intrinsic __SMLSLDX see intrinsics.h */ -/* intrinsic __SEL see intrinsics.h */ -/* intrinsic __QADD see intrinsics.h */ -/* intrinsic __QSUB see intrinsics.h */ -/* intrinsic __PKHBT see intrinsics.h */ -/* intrinsic __PKHTB see intrinsics.h */ - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cmFunc.h b/bsp/mb9bf568r/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 88819f9dd1..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/mb9bf568r/CMSIS/Include/core_cmInstr.h b/bsp/mb9bf568r/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 78d2ef80ba..0000000000 --- a/bsp/mb9bf568r/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,585 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/mb9bf568r/CMSIS/SConscript b/bsp/mb9bf568r/CMSIS/SConscript deleted file mode 100644 index 6ab907fca5..0000000000 --- a/bsp/mb9bf568r/CMSIS/SConscript +++ /dev/null @@ -1,19 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('DeviceSupport/*.c') - -CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport'] - -# add for startup script -if rtconfig.CROSS_TOOL == 'keil': - src += ['DeviceSupport/arm/startup_mb9bf56xr.s'] - -if rtconfig.CROSS_TOOL == 'gcc': - src += ['DeviceSupport/gcc/startup_mb9bf56xr.S'] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf568r/SConscript b/bsp/mb9bf568r/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/mb9bf568r/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/mb9bf568r/SConstruct b/bsp/mb9bf568r/SConstruct deleted file mode 100644 index 1725b1f69c..0000000000 --- a/bsp/mb9bf568r/SConstruct +++ /dev/null @@ -1,36 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread-fm4.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/mb9bf568r/applications/SConscript b/bsp/mb9bf568r/applications/SConscript deleted file mode 100644 index 01eb940dfb..0000000000 --- a/bsp/mb9bf568r/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf568r/applications/application.c b/bsp/mb9bf568r/applications/application.c deleted file mode 100644 index 12199175b2..0000000000 --- a/bsp/mb9bf568r/applications/application.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-05-24 Bernard the first version - */ - -/** - * @addtogroup FM4 - */ -/*@{*/ - -#include -#include "board.h" - -void rt_init_thread_entry(void *parameter) -{ -#ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); -#endif - - - //finsh_system_init(); -#if !defined(RT_USING_POSIX_STDIO) && defined(RT_USING_DEVICE) - finsh_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - - /**< init led device */ - { - extern void rt_led_hw_init(void); - rt_led_hw_init(); - } - -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, 8, 20); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf568r/applications/startup.c b/bsp/mb9bf568r/applications/startup.c deleted file mode 100644 index 263bd20a28..0000000000 --- a/bsp/mb9bf568r/applications/startup.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup FM4 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP -#ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM4_SRAM_END); -#elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM4_SRAM_END); -#else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM4_SRAM_END); -#endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init application */ - rt_application_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf568r/drivers/SConscript b/bsp/mb9bf568r/drivers/SConscript deleted file mode 100644 index 5bbef48785..0000000000 --- a/bsp/mb9bf568r/drivers/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf568r/drivers/board.c b/bsp/mb9bf568r/drivers/board.c deleted file mode 100644 index bd44ad80b1..0000000000 --- a/bsp/mb9bf568r/drivers/board.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -#include "serial.h" - -/** - * @addtogroup FM4 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This fucntion returns milliseconds since system passed - */ -rt_uint32_t rt_hw_tick_get_millisecond(void) -{ - rt_tick_t tick; - rt_uint32_t value; - -#define TICK_MS (1000/RT_TICK_PER_SECOND) - - tick = rt_tick_get(); - value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD; - - return value; -} - -/** - * This fucntion returns microseconds since system passed - */ -rt_uint32_t rt_hw_tick_get_microsecond(void) -{ - rt_tick_t tick; - rt_uint32_t value; - -#define TICK_US (1000000/RT_TICK_PER_SECOND) - - tick = rt_tick_get(); - value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; - - return value; -} - -/** -* This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init(void) -{ - /* disable all analog input. */ - FM4_GPIO->ADE = 0x00u; - - /* init systick */ - SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -} - -/*@}*/ diff --git a/bsp/mb9bf568r/drivers/board.h b/bsp/mb9bf568r/drivers/board.h deleted file mode 100644 index ed258f82a0..0000000000 --- a/bsp/mb9bf568r/drivers/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - - -#include -#include -#include - -#include "serial.h" - - -#define FM4_SRAM_SIZE 128 -#define FM4_SRAM_END (0x1FFF0000 + FM4_SRAM_SIZE * 1024) - -/* RT_USING_UART */ -#define RT_USING_UART0 - -#define RT_UART_RX_BUFFER_SIZE 128 - -void rt_hw_board_init(void); -rt_uint32_t rt_hw_tick_get_millisecond(void); -rt_uint32_t rt_hw_tick_get_microsecond(void); - -#endif diff --git a/bsp/mb9bf568r/drivers/led.c b/bsp/mb9bf568r/drivers/led.c deleted file mode 100644 index db80b56fd0..0000000000 --- a/bsp/mb9bf568r/drivers/led.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#include -#include "board.h" - -#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */ - -#define LED_NUM 3 -struct fm4_gpio_ctrl -{ - uint32_t led_num; - volatile uint32_t * PDOR; - volatile uint32_t * PDIR; -}; - -struct fm4_led -{ - /* inherit from rt_device */ - struct rt_device parent; - - struct fm4_gpio_ctrl fm4_gpio_ctrl[LED_NUM]; -}; - -static struct fm4_led fm4_led; - -static rt_err_t rt_led_init (rt_device_t dev) -{ - uint32_t i; - - /* led0-1-2 : P27-P38-PE0 */ - FM4_GPIO->PFR2 &= ~((1<<7) ); /* set P27 fuction is GPIO. */ - FM4_GPIO->DDR2 |= (1<<7) ; /* set P27 output. */ - FM4_GPIO->PFR3 &= ~((1<<8) ); /* set P38 fuction is GPIO. */ - FM4_GPIO->DDR3 |= (1<<8) ; /* set P38 output. */ - FM4_GPIO->PFRE &= ~((1<<0) ); /* set PE0 fuction is GPIO. */ - FM4_GPIO->DDRE |= (1<<0) ; /* set PE0 output. */ - - /* LED0 */ - i = 0; - fm4_led.fm4_gpio_ctrl[i].led_num = 7; - fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR2; - fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR2; - - /* LED1 */ - i++; - fm4_led.fm4_gpio_ctrl[i].led_num = 8; - fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR3; - fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR3; - - /* LED2 */ - i++; - fm4_led.fm4_gpio_ctrl[i].led_num = 0; - fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDORE; - fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIRE; - - return RT_EOK; -} - -static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_led_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_ubase_t index = 0; - rt_ubase_t nr = size; - rt_uint8_t * value = buffer; - - RT_ASSERT(dev == &fm4_led.parent); - RT_ASSERT((pos+size) <= LED_NUM ); - - for(index=0; index -void led(rt_uint32_t led, rt_uint32_t value) -{ - rt_uint8_t led_value = value; - rt_led_write(&fm4_led.parent, led, &led_value, 1); -} -FINSH_FUNCTION_EXPORT(led, e.g:led(0,0)/led(0,1).) -#endif diff --git a/bsp/mb9bf568r/drivers/mcu.h b/bsp/mb9bf568r/drivers/mcu.h deleted file mode 100644 index 5717ff37cc..0000000000 --- a/bsp/mb9bf568r/drivers/mcu.h +++ /dev/null @@ -1,65 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/** - ****************************************************************************** - ** \file mcu.h - ** - ** Header File for device dependent includes - ** - ** History: - ** 2011-05-19 V1.00 MWi first version - ** - ******************************************************************************/ - -#define PDL_INT_TYPE_C 1 -#define PDL_INT_TYPE_A 2 - -#define PDL_MCU_INT_TYPE PDL_INT_TYPE_A - -/** - ****************************************************************************** - ** \brief MCU header file include - ** - ******************************************************************************/ -#ifndef _MB9B560R_H_ - #include "mb9b560r.h" -#endif - -/** - ****************************************************************************** - ** \brief MCU system start-up header file include - ** - ******************************************************************************/ -#ifndef _SYSTEM_MB9ABXXX_H_ - #include "system_mb9bf56xr.h" -#endif diff --git a/bsp/mb9bf568r/drivers/serial.c b/bsp/mb9bf568r/drivers/serial.c deleted file mode 100644 index 6c3a132216..0000000000 --- a/bsp/mb9bf568r/drivers/serial.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#include - -#include "serial.h" - -/** - * @addtogroup FM4 MB9BF568R - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable interrupt */ - UART_ENABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - UART_DISABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->SSR & SSR_RDRF) - { - *ptr = uart->uart_device->RDR & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, - const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = '\r'; - } - - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = (*ptr & 0x1FF); - - ++ptr; - --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, - rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->SSR & SSR_RDRF) - { - rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -#ifdef RT_USING_UART0 -/* UART0 device driver structure */ -#define UART0 FM4_MFS0 -struct serial_int_rx uart0_int_rx; -struct serial_device uart0 = -{ - UART0, - MFS0_RX_IRQn, - MFS0_TX_IRQn, - &uart0_int_rx, - RT_NULL -}; -struct rt_device uart0_device; - -void MFS0_RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&uart0_device); - /* leave interrupt */ - rt_interrupt_leave(); -} - - -#endif /**< #ifdef RT_USING_UART0 */ - - -void rt_hw_serial_init(void) -{ - uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); - -#ifdef RT_USING_UART0 - // Initialize ports for MFS0 - FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 - FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; - FM4_GPIO->EPFR07 |= 0x00000040ul; - - // Initialize MFS to UART asynchronous mode - - uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; - uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ - uart0.uart_device->ESCR = ESCR_DATABITS_8; - uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - /* register UART0 device */ - rt_hw_serial_register(&uart0_device, - "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); - - -#endif /**< #ifdef RT_USING_UART0 */ - -} - -/*@}*/ diff --git a/bsp/mb9bf568r/drivers/serial.h b/bsp/mb9bf568r/drivers/serial.h deleted file mode 100644 index 776b2a3877..0000000000 --- a/bsp/mb9bf568r/drivers/serial.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#include "board.h" - -#define SMR_SOE 0x01U -#define SMR_BDS 0x04U -#define SMR_SBL 0x08U -#define SMR_WUCR 0x10U -#define SMR_MD_UART 0x00U -#define SMR_MD_UART_MP 0x20U -#define SMR_MD_SIO 0x40U -#define SMR_MD_LIN 0x60U -#define SMR_MD_I2C 0x80U - -#define SCR_TXE 0x01U -#define SCR_RXE 0x02U -#define SCR_TBIE 0x04U -#define SCR_TIE 0x08U -#define SCR_RIE 0x10U -#define SCR_UPGL 0x80U - -#define SSR_TBI 0x01U -#define SSR_TDRE 0x02U -#define SSR_RDRF 0x04U -#define SSR_ORE 0x08U -#define SSR_FRE 0x10U -#define SSR_PE 0x20U -#define SSR_REC 0x80U - -#define ESCR_P 0x08U -#define ESCR_PEN 0x10U -#define ESCR_INV 0x20U -#define ESCR_ESBL 0x40U -#define ESCR_FLWEN 0x80U -#define ESCR_DATABITS_8 0x00U -#define ESCR_DATABITS_5 0x01U -#define ESCR_DATABITS_6 0x02U -#define ESCR_DATABITS_7 0x03U -#define ESCR_DATABITS_9 0x04U - -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 128 -#define UART_TX_BUFFER_SIZE 128 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -/* - * Enable/DISABLE Interrupt Controller - */ -/* deviation from MISRA-C:2004 Rule 19.7 */ -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -struct serial_device -{ - FM4_MFS_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -void rt_hw_serial_isr(rt_device_t device); -void rt_hw_serial_init(void); - -#endif diff --git a/bsp/mb9bf568r/project.uvopt b/bsp/mb9bf568r/project.uvopt deleted file mode 100644 index c7c71b2bbf..0000000000 --- a/bsp/mb9bf568r/project.uvopt +++ /dev/null @@ -1,172 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rtthread-fm4 - 0x4 - ARM-ADS - - 4000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 14 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"CMSIS-DAP" -U -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000 - - - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - - - - - - - - Source Group 1 - 0 - 0 - 0 - 0 - - - diff --git a/bsp/mb9bf568r/project.uvproj b/bsp/mb9bf568r/project.uvproj deleted file mode 100644 index 2518cee715..0000000000 --- a/bsp/mb9bf568r/project.uvproj +++ /dev/null @@ -1,629 +0,0 @@ - - - 1.1 -
### uVision Project, (C) Keil Software
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- - - - - - - - - - - Applications - - - startup.c - 1 - applications\startup.c - - - - - application.c - 1 - applications\application.c - - - - - CMSIS - - - startup_mb9bf56xr.s - 2 - CMSIS\DeviceSupport\arm\startup_mb9bf56xr.s - - - - - system_mb9abxxx.c - 1 - CMSIS\DeviceSupport\system_mb9abxxx.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - time.c - 1 - ..\..\components\libc\compilers\common\time.c - - - - - stdlib.c - 1 - ..\..\components\libc\compilers\common\stdlib.c - - - - - CPU - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c - - - - - Drivers - - - serial.c - 1 - drivers\serial.c - - - - - board.c - 1 - drivers\board.c - - - - - led.c - 1 - drivers\led.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - Kernel - - - object.c - 1 - ..\..\src\object.c - - - - - clock.c - 1 - ..\..\src\clock.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - device.c - 1 - ..\..\src\device.c - - - - - - - diff --git a/bsp/mb9bf568r/rtconfig.h b/bsp/mb9bf568r/rtconfig.h deleted file mode 100644 index 8191fc8e65..0000000000 --- a/bsp/mb9bf568r/rtconfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 - -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 64 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_DEBUG_COLOR -#define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ -#define RT_USING_HOOK - -/* SECTION: IPC */ -/* Using Semaphore */ -#define RT_USING_SEMAPHORE - -/* Using Mutex */ -#define RT_USING_MUTEX - -/* Using Event */ -#define RT_USING_EVENT - -/* Using MailBox */ -#define RT_USING_MAILBOX - -/* Using Message Queue */ -#define RT_USING_MESSAGEQUEUE - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ -#define RT_USING_HEAP - -/* Using Small MM */ -#define RT_USING_SMALL_MEM - -// -#define RT_USING_COMPONENTS_INIT - -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE - -/* SECTION: Console options */ -/* #define RT_TINY_SIZE */ -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart0" - -/* SECTION: finsh, a C-Express shell */ -/* Using FinSH as Shell*/ -#define RT_USING_FINSH -/* Using symbol table */ -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_STACK_SIZE 1024 - -#endif diff --git a/bsp/mb9bf568r/rtconfig.py b/bsp/mb9bf568r/rtconfig.py deleted file mode 100644 index abee5014b2..0000000000 --- a/bsp/mb9bf568r/rtconfig.py +++ /dev/null @@ -1,86 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='keil' -BOARD_NAME = 'mb9bf568r' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil_MDK_471' -elif CROSS_TOOL == 'iar': - print('================ERROR============================') - print('Not support iar yet!') - print('=================================================') - exit(0) - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'g++' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-' + BOARD_NAME + '.map,-cref,-u,Reset_Handler -T rtthread-' + BOARD_NAME + '.ld -nostartfiles' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread_' + \ - BOARD_NAME + '.map --scatter rtthread-' + BOARD_NAME + '.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' diff --git a/bsp/mb9bf568r/rtthread-mb9bf568r.ld b/bsp/mb9bf568r/rtthread-mb9bf568r.ld deleted file mode 100644 index c6700b9535..0000000000 --- a/bsp/mb9bf568r/rtthread-mb9bf568r.ld +++ /dev/null @@ -1,221 +0,0 @@ -/* Linker script to configure memory regions - * - * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 - * BugURL:https://support.codesourcery.com/GNUToolchain/ - * - * Copyright 2007 CodeSourcery. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. */ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -ENTRY(_start) -SEARCH_DIR(.) - -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1024k */ - ram (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 /* 64k */ -} - -/* These force the linker to search for particular symbols from - * the start of the link process and thus ensure the user's - * overrides are picked up - */ -EXTERN(__cs3_reset_cortex_m) -EXTERN(__cs3_interrupt_vector_cortex_m) -EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) - -PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); -PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); -PROVIDE(__cs3_heap_start = _end); -PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - __cs3_region_start_rom = .; - *(.cs3.region-head.rom) - __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; - *(.cs3.interrupt_vector) - /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); - *(.rom) - *(.rom.b) - - __cs3_reset = __cs3_reset_cortex_m; - *(.cs3.reset) - /* Make sure we pulled in some reset code. */ - ASSERT (. != __cs3_reset, "No reset code"); - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - *(.gnu.warning) - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - __cs3_regions = .; - LONG (0) - LONG (__cs3_region_init_ram) - LONG (__cs3_region_start_ram) - LONG (__cs3_region_init_size_ram) - LONG (__cs3_region_zero_size_ram) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - } - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >rom - __exidx_end = .; - .text.align : - { - . = ALIGN(8); - _etext = .; - } >rom - __cs3_region_size_rom = LENGTH(rom); - __cs3_region_num = 1; - - .data : - { - __cs3_region_start_ram = .; - *(.cs3.region-head.ram) - KEEP(*(.jcr)) - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - *(.ram) - . = ALIGN (8); - _edata = .; - } >ram AT>rom - - .bss : - { - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - *(.ram.b) - . = ALIGN (8); - _end = .; - __end = .; - } >ram AT>rom - - .heap : - { - *(.heap) - } >ram - - __bss_end = .; - - .stack (__cs3_stack - __cs3_stack_size) : - { - *(.stack) - } >ram - - __cs3_region_init_ram = LOADADDR (.data); - __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; - __cs3_region_zero_size_ram = _end - _edata; - __cs3_region_size_ram = LENGTH(ram); - __cs3_region_num = 1; - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } - .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) } -} diff --git a/bsp/mb9bf568r/rtthread-mb9bf568r.sct b/bsp/mb9bf568r/rtthread-mb9bf568r.sct deleted file mode 100644 index 5b025eb611..0000000000 --- a/bsp/mb9bf568r/rtthread-mb9bf568r.sct +++ /dev/null @@ -1,23 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00100000 { ; load region size_region - ER_IROM1 0x00000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x1FFF0000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } - RW_IRAM2 0x20038000 0x00010000 { - .ANY (+RW +ZI) - } -} - -LR_IROM2 0x200C0000 0x00008000 { - ER_IROM2 0x200C0000 0x00008000 { ; load address = execution address - .ANY (+RO) - } -} diff --git a/bsp/mb9bf568r/template.uvopt b/bsp/mb9bf568r/template.uvopt deleted file mode 100644 index c7c71b2bbf..0000000000 --- a/bsp/mb9bf568r/template.uvopt +++ /dev/null @@ -1,172 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rtthread-fm4 - 0x4 - ARM-ADS - - 4000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 14 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"CMSIS-DAP" -U -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000 - - - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - - - - - - - - Source Group 1 - 0 - 0 - 0 - 0 - - - diff --git a/bsp/mb9bf568r/template.uvproj b/bsp/mb9bf568r/template.uvproj deleted file mode 100644 index b65281bbef..0000000000 --- a/bsp/mb9bf568r/template.uvproj +++ /dev/null @@ -1,398 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rtthread-fm4 - 0x4 - ARM-ADS - - - Cortex-M4 FPU - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 - - - - 5237 - - - - - - - - - - - - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - template_mb9b56xx - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - - 0 - 14 - - - - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - - 1 - 0 - 0 - 0 - 1 - 4105 - - BIN\CMSIS_AGDI.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 1 - 0 - 0 - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x200c0000 - 0x8000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x1fff0000 - 0x10000 - - - 0 - 0x20038000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - - - - - - - - - - - Source Group 1 - - - - - - diff --git a/bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf deleted file mode 100644 index aabdddc5d9..0000000000 Binary files a/bsp/mb9bf618s/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf and /dev/null differ diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h deleted file mode 100644 index 374040f314..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h +++ /dev/null @@ -1,29269 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/* */ -/* Header File for Device MB9BF618S */ -/* Version V1.00 */ -/* Date 2011-08-04 */ -/* */ -/************************************************************************/ - -#ifndef _MB9BF618S_H_ -#define _MB9BF618S_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - - -/****************************************************************************** - * Interrupt Number Definition - ******************************************************************************/ -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Super Visor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detector */ - WFG_IRQn = 3, /* Wave Form Generator */ - EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ - EXINT8_31_IRQn = 5, /* External Interrupt Request ch.8 to ch.31 */ - DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ - MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ - MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ - MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ - MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ - MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ - MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ - MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ - MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ - MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ - MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ - MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ - MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ - MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ - MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ - MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ - MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ - PPG_IRQn = 23, /* PPG */ - OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ - ADC0_IRQn = 25, /* ADC0 */ - ADC1_IRQn = 26, /* ADC1 */ - ADC2_IRQn = 27, /* ADC2 */ - FRTIM_IRQn = 28, /* Free-run Timer */ - INCAP_IRQn = 29, /* Input Capture */ - OUTCOMP_IRQn = 30, /* Output Compare */ - BTIM0_7_IRQn = 31, /* Base Timer ch.0 to ch.7 */ - ETHER_MAC0_IRQn = 32, /* Ethernet MAC ch.0 */ - ETHER_MAC1_IRQn = 33, /* Ethernet MAC ch.1 */ - USB0F_IRQn = 34, /* USB Function ch.0 */ - USB0F_USB0H_IRQn = 35, /* USB Function ch.0 / USB Host ch.0 */ - USB1F_IRQn = 36, /* USB Function ch.1 */ - USB1F_USB1H_IRQn = 37, /* USB Function ch.1 / USB Host ch.1 */ - DMAC0_IRQn = 38, /* DMAC ch.0 */ - DMAC1_IRQn = 39, /* DMAC ch.1 */ - DMAC2_IRQn = 40, /* DMAC ch.2 */ - DMAC3_IRQn = 41, /* DMAC ch.3 */ - DMAC4_IRQn = 42, /* DMAC ch.4 */ - DMAC5_IRQn = 43, /* DMAC ch.5 */ - DMAC6_IRQn = 44, /* DMAC ch.6 */ - DMAC7_IRQn = 45, /* DMAC ch.7 */ - BTIM8_15_IRQn = 46 /* Base Timer ch.8 to ch.15 */ - /* Reserved = 47 */ -} IRQn_Type; - - -#include -#include "system_mb9bf61x.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * Peripheral register bit fields - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash_IF_MODULE register bit fields */ -typedef struct stc_flash_if_faszr_field -{ - __IO uint32_t ASZ0 : 1; - __IO uint32_t ASZ1 : 1; -} stc_flash_if_faszr_field_t; - -typedef struct stc_flash_if_frwtr_field -{ - __IO uint32_t RWT0 : 1; - __IO uint32_t RWT1 : 1; -} stc_flash_if_frwtr_field_t; - -typedef struct stc_flash_if_fstr_field -{ - __IO uint32_t RDY : 1; - __IO uint32_t HNG : 1; - __IO uint32_t EER : 1; -} stc_flash_if_fstr_field_t; - -typedef struct stc_flash_if_fsyndn_field -{ - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; -} stc_flash_if_fsyndn_field_t; - -typedef struct stc_flash_if_crtrmm_field -{ - __IO uint32_t TRMM0 : 1; - __IO uint32_t TRMM1 : 1; - __IO uint32_t TRMM2 : 1; - __IO uint32_t TRMM3 : 1; - __IO uint32_t TRMM4 : 1; - __IO uint32_t TRMM5 : 1; - __IO uint32_t TRMM6 : 1; - __IO uint32_t TRMM7 : 1; - __IO uint32_t TRMM8 : 1; - __IO uint32_t TRMM9 : 1; -} stc_flash_if_crtrmm_field_t; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock_Reset_MODULE register bit fields */ -typedef struct stc_crg_scm_ctl_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MOSCE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SOSCE : 1; - __IO uint8_t PLLE : 1; - __IO uint8_t RCS0 : 1; - __IO uint8_t RCS1 : 1; - __IO uint8_t RCS2 : 1; -} stc_crg_scm_ctl_field_t; - -typedef struct stc_crg_scm_str_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MORDY : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SORDY : 1; - __IO uint8_t PLRDY : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t RCM2 : 1; -} stc_crg_scm_str_field_t; - -typedef struct stc_crg_rst_str_field -{ - __IO uint16_t PONR : 1; - __IO uint16_t INITX : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SWDT : 1; - __IO uint16_t HWDT : 1; - __IO uint16_t CSVR : 1; - __IO uint16_t FCSR : 1; - __IO uint16_t SRST : 1; -} stc_crg_rst_str_field_t; - -typedef struct stc_crg_bsc_psr_field -{ - __IO uint8_t BSR0 : 1; - __IO uint8_t BSR1 : 1; - __IO uint8_t BSR2 : 1; -} stc_crg_bsc_psr_field_t; - -typedef struct stc_crg_apbc0_psr_field -{ - __IO uint8_t APBC00 : 1; - __IO uint8_t APBC01 : 1; -} stc_crg_apbc0_psr_field_t; - -typedef struct stc_crg_apbc1_psr_field -{ - __IO uint8_t APBC10 : 1; - __IO uint8_t APBC11 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC1RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC1EN : 1; -} stc_crg_apbc1_psr_field_t; - -typedef struct stc_crg_apbc2_psr_field -{ - __IO uint8_t APBC20 : 1; - __IO uint8_t APBC21 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC2RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC2EN : 1; -} stc_crg_apbc2_psr_field_t; - -typedef struct stc_crg_swc_psr_field -{ - __IO uint8_t SWDS0 : 1; - __IO uint8_t SWDS1 : 1; - uint8_t RESERVED1 : 5; - __IO uint8_t TESTB : 1; -} stc_crg_swc_psr_field_t; - -typedef struct stc_crg_ttc_psr_field -{ - __IO uint8_t TTC0 : 1; - __IO uint8_t TTC1 : 1; -} stc_crg_ttc_psr_field_t; - -typedef struct stc_crg_csw_tmr_field -{ - __IO uint8_t MOWT0 : 1; - __IO uint8_t MOWT1 : 1; - __IO uint8_t MOWT2 : 1; - __IO uint8_t MOWT3 : 1; - __IO uint8_t SOWT0 : 1; - __IO uint8_t SOWT1 : 1; - __IO uint8_t SOWT2 : 1; -} stc_crg_csw_tmr_field_t; - -typedef struct stc_crg_psw_tmr_field -{ - __IO uint8_t POWT0 : 1; - __IO uint8_t POWT1 : 1; - __IO uint8_t POWT2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t PINC : 1; -} stc_crg_psw_tmr_field_t; - -typedef struct stc_crg_pll_ctl1_field -{ - __IO uint8_t PLLM0 : 1; - __IO uint8_t PLLM1 : 1; - __IO uint8_t PLLM2 : 1; - __IO uint8_t PLLM3 : 1; - __IO uint8_t PLLK0 : 1; - __IO uint8_t PLLK1 : 1; - __IO uint8_t PLLK2 : 1; - __IO uint8_t PLLK3 : 1; -} stc_crg_pll_ctl1_field_t; - -typedef struct stc_crg_pll_ctl2_field -{ - __IO uint8_t PLLN0 : 1; - __IO uint8_t PLLN1 : 1; - __IO uint8_t PLLN2 : 1; - __IO uint8_t PLLN3 : 1; - __IO uint8_t PLLN4 : 1; - __IO uint8_t PLLN5 : 1; -} stc_crg_pll_ctl2_field_t; - -typedef struct stc_crg_csv_ctl_field -{ - __IO uint16_t MCSVE : 1; - __IO uint16_t SCSVE : 1; - uint16_t RESERVED1 : 6; - __IO uint16_t FCSDE : 1; - __IO uint16_t FCSRE : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t FCD0 : 1; - __IO uint16_t FCD1 : 1; - __IO uint16_t FCD2 : 1; -} stc_crg_csv_ctl_field_t; - -typedef struct stc_crg_csv_str_field -{ - __IO uint8_t MCMF : 1; - __IO uint8_t SCMF : 1; -} stc_crg_csv_str_field_t; - -typedef struct stc_crg_dbwdt_ctl_field -{ - uint8_t RESERVED1 : 5; - __IO uint8_t DPSWBE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t DPHWBE : 1; -} stc_crg_dbwdt_ctl_field_t; - -typedef struct stc_crg_int_enr_field -{ - __IO uint8_t MCSE : 1; - __IO uint8_t SCSE : 1; - __IO uint8_t PCSE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSE : 1; -} stc_crg_int_enr_field_t; - -typedef struct stc_crg_int_str_field -{ - __IO uint8_t MCSI : 1; - __IO uint8_t SCSI : 1; - __IO uint8_t PCSI : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSI : 1; -} stc_crg_int_str_field_t; - -typedef struct stc_crg_int_clr_field -{ - __IO uint8_t MCSC : 1; - __IO uint8_t SCSC : 1; - __IO uint8_t PCSC : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSC : 1; -} stc_crg_int_clr_field_t; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* HWWDT_MODULE register bit fields */ -typedef struct stc_hwwdt_wdg_ctl_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_hwwdt_wdg_ctl_field_t; - -typedef struct stc_hwwdt_wdg_ris_field -{ - __IO uint8_t RIS : 1; -} stc_hwwdt_wdg_ris_field_t; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* SWWDT_MODULE register bit fields */ -typedef struct stc_swwdt_wdogcontrol_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_swwdt_wdogcontrol_field_t; - -typedef struct stc_swwdt_wdogris_field -{ - __IO uint8_t RIS : 1; -} stc_swwdt_wdogris_field_t; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* DTIM_MODULE register bit fields */ -typedef struct stc_dtim_timer1control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer1control_field_t; - -typedef struct stc_dtim_timer1ris_field -{ - __IO uint32_t TIMER1RIS : 1; -} stc_dtim_timer1ris_field_t; - -typedef struct stc_dtim_timer1mis_field -{ - __IO uint32_t TIMER1MIS : 1; -} stc_dtim_timer1mis_field_t; - -typedef struct stc_dtim_timer2control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer2control_field_t; - -typedef struct stc_dtim_timer2ris_field -{ - __IO uint32_t TIMER2RIS : 1; -} stc_dtim_timer2ris_field_t; - -typedef struct stc_dtim_timer2mis_field -{ - __IO uint32_t TIMER2MIS : 1; -} stc_dtim_timer2mis_field_t; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* MFT_FRT_MODULE register bit fields */ -typedef struct stc_mft_frt_tcsa0_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa0_field_t; - -typedef struct stc_mft_frt_tcsb0_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb0_field_t; - -typedef struct stc_mft_frt_tcsa1_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa1_field_t; - -typedef struct stc_mft_frt_tcsb1_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb1_field_t; - -typedef struct stc_mft_frt_tcsa2_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa2_field_t; - -typedef struct stc_mft_frt_tcsb2_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb2_field_t; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* MFT_OCU_MODULE register bit fields */ -typedef struct stc_mft_ocu_ocsa10_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa10_field_t; - -typedef struct stc_mft_ocu_ocsb10_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; -} stc_mft_ocu_ocsb10_field_t; - -typedef struct stc_mft_ocu_ocsa32_field -{ - __IO uint8_t CST2 : 1; - __IO uint8_t CST3 : 1; - __IO uint8_t BDIS2 : 1; - __IO uint8_t BDIS3 : 1; - __IO uint8_t IOE2 : 1; - __IO uint8_t IOE3 : 1; - __IO uint8_t IOP2 : 1; - __IO uint8_t IOP3 : 1; -} stc_mft_ocu_ocsa32_field_t; - -typedef struct stc_mft_ocu_ocsb32_field -{ - __IO uint8_t OTD2 : 1; - __IO uint8_t OTD3 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS2 : 1; - __IO uint8_t BTS3 : 1; -} stc_mft_ocu_ocsb32_field_t; - -typedef struct stc_mft_ocu_ocsa54_field -{ - __IO uint8_t CST4 : 1; - __IO uint8_t CST5 : 1; - __IO uint8_t BDIS4 : 1; - __IO uint8_t BDIS5 : 1; - __IO uint8_t IOE4 : 1; - __IO uint8_t IOE5 : 1; - __IO uint8_t IOP4 : 1; - __IO uint8_t IOP5 : 1; -} stc_mft_ocu_ocsa54_field_t; - -typedef struct stc_mft_ocu_ocsb54_field -{ - __IO uint8_t OTD4 : 1; - __IO uint8_t OTD5 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS4 : 1; - __IO uint8_t BTS5 : 1; -} stc_mft_ocu_ocsb54_field_t; - -typedef struct stc_mft_ocu_ocsc_field -{ - __IO uint8_t MOD0 : 1; - __IO uint8_t MOD1 : 1; - __IO uint8_t MOD2 : 1; - __IO uint8_t MOD3 : 1; - __IO uint8_t MOD4 : 1; - __IO uint8_t MOD5 : 1; -} stc_mft_ocu_ocsc_field_t; - -typedef struct stc_mft_ocu_ocfs10_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs10_field_t; - -typedef struct stc_mft_ocu_ocfs32_field -{ - __IO uint8_t FSO20 : 1; - __IO uint8_t FSO21 : 1; - __IO uint8_t FSO22 : 1; - __IO uint8_t FSO23 : 1; - __IO uint8_t FSO30 : 1; - __IO uint8_t FSO31 : 1; - __IO uint8_t FSO32 : 1; - __IO uint8_t FSO33 : 1; -} stc_mft_ocu_ocfs32_field_t; - -typedef struct stc_mft_ocu_ocfs54_field -{ - __IO uint8_t FSO40 : 1; - __IO uint8_t FSO41 : 1; - __IO uint8_t FSO42 : 1; - __IO uint8_t FSO43 : 1; - __IO uint8_t FSO50 : 1; - __IO uint8_t FSO51 : 1; - __IO uint8_t FSO52 : 1; - __IO uint8_t FSO53 : 1; -} stc_mft_ocu_ocfs54_field_t; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* MFT_WFG_MODULE register bit fields */ -typedef struct stc_mft_wfg_wfsa10_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa10_field_t; - -typedef struct stc_mft_wfg_wfsa32_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa32_field_t; - -typedef struct stc_mft_wfg_wfsa54_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD0 : 1; - __IO uint16_t TMD1 : 1; - __IO uint16_t TMD2 : 1; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa54_field_t; - -typedef struct stc_mft_wfg_wfir_field -{ - __IO uint16_t DTIF : 1; - __IO uint16_t DTIC : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t TMIF10 : 1; - __IO uint16_t TMIC10 : 1; - __IO uint16_t TMIE10 : 1; - __IO uint16_t TMIS10 : 1; - __IO uint16_t TMIF32 : 1; - __IO uint16_t TMIC32 : 1; - __IO uint16_t TMIE32 : 1; - __IO uint16_t TMIS32 : 1; - __IO uint16_t TMIF54 : 1; - __IO uint16_t TMIC54 : 1; - __IO uint16_t TMIE54 : 1; - __IO uint16_t TMIS54 : 1; -} stc_mft_wfg_wfir_field_t; - -typedef struct stc_mft_wfg_nzcl_field -{ - __IO uint16_t DTIE : 1; - __IO uint16_t NWS0 : 1; - __IO uint16_t NWS1 : 1; - __IO uint16_t NWS2 : 1; - __IO uint16_t SDTI : 1; -} stc_mft_wfg_nzcl_field_t; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* MFT_ICU_MODULE register bit fields */ -typedef struct stc_mft_icu_icfs10_field -{ - __IO uint8_t FSI00 : 1; - __IO uint8_t FSI01 : 1; - __IO uint8_t FSI02 : 1; - __IO uint8_t FSI03 : 1; - __IO uint8_t FSI10 : 1; - __IO uint8_t FSI11 : 1; - __IO uint8_t FSI12 : 1; - __IO uint8_t FSI13 : 1; -} stc_mft_icu_icfs10_field_t; - -typedef struct stc_mft_icu_icfs32_field -{ - __IO uint8_t FSI20 : 1; - __IO uint8_t FSI21 : 1; - __IO uint8_t FSI22 : 1; - __IO uint8_t FSI23 : 1; - __IO uint8_t FSI30 : 1; - __IO uint8_t FSI31 : 1; - __IO uint8_t FSI32 : 1; - __IO uint8_t FSI33 : 1; -} stc_mft_icu_icfs32_field_t; - -typedef struct stc_mft_icu_icsa10_field -{ - __IO uint8_t EG00 : 1; - __IO uint8_t EG01 : 1; - __IO uint8_t EG10 : 1; - __IO uint8_t EG11 : 1; - __IO uint8_t ICE0 : 1; - __IO uint8_t ICE1 : 1; - __IO uint8_t ICP0 : 1; - __IO uint8_t ICP1 : 1; -} stc_mft_icu_icsa10_field_t; - -typedef struct stc_mft_icu_icsb10_field -{ - __IO uint8_t IEI0 : 1; - __IO uint8_t IEI1 : 1; -} stc_mft_icu_icsb10_field_t; - -typedef struct stc_mft_icu_icsa32_field -{ - __IO uint8_t EG20 : 1; - __IO uint8_t EG21 : 1; - __IO uint8_t EG30 : 1; - __IO uint8_t EG31 : 1; - __IO uint8_t ICE2 : 1; - __IO uint8_t ICE3 : 1; - __IO uint8_t ICP2 : 1; - __IO uint8_t ICP3 : 1; -} stc_mft_icu_icsa32_field_t; - -typedef struct stc_mft_icu_icsb32_field -{ - __IO uint8_t IEI2 : 1; - __IO uint8_t IEI3 : 1; -} stc_mft_icu_icsb32_field_t; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* MFT_ADCMP_MODULE register bit fields */ -typedef struct stc_mft_adcmp_acsb_field -{ - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t BDIS2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; - __IO uint8_t BTS2 : 1; -} stc_mft_adcmp_acsb_field_t; - -typedef struct stc_mft_adcmp_acsa_field -{ - __IO uint16_t CE00 : 1; - __IO uint16_t CE01 : 1; - __IO uint16_t CE10 : 1; - __IO uint16_t CE11 : 1; - __IO uint16_t CE20 : 1; - __IO uint16_t CE21 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SEL00 : 1; - __IO uint16_t SEL01 : 1; - __IO uint16_t SEL10 : 1; - __IO uint16_t SEL11 : 1; - __IO uint16_t SEL20 : 1; - __IO uint16_t SEL21 : 1; -} stc_mft_adcmp_acsa_field_t; - -typedef struct stc_mft_adcmp_atsa_field -{ - __IO uint16_t AD0S0 : 1; - __IO uint16_t AD0S1 : 1; - __IO uint16_t AD1S0 : 1; - __IO uint16_t AD1S1 : 1; - __IO uint16_t AD2S0 : 1; - __IO uint16_t AD2S1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t AD0P0 : 1; - __IO uint16_t AD0P1 : 1; - __IO uint16_t AD1P0 : 1; - __IO uint16_t AD1P1 : 1; - __IO uint16_t AD2P0 : 1; - __IO uint16_t AD2P1 : 1; -} stc_mft_adcmp_atsa_field_t; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* MFT_PPG_MODULE register bit fields */ -typedef struct stc_mft_ppg_ttcr0_field -{ - __IO uint8_t STR0 : 1; - __IO uint8_t MONI0 : 1; - __IO uint8_t CS00 : 1; - __IO uint8_t CS01 : 1; - __IO uint8_t TRG0O : 1; - __IO uint8_t TRG2O : 1; - __IO uint8_t TRG4O : 1; - __IO uint8_t TRG6O : 1; -} stc_mft_ppg_ttcr0_field_t; - -typedef struct stc_mft_ppg_ttcr1_field -{ - __IO uint8_t STR1 : 1; - __IO uint8_t MONI1 : 1; - __IO uint8_t CS10 : 1; - __IO uint8_t CS11 : 1; - __IO uint8_t TRG1O : 1; - __IO uint8_t TRG3O : 1; - __IO uint8_t TRG5O : 1; - __IO uint8_t TRG7O : 1; -} stc_mft_ppg_ttcr1_field_t; - -typedef struct stc_mft_ppg_ttcr2_field -{ - __IO uint8_t STR2 : 1; - __IO uint8_t MONI2 : 1; - __IO uint8_t CS20 : 1; - __IO uint8_t CS21 : 1; - __IO uint8_t TRG16O : 1; - __IO uint8_t TRG18O : 1; - __IO uint8_t TRG20O : 1; - __IO uint8_t TRG22O : 1; -} stc_mft_ppg_ttcr2_field_t; - -typedef struct stc_mft_ppg_trg_field -{ - __IO uint16_t PEN00 : 1; - __IO uint16_t PEN01 : 1; - __IO uint16_t PEN02 : 1; - __IO uint16_t PEN03 : 1; - __IO uint16_t PEN04 : 1; - __IO uint16_t PEN05 : 1; - __IO uint16_t PEN06 : 1; - __IO uint16_t PEN07 : 1; - __IO uint16_t PEN08 : 1; - __IO uint16_t PEN09 : 1; - __IO uint16_t PEN10 : 1; - __IO uint16_t PEN11 : 1; - __IO uint16_t PEN12 : 1; - __IO uint16_t PEN13 : 1; - __IO uint16_t PEN14 : 1; - __IO uint16_t PEN15 : 1; -} stc_mft_ppg_trg_field_t; - -typedef struct stc_mft_ppg_trg1_field -{ - __IO uint16_t PEN16 : 1; - __IO uint16_t PEN17 : 1; - __IO uint16_t PEN18 : 1; - __IO uint16_t PEN19 : 1; - __IO uint16_t PEN20 : 1; - __IO uint16_t PEN21 : 1; - __IO uint16_t PEN22 : 1; - __IO uint16_t PEN23 : 1; -} stc_mft_ppg_trg1_field_t; - -typedef struct stc_mft_ppg_revc_field -{ - __IO uint16_t REV00 : 1; - __IO uint16_t REV01 : 1; - __IO uint16_t REV02 : 1; - __IO uint16_t REV03 : 1; - __IO uint16_t REV04 : 1; - __IO uint16_t REV05 : 1; - __IO uint16_t REV06 : 1; - __IO uint16_t REV07 : 1; - __IO uint16_t REV08 : 1; - __IO uint16_t REV09 : 1; - __IO uint16_t REV10 : 1; - __IO uint16_t REV11 : 1; - __IO uint16_t REV12 : 1; - __IO uint16_t REV13 : 1; - __IO uint16_t REV14 : 1; - __IO uint16_t REV15 : 1; -} stc_mft_ppg_revc_field_t; - -typedef struct stc_mft_ppg_revc1_field -{ - __IO uint16_t REV16 : 1; - __IO uint16_t REV17 : 1; - __IO uint16_t REV18 : 1; - __IO uint16_t REV19 : 1; - __IO uint16_t REV20 : 1; - __IO uint16_t REV21 : 1; - __IO uint16_t REV22 : 1; - __IO uint16_t REV23 : 1; -} stc_mft_ppg_revc1_field_t; - -typedef struct stc_mft_ppg_ppgc1_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc1_field_t; - -typedef struct stc_mft_ppg_ppgc0_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc0_field_t; - -typedef struct stc_mft_ppg_ppgc3_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc3_field_t; - -typedef struct stc_mft_ppg_ppgc2_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc2_field_t; - -typedef struct stc_mft_ppg_gatec0_field -{ - __IO uint8_t EDGE0 : 1; - __IO uint8_t STRG0 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE2 : 1; - __IO uint8_t STRG2 : 1; -} stc_mft_ppg_gatec0_field_t; - -typedef struct stc_mft_ppg_ppgc5_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc5_field_t; - -typedef struct stc_mft_ppg_ppgc4_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc4_field_t; - -typedef struct stc_mft_ppg_ppgc7_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc7_field_t; - -typedef struct stc_mft_ppg_ppgc6_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc6_field_t; - -typedef struct stc_mft_ppg_gatec4_field -{ - __IO uint8_t EDGE4 : 1; - __IO uint8_t STRG4 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE6 : 1; - __IO uint8_t STRG6 : 1; -} stc_mft_ppg_gatec4_field_t; - -typedef struct stc_mft_ppg_ppgc9_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc9_field_t; - -typedef struct stc_mft_ppg_ppgc8_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc8_field_t; - -typedef struct stc_mft_ppg_ppgc11_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc11_field_t; - -typedef struct stc_mft_ppg_ppgc10_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc10_field_t; - -typedef struct stc_mft_ppg_gatec8_field -{ - __IO uint8_t EDGE8 : 1; - __IO uint8_t STRG8 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE10 : 1; - __IO uint8_t STRG10 : 1; -} stc_mft_ppg_gatec8_field_t; - -typedef struct stc_mft_ppg_ppgc13_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc13_field_t; - -typedef struct stc_mft_ppg_ppgc12_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc12_field_t; - -typedef struct stc_mft_ppg_ppgc15_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc15_field_t; - -typedef struct stc_mft_ppg_ppgc14_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc14_field_t; - -typedef struct stc_mft_ppg_gatec12_field -{ - __IO uint8_t EDGE12 : 1; - __IO uint8_t STRG12 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE14 : 1; - __IO uint8_t STRG14 : 1; -} stc_mft_ppg_gatec12_field_t; - -typedef struct stc_mft_ppg_ppgc17_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc17_field_t; - -typedef struct stc_mft_ppg_ppgc16_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc16_field_t; - -typedef struct stc_mft_ppg_ppgc19_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc19_field_t; - -typedef struct stc_mft_ppg_ppgc18_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc18_field_t; - -typedef struct stc_mft_ppg_gatec16_field -{ - __IO uint8_t EDGE16 : 1; - __IO uint8_t STRG16 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE18 : 1; - __IO uint8_t STRG18 : 1; -} stc_mft_ppg_gatec16_field_t; - -typedef struct stc_mft_ppg_ppgc21_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc21_field_t; - -typedef struct stc_mft_ppg_ppgc20_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc20_field_t; - -typedef struct stc_mft_ppg_ppgc23_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc23_field_t; - -typedef struct stc_mft_ppg_ppgc22_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc22_field_t; - -typedef struct stc_mft_ppg_gatec20_field -{ - __IO uint8_t EDGE20 : 1; - __IO uint8_t STRG20 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE22 : 1; - __IO uint8_t STRG22 : 1; -} stc_mft_ppg_gatec20_field_t; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* BT_PPG_MODULE register bit fields */ -typedef struct stc_bt_ppg_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_ppg_tmcr_field_t; - -typedef struct stc_bt_ppg_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_ppg_stc_field_t; - -typedef struct stc_bt_ppg_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_ppg_tmcr2_field_t; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* BT_PWM_MODULE register bit fields */ -typedef struct stc_bt_pwm_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwm_tmcr_field_t; - -typedef struct stc_bt_pwm_stc_field -{ - __IO uint8_t UDIR : 1; - __IO uint8_t DTIR : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t UDIE : 1; - __IO uint8_t DTIE : 1; - __IO uint8_t TGIE : 1; -} stc_bt_pwm_stc_field_t; - -typedef struct stc_bt_pwm_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwm_tmcr2_field_t; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* BT_RT_MODULE register bit fields */ -typedef struct stc_bt_rt_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_rt_tmcr_field_t; - -typedef struct stc_bt_rt_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_rt_stc_field_t; - -typedef struct stc_bt_rt_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_rt_tmcr2_field_t; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* BT_PWC_MODULE register bit fields */ -typedef struct stc_bt_pwc_tmcr_field -{ - uint16_t RESERVED1 : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FMD0 : 1; - __IO uint16_t FMD1 : 1; - __IO uint16_t FMD2 : 1; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t EGS2 : 1; - uint16_t RESERVED3 : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwc_tmcr_field_t; - -typedef struct stc_bt_pwc_stc_field -{ - __IO uint8_t OVIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t EDIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t OVIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t EDIE : 1; - __IO uint8_t ERR : 1; -} stc_bt_pwc_stc_field_t; - -typedef struct stc_bt_pwc_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwc_tmcr2_field_t; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* BTIOSEL03_MODULE register bit fields */ -typedef struct stc_btiosel03_btsel0123_field -{ - __IO uint8_t SEL01_0 : 1; - __IO uint8_t SEL01_1 : 1; - __IO uint8_t SEL01_2 : 1; - __IO uint8_t SEL01_3 : 1; - __IO uint8_t SEL23_0 : 1; - __IO uint8_t SEL23_1 : 1; - __IO uint8_t SEL23_2 : 1; - __IO uint8_t SEL23_3 : 1; -} stc_btiosel03_btsel0123_field_t; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* BTIOSEL47_MODULE register bit fields */ -typedef struct stc_btiosel47_btsel4567_field -{ - __IO uint8_t SEL45_0 : 1; - __IO uint8_t SEL45_1 : 1; - __IO uint8_t SEL45_2 : 1; - __IO uint8_t SEL45_3 : 1; - __IO uint8_t SEL67_0 : 1; - __IO uint8_t SEL67_1 : 1; - __IO uint8_t SEL67_2 : 1; - __IO uint8_t SEL67_3 : 1; -} stc_btiosel47_btsel4567_field_t; - -/****************************************************************************** - * BTIOSEL811_MODULE - ******************************************************************************/ -/* BTIOSEL811_MODULE register bit fields */ -typedef struct stc_btiosel8b_btsel89ab_field -{ - __IO uint8_t SEL89_0 : 1; - __IO uint8_t SEL89_1 : 1; - __IO uint8_t SEL89_2 : 1; - __IO uint8_t SEL89_3 : 1; - __IO uint8_t SELAB_0 : 1; - __IO uint8_t SELAB_1 : 1; - __IO uint8_t SELAB_2 : 1; - __IO uint8_t SELAB_3 : 1; -} stc_btiosel8b_btsel89ab_field_t; - -/****************************************************************************** - * BTIOSEL1215_MODULE - ******************************************************************************/ -/* BTIOSEL1215_MODULE register bit fields */ -typedef struct stc_btioselcf_btselcdef_field -{ - __IO uint8_t SELCD_0 : 1; - __IO uint8_t SELCD_1 : 1; - __IO uint8_t SELCD_2 : 1; - __IO uint8_t SELCD_3 : 1; - __IO uint8_t SELEF_0 : 1; - __IO uint8_t SELEF_1 : 1; - __IO uint8_t SELEF_2 : 1; - __IO uint8_t SELEF_3 : 1; -} stc_btioselcf_btselcdef_field_t; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* SBSSR_MODULE register bit fields */ -typedef struct stc_sbssr_btsssr_field -{ - __IO uint16_t SSR0 : 1; - __IO uint16_t SSR1 : 1; - __IO uint16_t SSR2 : 1; - __IO uint16_t SSR3 : 1; - __IO uint16_t SSR4 : 1; - __IO uint16_t SSR5 : 1; - __IO uint16_t SSR6 : 1; - __IO uint16_t SSR7 : 1; - __IO uint16_t SSR8 : 1; - __IO uint16_t SSR9 : 1; - __IO uint16_t SSR10 : 1; - __IO uint16_t SSR11 : 1; - __IO uint16_t SSR12 : 1; - __IO uint16_t SSR13 : 1; - __IO uint16_t SSR14 : 1; - __IO uint16_t SSR15 : 1; -} stc_sbssr_btsssr_field_t; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* QPRC_MODULE register bit fields */ -typedef struct stc_qprc_qicr_field -{ - __IO uint16_t QPCMIE : 1; - __IO uint16_t QPCMF : 1; - __IO uint16_t QPRCMIE : 1; - __IO uint16_t QPRCMF : 1; - __IO uint16_t OUZIE : 1; - __IO uint16_t UFDF : 1; - __IO uint16_t OFDF : 1; - __IO uint16_t ZIIF : 1; - __IO uint16_t CDCIE : 1; - __IO uint16_t CDCF : 1; - __IO uint16_t DIRPC : 1; - __IO uint16_t DIROU : 1; - __IO uint16_t QPCNRCMIE : 1; - __IO uint16_t QPCNRCMF : 1; -} stc_qprc_qicr_field_t; - -typedef struct stc_qprc_qicrl_field -{ - __IO uint8_t QPCMIE : 1; - __IO uint8_t QPCMF : 1; - __IO uint8_t QPRCMIE : 1; - __IO uint8_t QPRCMF : 1; - __IO uint8_t OUZIE : 1; - __IO uint8_t UFDF : 1; - __IO uint8_t OFDF : 1; - __IO uint8_t ZIIF : 1; -} stc_qprc_qicrl_field_t; - -typedef struct stc_qprc_qicrh_field -{ - __IO uint8_t CDCIE : 1; - __IO uint8_t CDCF : 1; - __IO uint8_t DIRPC : 1; - __IO uint8_t DIROU : 1; - __IO uint8_t QPCNRCMIE : 1; - __IO uint8_t QPCNRCMF : 1; -} stc_qprc_qicrh_field_t; - -typedef struct stc_qprc_qcr_field -{ - __IO uint16_t PCM0 : 1; - __IO uint16_t PCM1 : 1; - __IO uint16_t RCM0 : 1; - __IO uint16_t RCM1 : 1; - __IO uint16_t PSTP : 1; - __IO uint16_t CGSC : 1; - __IO uint16_t RSEL : 1; - __IO uint16_t SWAP : 1; - __IO uint16_t PCRM0 : 1; - __IO uint16_t PCRM1 : 1; - __IO uint16_t AES0 : 1; - __IO uint16_t AES1 : 1; - __IO uint16_t BES0 : 1; - __IO uint16_t BES1 : 1; - __IO uint16_t CGE0 : 1; - __IO uint16_t CGE1 : 1; -} stc_qprc_qcr_field_t; - -typedef struct stc_qprc_qcrl_field -{ - __IO uint8_t PCM0 : 1; - __IO uint8_t PCM1 : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t PSTP : 1; - __IO uint8_t CGSC : 1; - __IO uint8_t RSEL : 1; - __IO uint8_t SWAP : 1; -} stc_qprc_qcrl_field_t; - -typedef struct stc_qprc_qcrh_field -{ - __IO uint8_t PCRM0 : 1; - __IO uint8_t PCRM1 : 1; - __IO uint8_t AES0 : 1; - __IO uint8_t AES1 : 1; - __IO uint8_t BES0 : 1; - __IO uint8_t BES1 : 1; - __IO uint8_t CGE0 : 1; - __IO uint8_t CGE1 : 1; -} stc_qprc_qcrh_field_t; - -typedef struct stc_qprc_qecr_field -{ - __IO uint16_t ORNGMD : 1; - __IO uint16_t ORNGF : 1; - __IO uint16_t ORNGIE : 1; -} stc_qprc_qecr_field_t; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* ADC12_MODULE register bit fields */ -typedef struct stc_adc_adsr_field -{ - __IO uint8_t SCS : 1; - __IO uint8_t PCS : 1; - __IO uint8_t PCNS : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t FDAS : 1; - __IO uint8_t ADSTP : 1; -} stc_adc_adsr_field_t; - -typedef struct stc_adc_adcr_field -{ - __IO uint8_t OVRIE : 1; - __IO uint8_t CMPIE : 1; - __IO uint8_t PCIE : 1; - __IO uint8_t SCIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t CMPIF : 1; - __IO uint8_t PCIF : 1; - __IO uint8_t SCIF : 1; -} stc_adc_adcr_field_t; - -typedef struct stc_adc_sfns_field -{ - __IO uint8_t SFS0 : 1; - __IO uint8_t SFS1 : 1; - __IO uint8_t SFS2 : 1; - __IO uint8_t SFS3 : 1; -} stc_adc_sfns_field_t; - -typedef struct stc_adc_sccr_field -{ - __IO uint8_t SSTR : 1; - __IO uint8_t SHEN : 1; - __IO uint8_t RPT : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t SFCLR : 1; - __IO uint8_t SOVR : 1; - __IO uint8_t SFUL : 1; - __IO uint8_t SEMP : 1; -} stc_adc_sccr_field_t; - -typedef struct stc_adc_scfd_field -{ - __IO uint32_t SC0 : 1; - __IO uint32_t SC1 : 1; - __IO uint32_t SC2 : 1; - __IO uint32_t SC3 : 1; - __IO uint32_t SC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; - __IO uint32_t SD3 : 1; - __IO uint32_t SD4 : 1; - __IO uint32_t SD5 : 1; - __IO uint32_t SD6 : 1; - __IO uint32_t SD7 : 1; - __IO uint32_t SD8 : 1; - __IO uint32_t SD9 : 1; - __IO uint32_t SD10 : 1; - __IO uint32_t SD11 : 1; -} stc_adc_scfd_field_t; - -typedef struct stc_adc_scfdl_field -{ - __IO uint16_t SC0 : 1; - __IO uint16_t SC1 : 1; - __IO uint16_t SC2 : 1; - __IO uint16_t SC3 : 1; - __IO uint16_t SC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t INVL : 1; -} stc_adc_scfdl_field_t; - -typedef struct stc_adc_scfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t SD0 : 1; - __IO uint16_t SD1 : 1; - __IO uint16_t SD2 : 1; - __IO uint16_t SD3 : 1; - __IO uint16_t SD4 : 1; - __IO uint16_t SD5 : 1; - __IO uint16_t SD6 : 1; - __IO uint16_t SD7 : 1; - __IO uint16_t SD8 : 1; - __IO uint16_t SD9 : 1; - __IO uint16_t SD10 : 1; - __IO uint16_t SD11 : 1; -} stc_adc_scfdh_field_t; - -typedef struct stc_adc_scis23_field -{ - __IO uint16_t AN16 : 1; - __IO uint16_t AN17 : 1; - __IO uint16_t AN18 : 1; - __IO uint16_t AN19 : 1; - __IO uint16_t AN20 : 1; - __IO uint16_t AN21 : 1; - __IO uint16_t AN22 : 1; - __IO uint16_t AN23 : 1; - __IO uint16_t AN24 : 1; - __IO uint16_t AN25 : 1; - __IO uint16_t AN26 : 1; - __IO uint16_t AN27 : 1; - __IO uint16_t AN28 : 1; - __IO uint16_t AN29 : 1; - __IO uint16_t AN30 : 1; - __IO uint16_t AN31 : 1; -} stc_adc_scis23_field_t; - -typedef struct stc_adc_scis2_field -{ - __IO uint8_t AN16 : 1; - __IO uint8_t AN17 : 1; - __IO uint8_t AN18 : 1; - __IO uint8_t AN19 : 1; - __IO uint8_t AN20 : 1; - __IO uint8_t AN21 : 1; - __IO uint8_t AN22 : 1; - __IO uint8_t AN23 : 1; -} stc_adc_scis2_field_t; - -typedef struct stc_adc_scis3_field -{ - __IO uint8_t AN24 : 1; - __IO uint8_t AN25 : 1; - __IO uint8_t AN26 : 1; - __IO uint8_t AN27 : 1; - __IO uint8_t AN28 : 1; - __IO uint8_t AN29 : 1; - __IO uint8_t AN30 : 1; - __IO uint8_t AN31 : 1; -} stc_adc_scis3_field_t; - -typedef struct stc_adc_scis01_field -{ - __IO uint16_t AN0 : 1; - __IO uint16_t AN1 : 1; - __IO uint16_t AN2 : 1; - __IO uint16_t AN3 : 1; - __IO uint16_t AN4 : 1; - __IO uint16_t AN5 : 1; - __IO uint16_t AN6 : 1; - __IO uint16_t AN7 : 1; - __IO uint16_t AN8 : 1; - __IO uint16_t AN9 : 1; - __IO uint16_t AN10 : 1; - __IO uint16_t AN11 : 1; - __IO uint16_t AN12 : 1; - __IO uint16_t AN13 : 1; - __IO uint16_t AN14 : 1; - __IO uint16_t AN15 : 1; -} stc_adc_scis01_field_t; - -typedef struct stc_adc_scis0_field -{ - __IO uint8_t AN0 : 1; - __IO uint8_t AN1 : 1; - __IO uint8_t AN2 : 1; - __IO uint8_t AN3 : 1; - __IO uint8_t AN4 : 1; - __IO uint8_t AN5 : 1; - __IO uint8_t AN6 : 1; - __IO uint8_t AN7 : 1; -} stc_adc_scis0_field_t; - -typedef struct stc_adc_scis1_field -{ - __IO uint8_t AN8 : 1; - __IO uint8_t AN9 : 1; - __IO uint8_t AN10 : 1; - __IO uint8_t AN11 : 1; - __IO uint8_t AN12 : 1; - __IO uint8_t AN13 : 1; - __IO uint8_t AN14 : 1; - __IO uint8_t AN15 : 1; -} stc_adc_scis1_field_t; - -typedef struct stc_adc_pfns_field -{ - __IO uint8_t PFS0 : 1; - __IO uint8_t PFS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t TEST0 : 1; - __IO uint8_t TEST1 : 1; -} stc_adc_pfns_field_t; - -typedef struct stc_adc_pccr_field -{ - __IO uint8_t PSTR : 1; - __IO uint8_t PHEN : 1; - __IO uint8_t PEEN : 1; - __IO uint8_t ESCE : 1; - __IO uint8_t PFCLR : 1; - __IO uint8_t POVR : 1; - __IO uint8_t PFUL : 1; - __IO uint8_t PEMP : 1; -} stc_adc_pccr_field_t; - -typedef struct stc_adc_pcfd_field -{ - __IO uint32_t PC0 : 1; - __IO uint32_t PC1 : 1; - __IO uint32_t PC2 : 1; - __IO uint32_t PC3 : 1; - __IO uint32_t PC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t PD0 : 1; - __IO uint32_t PD1 : 1; - __IO uint32_t PD2 : 1; - __IO uint32_t PD3 : 1; - __IO uint32_t PD4 : 1; - __IO uint32_t PD5 : 1; - __IO uint32_t PD6 : 1; - __IO uint32_t PD7 : 1; - __IO uint32_t PD8 : 1; - __IO uint32_t PD9 : 1; - __IO uint32_t PD10 : 1; - __IO uint32_t PD11 : 1; -} stc_adc_pcfd_field_t; - -typedef struct stc_adc_pcfdl_field -{ - __IO uint16_t PC0 : 1; - __IO uint16_t PC1 : 1; - __IO uint16_t PC2 : 1; - __IO uint16_t PC3 : 1; - __IO uint16_t PC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - __IO uint16_t RS2 : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t INVL : 1; -} stc_adc_pcfdl_field_t; - -typedef struct stc_adc_pcfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t PD0 : 1; - __IO uint16_t PD1 : 1; - __IO uint16_t PD2 : 1; - __IO uint16_t PD3 : 1; - __IO uint16_t PD4 : 1; - __IO uint16_t PD5 : 1; - __IO uint16_t PD6 : 1; - __IO uint16_t PD7 : 1; - __IO uint16_t PD8 : 1; - __IO uint16_t PD9 : 1; - __IO uint16_t PD10 : 1; - __IO uint16_t PD11 : 1; -} stc_adc_pcfdh_field_t; - -typedef struct stc_adc_pcis_field -{ - __IO uint8_t P1A0 : 1; - __IO uint8_t P1A1 : 1; - __IO uint8_t P1A2 : 1; - __IO uint8_t P2A0 : 1; - __IO uint8_t P2A1 : 1; - __IO uint8_t P2A2 : 1; - __IO uint8_t P2A3 : 1; - __IO uint8_t P2A4 : 1; -} stc_adc_pcis_field_t; - -typedef struct stc_adc_cmpcr_field -{ - __IO uint8_t CCH0 : 1; - __IO uint8_t CCH1 : 1; - __IO uint8_t CCH2 : 1; - __IO uint8_t CCH3 : 1; - __IO uint8_t CCH4 : 1; - __IO uint8_t CMD0 : 1; - __IO uint8_t CMD1 : 1; - __IO uint8_t CMPEN : 1; -} stc_adc_cmpcr_field_t; - -typedef struct stc_adc_cmpd_field -{ - uint16_t RESERVED1 : 6; - __IO uint16_t CMAD2 : 1; - __IO uint16_t CMAD3 : 1; - __IO uint16_t CMAD4 : 1; - __IO uint16_t CMAD5 : 1; - __IO uint16_t CMAD6 : 1; - __IO uint16_t CMAD7 : 1; - __IO uint16_t CMAD8 : 1; - __IO uint16_t CMAD9 : 1; - __IO uint16_t CMAD10 : 1; - __IO uint16_t CMAD11 : 1; -} stc_adc_cmpd_field_t; - -typedef struct stc_adc_adss23_field -{ - __IO uint16_t TS16 : 1; - __IO uint16_t TS17 : 1; - __IO uint16_t TS18 : 1; - __IO uint16_t TS19 : 1; - __IO uint16_t TS20 : 1; - __IO uint16_t TS21 : 1; - __IO uint16_t TS22 : 1; - __IO uint16_t TS23 : 1; - __IO uint16_t TS24 : 1; - __IO uint16_t TS25 : 1; - __IO uint16_t TS26 : 1; - __IO uint16_t TS27 : 1; - __IO uint16_t TS28 : 1; - __IO uint16_t TS29 : 1; - __IO uint16_t TS30 : 1; - __IO uint16_t TS31 : 1; -} stc_adc_adss23_field_t; - -typedef struct stc_adc_adss2_field -{ - __IO uint8_t TS16 : 1; - __IO uint8_t TS17 : 1; - __IO uint8_t TS18 : 1; - __IO uint8_t TS19 : 1; - __IO uint8_t TS20 : 1; - __IO uint8_t TS21 : 1; - __IO uint8_t TS22 : 1; - __IO uint8_t TS23 : 1; -} stc_adc_adss2_field_t; - -typedef struct stc_adc_adss3_field -{ - __IO uint8_t TS24 : 1; - __IO uint8_t TS25 : 1; - __IO uint8_t TS26 : 1; - __IO uint8_t TS27 : 1; - __IO uint8_t TS28 : 1; - __IO uint8_t TS29 : 1; - __IO uint8_t TS30 : 1; - __IO uint8_t TS31 : 1; -} stc_adc_adss3_field_t; - -typedef struct stc_adc_adss01_field -{ - __IO uint16_t TS0 : 1; - __IO uint16_t TS1 : 1; - __IO uint16_t TS2 : 1; - __IO uint16_t TS3 : 1; - __IO uint16_t TS4 : 1; - __IO uint16_t TS5 : 1; - __IO uint16_t TS6 : 1; - __IO uint16_t TS7 : 1; - __IO uint16_t TS8 : 1; - __IO uint16_t TS9 : 1; - __IO uint16_t TS10 : 1; - __IO uint16_t TS11 : 1; - __IO uint16_t TS12 : 1; - __IO uint16_t TS13 : 1; - __IO uint16_t TS14 : 1; - __IO uint16_t TS15 : 1; -} stc_adc_adss01_field_t; - -typedef struct stc_adc_adss0_field -{ - __IO uint8_t TS0 : 1; - __IO uint8_t TS1 : 1; - __IO uint8_t TS2 : 1; - __IO uint8_t TS3 : 1; - __IO uint8_t TS4 : 1; - __IO uint8_t TS5 : 1; - __IO uint8_t TS6 : 1; - __IO uint8_t TS7 : 1; -} stc_adc_adss0_field_t; - -typedef struct stc_adc_adss1_field -{ - __IO uint8_t TS8 : 1; - __IO uint8_t TS9 : 1; - __IO uint8_t TS10 : 1; - __IO uint8_t TS11 : 1; - __IO uint8_t TS12 : 1; - __IO uint8_t TS13 : 1; - __IO uint8_t TS14 : 1; - __IO uint8_t TS15 : 1; -} stc_adc_adss1_field_t; - -typedef struct stc_adc_adst01_field -{ - __IO uint16_t ST10 : 1; - __IO uint16_t ST11 : 1; - __IO uint16_t ST12 : 1; - __IO uint16_t ST13 : 1; - __IO uint16_t ST14 : 1; - __IO uint16_t STX10 : 1; - __IO uint16_t STX11 : 1; - __IO uint16_t STX12 : 1; - __IO uint16_t ST00 : 1; - __IO uint16_t ST01 : 1; - __IO uint16_t ST02 : 1; - __IO uint16_t ST03 : 1; - __IO uint16_t ST04 : 1; - __IO uint16_t STX00 : 1; - __IO uint16_t STX01 : 1; - __IO uint16_t STX02 : 1; -} stc_adc_adst01_field_t; - -typedef struct stc_adc_adst1_field -{ - __IO uint8_t ST10 : 1; - __IO uint8_t ST11 : 1; - __IO uint8_t ST12 : 1; - __IO uint8_t ST13 : 1; - __IO uint8_t ST14 : 1; - __IO uint8_t STX10 : 1; - __IO uint8_t STX11 : 1; - __IO uint8_t STX12 : 1; -} stc_adc_adst1_field_t; - -typedef struct stc_adc_adst0_field -{ - __IO uint8_t ST00 : 1; - __IO uint8_t ST01 : 1; - __IO uint8_t ST02 : 1; - __IO uint8_t ST03 : 1; - __IO uint8_t ST04 : 1; - __IO uint8_t STX00 : 1; - __IO uint8_t STX01 : 1; - __IO uint8_t STX02 : 1; -} stc_adc_adst0_field_t; - -typedef struct stc_adc_adct_field -{ - __IO uint8_t CT0 : 1; - __IO uint8_t CT1 : 1; - __IO uint8_t CT2 : 1; - __IO uint8_t CT3 : 1; - __IO uint8_t CT4 : 1; - __IO uint8_t CT5 : 1; - __IO uint8_t CT6 : 1; - __IO uint8_t CT7 : 1; -} stc_adc_adct_field_t; - -typedef struct stc_adc_prtsl_field -{ - __IO uint8_t PRTSL0 : 1; - __IO uint8_t PRTSL1 : 1; - __IO uint8_t PRTSL2 : 1; - __IO uint8_t PRTSL3 : 1; -} stc_adc_prtsl_field_t; - -typedef struct stc_adc_sctsl_field -{ - __IO uint8_t SCTSL0 : 1; - __IO uint8_t SCTSL1 : 1; - __IO uint8_t SCTSL2 : 1; - __IO uint8_t SCTSL3 : 1; -} stc_adc_sctsl_field_t; - -typedef struct stc_adc_adcen_field -{ - __IO uint8_t ENBL : 1; - __IO uint8_t READY : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CYCLSL0 : 1; - __IO uint8_t CYCLSL1 : 1; -} stc_adc_adcen_field_t; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CRTRIM_MODULE register bit fields */ -typedef struct stc_crtrim_mcr_psr_field -{ - __IO uint8_t CSR0 : 1; - __IO uint8_t CSR1 : 1; -} stc_crtrim_mcr_psr_field_t; - -typedef struct stc_crtrim_mcr_ftrm_field -{ - __IO uint16_t TRD0 : 1; - __IO uint16_t TRD1 : 1; - __IO uint16_t TRD2 : 1; - __IO uint16_t TRD3 : 1; - __IO uint16_t TRD4 : 1; - __IO uint16_t TRD5 : 1; - __IO uint16_t TRD6 : 1; - __IO uint16_t TRD7 : 1; -} stc_crtrim_mcr_ftrm_field_t; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* EXTI_MODULE registEN bit fields */ -typedef struct stc_exti_enir_field -{ - __IO uint16_t EN0 : 1; - __IO uint16_t EN1 : 1; - __IO uint16_t EN2 : 1; - __IO uint16_t EN3 : 1; - __IO uint16_t EN4 : 1; - __IO uint16_t EN5 : 1; - __IO uint16_t EN6 : 1; - __IO uint16_t EN7 : 1; - __IO uint16_t EN8 : 1; - __IO uint16_t EN9 : 1; - __IO uint16_t EN10 : 1; - __IO uint16_t EN11 : 1; - __IO uint16_t EN12 : 1; - __IO uint16_t EN13 : 1; - __IO uint16_t EN14 : 1; - __IO uint16_t EN15 : 1; - __IO uint16_t EN16 : 1; - __IO uint16_t EN17 : 1; - __IO uint16_t EN18 : 1; - __IO uint16_t EN19 : 1; - __IO uint16_t EN20 : 1; - __IO uint16_t EN21 : 1; - __IO uint16_t EN22 : 1; - __IO uint16_t EN23 : 1; - __IO uint16_t EN24 : 1; - __IO uint16_t EN25 : 1; - __IO uint16_t EN26 : 1; - __IO uint16_t EN27 : 1; - __IO uint16_t EN28 : 1; - __IO uint16_t EN29 : 1; - __IO uint16_t EN30 : 1; - __IO uint16_t EN31 : 1; -} stc_exti_enir_field_t; - -typedef struct stc_exti_eirr_field -{ - __IO uint16_t ER0 : 1; - __IO uint16_t ER1 : 1; - __IO uint16_t ER2 : 1; - __IO uint16_t ER3 : 1; - __IO uint16_t ER4 : 1; - __IO uint16_t ER5 : 1; - __IO uint16_t ER6 : 1; - __IO uint16_t ER7 : 1; - __IO uint16_t ER8 : 1; - __IO uint16_t ER9 : 1; - __IO uint16_t ER10 : 1; - __IO uint16_t ER11 : 1; - __IO uint16_t ER12 : 1; - __IO uint16_t ER13 : 1; - __IO uint16_t ER14 : 1; - __IO uint16_t ER15 : 1; - __IO uint16_t ER16 : 1; - __IO uint16_t ER17 : 1; - __IO uint16_t ER18 : 1; - __IO uint16_t ER19 : 1; - __IO uint16_t ER20 : 1; - __IO uint16_t ER21 : 1; - __IO uint16_t ER22 : 1; - __IO uint16_t ER23 : 1; - __IO uint16_t ER24 : 1; - __IO uint16_t ER25 : 1; - __IO uint16_t ER26 : 1; - __IO uint16_t ER27 : 1; - __IO uint16_t ER28 : 1; - __IO uint16_t ER29 : 1; - __IO uint16_t ER30 : 1; - __IO uint16_t ER31 : 1; -} stc_exti_eirr_field_t; - -typedef struct stc_exti_eicl_field -{ - __IO uint16_t ECL0 : 1; - __IO uint16_t ECL1 : 1; - __IO uint16_t ECL2 : 1; - __IO uint16_t ECL3 : 1; - __IO uint16_t ECL4 : 1; - __IO uint16_t ECL5 : 1; - __IO uint16_t ECL6 : 1; - __IO uint16_t ECL7 : 1; - __IO uint16_t ECL8 : 1; - __IO uint16_t ECL9 : 1; - __IO uint16_t ECL10 : 1; - __IO uint16_t ECL11 : 1; - __IO uint16_t ECL12 : 1; - __IO uint16_t ECL13 : 1; - __IO uint16_t ECL14 : 1; - __IO uint16_t ECL15 : 1; - __IO uint16_t ECL16 : 1; - __IO uint16_t ECL17 : 1; - __IO uint16_t ECL18 : 1; - __IO uint16_t ECL19 : 1; - __IO uint16_t ECL20 : 1; - __IO uint16_t ECL21 : 1; - __IO uint16_t ECL22 : 1; - __IO uint16_t ECL23 : 1; - __IO uint16_t ECL24 : 1; - __IO uint16_t ECL25 : 1; - __IO uint16_t ECL26 : 1; - __IO uint16_t ECL27 : 1; - __IO uint16_t ECL28 : 1; - __IO uint16_t ECL29 : 1; - __IO uint16_t ECL30 : 1; - __IO uint16_t ECL31 : 1; -} stc_exti_eicl_field_t; - -typedef struct stc_exti_elvr_field -{ - __IO uint32_t LA0 : 1; - __IO uint32_t LB0 : 1; - __IO uint32_t LA1 : 1; - __IO uint32_t LB1 : 1; - __IO uint32_t LA2 : 1; - __IO uint32_t LB2 : 1; - __IO uint32_t LA3 : 1; - __IO uint32_t LB3 : 1; - __IO uint32_t LA4 : 1; - __IO uint32_t LB4 : 1; - __IO uint32_t LA5 : 1; - __IO uint32_t LB5 : 1; - __IO uint32_t LA6 : 1; - __IO uint32_t LB6 : 1; - __IO uint32_t LA7 : 1; - __IO uint32_t LB7 : 1; - __IO uint32_t LA8 : 1; - __IO uint32_t LB8 : 1; - __IO uint32_t LA9 : 1; - __IO uint32_t LB9 : 1; - __IO uint32_t LA10 : 1; - __IO uint32_t LB10 : 1; - __IO uint32_t LA11 : 1; - __IO uint32_t LB11 : 1; - __IO uint32_t LA12 : 1; - __IO uint32_t LB12 : 1; - __IO uint32_t LA13 : 1; - __IO uint32_t LB13 : 1; - __IO uint32_t LA14 : 1; - __IO uint32_t LB14 : 1; - __IO uint32_t LA15 : 1; - __IO uint32_t LB15 : 1; -} stc_exti_elvr_field_t; - -typedef struct stc_exti_elvr1_field -{ - __IO uint32_t LA16 : 1; - __IO uint32_t LB16 : 1; - __IO uint32_t LA17 : 1; - __IO uint32_t LB17 : 1; - __IO uint32_t LA18 : 1; - __IO uint32_t LB18 : 1; - __IO uint32_t LA19 : 1; - __IO uint32_t LB19 : 1; - __IO uint32_t LA20 : 1; - __IO uint32_t LB20 : 1; - __IO uint32_t LA21 : 1; - __IO uint32_t LB21 : 1; - __IO uint32_t LA22 : 1; - __IO uint32_t LB22 : 1; - __IO uint32_t LA23 : 1; - __IO uint32_t LB23 : 1; - __IO uint32_t LA24 : 1; - __IO uint32_t LB24 : 1; - __IO uint32_t LA25 : 1; - __IO uint32_t LB25 : 1; - __IO uint32_t LA26 : 1; - __IO uint32_t LB26 : 1; - __IO uint32_t LA27 : 1; - __IO uint32_t LB27 : 1; - __IO uint32_t LA28 : 1; - __IO uint32_t LB28 : 1; - __IO uint32_t LA29 : 1; - __IO uint32_t LB29 : 1; - __IO uint32_t LA30 : 1; - __IO uint32_t LB30 : 1; - __IO uint32_t LA31 : 1; - __IO uint32_t LB31 : 1; -} stc_exti_elvr1_field_t; - -typedef struct stc_exti_nmirr_field -{ - __IO uint8_t NR0 : 1; -} stc_exti_nmirr_field_t; - -typedef struct stc_exti_nmicl_field -{ - __IO uint8_t NCL0 : 1; -} stc_exti_nmicl_field_t; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* INTREQ_MODULE register bit fields */ -typedef struct stc_intreq_drqsel_field -{ - __IO uint32_t DRQSEL0 : 1; - __IO uint32_t DRQSEL1 : 1; - __IO uint32_t DRQSEL2 : 1; - __IO uint32_t DRQSEL3 : 1; - __IO uint32_t DRQSEL4 : 1; - __IO uint32_t DRQSEL5 : 1; - __IO uint32_t DRQSEL6 : 1; - __IO uint32_t DRQSEL7 : 1; - __IO uint32_t DRQSEL8 : 1; - __IO uint32_t DRQSEL9 : 1; - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; - __IO uint32_t DRQSEL15 : 1; - __IO uint32_t DRQSEL16 : 1; - __IO uint32_t DRQSEL17 : 1; - __IO uint32_t DRQSEL18 : 1; - __IO uint32_t DRQSEL19 : 1; - __IO uint32_t DRQSEL20 : 1; - __IO uint32_t DRQSEL21 : 1; - __IO uint32_t DRQSEL22 : 1; - __IO uint32_t DRQSEL23 : 1; - __IO uint32_t DRQSEL24 : 1; - __IO uint32_t DRQSEL25 : 1; - __IO uint32_t DRQSEL26 : 1; - __IO uint32_t DRQSEL27 : 1; - __IO uint32_t DRQSEL28 : 1; - __IO uint32_t DRQSEL29 : 1; - __IO uint32_t DRQSEL30 : 1; - __IO uint32_t DRQSEL31 : 1; -} stc_intreq_drqsel_field_t; - -typedef struct stc_intreq_oddpks_field -{ - __IO uint8_t ODDPKS0 : 1; - __IO uint8_t ODDPKS1 : 1; - __IO uint8_t ODDPKS2 : 1; - __IO uint8_t ODDPKS3 : 1; - __IO uint8_t ODDPKS4 : 1; -} stc_intreq_oddpks_field_t; - -typedef struct stc_intreq_exc02mon_field -{ - __IO uint32_t NMI : 1; - __IO uint32_t HWINT : 1; -} stc_intreq_exc02mon_field_t; - -typedef struct stc_intreq_irq00mon_field -{ - __IO uint32_t FCSINT : 1; -} stc_intreq_irq00mon_field_t; - -typedef struct stc_intreq_irq01mon_field -{ - __IO uint32_t SWWDTINT : 1; -} stc_intreq_irq01mon_field_t; - -typedef struct stc_intreq_irq02mon_field -{ - __IO uint32_t LVDINT : 1; -} stc_intreq_irq02mon_field_t; - -typedef struct stc_intreq_irq03mon_field -{ - __IO uint32_t WAVE0INT0 : 1; - __IO uint32_t WAVE0INT1 : 1; - __IO uint32_t WAVE0INT2 : 1; - __IO uint32_t WAVE0INT3 : 1; - __IO uint32_t WAVE1INT0 : 1; - __IO uint32_t WAVE1INT1 : 1; - __IO uint32_t WAVE1INT2 : 1; - __IO uint32_t WAVE1INT3 : 1; - __IO uint32_t WAVE2INT0 : 1; - __IO uint32_t WAVE2INT1 : 1; - __IO uint32_t WAVE2INT2 : 1; - __IO uint32_t WAVE2INT3 : 1; -} stc_intreq_irq03mon_field_t; - -typedef struct stc_intreq_irq04mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; -} stc_intreq_irq04mon_field_t; - -typedef struct stc_intreq_irq05mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; - __IO uint32_t EXTINT8 : 1; - __IO uint32_t EXTINT9 : 1; - __IO uint32_t EXTINT10 : 1; - __IO uint32_t EXTINT11 : 1; - __IO uint32_t EXTINT12 : 1; - __IO uint32_t EXTINT13 : 1; - __IO uint32_t EXTINT14 : 1; - __IO uint32_t EXTINT15 : 1; - __IO uint32_t EXTINT16 : 1; - __IO uint32_t EXTINT17 : 1; - __IO uint32_t EXTINT18 : 1; - __IO uint32_t EXTINT19 : 1; - __IO uint32_t EXTINT20 : 1; - __IO uint32_t EXTINT21 : 1; - __IO uint32_t EXTINT22 : 1; - __IO uint32_t EXTINT23 : 1; -} stc_intreq_irq05mon_field_t; - -typedef struct stc_intreq_irq06mon_field -{ - __IO uint32_t TIMINT1 : 1; - __IO uint32_t TIMINT2 : 1; - __IO uint32_t QUD0INT0 : 1; - __IO uint32_t QUD0INT1 : 1; - __IO uint32_t QUD0INT2 : 1; - __IO uint32_t QUD0INT3 : 1; - __IO uint32_t QUD0INT4 : 1; - __IO uint32_t QUD0INT5 : 1; - __IO uint32_t QUD1INT0 : 1; - __IO uint32_t QUD1INT1 : 1; - __IO uint32_t QUD1INT2 : 1; - __IO uint32_t QUD1INT3 : 1; - __IO uint32_t QUD1INT4 : 1; - __IO uint32_t QUD1INT5 : 1; - __IO uint32_t QUD2INT0 : 1; - __IO uint32_t QUD2INT1 : 1; - __IO uint32_t QUD2INT2 : 1; - __IO uint32_t QUD2INT3 : 1; - __IO uint32_t QUD2INT4 : 1; - __IO uint32_t QUD2INT5 : 1; -} stc_intreq_irq06mon_field_t; - -typedef struct stc_intreq_irq07mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq07mon_field_t; - -typedef struct stc_intreq_irq08mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq08mon_field_t; - -typedef struct stc_intreq_irq09mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq09mon_field_t; - -typedef struct stc_intreq_irq10mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq10mon_field_t; - -typedef struct stc_intreq_irq11mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq11mon_field_t; - -typedef struct stc_intreq_irq12mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq12mon_field_t; - -typedef struct stc_intreq_irq13mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq13mon_field_t; - -typedef struct stc_intreq_irq14mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq14mon_field_t; - -typedef struct stc_intreq_irq15mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq15mon_field_t; - -typedef struct stc_intreq_irq16mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq16mon_field_t; - -typedef struct stc_intreq_irq17mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq17mon_field_t; - -typedef struct stc_intreq_irq18mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq18mon_field_t; - -typedef struct stc_intreq_irq19mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq19mon_field_t; - -typedef struct stc_intreq_irq20mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq20mon_field_t; - -typedef struct stc_intreq_irq21mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq21mon_field_t; - -typedef struct stc_intreq_irq22mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq22mon_field_t; - -typedef struct stc_intreq_irq23mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; - __IO uint32_t PPGINT3 : 1; - __IO uint32_t PPGINT4 : 1; - __IO uint32_t PPGINT5 : 1; - __IO uint32_t PPGINT6 : 1; - __IO uint32_t PPGINT7 : 1; - __IO uint32_t PPGINT8 : 1; -} stc_intreq_irq23mon_field_t; - -typedef struct stc_intreq_irq24mon_field -{ - __IO uint32_t MOSCINT : 1; - __IO uint32_t SOSCINT : 1; - __IO uint32_t MPLLINT : 1; - __IO uint32_t UPLLINT : 1; - __IO uint32_t WCINT : 1; -} stc_intreq_irq24mon_field_t; - -typedef struct stc_intreq_irq25mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq25mon_field_t; - -typedef struct stc_intreq_irq26mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq26mon_field_t; - -typedef struct stc_intreq_irq27mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq27mon_field_t; - -typedef struct stc_intreq_irq28mon_field -{ - __IO uint32_t FRT0INT0 : 1; - __IO uint32_t FRT0INT1 : 1; - __IO uint32_t FRT0INT2 : 1; - __IO uint32_t FRT0INT3 : 1; - __IO uint32_t FRT0INT4 : 1; - __IO uint32_t FRT0INT5 : 1; - __IO uint32_t FRT1INT0 : 1; - __IO uint32_t FRT1INT1 : 1; - __IO uint32_t FRT1INT2 : 1; - __IO uint32_t FRT1INT3 : 1; - __IO uint32_t FRT1INT4 : 1; - __IO uint32_t FRT1INT5 : 1; - __IO uint32_t FRT2INT0 : 1; - __IO uint32_t FRT2INT1 : 1; - __IO uint32_t FRT2INT2 : 1; - __IO uint32_t FRT2INT3 : 1; - __IO uint32_t FRT2INT4 : 1; - __IO uint32_t FRT2INT5 : 1; -} stc_intreq_irq28mon_field_t; - -typedef struct stc_intreq_irq29mon_field -{ - __IO uint32_t ICU0INT0 : 1; - __IO uint32_t ICU0INT1 : 1; - __IO uint32_t ICU0INT2 : 1; - __IO uint32_t ICU0INT3 : 1; - __IO uint32_t ICU1INT0 : 1; - __IO uint32_t ICU1INT1 : 1; - __IO uint32_t ICU1INT2 : 1; - __IO uint32_t ICU1INT3 : 1; - __IO uint32_t ICU2INT0 : 1; - __IO uint32_t ICU2INT1 : 1; - __IO uint32_t ICU2INT2 : 1; - __IO uint32_t ICU2INT3 : 1; -} stc_intreq_irq29mon_field_t; - -typedef struct stc_intreq_irq30mon_field -{ - __IO uint32_t OCU0INT0 : 1; - __IO uint32_t OCU0INT1 : 1; - __IO uint32_t OCU0INT2 : 1; - __IO uint32_t OCU0INT3 : 1; - __IO uint32_t OCU0INT4 : 1; - __IO uint32_t OCU0INT5 : 1; - __IO uint32_t OCU1INT0 : 1; - __IO uint32_t OCU1INT1 : 1; - __IO uint32_t OCU1INT2 : 1; - __IO uint32_t OCU1INT3 : 1; - __IO uint32_t OCU1INT4 : 1; - __IO uint32_t OCU1INT5 : 1; - __IO uint32_t OCU2INT0 : 1; - __IO uint32_t OCU2INT1 : 1; - __IO uint32_t OCU2INT2 : 1; - __IO uint32_t OCU2INT3 : 1; - __IO uint32_t OCU2INT4 : 1; - __IO uint32_t OCU2INT5 : 1; -} stc_intreq_irq30mon_field_t; - -typedef struct stc_intreq_irq31mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; - __IO uint32_t BTINT8 : 1; - __IO uint32_t BTINT9 : 1; - __IO uint32_t BTINT10 : 1; - __IO uint32_t BTINT11 : 1; - __IO uint32_t BTINT12 : 1; - __IO uint32_t BTINT13 : 1; - __IO uint32_t BTINT14 : 1; - __IO uint32_t BTINT15 : 1; -} stc_intreq_irq31mon_field_t; - -typedef struct stc_intreq_irq32mon_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t MAC0SBD : 1; - __IO uint32_t MAC0PMI : 1; - __IO uint32_t MAC0LPI : 1; -} stc_intreq_irq32mon_field_t; - -typedef struct stc_intreq_irq33mon_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t MAC1SBD : 1; - __IO uint32_t MAC1PMI : 1; -} stc_intreq_irq33mon_field_t; - -typedef struct stc_intreq_irq34mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; -} stc_intreq_irq34mon_field_t; - -typedef struct stc_intreq_irq35mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; - __IO uint32_t USB0INT5 : 1; -} stc_intreq_irq35mon_field_t; - -typedef struct stc_intreq_irq36mon_field -{ - __IO uint32_t USB1INT0 : 1; - __IO uint32_t USB1INT1 : 1; - __IO uint32_t USB1INT2 : 1; - __IO uint32_t USB1INT3 : 1; - __IO uint32_t USB1INT4 : 1; -} stc_intreq_irq36mon_field_t; - -typedef struct stc_intreq_irq37mon_field -{ - __IO uint32_t USB1INT0 : 1; - __IO uint32_t USB1INT1 : 1; - __IO uint32_t USB1INT2 : 1; - __IO uint32_t USB1INT3 : 1; - __IO uint32_t USB1INT4 : 1; - __IO uint32_t USB1INT5 : 1; -} stc_intreq_irq37mon_field_t; - -typedef struct stc_intreq_irq38mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq38mon_field_t; - -typedef struct stc_intreq_irq39mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq39mon_field_t; - -typedef struct stc_intreq_irq40mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq40mon_field_t; - -typedef struct stc_intreq_irq41mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq41mon_field_t; - -typedef struct stc_intreq_irq42mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq42mon_field_t; - -typedef struct stc_intreq_irq43mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq43mon_field_t; - -typedef struct stc_intreq_irq44mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq44mon_field_t; - -typedef struct stc_intreq_irq45mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq45mon_field_t; - -typedef struct stc_intreq_irq46mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; - __IO uint32_t BTINT8 : 1; - __IO uint32_t BTINT9 : 1; - __IO uint32_t BTINT10 : 1; - __IO uint32_t BTINT11 : 1; - __IO uint32_t BTINT12 : 1; - __IO uint32_t BTINT13 : 1; - __IO uint32_t BTINT14 : 1; - __IO uint32_t BTINT15 : 1; -} stc_intreq_irq46mon_field_t; - -typedef struct stc_intreq_drqsel1_field -{ - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; -} stc_intreq_drqsel1_field_t; - -typedef struct stc_intreq_dqesel_field -{ - __IO uint32_t ESEL100 : 1; - __IO uint32_t ESEL101 : 1; - __IO uint32_t ESEL102 : 1; - __IO uint32_t ESEL103 : 1; - __IO uint32_t ESEL110 : 1; - __IO uint32_t ESEL111 : 1; - __IO uint32_t ESEL112 : 1; - __IO uint32_t ESEL113 : 1; - __IO uint32_t ESEL240 : 1; - __IO uint32_t ESEL241 : 1; - __IO uint32_t ESEL242 : 1; - __IO uint32_t ESEL243 : 1; - __IO uint32_t ESEL250 : 1; - __IO uint32_t ESEL251 : 1; - __IO uint32_t ESEL252 : 1; - __IO uint32_t ESEL253 : 1; - __IO uint32_t ESEL260 : 1; - __IO uint32_t ESEL261 : 1; - __IO uint32_t ESEL262 : 1; - __IO uint32_t ESEL263 : 1; - __IO uint32_t ESEL270 : 1; - __IO uint32_t ESEL271 : 1; - __IO uint32_t ESEL272 : 1; - __IO uint32_t ESEL273 : 1; - __IO uint32_t ESEL300 : 1; - __IO uint32_t ESEL301 : 1; - __IO uint32_t ESEL302 : 1; - __IO uint32_t ESEL303 : 1; - __IO uint32_t ESEL310 : 1; - __IO uint32_t ESEL311 : 1; - __IO uint32_t ESEL312 : 1; - __IO uint32_t ESEL313 : 1; -} stc_intreq_dqesel_field_t; - -typedef struct stc_intreq_oddpks1_field -{ - __IO uint8_t ODDPKS10 : 1; - __IO uint8_t ODDPKS11 : 1; - __IO uint8_t ODDPKS12 : 1; - __IO uint8_t ODDPKS13 : 1; - __IO uint8_t ODDPKS14 : 1; -} stc_intreq_oddpks1_field_t; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* GPIO_MODULE register bit fields */ -typedef struct stc_gpio_pfr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pfr0_field_t; - -typedef struct stc_gpio_pfr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr1_field_t; - -typedef struct stc_gpio_pfr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pfr2_field_t; - -typedef struct stc_gpio_pfr3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr3_field_t; - -typedef struct stc_gpio_pfr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pfr4_field_t; - -typedef struct stc_gpio_pfr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pfr5_field_t; - -typedef struct stc_gpio_pfr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pfr6_field_t; - -typedef struct stc_gpio_pfr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_pfr7_field_t; - -typedef struct stc_gpio_pfr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfr8_field_t; - - -typedef struct stc_gpio_pfra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pfra_field_t; - -typedef struct stc_gpio_pfrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfrc_field_t; - -typedef struct stc_gpio_pfrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfrd_field_t; - -typedef struct stc_gpio_pfre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfre_field_t; - -typedef struct stc_gpio_pfrf_field -{ - uint32_t RESERVED1 : 5; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pfrf_field_t; - -typedef struct stc_gpio_pcr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pcr0_field_t; - -typedef struct stc_gpio_pcr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr1_field_t; - -typedef struct stc_gpio_pcr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pcr2_field_t; - -typedef struct stc_gpio_pcr3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr3_field_t; - -typedef struct stc_gpio_pcr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pcr4_field_t; - -typedef struct stc_gpio_pcr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pcr5_field_t; - -typedef struct stc_gpio_pcr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pcr6_field_t; - -typedef struct stc_gpio_pcr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_pcr7_field_t; - -typedef struct stc_gpio_pcra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pcra_field_t; - -typedef struct stc_gpio_pcrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcrc_field_t; - -typedef struct stc_gpio_pcrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pcrd_field_t; - -typedef struct stc_gpio_pcre_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pcre_field_t; - -typedef struct stc_gpio_ddr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_ddr0_field_t; - -typedef struct stc_gpio_ddr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr1_field_t; - -typedef struct stc_gpio_ddr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_ddr2_field_t; - -typedef struct stc_gpio_ddr3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr3_field_t; - -typedef struct stc_gpio_ddr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_ddr4_field_t; - -typedef struct stc_gpio_ddr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_ddr5_field_t; - -typedef struct stc_gpio_ddr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_ddr6_field_t; - -typedef struct stc_gpio_ddr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_ddr7_field_t; - -typedef struct stc_gpio_ddr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddr8_field_t; - -typedef struct stc_gpio_ddra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_ddra_field_t; - -typedef struct stc_gpio_ddrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddrc_field_t; - -typedef struct stc_gpio_ddrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddrd_field_t; - -typedef struct stc_gpio_ddre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddre_field_t; - -typedef struct stc_gpio_ddrf_field -{ - uint32_t RESERVED1 : 5; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_ddrf_field_t; - -typedef struct stc_gpio_pdir0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdir0_field_t; - -typedef struct stc_gpio_pdir1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir1_field_t; - -typedef struct stc_gpio_pdir2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdir2_field_t; - -typedef struct stc_gpio_pdir3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir3_field_t; - -typedef struct stc_gpio_pdir4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdir4_field_t; - -typedef struct stc_gpio_pdir5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pdir5_field_t; - -typedef struct stc_gpio_pdir6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pdir6_field_t; - -typedef struct stc_gpio_pdir7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_pdir7_field_t; - -typedef struct stc_gpio_pdir8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdir8_field_t; - -typedef struct stc_gpio_pdira_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdira_field_t; - -typedef struct stc_gpio_pdirc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdirc_field_t; - -typedef struct stc_gpio_pdird_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdird_field_t; - -typedef struct stc_gpio_pdire_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdire_field_t; - -typedef struct stc_gpio_pdirf_field -{ - uint32_t RESERVED1 : 5; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pdirf_field_t; - -typedef struct stc_gpio_pdor0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdor0_field_t; - -typedef struct stc_gpio_pdor1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor1_field_t; - -typedef struct stc_gpio_pdor2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdor2_field_t; - -typedef struct stc_gpio_pdor3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor3_field_t; - -typedef struct stc_gpio_pdor4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdor4_field_t; - -typedef struct stc_gpio_pdor5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pdor5_field_t; - -typedef struct stc_gpio_pdor6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pdor6_field_t; - -typedef struct stc_gpio_pdor7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_pdor7_field_t; - -typedef struct stc_gpio_pdor8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdor8_field_t; - -typedef struct stc_gpio_pdora_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdora_field_t; - -typedef struct stc_gpio_pdorc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdorc_field_t; - -typedef struct stc_gpio_pdord_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdord_field_t; - -typedef struct stc_gpio_pdore_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdore_field_t; - -typedef struct stc_gpio_pdorf_field -{ - uint32_t RESERVED1 : 5; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pdorf_field_t; - -typedef struct stc_gpio_ade_field -{ - __IO uint32_t AN0 : 1; - __IO uint32_t AN1 : 1; - __IO uint32_t AN2 : 1; - __IO uint32_t AN3 : 1; - __IO uint32_t AN4 : 1; - __IO uint32_t AN5 : 1; - __IO uint32_t AN6 : 1; - __IO uint32_t AN7 : 1; - __IO uint32_t AN8 : 1; - __IO uint32_t AN9 : 1; - __IO uint32_t AN10 : 1; - __IO uint32_t AN11 : 1; - __IO uint32_t AN12 : 1; - __IO uint32_t AN13 : 1; - __IO uint32_t AN14 : 1; - __IO uint32_t AN15 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t AN24 : 1; - __IO uint32_t AN25 : 1; - __IO uint32_t AN26 : 1; - __IO uint32_t AN27 : 1; - __IO uint32_t AN28 : 1; - __IO uint32_t AN29 : 1; - __IO uint32_t AN30 : 1; - __IO uint32_t AN31 : 1; -} stc_gpio_ade_field_t; - -typedef struct stc_gpio_spsr_field -{ - __IO uint32_t SUBXC : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MAINXC : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t USB0C : 1; - __IO uint32_t USB1C : 1; -} stc_gpio_spsr_field_t; - -typedef struct stc_gpio_epfr00_field -{ - __IO uint32_t NMIS : 1; - __IO uint32_t CROUTE0 : 1; - __IO uint32_t CROUTE1 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t SUBOUTE0 : 1; - __IO uint32_t SUBOUTE1 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t USBP0E : 1; - uint32_t RESERVED3 : 3; - __IO uint32_t USBP1E : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t JTAGEN0B : 1; - __IO uint32_t JTAGEN1S : 1; - uint32_t RESERVED5 : 6; - __IO uint32_t TRC0E : 1; - __IO uint32_t TRC1E : 1; -} stc_gpio_epfr00_field_t; - -typedef struct stc_gpio_epfr01_field -{ - __IO uint32_t RTO00E0 : 1; - __IO uint32_t RTO00E1 : 1; - __IO uint32_t RTO01E0 : 1; - __IO uint32_t RTO01E1 : 1; - __IO uint32_t RTO02E0 : 1; - __IO uint32_t RTO02E1 : 1; - __IO uint32_t RTO03E0 : 1; - __IO uint32_t RTO03E1 : 1; - __IO uint32_t RTO04E0 : 1; - __IO uint32_t RTO04E1 : 1; - __IO uint32_t RTO05E0 : 1; - __IO uint32_t RTO05E1 : 1; - __IO uint32_t DTTI0C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI0S0 : 1; - __IO uint32_t DTTI0S1 : 1; - __IO uint32_t FRCK0S0 : 1; - __IO uint32_t FRCK0S1 : 1; - __IO uint32_t IC00S0 : 1; - __IO uint32_t IC00S1 : 1; - __IO uint32_t IC00S2 : 1; - __IO uint32_t IC01S0 : 1; - __IO uint32_t IC01S1 : 1; - __IO uint32_t IC01S2 : 1; - __IO uint32_t IC02S0 : 1; - __IO uint32_t IC02S1 : 1; - __IO uint32_t IC02S2 : 1; - __IO uint32_t IC03S0 : 1; - __IO uint32_t IC03S1 : 1; - __IO uint32_t IC03S2 : 1; -} stc_gpio_epfr01_field_t; - -typedef struct stc_gpio_epfr02_field -{ - __IO uint32_t RTO10E0 : 1; - __IO uint32_t RTO10E1 : 1; - __IO uint32_t RTO11E0 : 1; - __IO uint32_t RTO11E1 : 1; - __IO uint32_t RTO12E0 : 1; - __IO uint32_t RTO12E1 : 1; - __IO uint32_t RTO13E0 : 1; - __IO uint32_t RTO13E1 : 1; - __IO uint32_t RTO14E0 : 1; - __IO uint32_t RTO14E1 : 1; - __IO uint32_t RTO15E0 : 1; - __IO uint32_t RTO15E1 : 1; - __IO uint32_t DTTI1C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI1S0 : 1; - __IO uint32_t DTTI1S1 : 1; - __IO uint32_t FRCK1S0 : 1; - __IO uint32_t FRCK1S1 : 1; - __IO uint32_t IC10S0 : 1; - __IO uint32_t IC10S1 : 1; - __IO uint32_t IC10S2 : 1; - __IO uint32_t IC11S0 : 1; - __IO uint32_t IC11S1 : 1; - __IO uint32_t IC11S2 : 1; - __IO uint32_t IC12S0 : 1; - __IO uint32_t IC12S1 : 1; - __IO uint32_t IC12S2 : 1; - __IO uint32_t IC13S0 : 1; - __IO uint32_t IC13S1 : 1; - __IO uint32_t IC13S2 : 1; -} stc_gpio_epfr02_field_t; - -typedef struct stc_gpio_epfr03_field -{ - __IO uint32_t RTO20E0 : 1; - __IO uint32_t RTO20E1 : 1; - __IO uint32_t RTO21E0 : 1; - __IO uint32_t RTO21E1 : 1; - __IO uint32_t RTO22E0 : 1; - __IO uint32_t RTO22E1 : 1; - __IO uint32_t RTO23E0 : 1; - __IO uint32_t RTO23E1 : 1; - __IO uint32_t RTO24E0 : 1; - __IO uint32_t RTO24E1 : 1; - __IO uint32_t RTO25E0 : 1; - __IO uint32_t RTO25E1 : 1; - __IO uint32_t DTTI2C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI2S0 : 1; - __IO uint32_t DTTI2S1 : 1; - __IO uint32_t FRCK2S0 : 1; - __IO uint32_t FRCK2S1 : 1; - __IO uint32_t IC20S0 : 1; - __IO uint32_t IC20S1 : 1; - __IO uint32_t IC20S2 : 1; - __IO uint32_t IC21S0 : 1; - __IO uint32_t IC21S1 : 1; - __IO uint32_t IC21S2 : 1; - __IO uint32_t IC22S0 : 1; - __IO uint32_t IC22S1 : 1; - __IO uint32_t IC22S2 : 1; - __IO uint32_t IC23S0 : 1; - __IO uint32_t IC23S1 : 1; - __IO uint32_t IC23S2 : 1; -} stc_gpio_epfr03_field_t; - -typedef struct stc_gpio_epfr04_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA0E0 : 1; - __IO uint32_t TIOA0E1 : 1; - __IO uint32_t TIOB0S0 : 1; - __IO uint32_t TIOB0S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA1S0 : 1; - __IO uint32_t TIOA1S1 : 1; - __IO uint32_t TIOA1E0 : 1; - __IO uint32_t TIOA1E1 : 1; - __IO uint32_t TIOB1S0 : 1; - __IO uint32_t TIOB1S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA2E0 : 1; - __IO uint32_t TIOA2E1 : 1; - __IO uint32_t TIOB2S0 : 1; - __IO uint32_t TIOB2S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA3S0 : 1; - __IO uint32_t TIOA3S1 : 1; - __IO uint32_t TIOA3E0 : 1; - __IO uint32_t TIOA3E1 : 1; - __IO uint32_t TIOB3S0 : 1; - __IO uint32_t TIOB3S1 : 1; -} stc_gpio_epfr04_field_t; - -typedef struct stc_gpio_epfr05_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA4E0 : 1; - __IO uint32_t TIOA4E1 : 1; - __IO uint32_t TIOB4S0 : 1; - __IO uint32_t TIOB4S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA5S0 : 1; - __IO uint32_t TIOA5S1 : 1; - __IO uint32_t TIOA5E0 : 1; - __IO uint32_t TIOA5E1 : 1; - __IO uint32_t TIOB5S0 : 1; - __IO uint32_t TIOB5S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA6E0 : 1; - __IO uint32_t TIOA6E1 : 1; - __IO uint32_t TIOB6S0 : 1; - __IO uint32_t TIOB6S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA7S0 : 1; - __IO uint32_t TIOA7S1 : 1; - __IO uint32_t TIOA7E0 : 1; - __IO uint32_t TIOA7E1 : 1; - __IO uint32_t TIOB7S0 : 1; - __IO uint32_t TIOB7S1 : 1; -} stc_gpio_epfr05_field_t; - -typedef struct stc_gpio_epfr06_field -{ - __IO uint32_t EINT00S0 : 1; - __IO uint32_t EINT00S1 : 1; - __IO uint32_t EINT01S0 : 1; - __IO uint32_t EINT01S1 : 1; - __IO uint32_t EINT02S0 : 1; - __IO uint32_t EINT02S1 : 1; - __IO uint32_t EINT03S0 : 1; - __IO uint32_t EINT03S1 : 1; - __IO uint32_t EINT04S0 : 1; - __IO uint32_t EINT04S1 : 1; - __IO uint32_t EINT05S0 : 1; - __IO uint32_t EINT05S1 : 1; - __IO uint32_t EINT06S0 : 1; - __IO uint32_t EINT06S1 : 1; - __IO uint32_t EINT07S0 : 1; - __IO uint32_t EINT07S1 : 1; - __IO uint32_t EINT08S0 : 1; - __IO uint32_t EINT08S1 : 1; - __IO uint32_t EINT09S0 : 1; - __IO uint32_t EINT09S1 : 1; - __IO uint32_t EINT10S0 : 1; - __IO uint32_t EINT10S1 : 1; - __IO uint32_t EINT11S0 : 1; - __IO uint32_t EINT11S1 : 1; - __IO uint32_t EINT12S0 : 1; - __IO uint32_t EINT12S1 : 1; - __IO uint32_t EINT13S0 : 1; - __IO uint32_t EINT13S1 : 1; - __IO uint32_t EINT14S0 : 1; - __IO uint32_t EINT14S1 : 1; - __IO uint32_t EINT15S0 : 1; - __IO uint32_t EINT15S1 : 1; -} stc_gpio_epfr06_field_t; - -typedef struct stc_gpio_epfr07_field -{ - uint32_t RESERVED1 : 4; - __IO uint32_t SIN0S0 : 1; - __IO uint32_t SIN0S1 : 1; - __IO uint32_t SOT0B0 : 1; - __IO uint32_t SOT0B1 : 1; - __IO uint32_t SCK0B0 : 1; - __IO uint32_t SCK0B1 : 1; - __IO uint32_t SIN1S0 : 1; - __IO uint32_t SIN1S1 : 1; - __IO uint32_t SOT1B0 : 1; - __IO uint32_t SOT1B1 : 1; - __IO uint32_t SCK1B0 : 1; - __IO uint32_t SCK1B1 : 1; - __IO uint32_t SIN2S0 : 1; - __IO uint32_t SIN2S1 : 1; - __IO uint32_t SOT2B0 : 1; - __IO uint32_t SOT2B1 : 1; - __IO uint32_t SCK2B0 : 1; - __IO uint32_t SCK2B1 : 1; - __IO uint32_t SIN3S0 : 1; - __IO uint32_t SIN3S1 : 1; - __IO uint32_t SOT3B0 : 1; - __IO uint32_t SOT3B1 : 1; - __IO uint32_t SCK3B0 : 1; - __IO uint32_t SCK3B1 : 1; -} stc_gpio_epfr07_field_t; - -typedef struct stc_gpio_epfr08_field -{ - __IO uint32_t RTS4E0 : 1; - __IO uint32_t RTS4E1 : 1; - __IO uint32_t CTS4S0 : 1; - __IO uint32_t CTS4S1 : 1; - __IO uint32_t SIN4S0 : 1; - __IO uint32_t SIN4S1 : 1; - __IO uint32_t SOT4B0 : 1; - __IO uint32_t SOT4B1 : 1; - __IO uint32_t SCK4B0 : 1; - __IO uint32_t SCK4B1 : 1; - __IO uint32_t SIN5S0 : 1; - __IO uint32_t SIN5S1 : 1; - __IO uint32_t SOT5B0 : 1; - __IO uint32_t SOT5B1 : 1; - __IO uint32_t SCK5B0 : 1; - __IO uint32_t SCK5B1 : 1; - __IO uint32_t SIN6S0 : 1; - __IO uint32_t SIN6S1 : 1; - __IO uint32_t SOT6B0 : 1; - __IO uint32_t SOT6B1 : 1; - __IO uint32_t SCK6B0 : 1; - __IO uint32_t SCK6B1 : 1; - __IO uint32_t SIN7S0 : 1; - __IO uint32_t SIN7S1 : 1; - __IO uint32_t SOT7B0 : 1; - __IO uint32_t SOT7B1 : 1; - __IO uint32_t SCK7B0 : 1; - __IO uint32_t SCK7B1 : 1; -} stc_gpio_epfr08_field_t; - -typedef struct stc_gpio_epfr09_field -{ - __IO uint32_t QAIN0S0 : 1; - __IO uint32_t QAIN0S1 : 1; - __IO uint32_t QBIN0S0 : 1; - __IO uint32_t QBIN0S1 : 1; - __IO uint32_t QZIN0S0 : 1; - __IO uint32_t QZIN0S1 : 1; - __IO uint32_t QAIN1S0 : 1; - __IO uint32_t QAIN1S1 : 1; - __IO uint32_t QBIN1S0 : 1; - __IO uint32_t QBIN1S1 : 1; - __IO uint32_t QZIN1S0 : 1; - __IO uint32_t QZIN1S1 : 1; - __IO uint32_t ADTRG0S0 : 1; - __IO uint32_t ADTRG0S1 : 1; - __IO uint32_t ADTRG0S2 : 1; - __IO uint32_t ADTRG0S3 : 1; - __IO uint32_t ADTRG1S0 : 1; - __IO uint32_t ADTRG1S1 : 1; - __IO uint32_t ADTRG1S2 : 1; - __IO uint32_t ADTRG1S3 : 1; - __IO uint32_t ADTRG2S0 : 1; - __IO uint32_t ADTRG2S1 : 1; - __IO uint32_t ADTRG2S2 : 1; - __IO uint32_t ADTRG2S3 : 1; -} stc_gpio_epfr09_field_t; - -typedef struct stc_gpio_epfr10_field -{ - __IO uint32_t UEDEFB : 1; - __IO uint32_t UEDTHB : 1; - __IO uint32_t UECLKE : 1; - __IO uint32_t UEWEXE : 1; - __IO uint32_t UEDQME : 1; - __IO uint32_t UEOEXE : 1; - __IO uint32_t UEFLSE : 1; - __IO uint32_t UECS1E : 1; - __IO uint32_t UECS2E : 1; - __IO uint32_t UECS3E : 1; - __IO uint32_t UECS4E : 1; - __IO uint32_t UECS5E : 1; - __IO uint32_t UECS6E : 1; - __IO uint32_t UECS7E : 1; - __IO uint32_t UEAOOE : 1; - __IO uint32_t UEA08E : 1; - __IO uint32_t UEA09E : 1; - __IO uint32_t UEA10E : 1; - __IO uint32_t UEA11E : 1; - __IO uint32_t UEA12E : 1; - __IO uint32_t UEA13E : 1; - __IO uint32_t UEA14E : 1; - __IO uint32_t UEA15E : 1; - __IO uint32_t UEA16E : 1; - __IO uint32_t UEA17E : 1; - __IO uint32_t UEA18E : 1; -} stc_gpio_epfr10_field_t; - -typedef struct stc_gpio_epfr11_field -{ - __IO uint32_t UEALEE : 1; - __IO uint32_t UECS0E : 1; - __IO uint32_t UEA01E : 1; - __IO uint32_t UEA02E : 1; - __IO uint32_t UEA03E : 1; - __IO uint32_t UEA04E : 1; - __IO uint32_t UEA05E : 1; - __IO uint32_t UEA06E : 1; - __IO uint32_t UEA07E : 1; - __IO uint32_t UED00B : 1; - __IO uint32_t UED01B : 1; - __IO uint32_t UED02B : 1; - __IO uint32_t UED03B : 1; - __IO uint32_t UED04B : 1; - __IO uint32_t UED05B : 1; - __IO uint32_t UED06B : 1; - __IO uint32_t UED07B : 1; - __IO uint32_t UED08B : 1; - __IO uint32_t UED09B : 1; - __IO uint32_t UED10B : 1; - __IO uint32_t UED11B : 1; - __IO uint32_t UED12B : 1; - __IO uint32_t UED13B : 1; - __IO uint32_t UED14B : 1; - __IO uint32_t UED15B : 1; - __IO uint32_t UERLC : 1; -} stc_gpio_epfr11_field_t; - -typedef struct stc_gpio_epfr12_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA8E0 : 1; - __IO uint32_t TIOA8E1 : 1; - __IO uint32_t TIOB8S0 : 1; - __IO uint32_t TIOB8S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA9S0 : 1; - __IO uint32_t TIOA9S1 : 1; - __IO uint32_t TIOA9E0 : 1; - __IO uint32_t TIOA9E1 : 1; - __IO uint32_t TIOB9S0 : 1; - __IO uint32_t TIOB9S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA10E0 : 1; - __IO uint32_t TIOA10E1 : 1; - __IO uint32_t TIOB10S0 : 1; - __IO uint32_t TIOB10S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA11S0 : 1; - __IO uint32_t TIOA11S1 : 1; - __IO uint32_t TIOA11E0 : 1; - __IO uint32_t TIOA11E1 : 1; - __IO uint32_t TIOB11S0 : 1; - __IO uint32_t TIOB11S1 : 1; -} stc_gpio_epfr12_field_t; - -typedef struct stc_gpio_epfr13_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA12E0 : 1; - __IO uint32_t TIOA12E1 : 1; - __IO uint32_t TIOB12S0 : 1; - __IO uint32_t TIOB12S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA13S0 : 1; - __IO uint32_t TIOA13S1 : 1; - __IO uint32_t TIOA13E0 : 1; - __IO uint32_t TIOA13E1 : 1; - __IO uint32_t TIOB13S0 : 1; - __IO uint32_t TIOB13S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA14E0 : 1; - __IO uint32_t TIOA14E1 : 1; - __IO uint32_t TIOB14S0 : 1; - __IO uint32_t TIOB14S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA15S0 : 1; - __IO uint32_t TIOA15S1 : 1; - __IO uint32_t TIOA15E0 : 1; - __IO uint32_t TIOA15E1 : 1; - __IO uint32_t TIOB15S0 : 1; - __IO uint32_t TIOB15S1 : 1; -} stc_gpio_epfr13_field_t; - -typedef struct stc_gpio_epfr14_field -{ - __IO uint32_t QAIN2S0 : 1; - __IO uint32_t QAIN2S1 : 1; - __IO uint32_t QBIN2S0 : 1; - __IO uint32_t QBIN2S1 : 1; - __IO uint32_t QZIN2S0 : 1; - __IO uint32_t QZIN2S1 : 1; - uint32_t RESERVED1 : 12; - __IO uint32_t E_TD0E : 1; - __IO uint32_t E_TD1E : 1; - __IO uint32_t E_TE0E : 1; - __IO uint32_t E_TE1E : 1; - __IO uint32_t E_MC0E : 1; - __IO uint32_t E_MC1B : 1; - __IO uint32_t E_MD0B : 1; - __IO uint32_t E_MD1B : 1; - __IO uint32_t E_CKE : 1; - __IO uint32_t E_PSE : 1; - __IO uint32_t E_SPLC0 : 1; - __IO uint32_t E_SPLC1 : 1; -} stc_gpio_epfr14_field_t; - -typedef struct stc_gpio_epfr15_field -{ - __IO uint32_t EINT16S0 : 1; - __IO uint32_t EINT16S1 : 1; - __IO uint32_t EINT17S0 : 1; - __IO uint32_t EINT17S1 : 1; - __IO uint32_t EINT18S0 : 1; - __IO uint32_t EINT18S1 : 1; - __IO uint32_t EINT19S0 : 1; - __IO uint32_t EINT19S1 : 1; - __IO uint32_t EINT20S0 : 1; - __IO uint32_t EINT20S1 : 1; - __IO uint32_t EINT21S0 : 1; - __IO uint32_t EINT21S1 : 1; - __IO uint32_t EINT22S0 : 1; - __IO uint32_t EINT22S1 : 1; - __IO uint32_t EINT23S0 : 1; - __IO uint32_t EINT23S1 : 1; - __IO uint32_t EINT24S0 : 1; - __IO uint32_t EINT24S1 : 1; - __IO uint32_t EINT25S0 : 1; - __IO uint32_t EINT25S1 : 1; - __IO uint32_t EINT26S0 : 1; - __IO uint32_t EINT26S1 : 1; - __IO uint32_t EINT27S0 : 1; - __IO uint32_t EINT27S1 : 1; - __IO uint32_t EINT28S0 : 1; - __IO uint32_t EINT28S1 : 1; - __IO uint32_t EINT29S0 : 1; - __IO uint32_t EINT29S1 : 1; - __IO uint32_t EINT30S0 : 1; - __IO uint32_t EINT30S1 : 1; - __IO uint32_t EINT31S0 : 1; - __IO uint32_t EINT31S1 : 1; -} stc_gpio_epfr15_field_t; - -typedef struct stc_gpio_pzr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pzr0_field_t; - -typedef struct stc_gpio_pzr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzr1_field_t; - -typedef struct stc_gpio_pzr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pzr2_field_t; - -typedef struct stc_gpio_pzr3_field -{ - uint32_t RESERVED1 : 6; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzr3_field_t; - -typedef struct stc_gpio_pzr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pzr4_field_t; - -typedef struct stc_gpio_pzr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; -} stc_gpio_pzr5_field_t; - -typedef struct stc_gpio_pzr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pzr6_field_t; - -typedef struct stc_gpio_pzr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; -} stc_gpio_pzr7_field_t; - -typedef struct stc_gpio_pzr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzr8_field_t; - -typedef struct stc_gpio_pzra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pzra_field_t; - -typedef struct stc_gpio_pzrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzrc_field_t; - -typedef struct stc_gpio_pzrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzrd_field_t; - -typedef struct stc_gpio_pzre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzre_field_t; - -typedef struct stc_gpio_pzrf_field -{ - uint32_t RESERVED1 : 5; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pzrf_field_t; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* LVD_MODULE register bit fields */ -typedef struct stc_lvd_lvd_ctl_field -{ - uint8_t RESERVED1 : 2; - __IO uint8_t SVHI0 : 1; - __IO uint8_t SVHI1 : 1; - __IO uint8_t SVHI2 : 1; - __IO uint8_t SVHI3 : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t LVDIE : 1; -} stc_lvd_lvd_ctl_field_t; - -typedef struct stc_lvd_lvd_str_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIR : 1; -} stc_lvd_lvd_str_field_t; - -typedef struct stc_lvd_lvd_clr_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDCL : 1; -} stc_lvd_lvd_clr_field_t; - -typedef struct stc_lvd_lvd_str2_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIRDY : 1; -} stc_lvd_lvd_str2_field_t; - -/****************************************************************************** - * USB Ethernet CLK - ******************************************************************************/ -/* USB ETHERNET CLK register bit fields */ -typedef struct stc_usbethernetclk_uccr_field -{ - __IO uint8_t UCEN0 : 1; - __IO uint8_t UCSEL0 : 1; - __IO uint8_t UCSEL1 : 1; - __IO uint8_t UCEN1 : 1; - __IO uint8_t ECEN : 1; - __IO uint8_t ECSEL0 : 1; - __IO uint8_t ECSEL1 : 1; -} stc_usbethernetclk_uccr_field_t; - -typedef struct stc_usbethernetclk_upcr1_field -{ - __IO uint8_t UPLLEN : 1; - __IO uint8_t UPINC : 1; -} stc_usbethernetclk_upcr1_field_t; - -typedef struct stc_usbethernetclk_upcr2_field -{ - __IO uint8_t UPOWT0 : 1; - __IO uint8_t UPOWT1 : 1; - __IO uint8_t UPOWT2 : 1; -} stc_usbethernetclk_upcr2_field_t; - -typedef struct stc_usbethernetclk_upcr3_field -{ - __IO uint8_t UPLLK0 : 1; - __IO uint8_t UPLLK1 : 1; - __IO uint8_t UPLLK2 : 1; - __IO uint8_t UPLLK3 : 1; - __IO uint8_t UPLLK4 : 1; -} stc_usbethernetclk_upcr3_field_t; - -typedef struct stc_usbethernetclk_upcr4_field -{ - __IO uint8_t UPLLN0 : 1; - __IO uint8_t UPLLN1 : 1; - __IO uint8_t UPLLN2 : 1; - __IO uint8_t UPLLN3 : 1; - __IO uint8_t UPLLN4 : 1; - __IO uint8_t UPLLN5 : 1; - __IO uint8_t UPLLN6 : 1; -} stc_usbethernetclk_upcr4_field_t; - -typedef struct stc_usbethernetclk_up_str_field -{ - __IO uint8_t UPRDY : 1; -} stc_usbethernetclk_up_str_field_t; - -typedef struct stc_usbethernetclk_upint_enr_field -{ - __IO uint8_t UPCSE : 1; -} stc_usbethernetclk_upint_enr_field_t; - -typedef struct stc_usbethernetclk_upint_clr_field -{ - __IO uint8_t UPCSC : 1; -} stc_usbethernetclk_upint_clr_field_t; - -typedef struct stc_usbethernetclk_upint_str_field -{ - __IO uint8_t UPCSI : 1; -} stc_usbethernetclk_upint_str_field_t; - -typedef struct stc_usbethernetclk_upcr5_field -{ - __IO uint8_t UPLLM0 : 1; - __IO uint8_t UPLLM1 : 1; - __IO uint8_t UPLLM2 : 1; - __IO uint8_t UPLLM3 : 1; -} stc_usbethernetclk_upcr5_field_t; - -typedef struct stc_usbethernetclk_upcr6_field -{ - __IO uint8_t UBSR0 : 1; - __IO uint8_t UBSR1 : 1; - __IO uint8_t UBSR2 : 1; - __IO uint8_t UBSR3 : 1; -} stc_usbethernetclk_upcr6_field_t; - -typedef struct stc_usbethernetclk_upcr7_field -{ - __IO uint8_t EPLLEN : 1; -} stc_usbethernetclk_upcr7_field_t; - -typedef struct stc_usbethernetclk_usben0_field -{ - __IO uint8_t USBEN0 : 1; -} stc_usbethernetclk_usben0_field_t; - -typedef struct stc_usbethernetclk_usben1_field -{ - __IO uint8_t USBEN1 : 1; -} stc_usbethernetclk_usben1_field_t; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* MFS03_UART_MODULE register bit fields */ -typedef struct stc_mfs03_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_uart_smr_field_t; - -typedef struct stc_mfs03_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs03_uart_scr_field_t; - -typedef struct stc_mfs03_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs03_uart_escr_field_t; - -typedef struct stc_mfs03_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_uart_ssr_field_t; - -typedef struct stc_mfs03_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_rdr_field_t; - -typedef struct stc_mfs03_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_tdr_field_t; - -typedef struct stc_mfs03_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_uart_bgr_field_t; - -typedef struct stc_mfs03_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_uart_bgr1_field_t; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* MFS03_CSIO_MODULE register bit fields */ -typedef struct stc_mfs03_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_csio_smr_field_t; - -typedef struct stc_mfs03_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_csio_scr_field_t; - -typedef struct stc_mfs03_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs03_csio_escr_field_t; - -typedef struct stc_mfs03_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs03_csio_ssr_field_t; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* MFS03_LIN_MODULE register bit fields */ -typedef struct stc_mfs03_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_lin_smr_field_t; - -typedef struct stc_mfs03_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_lin_scr_field_t; - -typedef struct stc_mfs03_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs03_lin_escr_field_t; - -typedef struct stc_mfs03_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_lin_ssr_field_t; - -typedef struct stc_mfs03_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_lin_bgr_field_t; - -typedef struct stc_mfs03_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_lin_bgr1_field_t; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* MFS03_I2C_MODULE register bit fields */ -typedef struct stc_mfs03_i2c_smr_field -{ - __IO uint8_t ITST0 : 1; - __IO uint8_t ITST1 : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs03_i2c_smr_field_t; - -typedef struct stc_mfs03_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs03_i2c_ibcr_field_t; - -typedef struct stc_mfs03_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs03_i2c_ibsr_field_t; - -typedef struct stc_mfs03_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs03_i2c_ssr_field_t; - -typedef struct stc_mfs03_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs03_i2c_isba_field_t; - -typedef struct stc_mfs03_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs03_i2c_ismk_field_t; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* MFS47_UART_MODULE register bit fields */ -typedef struct stc_mfs47_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_uart_smr_field_t; - -typedef struct stc_mfs47_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs47_uart_scr_field_t; - -typedef struct stc_mfs47_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs47_uart_escr_field_t; - -typedef struct stc_mfs47_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_uart_ssr_field_t; - -typedef struct stc_mfs47_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_rdr_field_t; - -typedef struct stc_mfs47_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_tdr_field_t; - -typedef struct stc_mfs47_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_uart_bgr_field_t; - -typedef struct stc_mfs47_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_uart_bgr1_field_t; - -typedef struct stc_mfs47_uart_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_uart_fcr_field_t; - -typedef struct stc_mfs47_uart_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_uart_fcr0_field_t; - -typedef struct stc_mfs47_uart_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_uart_fcr1_field_t; - -typedef struct stc_mfs47_uart_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_uart_fbyte_field_t; - -typedef struct stc_mfs47_uart_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_uart_fbyte1_field_t; - -typedef struct stc_mfs47_uart_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_uart_fbyte2_field_t; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* MFS47_CSIO_MODULE register bit fields */ -typedef struct stc_mfs47_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_csio_smr_field_t; - -typedef struct stc_mfs47_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_csio_scr_field_t; - -typedef struct stc_mfs47_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs47_csio_escr_field_t; - -typedef struct stc_mfs47_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs47_csio_ssr_field_t; - -typedef struct stc_mfs47_csio_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_csio_fcr_field_t; - -typedef struct stc_mfs47_csio_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_csio_fcr0_field_t; - -typedef struct stc_mfs47_csio_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_csio_fcr1_field_t; - -typedef struct stc_mfs47_csio_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_csio_fbyte_field_t; - -typedef struct stc_mfs47_csio_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_csio_fbyte1_field_t; - -typedef struct stc_mfs47_csio_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_csio_fbyte2_field_t; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* MFS47_LIN_MODULE register bit fields */ -typedef struct stc_mfs47_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_lin_smr_field_t; - -typedef struct stc_mfs47_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_lin_scr_field_t; - -typedef struct stc_mfs47_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs47_lin_escr_field_t; - -typedef struct stc_mfs47_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_lin_ssr_field_t; - -typedef struct stc_mfs47_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_lin_bgr_field_t; - -typedef struct stc_mfs47_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_lin_bgr1_field_t; - -typedef struct stc_mfs47_lin_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_lin_fcr_field_t; - -typedef struct stc_mfs47_lin_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_lin_fcr0_field_t; - -typedef struct stc_mfs47_lin_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_lin_fcr1_field_t; - -typedef struct stc_mfs47_lin_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_lin_fbyte_field_t; - -typedef struct stc_mfs47_lin_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_lin_fbyte1_field_t; - -typedef struct stc_mfs47_lin_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_lin_fbyte2_field_t; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* MFS47_I2C_MODULE register bit fields */ -typedef struct stc_mfs47_i2c_smr_field -{ - __IO uint8_t ITST0 : 1; - __IO uint8_t ITST1 : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD0 : 1; - __IO uint8_t MD1 : 1; - __IO uint8_t MD2 : 1; -} stc_mfs47_i2c_smr_field_t; - -typedef struct stc_mfs47_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs47_i2c_ibcr_field_t; - -typedef struct stc_mfs47_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs47_i2c_ibsr_field_t; - -typedef struct stc_mfs47_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs47_i2c_ssr_field_t; - -typedef struct stc_mfs47_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs47_i2c_isba_field_t; - -typedef struct stc_mfs47_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs47_i2c_ismk_field_t; - -typedef struct stc_mfs47_i2c_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_i2c_fcr_field_t; - -typedef struct stc_mfs47_i2c_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_i2c_fcr0_field_t; - -typedef struct stc_mfs47_i2c_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_i2c_fcr1_field_t; - -typedef struct stc_mfs47_i2c_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_i2c_fbyte_field_t; - -typedef struct stc_mfs47_i2c_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_i2c_fbyte1_field_t; - -typedef struct stc_mfs47_i2c_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_i2c_fbyte2_field_t; - -/****************************************************************************** - * MFS_NFC_MODULE - ******************************************************************************/ -/* MFS_NFC_MODULE register bit fields */ -typedef struct stc_mfs_nfc_i2cdnf_field -{ - __IO uint16_t I2CDNF00 : 1; - __IO uint16_t I2CDNF01 : 1; - __IO uint16_t I2CDNF10 : 1; - __IO uint16_t I2CDNF11 : 1; - __IO uint16_t I2CDNF20 : 1; - __IO uint16_t I2CDNF21 : 1; - __IO uint16_t I2CDNF30 : 1; - __IO uint16_t I2CDNF31 : 1; - __IO uint16_t I2CDNF40 : 1; - __IO uint16_t I2CDNF41 : 1; - __IO uint16_t I2CDNF50 : 1; - __IO uint16_t I2CDNF51 : 1; - __IO uint16_t I2CDNF60 : 1; - __IO uint16_t I2CDNF61 : 1; - __IO uint16_t I2CDNF70 : 1; - __IO uint16_t I2CDNF71 : 1; -} stc_mfs_nfc_i2cdnf_field_t; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC_MODULE register bit fields */ -typedef struct stc_crc_crccr_field -{ - __IO uint8_t INIT : 1; - __IO uint8_t CRC32 : 1; - __IO uint8_t LTLEND : 1; - __IO uint8_t LSBFST : 1; - __IO uint8_t CRCLTE : 1; - __IO uint8_t CRCLSF : 1; - __IO uint8_t FXOR : 1; -} stc_crc_crccr_field_t; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* WC_MODULE register bit fields */ -typedef struct stc_wc_wcrd_field -{ - __IO uint8_t CTR0 : 1; - __IO uint8_t CTR1 : 1; - __IO uint8_t CTR2 : 1; - __IO uint8_t CTR3 : 1; - __IO uint8_t CTR4 : 1; - __IO uint8_t CTR5 : 1; -} stc_wc_wcrd_field_t; - -typedef struct stc_wc_wcrl_field -{ - __IO uint8_t RLC0 : 1; - __IO uint8_t RLC1 : 1; - __IO uint8_t RLC2 : 1; - __IO uint8_t RLC3 : 1; - __IO uint8_t RLC4 : 1; - __IO uint8_t RLC5 : 1; -} stc_wc_wcrl_field_t; - -typedef struct stc_wc_wccr_field -{ - __IO uint8_t WCIF : 1; - __IO uint8_t WCIE : 1; - __IO uint8_t CS0 : 1; - __IO uint8_t CS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t WCOP : 1; - __IO uint8_t WCEN : 1; -} stc_wc_wccr_field_t; - -typedef struct stc_wc_clk_sel_field -{ - __IO uint16_t SEL_IN : 1; - uint16_t RESERVED1 : 7; - __IO uint16_t SEL_OUT : 1; -} stc_wc_clk_sel_field_t; - -typedef struct stc_wc_clk_en_field -{ - __IO uint8_t CLK_EN : 1; - __IO uint8_t CLK_EN_R : 1; -} stc_wc_clk_en_field_t; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* EXBUS_MODULE register bit fields */ -typedef struct stc_exbus_mode0_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode0_field_t; - -typedef struct stc_exbus_mode1_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode1_field_t; - -typedef struct stc_exbus_mode2_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode2_field_t; - -typedef struct stc_exbus_mode3_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode3_field_t; - -typedef struct stc_exbus_mode4_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode4_field_t; - -typedef struct stc_exbus_mode5_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode5_field_t; - -typedef struct stc_exbus_mode6_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode6_field_t; - -typedef struct stc_exbus_mode7_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode7_field_t; - -typedef struct stc_exbus_tim0_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim0_field_t; - -typedef struct stc_exbus_tim1_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim1_field_t; - -typedef struct stc_exbus_tim2_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim2_field_t; - -typedef struct stc_exbus_tim3_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim3_field_t; - -typedef struct stc_exbus_tim4_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim4_field_t; - -typedef struct stc_exbus_tim5_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim5_field_t; - -typedef struct stc_exbus_tim6_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim6_field_t; - -typedef struct stc_exbus_tim7_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim7_field_t; - -typedef struct stc_exbus_area0_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area0_field_t; - -typedef struct stc_exbus_area1_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area1_field_t; - -typedef struct stc_exbus_area2_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area2_field_t; - -typedef struct stc_exbus_area3_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area3_field_t; - -typedef struct stc_exbus_area4_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area4_field_t; - -typedef struct stc_exbus_area5_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area5_field_t; - -typedef struct stc_exbus_area6_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area6_field_t; - -typedef struct stc_exbus_area7_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area7_field_t; - -typedef struct stc_exbus_atim0_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim0_field_t; - -typedef struct stc_exbus_atim1_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim1_field_t; - -typedef struct stc_exbus_atim2_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim2_field_t; - -typedef struct stc_exbus_atim3_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim3_field_t; - -typedef struct stc_exbus_atim4_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim4_field_t; - -typedef struct stc_exbus_atim5_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim5_field_t; - -typedef struct stc_exbus_atim6_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim6_field_t; - -typedef struct stc_exbus_atim7_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim7_field_t; - -typedef struct stc_exbus_dclkr_field -{ - __IO uint8_t MDIV0 : 1; - __IO uint8_t MDIV1 : 1; - __IO uint8_t MDIV2 : 1; - __IO uint8_t MDIV3 : 1; - __IO uint8_t MCLKON : 1; -} stc_exbus_dclkr_field_t; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB_MODULE register bit fields */ -typedef struct stc_usb_hcnt_field -{ - __IO uint16_t HOST : 1; - __IO uint16_t URST : 1; - __IO uint16_t SOFIRE : 1; - __IO uint16_t DIRE : 1; - __IO uint16_t CNNIRE : 1; - __IO uint16_t CMPIRE : 1; - __IO uint16_t URIRE : 1; - __IO uint16_t RWKIRE : 1; - __IO uint16_t RETRY : 1; - __IO uint16_t CANCEL : 1; - __IO uint16_t SOFSTEP : 1; -} stc_usb_hcnt_field_t; - -typedef struct stc_usb_hcnt0_field -{ - __IO uint8_t HOST : 1; - __IO uint8_t URST : 1; - __IO uint8_t SOFIRE : 1; - __IO uint8_t DIRE : 1; - __IO uint8_t CNNIRE : 1; - __IO uint8_t CMPIRE : 1; - __IO uint8_t URIRE : 1; - __IO uint8_t RWKIRE : 1; -} stc_usb_hcnt0_field_t; - -typedef struct stc_usb_hcnt1_field -{ - __IO uint8_t RETRY : 1; - __IO uint8_t CANCEL : 1; - __IO uint8_t SOFSTEP : 1; -} stc_usb_hcnt1_field_t; - -typedef struct stc_usb_hirq_field -{ - __IO uint8_t SOFIRQ : 1; - __IO uint8_t DIRQ : 1; - __IO uint8_t CNNIRQ : 1; - __IO uint8_t CMPIRQ : 1; - __IO uint8_t URIRQ : 1; - __IO uint8_t RWKIRQ : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TCAN : 1; -} stc_usb_hirq_field_t; - -typedef struct stc_usb_herr_field -{ - __IO uint8_t HS0 : 1; - __IO uint8_t HS1 : 1; - __IO uint8_t STUFF : 1; - __IO uint8_t TGERR : 1; - __IO uint8_t CRC : 1; - __IO uint8_t TOUT : 1; - __IO uint8_t RERR : 1; - __IO uint8_t LSTOF : 1; -} stc_usb_herr_field_t; - -typedef struct stc_usb_hstate_field -{ - __IO uint8_t CSTAT : 1; - __IO uint8_t TMODE : 1; - __IO uint8_t SUSP : 1; - __IO uint8_t SOFBUSY : 1; - __IO uint8_t CLKSEL : 1; - __IO uint8_t ALIVE : 1; -} stc_usb_hstate_field_t; - -typedef struct stc_usb_hfcomp_field -{ - __IO uint8_t FRAMECOMP0 : 1; - __IO uint8_t FRAMECOMP1 : 1; - __IO uint8_t FRAMECOMP2 : 1; - __IO uint8_t FRAMECOMP3 : 1; - __IO uint8_t FRAMECOMP4 : 1; - __IO uint8_t FRAMECOMP5 : 1; - __IO uint8_t FRAMECOMP6 : 1; - __IO uint8_t FRAMECOMP7 : 1; -} stc_usb_hfcomp_field_t; - -typedef struct stc_usb_hrtimer_field -{ - __IO uint16_t RTIMER0 : 1; - __IO uint16_t RTIMER1 : 1; - __IO uint16_t RTIMER2 : 1; - __IO uint16_t RTIMER3 : 1; - __IO uint16_t RTIMER4 : 1; - __IO uint16_t RTIMER5 : 1; - __IO uint16_t RTIMER6 : 1; - __IO uint16_t RTIMER7 : 1; - __IO uint16_t RTIMER8 : 1; - __IO uint16_t RTIMER9 : 1; - __IO uint16_t RTIMER10 : 1; - __IO uint16_t RTIMER11 : 1; - __IO uint16_t RTIMER12 : 1; - __IO uint16_t RTIMER13 : 1; - __IO uint16_t RTIMER14 : 1; - __IO uint16_t RTIMER15 : 1; -} stc_usb_hrtimer_field_t; - -typedef struct stc_usb_hrtimer0_field -{ - __IO uint8_t RTIMER00 : 1; - __IO uint8_t RTIMER01 : 1; - __IO uint8_t RTIMER02 : 1; - __IO uint8_t RTIMER03 : 1; - __IO uint8_t RTIMER04 : 1; - __IO uint8_t RTIMER05 : 1; - __IO uint8_t RTIMER06 : 1; - __IO uint8_t RTIMER07 : 1; -} stc_usb_hrtimer0_field_t; - -typedef struct stc_usb_hrtimer1_field -{ - __IO uint8_t RTIMER10 : 1; - __IO uint8_t RTIMER11 : 1; - __IO uint8_t RTIMER12 : 1; - __IO uint8_t RTIMER13 : 1; - __IO uint8_t RTIMER14 : 1; - __IO uint8_t RTIMER15 : 1; - __IO uint8_t RTIMER16 : 1; - __IO uint8_t RTIMER17 : 1; -} stc_usb_hrtimer1_field_t; - -typedef struct stc_usb_hrtimer2_field -{ - __IO uint8_t RTIMER20 : 1; - __IO uint8_t RTIMER21 : 1; - __IO uint8_t RTIMER22 : 1; -} stc_usb_hrtimer2_field_t; - -typedef struct stc_usb_hadr_field -{ - __IO uint8_t ADDRESS0 : 1; - __IO uint8_t ADDRESS1 : 1; - __IO uint8_t ADDRESS2 : 1; - __IO uint8_t ADDRESS3 : 1; - __IO uint8_t ADDRESS4 : 1; - __IO uint8_t ADDRESS5 : 1; - __IO uint8_t ADDRESS6 : 1; -} stc_usb_hadr_field_t; - -typedef struct stc_usb_heof_field -{ - __IO uint16_t EOF0 : 1; - __IO uint16_t EOF1 : 1; - __IO uint16_t EOF2 : 1; - __IO uint16_t EOF3 : 1; - __IO uint16_t EOF4 : 1; - __IO uint16_t EOF5 : 1; - __IO uint16_t EOF6 : 1; - __IO uint16_t EOF7 : 1; - __IO uint16_t EOF8 : 1; - __IO uint16_t EOF9 : 1; - __IO uint16_t EOF10 : 1; - __IO uint16_t EOF11 : 1; - __IO uint16_t EOF12 : 1; - __IO uint16_t EOF13 : 1; - __IO uint16_t EOF14 : 1; - __IO uint16_t EOF15 : 1; -} stc_usb_heof_field_t; - -typedef struct stc_usb_heof0_field -{ - __IO uint8_t EOF00 : 1; - __IO uint8_t EOF01 : 1; - __IO uint8_t EOF02 : 1; - __IO uint8_t EOF03 : 1; - __IO uint8_t EOF04 : 1; - __IO uint8_t EOF05 : 1; - __IO uint8_t EOF06 : 1; - __IO uint8_t EOF07 : 1; -} stc_usb_heof0_field_t; - -typedef struct stc_usb_heof1_field -{ - __IO uint8_t EOF10 : 1; - __IO uint8_t EOF11 : 1; - __IO uint8_t EOF12 : 1; - __IO uint8_t EOF13 : 1; - __IO uint8_t EOF14 : 1; - __IO uint8_t EOF15 : 1; -} stc_usb_heof1_field_t; - -typedef struct stc_usb_hframe_field -{ - __IO uint16_t FRAME0 : 1; - __IO uint16_t FRAME1 : 1; - __IO uint16_t FRAME2 : 1; - __IO uint16_t FRAME3 : 1; - __IO uint16_t FRAME4 : 1; - __IO uint16_t FRAME5 : 1; - __IO uint16_t FRAME6 : 1; - __IO uint16_t FRAME7 : 1; - __IO uint16_t FRAME8 : 1; - __IO uint16_t FRAME9 : 1; - __IO uint16_t FRAME10 : 1; -} stc_usb_hframe_field_t; - -typedef struct stc_usb_hframe0_field -{ - __IO uint8_t FRAME00 : 1; - __IO uint8_t FRAME01 : 1; - __IO uint8_t FRAME02 : 1; - __IO uint8_t FRAME03 : 1; - __IO uint8_t FRAME04 : 1; - __IO uint8_t FRAME05 : 1; - __IO uint8_t FRAME06 : 1; - __IO uint8_t FRAME07 : 1; -} stc_usb_hframe0_field_t; - -typedef struct stc_usb_hframe1_field -{ - __IO uint8_t FRAME10 : 1; - __IO uint8_t FRAME11 : 1; - __IO uint8_t FRAME12 : 1; - __IO uint8_t FRAME13 : 1; -} stc_usb_hframe1_field_t; - -typedef struct stc_usb_htoken_field -{ - __IO uint8_t ENDPT0 : 1; - __IO uint8_t ENDPT1 : 1; - __IO uint8_t ENDPT2 : 1; - __IO uint8_t ENDPT3 : 1; - __IO uint8_t TKNEN0 : 1; - __IO uint8_t TKNEN1 : 1; - __IO uint8_t TKNEN2 : 1; - __IO uint8_t TGGL : 1; -} stc_usb_htoken_field_t; - -typedef struct stc_usb_udcc_field -{ - __IO uint16_t PWC : 1; - __IO uint16_t RFBK : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t STALCLREN : 1; - __IO uint16_t USTP : 1; - __IO uint16_t HCONX : 1; - __IO uint16_t RESUM : 1; - __IO uint16_t RST : 1; -} stc_usb_udcc_field_t; - -typedef struct stc_usb_ep0c_field -{ - __IO uint16_t PKS00 : 1; - __IO uint16_t PKS01 : 1; - __IO uint16_t PKS02 : 1; - __IO uint16_t PKS03 : 1; - __IO uint16_t PKS04 : 1; - __IO uint16_t PKS05 : 1; - __IO uint16_t PKS06 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; -} stc_usb_ep0c_field_t; - -typedef struct stc_usb_ep1c_field -{ - __IO uint16_t PKS10 : 1; - __IO uint16_t PKS11 : 1; - __IO uint16_t PKS12 : 1; - __IO uint16_t PKS13 : 1; - __IO uint16_t PKS14 : 1; - __IO uint16_t PKS15 : 1; - __IO uint16_t PKS16 : 1; - __IO uint16_t PKS17 : 1; - __IO uint16_t PKS18 : 1; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep1c_field_t; - -typedef struct stc_usb_ep2c_field -{ - __IO uint16_t PKS20 : 1; - __IO uint16_t PKS21 : 1; - __IO uint16_t PKS22 : 1; - __IO uint16_t PKS23 : 1; - __IO uint16_t PKS24 : 1; - __IO uint16_t PKS25 : 1; - __IO uint16_t PKS26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep2c_field_t; - -typedef struct stc_usb_ep3c_field -{ - __IO uint16_t PKS30 : 1; - __IO uint16_t PKS31 : 1; - __IO uint16_t PKS32 : 1; - __IO uint16_t PKS33 : 1; - __IO uint16_t PKS34 : 1; - __IO uint16_t PKS35 : 1; - __IO uint16_t PKS36 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep3c_field_t; - -typedef struct stc_usb_ep4c_field -{ - __IO uint16_t PKS40 : 1; - __IO uint16_t PKS41 : 1; - __IO uint16_t PKS42 : 1; - __IO uint16_t PKS43 : 1; - __IO uint16_t PKS44 : 1; - __IO uint16_t PKS45 : 1; - __IO uint16_t PKS46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep4c_field_t; - -typedef struct stc_usb_ep5c_field -{ - __IO uint16_t PKS50 : 1; - __IO uint16_t PKS51 : 1; - __IO uint16_t PKS52 : 1; - __IO uint16_t PKS53 : 1; - __IO uint16_t PKS54 : 1; - __IO uint16_t PKS55 : 1; - __IO uint16_t PKS56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep5c_field_t; - -typedef struct stc_usb_tmsp_field -{ - __IO uint16_t TMSP0 : 1; - __IO uint16_t TMSP1 : 1; - __IO uint16_t TMSP2 : 1; - __IO uint16_t TMSP3 : 1; - __IO uint16_t TMSP4 : 1; - __IO uint16_t TMSP5 : 1; - __IO uint16_t TMSP6 : 1; - __IO uint16_t TMSP7 : 1; - __IO uint16_t TMSP8 : 1; - __IO uint16_t TMSP9 : 1; - __IO uint16_t TMSP10 : 1; -} stc_usb_tmsp_field_t; - -typedef struct stc_usb_udcs_field -{ - __IO uint8_t CONF : 1; - __IO uint8_t SETP : 1; - __IO uint8_t WKUP : 1; - __IO uint8_t BRST : 1; - __IO uint8_t SOF : 1; - __IO uint8_t SUSP : 1; -} stc_usb_udcs_field_t; - -typedef struct stc_usb_udcie_field -{ - __IO uint8_t CONFIE : 1; - __IO uint8_t CONFN : 1; - __IO uint8_t WKUPIE : 1; - __IO uint8_t BRSTIE : 1; - __IO uint8_t SOFIE : 1; - __IO uint8_t SUSPIE : 1; -} stc_usb_udcie_field_t; - -typedef struct stc_usb_ep0is_field -{ - uint16_t RESERVED1 : 10; - __IO uint16_t DRQI : 1; - uint16_t RESERVED2 : 3; - __IO uint16_t DRQIIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0is_field_t; - -typedef struct stc_usb_ep0os_field -{ - __IO uint16_t SIZE0 : 1; - __IO uint16_t SIZE1 : 1; - __IO uint16_t SIZE2 : 1; - __IO uint16_t SIZE3 : 1; - __IO uint16_t SIZE4 : 1; - __IO uint16_t SIZE5 : 1; - __IO uint16_t SIZE6 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQO : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQOIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0os_field_t; - -typedef struct stc_usb_ep1s_field -{ - __IO uint16_t SIZE10 : 1; - __IO uint16_t SIZE11 : 1; - __IO uint16_t SIZE12 : 1; - __IO uint16_t SIZE13 : 1; - __IO uint16_t SIZE14 : 1; - __IO uint16_t SIZE15 : 1; - __IO uint16_t SIZE16 : 1; - __IO uint16_t SIZE17 : 1; - __IO uint16_t SIZE18 : 1; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep1s_field_t; - -typedef struct stc_usb_ep2s_field -{ - __IO uint16_t SIZE20 : 1; - __IO uint16_t SIZE21 : 1; - __IO uint16_t SIZE22 : 1; - __IO uint16_t SIZE23 : 1; - __IO uint16_t SIZE24 : 1; - __IO uint16_t SIZE25 : 1; - __IO uint16_t SIZE26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep2s_field_t; - -typedef struct stc_usb_ep4s_field -{ - __IO uint16_t SIZE40 : 1; - __IO uint16_t SIZE41 : 1; - __IO uint16_t SIZE42 : 1; - __IO uint16_t SIZE43 : 1; - __IO uint16_t SIZE44 : 1; - __IO uint16_t SIZE45 : 1; - __IO uint16_t SIZE46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep4s_field_t; - -typedef struct stc_usb_ep5s_field -{ - __IO uint16_t SIZE50 : 1; - __IO uint16_t SIZE51 : 1; - __IO uint16_t SIZE52 : 1; - __IO uint16_t SIZE53 : 1; - __IO uint16_t SIZE54 : 1; - __IO uint16_t SIZE55 : 1; - __IO uint16_t SIZE56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep5s_field_t; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMAC_MODULE register bit fields */ -typedef struct stc_dmac_dmacr_field -{ - uint32_t RESERVED1 : 24; - __IO uint32_t DH0 : 1; - __IO uint32_t DH1 : 1; - __IO uint32_t DH2 : 1; - __IO uint32_t DH3 : 1; - __IO uint32_t PR : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t DS : 1; - __IO uint32_t DE : 1; -} stc_dmac_dmacr_field_t; - -typedef struct stc_dmac_dmaca0_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca0_field_t; - -typedef struct stc_dmac_dmacb0_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb0_field_t; - -typedef struct stc_dmac_dmaca1_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca1_field_t; - -typedef struct stc_dmac_dmacb1_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb1_field_t; - -typedef struct stc_dmac_dmaca2_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca2_field_t; - -typedef struct stc_dmac_dmacb2_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb2_field_t; - -typedef struct stc_dmac_dmaca3_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca3_field_t; - -typedef struct stc_dmac_dmacb3_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb3_field_t; - -typedef struct stc_dmac_dmaca4_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca4_field_t; - -typedef struct stc_dmac_dmacb4_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb4_field_t; - -typedef struct stc_dmac_dmaca5_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca5_field_t; - -typedef struct stc_dmac_dmacb5_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb5_field_t; - -typedef struct stc_dmac_dmaca6_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca6_field_t; - -typedef struct stc_dmac_dmacb6_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb6_field_t; - -typedef struct stc_dmac_dmaca7_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca7_field_t; - -typedef struct stc_dmac_dmacb7_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb7_field_t; - -/****************************************************************************** - * ETHERNET_MAC_MODULE - ******************************************************************************/ -/* ETHERNET_MAC_MODULE register bit fields */ -typedef struct stc_ethernet_mac_mcr_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t RE : 1; - __IO uint32_t TE : 1; - __IO uint32_t DC : 1; - __IO uint32_t BL0 : 1; - __IO uint32_t BL1 : 1; - __IO uint32_t ACS : 1; - __IO uint32_t LUD : 1; - __IO uint32_t DR : 1; - __IO uint32_t IPC : 1; - __IO uint32_t DM : 1; - __IO uint32_t LM : 1; - __IO uint32_t DO : 1; - __IO uint32_t FES : 1; - __IO uint32_t PS : 1; - __IO uint32_t DCRS : 1; - __IO uint32_t IFG0 : 1; - __IO uint32_t IFG1 : 1; - __IO uint32_t IFG2 : 1; - __IO uint32_t JE : 1; - __IO uint32_t BE : 1; - __IO uint32_t JD : 1; - __IO uint32_t WD : 1; - __IO uint32_t TC : 1; - __IO uint32_t CST : 1; -} stc_ethernet_mac_mcr_field_t; - -typedef struct stc_ethernet_mac_mffr_field -{ - __IO uint32_t PR : 1; - __IO uint32_t HUC : 1; - __IO uint32_t HMC : 1; - __IO uint32_t DAIF : 1; - __IO uint32_t PM : 1; - __IO uint32_t DB : 1; - __IO uint32_t PCF0 : 1; - __IO uint32_t PCF1 : 1; - __IO uint32_t SAIF : 1; - __IO uint32_t SAF : 1; - __IO uint32_t HPF : 1; - uint32_t RESERVED1 :20; - __IO uint32_t RA : 1; -} stc_ethernet_mac_mffr_field_t; - -typedef struct stc_ethernet_mac_mhtrh_field -{ - __IO uint32_t HTH0 : 1; - __IO uint32_t HTH1 : 1; - __IO uint32_t HTH2 : 1; - __IO uint32_t HTH3 : 1; - __IO uint32_t HTH4 : 1; - __IO uint32_t HTH5 : 1; - __IO uint32_t HTH6 : 1; - __IO uint32_t HTH7 : 1; - __IO uint32_t HTH8 : 1; - __IO uint32_t HTH9 : 1; - __IO uint32_t HTH10 : 1; - __IO uint32_t HTH11 : 1; - __IO uint32_t HTH12 : 1; - __IO uint32_t HTH13 : 1; - __IO uint32_t HTH14 : 1; - __IO uint32_t HTH15 : 1; - __IO uint32_t HTH16 : 1; - __IO uint32_t HTH17 : 1; - __IO uint32_t HTH18 : 1; - __IO uint32_t HTH19 : 1; - __IO uint32_t HTH20 : 1; - __IO uint32_t HTH21 : 1; - __IO uint32_t HTH22 : 1; - __IO uint32_t HTH23 : 1; - __IO uint32_t HTH24 : 1; - __IO uint32_t HTH25 : 1; - __IO uint32_t HTH26 : 1; - __IO uint32_t HTH27 : 1; - __IO uint32_t HTH28 : 1; - __IO uint32_t HTH29 : 1; - __IO uint32_t HTH30 : 1; - __IO uint32_t HTH31 : 1; -} stc_ethernet_mac_mhtrh_field_t; - -typedef struct stc_ethernet_mac_mhtrl_field -{ - __IO uint32_t HTL0 : 1; - __IO uint32_t HTL1 : 1; - __IO uint32_t HTL2 : 1; - __IO uint32_t HTL3 : 1; - __IO uint32_t HTL4 : 1; - __IO uint32_t HTL5 : 1; - __IO uint32_t HTL6 : 1; - __IO uint32_t HTL7 : 1; - __IO uint32_t HTL8 : 1; - __IO uint32_t HTL9 : 1; - __IO uint32_t HTL10 : 1; - __IO uint32_t HTL11 : 1; - __IO uint32_t HTL12 : 1; - __IO uint32_t HTL13 : 1; - __IO uint32_t HTL14 : 1; - __IO uint32_t HTL15 : 1; - __IO uint32_t HTL16 : 1; - __IO uint32_t HTL17 : 1; - __IO uint32_t HTL18 : 1; - __IO uint32_t HTL19 : 1; - __IO uint32_t HTL20 : 1; - __IO uint32_t HTL21 : 1; - __IO uint32_t HTL22 : 1; - __IO uint32_t HTL23 : 1; - __IO uint32_t HTL24 : 1; - __IO uint32_t HTL25 : 1; - __IO uint32_t HTL26 : 1; - __IO uint32_t HTL27 : 1; - __IO uint32_t HTL28 : 1; - __IO uint32_t HTL29 : 1; - __IO uint32_t HTL30 : 1; - __IO uint32_t HTL31 : 1; -} stc_ethernet_mac_mhtrl_field_t; - -typedef struct stc_ethernet_mac_gar_field -{ - __IO uint32_t GB : 1; - __IO uint32_t GW : 1; - __IO uint32_t CR0 : 1; - __IO uint32_t CR1 : 1; - __IO uint32_t CR2 : 1; - __IO uint32_t CR3 : 1; - __IO uint32_t GR0 : 1; - __IO uint32_t GR1 : 1; - __IO uint32_t GR2 : 1; - __IO uint32_t GR3 : 1; - __IO uint32_t GR4 : 1; - __IO uint32_t PA0 : 1; - __IO uint32_t PA1 : 1; - __IO uint32_t PA2 : 1; - __IO uint32_t PA3 : 1; - __IO uint32_t PA4 : 1; -} stc_ethernet_mac_gar_field_t; - -typedef struct stc_ethernet_mac_gdr_field -{ - __IO uint32_t GD0 : 1; - __IO uint32_t GD1 : 1; - __IO uint32_t GD2 : 1; - __IO uint32_t GD3 : 1; - __IO uint32_t GD4 : 1; - __IO uint32_t GD5 : 1; - __IO uint32_t GD6 : 1; - __IO uint32_t GD7 : 1; - __IO uint32_t GD8 : 1; - __IO uint32_t GD9 : 1; - __IO uint32_t GD10 : 1; - __IO uint32_t GD11 : 1; - __IO uint32_t GD12 : 1; - __IO uint32_t GD13 : 1; - __IO uint32_t GD14 : 1; - __IO uint32_t GD15 : 1; -} stc_ethernet_mac_gdr_field_t; - -typedef struct stc_ethernet_mac_fcr_field -{ - __IO uint32_t FCB_BPA : 1; - __IO uint32_t TFE : 1; - __IO uint32_t RFE : 1; - __IO uint32_t UP : 1; - __IO uint32_t PLT0 : 1; - __IO uint32_t PLT1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t DZPQ : 1; - uint32_t RESERVED2 : 8; - __IO uint32_t PT0 : 1; - __IO uint32_t PT1 : 1; - __IO uint32_t PT2 : 1; - __IO uint32_t PT3 : 1; - __IO uint32_t PT4 : 1; - __IO uint32_t PT5 : 1; - __IO uint32_t PT6 : 1; - __IO uint32_t PT7 : 1; - __IO uint32_t PT8 : 1; - __IO uint32_t PT9 : 1; - __IO uint32_t PT10 : 1; - __IO uint32_t PT11 : 1; - __IO uint32_t PT12 : 1; - __IO uint32_t PT13 : 1; - __IO uint32_t PT14 : 1; - __IO uint32_t PT15 : 1; -} stc_ethernet_mac_fcr_field_t; - -typedef struct stc_ethernet_mac_vtr_field -{ - __IO uint32_t VL0 : 1; - __IO uint32_t VL1 : 1; - __IO uint32_t VL2 : 1; - __IO uint32_t VL3 : 1; - __IO uint32_t VL4 : 1; - __IO uint32_t VL5 : 1; - __IO uint32_t VL6 : 1; - __IO uint32_t VL7 : 1; - __IO uint32_t VL8 : 1; - __IO uint32_t VL9 : 1; - __IO uint32_t VL10 : 1; - __IO uint32_t VL11 : 1; - __IO uint32_t VL12 : 1; - __IO uint32_t VL13 : 1; - __IO uint32_t VL14 : 1; - __IO uint32_t VL15 : 1; - __IO uint32_t ETV : 1; -} stc_ethernet_mac_vtr_field_t; - -typedef struct stc_ethernet_mac_rwffr_field -{ - __IO uint32_t RWFFR0 : 1; - __IO uint32_t RWFFR1 : 1; - __IO uint32_t RWFFR2 : 1; - __IO uint32_t RWFFR3 : 1; - __IO uint32_t RWFFR4 : 1; - __IO uint32_t RWFFR5 : 1; - __IO uint32_t RWFFR6 : 1; - __IO uint32_t RWFFR7 : 1; - __IO uint32_t RWFFR8 : 1; - __IO uint32_t RWFFR9 : 1; - __IO uint32_t RWFFR10 : 1; - __IO uint32_t RWFFR11 : 1; - __IO uint32_t RWFFR12 : 1; - __IO uint32_t RWFFR13 : 1; - __IO uint32_t RWFFR14 : 1; - __IO uint32_t RWFFR15 : 1; - __IO uint32_t RWFFR16 : 1; - __IO uint32_t RWFFR17 : 1; - __IO uint32_t RWFFR18 : 1; - __IO uint32_t RWFFR19 : 1; - __IO uint32_t RWFFR20 : 1; - __IO uint32_t RWFFR21 : 1; - __IO uint32_t RWFFR22 : 1; - __IO uint32_t RWFFR23 : 1; - __IO uint32_t RWFFR24 : 1; - __IO uint32_t RWFFR25 : 1; - __IO uint32_t RWFFR26 : 1; - __IO uint32_t RWFFR27 : 1; - __IO uint32_t RWFFR28 : 1; - __IO uint32_t RWFFR29 : 1; - __IO uint32_t RWFFR30 : 1; - __IO uint32_t RWFFR31 : 1; -} stc_ethernet_mac_rwffr_field_t; - -typedef struct stc_ethernet_mac_pmtr_field -{ - __IO uint32_t PD : 1; - __IO uint32_t MPE : 1; - __IO uint32_t WFE : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t MPR : 1; - __IO uint32_t WPR : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t GU : 1; - uint32_t RESERVED3 :21; - __IO uint32_t RWFFRPR : 1; -} stc_ethernet_mac_pmtr_field_t; - -typedef struct stc_ethernet_mac_lpicsr_field -{ - __IO uint32_t TLPIEN : 1; - __IO uint32_t TLPIEX : 1; - __IO uint32_t RLPIEN : 1; - __IO uint32_t RLPIEX : 1; - uint32_t RESERVED1 : 4; - __IO uint32_t TLPIST : 1; - __IO uint32_t RLPIST : 1; - uint32_t RESERVED2 : 6; - __IO uint32_t LPIEN : 1; - __IO uint32_t PLS : 1; - __IO uint32_t PLSEN : 1; - __IO uint32_t LPITXA : 1; -} stc_ethernet_mac_lpicsr_field_t; - -typedef struct stc_ethernet_mac_lpitcr_field -{ - __IO uint32_t TWT0 : 1; - __IO uint32_t TWT1 : 1; - __IO uint32_t TWT2 : 1; - __IO uint32_t TWT3 : 1; - __IO uint32_t TWT4 : 1; - __IO uint32_t TWT5 : 1; - __IO uint32_t TWT6 : 1; - __IO uint32_t TWT7 : 1; - __IO uint32_t TWT8 : 1; - __IO uint32_t TWT9 : 1; - __IO uint32_t TWT10 : 1; - __IO uint32_t TWT11 : 1; - __IO uint32_t TWT12 : 1; - __IO uint32_t TWT13 : 1; - __IO uint32_t TWT14 : 1; - __IO uint32_t TWT15 : 1; - __IO uint32_t LIT0 : 1; - __IO uint32_t LIT1 : 1; - __IO uint32_t LIT2 : 1; - __IO uint32_t LIT3 : 1; - __IO uint32_t LIT4 : 1; - __IO uint32_t LIT5 : 1; - __IO uint32_t LIT6 : 1; - __IO uint32_t LIT7 : 1; - __IO uint32_t LIT8 : 1; - __IO uint32_t LIT9 : 1; -} stc_ethernet_mac_lpitcr_field_t; - -typedef struct stc_ethernet_mac_isr_field -{ - __IO uint32_t RGIS : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t PIS : 1; - __IO uint32_t MIS : 1; - __IO uint32_t RIS : 1; - __IO uint32_t TIS : 1; - __IO uint32_t COIS : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t TSIS : 1; - __IO uint32_t LPIIS : 1; -} stc_ethernet_mac_isr_field_t; - -typedef struct stc_ethernet_mac_imr_field -{ - __IO uint32_t RGIM : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t PIM : 1; - uint32_t RESERVED2 : 5; - __IO uint32_t TSIM : 1; - __IO uint32_t LPIIM : 1; -} stc_ethernet_mac_imr_field_t; - -typedef struct stc_ethernet_mac_mar0h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 :15; - __IO uint32_t MO : 1; -} stc_ethernet_mac_mar0h_field_t; - -typedef struct stc_ethernet_mac_mar0l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar0l_field_t; - -typedef struct stc_ethernet_mac_mar1h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar1h_field_t; - -typedef struct stc_ethernet_mac_mar1l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar1l_field_t; - -typedef struct stc_ethernet_mac_mar2h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar2h_field_t; - -typedef struct stc_ethernet_mac_mar2l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar2l_field_t; - -typedef struct stc_ethernet_mac_mar3h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar3h_field_t; - -typedef struct stc_ethernet_mac_mar3l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar3l_field_t; - -typedef struct stc_ethernet_mac_mar4h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar4h_field_t; - -typedef struct stc_ethernet_mac_mar4l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar4l_field_t; - -typedef struct stc_ethernet_mac_mar5h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar5h_field_t; - -typedef struct stc_ethernet_mac_mar5l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar5l_field_t; - -typedef struct stc_ethernet_mac_mar6h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar6h_field_t; - -typedef struct stc_ethernet_mac_mar6l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar6l_field_t; - -typedef struct stc_ethernet_mac_mar7h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar7h_field_t; - -typedef struct stc_ethernet_mac_mar7l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar7l_field_t; - -typedef struct stc_ethernet_mac_mar8h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar8h_field_t; - -typedef struct stc_ethernet_mac_mar8l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar8l_field_t; - -typedef struct stc_ethernet_mac_mar9h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar9h_field_t; - -typedef struct stc_ethernet_mac_mar9l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar9l_field_t; - -typedef struct stc_ethernet_mac_mar10h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar10h_field_t; - -typedef struct stc_ethernet_mac_mar10l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar10l_field_t; - -typedef struct stc_ethernet_mac_mar11h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar11h_field_t; - -typedef struct stc_ethernet_mac_mar11l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar11l_field_t; - -typedef struct stc_ethernet_mac_mar12h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar12h_field_t; - -typedef struct stc_ethernet_mac_mar12l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar12l_field_t; - -typedef struct stc_ethernet_mac_mar13h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar13h_field_t; - -typedef struct stc_ethernet_mac_mar13l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar13l_field_t; - -typedef struct stc_ethernet_mac_mar14h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar14h_field_t; - -typedef struct stc_ethernet_mac_mar14l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar14l_field_t; - -typedef struct stc_ethernet_mac_mar15h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar15h_field_t; - -typedef struct stc_ethernet_mac_mar15l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar15l_field_t; - -typedef struct stc_ethernet_mac_rgsr_field -{ - __IO uint32_t LM : 1; - __IO uint32_t LSP0 : 1; - __IO uint32_t LSP1 : 1; - __IO uint32_t LS : 1; -} stc_ethernet_mac_rgsr_field_t; - -typedef struct stc_ethernet_mac_tscr_field -{ - __IO uint32_t TSE : 1; - __IO uint32_t TFCU : 1; - __IO uint32_t TSI : 1; - __IO uint32_t TSU : 1; - __IO uint32_t TITE : 1; - __IO uint32_t TARU : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t TSEA : 1; - __IO uint32_t TSDB : 1; - __IO uint32_t TSV2E : 1; - __IO uint32_t TETSP : 1; - __IO uint32_t TSIP6E : 1; - __IO uint32_t TSIP4E : 1; - __IO uint32_t TETSEM : 1; - __IO uint32_t TSMRM : 1; - __IO uint32_t TSPS0 : 1; - __IO uint32_t TSPS1 : 1; - __IO uint32_t TSENMF : 1; - uint32_t RESERVED2 : 5; - __IO uint32_t ATSFC : 1; -} stc_ethernet_mac_tscr_field_t; - -typedef struct stc_ethernet_mac_ssir_field -{ - __IO uint32_t SSINC0 : 1; - __IO uint32_t SSINC1 : 1; - __IO uint32_t SSINC2 : 1; - __IO uint32_t SSINC3 : 1; - __IO uint32_t SSINC4 : 1; - __IO uint32_t SSINC5 : 1; - __IO uint32_t SSINC6 : 1; - __IO uint32_t SSINC7 : 1; -} stc_ethernet_mac_ssir_field_t; - -typedef struct stc_ethernet_mac_stsr_field -{ - __IO uint32_t TSS0 : 1; - __IO uint32_t TSS1 : 1; - __IO uint32_t TSS2 : 1; - __IO uint32_t TSS3 : 1; - __IO uint32_t TSS4 : 1; - __IO uint32_t TSS5 : 1; - __IO uint32_t TSS6 : 1; - __IO uint32_t TSS7 : 1; - __IO uint32_t TSS8 : 1; - __IO uint32_t TSS9 : 1; - __IO uint32_t TSS10 : 1; - __IO uint32_t TSS11 : 1; - __IO uint32_t TSS12 : 1; - __IO uint32_t TSS13 : 1; - __IO uint32_t TSS14 : 1; - __IO uint32_t TSS15 : 1; - __IO uint32_t TSS16 : 1; - __IO uint32_t TSS17 : 1; - __IO uint32_t TSS18 : 1; - __IO uint32_t TSS19 : 1; - __IO uint32_t TSS20 : 1; - __IO uint32_t TSS21 : 1; - __IO uint32_t TSS22 : 1; - __IO uint32_t TSS23 : 1; - __IO uint32_t TSS24 : 1; - __IO uint32_t TSS25 : 1; - __IO uint32_t TSS26 : 1; - __IO uint32_t TSS27 : 1; - __IO uint32_t TSS28 : 1; - __IO uint32_t TSS29 : 1; - __IO uint32_t TSS30 : 1; - __IO uint32_t TSS31 : 1; -} stc_ethernet_mac_stsr_field_t; - -typedef struct stc_ethernet_mac_stnr_field -{ - __IO uint32_t TSSS0 : 1; - __IO uint32_t TSSS1 : 1; - __IO uint32_t TSSS2 : 1; - __IO uint32_t TSSS3 : 1; - __IO uint32_t TSSS4 : 1; - __IO uint32_t TSSS5 : 1; - __IO uint32_t TSSS6 : 1; - __IO uint32_t TSSS7 : 1; - __IO uint32_t TSSS8 : 1; - __IO uint32_t TSSS9 : 1; - __IO uint32_t TSSS10 : 1; - __IO uint32_t TSSS11 : 1; - __IO uint32_t TSSS12 : 1; - __IO uint32_t TSSS13 : 1; - __IO uint32_t TSSS14 : 1; - __IO uint32_t TSSS15 : 1; - __IO uint32_t TSSS16 : 1; - __IO uint32_t TSSS17 : 1; - __IO uint32_t TSSS18 : 1; - __IO uint32_t TSSS19 : 1; - __IO uint32_t TSSS20 : 1; - __IO uint32_t TSSS21 : 1; - __IO uint32_t TSSS22 : 1; - __IO uint32_t TSSS23 : 1; - __IO uint32_t TSSS24 : 1; - __IO uint32_t TSSS25 : 1; - __IO uint32_t TSSS26 : 1; - __IO uint32_t TSSS27 : 1; - __IO uint32_t TSSS28 : 1; - __IO uint32_t TSSS29 : 1; - __IO uint32_t TSSS30 : 1; -} stc_ethernet_mac_stnr_field_t; - -typedef struct stc_ethernet_mac_stsur_field -{ - __IO uint32_t TSS0 : 1; - __IO uint32_t TSS1 : 1; - __IO uint32_t TSS2 : 1; - __IO uint32_t TSS3 : 1; - __IO uint32_t TSS4 : 1; - __IO uint32_t TSS5 : 1; - __IO uint32_t TSS6 : 1; - __IO uint32_t TSS7 : 1; - __IO uint32_t TSS8 : 1; - __IO uint32_t TSS9 : 1; - __IO uint32_t TSS10 : 1; - __IO uint32_t TSS11 : 1; - __IO uint32_t TSS12 : 1; - __IO uint32_t TSS13 : 1; - __IO uint32_t TSS14 : 1; - __IO uint32_t TSS15 : 1; - __IO uint32_t TSS16 : 1; - __IO uint32_t TSS17 : 1; - __IO uint32_t TSS18 : 1; - __IO uint32_t TSS19 : 1; - __IO uint32_t TSS20 : 1; - __IO uint32_t TSS21 : 1; - __IO uint32_t TSS22 : 1; - __IO uint32_t TSS23 : 1; - __IO uint32_t TSS24 : 1; - __IO uint32_t TSS25 : 1; - __IO uint32_t TSS26 : 1; - __IO uint32_t TSS27 : 1; - __IO uint32_t TSS28 : 1; - __IO uint32_t TSS29 : 1; - __IO uint32_t TSS30 : 1; - __IO uint32_t TSS31 : 1; -} stc_ethernet_mac_stsur_field_t; - -typedef struct stc_ethernet_mac_stnur_field -{ - __IO uint32_t TSSS0 : 1; - __IO uint32_t TSSS1 : 1; - __IO uint32_t TSSS2 : 1; - __IO uint32_t TSSS3 : 1; - __IO uint32_t TSSS4 : 1; - __IO uint32_t TSSS5 : 1; - __IO uint32_t TSSS6 : 1; - __IO uint32_t TSSS7 : 1; - __IO uint32_t TSSS8 : 1; - __IO uint32_t TSSS9 : 1; - __IO uint32_t TSSS10 : 1; - __IO uint32_t TSSS11 : 1; - __IO uint32_t TSSS12 : 1; - __IO uint32_t TSSS13 : 1; - __IO uint32_t TSSS14 : 1; - __IO uint32_t TSSS15 : 1; - __IO uint32_t TSSS16 : 1; - __IO uint32_t TSSS17 : 1; - __IO uint32_t TSSS18 : 1; - __IO uint32_t TSSS19 : 1; - __IO uint32_t TSSS20 : 1; - __IO uint32_t TSSS21 : 1; - __IO uint32_t TSSS22 : 1; - __IO uint32_t TSSS23 : 1; - __IO uint32_t TSSS24 : 1; - __IO uint32_t TSSS25 : 1; - __IO uint32_t TSSS26 : 1; - __IO uint32_t TSSS27 : 1; - __IO uint32_t TSSS28 : 1; - __IO uint32_t TSSS29 : 1; - __IO uint32_t TSSS30 : 1; - __IO uint32_t ADDSUB : 1; -} stc_ethernet_mac_stnur_field_t; - -typedef struct stc_ethernet_mac_tsar_field -{ - __IO uint32_t TSAR0 : 1; - __IO uint32_t TSAR1 : 1; - __IO uint32_t TSAR2 : 1; - __IO uint32_t TSAR3 : 1; - __IO uint32_t TSAR4 : 1; - __IO uint32_t TSAR5 : 1; - __IO uint32_t TSAR6 : 1; - __IO uint32_t TSAR7 : 1; - __IO uint32_t TSAR8 : 1; - __IO uint32_t TSAR9 : 1; - __IO uint32_t TSAR10 : 1; - __IO uint32_t TSAR11 : 1; - __IO uint32_t TSAR12 : 1; - __IO uint32_t TSAR13 : 1; - __IO uint32_t TSAR14 : 1; - __IO uint32_t TSAR15 : 1; - __IO uint32_t TSAR16 : 1; - __IO uint32_t TSAR17 : 1; - __IO uint32_t TSAR18 : 1; - __IO uint32_t TSAR19 : 1; - __IO uint32_t TSAR20 : 1; - __IO uint32_t TSAR21 : 1; - __IO uint32_t TSAR22 : 1; - __IO uint32_t TSAR23 : 1; - __IO uint32_t TSAR24 : 1; - __IO uint32_t TSAR25 : 1; - __IO uint32_t TSAR26 : 1; - __IO uint32_t TSAR27 : 1; - __IO uint32_t TSAR28 : 1; - __IO uint32_t TSAR29 : 1; - __IO uint32_t TSAR30 : 1; - __IO uint32_t TSAR31 : 1; -} stc_ethernet_mac_tsar_field_t; - -typedef struct stc_ethernet_mac_ttsr_field -{ - __IO uint32_t TSTR0 : 1; - __IO uint32_t TSTR1 : 1; - __IO uint32_t TSTR2 : 1; - __IO uint32_t TSTR3 : 1; - __IO uint32_t TSTR4 : 1; - __IO uint32_t TSTR5 : 1; - __IO uint32_t TSTR6 : 1; - __IO uint32_t TSTR7 : 1; - __IO uint32_t TSTR8 : 1; - __IO uint32_t TSTR9 : 1; - __IO uint32_t TSTR10 : 1; - __IO uint32_t TSTR11 : 1; - __IO uint32_t TSTR12 : 1; - __IO uint32_t TSTR13 : 1; - __IO uint32_t TSTR14 : 1; - __IO uint32_t TSTR15 : 1; - __IO uint32_t TSTR16 : 1; - __IO uint32_t TSTR17 : 1; - __IO uint32_t TSTR18 : 1; - __IO uint32_t TSTR19 : 1; - __IO uint32_t TSTR20 : 1; - __IO uint32_t TSTR21 : 1; - __IO uint32_t TSTR22 : 1; - __IO uint32_t TSTR23 : 1; - __IO uint32_t TSTR24 : 1; - __IO uint32_t TSTR25 : 1; - __IO uint32_t TSTR26 : 1; - __IO uint32_t TSTR27 : 1; - __IO uint32_t TSTR28 : 1; - __IO uint32_t TSTR29 : 1; - __IO uint32_t TSTR30 : 1; - __IO uint32_t TSTR31 : 1; -} stc_ethernet_mac_ttsr_field_t; - -typedef struct stc_ethernet_mac_ttnr_field -{ - __IO uint32_t TSTR0 : 1; - __IO uint32_t TSTR1 : 1; - __IO uint32_t TSTR2 : 1; - __IO uint32_t TSTR3 : 1; - __IO uint32_t TSTR4 : 1; - __IO uint32_t TSTR5 : 1; - __IO uint32_t TSTR6 : 1; - __IO uint32_t TSTR7 : 1; - __IO uint32_t TSTR8 : 1; - __IO uint32_t TSTR9 : 1; - __IO uint32_t TSTR10 : 1; - __IO uint32_t TSTR11 : 1; - __IO uint32_t TSTR12 : 1; - __IO uint32_t TSTR13 : 1; - __IO uint32_t TSTR14 : 1; - __IO uint32_t TSTR15 : 1; - __IO uint32_t TSTR16 : 1; - __IO uint32_t TSTR17 : 1; - __IO uint32_t TSTR18 : 1; - __IO uint32_t TSTR19 : 1; - __IO uint32_t TSTR20 : 1; - __IO uint32_t TSTR21 : 1; - __IO uint32_t TSTR22 : 1; - __IO uint32_t TSTR23 : 1; - __IO uint32_t TSTR24 : 1; - __IO uint32_t TSTR25 : 1; - __IO uint32_t TSTR26 : 1; - __IO uint32_t TSTR27 : 1; - __IO uint32_t TSTR28 : 1; - __IO uint32_t TSTR29 : 1; - __IO uint32_t TSTR30 : 1; -} stc_ethernet_mac_ttnr_field_t; - -typedef struct stc_ethernet_mac_sthwsr_field -{ - __IO uint32_t TSHWR0 : 1; - __IO uint32_t TSHWR1 : 1; - __IO uint32_t TSHWR2 : 1; - __IO uint32_t TSHWR3 : 1; - __IO uint32_t TSHWR4 : 1; - __IO uint32_t TSHWR5 : 1; - __IO uint32_t TSHWR6 : 1; - __IO uint32_t TSHWR7 : 1; - __IO uint32_t TSHWR8 : 1; - __IO uint32_t TSHWR9 : 1; - __IO uint32_t TSHWR10 : 1; - __IO uint32_t TSHWR11 : 1; - __IO uint32_t TSHWR12 : 1; - __IO uint32_t TSHWR13 : 1; - __IO uint32_t TSHWR14 : 1; - __IO uint32_t TSHWR15 : 1; -} stc_ethernet_mac_sthwsr_field_t; - -typedef struct stc_ethernet_mac_tsr_field -{ - __IO uint32_t TSSOVF : 1; - __IO uint32_t TSTART : 1; - __IO uint32_t ATSTS : 1; - __IO uint32_t TRGTER : 1; - uint32_t RESERVED1 :20; - __IO uint32_t ATSSTM : 1; - __IO uint32_t ATSNS0 : 1; - __IO uint32_t ATSNS1 : 1; - __IO uint32_t ATSNS2 : 1; -} stc_ethernet_mac_tsr_field_t; - -typedef struct stc_ethernet_mac_ppscr_field -{ - __IO uint32_t PPSCTRL0 : 1; - __IO uint32_t PPSCTRL1 : 1; - __IO uint32_t PPSCTRL2 : 1; - __IO uint32_t PPSCTRL3 : 1; -} stc_ethernet_mac_ppscr_field_t; - -typedef struct stc_ethernet_mac_atnr_field -{ - __IO uint32_t ATN0 : 1; - __IO uint32_t ATN1 : 1; - __IO uint32_t ATN2 : 1; - __IO uint32_t ATN3 : 1; - __IO uint32_t ATN4 : 1; - __IO uint32_t ATN5 : 1; - __IO uint32_t ATN6 : 1; - __IO uint32_t ATN7 : 1; - __IO uint32_t ATN8 : 1; - __IO uint32_t ATN9 : 1; - __IO uint32_t ATN10 : 1; - __IO uint32_t ATN11 : 1; - __IO uint32_t ATN12 : 1; - __IO uint32_t ATN13 : 1; - __IO uint32_t ATN14 : 1; - __IO uint32_t ATN15 : 1; - __IO uint32_t ATN16 : 1; - __IO uint32_t ATN17 : 1; - __IO uint32_t ATN18 : 1; - __IO uint32_t ATN19 : 1; - __IO uint32_t ATN20 : 1; - __IO uint32_t ATN21 : 1; - __IO uint32_t ATN22 : 1; - __IO uint32_t ATN23 : 1; - __IO uint32_t ATN24 : 1; - __IO uint32_t ATN25 : 1; - __IO uint32_t ATN26 : 1; - __IO uint32_t ATN27 : 1; - __IO uint32_t ATN28 : 1; - __IO uint32_t ATN29 : 1; - __IO uint32_t ATN30 : 1; -} stc_ethernet_mac_atnr_field_t; - -typedef struct stc_ethernet_mac_atsr_field -{ - __IO uint32_t ATS0 : 1; - __IO uint32_t ATS1 : 1; - __IO uint32_t ATS2 : 1; - __IO uint32_t ATS3 : 1; - __IO uint32_t ATS4 : 1; - __IO uint32_t ATS5 : 1; - __IO uint32_t ATS6 : 1; - __IO uint32_t ATS7 : 1; - __IO uint32_t ATS8 : 1; - __IO uint32_t ATS9 : 1; - __IO uint32_t ATS10 : 1; - __IO uint32_t ATS11 : 1; - __IO uint32_t ATS12 : 1; - __IO uint32_t ATS13 : 1; - __IO uint32_t ATS14 : 1; - __IO uint32_t ATS15 : 1; - __IO uint32_t ATS16 : 1; - __IO uint32_t ATS17 : 1; - __IO uint32_t ATS18 : 1; - __IO uint32_t ATS19 : 1; - __IO uint32_t ATS20 : 1; - __IO uint32_t ATS21 : 1; - __IO uint32_t ATS22 : 1; - __IO uint32_t ATS23 : 1; - __IO uint32_t ATS24 : 1; - __IO uint32_t ATS25 : 1; - __IO uint32_t ATS26 : 1; - __IO uint32_t ATS27 : 1; - __IO uint32_t ATS28 : 1; - __IO uint32_t ATS29 : 1; - __IO uint32_t ATS30 : 1; - __IO uint32_t ATS31 : 1; -} stc_ethernet_mac_atsr_field_t; - -typedef struct stc_ethernet_mac_mar16h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar16h_field_t; - -typedef struct stc_ethernet_mac_mar16l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar16l_field_t; - -typedef struct stc_ethernet_mac_mar17h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar17h_field_t; - -typedef struct stc_ethernet_mac_mar17l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar17l_field_t; - -typedef struct stc_ethernet_mac_mar18h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar18h_field_t; - -typedef struct stc_ethernet_mac_mar18l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar18l_field_t; - -typedef struct stc_ethernet_mac_mar19h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar19h_field_t; - -typedef struct stc_ethernet_mac_mar19l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar19l_field_t; - -typedef struct stc_ethernet_mac_mar20h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar20h_field_t; - -typedef struct stc_ethernet_mac_mar20l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar20l_field_t; - -typedef struct stc_ethernet_mac_mar21h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar21h_field_t; - -typedef struct stc_ethernet_mac_mar21l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar21l_field_t; - -typedef struct stc_ethernet_mac_mar22h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar22h_field_t; - -typedef struct stc_ethernet_mac_mar22l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar22l_field_t; - -typedef struct stc_ethernet_mac_mar23h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar23h_field_t; - -typedef struct stc_ethernet_mac_mar23l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar23l_field_t; - -typedef struct stc_ethernet_mac_mar24h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar24h_field_t; - -typedef struct stc_ethernet_mac_mar24l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar24l_field_t; - -typedef struct stc_ethernet_mac_mar25h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar25h_field_t; - -typedef struct stc_ethernet_mac_mar25l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar25l_field_t; - -typedef struct stc_ethernet_mac_mar26h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar26h_field_t; - -typedef struct stc_ethernet_mac_mar26l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar26l_field_t; - -typedef struct stc_ethernet_mac_mar27h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar27h_field_t; - -typedef struct stc_ethernet_mac_mar27l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar27l_field_t; - -typedef struct stc_ethernet_mac_mar28h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar28h_field_t; - -typedef struct stc_ethernet_mac_mar28l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar28l_field_t; - -typedef struct stc_ethernet_mac_mar29h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar29h_field_t; - -typedef struct stc_ethernet_mac_mar29l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar29l_field_t; - -typedef struct stc_ethernet_mac_mar30h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar30h_field_t; - -typedef struct stc_ethernet_mac_mar30l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar30l_field_t; - -typedef struct stc_ethernet_mac_mar31h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar31h_field_t; - -typedef struct stc_ethernet_mac_mar31l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar31l_field_t; - -typedef struct stc_ethernet_mac_bmr_field -{ - __IO uint32_t SWR : 1; - __IO uint32_t DA : 1; - __IO uint32_t DSL0 : 1; - __IO uint32_t DSL1 : 1; - __IO uint32_t DSL2 : 1; - __IO uint32_t DSL3 : 1; - __IO uint32_t DSL4 : 1; - __IO uint32_t ATDS : 1; - __IO uint32_t PBL0 : 1; - __IO uint32_t PBL1 : 1; - __IO uint32_t PBL2 : 1; - __IO uint32_t PBL3 : 1; - __IO uint32_t PBL4 : 1; - __IO uint32_t PBL5 : 1; - __IO uint32_t PR0 : 1; - __IO uint32_t PR1 : 1; - __IO uint32_t FB : 1; - __IO uint32_t RPBL0 : 1; - __IO uint32_t RPBL1 : 1; - __IO uint32_t RPBL2 : 1; - __IO uint32_t RPBL3 : 1; - __IO uint32_t RPBL4 : 1; - __IO uint32_t RPBL5 : 1; - __IO uint32_t USP : 1; - __IO uint32_t _8XPBL : 1; - __IO uint32_t AAL : 1; - __IO uint32_t MB : 1; - __IO uint32_t TXPR : 1; -} stc_ethernet_mac_bmr_field_t; - -typedef struct stc_ethernet_mac_tpdr_field -{ - __IO uint32_t TPD0 : 1; - __IO uint32_t TPD1 : 1; - __IO uint32_t TPD2 : 1; - __IO uint32_t TPD3 : 1; - __IO uint32_t TPD4 : 1; - __IO uint32_t TPD5 : 1; - __IO uint32_t TPD6 : 1; - __IO uint32_t TPD7 : 1; - __IO uint32_t TPD8 : 1; - __IO uint32_t TPD9 : 1; - __IO uint32_t TPD10 : 1; - __IO uint32_t TPD11 : 1; - __IO uint32_t TPD12 : 1; - __IO uint32_t TPD13 : 1; - __IO uint32_t TPD14 : 1; - __IO uint32_t TPD15 : 1; - __IO uint32_t TPD16 : 1; - __IO uint32_t TPD17 : 1; - __IO uint32_t TPD18 : 1; - __IO uint32_t TPD19 : 1; - __IO uint32_t TPD20 : 1; - __IO uint32_t TPD21 : 1; - __IO uint32_t TPD22 : 1; - __IO uint32_t TPD23 : 1; - __IO uint32_t TPD24 : 1; - __IO uint32_t TPD25 : 1; - __IO uint32_t TPD26 : 1; - __IO uint32_t TPD27 : 1; - __IO uint32_t TPD28 : 1; - __IO uint32_t TPD29 : 1; - __IO uint32_t TPD30 : 1; - __IO uint32_t TPD31 : 1; -} stc_ethernet_mac_tpdr_field_t; - -typedef struct stc_ethernet_mac_rpdr_field -{ - __IO uint32_t RPD0 : 1; - __IO uint32_t RPD1 : 1; - __IO uint32_t RPD2 : 1; - __IO uint32_t RPD3 : 1; - __IO uint32_t RPD4 : 1; - __IO uint32_t RPD5 : 1; - __IO uint32_t RPD6 : 1; - __IO uint32_t RPD7 : 1; - __IO uint32_t RPD8 : 1; - __IO uint32_t RPD9 : 1; - __IO uint32_t RPD10 : 1; - __IO uint32_t RPD11 : 1; - __IO uint32_t RPD12 : 1; - __IO uint32_t RPD13 : 1; - __IO uint32_t RPD14 : 1; - __IO uint32_t RPD15 : 1; - __IO uint32_t RPD16 : 1; - __IO uint32_t RPD17 : 1; - __IO uint32_t RPD18 : 1; - __IO uint32_t RPD19 : 1; - __IO uint32_t RPD20 : 1; - __IO uint32_t RPD21 : 1; - __IO uint32_t RPD22 : 1; - __IO uint32_t RPD23 : 1; - __IO uint32_t RPD24 : 1; - __IO uint32_t RPD25 : 1; - __IO uint32_t RPD26 : 1; - __IO uint32_t RPD27 : 1; - __IO uint32_t RPD28 : 1; - __IO uint32_t RPD29 : 1; - __IO uint32_t RPD30 : 1; - __IO uint32_t RPD31 : 1; -} stc_ethernet_mac_rpdr_field_t; - -typedef struct stc_ethernet_mac_rdlar_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t SRL2 : 1; - __IO uint32_t SRL3 : 1; - __IO uint32_t SRL4 : 1; - __IO uint32_t SRL5 : 1; - __IO uint32_t SRL6 : 1; - __IO uint32_t SRL7 : 1; - __IO uint32_t SRL8 : 1; - __IO uint32_t SRL9 : 1; - __IO uint32_t SRL10 : 1; - __IO uint32_t SRL11 : 1; - __IO uint32_t SRL12 : 1; - __IO uint32_t SRL13 : 1; - __IO uint32_t SRL14 : 1; - __IO uint32_t SRL15 : 1; - __IO uint32_t SRL16 : 1; - __IO uint32_t SRL17 : 1; - __IO uint32_t SRL18 : 1; - __IO uint32_t SRL19 : 1; - __IO uint32_t SRL20 : 1; - __IO uint32_t SRL21 : 1; - __IO uint32_t SRL22 : 1; - __IO uint32_t SRL23 : 1; - __IO uint32_t SRL24 : 1; - __IO uint32_t SRL25 : 1; - __IO uint32_t SRL26 : 1; - __IO uint32_t SRL27 : 1; - __IO uint32_t SRL28 : 1; - __IO uint32_t SRL29 : 1; - __IO uint32_t SRL30 : 1; - __IO uint32_t SRL31 : 1; -} stc_ethernet_mac_rdlar_field_t; - -typedef struct stc_ethernet_mac_tdlar_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t STL2 : 1; - __IO uint32_t STL3 : 1; - __IO uint32_t STL4 : 1; - __IO uint32_t STL5 : 1; - __IO uint32_t STL6 : 1; - __IO uint32_t STL7 : 1; - __IO uint32_t STL8 : 1; - __IO uint32_t STL9 : 1; - __IO uint32_t STL10 : 1; - __IO uint32_t STL11 : 1; - __IO uint32_t STL12 : 1; - __IO uint32_t STL13 : 1; - __IO uint32_t STL14 : 1; - __IO uint32_t STL15 : 1; - __IO uint32_t STL16 : 1; - __IO uint32_t STL17 : 1; - __IO uint32_t STL18 : 1; - __IO uint32_t STL19 : 1; - __IO uint32_t STL20 : 1; - __IO uint32_t STL21 : 1; - __IO uint32_t STL22 : 1; - __IO uint32_t STL23 : 1; - __IO uint32_t STL24 : 1; - __IO uint32_t STL25 : 1; - __IO uint32_t STL26 : 1; - __IO uint32_t STL27 : 1; - __IO uint32_t STL28 : 1; - __IO uint32_t STL29 : 1; - __IO uint32_t STL30 : 1; - __IO uint32_t STL31 : 1; -} stc_ethernet_mac_tdlar_field_t; - -typedef struct stc_ethernet_mac_sr_field -{ - __IO uint32_t TI : 1; - __IO uint32_t TPS : 1; - __IO uint32_t TU : 1; - __IO uint32_t TJT : 1; - __IO uint32_t OVF : 1; - __IO uint32_t UNF : 1; - __IO uint32_t RI : 1; - __IO uint32_t RU : 1; - __IO uint32_t RPS : 1; - __IO uint32_t RWT : 1; - __IO uint32_t ETI : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t FBI : 1; - __IO uint32_t ERI : 1; - __IO uint32_t AIS : 1; - __IO uint32_t NIS : 1; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - __IO uint32_t TS0 : 1; - __IO uint32_t TS1 : 1; - __IO uint32_t TS2 : 1; - __IO uint32_t EB0 : 1; - __IO uint32_t EB1 : 1; - __IO uint32_t EB2 : 1; - __IO uint32_t GLI : 1; - __IO uint32_t GMI : 1; - __IO uint32_t GPI : 1; - __IO uint32_t TTI : 1; - __IO uint32_t GLPII : 1; -} stc_ethernet_mac_sr_field_t; - -typedef struct stc_ethernet_mac_omr_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t SR : 1; - __IO uint32_t OSF : 1; - __IO uint32_t RTC0 : 1; - __IO uint32_t RTC1 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t FUF : 1; - __IO uint32_t FEF : 1; - uint32_t RESERVED3 : 5; - __IO uint32_t ST : 1; - __IO uint32_t TTC0 : 1; - __IO uint32_t TTC1 : 1; - __IO uint32_t TTC2 : 1; - uint32_t RESERVED4 : 3; - __IO uint32_t FTF : 1; - __IO uint32_t TSF : 1; - uint32_t RESERVED5 : 2; - __IO uint32_t DFF : 1; - __IO uint32_t RSF : 1; - __IO uint32_t DT : 1; -} stc_ethernet_mac_omr_field_t; - -typedef struct stc_ethernet_mac_ier_field -{ - __IO uint32_t TIE : 1; - __IO uint32_t TSE : 1; - __IO uint32_t TUE : 1; - __IO uint32_t TJE : 1; - __IO uint32_t OVE : 1; - __IO uint32_t UNE : 1; - __IO uint32_t RIE : 1; - __IO uint32_t RUE : 1; - __IO uint32_t RSE : 1; - __IO uint32_t RWE : 1; - __IO uint32_t ETE : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t FBE : 1; - __IO uint32_t ERE : 1; - __IO uint32_t AIE : 1; - __IO uint32_t NIE : 1; -} stc_ethernet_mac_ier_field_t; - -typedef struct stc_ethernet_mac_mfbocr_field -{ - __IO uint32_t NMFH0 : 1; - __IO uint32_t NMFH1 : 1; - __IO uint32_t NMFH2 : 1; - __IO uint32_t NMFH3 : 1; - __IO uint32_t NMFH4 : 1; - __IO uint32_t NMFH5 : 1; - __IO uint32_t NMFH6 : 1; - __IO uint32_t NMFH7 : 1; - __IO uint32_t NMFH8 : 1; - __IO uint32_t NMFH9 : 1; - __IO uint32_t NMFH10 : 1; - __IO uint32_t NMFH11 : 1; - __IO uint32_t NMFH12 : 1; - __IO uint32_t NMFH13 : 1; - __IO uint32_t NMFH14 : 1; - __IO uint32_t NMFH15 : 1; - __IO uint32_t ONMFH : 1; - __IO uint32_t NMFF0 : 1; - __IO uint32_t NMFF1 : 1; - __IO uint32_t NMFF2 : 1; - __IO uint32_t NMFF3 : 1; - __IO uint32_t NMFF4 : 1; - __IO uint32_t NMFF5 : 1; - __IO uint32_t NMFF6 : 1; - __IO uint32_t NMFF7 : 1; - __IO uint32_t NMFF8 : 1; - __IO uint32_t NMFF9 : 1; - __IO uint32_t NMFF10 : 1; - __IO uint32_t ONMFF : 1; -} stc_ethernet_mac_mfbocr_field_t; - -typedef struct stc_ethernet_mac_riwtr_field -{ - __IO uint32_t RIWT0 : 1; - __IO uint32_t RIWT1 : 1; - __IO uint32_t RIWT2 : 1; - __IO uint32_t RIWT3 : 1; - __IO uint32_t RIWT4 : 1; - __IO uint32_t RIWT5 : 1; - __IO uint32_t RIWT6 : 1; - __IO uint32_t RIWT7 : 1; -} stc_ethernet_mac_riwtr_field_t; - -typedef struct stc_ethernet_mac_ahbsr_field -{ - __IO uint32_t AHBS : 1; -} stc_ethernet_mac_ahbsr_field_t; - -typedef struct stc_ethernet_mac_chtdr_field -{ - __IO uint32_t HTDAP0 : 1; - __IO uint32_t HTDAP1 : 1; - __IO uint32_t HTDAP2 : 1; - __IO uint32_t HTDAP3 : 1; - __IO uint32_t HTDAP4 : 1; - __IO uint32_t HTDAP5 : 1; - __IO uint32_t HTDAP6 : 1; - __IO uint32_t HTDAP7 : 1; - __IO uint32_t HTDAP8 : 1; - __IO uint32_t HTDAP9 : 1; - __IO uint32_t HTDAP10 : 1; - __IO uint32_t HTDAP11 : 1; - __IO uint32_t HTDAP12 : 1; - __IO uint32_t HTDAP13 : 1; - __IO uint32_t HTDAP14 : 1; - __IO uint32_t HTDAP15 : 1; - __IO uint32_t HTDAP16 : 1; - __IO uint32_t HTDAP17 : 1; - __IO uint32_t HTDAP18 : 1; - __IO uint32_t HTDAP19 : 1; - __IO uint32_t HTDAP20 : 1; - __IO uint32_t HTDAP21 : 1; - __IO uint32_t HTDAP22 : 1; - __IO uint32_t HTDAP23 : 1; - __IO uint32_t HTDAP24 : 1; - __IO uint32_t HTDAP25 : 1; - __IO uint32_t HTDAP26 : 1; - __IO uint32_t HTDAP27 : 1; - __IO uint32_t HTDAP28 : 1; - __IO uint32_t HTDAP29 : 1; - __IO uint32_t HTDAP30 : 1; - __IO uint32_t HTDAP31 : 1; -} stc_ethernet_mac_chtdr_field_t; - -typedef struct stc_ethernet_mac_chrdr_field -{ - __IO uint32_t HRDAP0 : 1; - __IO uint32_t HRDAP1 : 1; - __IO uint32_t HRDAP2 : 1; - __IO uint32_t HRDAP3 : 1; - __IO uint32_t HRDAP4 : 1; - __IO uint32_t HRDAP5 : 1; - __IO uint32_t HRDAP6 : 1; - __IO uint32_t HRDAP7 : 1; - __IO uint32_t HRDAP8 : 1; - __IO uint32_t HRDAP9 : 1; - __IO uint32_t HRDAP10 : 1; - __IO uint32_t HRDAP11 : 1; - __IO uint32_t HRDAP12 : 1; - __IO uint32_t HRDAP13 : 1; - __IO uint32_t HRDAP14 : 1; - __IO uint32_t HRDAP15 : 1; - __IO uint32_t HRDAP16 : 1; - __IO uint32_t HRDAP17 : 1; - __IO uint32_t HRDAP18 : 1; - __IO uint32_t HRDAP19 : 1; - __IO uint32_t HRDAP20 : 1; - __IO uint32_t HRDAP21 : 1; - __IO uint32_t HRDAP22 : 1; - __IO uint32_t HRDAP23 : 1; - __IO uint32_t HRDAP24 : 1; - __IO uint32_t HRDAP25 : 1; - __IO uint32_t HRDAP26 : 1; - __IO uint32_t HRDAP27 : 1; - __IO uint32_t HRDAP28 : 1; - __IO uint32_t HRDAP29 : 1; - __IO uint32_t HRDAP30 : 1; - __IO uint32_t HRDAP31 : 1; -} stc_ethernet_mac_chrdr_field_t; - -typedef struct stc_ethernet_mac_chtbar_field -{ - __IO uint32_t HTBAR0 : 1; - __IO uint32_t HTBAR1 : 1; - __IO uint32_t HTBAR2 : 1; - __IO uint32_t HTBAR3 : 1; - __IO uint32_t HTBAR4 : 1; - __IO uint32_t HTBAR5 : 1; - __IO uint32_t HTBAR6 : 1; - __IO uint32_t HTBAR7 : 1; - __IO uint32_t HTBAR8 : 1; - __IO uint32_t HTBAR9 : 1; - __IO uint32_t HTBAR10 : 1; - __IO uint32_t HTBAR11 : 1; - __IO uint32_t HTBAR12 : 1; - __IO uint32_t HTBAR13 : 1; - __IO uint32_t HTBAR14 : 1; - __IO uint32_t HTBAR15 : 1; - __IO uint32_t HTBAR16 : 1; - __IO uint32_t HTBAR17 : 1; - __IO uint32_t HTBAR18 : 1; - __IO uint32_t HTBAR19 : 1; - __IO uint32_t HTBAR20 : 1; - __IO uint32_t HTBAR21 : 1; - __IO uint32_t HTBAR22 : 1; - __IO uint32_t HTBAR23 : 1; - __IO uint32_t HTBAR24 : 1; - __IO uint32_t HTBAR25 : 1; - __IO uint32_t HTBAR26 : 1; - __IO uint32_t HTBAR27 : 1; - __IO uint32_t HTBAR28 : 1; - __IO uint32_t HTBAR29 : 1; - __IO uint32_t HTBAR30 : 1; - __IO uint32_t HTBAR31 : 1; -} stc_ethernet_mac_chtbar_field_t; - -typedef struct stc_ethernet_mac_chrbar_field -{ - __IO uint32_t HRBAR0 : 1; - __IO uint32_t HRBAR1 : 1; - __IO uint32_t HRBAR2 : 1; - __IO uint32_t HRBAR3 : 1; - __IO uint32_t HRBAR4 : 1; - __IO uint32_t HRBAR5 : 1; - __IO uint32_t HRBAR6 : 1; - __IO uint32_t HRBAR7 : 1; - __IO uint32_t HRBAR8 : 1; - __IO uint32_t HRBAR9 : 1; - __IO uint32_t HRBAR10 : 1; - __IO uint32_t HRBAR11 : 1; - __IO uint32_t HRBAR12 : 1; - __IO uint32_t HRBAR13 : 1; - __IO uint32_t HRBAR14 : 1; - __IO uint32_t HRBAR15 : 1; - __IO uint32_t HRBAR16 : 1; - __IO uint32_t HRBAR17 : 1; - __IO uint32_t HRBAR18 : 1; - __IO uint32_t HRBAR19 : 1; - __IO uint32_t HRBAR20 : 1; - __IO uint32_t HRBAR21 : 1; - __IO uint32_t HRBAR22 : 1; - __IO uint32_t HRBAR23 : 1; - __IO uint32_t HRBAR24 : 1; - __IO uint32_t HRBAR25 : 1; - __IO uint32_t HRBAR26 : 1; - __IO uint32_t HRBAR27 : 1; - __IO uint32_t HRBAR28 : 1; - __IO uint32_t HRBAR29 : 1; - __IO uint32_t HRBAR30 : 1; - __IO uint32_t HRBAR31 : 1; -} stc_ethernet_mac_chrbar_field_t; - -/* ETHERNET_CONTROL_MODULE register bit fields */ -typedef struct stc_ethernet_control_eth_mode_field -{ - __IO uint32_t IFMODE : 1; - uint32_t RESERVED1 : 7; - __IO uint32_t RST0 : 1; - __IO uint32_t RST1 : 1; - uint32_t RESERVED2 :18; - __IO uint32_t ASZPPSSEL : 1; -} stc_ethernet_control_eth_mode_field_t; - -typedef struct stc_ethernet_control_eth_clkg_field -{ - __IO uint32_t MACEN0 : 1; - __IO uint32_t MACEN1 : 1; -} stc_ethernet_control_eth_clkg_field_t; - -/****************************************************************************** - * Peripheral register structures - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - union { - __IO uint32_t FASZR; - stc_flash_if_faszr_field_t FASZR_f; - }; - union { - __IO uint32_t FRWTR; - stc_flash_if_frwtr_field_t FRWTR_f; - }; - union { - __IO uint32_t FSTR; - stc_flash_if_fstr_field_t FSTR_f; - }; - uint8_t RESERVED0[4]; - union { - __IO uint32_t FSYNDN; - stc_flash_if_fsyndn_field_t FSYNDN_f; - }; - uint8_t RESERVED1[236]; - union { - __IO uint32_t CRTRMM; - stc_flash_if_crtrmm_field_t CRTRMM_f; - }; -}FM3_FLASH_IF_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - union { - __IO uint8_t SCM_CTL; - stc_crg_scm_ctl_field_t SCM_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t SCM_STR; - stc_crg_scm_str_field_t SCM_STR_f; - }; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - union { - __IO uint16_t RST_STR; - stc_crg_rst_str_field_t RST_STR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t BSC_PSR; - stc_crg_bsc_psr_field_t BSC_PSR_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t APBC0_PSR; - stc_crg_apbc0_psr_field_t APBC0_PSR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t APBC1_PSR; - stc_crg_apbc1_psr_field_t APBC1_PSR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t APBC2_PSR; - stc_crg_apbc2_psr_field_t APBC2_PSR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t SWC_PSR; - stc_crg_swc_psr_field_t SWC_PSR_f; - }; - uint8_t RESERVED7[7]; - union { - __IO uint8_t TTC_PSR; - stc_crg_ttc_psr_field_t TTC_PSR_f; - }; - uint8_t RESERVED8[7]; - union { - __IO uint8_t CSW_TMR; - stc_crg_csw_tmr_field_t CSW_TMR_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t PSW_TMR; - stc_crg_psw_tmr_field_t PSW_TMR_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PLL_CTL1; - stc_crg_pll_ctl1_field_t PLL_CTL1_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t PLL_CTL2; - stc_crg_pll_ctl2_field_t PLL_CTL2_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint16_t CSV_CTL; - stc_crg_csv_ctl_field_t CSV_CTL_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint8_t CSV_STR; - stc_crg_csv_str_field_t CSV_STR_f; - }; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - union { - __IO uint8_t DBWDT_CTL; - stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; - }; - uint8_t RESERVED18[11]; - union { - __IO uint8_t INT_ENR; - stc_crg_int_enr_field_t INT_ENR_f; - }; - uint8_t RESERVED19[3]; - union { - __IO uint8_t INT_STR; - stc_crg_int_str_field_t INT_STR_f; - }; - uint8_t RESERVED20[3]; - union { - __IO uint8_t INT_CLR; - stc_crg_int_clr_field_t INT_CLR_f; - }; -}FM3_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - union { - __IO uint8_t WDG_CTL; - stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; - }; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WDG_RIS; - stc_hwwdt_wdg_ris_field_t WDG_RIS_f; - }; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM3_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - union { - __IO uint8_t WDOGCONTROL; - stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - union { - __IO uint8_t WDOGRIS; - stc_swwdt_wdogris_field_t WDOGRIS_f; - }; - uint8_t RESERVED1[3055]; - __IO uint32_t WDOGLOCK; -}FM3_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMER1LOAD; - __IO uint32_t TIMER1VALUE; - union { - __IO uint32_t TIMER1CONTROL; - stc_dtim_timer1control_field_t TIMER1CONTROL_f; - }; - __IO uint32_t TIMER1INTCLR; - union { - __IO uint32_t TIMER1RIS; - stc_dtim_timer1ris_field_t TIMER1RIS_f; - }; - union { - __IO uint32_t TIMER1MIS; - stc_dtim_timer1mis_field_t TIMER1MIS_f; - }; - __IO uint32_t TIMER1BGLOAD; - uint8_t RESERVED0[4]; - __IO uint32_t TIMER2LOAD; - __IO uint32_t TIMER2VALUE; - union { - __IO uint32_t TIMER2CONTROL; - stc_dtim_timer2control_field_t TIMER2CONTROL_f; - }; - __IO uint32_t TIMER2INTCLR; - union { - __IO uint32_t TIMER2RIS; - stc_dtim_timer2ris_field_t TIMER2RIS_f; - }; - union { - __IO uint32_t TIMER2MIS; - stc_dtim_timer2mis_field_t TIMER2MIS_f; - }; - __IO uint32_t TIMER2BGLOAD; -}FM3_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[40]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TCSA0; - stc_mft_frt_tcsa0_field_t TCSA0_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t TCSB0; - stc_mft_frt_tcsb0_field_t TCSB0_f; - }; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT1; - uint8_t RESERVED6[2]; - union { - __IO uint16_t TCSA1; - stc_mft_frt_tcsa1_field_t TCSA1_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t TCSB1; - stc_mft_frt_tcsb1_field_t TCSB1_f; - }; - uint8_t RESERVED8[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED9[2]; - __IO uint16_t TCDT2; - uint8_t RESERVED10[2]; - union { - __IO uint16_t TCSA2; - stc_mft_frt_tcsa2_field_t TCSA2_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t TCSB2; - stc_mft_frt_tcsb2_field_t TCSB2_f; - }; -}FM3_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - __IO uint16_t OCCP0; - uint8_t RESERVED0[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP5; - uint8_t RESERVED5[2]; - union { - __IO uint8_t OCSA10; - stc_mft_ocu_ocsa10_field_t OCSA10_f; - }; - union { - __IO uint8_t OCSB10; - stc_mft_ocu_ocsb10_field_t OCSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t OCSA32; - stc_mft_ocu_ocsa32_field_t OCSA32_f; - }; - union { - __IO uint8_t OCSB32; - stc_mft_ocu_ocsb32_field_t OCSB32_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint8_t OCSA54; - stc_mft_ocu_ocsa54_field_t OCSA54_f; - }; - union { - __IO uint8_t OCSB54; - stc_mft_ocu_ocsb54_field_t OCSB54_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t OCSC; - stc_mft_ocu_ocsc_field_t OCSC_f; - }; - uint8_t RESERVED9[50]; - union { - __IO uint8_t OCFS10; - stc_mft_ocu_ocfs10_field_t OCFS10_f; - }; - union { - __IO uint8_t OCFS32; - stc_mft_ocu_ocfs32_field_t OCFS32_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint8_t OCFS54; - stc_mft_ocu_ocfs54_field_t OCFS54_f; - }; -}FM3_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[128]; - __IO uint16_t WFTM10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTM32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTM54; - uint8_t RESERVED3[2]; - union { - __IO uint16_t WFSA10; - stc_mft_wfg_wfsa10_field_t WFSA10_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t WFSA32; - stc_mft_wfg_wfsa32_field_t WFSA32_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t WFSA54; - stc_mft_wfg_wfsa54_field_t WFSA54_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t WFIR; - stc_mft_wfg_wfir_field_t WFIR_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t NZCL; - stc_mft_wfg_nzcl_field_t NZCL_f; - }; -}FM3_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[96]; - union { - __IO uint8_t ICFS10; - stc_mft_icu_icfs10_field_t ICFS10_f; - }; - union { - __IO uint8_t ICFS32; - stc_mft_icu_icfs32_field_t ICFS32_f; - }; - uint8_t RESERVED1[6]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - uint8_t RESERVED5[2]; - union { - __IO uint8_t ICSA10; - stc_mft_icu_icsa10_field_t ICSA10_f; - }; - union { - __IO uint8_t ICSB10; - stc_mft_icu_icsb10_field_t ICSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ICSA32; - stc_mft_icu_icsa32_field_t ICSA32_f; - }; - union { - __IO uint8_t ICSB32; - stc_mft_icu_icsb32_field_t ICSB32_f; - }; -}FM3_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[160]; - __IO uint16_t ACCP0; - uint8_t RESERVED1[2]; - __IO uint16_t ACCPDN0; - uint8_t RESERVED2[2]; - __IO uint16_t ACCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACCPDN1; - uint8_t RESERVED4[2]; - __IO uint16_t ACCP2; - uint8_t RESERVED5[2]; - __IO uint16_t ACCPDN2; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ACSB; - stc_mft_adcmp_acsb_field_t ACSB_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t ACSA; - stc_mft_adcmp_acsa_field_t ACSA_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t ATSA; - stc_mft_adcmp_atsa_field_t ATSA_f; - }; -}FM3_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t TTCR0; - stc_mft_ppg_ttcr0_field_t TTCR0_f; - }; - uint8_t RESERVED1[7]; - __IO uint8_t COMP0; - uint8_t RESERVED2[2]; - __IO uint8_t COMP2; - uint8_t RESERVED3[4]; - __IO uint8_t COMP4; - uint8_t RESERVED4[2]; - __IO uint8_t COMP6; - uint8_t RESERVED5[12]; - union { - __IO uint8_t TTCR1; - stc_mft_ppg_ttcr1_field_t TTCR1_f; - }; - uint8_t RESERVED6[7]; - __IO uint8_t COMP1; - uint8_t RESERVED7[2]; - __IO uint8_t COMP3; - uint8_t RESERVED8[4]; - __IO uint8_t COMP5; - uint8_t RESERVED9[2]; - __IO uint8_t COMP7; - uint8_t RESERVED10[12]; - union { - __IO uint8_t TTCR2; - stc_mft_ppg_ttcr2_field_t TTCR2_f; - }; - uint8_t RESERVED11[7]; - __IO uint8_t COMP8; - uint8_t RESERVED12[2]; - __IO uint8_t COMP10; - uint8_t RESERVED13[4]; - __IO uint8_t COMP12; - uint8_t RESERVED14[2]; - __IO uint8_t COMP14; - uint8_t RESERVED15[171]; - union { - __IO uint16_t TRG; - stc_mft_ppg_trg_field_t TRG_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t REVC; - stc_mft_ppg_revc_field_t REVC_f; - }; - uint8_t RESERVED17[58]; - union { - __IO uint16_t TRG1; - stc_mft_ppg_trg1_field_t TRG1_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t REVC1; - stc_mft_ppg_revc1_field_t REVC1_f; - }; - uint8_t RESERVED19[186]; - union { - __IO uint8_t PPGC1; - stc_mft_ppg_ppgc1_field_t PPGC1_f; - }; - union { - __IO uint8_t PPGC0; - stc_mft_ppg_ppgc0_field_t PPGC0_f; - }; - uint8_t RESERVED20[2]; - union { - __IO uint8_t PPGC3; - stc_mft_ppg_ppgc3_field_t PPGC3_f; - }; - union { - __IO uint8_t PPGC2; - stc_mft_ppg_ppgc2_field_t PPGC2_f; - }; - uint8_t RESERVED21[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint8_t GATEC0; - stc_mft_ppg_gatec0_field_t GATEC0_f; - }; - uint8_t RESERVED26[39]; - union { - __IO uint8_t PPGC5; - stc_mft_ppg_ppgc5_field_t PPGC5_f; - }; - union { - __IO uint8_t PPGC4; - stc_mft_ppg_ppgc4_field_t PPGC4_f; - }; - uint8_t RESERVED27[2]; - union { - __IO uint8_t PPGC7; - stc_mft_ppg_ppgc7_field_t PPGC7_f; - }; - union { - __IO uint8_t PPGC6; - stc_mft_ppg_ppgc6_field_t PPGC6_f; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED30[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED31[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED32[2]; - union { - __IO uint8_t GATEC4; - stc_mft_ppg_gatec4_field_t GATEC4_f; - }; - uint8_t RESERVED33[39]; - union { - __IO uint8_t PPGC9; - stc_mft_ppg_ppgc9_field_t PPGC9_f; - }; - union { - __IO uint8_t PPGC8; - stc_mft_ppg_ppgc8_field_t PPGC8_f; - }; - uint8_t RESERVED34[2]; - union { - __IO uint8_t PPGC11; - stc_mft_ppg_ppgc11_field_t PPGC11_f; - }; - union { - __IO uint8_t PPGC10; - stc_mft_ppg_ppgc10_field_t PPGC10_f; - }; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED37[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED38[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED39[2]; - union { - __IO uint8_t GATEC8; - stc_mft_ppg_gatec8_field_t GATEC8_f; - }; - uint8_t RESERVED40[39]; - union { - __IO uint8_t PPGC13; - stc_mft_ppg_ppgc13_field_t PPGC13_f; - }; - union { - __IO uint8_t PPGC12; - stc_mft_ppg_ppgc12_field_t PPGC12_f; - }; - uint8_t RESERVED41[2]; - union { - __IO uint8_t PPGC15; - stc_mft_ppg_ppgc15_field_t PPGC15_f; - }; - union { - __IO uint8_t PPGC14; - stc_mft_ppg_ppgc14_field_t PPGC14_f; - }; - uint8_t RESERVED42[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED43[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED44[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED45[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED46[2]; - union { - __IO uint8_t GATEC12; - stc_mft_ppg_gatec12_field_t GATEC12_f; - }; - uint8_t RESERVED47[39]; - union { - __IO uint8_t PPGC17; - stc_mft_ppg_ppgc17_field_t PPGC17_f; - }; - union { - __IO uint8_t PPGC16; - stc_mft_ppg_ppgc16_field_t PPGC16_f; - }; - uint8_t RESERVED48[2]; - union { - __IO uint8_t PPGC19; - stc_mft_ppg_ppgc19_field_t PPGC19_f; - }; - union { - __IO uint8_t PPGC18; - stc_mft_ppg_ppgc18_field_t PPGC18_f; - }; - uint8_t RESERVED49[2]; - union { - __IO uint16_t PRL16; - struct { - __IO uint8_t PRLL16; - __IO uint8_t PRLH16; - }; - }; - uint8_t RESERVED50[2]; - union { - __IO uint16_t PRL17; - struct { - __IO uint8_t PRLL17; - __IO uint8_t PRLH17; - }; - }; - uint8_t RESERVED51[2]; - union { - __IO uint16_t PRL18; - struct { - __IO uint8_t PRLL18; - __IO uint8_t PRLH18; - }; - }; - uint8_t RESERVED52[2]; - union { - __IO uint16_t PRL19; - struct { - __IO uint8_t PRLL19; - __IO uint8_t PRLH19; - }; - }; - uint8_t RESERVED53[2]; - union { - __IO uint8_t GATEC16; - stc_mft_ppg_gatec16_field_t GATEC16_f; - }; - uint8_t RESERVED54[39]; - union { - __IO uint8_t PPGC21; - stc_mft_ppg_ppgc21_field_t PPGC21_f; - }; - union { - __IO uint8_t PPGC20; - stc_mft_ppg_ppgc20_field_t PPGC20_f; - }; - uint8_t RESERVED55[2]; - union { - __IO uint8_t PPGC23; - stc_mft_ppg_ppgc23_field_t PPGC23_f; - }; - union { - __IO uint8_t PPGC22; - stc_mft_ppg_ppgc22_field_t PPGC22_f; - }; - uint8_t RESERVED56[2]; - union { - __IO uint16_t PRL20; - struct { - __IO uint8_t PRLL20; - __IO uint8_t PRLH20; - }; - }; - uint8_t RESERVED57[2]; - union { - __IO uint16_t PRL21; - struct { - __IO uint8_t PRLL21; - __IO uint8_t PRLH21; - }; - }; - uint8_t RESERVED58[2]; - union { - __IO uint16_t PRL22; - struct { - __IO uint8_t PRLL22; - __IO uint8_t PRLH22; - }; - }; - uint8_t RESERVED59[2]; - union { - __IO uint16_t PRL23; - struct { - __IO uint8_t PRLL23; - __IO uint8_t PRLH23; - }; - }; - uint8_t RESERVED60[2]; - union { - __IO uint8_t GATEC20; - stc_mft_ppg_gatec20_field_t GATEC20_f; - }; -}FM3_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_ppg_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_ppg_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_ppg_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_pwm_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_pwm_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwm_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t TMCR; - stc_bt_rt_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_rt_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_rt_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - union { - __IO uint16_t TMCR; - stc_bt_pwc_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_pwc_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwc_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL0123; - stc_btiosel03_btsel0123_field_t BTSEL0123_f; - }; -}FM3_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL4567; - stc_btiosel47_btsel4567_field_t BTSEL4567_f; - }; -}FM3_BTIOSEL47_TypeDef; - -/****************************************************************************** - * BTIOSEL8B_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 8 - channel 11 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL89AB; - stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; - }; -}FM3_BTIOSEL8B_TypeDef; - -/****************************************************************************** - * BTIOSELCF_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 12 - channel 15 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSELCDEF; - stc_btioselcf_btselcdef_field_t BTSELCDEF_f; - }; -}FM3_BTIOSELCF_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - union { - __IO uint16_t BTSSSR; - stc_sbssr_btsssr_field_t BTSSSR_f; - }; -}FM3_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t QICR; - stc_qprc_qicr_field_t QICR_f; - }; - struct { - union { - __IO uint8_t QICRL; - stc_qprc_qicrl_field_t QICRL_f; - }; - union { - __IO uint8_t QICRH; - stc_qprc_qicrh_field_t QICRH_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t QCR; - stc_qprc_qcr_field_t QCR_f; - }; - struct { - union { - __IO uint8_t QCRL; - stc_qprc_qcrl_field_t QCRL_f; - }; - union { - __IO uint8_t QCRH; - stc_qprc_qcrh_field_t QCRH_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t QECR; - stc_qprc_qecr_field_t QECR_f; - }; - uint8_t RESERVED7[30]; - __IO uint16_t QRCRR; - __IO uint16_t QPCRR; -}FM3_QPRC_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - union { - __IO uint8_t ADSR; - stc_adc_adsr_field_t ADSR_f; - }; - union { - __IO uint8_t ADCR; - stc_adc_adcr_field_t ADCR_f; - }; - uint8_t RESERVED0[6]; - union { - __IO uint8_t SFNS; - stc_adc_sfns_field_t SFNS_f; - }; - union { - __IO uint8_t SCCR; - stc_adc_sccr_field_t SCCR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint32_t SCFD; - stc_adc_scfd_field_t SCFD_f; - }; - struct { - union { - __IO uint16_t SCFDL; - stc_adc_scfdl_field_t SCFDL_f; - }; - union { - __IO uint16_t SCFDH; - stc_adc_scfdh_field_t SCFDH_f; - }; - }; - }; - union { - union { - __IO uint16_t SCIS23; - stc_adc_scis23_field_t SCIS23_f; - }; - struct { - union { - __IO uint8_t SCIS2; - stc_adc_scis2_field_t SCIS2_f; - }; - union { - __IO uint8_t SCIS3; - stc_adc_scis3_field_t SCIS3_f; - }; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t SCIS01; - stc_adc_scis01_field_t SCIS01_f; - }; - struct { - union { - __IO uint8_t SCIS0; - stc_adc_scis0_field_t SCIS0_f; - }; - union { - __IO uint8_t SCIS1; - stc_adc_scis1_field_t SCIS1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t PFNS; - stc_adc_pfns_field_t PFNS_f; - }; - union { - __IO uint8_t PCCR; - stc_adc_pccr_field_t PCCR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint32_t PCFD; - stc_adc_pcfd_field_t PCFD_f; - }; - struct { - union { - __IO uint16_t PCFDL; - stc_adc_pcfdl_field_t PCFDL_f; - }; - union { - __IO uint16_t PCFDH; - stc_adc_pcfdh_field_t PCFDH_f; - }; - }; - }; - union { - __IO uint8_t PCIS; - stc_adc_pcis_field_t PCIS_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t CMPCR; - stc_adc_cmpcr_field_t CMPCR_f; - }; - uint8_t RESERVED6; - union { - __IO uint16_t CMPD; - stc_adc_cmpd_field_t CMPD_f; - }; - union { - union { - __IO uint16_t ADSS23; - stc_adc_adss23_field_t ADSS23_f; - }; - struct { - union { - __IO uint8_t ADSS2; - stc_adc_adss2_field_t ADSS2_f; - }; - union { - __IO uint8_t ADSS3; - stc_adc_adss3_field_t ADSS3_f; - }; - }; - }; - uint8_t RESERVED7[2]; - union { - union { - __IO uint16_t ADSS01; - stc_adc_adss01_field_t ADSS01_f; - }; - struct { - union { - __IO uint8_t ADSS0; - stc_adc_adss0_field_t ADSS0_f; - }; - union { - __IO uint8_t ADSS1; - stc_adc_adss1_field_t ADSS1_f; - }; - }; - }; - uint8_t RESERVED8[2]; - union { - union { - __IO uint16_t ADST01; - stc_adc_adst01_field_t ADST01_f; - }; - struct { - union { - __IO uint8_t ADST1; - stc_adc_adst1_field_t ADST1_f; - }; - union { - __IO uint8_t ADST0; - stc_adc_adst0_field_t ADST0_f; - }; - }; - }; - uint8_t RESERVED9[2]; - union { - __IO uint8_t ADCT; - stc_adc_adct_field_t ADCT_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PRTSL; - stc_adc_prtsl_field_t PRTSL_f; - }; - union { - __IO uint8_t SCTSL; - stc_adc_sctsl_field_t SCTSL_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint8_t ADCEN; - stc_adc_adcen_field_t ADCEN_f; - }; -}FM3_ADC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - union { - __IO uint8_t MCR_PSR; - stc_crtrim_mcr_psr_field_t MCR_PSR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint16_t MCR_FTRM; - stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; - }; - uint8_t RESERVED1[6]; - __IO uint32_t MCR_RLR; -}FM3_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - union { - __IO uint32_t ENIR; - stc_exti_enir_field_t ENIR_f; - }; - union { - __IO uint32_t EIRR; - stc_exti_eirr_field_t EIRR_f; - }; - union { - __IO uint32_t EICL; - stc_exti_eicl_field_t EICL_f; - }; - union { - __IO uint32_t ELVR; - stc_exti_elvr_field_t ELVR_f; - }; - union { - __IO uint32_t ELVR1; - stc_exti_elvr1_field_t ELVR1_f; - }; - union { - __IO uint8_t NMIRR; - stc_exti_nmirr_field_t NMIRR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t NMICL; - stc_exti_nmicl_field_t NMICL_f; - }; -}FM3_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - union { - __IO uint32_t DRQSEL; - stc_intreq_drqsel_field_t DRQSEL_f; - }; - uint8_t RESERVED0[7]; - union { - __IO uint8_t ODDPKS; - stc_intreq_oddpks_field_t ODDPKS_f; - }; - uint8_t RESERVED1[4]; - union { - __IO uint32_t EXC02MON; - stc_intreq_exc02mon_field_t EXC02MON_f; - }; - union { - __IO uint32_t IRQ00MON; - stc_intreq_irq00mon_field_t IRQ00MON_f; - }; - union { - __IO uint32_t IRQ01MON; - stc_intreq_irq01mon_field_t IRQ01MON_f; - }; - union { - __IO uint32_t IRQ02MON; - stc_intreq_irq02mon_field_t IRQ02MON_f; - }; - union { - __IO uint32_t IRQ03MON; - stc_intreq_irq03mon_field_t IRQ03MON_f; - }; - union { - __IO uint32_t IRQ04MON; - stc_intreq_irq04mon_field_t IRQ04MON_f; - }; - union { - __IO uint32_t IRQ05MON; - stc_intreq_irq05mon_field_t IRQ05MON_f; - }; - union { - __IO uint32_t IRQ06MON; - stc_intreq_irq06mon_field_t IRQ06MON_f; - }; - union { - __IO uint32_t IRQ07MON; - stc_intreq_irq07mon_field_t IRQ07MON_f; - }; - union { - __IO uint32_t IRQ08MON; - stc_intreq_irq08mon_field_t IRQ08MON_f; - }; - union { - __IO uint32_t IRQ09MON; - stc_intreq_irq09mon_field_t IRQ09MON_f; - }; - union { - __IO uint32_t IRQ10MON; - stc_intreq_irq10mon_field_t IRQ10MON_f; - }; - union { - __IO uint32_t IRQ11MON; - stc_intreq_irq11mon_field_t IRQ11MON_f; - }; - union { - __IO uint32_t IRQ12MON; - stc_intreq_irq12mon_field_t IRQ12MON_f; - }; - union { - __IO uint32_t IRQ13MON; - stc_intreq_irq13mon_field_t IRQ13MON_f; - }; - union { - __IO uint32_t IRQ14MON; - stc_intreq_irq14mon_field_t IRQ14MON_f; - }; - union { - __IO uint32_t IRQ15MON; - stc_intreq_irq15mon_field_t IRQ15MON_f; - }; - union { - __IO uint32_t IRQ16MON; - stc_intreq_irq16mon_field_t IRQ16MON_f; - }; - union { - __IO uint32_t IRQ17MON; - stc_intreq_irq17mon_field_t IRQ17MON_f; - }; - union { - __IO uint32_t IRQ18MON; - stc_intreq_irq18mon_field_t IRQ18MON_f; - }; - union { - __IO uint32_t IRQ19MON; - stc_intreq_irq19mon_field_t IRQ19MON_f; - }; - union { - __IO uint32_t IRQ20MON; - stc_intreq_irq20mon_field_t IRQ20MON_f; - }; - union { - __IO uint32_t IRQ21MON; - stc_intreq_irq21mon_field_t IRQ21MON_f; - }; - union { - __IO uint32_t IRQ22MON; - stc_intreq_irq22mon_field_t IRQ22MON_f; - }; - union { - __IO uint32_t IRQ23MON; - stc_intreq_irq23mon_field_t IRQ23MON_f; - }; - union { - __IO uint32_t IRQ24MON; - stc_intreq_irq24mon_field_t IRQ24MON_f; - }; - union { - __IO uint32_t IRQ25MON; - stc_intreq_irq25mon_field_t IRQ25MON_f; - }; - union { - __IO uint32_t IRQ26MON; - stc_intreq_irq26mon_field_t IRQ26MON_f; - }; - union { - __IO uint32_t IRQ27MON; - stc_intreq_irq27mon_field_t IRQ27MON_f; - }; - union { - __IO uint32_t IRQ28MON; - stc_intreq_irq28mon_field_t IRQ28MON_f; - }; - union { - __IO uint32_t IRQ29MON; - stc_intreq_irq29mon_field_t IRQ29MON_f; - }; - union { - __IO uint32_t IRQ30MON; - stc_intreq_irq30mon_field_t IRQ30MON_f; - }; - union { - __IO uint32_t IRQ31MON; - stc_intreq_irq31mon_field_t IRQ31MON_f; - }; - union { - __IO uint32_t IRQ32MON; - stc_intreq_irq32mon_field_t IRQ32MON_f; - }; - union { - __IO uint32_t IRQ33MON; - stc_intreq_irq33mon_field_t IRQ33MON_f; - }; - union { - __IO uint32_t IRQ34MON; - stc_intreq_irq34mon_field_t IRQ34MON_f; - }; - union { - __IO uint32_t IRQ35MON; - stc_intreq_irq35mon_field_t IRQ35MON_f; - }; - union { - __IO uint32_t IRQ36MON; - stc_intreq_irq36mon_field_t IRQ36MON_f; - }; - union { - __IO uint32_t IRQ37MON; - stc_intreq_irq37mon_field_t IRQ37MON_f; - }; - union { - __IO uint32_t IRQ38MON; - stc_intreq_irq38mon_field_t IRQ38MON_f; - }; - union { - __IO uint32_t IRQ39MON; - stc_intreq_irq39mon_field_t IRQ39MON_f; - }; - union { - __IO uint32_t IRQ40MON; - stc_intreq_irq40mon_field_t IRQ40MON_f; - }; - union { - __IO uint32_t IRQ41MON; - stc_intreq_irq41mon_field_t IRQ41MON_f; - }; - union { - __IO uint32_t IRQ42MON; - stc_intreq_irq42mon_field_t IRQ42MON_f; - }; - union { - __IO uint32_t IRQ43MON; - stc_intreq_irq43mon_field_t IRQ43MON_f; - }; - union { - __IO uint32_t IRQ44MON; - stc_intreq_irq44mon_field_t IRQ44MON_f; - }; - union { - __IO uint32_t IRQ45MON; - stc_intreq_irq45mon_field_t IRQ45MON_f; - }; - union { - __IO uint32_t IRQ46MON; - stc_intreq_irq46mon_field_t IRQ46MON_f; - }; - uint8_t RESERVED2[300]; - union { - __IO uint32_t DRQSEL1; - stc_intreq_drqsel1_field_t DRQSEL1_f; - }; - union { - __IO uint32_t DQESEL; - stc_intreq_dqesel_field_t DQESEL_f; - }; - uint8_t RESERVED3[7]; - union { - __IO uint8_t ODDPKS1; - stc_intreq_oddpks1_field_t ODDPKS1_f; - }; -}FM3_INTREQ_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - union { - __IO uint32_t PFR0; - stc_gpio_pfr0_field_t PFR0_f; - }; - union { - __IO uint32_t PFR1; - stc_gpio_pfr1_field_t PFR1_f; - }; - union { - __IO uint32_t PFR2; - stc_gpio_pfr2_field_t PFR2_f; - }; - union { - __IO uint32_t PFR3; - stc_gpio_pfr3_field_t PFR3_f; - }; - union { - __IO uint32_t PFR4; - stc_gpio_pfr4_field_t PFR4_f; - }; - union { - __IO uint32_t PFR5; - stc_gpio_pfr5_field_t PFR5_f; - }; - union { - __IO uint32_t PFR6; - stc_gpio_pfr6_field_t PFR6_f; - }; - union { - __IO uint32_t PFR7; - stc_gpio_pfr7_field_t PFR7_f; - }; - union { - __IO uint32_t PFR8; - stc_gpio_pfr8_field_t PFR8_f; - }; - __IO uint32_t PFR9; - union { - __IO uint32_t PFRA; - stc_gpio_pfra_field_t PFRA_f; - }; - __IO uint32_t PFRB; - union { - __IO uint32_t PFRC; - stc_gpio_pfrc_field_t PFRC_f; - }; - union { - __IO uint32_t PFRD; - stc_gpio_pfrd_field_t PFRD_f; - }; - union { - __IO uint32_t PFRE; - stc_gpio_pfre_field_t PFRE_f; - }; - union { - __IO uint32_t PFRF; - stc_gpio_pfrf_field_t PFRF_f; - }; - uint8_t RESERVED0[192]; - union { - __IO uint32_t PCR0; - stc_gpio_pcr0_field_t PCR0_f; - }; - union { - __IO uint32_t PCR1; - stc_gpio_pcr1_field_t PCR1_f; - }; - union { - __IO uint32_t PCR2; - stc_gpio_pcr2_field_t PCR2_f; - }; - union { - __IO uint32_t PCR3; - stc_gpio_pcr3_field_t PCR3_f; - }; - union { - __IO uint32_t PCR4; - stc_gpio_pcr4_field_t PCR4_f; - }; - union { - __IO uint32_t PCR5; - stc_gpio_pcr5_field_t PCR5_f; - }; - union { - __IO uint32_t PCR6; - stc_gpio_pcr6_field_t PCR6_f; - }; - union { - __IO uint32_t PCR7; - stc_gpio_pcr7_field_t PCR7_f; - }; - __IO uint32_t PCR8; - __IO uint32_t PCR9; - union { - __IO uint32_t PCRA; - stc_gpio_pcra_field_t PCRA_f; - }; - __IO uint32_t PCRB; - union { - __IO uint32_t PCRC; - stc_gpio_pcrc_field_t PCRC_f; - }; - union { - __IO uint32_t PCRD; - stc_gpio_pcrd_field_t PCRD_f; - }; - union { - __IO uint32_t PCRE; - stc_gpio_pcre_field_t PCRE_f; - }; - __IO uint32_t PCRF; - uint8_t RESERVED1[192]; - union { - __IO uint32_t DDR0; - stc_gpio_ddr0_field_t DDR0_f; - }; - union { - __IO uint32_t DDR1; - stc_gpio_ddr1_field_t DDR1_f; - }; - union { - __IO uint32_t DDR2; - stc_gpio_ddr2_field_t DDR2_f; - }; - union { - __IO uint32_t DDR3; - stc_gpio_ddr3_field_t DDR3_f; - }; - union { - __IO uint32_t DDR4; - stc_gpio_ddr4_field_t DDR4_f; - }; - union { - __IO uint32_t DDR5; - stc_gpio_ddr5_field_t DDR5_f; - }; - union { - __IO uint32_t DDR6; - stc_gpio_ddr6_field_t DDR6_f; - }; - union { - __IO uint32_t DDR7; - stc_gpio_ddr7_field_t DDR7_f; - }; - union { - __IO uint32_t DDR8; - stc_gpio_ddr8_field_t DDR8_f; - }; - __IO uint32_t DDR9; - union { - __IO uint32_t DDRA; - stc_gpio_ddra_field_t DDRA_f; - }; - __IO uint32_t DDRB; - union { - __IO uint32_t DDRC; - stc_gpio_ddrc_field_t DDRC_f; - }; - union { - __IO uint32_t DDRD; - stc_gpio_ddrd_field_t DDRD_f; - }; - union { - __IO uint32_t DDRE; - stc_gpio_ddre_field_t DDRE_f; - }; - union { - __IO uint32_t DDRF; - stc_gpio_ddrf_field_t DDRF_f; - }; - uint8_t RESERVED2[192]; - union { - __IO uint32_t PDIR0; - stc_gpio_pdir0_field_t PDIR0_f; - }; - union { - __IO uint32_t PDIR1; - stc_gpio_pdir1_field_t PDIR1_f; - }; - union { - __IO uint32_t PDIR2; - stc_gpio_pdir2_field_t PDIR2_f; - }; - union { - __IO uint32_t PDIR3; - stc_gpio_pdir3_field_t PDIR3_f; - }; - union { - __IO uint32_t PDIR4; - stc_gpio_pdir4_field_t PDIR4_f; - }; - union { - __IO uint32_t PDIR5; - stc_gpio_pdir5_field_t PDIR5_f; - }; - union { - __IO uint32_t PDIR6; - stc_gpio_pdir6_field_t PDIR6_f; - }; - union { - __IO uint32_t PDIR7; - stc_gpio_pdir7_field_t PDIR7_f; - }; - union { - __IO uint32_t PDIR8; - stc_gpio_pdir8_field_t PDIR8_f; - }; - __IO uint32_t PDIR9; - union { - __IO uint32_t PDIRA; - stc_gpio_pdira_field_t PDIRA_f; - }; - __IO uint32_t PDIRB; - union { - __IO uint32_t PDIRC; - stc_gpio_pdirc_field_t PDIRC_f; - }; - union { - __IO uint32_t PDIRD; - stc_gpio_pdird_field_t PDIRD_f; - }; - union { - __IO uint32_t PDIRE; - stc_gpio_pdire_field_t PDIRE_f; - }; - union { - __IO uint32_t PDIRF; - stc_gpio_pdirf_field_t PDIRF_f; - }; - uint8_t RESERVED3[192]; - union { - __IO uint32_t PDOR0; - stc_gpio_pdor0_field_t PDOR0_f; - }; - union { - __IO uint32_t PDOR1; - stc_gpio_pdor1_field_t PDOR1_f; - }; - union { - __IO uint32_t PDOR2; - stc_gpio_pdor2_field_t PDOR2_f; - }; - union { - __IO uint32_t PDOR3; - stc_gpio_pdor3_field_t PDOR3_f; - }; - union { - __IO uint32_t PDOR4; - stc_gpio_pdor4_field_t PDOR4_f; - }; - union { - __IO uint32_t PDOR5; - stc_gpio_pdor5_field_t PDOR5_f; - }; - union { - __IO uint32_t PDOR6; - stc_gpio_pdor6_field_t PDOR6_f; - }; - union { - __IO uint32_t PDOR7; - stc_gpio_pdor7_field_t PDOR7_f; - }; - union { - __IO uint32_t PDOR8; - stc_gpio_pdor8_field_t PDOR8_f; - }; - __IO uint32_t PDOR9; - union { - __IO uint32_t PDORA; - stc_gpio_pdora_field_t PDORA_f; - }; - __IO uint32_t PDORB; - union { - __IO uint32_t PDORC; - stc_gpio_pdorc_field_t PDORC_f; - }; - union { - __IO uint32_t PDORD; - stc_gpio_pdord_field_t PDORD_f; - }; - union { - __IO uint32_t PDORE; - stc_gpio_pdore_field_t PDORE_f; - }; - union { - __IO uint32_t PDORF; - stc_gpio_pdorf_field_t PDORF_f; - }; - uint8_t RESERVED4[192]; - union { - __IO uint32_t ADE; - stc_gpio_ade_field_t ADE_f; - }; - uint8_t RESERVED5[124]; - union { - __IO uint32_t SPSR; - stc_gpio_spsr_field_t SPSR_f; - }; - uint8_t RESERVED6[124]; - union { - __IO uint32_t EPFR00; - stc_gpio_epfr00_field_t EPFR00_f; - }; - union { - __IO uint32_t EPFR01; - stc_gpio_epfr01_field_t EPFR01_f; - }; - union { - __IO uint32_t EPFR02; - stc_gpio_epfr02_field_t EPFR02_f; - }; - union { - __IO uint32_t EPFR03; - stc_gpio_epfr03_field_t EPFR03_f; - }; - union { - __IO uint32_t EPFR04; - stc_gpio_epfr04_field_t EPFR04_f; - }; - union { - __IO uint32_t EPFR05; - stc_gpio_epfr05_field_t EPFR05_f; - }; - union { - __IO uint32_t EPFR06; - stc_gpio_epfr06_field_t EPFR06_f; - }; - union { - __IO uint32_t EPFR07; - stc_gpio_epfr07_field_t EPFR07_f; - }; - union { - __IO uint32_t EPFR08; - stc_gpio_epfr08_field_t EPFR08_f; - }; - union { - __IO uint32_t EPFR09; - stc_gpio_epfr09_field_t EPFR09_f; - }; - union { - __IO uint32_t EPFR10; - stc_gpio_epfr10_field_t EPFR10_f; - }; - union { - __IO uint32_t EPFR11; - stc_gpio_epfr11_field_t EPFR11_f; - }; - union { - __IO uint32_t EPFR12; - stc_gpio_epfr12_field_t EPFR12_f; - }; - union { - __IO uint32_t EPFR13; - stc_gpio_epfr13_field_t EPFR13_f; - }; - union { - __IO uint32_t EPFR14; - stc_gpio_epfr14_field_t EPFR14_f; - }; - union { - __IO uint32_t EPFR15; - stc_gpio_epfr15_field_t EPFR15_f; - }; - uint8_t RESERVED7[192]; - union { - __IO uint32_t PZR0; - stc_gpio_pzr0_field_t PZR0_f; - }; - union { - __IO uint32_t PZR1; - stc_gpio_pzr1_field_t PZR1_f; - }; - union { - __IO uint32_t PZR2; - stc_gpio_pzr2_field_t PZR2_f; - }; - union { - __IO uint32_t PZR3; - stc_gpio_pzr3_field_t PZR3_f; - }; - union { - __IO uint32_t PZR4; - stc_gpio_pzr4_field_t PZR4_f; - }; - union { - __IO uint32_t PZR5; - stc_gpio_pzr5_field_t PZR5_f; - }; - union { - __IO uint32_t PZR6; - stc_gpio_pzr6_field_t PZR6_f; - }; - union { - __IO uint32_t PZR7; - stc_gpio_pzr7_field_t PZR7_f; - }; - union { - __IO uint32_t PZR8; - stc_gpio_pzr8_field_t PZR8_f; - }; - __IO uint32_t PZR9; - union { - __IO uint32_t PZRA; - stc_gpio_pzra_field_t PZRA_f; - }; - __IO uint32_t PZRB; - union { - __IO uint32_t PZRC; - stc_gpio_pzrc_field_t PZRC_f; - }; - union { - __IO uint32_t PZRD; - stc_gpio_pzrd_field_t PZRD_f; - }; - union { - __IO uint32_t PZRE; - stc_gpio_pzre_field_t PZRE_f; - }; - union { - __IO uint32_t PZRF; - stc_gpio_pzrf_field_t PZRF_f; - }; -}FM3_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - union { - __IO uint8_t LVD_CTL; - stc_lvd_lvd_ctl_field_t LVD_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t LVD_STR; - stc_lvd_lvd_str_field_t LVD_STR_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t LVD_CLR; - stc_lvd_lvd_clr_field_t LVD_CLR_f; - }; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - union { - __IO uint8_t LVD_STR2; - stc_lvd_lvd_str2_field_t LVD_STR2_f; - }; -}FM3_LVD_TypeDef; - -/****************************************************************************** - * USBETHERNETCLK - ******************************************************************************/ -/* USB Ethernet clock registers */ -typedef struct -{ - union { - __IO uint8_t UCCR; - stc_usbethernetclk_uccr_field_t UCCR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t UPCR1; - stc_usbethernetclk_upcr1_field_t UPCR1_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t UPCR2; - stc_usbethernetclk_upcr2_field_t UPCR2_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t UPCR3; - stc_usbethernetclk_upcr3_field_t UPCR3_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t UPCR4; - stc_usbethernetclk_upcr4_field_t UPCR4_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t UP_STR; - stc_usbethernetclk_up_str_field_t UP_STR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t UPINT_ENR; - stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t UPINT_CLR; - stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint8_t UPINT_STR; - stc_usbethernetclk_upint_str_field_t UPINT_STR_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t UPCR5; - stc_usbethernetclk_upcr5_field_t UPCR5_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t UPCR6; - stc_usbethernetclk_upcr6_field_t UPCR6_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t UPCR7; - stc_usbethernetclk_upcr7_field_t UPCR7_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t USBEN0; - stc_usbethernetclk_usben0_field_t USBEN0_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint8_t USBEN1; - stc_usbethernetclk_usben1_field_t USBEN1_f; - }; -}FM3_USBETHERNETCLK_TypeDef; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs03_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs03_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_uart_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_UART_TypeDef; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_CSIO_TypeDef; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_lin_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_LIN_TypeDef; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* I2C channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs03_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs03_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs03_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs03_i2c_ismk_field_t ISMK_f; - }; -}FM3_MFS03_I2C_TypeDef; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs47_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs47_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_uart_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_uart_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_uart_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_uart_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_uart_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_uart_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_uart_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_UART_TypeDef; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_csio_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_csio_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_csio_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_csio_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_csio_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_csio_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_CSIO_TypeDef; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_lin_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_lin_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_lin_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_lin_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_lin_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_lin_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_lin_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_LIN_TypeDef; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* I2C channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs47_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs47_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs47_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs47_i2c_ismk_field_t ISMK_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_i2c_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_i2c_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_i2c_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_i2c_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_I2C_TypeDef; - -/****************************************************************************** - * MFS_NFC_MODULE - ******************************************************************************/ -/* MFS_NFC_MODULE register bit fields */ -typedef struct -{ - union { - __IO uint16_t I2CDNF; - stc_mfs_nfc_i2cdnf_field_t I2CDNF_f; - }; -}FM3_MFS_NFC_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - union { - __IO uint8_t CRCCR; - stc_crc_crccr_field_t CRCCR_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM3_CRC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - union { - __IO uint8_t WCRD; - stc_wc_wcrd_field_t WCRD_f; - }; - union { - __IO uint8_t WCRL; - stc_wc_wcrl_field_t WCRL_f; - }; - union { - __IO uint8_t WCCR; - stc_wc_wccr_field_t WCCR_f; - }; - uint8_t RESERVED0[13]; - union { - __IO uint16_t CLK_SEL; - stc_wc_clk_sel_field_t CLK_SEL_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t CLK_EN; - stc_wc_clk_en_field_t CLK_EN_f; - }; -}FM3_WC_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - union { - __IO uint32_t MODE0; - stc_exbus_mode0_field_t MODE0_f; - }; - union { - __IO uint32_t MODE1; - stc_exbus_mode1_field_t MODE1_f; - }; - union { - __IO uint32_t MODE2; - stc_exbus_mode2_field_t MODE2_f; - }; - union { - __IO uint32_t MODE3; - stc_exbus_mode3_field_t MODE3_f; - }; - union { - __IO uint32_t MODE4; - stc_exbus_mode4_field_t MODE4_f; - }; - union { - __IO uint32_t MODE5; - stc_exbus_mode5_field_t MODE5_f; - }; - union { - __IO uint32_t MODE6; - stc_exbus_mode6_field_t MODE6_f; - }; - union { - __IO uint32_t MODE7; - stc_exbus_mode7_field_t MODE7_f; - }; - union { - __IO uint32_t TIM0; - stc_exbus_tim0_field_t TIM0_f; - }; - union { - __IO uint32_t TIM1; - stc_exbus_tim1_field_t TIM1_f; - }; - union { - __IO uint32_t TIM2; - stc_exbus_tim2_field_t TIM2_f; - }; - union { - __IO uint32_t TIM3; - stc_exbus_tim3_field_t TIM3_f; - }; - union { - __IO uint32_t TIM4; - stc_exbus_tim4_field_t TIM4_f; - }; - union { - __IO uint32_t TIM5; - stc_exbus_tim5_field_t TIM5_f; - }; - union { - __IO uint32_t TIM6; - stc_exbus_tim6_field_t TIM6_f; - }; - union { - __IO uint32_t TIM7; - stc_exbus_tim7_field_t TIM7_f; - }; - union { - __IO uint32_t AREA0; - stc_exbus_area0_field_t AREA0_f; - }; - union { - __IO uint32_t AREA1; - stc_exbus_area1_field_t AREA1_f; - }; - union { - __IO uint32_t AREA2; - stc_exbus_area2_field_t AREA2_f; - }; - union { - __IO uint32_t AREA3; - stc_exbus_area3_field_t AREA3_f; - }; - union { - __IO uint32_t AREA4; - stc_exbus_area4_field_t AREA4_f; - }; - union { - __IO uint32_t AREA5; - stc_exbus_area5_field_t AREA5_f; - }; - union { - __IO uint32_t AREA6; - stc_exbus_area6_field_t AREA6_f; - }; - union { - __IO uint32_t AREA7; - stc_exbus_area7_field_t AREA7_f; - }; - union { - __IO uint16_t ATIM0; - stc_exbus_atim0_field_t ATIM0_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint16_t ATIM1; - stc_exbus_atim1_field_t ATIM1_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t ATIM2; - stc_exbus_atim2_field_t ATIM2_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t ATIM3; - stc_exbus_atim3_field_t ATIM3_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t ATIM4; - stc_exbus_atim4_field_t ATIM4_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t ATIM5; - stc_exbus_atim5_field_t ATIM5_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t ATIM6; - stc_exbus_atim6_field_t ATIM6_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t ATIM7; - stc_exbus_atim7_field_t ATIM7_f; - }; - uint8_t RESERVED7[642]; - union { - __IO uint8_t DCLKR; - stc_exbus_dclkr_field_t DCLKR_f; - }; -}FM3_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - union { - __IO uint16_t HCNT; - stc_usb_hcnt_field_t HCNT_f; - }; - struct { - union { - __IO uint8_t HCNT0; - stc_usb_hcnt0_field_t HCNT0_f; - }; - union { - __IO uint8_t HCNT1; - stc_usb_hcnt1_field_t HCNT1_f; - }; - }; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t HIRQ; - stc_usb_hirq_field_t HIRQ_f; - }; - union { - __IO uint8_t HERR; - stc_usb_herr_field_t HERR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t HSTATE; - stc_usb_hstate_field_t HSTATE_f; - }; - union { - __IO uint8_t HFCOMP; - stc_usb_hfcomp_field_t HFCOMP_f; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t HRTIMER; - stc_usb_hrtimer_field_t HRTIMER_f; - }; - struct { - union { - __IO uint8_t HRTIMER0; - stc_usb_hrtimer0_field_t HRTIMER0_f; - }; - union { - __IO uint8_t HRTIMER1; - stc_usb_hrtimer1_field_t HRTIMER1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t HRTIMER2; - stc_usb_hrtimer2_field_t HRTIMER2_f; - }; - union { - __IO uint8_t HADR; - stc_usb_hadr_field_t HADR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t HEOF; - stc_usb_heof_field_t HEOF_f; - }; - struct { - union { - __IO uint8_t HEOF0; - stc_usb_heof0_field_t HEOF0_f; - }; - union { - __IO uint8_t HEOF1; - stc_usb_heof1_field_t HEOF1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t HFRAME; - stc_usb_hframe_field_t HFRAME_f; - }; - struct { - union { - __IO uint8_t HFRAME0; - stc_usb_hframe0_field_t HFRAME0_f; - }; - union { - __IO uint8_t HFRAME1; - stc_usb_hframe1_field_t HFRAME1_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t HTOKEN; - stc_usb_htoken_field_t HTOKEN_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t UDCC; - stc_usb_udcc_field_t UDCC_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t EP0C; - stc_usb_ep0c_field_t EP0C_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t EP1C; - stc_usb_ep1c_field_t EP1C_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint16_t EP2C; - stc_usb_ep2c_field_t EP2C_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t EP3C; - stc_usb_ep3c_field_t EP3C_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint16_t EP4C; - stc_usb_ep4c_field_t EP4C_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint16_t EP5C; - stc_usb_ep5c_field_t EP5C_f; - }; - uint8_t RESERVED14[2]; - union { - __IO uint16_t TMSP; - stc_usb_tmsp_field_t TMSP_f; - }; - uint8_t RESERVED15[2]; - union { - __IO uint8_t UDCS; - stc_usb_udcs_field_t UDCS_f; - }; - union { - __IO uint8_t UDCIE; - stc_usb_udcie_field_t UDCIE_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t EP0IS; - stc_usb_ep0is_field_t EP0IS_f; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t EP0OS; - stc_usb_ep0os_field_t EP0OS_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t EP1S; - stc_usb_ep1s_field_t EP1S_f; - }; - uint8_t RESERVED19[2]; - union { - __IO uint16_t EP2S; - stc_usb_ep2s_field_t EP2S_f; - }; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - union { - __IO uint16_t EP4S; - stc_usb_ep4s_field_t EP4S_f; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t EP5S; - stc_usb_ep5s_field_t EP5S_f; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM3_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - union { - __IO uint32_t DMACR; - stc_dmac_dmacr_field_t DMACR_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint32_t DMACA0; - stc_dmac_dmaca0_field_t DMACA0_f; - }; - union { - __IO uint32_t DMACB0; - stc_dmac_dmacb0_field_t DMACB0_f; - }; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - union { - __IO uint32_t DMACA1; - stc_dmac_dmaca1_field_t DMACA1_f; - }; - union { - __IO uint32_t DMACB1; - stc_dmac_dmacb1_field_t DMACB1_f; - }; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - union { - __IO uint32_t DMACA2; - stc_dmac_dmaca2_field_t DMACA2_f; - }; - union { - __IO uint32_t DMACB2; - stc_dmac_dmacb2_field_t DMACB2_f; - }; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - union { - __IO uint32_t DMACA3; - stc_dmac_dmaca3_field_t DMACA3_f; - }; - union { - __IO uint32_t DMACB3; - stc_dmac_dmacb3_field_t DMACB3_f; - }; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - union { - __IO uint32_t DMACA4; - stc_dmac_dmaca4_field_t DMACA4_f; - }; - union { - __IO uint32_t DMACB4; - stc_dmac_dmacb4_field_t DMACB4_f; - }; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - union { - __IO uint32_t DMACA5; - stc_dmac_dmaca5_field_t DMACA5_f; - }; - union { - __IO uint32_t DMACB5; - stc_dmac_dmacb5_field_t DMACB5_f; - }; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - union { - __IO uint32_t DMACA6; - stc_dmac_dmaca6_field_t DMACA6_f; - }; - union { - __IO uint32_t DMACB6; - stc_dmac_dmacb6_field_t DMACB6_f; - }; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - union { - __IO uint32_t DMACA7; - stc_dmac_dmaca7_field_t DMACA7_f; - }; - union { - __IO uint32_t DMACB7; - stc_dmac_dmacb7_field_t DMACB7_f; - }; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM3_DMAC_TypeDef; - -/****************************************************************************** - * ETHERNET_MAC_MODULE - ******************************************************************************/ -/* ETHERNET-MAC registers */ -typedef struct -{ - union { - __IO uint32_t MCR; - stc_ethernet_mac_mcr_field_t MCR_f; - }; - union { - __IO uint32_t MFFR; - stc_ethernet_mac_mffr_field_t MFFR_f; - }; - union { - __IO uint32_t MHTRH; - stc_ethernet_mac_mhtrh_field_t MHTRH_f; - }; - union { - __IO uint32_t MHTRL; - stc_ethernet_mac_mhtrl_field_t MHTRL_f; - }; - union { - __IO uint32_t GAR; - stc_ethernet_mac_gar_field_t GAR_f; - }; - union { - __IO uint32_t GDR; - stc_ethernet_mac_gdr_field_t GDR_f; - }; - union { - __IO uint32_t FCR; - stc_ethernet_mac_fcr_field_t FCR_f; - }; - union { - __IO uint32_t VTR; - stc_ethernet_mac_vtr_field_t VTR_f; - }; - uint8_t RESERVED0[8]; - union { - __IO uint32_t RWFFR; - stc_ethernet_mac_rwffr_field_t RWFFR_f; - }; - union { - __IO uint32_t PMTR; - stc_ethernet_mac_pmtr_field_t PMTR_f; - }; - union { - __IO uint32_t LPICSR; - stc_ethernet_mac_lpicsr_field_t LPICSR_f; - }; - union { - __IO uint32_t LPITCR; - stc_ethernet_mac_lpitcr_field_t LPITCR_f; - }; - union { - __IO uint32_t ISR; - stc_ethernet_mac_isr_field_t ISR_f; - }; - union { - __IO uint32_t IMR; - stc_ethernet_mac_imr_field_t IMR_f; - }; - union { - __IO uint32_t MAR0H; - stc_ethernet_mac_mar0h_field_t MAR0H_f; - }; - union { - __IO uint32_t MAR0L; - stc_ethernet_mac_mar0l_field_t MAR0L_f; - }; - union { - __IO uint32_t MAR1H; - stc_ethernet_mac_mar1h_field_t MAR1H_f; - }; - union { - __IO uint32_t MAR1L; - stc_ethernet_mac_mar1l_field_t MAR1L_f; - }; - union { - __IO uint32_t MAR2H; - stc_ethernet_mac_mar2h_field_t MAR2H_f; - }; - union { - __IO uint32_t MAR2L; - stc_ethernet_mac_mar2l_field_t MAR2L_f; - }; - union { - __IO uint32_t MAR3H; - stc_ethernet_mac_mar3h_field_t MAR3H_f; - }; - union { - __IO uint32_t MAR3L; - stc_ethernet_mac_mar3l_field_t MAR3L_f; - }; - union { - __IO uint32_t MAR4H; - stc_ethernet_mac_mar4h_field_t MAR4H_f; - }; - union { - __IO uint32_t MAR4L; - stc_ethernet_mac_mar4l_field_t MAR4L_f; - }; - union { - __IO uint32_t MAR5H; - stc_ethernet_mac_mar5h_field_t MAR5H_f; - }; - union { - __IO uint32_t MAR5L; - stc_ethernet_mac_mar5l_field_t MAR5L_f; - }; - union { - __IO uint32_t MAR6H; - stc_ethernet_mac_mar6h_field_t MAR6H_f; - }; - union { - __IO uint32_t MAR6L; - stc_ethernet_mac_mar6l_field_t MAR6L_f; - }; - union { - __IO uint32_t MAR7H; - stc_ethernet_mac_mar7h_field_t MAR7H_f; - }; - union { - __IO uint32_t MAR7L; - stc_ethernet_mac_mar7l_field_t MAR7L_f; - }; - union { - __IO uint32_t MAR8H; - stc_ethernet_mac_mar8h_field_t MAR8H_f; - }; - union { - __IO uint32_t MAR8L; - stc_ethernet_mac_mar8l_field_t MAR8L_f; - }; - union { - __IO uint32_t MAR9H; - stc_ethernet_mac_mar9h_field_t MAR9H_f; - }; - union { - __IO uint32_t MAR9L; - stc_ethernet_mac_mar9l_field_t MAR9L_f; - }; - union { - __IO uint32_t MAR10H; - stc_ethernet_mac_mar10h_field_t MAR10H_f; - }; - union { - __IO uint32_t MAR10L; - stc_ethernet_mac_mar10l_field_t MAR10L_f; - }; - union { - __IO uint32_t MAR11H; - stc_ethernet_mac_mar11h_field_t MAR11H_f; - }; - union { - __IO uint32_t MAR11L; - stc_ethernet_mac_mar11l_field_t MAR11L_f; - }; - union { - __IO uint32_t MAR12H; - stc_ethernet_mac_mar12h_field_t MAR12H_f; - }; - union { - __IO uint32_t MAR12L; - stc_ethernet_mac_mar12l_field_t MAR12L_f; - }; - union { - __IO uint32_t MAR13H; - stc_ethernet_mac_mar13h_field_t MAR13H_f; - }; - union { - __IO uint32_t MAR13L; - stc_ethernet_mac_mar13l_field_t MAR13L_f; - }; - union { - __IO uint32_t MAR14H; - stc_ethernet_mac_mar14h_field_t MAR14H_f; - }; - union { - __IO uint32_t MAR14L; - stc_ethernet_mac_mar14l_field_t MAR14L_f; - }; - union { - __IO uint32_t MAR15H; - stc_ethernet_mac_mar15h_field_t MAR15H_f; - }; - union { - __IO uint32_t MAR15L; - stc_ethernet_mac_mar15l_field_t MAR15L_f; - }; - uint8_t RESERVED1[24]; - union { - __IO uint32_t RGSR; - stc_ethernet_mac_rgsr_field_t RGSR_f; - }; - uint8_t RESERVED2[36]; - __IO uint32_t mmc_cntl; - __IO uint32_t mmc_intr_rx; - __IO uint32_t mmc_intr_tx; - __IO uint32_t mmc_intr_mask_rx; - __IO uint32_t mmc_intr_mask_tx; - __IO uint32_t txoctetcount_gb; - __IO uint32_t txframecount_gb; - __IO uint32_t txbroadcastframes_g; - __IO uint32_t txmulticastframes_g; - __IO uint32_t tx64octets_gb; - __IO uint32_t tx65to127octets_gb; - __IO uint32_t tx128to255octets_gb; - __IO uint32_t tx256to511octets_gb; - __IO uint32_t tx512to1023octets_gb; - __IO uint32_t tx1024tomaxoctets_gb; - __IO uint32_t txunicastframes_gb; - __IO uint32_t txmulticastframes_gb; - __IO uint32_t txbroadcastframes_gb; - __IO uint32_t txunderflowerror; - __IO uint32_t txsinglecol_g; - __IO uint32_t txmulticol_g; - __IO uint32_t txdeferred; - __IO uint32_t txlatecol; - __IO uint32_t txexesscol; - __IO uint32_t txcarriererror; - __IO uint32_t txoctetcount_g; - __IO uint32_t txframecount_g; - __IO uint32_t txexecessdef_g; - __IO uint32_t txpauseframes; - __IO uint32_t txvlanframes_g; - uint8_t RESERVED3[8]; - __IO uint32_t rxframecount_gb; - __IO uint32_t rxoctetcount_gb; - __IO uint32_t rxoctetcount_g; - __IO uint32_t rxbroadcastframes_g; - __IO uint32_t rxmulticastframes_g; - __IO uint32_t rxcrcerror; - __IO uint32_t rxallignmenterror; - __IO uint32_t rxrunterror; - __IO uint32_t rxjabbererror; - __IO uint32_t rxundersize_g; - __IO uint32_t rxoversize_g; - __IO uint32_t rx64octets_gb; - __IO uint32_t rx65to127octets_gb; - __IO uint32_t rx128to255octets_gb; - __IO uint32_t rx256to511octets_gb; - __IO uint32_t rx512to1023octets_gb; - __IO uint32_t rx1024tomaxoctets_gb; - __IO uint32_t rxunicastframes_g; - __IO uint32_t rxlengtherror; - __IO uint32_t rxoutofrangetype; - __IO uint32_t rxpauseframes; - __IO uint32_t rxfifooverflow; - __IO uint32_t rxvlanframes_gb; - __IO uint32_t rxwatchdogerror; - uint8_t RESERVED4[32]; - __IO uint32_t mmc_ipc_intr_mask_rx; - uint8_t RESERVED5[4]; - __IO uint32_t mmc_ipc_intr_rx; - uint8_t RESERVED6[4]; - __IO uint32_t rxipv4_gd_frms; - __IO uint32_t rxipv4_hdrerr_frms; - __IO uint32_t rxipv4_nopay_frms; - __IO uint32_t rxipv4_frag_frms; - __IO uint32_t rxipv4_udsbl_frms; - __IO uint32_t rxipv6_gd_frms; - __IO uint32_t rxipv6_hdrerr_frms; - __IO uint32_t rxipv6_nopay_frms; - __IO uint32_t rxudp_gd_frms; - __IO uint32_t rxudp_err_frms; - __IO uint32_t rxtcp_gd_frms; - __IO uint32_t rxtcp_err_frms; - __IO uint32_t rxicmp_gd_frms; - __IO uint32_t rxicmp_err_frms; - uint8_t RESERVED7[8]; - __IO uint32_t rxipv4_gd_octets; - __IO uint32_t rxipv4_hdrerr_octets; - __IO uint32_t rxipv4_nopay_octets; - __IO uint32_t rxipv4_frag_octets; - __IO uint32_t rxipv4_udsbl_octets; - __IO uint32_t rxipv6_gd_octets; - __IO uint32_t rxipv6_hdrerr_octets; - __IO uint32_t rxipv6_nopay_octets; - __IO uint32_t rxudp_gd_octets; - __IO uint32_t rxudp_err_octets; - __IO uint32_t rxtcp_gd_octets; - __IO uint32_t rxtcp_err_octets; - __IO uint32_t rxicmp_gd_octets; - __IO uint32_t rxicmp_err_octets; - uint8_t RESERVED8[1144]; - union { - __IO uint32_t TSCR; - stc_ethernet_mac_tscr_field_t TSCR_f; - }; - union { - __IO uint32_t SSIR; - stc_ethernet_mac_ssir_field_t SSIR_f; - }; - union { - __IO uint32_t STSR; - stc_ethernet_mac_stsr_field_t STSR_f; - }; - union { - __IO uint32_t STNR; - stc_ethernet_mac_stnr_field_t STNR_f; - }; - union { - __IO uint32_t STSUR; - stc_ethernet_mac_stsur_field_t STSUR_f; - }; - union { - __IO uint32_t STNUR; - stc_ethernet_mac_stnur_field_t STNUR_f; - }; - union { - __IO uint32_t TSAR; - stc_ethernet_mac_tsar_field_t TSAR_f; - }; - union { - __IO uint32_t TTSR; - stc_ethernet_mac_ttsr_field_t TTSR_f; - }; - union { - __IO uint32_t TTNR; - stc_ethernet_mac_ttnr_field_t TTNR_f; - }; - union { - __IO uint32_t STHWSR; - stc_ethernet_mac_sthwsr_field_t STHWSR_f; - }; - union { - __IO uint32_t TSR; - stc_ethernet_mac_tsr_field_t TSR_f; - }; - union { - __IO uint32_t PPSCR; - stc_ethernet_mac_ppscr_field_t PPSCR_f; - }; - union { - __IO uint32_t ATNR; - stc_ethernet_mac_atnr_field_t ATNR_f; - }; - union { - __IO uint32_t ATSR; - stc_ethernet_mac_atsr_field_t ATSR_f; - }; - uint8_t RESERVED9[200]; - union { - __IO uint32_t MAR16H; - stc_ethernet_mac_mar16h_field_t MAR16H_f; - }; - union { - __IO uint32_t MAR16L; - stc_ethernet_mac_mar16l_field_t MAR16L_f; - }; - union { - __IO uint32_t MAR17H; - stc_ethernet_mac_mar17h_field_t MAR17H_f; - }; - union { - __IO uint32_t MAR17L; - stc_ethernet_mac_mar17l_field_t MAR17L_f; - }; - union { - __IO uint32_t MAR18H; - stc_ethernet_mac_mar18h_field_t MAR18H_f; - }; - union { - __IO uint32_t MAR18L; - stc_ethernet_mac_mar18l_field_t MAR18L_f; - }; - union { - __IO uint32_t MAR19H; - stc_ethernet_mac_mar19h_field_t MAR19H_f; - }; - union { - __IO uint32_t MAR19L; - stc_ethernet_mac_mar19l_field_t MAR19L_f; - }; - union { - __IO uint32_t MAR20H; - stc_ethernet_mac_mar20h_field_t MAR20H_f; - }; - union { - __IO uint32_t MAR20L; - stc_ethernet_mac_mar20l_field_t MAR20L_f; - }; - union { - __IO uint32_t MAR21H; - stc_ethernet_mac_mar21h_field_t MAR21H_f; - }; - union { - __IO uint32_t MAR21L; - stc_ethernet_mac_mar21l_field_t MAR21L_f; - }; - union { - __IO uint32_t MAR22H; - stc_ethernet_mac_mar22h_field_t MAR22H_f; - }; - union { - __IO uint32_t MAR22L; - stc_ethernet_mac_mar22l_field_t MAR22L_f; - }; - union { - __IO uint32_t MAR23H; - stc_ethernet_mac_mar23h_field_t MAR23H_f; - }; - union { - __IO uint32_t MAR23L; - stc_ethernet_mac_mar23l_field_t MAR23L_f; - }; - union { - __IO uint32_t MAR24H; - stc_ethernet_mac_mar24h_field_t MAR24H_f; - }; - union { - __IO uint32_t MAR24L; - stc_ethernet_mac_mar24l_field_t MAR24L_f; - }; - union { - __IO uint32_t MAR25H; - stc_ethernet_mac_mar25h_field_t MAR25H_f; - }; - union { - __IO uint32_t MAR25L; - stc_ethernet_mac_mar25l_field_t MAR25L_f; - }; - union { - __IO uint32_t MAR26H; - stc_ethernet_mac_mar26h_field_t MAR26H_f; - }; - union { - __IO uint32_t MAR26L; - stc_ethernet_mac_mar26l_field_t MAR26L_f; - }; - union { - __IO uint32_t MAR27H; - stc_ethernet_mac_mar27h_field_t MAR27H_f; - }; - union { - __IO uint32_t MAR27L; - stc_ethernet_mac_mar27l_field_t MAR27L_f; - }; - union { - __IO uint32_t MAR28H; - stc_ethernet_mac_mar28h_field_t MAR28H_f; - }; - union { - __IO uint32_t MAR28L; - stc_ethernet_mac_mar28l_field_t MAR28L_f; - }; - union { - __IO uint32_t MAR29H; - stc_ethernet_mac_mar29h_field_t MAR29H_f; - }; - union { - __IO uint32_t MAR29L; - stc_ethernet_mac_mar29l_field_t MAR29L_f; - }; - union { - __IO uint32_t MAR30H; - stc_ethernet_mac_mar30h_field_t MAR30H_f; - }; - union { - __IO uint32_t MAR30L; - stc_ethernet_mac_mar30l_field_t MAR30L_f; - }; - union { - __IO uint32_t MAR31H; - stc_ethernet_mac_mar31h_field_t MAR31H_f; - }; - union { - __IO uint32_t MAR31L; - stc_ethernet_mac_mar31l_field_t MAR31L_f; - }; - uint8_t RESERVED10[1920]; - union { - __IO uint32_t BMR; - stc_ethernet_mac_bmr_field_t BMR_f; - }; - union { - __IO uint32_t TPDR; - stc_ethernet_mac_tpdr_field_t TPDR_f; - }; - union { - __IO uint32_t RPDR; - stc_ethernet_mac_rpdr_field_t RPDR_f; - }; - union { - __IO uint32_t RDLAR; - stc_ethernet_mac_rdlar_field_t RDLAR_f; - }; - union { - __IO uint32_t TDLAR; - stc_ethernet_mac_tdlar_field_t TDLAR_f; - }; - union { - __IO uint32_t SR; - stc_ethernet_mac_sr_field_t SR_f; - }; - union { - __IO uint32_t OMR; - stc_ethernet_mac_omr_field_t OMR_f; - }; - union { - __IO uint32_t IER; - stc_ethernet_mac_ier_field_t IER_f; - }; - union { - __IO uint32_t MFBOCR; - stc_ethernet_mac_mfbocr_field_t MFBOCR_f; - }; - union { - __IO uint32_t RIWTR; - stc_ethernet_mac_riwtr_field_t RIWTR_f; - }; - uint8_t RESERVED11[4]; - union { - __IO uint32_t AHBSR; - stc_ethernet_mac_ahbsr_field_t AHBSR_f; - }; - uint8_t RESERVED12[24]; - union { - __IO uint32_t CHTDR; - stc_ethernet_mac_chtdr_field_t CHTDR_f; - }; - union { - __IO uint32_t CHRDR; - stc_ethernet_mac_chrdr_field_t CHRDR_f; - }; - union { - __IO uint32_t CHTBAR; - stc_ethernet_mac_chtbar_field_t CHTBAR_f; - }; - union { - __IO uint32_t CHRBAR; - stc_ethernet_mac_chrbar_field_t CHRBAR_f; - }; -}FM3_ETHERNET_MAC_TypeDef; - -/* ETHERNET-CONTROL registers */ -typedef struct -{ - union { - __IO uint32_t ETH_MODE; - stc_ethernet_control_eth_mode_field_t ETH_MODE_f; - }; - uint8_t RESERVED1[4]; - union { - __IO uint32_t ETH_CLKG; - stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f; - }; -}FM3_ETHERNET_CONTROL_TypeDef; - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM3_MFT2_FRT_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Free Running Timer registers */ -#define FM3_MFT2_OCU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ -#define FM3_MFT2_WFG_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT2_ICU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ -#define FM3_MFT2_ADCMP_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM3_BT8_PPG_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ -#define FM3_BT8_PWM_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ -#define FM3_BT8_RT_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ -#define FM3_BT8_PWC_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ -#define FM3_BT9_PPG_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ -#define FM3_BT9_PWM_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ -#define FM3_BT9_RT_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ -#define FM3_BT9_PWC_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ -#define FM3_BT10_PPG_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ -#define FM3_BT10_PWM_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ -#define FM3_BT10_RT_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ -#define FM3_BT10_PWC_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ -#define FM3_BT11_PPG_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ -#define FM3_BT11_PWM_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ -#define FM3_BT11_RT_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ -#define FM3_BT11_PWC_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ -#define FM3_BT12_PPG_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ -#define FM3_BT12_PWM_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ -#define FM3_BT12_RT_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ -#define FM3_BT12_PWC_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ -#define FM3_BT13_PPG_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ -#define FM3_BT13_PWM_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ -#define FM3_BT13_RT_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ -#define FM3_BT13_PWC_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ -#define FM3_BT14_PPG_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ -#define FM3_BT14_PWM_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ -#define FM3_BT14_RT_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ -#define FM3_BT14_PWC_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ -#define FM3_BT15_PPG_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ -#define FM3_BT15_PWM_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ -#define FM3_BT15_RT_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ -#define FM3_BT15_PWC_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ -#define FM3_BTIOSEL8B_BASE (FM3_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ -#define FM3_BTIOSELCF_BASE (FM3_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ -#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM3_QPRC2_BASE (FM3_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ -#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ -#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ -#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ -#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ -#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ -#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ -#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ -#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ -#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ -#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ -#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ -#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ -#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ -#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ -#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ -#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ -#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ -#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ -#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ -#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ -#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ -#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ -#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ -#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ -#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ -#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ -#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ -#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ -#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ -#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ -#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ -#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ -#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ -#define FM3_MFS_NFC_BASE (FM3_PERIPH_BASE + 0x38800UL) /* MFS Noise Filter Control register */ -#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM3_USB1_BASE (FM3_PERIPH_BASE + 0x52100UL) /* USB channel 1 registers */ -#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM3_ETHERNET_MAC0_BASE (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers */ -#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers */ -#define FM3_ETHERNET_MAC1_BASE (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) -#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) -#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) -#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) -#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) -#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) -#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) -#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) -#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) -#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) -#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) -#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) -#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) -#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) -#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) -#define FM3_MFT2_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE) -#define FM3_MFT2_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE) -#define FM3_MFT2_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE) -#define FM3_MFT2_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE) -#define FM3_MFT2_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE) -#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) -#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) -#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) -#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) -#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) -#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) -#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) -#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) -#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) -#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) -#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) -#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) -#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) -#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) -#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) -#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) -#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) -#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) -#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) -#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) -#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) -#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) -#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) -#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) -#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) -#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) -#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) -#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) -#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) -#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) -#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) -#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) -#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) -#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) -#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) -#define FM3_BT8_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE) -#define FM3_BT8_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE) -#define FM3_BT8_RT ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE) -#define FM3_BT8_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE) -#define FM3_BT9_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE) -#define FM3_BT9_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE) -#define FM3_BT9_RT ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE) -#define FM3_BT9_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE) -#define FM3_BT10_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE) -#define FM3_BT10_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE) -#define FM3_BT10_RT ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE) -#define FM3_BT10_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE) -#define FM3_BT11_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE) -#define FM3_BT11_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE) -#define FM3_BT11_RT ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE) -#define FM3_BT11_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE) -#define FM3_BT12_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE) -#define FM3_BT12_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE) -#define FM3_BT12_RT ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE) -#define FM3_BT12_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE) -#define FM3_BT13_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE) -#define FM3_BT13_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE) -#define FM3_BT13_RT ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE) -#define FM3_BT13_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE) -#define FM3_BT14_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE) -#define FM3_BT14_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE) -#define FM3_BT14_RT ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE) -#define FM3_BT14_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE) -#define FM3_BT15_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE) -#define FM3_BT15_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE) -#define FM3_BT15_RT ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE) -#define FM3_BT15_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE) -#define FM3_BTIOSEL8B ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE) -#define FM3_BTIOSELCF ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE) -#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) -#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) -#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) -#define FM3_QPRC3 ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE) -#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) -#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) -#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) -#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) -#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) -#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) -#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) -#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) -#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE) -#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) -#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) -#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) -#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) -#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) -#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) -#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) -#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) -#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) -#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) -#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) -#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) -#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) -#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) -#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) -#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) -#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) -#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) -#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) -#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) -#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) -#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) -#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) -#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) -#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) -#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) -#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) -#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) -#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) -#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) -#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) -#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) -#define FM3_MFS_NFC ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE) -#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) -#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) -#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) -#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) -#define FM3_USB1 ((FM3_USB_TypeDef *)FM3_USB1_BASE) -#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) -#define FM3_ETHERNET_MAC0 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE) -#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_CONTROL_TypeDef *)FM3_ETHERNET_CONTROL_BASE) -#define FM3_ETHERNET_MAC1 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Flash interface registers */ -#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) -#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) - -/* Clock and reset registers */ -#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM3_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) -#define bFM3_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) -#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) -#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) - -/* Dual timer 1/2 registers */ -#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM3_DTIM_TIMER1RIS_TIMER1RIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM3_DTIM_TIMER1MIS_TIMER1MIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM3_DTIM_TIMER2RIS_TIMER2RIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM3_DTIM_TIMER2MIS_TIMER2MIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) -#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) -#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) -#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) -#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) -#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) -#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) -#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) -#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) -#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) -#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) -#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) -#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) -#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) -#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) -#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) -#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) -#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) -#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) -#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) -#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) -#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) -#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) -#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) -#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) -#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) -#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) -#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) -#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) -#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) -#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) -#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) -#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) -#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) -#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) -#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) -#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) -#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) -#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) -#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) -#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) -#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) -#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) -#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) -#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) -#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) -#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) -#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) -#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) -#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) -#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) -#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) -#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) -#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) -#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) -#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) -#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) -#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) -#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) -#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) -#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) -#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) -#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) -#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) -#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) -#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) -#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) -#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) -#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) -#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) -#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) -#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) -#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) -#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) -#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) -#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) -#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) -#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) -#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) -#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) -#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) -#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) -#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) -#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) -#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) -#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) -#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) -#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) -#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) -#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) -#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) -#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) -#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) -#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) -#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) -#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) -#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) -#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) -#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) -#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) -#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) -#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) -#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) -#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) -#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) -#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) -#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) -#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) -#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) -#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) -#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) -#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) -#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) -#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) -#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) -#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) -#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) -#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) -#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) -#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) -#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) -#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) -#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) -#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) -#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) -#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) -#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) -#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) -#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) -#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) -#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) -#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) -#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) -#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) -#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) -#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) -#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) -#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) -#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) -#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) -#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) -#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) -#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) -#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) -#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) -#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) -#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) -#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) -#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) -#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) -#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) -#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) -#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) -#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) -#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) -#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) -#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) -#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) -#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) -#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) -#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) -#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) -#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) -#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) -#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) -#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) -#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) -#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) -#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) -#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) -#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) -#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) -#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) -#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) -#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) - -/* Multifunction Timer unit 2 Free Running Timer registers */ -#define bFM3_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42440600UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42440604UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42440608UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244060CUL)) -#define bFM3_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42440610UL)) -#define bFM3_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42440614UL)) -#define bFM3_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42440618UL)) -#define bFM3_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244061CUL)) -#define bFM3_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42440620UL)) -#define bFM3_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42440624UL)) -#define bFM3_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42440634UL)) -#define bFM3_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42440638UL)) -#define bFM3_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244063CUL)) -#define bFM3_MFT2_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42440680UL)) -#define bFM3_MFT2_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42440684UL)) -#define bFM3_MFT2_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42440688UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42440800UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42440804UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42440808UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4244080CUL)) -#define bFM3_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42440810UL)) -#define bFM3_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42440814UL)) -#define bFM3_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42440818UL)) -#define bFM3_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4244081CUL)) -#define bFM3_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42440820UL)) -#define bFM3_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42440824UL)) -#define bFM3_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42440834UL)) -#define bFM3_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42440838UL)) -#define bFM3_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4244083CUL)) -#define bFM3_MFT2_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42440880UL)) -#define bFM3_MFT2_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42440884UL)) -#define bFM3_MFT2_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42440888UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42440A00UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42440A04UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42440A08UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42440A0CUL)) -#define bFM3_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42440A10UL)) -#define bFM3_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42440A14UL)) -#define bFM3_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42440A18UL)) -#define bFM3_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42440A1CUL)) -#define bFM3_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42440A20UL)) -#define bFM3_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42440A24UL)) -#define bFM3_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42440A34UL)) -#define bFM3_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42440A38UL)) -#define bFM3_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42440A3CUL)) -#define bFM3_MFT2_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42440A80UL)) -#define bFM3_MFT2_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42440A84UL)) -#define bFM3_MFT2_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42440A88UL)) - -/* Multifunction Timer unit 2 Output Compare Unit registers */ -#define bFM3_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42440300UL)) -#define bFM3_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42440304UL)) -#define bFM3_MFT2_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42440308UL)) -#define bFM3_MFT2_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4244030CUL)) -#define bFM3_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42440310UL)) -#define bFM3_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42440314UL)) -#define bFM3_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42440318UL)) -#define bFM3_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244031CUL)) -#define bFM3_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42440320UL)) -#define bFM3_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42440324UL)) -#define bFM3_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42440330UL)) -#define bFM3_MFT2_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42440334UL)) -#define bFM3_MFT2_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42440338UL)) -#define bFM3_MFT2_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42440380UL)) -#define bFM3_MFT2_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42440384UL)) -#define bFM3_MFT2_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42440388UL)) -#define bFM3_MFT2_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4244038CUL)) -#define bFM3_MFT2_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42440390UL)) -#define bFM3_MFT2_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42440394UL)) -#define bFM3_MFT2_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42440398UL)) -#define bFM3_MFT2_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4244039CUL)) -#define bFM3_MFT2_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424403A0UL)) -#define bFM3_MFT2_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424403A4UL)) -#define bFM3_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424403B0UL)) -#define bFM3_MFT2_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424403B4UL)) -#define bFM3_MFT2_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424403B8UL)) -#define bFM3_MFT2_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42440400UL)) -#define bFM3_MFT2_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42440404UL)) -#define bFM3_MFT2_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42440408UL)) -#define bFM3_MFT2_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4244040CUL)) -#define bFM3_MFT2_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42440410UL)) -#define bFM3_MFT2_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42440414UL)) -#define bFM3_MFT2_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42440418UL)) -#define bFM3_MFT2_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4244041CUL)) -#define bFM3_MFT2_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42440420UL)) -#define bFM3_MFT2_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42440424UL)) -#define bFM3_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42440430UL)) -#define bFM3_MFT2_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42440434UL)) -#define bFM3_MFT2_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42440438UL)) -#define bFM3_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424404A0UL)) -#define bFM3_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424404A4UL)) -#define bFM3_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424404A8UL)) -#define bFM3_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424404ACUL)) -#define bFM3_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424404B0UL)) -#define bFM3_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424404B4UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42440B00UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42440B04UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42440B08UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42440B0CUL)) -#define bFM3_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42440B10UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42440B14UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42440B18UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42440B1CUL)) -#define bFM3_MFT2_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42440B20UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42440B24UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42440B28UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42440B2CUL)) -#define bFM3_MFT2_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42440B30UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42440B34UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42440B38UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42440B3CUL)) -#define bFM3_MFT2_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42440B80UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42440B84UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42440B88UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42440B8CUL)) -#define bFM3_MFT2_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42440B90UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42440B94UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42440B98UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42440B9CUL)) - -/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42441180UL)) -#define bFM3_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42441184UL)) -#define bFM3_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42441188UL)) -#define bFM3_MFT2_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4244118CUL)) -#define bFM3_MFT2_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42441190UL)) -#define bFM3_MFT2_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42441194UL)) -#define bFM3_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42441198UL)) -#define bFM3_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244119CUL)) -#define bFM3_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424411A0UL)) -#define bFM3_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424411A4UL)) -#define bFM3_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424411A8UL)) -#define bFM3_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424411ACUL)) -#define bFM3_MFT2_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424411B0UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42441200UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42441204UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42441208UL)) -#define bFM3_MFT2_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4244120CUL)) -#define bFM3_MFT2_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42441210UL)) -#define bFM3_MFT2_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42441214UL)) -#define bFM3_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42441218UL)) -#define bFM3_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244121CUL)) -#define bFM3_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42441220UL)) -#define bFM3_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42441224UL)) -#define bFM3_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42441228UL)) -#define bFM3_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244122CUL)) -#define bFM3_MFT2_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42441230UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42441280UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42441284UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42441288UL)) -#define bFM3_MFT2_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4244128CUL)) -#define bFM3_MFT2_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42441290UL)) -#define bFM3_MFT2_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42441294UL)) -#define bFM3_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42441298UL)) -#define bFM3_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244129CUL)) -#define bFM3_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424412A0UL)) -#define bFM3_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424412A4UL)) -#define bFM3_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424412A8UL)) -#define bFM3_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424412ACUL)) -#define bFM3_MFT2_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424412B0UL)) -#define bFM3_MFT2_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42441300UL)) -#define bFM3_MFT2_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42441304UL)) -#define bFM3_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42441310UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42441314UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42441318UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244131CUL)) -#define bFM3_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42441320UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42441324UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42441328UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244132CUL)) -#define bFM3_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42441330UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42441334UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42441338UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244133CUL)) -#define bFM3_MFT2_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42441380UL)) -#define bFM3_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42441384UL)) -#define bFM3_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42441388UL)) -#define bFM3_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244138CUL)) -#define bFM3_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42441390UL)) - -/* Multifunction Timer unit 2 Input Capture Unit registers */ -#define bFM3_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42440C00UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42440C04UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42440C08UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42440C0CUL)) -#define bFM3_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42440C10UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42440C14UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42440C18UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42440C1CUL)) -#define bFM3_MFT2_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42440C20UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42440C24UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42440C28UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42440C2CUL)) -#define bFM3_MFT2_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42440C30UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42440C34UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42440C38UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42440C3CUL)) -#define bFM3_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42440F00UL)) -#define bFM3_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42440F04UL)) -#define bFM3_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42440F08UL)) -#define bFM3_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42440F0CUL)) -#define bFM3_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42440F10UL)) -#define bFM3_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42440F14UL)) -#define bFM3_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42440F18UL)) -#define bFM3_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42440F1CUL)) -#define bFM3_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42440F20UL)) -#define bFM3_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42440F24UL)) -#define bFM3_MFT2_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42440F80UL)) -#define bFM3_MFT2_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42440F84UL)) -#define bFM3_MFT2_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42440F88UL)) -#define bFM3_MFT2_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42440F8CUL)) -#define bFM3_MFT2_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42440F90UL)) -#define bFM3_MFT2_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42440F94UL)) -#define bFM3_MFT2_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42440F98UL)) -#define bFM3_MFT2_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42440F9CUL)) -#define bFM3_MFT2_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42440FA0UL)) -#define bFM3_MFT2_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42440FA4UL)) - -/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define bFM3_MFT2_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42441700UL)) -#define bFM3_MFT2_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42441704UL)) -#define bFM3_MFT2_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42441708UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42441710UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42441714UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42441718UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42441780UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42441784UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42441788UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4244178CUL)) -#define bFM3_MFT2_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42441790UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42441794UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424417A0UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424417A4UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424417A8UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424417ACUL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424417B0UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424417B4UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42441800UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42441804UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42441808UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4244180CUL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42441810UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42441814UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42441820UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42441824UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42441828UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4244182CUL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42441830UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42441834UL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) -#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) -#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) -#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) -#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) -#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) -#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) -#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) -#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) -#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) -#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) -#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) -#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) -#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) -#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) -#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) -#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) -#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) -#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) -#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) -#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) -#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) -#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) -#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) -#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) -#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) -#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) -#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) -#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) -#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) -#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) -#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) -#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) -#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) -#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) -#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) -#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) -#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) -#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) -#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) -#define bFM3_MFT_PPG_PPGC17_MD0 *((volatile unsigned int*)(0x42486004UL)) -#define bFM3_MFT_PPG_PPGC17_MD1 *((volatile unsigned int*)(0x42486008UL)) -#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) -#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) -#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) -#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) -#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) -#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) -#define bFM3_MFT_PPG_PPGC16_MD0 *((volatile unsigned int*)(0x42486024UL)) -#define bFM3_MFT_PPG_PPGC16_MD1 *((volatile unsigned int*)(0x42486028UL)) -#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) -#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) -#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) -#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) -#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) -#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) -#define bFM3_MFT_PPG_PPGC19_MD0 *((volatile unsigned int*)(0x42486084UL)) -#define bFM3_MFT_PPG_PPGC19_MD1 *((volatile unsigned int*)(0x42486088UL)) -#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) -#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) -#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) -#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) -#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) -#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) -#define bFM3_MFT_PPG_PPGC18_MD0 *((volatile unsigned int*)(0x424860A4UL)) -#define bFM3_MFT_PPG_PPGC18_MD1 *((volatile unsigned int*)(0x424860A8UL)) -#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) -#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) -#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) -#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) -#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) -#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) -#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) -#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) -#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) -#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) -#define bFM3_MFT_PPG_PPGC21_MD0 *((volatile unsigned int*)(0x42486804UL)) -#define bFM3_MFT_PPG_PPGC21_MD1 *((volatile unsigned int*)(0x42486808UL)) -#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) -#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) -#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) -#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) -#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) -#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) -#define bFM3_MFT_PPG_PPGC20_MD0 *((volatile unsigned int*)(0x42486824UL)) -#define bFM3_MFT_PPG_PPGC20_MD1 *((volatile unsigned int*)(0x42486828UL)) -#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) -#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) -#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) -#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) -#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) -#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) -#define bFM3_MFT_PPG_PPGC23_MD0 *((volatile unsigned int*)(0x42486884UL)) -#define bFM3_MFT_PPG_PPGC23_MD1 *((volatile unsigned int*)(0x42486888UL)) -#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) -#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) -#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) -#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) -#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) -#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) -#define bFM3_MFT_PPG_PPGC22_MD0 *((volatile unsigned int*)(0x424868A4UL)) -#define bFM3_MFT_PPG_PPGC22_MD1 *((volatile unsigned int*)(0x424868A8UL)) -#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) -#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) -#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) -#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) -#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) -#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) -#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) -#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) -#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Base Timer 8 PPG registers */ -#define bFM3_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) -#define bFM3_BT8_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) -#define bFM3_BT8_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) -#define bFM3_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM3_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWM registers */ -#define bFM3_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) -#define bFM3_BT8_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) -#define bFM3_BT8_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) -#define bFM3_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM3_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) -#define bFM3_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) -#define bFM3_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 RT registers */ -#define bFM3_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) -#define bFM3_BT8_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) -#define bFM3_BT8_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) -#define bFM3_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM3_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWC registers */ -#define bFM3_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A8190UL)) -#define bFM3_BT8_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A8194UL)) -#define bFM3_BT8_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A8198UL)) -#define bFM3_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM3_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) -#define bFM3_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 9 PPG registers */ -#define bFM3_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) -#define bFM3_BT9_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) -#define bFM3_BT9_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) -#define bFM3_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM3_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWM registers */ -#define bFM3_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) -#define bFM3_BT9_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) -#define bFM3_BT9_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) -#define bFM3_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM3_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) -#define bFM3_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) -#define bFM3_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 RT registers */ -#define bFM3_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) -#define bFM3_BT9_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) -#define bFM3_BT9_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) -#define bFM3_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM3_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWC registers */ -#define bFM3_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A8990UL)) -#define bFM3_BT9_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A8994UL)) -#define bFM3_BT9_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A8998UL)) -#define bFM3_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM3_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) -#define bFM3_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 10 PPG registers */ -#define bFM3_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) -#define bFM3_BT10_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) -#define bFM3_BT10_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) -#define bFM3_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM3_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWM registers */ -#define bFM3_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) -#define bFM3_BT10_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) -#define bFM3_BT10_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) -#define bFM3_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM3_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) -#define bFM3_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) -#define bFM3_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 RT registers */ -#define bFM3_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) -#define bFM3_BT10_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) -#define bFM3_BT10_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) -#define bFM3_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM3_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWC registers */ -#define bFM3_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A9190UL)) -#define bFM3_BT10_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A9194UL)) -#define bFM3_BT10_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A9198UL)) -#define bFM3_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM3_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) -#define bFM3_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 11 PPG registers */ -#define bFM3_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) -#define bFM3_BT11_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) -#define bFM3_BT11_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) -#define bFM3_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM3_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWM registers */ -#define bFM3_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) -#define bFM3_BT11_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) -#define bFM3_BT11_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) -#define bFM3_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM3_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) -#define bFM3_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) -#define bFM3_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 RT registers */ -#define bFM3_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) -#define bFM3_BT11_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) -#define bFM3_BT11_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) -#define bFM3_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM3_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWC registers */ -#define bFM3_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A9990UL)) -#define bFM3_BT11_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A9994UL)) -#define bFM3_BT11_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A9998UL)) -#define bFM3_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM3_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) -#define bFM3_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 12 PPG registers */ -#define bFM3_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) -#define bFM3_BT12_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) -#define bFM3_BT12_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) -#define bFM3_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM3_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWM registers */ -#define bFM3_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) -#define bFM3_BT12_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) -#define bFM3_BT12_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) -#define bFM3_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM3_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) -#define bFM3_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) -#define bFM3_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 RT registers */ -#define bFM3_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) -#define bFM3_BT12_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) -#define bFM3_BT12_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) -#define bFM3_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM3_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWC registers */ -#define bFM3_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AC190UL)) -#define bFM3_BT12_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AC194UL)) -#define bFM3_BT12_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AC198UL)) -#define bFM3_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM3_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) -#define bFM3_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 13 PPG registers */ -#define bFM3_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) -#define bFM3_BT13_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) -#define bFM3_BT13_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) -#define bFM3_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM3_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWM registers */ -#define bFM3_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) -#define bFM3_BT13_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) -#define bFM3_BT13_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) -#define bFM3_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM3_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) -#define bFM3_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) -#define bFM3_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 RT registers */ -#define bFM3_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) -#define bFM3_BT13_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) -#define bFM3_BT13_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) -#define bFM3_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM3_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWC registers */ -#define bFM3_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AC990UL)) -#define bFM3_BT13_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AC994UL)) -#define bFM3_BT13_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AC998UL)) -#define bFM3_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM3_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) -#define bFM3_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 14 PPG registers */ -#define bFM3_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) -#define bFM3_BT14_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) -#define bFM3_BT14_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) -#define bFM3_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM3_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWM registers */ -#define bFM3_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) -#define bFM3_BT14_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) -#define bFM3_BT14_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) -#define bFM3_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM3_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) -#define bFM3_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) -#define bFM3_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 RT registers */ -#define bFM3_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) -#define bFM3_BT14_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) -#define bFM3_BT14_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) -#define bFM3_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM3_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWC registers */ -#define bFM3_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AD190UL)) -#define bFM3_BT14_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AD194UL)) -#define bFM3_BT14_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AD198UL)) -#define bFM3_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM3_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) -#define bFM3_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 15 PPG registers */ -#define bFM3_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) -#define bFM3_BT15_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) -#define bFM3_BT15_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) -#define bFM3_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM3_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWM registers */ -#define bFM3_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) -#define bFM3_BT15_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) -#define bFM3_BT15_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) -#define bFM3_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM3_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) -#define bFM3_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) -#define bFM3_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 RT registers */ -#define bFM3_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) -#define bFM3_BT15_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) -#define bFM3_BT15_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) -#define bFM3_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM3_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWC registers */ -#define bFM3_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424AD990UL)) -#define bFM3_BT15_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424AD994UL)) -#define bFM3_BT15_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424AD998UL)) -#define bFM3_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM3_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) -#define bFM3_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer I/O selector channel 8 - channel 11 registers */ -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) - -/* Base Timer I/O selector channel 12 - channel 15 registers */ -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* Quad position and revolution counter channel 2 registers */ -#define bFM3_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM3_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM3_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM3_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM3_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM3_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM3_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM3_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM3_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM3_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM3_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM3_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM3_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM3_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM3_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM3_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM3_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM3_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM3_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM3_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM3_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM3_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM3_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM3_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM3_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM3_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM3_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM3_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM3_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM3_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM3_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM3_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM3_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM3_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM3_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM3_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM3_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM3_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM3_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM3_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM3_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM3_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM3_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM3_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM3_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM3_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM3_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM3_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM3_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM3_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM3_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM3_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM3_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM3_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM3_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM3_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM3_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM3_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM3_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM3_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM3_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) -#define bFM3_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) -#define bFM3_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) -#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) -#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) -#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) -#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) -#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) -#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) -#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) -#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) -#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) -#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) -#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) -#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) -#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) -#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) -#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) -#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) -#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) -#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) -#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) -#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) -#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) - -/* CR trimming registers */ -#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) - -/* External interrupt registers */ -#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM3_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) -#define bFM3_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) -#define bFM3_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) -#define bFM3_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) -#define bFM3_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) -#define bFM3_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) -#define bFM3_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) -#define bFM3_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) -#define bFM3_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) -#define bFM3_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) -#define bFM3_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) -#define bFM3_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) -#define bFM3_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) -#define bFM3_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) -#define bFM3_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) -#define bFM3_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) -#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM3_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) -#define bFM3_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) -#define bFM3_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) -#define bFM3_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) -#define bFM3_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) -#define bFM3_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) -#define bFM3_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) -#define bFM3_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) -#define bFM3_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) -#define bFM3_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) -#define bFM3_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) -#define bFM3_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) -#define bFM3_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) -#define bFM3_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) -#define bFM3_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) -#define bFM3_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) -#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM3_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) -#define bFM3_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) -#define bFM3_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) -#define bFM3_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) -#define bFM3_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) -#define bFM3_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) -#define bFM3_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) -#define bFM3_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) -#define bFM3_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) -#define bFM3_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) -#define bFM3_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) -#define bFM3_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) -#define bFM3_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) -#define bFM3_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) -#define bFM3_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) -#define bFM3_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) -#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM3_EXTI_ELVR_LA16 *((volatile unsigned int*)(0x42600200UL)) -#define bFM3_EXTI_ELVR_LB16 *((volatile unsigned int*)(0x42600204UL)) -#define bFM3_EXTI_ELVR_LA17 *((volatile unsigned int*)(0x42600208UL)) -#define bFM3_EXTI_ELVR_LB17 *((volatile unsigned int*)(0x4260020CUL)) -#define bFM3_EXTI_ELVR_LA18 *((volatile unsigned int*)(0x42600210UL)) -#define bFM3_EXTI_ELVR_LB18 *((volatile unsigned int*)(0x42600214UL)) -#define bFM3_EXTI_ELVR_LA19 *((volatile unsigned int*)(0x42600218UL)) -#define bFM3_EXTI_ELVR_LB19 *((volatile unsigned int*)(0x4260021CUL)) -#define bFM3_EXTI_ELVR_LA20 *((volatile unsigned int*)(0x42600220UL)) -#define bFM3_EXTI_ELVR_LB20 *((volatile unsigned int*)(0x42600224UL)) -#define bFM3_EXTI_ELVR_LA21 *((volatile unsigned int*)(0x42600228UL)) -#define bFM3_EXTI_ELVR_LB21 *((volatile unsigned int*)(0x4260022CUL)) -#define bFM3_EXTI_ELVR_LA22 *((volatile unsigned int*)(0x42600230UL)) -#define bFM3_EXTI_ELVR_LB22 *((volatile unsigned int*)(0x42600234UL)) -#define bFM3_EXTI_ELVR_LA23 *((volatile unsigned int*)(0x42600238UL)) -#define bFM3_EXTI_ELVR_LB23 *((volatile unsigned int*)(0x4260023CUL)) -#define bFM3_EXTI_ELVR_LA24 *((volatile unsigned int*)(0x42600240UL)) -#define bFM3_EXTI_ELVR_LB24 *((volatile unsigned int*)(0x42600244UL)) -#define bFM3_EXTI_ELVR_LA25 *((volatile unsigned int*)(0x42600248UL)) -#define bFM3_EXTI_ELVR_LB25 *((volatile unsigned int*)(0x4260024CUL)) -#define bFM3_EXTI_ELVR_LA26 *((volatile unsigned int*)(0x42600250UL)) -#define bFM3_EXTI_ELVR_LB26 *((volatile unsigned int*)(0x42600254UL)) -#define bFM3_EXTI_ELVR_LA27 *((volatile unsigned int*)(0x42600258UL)) -#define bFM3_EXTI_ELVR_LB27 *((volatile unsigned int*)(0x4260025CUL)) -#define bFM3_EXTI_ELVR_LA28 *((volatile unsigned int*)(0x42600260UL)) -#define bFM3_EXTI_ELVR_LB28 *((volatile unsigned int*)(0x42600264UL)) -#define bFM3_EXTI_ELVR_LA29 *((volatile unsigned int*)(0x42600268UL)) -#define bFM3_EXTI_ELVR_LB29 *((volatile unsigned int*)(0x4260026CUL)) -#define bFM3_EXTI_ELVR_LA30 *((volatile unsigned int*)(0x42600270UL)) -#define bFM3_EXTI_ELVR_LB30 *((volatile unsigned int*)(0x42600274UL)) -#define bFM3_EXTI_ELVR_LA31 *((volatile unsigned int*)(0x42600278UL)) -#define bFM3_EXTI_ELVR_LB31 *((volatile unsigned int*)(0x4260027CUL)) -#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) -#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned char*)(0x42620160UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned char*)(0x42620164UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned char*)(0x42620168UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned char*)(0x4262016CUL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned char*)(0x42620170UL)) -#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) -#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) -#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) -#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) -#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT0 *((volatile unsigned int*)(0x42620420UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT1 *((volatile unsigned int*)(0x42620424UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT2 *((volatile unsigned int*)(0x42620428UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT3 *((volatile unsigned int*)(0x4262042CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT8 *((volatile unsigned int*)(0x42620520UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT9 *((volatile unsigned int*)(0x42620524UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT10 *((volatile unsigned int*)(0x42620528UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT11 *((volatile unsigned int*)(0x4262052CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT12 *((volatile unsigned int*)(0x42620530UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT13 *((volatile unsigned int*)(0x42620534UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT14 *((volatile unsigned int*)(0x42620538UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT15 *((volatile unsigned int*)(0x4262053CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT16 *((volatile unsigned int*)(0x42620540UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT17 *((volatile unsigned int*)(0x42620544UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT18 *((volatile unsigned int*)(0x42620548UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT19 *((volatile unsigned int*)(0x4262054CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT20 *((volatile unsigned int*)(0x42620550UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT21 *((volatile unsigned int*)(0x42620554UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT22 *((volatile unsigned int*)(0x42620558UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT23 *((volatile unsigned int*)(0x4262055CUL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620580UL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT2 *((volatile unsigned int*)(0x42620584UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT0 *((volatile unsigned int*)(0x426205B8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT1 *((volatile unsigned int*)(0x426205BCUL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT2 *((volatile unsigned int*)(0x426205C0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT3 *((volatile unsigned int*)(0x426205C4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT4 *((volatile unsigned int*)(0x426205C8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT5 *((volatile unsigned int*)(0x426205CCUL)) -#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) -#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) -#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) -#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) -#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) -#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) -#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) -#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT6 *((volatile unsigned int*)(0x42620E18UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT7 *((volatile unsigned int*)(0x42620E1CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT8 *((volatile unsigned int*)(0x42620E20UL)) -#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) -#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) -#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) -#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) -#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT0 *((volatile unsigned int*)(0x426210B0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT1 *((volatile unsigned int*)(0x426210B4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT2 *((volatile unsigned int*)(0x426210B8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT3 *((volatile unsigned int*)(0x426210BCUL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT4 *((volatile unsigned int*)(0x426210C0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT5 *((volatile unsigned int*)(0x426210C4UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT0 *((volatile unsigned int*)(0x42621120UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT1 *((volatile unsigned int*)(0x42621124UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT2 *((volatile unsigned int*)(0x42621128UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT3 *((volatile unsigned int*)(0x4262112CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT0 *((volatile unsigned int*)(0x426211B0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT1 *((volatile unsigned int*)(0x426211B4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT2 *((volatile unsigned int*)(0x426211B8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT3 *((volatile unsigned int*)(0x426211BCUL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT4 *((volatile unsigned int*)(0x426211C0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT5 *((volatile unsigned int*)(0x426211C4UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) -#define bFM3_INTREQ_IRQ32MON_MAC0SBD *((volatile unsigned int*)(0x42621284UL)) -#define bFM3_INTREQ_IRQ32MON_MAC0PMI *((volatile unsigned int*)(0x42621288UL)) -#define bFM3_INTREQ_IRQ32MON_MAC0LPI *((volatile unsigned int*)(0x4262128CUL)) -#define bFM3_INTREQ_IRQ33MON_MAC1SBD *((volatile unsigned int*)(0x42621304UL)) -#define bFM3_INTREQ_IRQ33MON_MAC1PMI *((volatile unsigned int*)(0x42621308UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT0 *((volatile unsigned int*)(0x42621480UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT1 *((volatile unsigned int*)(0x42621484UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT2 *((volatile unsigned int*)(0x42621488UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT3 *((volatile unsigned int*)(0x4262148CUL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT4 *((volatile unsigned int*)(0x42621490UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT0 *((volatile unsigned int*)(0x42621500UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT1 *((volatile unsigned int*)(0x42621504UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT2 *((volatile unsigned int*)(0x42621508UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT3 *((volatile unsigned int*)(0x4262150CUL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT4 *((volatile unsigned int*)(0x42621510UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT5 *((volatile unsigned int*)(0x42621514UL)) -#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) -#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) -#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) -#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) -#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) -#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) -#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) -#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT0 *((volatile unsigned int*)(0x42621980UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT1 *((volatile unsigned int*)(0x42621984UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT2 *((volatile unsigned int*)(0x42621988UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT3 *((volatile unsigned int*)(0x4262198CUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT4 *((volatile unsigned int*)(0x42621990UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT5 *((volatile unsigned int*)(0x42621994UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT6 *((volatile unsigned int*)(0x42621998UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT7 *((volatile unsigned int*)(0x4262199CUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT8 *((volatile unsigned int*)(0x426219A0UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT9 *((volatile unsigned int*)(0x426219A4UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT10 *((volatile unsigned int*)(0x426219A8UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT11 *((volatile unsigned int*)(0x426219ACUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT12 *((volatile unsigned int*)(0x426219B0UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT13 *((volatile unsigned int*)(0x426219B4UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT14 *((volatile unsigned int*)(0x426219B8UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT15 *((volatile unsigned int*)(0x426219BCUL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL10 *((volatile unsigned int*)(0x42624000UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL11 *((volatile unsigned int*)(0x42624004UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL12 *((volatile unsigned int*)(0x42624008UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL13 *((volatile unsigned int*)(0x4262400CUL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL14 *((volatile unsigned int*)(0x42624010UL)) -#define bFM3_INTREQ_DQESEL_ESEL100 *((volatile unsigned int*)(0x42624080UL)) -#define bFM3_INTREQ_DQESEL_ESEL101 *((volatile unsigned int*)(0x42624084UL)) -#define bFM3_INTREQ_DQESEL_ESEL102 *((volatile unsigned int*)(0x42624088UL)) -#define bFM3_INTREQ_DQESEL_ESEL103 *((volatile unsigned int*)(0x4262408CUL)) -#define bFM3_INTREQ_DQESEL_ESEL110 *((volatile unsigned int*)(0x42624090UL)) -#define bFM3_INTREQ_DQESEL_ESEL111 *((volatile unsigned int*)(0x42624094UL)) -#define bFM3_INTREQ_DQESEL_ESEL112 *((volatile unsigned int*)(0x42624098UL)) -#define bFM3_INTREQ_DQESEL_ESEL113 *((volatile unsigned int*)(0x4262409CUL)) -#define bFM3_INTREQ_DQESEL_ESEL240 *((volatile unsigned int*)(0x426240A0UL)) -#define bFM3_INTREQ_DQESEL_ESEL241 *((volatile unsigned int*)(0x426240A4UL)) -#define bFM3_INTREQ_DQESEL_ESEL242 *((volatile unsigned int*)(0x426240A8UL)) -#define bFM3_INTREQ_DQESEL_ESEL243 *((volatile unsigned int*)(0x426240ACUL)) -#define bFM3_INTREQ_DQESEL_ESEL250 *((volatile unsigned int*)(0x426240B0UL)) -#define bFM3_INTREQ_DQESEL_ESEL251 *((volatile unsigned int*)(0x426240B4UL)) -#define bFM3_INTREQ_DQESEL_ESEL252 *((volatile unsigned int*)(0x426240B8UL)) -#define bFM3_INTREQ_DQESEL_ESEL253 *((volatile unsigned int*)(0x426240BCUL)) -#define bFM3_INTREQ_DQESEL_ESEL260 *((volatile unsigned int*)(0x426240C0UL)) -#define bFM3_INTREQ_DQESEL_ESEL261 *((volatile unsigned int*)(0x426240C4UL)) -#define bFM3_INTREQ_DQESEL_ESEL262 *((volatile unsigned int*)(0x426240C8UL)) -#define bFM3_INTREQ_DQESEL_ESEL263 *((volatile unsigned int*)(0x426240CCUL)) -#define bFM3_INTREQ_DQESEL_ESEL270 *((volatile unsigned int*)(0x426240D0UL)) -#define bFM3_INTREQ_DQESEL_ESEL271 *((volatile unsigned int*)(0x426240D4UL)) -#define bFM3_INTREQ_DQESEL_ESEL272 *((volatile unsigned int*)(0x426240D8UL)) -#define bFM3_INTREQ_DQESEL_ESEL273 *((volatile unsigned int*)(0x426240DCUL)) -#define bFM3_INTREQ_DQESEL_ESEL300 *((volatile unsigned int*)(0x426240E0UL)) -#define bFM3_INTREQ_DQESEL_ESEL301 *((volatile unsigned int*)(0x426240E4UL)) -#define bFM3_INTREQ_DQESEL_ESEL302 *((volatile unsigned int*)(0x426240E8UL)) -#define bFM3_INTREQ_DQESEL_ESEL303 *((volatile unsigned int*)(0x426240ECUL)) -#define bFM3_INTREQ_DQESEL_ESEL310 *((volatile unsigned int*)(0x426240F0UL)) -#define bFM3_INTREQ_DQESEL_ESEL311 *((volatile unsigned int*)(0x426240F4UL)) -#define bFM3_INTREQ_DQESEL_ESEL312 *((volatile unsigned int*)(0x426240F8UL)) -#define bFM3_INTREQ_DQESEL_ESEL313 *((volatile unsigned int*)(0x426240FCUL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS10 *((volatile unsigned char*)(0x426241E0UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS11 *((volatile unsigned char*)(0x426241E4UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS12 *((volatile unsigned char*)(0x426241E8UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS13 *((volatile unsigned char*)(0x426241ECUL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS14 *((volatile unsigned char*)(0x426241F0UL)) - -/* General purpose I/O registers */ -#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) -#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) -#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) -#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) -#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) -#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) -#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) -#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) -#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) -#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) -#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) -#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) -#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) -#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) -#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) -#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) -#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) -#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) -#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) -#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) -#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) -#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) -#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) -#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) -#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) -#define bFM3_GPIO_PFR2_P9 *((volatile unsigned int*)(0x42660124UL)) -#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) -#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) -#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) -#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) -#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) -#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) -#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) -#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) -#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) -#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) -#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) -#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) -#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) -#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) -#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) -#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) -#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) -#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) -#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) -#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) -#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) -#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) -#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) -#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) -#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) -#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) -#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) -#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) -#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) -#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) -#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) -#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) -#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) -#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) -#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) -#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) -#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) -#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) -#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) -#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) -#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) -#define bFM3_GPIO_PFR7_P5 *((volatile unsigned int*)(0x42660394UL)) -#define bFM3_GPIO_PFR7_P6 *((volatile unsigned int*)(0x42660398UL)) -#define bFM3_GPIO_PFR7_P7 *((volatile unsigned int*)(0x4266039CUL)) -#define bFM3_GPIO_PFR7_P8 *((volatile unsigned int*)(0x426603A0UL)) -#define bFM3_GPIO_PFR7_P9 *((volatile unsigned int*)(0x426603A4UL)) -#define bFM3_GPIO_PFR7_PA *((volatile unsigned int*)(0x426603A8UL)) -#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) -#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) -#define bFM3_GPIO_PFR8_P2 *((volatile unsigned int*)(0x42660408UL)) -#define bFM3_GPIO_PFR8_P3 *((volatile unsigned int*)(0x4266040CUL)) -#define bFM3_GPIO_PFRA_P0 *((volatile unsigned int*)(0x42660500UL)) -#define bFM3_GPIO_PFRA_P1 *((volatile unsigned int*)(0x42660504UL)) -#define bFM3_GPIO_PFRA_P2 *((volatile unsigned int*)(0x42660508UL)) -#define bFM3_GPIO_PFRA_P3 *((volatile unsigned int*)(0x4266050CUL)) -#define bFM3_GPIO_PFRA_P4 *((volatile unsigned int*)(0x42660510UL)) -#define bFM3_GPIO_PFRA_P5 *((volatile unsigned int*)(0x42660514UL)) -#define bFM3_GPIO_PFRC_P0 *((volatile unsigned int*)(0x42660600UL)) -#define bFM3_GPIO_PFRC_P1 *((volatile unsigned int*)(0x42660604UL)) -#define bFM3_GPIO_PFRC_P2 *((volatile unsigned int*)(0x42660608UL)) -#define bFM3_GPIO_PFRC_P3 *((volatile unsigned int*)(0x4266060CUL)) -#define bFM3_GPIO_PFRC_P4 *((volatile unsigned int*)(0x42660610UL)) -#define bFM3_GPIO_PFRC_P5 *((volatile unsigned int*)(0x42660614UL)) -#define bFM3_GPIO_PFRC_P6 *((volatile unsigned int*)(0x42660618UL)) -#define bFM3_GPIO_PFRC_P7 *((volatile unsigned int*)(0x4266061CUL)) -#define bFM3_GPIO_PFRC_P8 *((volatile unsigned int*)(0x42660620UL)) -#define bFM3_GPIO_PFRC_P9 *((volatile unsigned int*)(0x42660624UL)) -#define bFM3_GPIO_PFRC_PA *((volatile unsigned int*)(0x42660628UL)) -#define bFM3_GPIO_PFRC_PB *((volatile unsigned int*)(0x4266062CUL)) -#define bFM3_GPIO_PFRC_PC *((volatile unsigned int*)(0x42660630UL)) -#define bFM3_GPIO_PFRC_PD *((volatile unsigned int*)(0x42660634UL)) -#define bFM3_GPIO_PFRC_PE *((volatile unsigned int*)(0x42660638UL)) -#define bFM3_GPIO_PFRC_PF *((volatile unsigned int*)(0x4266063CUL)) -#define bFM3_GPIO_PFRD_P0 *((volatile unsigned int*)(0x42660680UL)) -#define bFM3_GPIO_PFRD_P1 *((volatile unsigned int*)(0x42660684UL)) -#define bFM3_GPIO_PFRD_P2 *((volatile unsigned int*)(0x42660688UL)) -#define bFM3_GPIO_PFRD_P3 *((volatile unsigned int*)(0x4266068CUL)) -#define bFM3_GPIO_PFRE_P0 *((volatile unsigned int*)(0x42660700UL)) -#define bFM3_GPIO_PFRE_P2 *((volatile unsigned int*)(0x42660708UL)) -#define bFM3_GPIO_PFRE_P3 *((volatile unsigned int*)(0x4266070CUL)) -#define bFM3_GPIO_PFRF_P5 *((volatile unsigned int*)(0x42660794UL)) -#define bFM3_GPIO_PFRF_P6 *((volatile unsigned int*)(0x42660798UL)) -#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) -#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) -#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) -#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) -#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) -#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) -#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) -#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) -#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) -#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) -#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) -#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) -#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) -#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) -#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) -#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) -#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) -#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) -#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) -#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) -#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) -#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) -#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) -#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) -#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) -#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) -#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) -#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) -#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) -#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) -#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) -#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) -#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) -#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) -#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) -#define bFM3_GPIO_PCR2_P9 *((volatile unsigned int*)(0x42662124UL)) -#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) -#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) -#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) -#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) -#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) -#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) -#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) -#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) -#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) -#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) -#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) -#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) -#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) -#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) -#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) -#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) -#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) -#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) -#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) -#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) -#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) -#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) -#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) -#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) -#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) -#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) -#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) -#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) -#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) -#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) -#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) -#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) -#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) -#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) -#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) -#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) -#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) -#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) -#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) -#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) -#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) -#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) -#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) -#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) -#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) -#define bFM3_GPIO_PCR7_P5 *((volatile unsigned int*)(0x42662394UL)) -#define bFM3_GPIO_PCR7_P6 *((volatile unsigned int*)(0x42662398UL)) -#define bFM3_GPIO_PCR7_P7 *((volatile unsigned int*)(0x4266239CUL)) -#define bFM3_GPIO_PCR7_P8 *((volatile unsigned int*)(0x426623A0UL)) -#define bFM3_GPIO_PCR7_P9 *((volatile unsigned int*)(0x426623A4UL)) -#define bFM3_GPIO_PCR7_PA *((volatile unsigned int*)(0x426623A8UL)) -#define bFM3_GPIO_PCRA_P0 *((volatile unsigned int*)(0x42662500UL)) -#define bFM3_GPIO_PCRA_P1 *((volatile unsigned int*)(0x42662504UL)) -#define bFM3_GPIO_PCRA_P2 *((volatile unsigned int*)(0x42662508UL)) -#define bFM3_GPIO_PCRA_P3 *((volatile unsigned int*)(0x4266250CUL)) -#define bFM3_GPIO_PCRA_P4 *((volatile unsigned int*)(0x42662510UL)) -#define bFM3_GPIO_PCRA_P5 *((volatile unsigned int*)(0x42662514UL)) -#define bFM3_GPIO_PCRC_P0 *((volatile unsigned int*)(0x42662600UL)) -#define bFM3_GPIO_PCRC_P1 *((volatile unsigned int*)(0x42662604UL)) -#define bFM3_GPIO_PCRC_P2 *((volatile unsigned int*)(0x42662608UL)) -#define bFM3_GPIO_PCRC_P3 *((volatile unsigned int*)(0x4266260CUL)) -#define bFM3_GPIO_PCRC_P4 *((volatile unsigned int*)(0x42662610UL)) -#define bFM3_GPIO_PCRC_P5 *((volatile unsigned int*)(0x42662614UL)) -#define bFM3_GPIO_PCRC_P6 *((volatile unsigned int*)(0x42662618UL)) -#define bFM3_GPIO_PCRC_P7 *((volatile unsigned int*)(0x4266261CUL)) -#define bFM3_GPIO_PCRC_P8 *((volatile unsigned int*)(0x42662620UL)) -#define bFM3_GPIO_PCRC_P9 *((volatile unsigned int*)(0x42662624UL)) -#define bFM3_GPIO_PCRC_PA *((volatile unsigned int*)(0x42662628UL)) -#define bFM3_GPIO_PCRC_PB *((volatile unsigned int*)(0x4266262CUL)) -#define bFM3_GPIO_PCRC_PC *((volatile unsigned int*)(0x42662630UL)) -#define bFM3_GPIO_PCRC_PD *((volatile unsigned int*)(0x42662634UL)) -#define bFM3_GPIO_PCRC_PE *((volatile unsigned int*)(0x42662638UL)) -#define bFM3_GPIO_PCRC_PF *((volatile unsigned int*)(0x4266263CUL)) -#define bFM3_GPIO_PCRD_P0 *((volatile unsigned int*)(0x42662680UL)) -#define bFM3_GPIO_PCRD_P1 *((volatile unsigned int*)(0x42662684UL)) -#define bFM3_GPIO_PCRD_P2 *((volatile unsigned int*)(0x42662688UL)) -#define bFM3_GPIO_PCRD_P3 *((volatile unsigned int*)(0x4266268CUL)) -#define bFM3_GPIO_PCRE_P2 *((volatile unsigned int*)(0x42662708UL)) -#define bFM3_GPIO_PCRE_P3 *((volatile unsigned int*)(0x4266270CUL)) -#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) -#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) -#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) -#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) -#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) -#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) -#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) -#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) -#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) -#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) -#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) -#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) -#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) -#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) -#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) -#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) -#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) -#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) -#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) -#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) -#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) -#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) -#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) -#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) -#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) -#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) -#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) -#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) -#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) -#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) -#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) -#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) -#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) -#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) -#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) -#define bFM3_GPIO_DDR2_P9 *((volatile unsigned int*)(0x42664124UL)) -#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) -#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) -#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) -#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) -#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) -#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) -#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) -#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) -#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) -#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) -#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) -#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) -#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) -#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) -#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) -#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) -#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) -#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) -#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) -#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) -#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) -#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) -#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) -#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) -#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) -#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) -#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) -#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) -#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) -#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) -#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) -#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) -#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) -#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) -#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) -#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) -#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) -#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) -#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) -#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) -#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) -#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) -#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) -#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) -#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) -#define bFM3_GPIO_DDR7_P5 *((volatile unsigned int*)(0x42664394UL)) -#define bFM3_GPIO_DDR7_P6 *((volatile unsigned int*)(0x42664398UL)) -#define bFM3_GPIO_DDR7_P7 *((volatile unsigned int*)(0x4266439CUL)) -#define bFM3_GPIO_DDR7_P8 *((volatile unsigned int*)(0x426643A0UL)) -#define bFM3_GPIO_DDR7_P9 *((volatile unsigned int*)(0x426643A4UL)) -#define bFM3_GPIO_DDR7_PA *((volatile unsigned int*)(0x426643A8UL)) -#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) -#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) -#define bFM3_GPIO_DDR8_P2 *((volatile unsigned int*)(0x42664408UL)) -#define bFM3_GPIO_DDR8_P3 *((volatile unsigned int*)(0x4266440CUL)) -#define bFM3_GPIO_DDRA_P0 *((volatile unsigned int*)(0x42664500UL)) -#define bFM3_GPIO_DDRA_P1 *((volatile unsigned int*)(0x42664504UL)) -#define bFM3_GPIO_DDRA_P2 *((volatile unsigned int*)(0x42664508UL)) -#define bFM3_GPIO_DDRA_P3 *((volatile unsigned int*)(0x4266450CUL)) -#define bFM3_GPIO_DDRA_P4 *((volatile unsigned int*)(0x42664510UL)) -#define bFM3_GPIO_DDRA_P5 *((volatile unsigned int*)(0x42664514UL)) -#define bFM3_GPIO_DDRC_P0 *((volatile unsigned int*)(0x42664600UL)) -#define bFM3_GPIO_DDRC_P1 *((volatile unsigned int*)(0x42664604UL)) -#define bFM3_GPIO_DDRC_P2 *((volatile unsigned int*)(0x42664608UL)) -#define bFM3_GPIO_DDRC_P3 *((volatile unsigned int*)(0x4266460CUL)) -#define bFM3_GPIO_DDRC_P4 *((volatile unsigned int*)(0x42664610UL)) -#define bFM3_GPIO_DDRC_P5 *((volatile unsigned int*)(0x42664614UL)) -#define bFM3_GPIO_DDRC_P6 *((volatile unsigned int*)(0x42664618UL)) -#define bFM3_GPIO_DDRC_P7 *((volatile unsigned int*)(0x4266461CUL)) -#define bFM3_GPIO_DDRC_P8 *((volatile unsigned int*)(0x42664620UL)) -#define bFM3_GPIO_DDRC_P9 *((volatile unsigned int*)(0x42664624UL)) -#define bFM3_GPIO_DDRC_PA *((volatile unsigned int*)(0x42664628UL)) -#define bFM3_GPIO_DDRC_PB *((volatile unsigned int*)(0x4266462CUL)) -#define bFM3_GPIO_DDRC_PC *((volatile unsigned int*)(0x42664630UL)) -#define bFM3_GPIO_DDRC_PD *((volatile unsigned int*)(0x42664634UL)) -#define bFM3_GPIO_DDRC_PE *((volatile unsigned int*)(0x42664638UL)) -#define bFM3_GPIO_DDRC_PF *((volatile unsigned int*)(0x4266463CUL)) -#define bFM3_GPIO_DDRD_P0 *((volatile unsigned int*)(0x42664680UL)) -#define bFM3_GPIO_DDRD_P1 *((volatile unsigned int*)(0x42664684UL)) -#define bFM3_GPIO_DDRD_P2 *((volatile unsigned int*)(0x42664688UL)) -#define bFM3_GPIO_DDRD_P3 *((volatile unsigned int*)(0x4266468CUL)) -#define bFM3_GPIO_DDRE_P0 *((volatile unsigned int*)(0x42664700UL)) -#define bFM3_GPIO_DDRE_P2 *((volatile unsigned int*)(0x42664708UL)) -#define bFM3_GPIO_DDRE_P3 *((volatile unsigned int*)(0x4266470CUL)) -#define bFM3_GPIO_DDRF_P5 *((volatile unsigned int*)(0x42664794UL)) -#define bFM3_GPIO_DDRF_P6 *((volatile unsigned int*)(0x42664798UL)) -#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) -#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) -#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) -#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) -#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) -#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) -#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) -#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) -#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) -#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) -#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) -#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) -#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) -#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) -#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) -#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) -#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) -#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) -#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) -#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) -#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) -#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) -#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) -#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) -#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) -#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) -#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) -#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) -#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) -#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) -#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) -#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) -#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) -#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) -#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) -#define bFM3_GPIO_PDIR2_P9 *((volatile unsigned int*)(0x42666124UL)) -#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) -#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) -#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) -#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) -#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) -#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) -#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) -#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) -#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) -#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) -#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) -#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) -#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) -#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) -#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) -#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) -#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) -#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) -#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) -#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) -#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) -#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) -#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) -#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) -#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) -#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) -#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) -#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) -#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) -#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) -#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) -#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) -#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) -#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) -#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) -#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) -#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) -#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) -#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) -#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) -#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) -#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) -#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) -#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) -#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) -#define bFM3_GPIO_PDIR7_P5 *((volatile unsigned int*)(0x42666394UL)) -#define bFM3_GPIO_PDIR7_P6 *((volatile unsigned int*)(0x42666398UL)) -#define bFM3_GPIO_PDIR7_P7 *((volatile unsigned int*)(0x4266639CUL)) -#define bFM3_GPIO_PDIR7_P8 *((volatile unsigned int*)(0x426663A0UL)) -#define bFM3_GPIO_PDIR7_P9 *((volatile unsigned int*)(0x426663A4UL)) -#define bFM3_GPIO_PDIR7_PA *((volatile unsigned int*)(0x426663A8UL)) -#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) -#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) -#define bFM3_GPIO_PDIR8_P2 *((volatile unsigned int*)(0x42666408UL)) -#define bFM3_GPIO_PDIR8_P3 *((volatile unsigned int*)(0x4266640CUL)) -#define bFM3_GPIO_PDIRA_P0 *((volatile unsigned int*)(0x42666500UL)) -#define bFM3_GPIO_PDIRA_P1 *((volatile unsigned int*)(0x42666504UL)) -#define bFM3_GPIO_PDIRA_P2 *((volatile unsigned int*)(0x42666508UL)) -#define bFM3_GPIO_PDIRA_P3 *((volatile unsigned int*)(0x4266650CUL)) -#define bFM3_GPIO_PDIRA_P4 *((volatile unsigned int*)(0x42666510UL)) -#define bFM3_GPIO_PDIRA_P5 *((volatile unsigned int*)(0x42666514UL)) -#define bFM3_GPIO_PDIRC_P0 *((volatile unsigned int*)(0x42666600UL)) -#define bFM3_GPIO_PDIRC_P1 *((volatile unsigned int*)(0x42666604UL)) -#define bFM3_GPIO_PDIRC_P2 *((volatile unsigned int*)(0x42666608UL)) -#define bFM3_GPIO_PDIRC_P3 *((volatile unsigned int*)(0x4266660CUL)) -#define bFM3_GPIO_PDIRC_P4 *((volatile unsigned int*)(0x42666610UL)) -#define bFM3_GPIO_PDIRC_P5 *((volatile unsigned int*)(0x42666614UL)) -#define bFM3_GPIO_PDIRC_P6 *((volatile unsigned int*)(0x42666618UL)) -#define bFM3_GPIO_PDIRC_P7 *((volatile unsigned int*)(0x4266661CUL)) -#define bFM3_GPIO_PDIRC_P8 *((volatile unsigned int*)(0x42666620UL)) -#define bFM3_GPIO_PDIRC_P9 *((volatile unsigned int*)(0x42666624UL)) -#define bFM3_GPIO_PDIRC_PA *((volatile unsigned int*)(0x42666628UL)) -#define bFM3_GPIO_PDIRC_PB *((volatile unsigned int*)(0x4266662CUL)) -#define bFM3_GPIO_PDIRC_PC *((volatile unsigned int*)(0x42666630UL)) -#define bFM3_GPIO_PDIRC_PD *((volatile unsigned int*)(0x42666634UL)) -#define bFM3_GPIO_PDIRC_PE *((volatile unsigned int*)(0x42666638UL)) -#define bFM3_GPIO_PDIRC_PF *((volatile unsigned int*)(0x4266663CUL)) -#define bFM3_GPIO_PDIRD_P0 *((volatile unsigned int*)(0x42666680UL)) -#define bFM3_GPIO_PDIRD_P1 *((volatile unsigned int*)(0x42666684UL)) -#define bFM3_GPIO_PDIRD_P2 *((volatile unsigned int*)(0x42666688UL)) -#define bFM3_GPIO_PDIRD_P3 *((volatile unsigned int*)(0x4266668CUL)) -#define bFM3_GPIO_PDIRE_P0 *((volatile unsigned int*)(0x42666700UL)) -#define bFM3_GPIO_PDIRE_P2 *((volatile unsigned int*)(0x42666708UL)) -#define bFM3_GPIO_PDIRE_P3 *((volatile unsigned int*)(0x4266670CUL)) -#define bFM3_GPIO_PDIRF_P5 *((volatile unsigned int*)(0x42666794UL)) -#define bFM3_GPIO_PDIRF_P6 *((volatile unsigned int*)(0x42666798UL)) -#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) -#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) -#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) -#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) -#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) -#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) -#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) -#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) -#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) -#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) -#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) -#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) -#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) -#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) -#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) -#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) -#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) -#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) -#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) -#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) -#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) -#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) -#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) -#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) -#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) -#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) -#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) -#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) -#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) -#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) -#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) -#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) -#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) -#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) -#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) -#define bFM3_GPIO_PDOR2_P9 *((volatile unsigned int*)(0x42668124UL)) -#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) -#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) -#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) -#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) -#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) -#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) -#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) -#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) -#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) -#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) -#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) -#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) -#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) -#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) -#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) -#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) -#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) -#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) -#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) -#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) -#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) -#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) -#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) -#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) -#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) -#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) -#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) -#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) -#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) -#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) -#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) -#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) -#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) -#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) -#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) -#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) -#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) -#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) -#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) -#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) -#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) -#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) -#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) -#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) -#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) -#define bFM3_GPIO_PDOR7_P5 *((volatile unsigned int*)(0x42668394UL)) -#define bFM3_GPIO_PDOR7_P6 *((volatile unsigned int*)(0x42668398UL)) -#define bFM3_GPIO_PDOR7_P7 *((volatile unsigned int*)(0x4266839CUL)) -#define bFM3_GPIO_PDOR7_P8 *((volatile unsigned int*)(0x426683A0UL)) -#define bFM3_GPIO_PDOR7_P9 *((volatile unsigned int*)(0x426683A4UL)) -#define bFM3_GPIO_PDOR7_PA *((volatile unsigned int*)(0x426683A8UL)) -#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) -#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) -#define bFM3_GPIO_PDOR8_P2 *((volatile unsigned int*)(0x42668408UL)) -#define bFM3_GPIO_PDOR8_P3 *((volatile unsigned int*)(0x4266840CUL)) -#define bFM3_GPIO_PDORA_P0 *((volatile unsigned int*)(0x42668500UL)) -#define bFM3_GPIO_PDORA_P1 *((volatile unsigned int*)(0x42668504UL)) -#define bFM3_GPIO_PDORA_P2 *((volatile unsigned int*)(0x42668508UL)) -#define bFM3_GPIO_PDORA_P3 *((volatile unsigned int*)(0x4266850CUL)) -#define bFM3_GPIO_PDORA_P4 *((volatile unsigned int*)(0x42668510UL)) -#define bFM3_GPIO_PDORA_P5 *((volatile unsigned int*)(0x42668514UL)) -#define bFM3_GPIO_PDORC_P0 *((volatile unsigned int*)(0x42668600UL)) -#define bFM3_GPIO_PDORC_P1 *((volatile unsigned int*)(0x42668604UL)) -#define bFM3_GPIO_PDORC_P2 *((volatile unsigned int*)(0x42668608UL)) -#define bFM3_GPIO_PDORC_P3 *((volatile unsigned int*)(0x4266860CUL)) -#define bFM3_GPIO_PDORC_P4 *((volatile unsigned int*)(0x42668610UL)) -#define bFM3_GPIO_PDORC_P5 *((volatile unsigned int*)(0x42668614UL)) -#define bFM3_GPIO_PDORC_P6 *((volatile unsigned int*)(0x42668618UL)) -#define bFM3_GPIO_PDORC_P7 *((volatile unsigned int*)(0x4266861CUL)) -#define bFM3_GPIO_PDORC_P8 *((volatile unsigned int*)(0x42668620UL)) -#define bFM3_GPIO_PDORC_P9 *((volatile unsigned int*)(0x42668624UL)) -#define bFM3_GPIO_PDORC_PA *((volatile unsigned int*)(0x42668628UL)) -#define bFM3_GPIO_PDORC_PB *((volatile unsigned int*)(0x4266862CUL)) -#define bFM3_GPIO_PDORC_PC *((volatile unsigned int*)(0x42668630UL)) -#define bFM3_GPIO_PDORC_PD *((volatile unsigned int*)(0x42668634UL)) -#define bFM3_GPIO_PDORC_PE *((volatile unsigned int*)(0x42668638UL)) -#define bFM3_GPIO_PDORC_PF *((volatile unsigned int*)(0x4266863CUL)) -#define bFM3_GPIO_PDORD_P0 *((volatile unsigned int*)(0x42668680UL)) -#define bFM3_GPIO_PDORD_P1 *((volatile unsigned int*)(0x42668684UL)) -#define bFM3_GPIO_PDORD_P2 *((volatile unsigned int*)(0x42668688UL)) -#define bFM3_GPIO_PDORD_P3 *((volatile unsigned int*)(0x4266868CUL)) -#define bFM3_GPIO_PDORE_P0 *((volatile unsigned int*)(0x42668700UL)) -#define bFM3_GPIO_PDORE_P2 *((volatile unsigned int*)(0x42668708UL)) -#define bFM3_GPIO_PDORE_P3 *((volatile unsigned int*)(0x4266870CUL)) -#define bFM3_GPIO_PDORF_P5 *((volatile unsigned int*)(0x42668794UL)) -#define bFM3_GPIO_PDORF_P6 *((volatile unsigned int*)(0x42668798UL)) -#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) -#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) -#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) -#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) -#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) -#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) -#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) -#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) -#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) -#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) -#define bFM3_GPIO_ADE_AN10 *((volatile unsigned int*)(0x4266A028UL)) -#define bFM3_GPIO_ADE_AN11 *((volatile unsigned int*)(0x4266A02CUL)) -#define bFM3_GPIO_ADE_AN12 *((volatile unsigned int*)(0x4266A030UL)) -#define bFM3_GPIO_ADE_AN13 *((volatile unsigned int*)(0x4266A034UL)) -#define bFM3_GPIO_ADE_AN14 *((volatile unsigned int*)(0x4266A038UL)) -#define bFM3_GPIO_ADE_AN15 *((volatile unsigned int*)(0x4266A03CUL)) -#define bFM3_GPIO_ADE_AN24 *((volatile unsigned int*)(0x4266A060UL)) -#define bFM3_GPIO_ADE_AN25 *((volatile unsigned int*)(0x4266A064UL)) -#define bFM3_GPIO_ADE_AN26 *((volatile unsigned int*)(0x4266A068UL)) -#define bFM3_GPIO_ADE_AN27 *((volatile unsigned int*)(0x4266A06CUL)) -#define bFM3_GPIO_ADE_AN28 *((volatile unsigned int*)(0x4266A070UL)) -#define bFM3_GPIO_ADE_AN29 *((volatile unsigned int*)(0x4266A074UL)) -#define bFM3_GPIO_ADE_AN30 *((volatile unsigned int*)(0x4266A078UL)) -#define bFM3_GPIO_ADE_AN31 *((volatile unsigned int*)(0x4266A07CUL)) -#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) -#define bFM3_GPIO_SPSR_MAINXC *((volatile unsigned int*)(0x4266B008UL)) -#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) -#define bFM3_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x4266B014UL)) -#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) -#define bFM3_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x4266C004UL)) -#define bFM3_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x4266C008UL)) -#define bFM3_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x4266C018UL)) -#define bFM3_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x4266C01CUL)) -#define bFM3_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x4266C024UL)) -#define bFM3_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x4266C034UL)) -#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) -#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) -#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) -#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) -#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) -#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) -#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) -#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) -#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) -#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) -#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) -#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) -#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) -#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) -#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) -#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) -#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) -#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) -#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) -#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) -#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) -#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) -#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) -#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) -#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) -#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) -#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) -#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) -#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) -#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) -#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) -#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) -#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) -#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) -#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) -#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) -#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) -#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) -#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) -#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) -#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) -#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) -#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) -#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) -#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) -#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) -#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) -#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) -#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) -#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) -#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) -#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) -#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) -#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) -#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) -#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) -#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) -#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) -#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) -#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) -#define bFM3_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x4266C180UL)) -#define bFM3_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x4266C184UL)) -#define bFM3_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x4266C188UL)) -#define bFM3_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x4266C18CUL)) -#define bFM3_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x4266C190UL)) -#define bFM3_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x4266C194UL)) -#define bFM3_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x4266C198UL)) -#define bFM3_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x4266C19CUL)) -#define bFM3_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x4266C1A0UL)) -#define bFM3_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x4266C1A4UL)) -#define bFM3_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x4266C1A8UL)) -#define bFM3_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x4266C1ACUL)) -#define bFM3_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x4266C1B0UL)) -#define bFM3_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x4266C1C0UL)) -#define bFM3_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x4266C1C4UL)) -#define bFM3_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x4266C1C8UL)) -#define bFM3_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x4266C1CCUL)) -#define bFM3_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x4266C1D0UL)) -#define bFM3_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x4266C1D4UL)) -#define bFM3_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x4266C1D8UL)) -#define bFM3_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x4266C1DCUL)) -#define bFM3_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x4266C1E0UL)) -#define bFM3_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x4266C1E4UL)) -#define bFM3_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x4266C1E8UL)) -#define bFM3_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x4266C1ECUL)) -#define bFM3_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x4266C1F0UL)) -#define bFM3_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x4266C1F4UL)) -#define bFM3_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x4266C1F8UL)) -#define bFM3_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x4266C1FCUL)) -#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) -#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) -#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) -#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) -#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) -#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) -#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) -#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) -#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) -#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) -#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) -#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) -#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) -#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) -#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) -#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) -#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) -#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) -#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) -#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) -#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) -#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) -#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) -#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) -#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) -#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) -#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) -#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) -#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) -#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) -#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) -#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) -#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) -#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) -#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) -#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) -#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) -#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) -#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) -#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) -#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) -#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) -#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) -#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) -#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) -#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) -#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) -#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) -#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) -#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) -#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) -#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) -#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) -#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) -#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) -#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) -#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) -#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) -#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) -#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) -#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) -#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) -#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) -#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) -#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) -#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) -#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) -#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) -#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) -#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) -#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) -#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) -#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) -#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) -#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) -#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) -#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) -#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) -#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) -#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) -#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) -#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) -#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) -#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) -#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) -#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) -#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) -#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) -#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) -#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) -#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) -#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) -#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) -#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) -#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) -#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) -#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) -#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) -#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) -#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) -#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) -#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) -#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) -#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) -#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) -#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) -#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) -#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) -#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) -#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) -#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) -#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) -#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) -#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) -#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) -#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) -#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) -#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) -#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) -#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) -#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) -#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) -#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) -#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) -#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) -#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) -#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) -#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) -#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) -#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) -#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) -#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) -#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) -#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) -#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) -#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) -#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) -#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) -#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) -#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) -#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) -#define bFM3_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x4266C508UL)) -#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) -#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) -#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) -#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) -#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) -#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) -#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) -#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) -#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) -#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) -#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) -#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) -#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) -#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) -#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) -#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) -#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) -#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) -#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) -#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) -#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) -#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) -#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) -#define bFM3_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x4266C580UL)) -#define bFM3_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x4266C584UL)) -#define bFM3_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x4266C588UL)) -#define bFM3_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x4266C58CUL)) -#define bFM3_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x4266C590UL)) -#define bFM3_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x4266C594UL)) -#define bFM3_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x4266C598UL)) -#define bFM3_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x4266C59CUL)) -#define bFM3_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x4266C5A0UL)) -#define bFM3_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x4266C5A4UL)) -#define bFM3_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x4266C5A8UL)) -#define bFM3_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x4266C5ACUL)) -#define bFM3_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x4266C5B0UL)) -#define bFM3_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x4266C5B4UL)) -#define bFM3_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x4266C5B8UL)) -#define bFM3_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x4266C5BCUL)) -#define bFM3_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x4266C5C0UL)) -#define bFM3_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x4266C5C4UL)) -#define bFM3_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x4266C5C8UL)) -#define bFM3_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x4266C5CCUL)) -#define bFM3_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x4266C5D0UL)) -#define bFM3_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x4266C5D4UL)) -#define bFM3_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x4266C5D8UL)) -#define bFM3_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x4266C5DCUL)) -#define bFM3_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x4266C5E0UL)) -#define bFM3_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x4266C5E4UL)) -#define bFM3_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x4266C608UL)) -#define bFM3_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x4266C60CUL)) -#define bFM3_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x4266C610UL)) -#define bFM3_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x4266C614UL)) -#define bFM3_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x4266C620UL)) -#define bFM3_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x4266C624UL)) -#define bFM3_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x4266C628UL)) -#define bFM3_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x4266C62CUL)) -#define bFM3_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x4266C630UL)) -#define bFM3_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x4266C634UL)) -#define bFM3_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x4266C648UL)) -#define bFM3_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x4266C64CUL)) -#define bFM3_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x4266C650UL)) -#define bFM3_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x4266C654UL)) -#define bFM3_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x4266C660UL)) -#define bFM3_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x4266C664UL)) -#define bFM3_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x4266C668UL)) -#define bFM3_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x4266C66CUL)) -#define bFM3_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x4266C670UL)) -#define bFM3_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x4266C674UL)) -#define bFM3_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x4266C688UL)) -#define bFM3_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x4266C68CUL)) -#define bFM3_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x4266C690UL)) -#define bFM3_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x4266C694UL)) -#define bFM3_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x4266C6A0UL)) -#define bFM3_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x4266C6A4UL)) -#define bFM3_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x4266C6A8UL)) -#define bFM3_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x4266C6ACUL)) -#define bFM3_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x4266C6B0UL)) -#define bFM3_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x4266C6B4UL)) -#define bFM3_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x4266C6C8UL)) -#define bFM3_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x4266C6CCUL)) -#define bFM3_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x4266C6D0UL)) -#define bFM3_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x4266C6D4UL)) -#define bFM3_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x4266C6E0UL)) -#define bFM3_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x4266C6E4UL)) -#define bFM3_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x4266C6E8UL)) -#define bFM3_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x4266C6ECUL)) -#define bFM3_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x4266C6F0UL)) -#define bFM3_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x4266C6F4UL)) -#define bFM3_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x4266C700UL)) -#define bFM3_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x4266C704UL)) -#define bFM3_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x4266C708UL)) -#define bFM3_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x4266C70CUL)) -#define bFM3_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x4266C710UL)) -#define bFM3_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x4266C714UL)) -#define bFM3_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x4266C748UL)) -#define bFM3_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x4266C74CUL)) -#define bFM3_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x4266C750UL)) -#define bFM3_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x4266C754UL)) -#define bFM3_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x4266C758UL)) -#define bFM3_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x4266C75CUL)) -#define bFM3_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x4266C760UL)) -#define bFM3_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x4266C764UL)) -#define bFM3_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x4266C768UL)) -#define bFM3_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x4266C76CUL)) -#define bFM3_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x4266C770UL)) -#define bFM3_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x4266C774UL)) -#define bFM3_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x4266C780UL)) -#define bFM3_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x4266C784UL)) -#define bFM3_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x4266C788UL)) -#define bFM3_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x4266C78CUL)) -#define bFM3_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x4266C790UL)) -#define bFM3_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x4266C794UL)) -#define bFM3_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x4266C798UL)) -#define bFM3_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x4266C79CUL)) -#define bFM3_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x4266C7A0UL)) -#define bFM3_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x4266C7A4UL)) -#define bFM3_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x4266C7A8UL)) -#define bFM3_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x4266C7ACUL)) -#define bFM3_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x4266C7B0UL)) -#define bFM3_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x4266C7B4UL)) -#define bFM3_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x4266C7B8UL)) -#define bFM3_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x4266C7BCUL)) -#define bFM3_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x4266C7C0UL)) -#define bFM3_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x4266C7C4UL)) -#define bFM3_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x4266C7C8UL)) -#define bFM3_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x4266C7CCUL)) -#define bFM3_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x4266C7D0UL)) -#define bFM3_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x4266C7D4UL)) -#define bFM3_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x4266C7D8UL)) -#define bFM3_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x4266C7DCUL)) -#define bFM3_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x4266C7E0UL)) -#define bFM3_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x4266C7E4UL)) -#define bFM3_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x4266C7E8UL)) -#define bFM3_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x4266C7ECUL)) -#define bFM3_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x4266C7F0UL)) -#define bFM3_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x4266C7F4UL)) -#define bFM3_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x4266C7F8UL)) -#define bFM3_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x4266C7FCUL)) -#define bFM3_GPIO_PZR0_P0 *((volatile unsigned int*)(0x4266E000UL)) -#define bFM3_GPIO_PZR0_P1 *((volatile unsigned int*)(0x4266E004UL)) -#define bFM3_GPIO_PZR0_P2 *((volatile unsigned int*)(0x4266E008UL)) -#define bFM3_GPIO_PZR0_P3 *((volatile unsigned int*)(0x4266E00CUL)) -#define bFM3_GPIO_PZR0_P4 *((volatile unsigned int*)(0x4266E010UL)) -#define bFM3_GPIO_PZR0_P5 *((volatile unsigned int*)(0x4266E014UL)) -#define bFM3_GPIO_PZR0_P6 *((volatile unsigned int*)(0x4266E018UL)) -#define bFM3_GPIO_PZR0_P7 *((volatile unsigned int*)(0x4266E01CUL)) -#define bFM3_GPIO_PZR0_P8 *((volatile unsigned int*)(0x4266E020UL)) -#define bFM3_GPIO_PZR0_P9 *((volatile unsigned int*)(0x4266E024UL)) -#define bFM3_GPIO_PZR1_P0 *((volatile unsigned int*)(0x4266E080UL)) -#define bFM3_GPIO_PZR1_P1 *((volatile unsigned int*)(0x4266E084UL)) -#define bFM3_GPIO_PZR1_P2 *((volatile unsigned int*)(0x4266E088UL)) -#define bFM3_GPIO_PZR1_P3 *((volatile unsigned int*)(0x4266E08CUL)) -#define bFM3_GPIO_PZR1_P4 *((volatile unsigned int*)(0x4266E090UL)) -#define bFM3_GPIO_PZR1_P5 *((volatile unsigned int*)(0x4266E094UL)) -#define bFM3_GPIO_PZR1_P6 *((volatile unsigned int*)(0x4266E098UL)) -#define bFM3_GPIO_PZR1_P7 *((volatile unsigned int*)(0x4266E09CUL)) -#define bFM3_GPIO_PZR1_P8 *((volatile unsigned int*)(0x4266E0A0UL)) -#define bFM3_GPIO_PZR1_P9 *((volatile unsigned int*)(0x4266E0A4UL)) -#define bFM3_GPIO_PZR1_PA *((volatile unsigned int*)(0x4266E0A8UL)) -#define bFM3_GPIO_PZR1_PB *((volatile unsigned int*)(0x4266E0ACUL)) -#define bFM3_GPIO_PZR1_PC *((volatile unsigned int*)(0x4266E0B0UL)) -#define bFM3_GPIO_PZR1_PD *((volatile unsigned int*)(0x4266E0B4UL)) -#define bFM3_GPIO_PZR1_PE *((volatile unsigned int*)(0x4266E0B8UL)) -#define bFM3_GPIO_PZR1_PF *((volatile unsigned int*)(0x4266E0BCUL)) -#define bFM3_GPIO_PZR2_P0 *((volatile unsigned int*)(0x4266E100UL)) -#define bFM3_GPIO_PZR2_P1 *((volatile unsigned int*)(0x4266E104UL)) -#define bFM3_GPIO_PZR2_P2 *((volatile unsigned int*)(0x4266E108UL)) -#define bFM3_GPIO_PZR2_P3 *((volatile unsigned int*)(0x4266E10CUL)) -#define bFM3_GPIO_PZR2_P4 *((volatile unsigned int*)(0x4266E110UL)) -#define bFM3_GPIO_PZR2_P5 *((volatile unsigned int*)(0x4266E114UL)) -#define bFM3_GPIO_PZR2_P6 *((volatile unsigned int*)(0x4266E118UL)) -#define bFM3_GPIO_PZR2_P7 *((volatile unsigned int*)(0x4266E11CUL)) -#define bFM3_GPIO_PZR2_P8 *((volatile unsigned int*)(0x4266E120UL)) -#define bFM3_GPIO_PZR2_P9 *((volatile unsigned int*)(0x4266E124UL)) -#define bFM3_GPIO_PZR3_P6 *((volatile unsigned int*)(0x4266E198UL)) -#define bFM3_GPIO_PZR3_P7 *((volatile unsigned int*)(0x4266E19CUL)) -#define bFM3_GPIO_PZR3_P8 *((volatile unsigned int*)(0x4266E1A0UL)) -#define bFM3_GPIO_PZR3_P9 *((volatile unsigned int*)(0x4266E1A4UL)) -#define bFM3_GPIO_PZR3_PA *((volatile unsigned int*)(0x4266E1A8UL)) -#define bFM3_GPIO_PZR3_PB *((volatile unsigned int*)(0x4266E1ACUL)) -#define bFM3_GPIO_PZR3_PC *((volatile unsigned int*)(0x4266E1B0UL)) -#define bFM3_GPIO_PZR3_PD *((volatile unsigned int*)(0x4266E1B4UL)) -#define bFM3_GPIO_PZR3_PE *((volatile unsigned int*)(0x4266E1B8UL)) -#define bFM3_GPIO_PZR3_PF *((volatile unsigned int*)(0x4266E1BCUL)) -#define bFM3_GPIO_PZR4_P0 *((volatile unsigned int*)(0x4266E200UL)) -#define bFM3_GPIO_PZR4_P1 *((volatile unsigned int*)(0x4266E204UL)) -#define bFM3_GPIO_PZR4_P2 *((volatile unsigned int*)(0x4266E208UL)) -#define bFM3_GPIO_PZR4_P3 *((volatile unsigned int*)(0x4266E20CUL)) -#define bFM3_GPIO_PZR4_P4 *((volatile unsigned int*)(0x4266E210UL)) -#define bFM3_GPIO_PZR4_P5 *((volatile unsigned int*)(0x4266E214UL)) -#define bFM3_GPIO_PZR4_P6 *((volatile unsigned int*)(0x4266E218UL)) -#define bFM3_GPIO_PZR4_P7 *((volatile unsigned int*)(0x4266E21CUL)) -#define bFM3_GPIO_PZR4_P8 *((volatile unsigned int*)(0x4266E220UL)) -#define bFM3_GPIO_PZR4_P9 *((volatile unsigned int*)(0x4266E224UL)) -#define bFM3_GPIO_PZR4_PA *((volatile unsigned int*)(0x4266E228UL)) -#define bFM3_GPIO_PZR4_PB *((volatile unsigned int*)(0x4266E22CUL)) -#define bFM3_GPIO_PZR4_PC *((volatile unsigned int*)(0x4266E230UL)) -#define bFM3_GPIO_PZR4_PD *((volatile unsigned int*)(0x4266E234UL)) -#define bFM3_GPIO_PZR4_PE *((volatile unsigned int*)(0x4266E238UL)) -#define bFM3_GPIO_PZR5_P0 *((volatile unsigned int*)(0x4266E280UL)) -#define bFM3_GPIO_PZR5_P1 *((volatile unsigned int*)(0x4266E284UL)) -#define bFM3_GPIO_PZR5_P2 *((volatile unsigned int*)(0x4266E288UL)) -#define bFM3_GPIO_PZR5_P3 *((volatile unsigned int*)(0x4266E28CUL)) -#define bFM3_GPIO_PZR5_P4 *((volatile unsigned int*)(0x4266E290UL)) -#define bFM3_GPIO_PZR5_P5 *((volatile unsigned int*)(0x4266E294UL)) -#define bFM3_GPIO_PZR5_P6 *((volatile unsigned int*)(0x4266E298UL)) -#define bFM3_GPIO_PZR5_P7 *((volatile unsigned int*)(0x4266E29CUL)) -#define bFM3_GPIO_PZR5_P8 *((volatile unsigned int*)(0x4266E2A0UL)) -#define bFM3_GPIO_PZR5_P9 *((volatile unsigned int*)(0x4266E2A4UL)) -#define bFM3_GPIO_PZR5_PA *((volatile unsigned int*)(0x4266E2A8UL)) -#define bFM3_GPIO_PZR5_PB *((volatile unsigned int*)(0x4266E2ACUL)) -#define bFM3_GPIO_PZR6_P0 *((volatile unsigned int*)(0x4266E300UL)) -#define bFM3_GPIO_PZR6_P1 *((volatile unsigned int*)(0x4266E304UL)) -#define bFM3_GPIO_PZR6_P2 *((volatile unsigned int*)(0x4266E308UL)) -#define bFM3_GPIO_PZR7_P0 *((volatile unsigned int*)(0x4266E380UL)) -#define bFM3_GPIO_PZR7_P1 *((volatile unsigned int*)(0x4266E384UL)) -#define bFM3_GPIO_PZR7_P2 *((volatile unsigned int*)(0x4266E388UL)) -#define bFM3_GPIO_PZR7_P3 *((volatile unsigned int*)(0x4266E38CUL)) -#define bFM3_GPIO_PZR7_P4 *((volatile unsigned int*)(0x4266E390UL)) -#define bFM3_GPIO_PZR7_P5 *((volatile unsigned int*)(0x4266E394UL)) -#define bFM3_GPIO_PZR7_P6 *((volatile unsigned int*)(0x4266E398UL)) -#define bFM3_GPIO_PZR7_P7 *((volatile unsigned int*)(0x4266E39CUL)) -#define bFM3_GPIO_PZR7_P8 *((volatile unsigned int*)(0x4266E3A0UL)) -#define bFM3_GPIO_PZR7_P9 *((volatile unsigned int*)(0x4266E3A4UL)) -#define bFM3_GPIO_PZR7_PA *((volatile unsigned int*)(0x4266E3A8UL)) -#define bFM3_GPIO_PZR8_P0 *((volatile unsigned int*)(0x4266E400UL)) -#define bFM3_GPIO_PZR8_P1 *((volatile unsigned int*)(0x4266E404UL)) -#define bFM3_GPIO_PZR8_P2 *((volatile unsigned int*)(0x4266E408UL)) -#define bFM3_GPIO_PZR8_P3 *((volatile unsigned int*)(0x4266E40CUL)) -#define bFM3_GPIO_PZRA_P0 *((volatile unsigned int*)(0x4266E500UL)) -#define bFM3_GPIO_PZRA_P1 *((volatile unsigned int*)(0x4266E504UL)) -#define bFM3_GPIO_PZRA_P2 *((volatile unsigned int*)(0x4266E508UL)) -#define bFM3_GPIO_PZRA_P3 *((volatile unsigned int*)(0x4266E50CUL)) -#define bFM3_GPIO_PZRA_P4 *((volatile unsigned int*)(0x4266E510UL)) -#define bFM3_GPIO_PZRA_P5 *((volatile unsigned int*)(0x4266E514UL)) -#define bFM3_GPIO_PZRC_P0 *((volatile unsigned int*)(0x4266E600UL)) -#define bFM3_GPIO_PZRC_P1 *((volatile unsigned int*)(0x4266E604UL)) -#define bFM3_GPIO_PZRC_P2 *((volatile unsigned int*)(0x4266E608UL)) -#define bFM3_GPIO_PZRC_P3 *((volatile unsigned int*)(0x4266E60CUL)) -#define bFM3_GPIO_PZRC_P4 *((volatile unsigned int*)(0x4266E610UL)) -#define bFM3_GPIO_PZRC_P5 *((volatile unsigned int*)(0x4266E614UL)) -#define bFM3_GPIO_PZRC_P6 *((volatile unsigned int*)(0x4266E618UL)) -#define bFM3_GPIO_PZRC_P7 *((volatile unsigned int*)(0x4266E61CUL)) -#define bFM3_GPIO_PZRC_P8 *((volatile unsigned int*)(0x4266E620UL)) -#define bFM3_GPIO_PZRC_P9 *((volatile unsigned int*)(0x4266E624UL)) -#define bFM3_GPIO_PZRC_PA *((volatile unsigned int*)(0x4266E628UL)) -#define bFM3_GPIO_PZRC_PB *((volatile unsigned int*)(0x4266E62CUL)) -#define bFM3_GPIO_PZRC_PC *((volatile unsigned int*)(0x4266E630UL)) -#define bFM3_GPIO_PZRC_PD *((volatile unsigned int*)(0x4266E634UL)) -#define bFM3_GPIO_PZRC_PE *((volatile unsigned int*)(0x4266E638UL)) -#define bFM3_GPIO_PZRC_PF *((volatile unsigned int*)(0x4266E63CUL)) -#define bFM3_GPIO_PZRD_P0 *((volatile unsigned int*)(0x4266E680UL)) -#define bFM3_GPIO_PZRD_P1 *((volatile unsigned int*)(0x4266E684UL)) -#define bFM3_GPIO_PZRD_P2 *((volatile unsigned int*)(0x4266E688UL)) -#define bFM3_GPIO_PZRD_P3 *((volatile unsigned int*)(0x4266E68CUL)) -#define bFM3_GPIO_PZRE_P0 *((volatile unsigned int*)(0x4266E700UL)) -#define bFM3_GPIO_PZRE_P2 *((volatile unsigned int*)(0x4266E708UL)) -#define bFM3_GPIO_PZRE_P3 *((volatile unsigned int*)(0x4266E70CUL)) -#define bFM3_GPIO_PZRF_P5 *((volatile unsigned int*)(0x4266E794UL)) -#define bFM3_GPIO_PZRF_P6 *((volatile unsigned int*)(0x4266E798UL)) - -/* Low voltage detection registers */ -#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* USB clock registers */ -#define bFM3_USBETHERNETCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) -#define bFM3_USBETHERNETCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) -#define bFM3_USBETHERNETCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) -#define bFM3_USBETHERNETCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) -#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM3_USBETHERNETCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) -#define bFM3_USBETHERNETCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) -#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) -#define bFM3_USBETHERNETCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) -#define bFM3_USBETHERNETCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) - -/* UART asynchronous channel 0 registers */ -#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* UART synchronous channel 0 registers */ -#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) - -/* UART LIN channel 0 registers */ -#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* I2C channel 0 registers */ -#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) - -/* UART asynchronous channel 1 registers */ -#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* UART synchronous channel 1 registers */ -#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) - -/* UART LIN channel 1 registers */ -#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* I2C channel 1 registers */ -#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) - -/* UART asynchronous channel 2 registers */ -#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* UART synchronous channel 2 registers */ -#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) - -/* UART LIN channel 2 registers */ -#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* I2C channel 2 registers */ -#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) - -/* UART asynchronous channel 3 registers */ -#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* UART synchronous channel 3 registers */ -#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) - -/* UART LIN channel 3 registers */ -#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* I2C channel 3 registers */ -#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) - -/* UART asynchronous channel 4 registers */ -#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART synchronous channel 4 registers */ -#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART LIN channel 4 registers */ -#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* I2C channel 4 registers */ -#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART asynchronous channel 5 registers */ -#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART synchronous channel 5 registers */ -#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART LIN channel 5 registers */ -#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* I2C channel 5 registers */ -#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART asynchronous channel 6 registers */ -#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART synchronous channel 6 registers */ -#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART LIN channel 6 registers */ -#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* I2C channel 6 registers */ -#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART asynchronous channel 7 registers */ -#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART synchronous channel 7 registers */ -#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART LIN channel 7 registers */ -#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* I2C channel 7 registers */ -#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* MFS Noise Filter Control registers */ -#define bFM3_MFS_NFC_I2CDNF_I2CDNF00 *((volatile unsigned int*)(0x42710000UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF01 *((volatile unsigned int*)(0x42710004UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF10 *((volatile unsigned int*)(0x42710008UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF11 *((volatile unsigned int*)(0x4271000CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF20 *((volatile unsigned int*)(0x42710010UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF21 *((volatile unsigned int*)(0x42710014UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF30 *((volatile unsigned int*)(0x42710018UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF31 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF40 *((volatile unsigned int*)(0x42710020UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF41 *((volatile unsigned int*)(0x42710024UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF50 *((volatile unsigned int*)(0x42710028UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF51 *((volatile unsigned int*)(0x4271002CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF60 *((volatile unsigned int*)(0x42710030UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF61 *((volatile unsigned int*)(0x42710034UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF70 *((volatile unsigned int*)(0x42710038UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF71 *((volatile unsigned int*)(0x4271003CUL)) - -/* CRC registers */ -#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* External bus interface registers */ -#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM3_EXBUS_MODE0_RDY *((volatile unsigned int*)(0x427E0018UL)) -#define bFM3_EXBUS_MODE0_SHRTDOUT *((volatile unsigned int*)(0x427E001CUL)) -#define bFM3_EXBUS_MODE0_MPXMODE *((volatile unsigned int*)(0x427E0020UL)) -#define bFM3_EXBUS_MODE0_ALEINV *((volatile unsigned int*)(0x427E0024UL)) -#define bFM3_EXBUS_MODE0_MPXDOFF *((volatile unsigned int*)(0x427E002CUL)) -#define bFM3_EXBUS_MODE0_MPXCSOF *((volatile unsigned int*)(0x427E0030UL)) -#define bFM3_EXBUS_MODE0_MOEXEUP *((volatile unsigned int*)(0x427E0034UL)) -#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) -#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM3_EXBUS_MODE1_RDY *((volatile unsigned int*)(0x427E0098UL)) -#define bFM3_EXBUS_MODE1_SHRTDOUT *((volatile unsigned int*)(0x427E009CUL)) -#define bFM3_EXBUS_MODE1_MPXMODE *((volatile unsigned int*)(0x427E00A0UL)) -#define bFM3_EXBUS_MODE1_ALEINV *((volatile unsigned int*)(0x427E00A4UL)) -#define bFM3_EXBUS_MODE1_MPXDOFF *((volatile unsigned int*)(0x427E00ACUL)) -#define bFM3_EXBUS_MODE1_MPXCSOF *((volatile unsigned int*)(0x427E00B0UL)) -#define bFM3_EXBUS_MODE1_MOEXEUP *((volatile unsigned int*)(0x427E00B4UL)) -#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) -#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM3_EXBUS_MODE2_RDY *((volatile unsigned int*)(0x427E0118UL)) -#define bFM3_EXBUS_MODE2_SHRTDOUT *((volatile unsigned int*)(0x427E011CUL)) -#define bFM3_EXBUS_MODE2_MPXMODE *((volatile unsigned int*)(0x427E0120UL)) -#define bFM3_EXBUS_MODE2_ALEINV *((volatile unsigned int*)(0x427E0124UL)) -#define bFM3_EXBUS_MODE2_MPXDOFF *((volatile unsigned int*)(0x427E012CUL)) -#define bFM3_EXBUS_MODE2_MPXCSOF *((volatile unsigned int*)(0x427E0130UL)) -#define bFM3_EXBUS_MODE2_MOEXEUP *((volatile unsigned int*)(0x427E0134UL)) -#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) -#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM3_EXBUS_MODE3_RDY *((volatile unsigned int*)(0x427E0198UL)) -#define bFM3_EXBUS_MODE3_SHRTDOUT *((volatile unsigned int*)(0x427E019CUL)) -#define bFM3_EXBUS_MODE3_MPXMODE *((volatile unsigned int*)(0x427E01A0UL)) -#define bFM3_EXBUS_MODE3_ALEINV *((volatile unsigned int*)(0x427E01A4UL)) -#define bFM3_EXBUS_MODE3_MPXDOFF *((volatile unsigned int*)(0x427E01ACUL)) -#define bFM3_EXBUS_MODE3_MPXCSOF *((volatile unsigned int*)(0x427E01B0UL)) -#define bFM3_EXBUS_MODE3_MOEXEUP *((volatile unsigned int*)(0x427E01B4UL)) -#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) -#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) -#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) -#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) -#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) -#define bFM3_EXBUS_MODE4_RDY *((volatile unsigned int*)(0x427E0218UL)) -#define bFM3_EXBUS_MODE4_SHRTDOUT *((volatile unsigned int*)(0x427E021CUL)) -#define bFM3_EXBUS_MODE4_MPXMODE *((volatile unsigned int*)(0x427E0220UL)) -#define bFM3_EXBUS_MODE4_ALEINV *((volatile unsigned int*)(0x427E0224UL)) -#define bFM3_EXBUS_MODE4_MPXDOFF *((volatile unsigned int*)(0x427E022CUL)) -#define bFM3_EXBUS_MODE4_MPXCSOF *((volatile unsigned int*)(0x427E0230UL)) -#define bFM3_EXBUS_MODE4_MOEXEUP *((volatile unsigned int*)(0x427E0234UL)) -#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) -#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) -#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) -#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) -#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) -#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) -#define bFM3_EXBUS_MODE5_RDY *((volatile unsigned int*)(0x427E0298UL)) -#define bFM3_EXBUS_MODE5_SHRTDOUT *((volatile unsigned int*)(0x427E029CUL)) -#define bFM3_EXBUS_MODE5_MPXMODE *((volatile unsigned int*)(0x427E02A0UL)) -#define bFM3_EXBUS_MODE5_ALEINV *((volatile unsigned int*)(0x427E02A4UL)) -#define bFM3_EXBUS_MODE5_MPXDOFF *((volatile unsigned int*)(0x427E02ACUL)) -#define bFM3_EXBUS_MODE5_MPXCSOF *((volatile unsigned int*)(0x427E02B0UL)) -#define bFM3_EXBUS_MODE5_MOEXEUP *((volatile unsigned int*)(0x427E02B4UL)) -#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) -#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) -#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) -#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) -#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) -#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) -#define bFM3_EXBUS_MODE6_RDY *((volatile unsigned int*)(0x427E0318UL)) -#define bFM3_EXBUS_MODE6_SHRTDOUT *((volatile unsigned int*)(0x427E031CUL)) -#define bFM3_EXBUS_MODE6_MPXMODE *((volatile unsigned int*)(0x427E0320UL)) -#define bFM3_EXBUS_MODE6_ALEINV *((volatile unsigned int*)(0x427E0324UL)) -#define bFM3_EXBUS_MODE6_MPXDOFF *((volatile unsigned int*)(0x427E032CUL)) -#define bFM3_EXBUS_MODE6_MPXCSOF *((volatile unsigned int*)(0x427E0330UL)) -#define bFM3_EXBUS_MODE6_MOEXEUP *((volatile unsigned int*)(0x427E0334UL)) -#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) -#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM3_EXBUS_MODE7_RDY *((volatile unsigned int*)(0x427E0398UL)) -#define bFM3_EXBUS_MODE7_SHRTDOUT *((volatile unsigned int*)(0x427E039CUL)) -#define bFM3_EXBUS_MODE7_MPXMODE *((volatile unsigned int*)(0x427E03A0UL)) -#define bFM3_EXBUS_MODE7_ALEINV *((volatile unsigned int*)(0x427E03A4UL)) -#define bFM3_EXBUS_MODE7_MPXDOFF *((volatile unsigned int*)(0x427E03ACUL)) -#define bFM3_EXBUS_MODE7_MPXCSOF *((volatile unsigned int*)(0x427E03B0UL)) -#define bFM3_EXBUS_MODE7_MOEXEUP *((volatile unsigned int*)(0x427E03B4UL)) -#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) -#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) -#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) -#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) -#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) -#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) -#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) -#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) -#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) -#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) -#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) -#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) -#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) -#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) -#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) -#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) -#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) -#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) -#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) -#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) -#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) -#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) -#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) -#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) -#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) -#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) -#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) -#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) -#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) -#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) -#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) -#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) -#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) -#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) -#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) -#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) -#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) -#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) -#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) -#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) -#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) -#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) -#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) -#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) -#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) -#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) -#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) -#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) -#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) -#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) -#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) -#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) -#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) -#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) -#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) -#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) -#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) -#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) -#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) -#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) -#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) -#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) -#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) -#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) -#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) -#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) -#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) -#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) -#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) -#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) -#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) -#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) -#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) -#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) -#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) -#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) -#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) -#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) -#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) -#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) -#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) -#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) -#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) -#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) -#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) -#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) -#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) -#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) -#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) -#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) -#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) -#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) -#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) -#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) -#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) -#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) -#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) -#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) -#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) -#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) -#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) -#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) -#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) -#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) -#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) -#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) -#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) -#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) -#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) -#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) -#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) -#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) -#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) -#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) -#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) -#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) -#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) -#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) -#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) -#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) -#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) -#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) -#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) -#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) -#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) -#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) -#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) -#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) -#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) -#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) -#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) -#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) -#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) -#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) -#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) -#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) -#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) -#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) -#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) -#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) -#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) -#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) -#define bFM3_EXBUS_ATIM0_ALC0 *((volatile unsigned int*)(0x427E0C00UL)) -#define bFM3_EXBUS_ATIM0_ALC1 *((volatile unsigned int*)(0x427E0C04UL)) -#define bFM3_EXBUS_ATIM0_ALC2 *((volatile unsigned int*)(0x427E0C08UL)) -#define bFM3_EXBUS_ATIM0_ALC3 *((volatile unsigned int*)(0x427E0C0CUL)) -#define bFM3_EXBUS_ATIM0_ALES0 *((volatile unsigned int*)(0x427E0C10UL)) -#define bFM3_EXBUS_ATIM0_ALES1 *((volatile unsigned int*)(0x427E0C14UL)) -#define bFM3_EXBUS_ATIM0_ALES2 *((volatile unsigned int*)(0x427E0C18UL)) -#define bFM3_EXBUS_ATIM0_ALES3 *((volatile unsigned int*)(0x427E0C1CUL)) -#define bFM3_EXBUS_ATIM0_ALEW0 *((volatile unsigned int*)(0x427E0C20UL)) -#define bFM3_EXBUS_ATIM0_ALEW1 *((volatile unsigned int*)(0x427E0C24UL)) -#define bFM3_EXBUS_ATIM0_ALEW2 *((volatile unsigned int*)(0x427E0C28UL)) -#define bFM3_EXBUS_ATIM0_ALEW3 *((volatile unsigned int*)(0x427E0C2CUL)) -#define bFM3_EXBUS_ATIM1_ALC0 *((volatile unsigned int*)(0x427E0C80UL)) -#define bFM3_EXBUS_ATIM1_ALC1 *((volatile unsigned int*)(0x427E0C84UL)) -#define bFM3_EXBUS_ATIM1_ALC2 *((volatile unsigned int*)(0x427E0C88UL)) -#define bFM3_EXBUS_ATIM1_ALC3 *((volatile unsigned int*)(0x427E0C8CUL)) -#define bFM3_EXBUS_ATIM1_ALES0 *((volatile unsigned int*)(0x427E0C90UL)) -#define bFM3_EXBUS_ATIM1_ALES1 *((volatile unsigned int*)(0x427E0C94UL)) -#define bFM3_EXBUS_ATIM1_ALES2 *((volatile unsigned int*)(0x427E0C98UL)) -#define bFM3_EXBUS_ATIM1_ALES3 *((volatile unsigned int*)(0x427E0C9CUL)) -#define bFM3_EXBUS_ATIM1_ALEW0 *((volatile unsigned int*)(0x427E0CA0UL)) -#define bFM3_EXBUS_ATIM1_ALEW1 *((volatile unsigned int*)(0x427E0CA4UL)) -#define bFM3_EXBUS_ATIM1_ALEW2 *((volatile unsigned int*)(0x427E0CA8UL)) -#define bFM3_EXBUS_ATIM1_ALEW3 *((volatile unsigned int*)(0x427E0CACUL)) -#define bFM3_EXBUS_ATIM2_ALC0 *((volatile unsigned int*)(0x427E0D00UL)) -#define bFM3_EXBUS_ATIM2_ALC1 *((volatile unsigned int*)(0x427E0D04UL)) -#define bFM3_EXBUS_ATIM2_ALC2 *((volatile unsigned int*)(0x427E0D08UL)) -#define bFM3_EXBUS_ATIM2_ALC3 *((volatile unsigned int*)(0x427E0D0CUL)) -#define bFM3_EXBUS_ATIM2_ALES0 *((volatile unsigned int*)(0x427E0D10UL)) -#define bFM3_EXBUS_ATIM2_ALES1 *((volatile unsigned int*)(0x427E0D14UL)) -#define bFM3_EXBUS_ATIM2_ALES2 *((volatile unsigned int*)(0x427E0D18UL)) -#define bFM3_EXBUS_ATIM2_ALES3 *((volatile unsigned int*)(0x427E0D1CUL)) -#define bFM3_EXBUS_ATIM2_ALEW0 *((volatile unsigned int*)(0x427E0D20UL)) -#define bFM3_EXBUS_ATIM2_ALEW1 *((volatile unsigned int*)(0x427E0D24UL)) -#define bFM3_EXBUS_ATIM2_ALEW2 *((volatile unsigned int*)(0x427E0D28UL)) -#define bFM3_EXBUS_ATIM2_ALEW3 *((volatile unsigned int*)(0x427E0D2CUL)) -#define bFM3_EXBUS_ATIM3_ALC0 *((volatile unsigned int*)(0x427E0D80UL)) -#define bFM3_EXBUS_ATIM3_ALC1 *((volatile unsigned int*)(0x427E0D84UL)) -#define bFM3_EXBUS_ATIM3_ALC2 *((volatile unsigned int*)(0x427E0D88UL)) -#define bFM3_EXBUS_ATIM3_ALC3 *((volatile unsigned int*)(0x427E0D8CUL)) -#define bFM3_EXBUS_ATIM3_ALES0 *((volatile unsigned int*)(0x427E0D90UL)) -#define bFM3_EXBUS_ATIM3_ALES1 *((volatile unsigned int*)(0x427E0D94UL)) -#define bFM3_EXBUS_ATIM3_ALES2 *((volatile unsigned int*)(0x427E0D98UL)) -#define bFM3_EXBUS_ATIM3_ALES3 *((volatile unsigned int*)(0x427E0D9CUL)) -#define bFM3_EXBUS_ATIM3_ALEW0 *((volatile unsigned int*)(0x427E0DA0UL)) -#define bFM3_EXBUS_ATIM3_ALEW1 *((volatile unsigned int*)(0x427E0DA4UL)) -#define bFM3_EXBUS_ATIM3_ALEW2 *((volatile unsigned int*)(0x427E0DA8UL)) -#define bFM3_EXBUS_ATIM3_ALEW3 *((volatile unsigned int*)(0x427E0DACUL)) -#define bFM3_EXBUS_ATIM4_ALC0 *((volatile unsigned int*)(0x427E0E00UL)) -#define bFM3_EXBUS_ATIM4_ALC1 *((volatile unsigned int*)(0x427E0E04UL)) -#define bFM3_EXBUS_ATIM4_ALC2 *((volatile unsigned int*)(0x427E0E08UL)) -#define bFM3_EXBUS_ATIM4_ALC3 *((volatile unsigned int*)(0x427E0E0CUL)) -#define bFM3_EXBUS_ATIM4_ALES0 *((volatile unsigned int*)(0x427E0E10UL)) -#define bFM3_EXBUS_ATIM4_ALES1 *((volatile unsigned int*)(0x427E0E14UL)) -#define bFM3_EXBUS_ATIM4_ALES2 *((volatile unsigned int*)(0x427E0E18UL)) -#define bFM3_EXBUS_ATIM4_ALES3 *((volatile unsigned int*)(0x427E0E1CUL)) -#define bFM3_EXBUS_ATIM4_ALEW0 *((volatile unsigned int*)(0x427E0E20UL)) -#define bFM3_EXBUS_ATIM4_ALEW1 *((volatile unsigned int*)(0x427E0E24UL)) -#define bFM3_EXBUS_ATIM4_ALEW2 *((volatile unsigned int*)(0x427E0E28UL)) -#define bFM3_EXBUS_ATIM4_ALEW3 *((volatile unsigned int*)(0x427E0E2CUL)) -#define bFM3_EXBUS_ATIM5_ALC0 *((volatile unsigned int*)(0x427E0E80UL)) -#define bFM3_EXBUS_ATIM5_ALC1 *((volatile unsigned int*)(0x427E0E84UL)) -#define bFM3_EXBUS_ATIM5_ALC2 *((volatile unsigned int*)(0x427E0E88UL)) -#define bFM3_EXBUS_ATIM5_ALC3 *((volatile unsigned int*)(0x427E0E8CUL)) -#define bFM3_EXBUS_ATIM5_ALES0 *((volatile unsigned int*)(0x427E0E90UL)) -#define bFM3_EXBUS_ATIM5_ALES1 *((volatile unsigned int*)(0x427E0E94UL)) -#define bFM3_EXBUS_ATIM5_ALES2 *((volatile unsigned int*)(0x427E0E98UL)) -#define bFM3_EXBUS_ATIM5_ALES3 *((volatile unsigned int*)(0x427E0E9CUL)) -#define bFM3_EXBUS_ATIM5_ALEW0 *((volatile unsigned int*)(0x427E0EA0UL)) -#define bFM3_EXBUS_ATIM5_ALEW1 *((volatile unsigned int*)(0x427E0EA4UL)) -#define bFM3_EXBUS_ATIM5_ALEW2 *((volatile unsigned int*)(0x427E0EA8UL)) -#define bFM3_EXBUS_ATIM5_ALEW3 *((volatile unsigned int*)(0x427E0EACUL)) -#define bFM3_EXBUS_ATIM6_ALC0 *((volatile unsigned int*)(0x427E0F00UL)) -#define bFM3_EXBUS_ATIM6_ALC1 *((volatile unsigned int*)(0x427E0F04UL)) -#define bFM3_EXBUS_ATIM6_ALC2 *((volatile unsigned int*)(0x427E0F08UL)) -#define bFM3_EXBUS_ATIM6_ALC3 *((volatile unsigned int*)(0x427E0F0CUL)) -#define bFM3_EXBUS_ATIM6_ALES0 *((volatile unsigned int*)(0x427E0F10UL)) -#define bFM3_EXBUS_ATIM6_ALES1 *((volatile unsigned int*)(0x427E0F14UL)) -#define bFM3_EXBUS_ATIM6_ALES2 *((volatile unsigned int*)(0x427E0F18UL)) -#define bFM3_EXBUS_ATIM6_ALES3 *((volatile unsigned int*)(0x427E0F1CUL)) -#define bFM3_EXBUS_ATIM6_ALEW0 *((volatile unsigned int*)(0x427E0F20UL)) -#define bFM3_EXBUS_ATIM6_ALEW1 *((volatile unsigned int*)(0x427E0F24UL)) -#define bFM3_EXBUS_ATIM6_ALEW2 *((volatile unsigned int*)(0x427E0F28UL)) -#define bFM3_EXBUS_ATIM6_ALEW3 *((volatile unsigned int*)(0x427E0F2CUL)) -#define bFM3_EXBUS_ATIM7_ALC0 *((volatile unsigned int*)(0x427E0F80UL)) -#define bFM3_EXBUS_ATIM7_ALC1 *((volatile unsigned int*)(0x427E0F84UL)) -#define bFM3_EXBUS_ATIM7_ALC2 *((volatile unsigned int*)(0x427E0F88UL)) -#define bFM3_EXBUS_ATIM7_ALC3 *((volatile unsigned int*)(0x427E0F8CUL)) -#define bFM3_EXBUS_ATIM7_ALES0 *((volatile unsigned int*)(0x427E0F90UL)) -#define bFM3_EXBUS_ATIM7_ALES1 *((volatile unsigned int*)(0x427E0F94UL)) -#define bFM3_EXBUS_ATIM7_ALES2 *((volatile unsigned int*)(0x427E0F98UL)) -#define bFM3_EXBUS_ATIM7_ALES3 *((volatile unsigned int*)(0x427E0F9CUL)) -#define bFM3_EXBUS_ATIM7_ALEW0 *((volatile unsigned int*)(0x427E0FA0UL)) -#define bFM3_EXBUS_ATIM7_ALEW1 *((volatile unsigned int*)(0x427E0FA4UL)) -#define bFM3_EXBUS_ATIM7_ALEW2 *((volatile unsigned int*)(0x427E0FA8UL)) -#define bFM3_EXBUS_ATIM7_ALEW3 *((volatile unsigned int*)(0x427E0FACUL)) -#define bFM3_EXBUS_DCLKR_MDIV0 *((volatile unsigned int*)(0x427E6000UL)) -#define bFM3_EXBUS_DCLKR_MDIV1 *((volatile unsigned int*)(0x427E6004UL)) -#define bFM3_EXBUS_DCLKR_MDIV2 *((volatile unsigned int*)(0x427E6008UL)) -#define bFM3_EXBUS_DCLKR_MDIV3 *((volatile unsigned int*)(0x427E600CUL)) -#define bFM3_EXBUS_DCLKR_MCLKON *((volatile unsigned int*)(0x427E6010UL)) - -/* USB channel 0 registers */ -#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) -#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* USB channel 1 registers */ -#define bFM3_USB1_HCNT_HOST *((volatile unsigned int*)(0x42A42000UL)) -#define bFM3_USB1_HCNT_URST *((volatile unsigned int*)(0x42A42004UL)) -#define bFM3_USB1_HCNT_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) -#define bFM3_USB1_HCNT_DIRE *((volatile unsigned int*)(0x42A4200CUL)) -#define bFM3_USB1_HCNT_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) -#define bFM3_USB1_HCNT_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) -#define bFM3_USB1_HCNT_URIRE *((volatile unsigned int*)(0x42A42018UL)) -#define bFM3_USB1_HCNT_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) -#define bFM3_USB1_HCNT_RETRY *((volatile unsigned int*)(0x42A42020UL)) -#define bFM3_USB1_HCNT_CANCEL *((volatile unsigned int*)(0x42A42024UL)) -#define bFM3_USB1_HCNT_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) -#define bFM3_USB1_HCNT0_HOST *((volatile unsigned int*)(0x42A42000UL)) -#define bFM3_USB1_HCNT0_URST *((volatile unsigned int*)(0x42A42004UL)) -#define bFM3_USB1_HCNT0_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) -#define bFM3_USB1_HCNT0_DIRE *((volatile unsigned int*)(0x42A4200CUL)) -#define bFM3_USB1_HCNT0_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) -#define bFM3_USB1_HCNT0_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) -#define bFM3_USB1_HCNT0_URIRE *((volatile unsigned int*)(0x42A42018UL)) -#define bFM3_USB1_HCNT0_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) -#define bFM3_USB1_HCNT1_RETRY *((volatile unsigned int*)(0x42A42020UL)) -#define bFM3_USB1_HCNT1_CANCEL *((volatile unsigned int*)(0x42A42024UL)) -#define bFM3_USB1_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) -#define bFM3_USB1_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42A42080UL)) -#define bFM3_USB1_HIRQ_DIRQ *((volatile unsigned int*)(0x42A42084UL)) -#define bFM3_USB1_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42A42088UL)) -#define bFM3_USB1_HIRQ_CMPIRQ *((volatile unsigned int*)(0x42A4208CUL)) -#define bFM3_USB1_HIRQ_URIRQ *((volatile unsigned int*)(0x42A42090UL)) -#define bFM3_USB1_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42A42094UL)) -#define bFM3_USB1_HIRQ_TCAN *((volatile unsigned int*)(0x42A4209CUL)) -#define bFM3_USB1_HERR_HS0 *((volatile unsigned int*)(0x42A420A0UL)) -#define bFM3_USB1_HERR_HS1 *((volatile unsigned int*)(0x42A420A4UL)) -#define bFM3_USB1_HERR_STUFF *((volatile unsigned int*)(0x42A420A8UL)) -#define bFM3_USB1_HERR_TGERR *((volatile unsigned int*)(0x42A420ACUL)) -#define bFM3_USB1_HERR_CRC *((volatile unsigned int*)(0x42A420B0UL)) -#define bFM3_USB1_HERR_TOUT *((volatile unsigned int*)(0x42A420B4UL)) -#define bFM3_USB1_HERR_RERR *((volatile unsigned int*)(0x42A420B8UL)) -#define bFM3_USB1_HERR_LSTOF *((volatile unsigned int*)(0x42A420BCUL)) -#define bFM3_USB1_HSTATE_CSTAT *((volatile unsigned int*)(0x42A42100UL)) -#define bFM3_USB1_HSTATE_TMODE *((volatile unsigned int*)(0x42A42104UL)) -#define bFM3_USB1_HSTATE_SUSP *((volatile unsigned int*)(0x42A42108UL)) -#define bFM3_USB1_HSTATE_SOFBUSY *((volatile unsigned int*)(0x42A4210CUL)) -#define bFM3_USB1_HSTATE_CLKSEL *((volatile unsigned int*)(0x42A42110UL)) -#define bFM3_USB1_HSTATE_ALIVE *((volatile unsigned int*)(0x42A42114UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42A42120UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42A42124UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42A42128UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x42A4212CUL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42A42130UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42A42134UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42A42138UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x42A4213CUL)) -#define bFM3_USB1_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42A42180UL)) -#define bFM3_USB1_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42A42184UL)) -#define bFM3_USB1_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42A42188UL)) -#define bFM3_USB1_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x42A4218CUL)) -#define bFM3_USB1_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42A42190UL)) -#define bFM3_USB1_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42A42194UL)) -#define bFM3_USB1_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42A42198UL)) -#define bFM3_USB1_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x42A4219CUL)) -#define bFM3_USB1_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x42A421A0UL)) -#define bFM3_USB1_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x42A421A4UL)) -#define bFM3_USB1_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x42A421A8UL)) -#define bFM3_USB1_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x42A421ACUL)) -#define bFM3_USB1_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x42A421B0UL)) -#define bFM3_USB1_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x42A421B4UL)) -#define bFM3_USB1_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x42A421B8UL)) -#define bFM3_USB1_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x42A421BCUL)) -#define bFM3_USB1_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42A42180UL)) -#define bFM3_USB1_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42A42184UL)) -#define bFM3_USB1_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42A42188UL)) -#define bFM3_USB1_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x42A4218CUL)) -#define bFM3_USB1_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42A42190UL)) -#define bFM3_USB1_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42A42194UL)) -#define bFM3_USB1_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42A42198UL)) -#define bFM3_USB1_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x42A4219CUL)) -#define bFM3_USB1_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x42A421A0UL)) -#define bFM3_USB1_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x42A421A4UL)) -#define bFM3_USB1_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x42A421A8UL)) -#define bFM3_USB1_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x42A421ACUL)) -#define bFM3_USB1_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x42A421B0UL)) -#define bFM3_USB1_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x42A421B4UL)) -#define bFM3_USB1_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x42A421B8UL)) -#define bFM3_USB1_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x42A421BCUL)) -#define bFM3_USB1_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42A42200UL)) -#define bFM3_USB1_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42A42204UL)) -#define bFM3_USB1_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42A42208UL)) -#define bFM3_USB1_HADR_ADDRESS0 *((volatile unsigned int*)(0x42A42220UL)) -#define bFM3_USB1_HADR_ADDRESS1 *((volatile unsigned int*)(0x42A42224UL)) -#define bFM3_USB1_HADR_ADDRESS2 *((volatile unsigned int*)(0x42A42228UL)) -#define bFM3_USB1_HADR_ADDRESS3 *((volatile unsigned int*)(0x42A4222CUL)) -#define bFM3_USB1_HADR_ADDRESS4 *((volatile unsigned int*)(0x42A42230UL)) -#define bFM3_USB1_HADR_ADDRESS5 *((volatile unsigned int*)(0x42A42234UL)) -#define bFM3_USB1_HADR_ADDRESS6 *((volatile unsigned int*)(0x42A42238UL)) -#define bFM3_USB1_HEOF_EOF0 *((volatile unsigned int*)(0x42A42280UL)) -#define bFM3_USB1_HEOF_EOF1 *((volatile unsigned int*)(0x42A42284UL)) -#define bFM3_USB1_HEOF_EOF2 *((volatile unsigned int*)(0x42A42288UL)) -#define bFM3_USB1_HEOF_EOF3 *((volatile unsigned int*)(0x42A4228CUL)) -#define bFM3_USB1_HEOF_EOF4 *((volatile unsigned int*)(0x42A42290UL)) -#define bFM3_USB1_HEOF_EOF5 *((volatile unsigned int*)(0x42A42294UL)) -#define bFM3_USB1_HEOF_EOF6 *((volatile unsigned int*)(0x42A42298UL)) -#define bFM3_USB1_HEOF_EOF7 *((volatile unsigned int*)(0x42A4229CUL)) -#define bFM3_USB1_HEOF_EOF8 *((volatile unsigned int*)(0x42A422A0UL)) -#define bFM3_USB1_HEOF_EOF9 *((volatile unsigned int*)(0x42A422A4UL)) -#define bFM3_USB1_HEOF_EOF10 *((volatile unsigned int*)(0x42A422A8UL)) -#define bFM3_USB1_HEOF_EOF11 *((volatile unsigned int*)(0x42A422ACUL)) -#define bFM3_USB1_HEOF_EOF12 *((volatile unsigned int*)(0x42A422B0UL)) -#define bFM3_USB1_HEOF_EOF13 *((volatile unsigned int*)(0x42A422B4UL)) -#define bFM3_USB1_HEOF_EOF14 *((volatile unsigned int*)(0x42A422B8UL)) -#define bFM3_USB1_HEOF_EOF15 *((volatile unsigned int*)(0x42A422BCUL)) -#define bFM3_USB1_HEOF0_EOF00 *((volatile unsigned int*)(0x42A42280UL)) -#define bFM3_USB1_HEOF0_EOF01 *((volatile unsigned int*)(0x42A42284UL)) -#define bFM3_USB1_HEOF0_EOF02 *((volatile unsigned int*)(0x42A42288UL)) -#define bFM3_USB1_HEOF0_EOF03 *((volatile unsigned int*)(0x42A4228CUL)) -#define bFM3_USB1_HEOF0_EOF04 *((volatile unsigned int*)(0x42A42290UL)) -#define bFM3_USB1_HEOF0_EOF05 *((volatile unsigned int*)(0x42A42294UL)) -#define bFM3_USB1_HEOF0_EOF06 *((volatile unsigned int*)(0x42A42298UL)) -#define bFM3_USB1_HEOF0_EOF07 *((volatile unsigned int*)(0x42A4229CUL)) -#define bFM3_USB1_HEOF1_EOF10 *((volatile unsigned int*)(0x42A422A0UL)) -#define bFM3_USB1_HEOF1_EOF11 *((volatile unsigned int*)(0x42A422A4UL)) -#define bFM3_USB1_HEOF1_EOF12 *((volatile unsigned int*)(0x42A422A8UL)) -#define bFM3_USB1_HEOF1_EOF13 *((volatile unsigned int*)(0x42A422ACUL)) -#define bFM3_USB1_HEOF1_EOF14 *((volatile unsigned int*)(0x42A422B0UL)) -#define bFM3_USB1_HEOF1_EOF15 *((volatile unsigned int*)(0x42A422B4UL)) -#define bFM3_USB1_HFRAME_FRAME0 *((volatile unsigned int*)(0x42A42300UL)) -#define bFM3_USB1_HFRAME_FRAME1 *((volatile unsigned int*)(0x42A42304UL)) -#define bFM3_USB1_HFRAME_FRAME2 *((volatile unsigned int*)(0x42A42308UL)) -#define bFM3_USB1_HFRAME_FRAME3 *((volatile unsigned int*)(0x42A4230CUL)) -#define bFM3_USB1_HFRAME_FRAME4 *((volatile unsigned int*)(0x42A42310UL)) -#define bFM3_USB1_HFRAME_FRAME5 *((volatile unsigned int*)(0x42A42314UL)) -#define bFM3_USB1_HFRAME_FRAME6 *((volatile unsigned int*)(0x42A42318UL)) -#define bFM3_USB1_HFRAME_FRAME7 *((volatile unsigned int*)(0x42A4231CUL)) -#define bFM3_USB1_HFRAME_FRAME8 *((volatile unsigned int*)(0x42A42320UL)) -#define bFM3_USB1_HFRAME_FRAME9 *((volatile unsigned int*)(0x42A42324UL)) -#define bFM3_USB1_HFRAME_FRAME10 *((volatile unsigned int*)(0x42A42328UL)) -#define bFM3_USB1_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42A42300UL)) -#define bFM3_USB1_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42A42304UL)) -#define bFM3_USB1_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42A42308UL)) -#define bFM3_USB1_HFRAME0_FRAME03 *((volatile unsigned int*)(0x42A4230CUL)) -#define bFM3_USB1_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42A42310UL)) -#define bFM3_USB1_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42A42314UL)) -#define bFM3_USB1_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42A42318UL)) -#define bFM3_USB1_HFRAME0_FRAME07 *((volatile unsigned int*)(0x42A4231CUL)) -#define bFM3_USB1_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42A42320UL)) -#define bFM3_USB1_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42A42324UL)) -#define bFM3_USB1_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42A42328UL)) -#define bFM3_USB1_HFRAME1_FRAME13 *((volatile unsigned int*)(0x42A4232CUL)) -#define bFM3_USB1_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42A42380UL)) -#define bFM3_USB1_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42A42384UL)) -#define bFM3_USB1_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42A42388UL)) -#define bFM3_USB1_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x42A4238CUL)) -#define bFM3_USB1_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42A42390UL)) -#define bFM3_USB1_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42A42394UL)) -#define bFM3_USB1_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42A42398UL)) -#define bFM3_USB1_HTOKEN_TGGL *((volatile unsigned int*)(0x42A4239CUL)) -#define bFM3_USB1_UDCC_PWC *((volatile unsigned int*)(0x42A42400UL)) -#define bFM3_USB1_UDCC_RFBK *((volatile unsigned int*)(0x42A42404UL)) -#define bFM3_USB1_UDCC_STALCLREN *((volatile unsigned int*)(0x42A4240CUL)) -#define bFM3_USB1_UDCC_USTP *((volatile unsigned int*)(0x42A42410UL)) -#define bFM3_USB1_UDCC_HCONX *((volatile unsigned int*)(0x42A42414UL)) -#define bFM3_USB1_UDCC_RESUM *((volatile unsigned int*)(0x42A42418UL)) -#define bFM3_USB1_UDCC_RST *((volatile unsigned int*)(0x42A4241CUL)) -#define bFM3_USB1_EP0C_PKS00 *((volatile unsigned int*)(0x42A42480UL)) -#define bFM3_USB1_EP0C_PKS01 *((volatile unsigned int*)(0x42A42484UL)) -#define bFM3_USB1_EP0C_PKS02 *((volatile unsigned int*)(0x42A42488UL)) -#define bFM3_USB1_EP0C_PKS03 *((volatile unsigned int*)(0x42A4248CUL)) -#define bFM3_USB1_EP0C_PKS04 *((volatile unsigned int*)(0x42A42490UL)) -#define bFM3_USB1_EP0C_PKS05 *((volatile unsigned int*)(0x42A42494UL)) -#define bFM3_USB1_EP0C_PKS06 *((volatile unsigned int*)(0x42A42498UL)) -#define bFM3_USB1_EP0C_STAL *((volatile unsigned int*)(0x42A424A4UL)) -#define bFM3_USB1_EP1C_PKS10 *((volatile unsigned int*)(0x42A42500UL)) -#define bFM3_USB1_EP1C_PKS11 *((volatile unsigned int*)(0x42A42504UL)) -#define bFM3_USB1_EP1C_PKS12 *((volatile unsigned int*)(0x42A42508UL)) -#define bFM3_USB1_EP1C_PKS13 *((volatile unsigned int*)(0x42A4250CUL)) -#define bFM3_USB1_EP1C_PKS14 *((volatile unsigned int*)(0x42A42510UL)) -#define bFM3_USB1_EP1C_PKS15 *((volatile unsigned int*)(0x42A42514UL)) -#define bFM3_USB1_EP1C_PKS16 *((volatile unsigned int*)(0x42A42518UL)) -#define bFM3_USB1_EP1C_PKS17 *((volatile unsigned int*)(0x42A4251CUL)) -#define bFM3_USB1_EP1C_PKS18 *((volatile unsigned int*)(0x42A42520UL)) -#define bFM3_USB1_EP1C_STAL *((volatile unsigned int*)(0x42A42524UL)) -#define bFM3_USB1_EP1C_NULE *((volatile unsigned int*)(0x42A42528UL)) -#define bFM3_USB1_EP1C_DMAE *((volatile unsigned int*)(0x42A4252CUL)) -#define bFM3_USB1_EP1C_DIR *((volatile unsigned int*)(0x42A42530UL)) -#define bFM3_USB1_EP1C_TYPE0 *((volatile unsigned int*)(0x42A42534UL)) -#define bFM3_USB1_EP1C_TYPE1 *((volatile unsigned int*)(0x42A42538UL)) -#define bFM3_USB1_EP1C_EPEN *((volatile unsigned int*)(0x42A4253CUL)) -#define bFM3_USB1_EP2C_PKS20 *((volatile unsigned int*)(0x42A42580UL)) -#define bFM3_USB1_EP2C_PKS21 *((volatile unsigned int*)(0x42A42584UL)) -#define bFM3_USB1_EP2C_PKS22 *((volatile unsigned int*)(0x42A42588UL)) -#define bFM3_USB1_EP2C_PKS23 *((volatile unsigned int*)(0x42A4258CUL)) -#define bFM3_USB1_EP2C_PKS24 *((volatile unsigned int*)(0x42A42590UL)) -#define bFM3_USB1_EP2C_PKS25 *((volatile unsigned int*)(0x42A42594UL)) -#define bFM3_USB1_EP2C_PKS26 *((volatile unsigned int*)(0x42A42598UL)) -#define bFM3_USB1_EP2C_STAL *((volatile unsigned int*)(0x42A425A4UL)) -#define bFM3_USB1_EP2C_NULE *((volatile unsigned int*)(0x42A425A8UL)) -#define bFM3_USB1_EP2C_DMAE *((volatile unsigned int*)(0x42A425ACUL)) -#define bFM3_USB1_EP2C_DIR *((volatile unsigned int*)(0x42A425B0UL)) -#define bFM3_USB1_EP2C_TYPE0 *((volatile unsigned int*)(0x42A425B4UL)) -#define bFM3_USB1_EP2C_TYPE1 *((volatile unsigned int*)(0x42A425B8UL)) -#define bFM3_USB1_EP2C_EPEN *((volatile unsigned int*)(0x42A425BCUL)) -#define bFM3_USB1_EP3C_PKS30 *((volatile unsigned int*)(0x42A42600UL)) -#define bFM3_USB1_EP3C_PKS31 *((volatile unsigned int*)(0x42A42604UL)) -#define bFM3_USB1_EP3C_PKS32 *((volatile unsigned int*)(0x42A42608UL)) -#define bFM3_USB1_EP3C_PKS33 *((volatile unsigned int*)(0x42A4260CUL)) -#define bFM3_USB1_EP3C_PKS34 *((volatile unsigned int*)(0x42A42610UL)) -#define bFM3_USB1_EP3C_PKS35 *((volatile unsigned int*)(0x42A42614UL)) -#define bFM3_USB1_EP3C_PKS36 *((volatile unsigned int*)(0x42A42618UL)) -#define bFM3_USB1_EP3C_STAL *((volatile unsigned int*)(0x42A42624UL)) -#define bFM3_USB1_EP3C_NULE *((volatile unsigned int*)(0x42A42628UL)) -#define bFM3_USB1_EP3C_DMAE *((volatile unsigned int*)(0x42A4262CUL)) -#define bFM3_USB1_EP3C_DIR *((volatile unsigned int*)(0x42A42630UL)) -#define bFM3_USB1_EP3C_TYPE0 *((volatile unsigned int*)(0x42A42634UL)) -#define bFM3_USB1_EP3C_TYPE1 *((volatile unsigned int*)(0x42A42638UL)) -#define bFM3_USB1_EP3C_EPEN *((volatile unsigned int*)(0x42A4263CUL)) -#define bFM3_USB1_EP4C_PKS40 *((volatile unsigned int*)(0x42A42680UL)) -#define bFM3_USB1_EP4C_PKS41 *((volatile unsigned int*)(0x42A42684UL)) -#define bFM3_USB1_EP4C_PKS42 *((volatile unsigned int*)(0x42A42688UL)) -#define bFM3_USB1_EP4C_PKS43 *((volatile unsigned int*)(0x42A4268CUL)) -#define bFM3_USB1_EP4C_PKS44 *((volatile unsigned int*)(0x42A42690UL)) -#define bFM3_USB1_EP4C_PKS45 *((volatile unsigned int*)(0x42A42694UL)) -#define bFM3_USB1_EP4C_PKS46 *((volatile unsigned int*)(0x42A42698UL)) -#define bFM3_USB1_EP4C_STAL *((volatile unsigned int*)(0x42A426A4UL)) -#define bFM3_USB1_EP4C_NULE *((volatile unsigned int*)(0x42A426A8UL)) -#define bFM3_USB1_EP4C_DMAE *((volatile unsigned int*)(0x42A426ACUL)) -#define bFM3_USB1_EP4C_DIR *((volatile unsigned int*)(0x42A426B0UL)) -#define bFM3_USB1_EP4C_TYPE0 *((volatile unsigned int*)(0x42A426B4UL)) -#define bFM3_USB1_EP4C_TYPE1 *((volatile unsigned int*)(0x42A426B8UL)) -#define bFM3_USB1_EP4C_EPEN *((volatile unsigned int*)(0x42A426BCUL)) -#define bFM3_USB1_EP5C_PKS50 *((volatile unsigned int*)(0x42A42700UL)) -#define bFM3_USB1_EP5C_PKS51 *((volatile unsigned int*)(0x42A42704UL)) -#define bFM3_USB1_EP5C_PKS52 *((volatile unsigned int*)(0x42A42708UL)) -#define bFM3_USB1_EP5C_PKS53 *((volatile unsigned int*)(0x42A4270CUL)) -#define bFM3_USB1_EP5C_PKS54 *((volatile unsigned int*)(0x42A42710UL)) -#define bFM3_USB1_EP5C_PKS55 *((volatile unsigned int*)(0x42A42714UL)) -#define bFM3_USB1_EP5C_PKS56 *((volatile unsigned int*)(0x42A42718UL)) -#define bFM3_USB1_EP5C_STAL *((volatile unsigned int*)(0x42A42724UL)) -#define bFM3_USB1_EP5C_NULE *((volatile unsigned int*)(0x42A42728UL)) -#define bFM3_USB1_EP5C_DMAE *((volatile unsigned int*)(0x42A4272CUL)) -#define bFM3_USB1_EP5C_DIR *((volatile unsigned int*)(0x42A42730UL)) -#define bFM3_USB1_EP5C_TYPE0 *((volatile unsigned int*)(0x42A42734UL)) -#define bFM3_USB1_EP5C_TYPE1 *((volatile unsigned int*)(0x42A42738UL)) -#define bFM3_USB1_EP5C_EPEN *((volatile unsigned int*)(0x42A4273CUL)) -#define bFM3_USB1_TMSP_TMSP0 *((volatile unsigned int*)(0x42A42780UL)) -#define bFM3_USB1_TMSP_TMSP1 *((volatile unsigned int*)(0x42A42784UL)) -#define bFM3_USB1_TMSP_TMSP2 *((volatile unsigned int*)(0x42A42788UL)) -#define bFM3_USB1_TMSP_TMSP3 *((volatile unsigned int*)(0x42A4278CUL)) -#define bFM3_USB1_TMSP_TMSP4 *((volatile unsigned int*)(0x42A42790UL)) -#define bFM3_USB1_TMSP_TMSP5 *((volatile unsigned int*)(0x42A42794UL)) -#define bFM3_USB1_TMSP_TMSP6 *((volatile unsigned int*)(0x42A42798UL)) -#define bFM3_USB1_TMSP_TMSP7 *((volatile unsigned int*)(0x42A4279CUL)) -#define bFM3_USB1_TMSP_TMSP8 *((volatile unsigned int*)(0x42A427A0UL)) -#define bFM3_USB1_TMSP_TMSP9 *((volatile unsigned int*)(0x42A427A4UL)) -#define bFM3_USB1_TMSP_TMSP10 *((volatile unsigned int*)(0x42A427A8UL)) -#define bFM3_USB1_UDCS_CONF *((volatile unsigned int*)(0x42A42800UL)) -#define bFM3_USB1_UDCS_SETP *((volatile unsigned int*)(0x42A42804UL)) -#define bFM3_USB1_UDCS_WKUP *((volatile unsigned int*)(0x42A42808UL)) -#define bFM3_USB1_UDCS_BRST *((volatile unsigned int*)(0x42A4280CUL)) -#define bFM3_USB1_UDCS_SOF *((volatile unsigned int*)(0x42A42810UL)) -#define bFM3_USB1_UDCS_SUSP *((volatile unsigned int*)(0x42A42814UL)) -#define bFM3_USB1_UDCIE_CONFIE *((volatile unsigned int*)(0x42A42820UL)) -#define bFM3_USB1_UDCIE_CONFN *((volatile unsigned int*)(0x42A42824UL)) -#define bFM3_USB1_UDCIE_WKUPIE *((volatile unsigned int*)(0x42A42828UL)) -#define bFM3_USB1_UDCIE_BRSTIE *((volatile unsigned int*)(0x42A4282CUL)) -#define bFM3_USB1_UDCIE_SOFIE *((volatile unsigned int*)(0x42A42830UL)) -#define bFM3_USB1_UDCIE_SUSPIE *((volatile unsigned int*)(0x42A42834UL)) -#define bFM3_USB1_EP0IS_DRQI *((volatile unsigned int*)(0x42A428A8UL)) -#define bFM3_USB1_EP0IS_DRQIIE *((volatile unsigned int*)(0x42A428B8UL)) -#define bFM3_USB1_EP0IS_BFINI *((volatile unsigned int*)(0x42A428BCUL)) -#define bFM3_USB1_EP0OS_SIZE0 *((volatile unsigned int*)(0x42A42900UL)) -#define bFM3_USB1_EP0OS_SIZE1 *((volatile unsigned int*)(0x42A42904UL)) -#define bFM3_USB1_EP0OS_SIZE2 *((volatile unsigned int*)(0x42A42908UL)) -#define bFM3_USB1_EP0OS_SIZE3 *((volatile unsigned int*)(0x42A4290CUL)) -#define bFM3_USB1_EP0OS_SIZE4 *((volatile unsigned int*)(0x42A42910UL)) -#define bFM3_USB1_EP0OS_SIZE5 *((volatile unsigned int*)(0x42A42914UL)) -#define bFM3_USB1_EP0OS_SIZE6 *((volatile unsigned int*)(0x42A42918UL)) -#define bFM3_USB1_EP0OS_SPK *((volatile unsigned int*)(0x42A42924UL)) -#define bFM3_USB1_EP0OS_DRQO *((volatile unsigned int*)(0x42A42928UL)) -#define bFM3_USB1_EP0OS_SPKIE *((volatile unsigned int*)(0x42A42934UL)) -#define bFM3_USB1_EP0OS_DRQOIE *((volatile unsigned int*)(0x42A42938UL)) -#define bFM3_USB1_EP0OS_BFINI *((volatile unsigned int*)(0x42A4293CUL)) -#define bFM3_USB1_EP1S_SIZE10 *((volatile unsigned int*)(0x42A42980UL)) -#define bFM3_USB1_EP1S_SIZE11 *((volatile unsigned int*)(0x42A42984UL)) -#define bFM3_USB1_EP1S_SIZE12 *((volatile unsigned int*)(0x42A42988UL)) -#define bFM3_USB1_EP1S_SIZE13 *((volatile unsigned int*)(0x42A4298CUL)) -#define bFM3_USB1_EP1S_SIZE14 *((volatile unsigned int*)(0x42A42990UL)) -#define bFM3_USB1_EP1S_SIZE15 *((volatile unsigned int*)(0x42A42994UL)) -#define bFM3_USB1_EP1S_SIZE16 *((volatile unsigned int*)(0x42A42998UL)) -#define bFM3_USB1_EP1S_SIZE17 *((volatile unsigned int*)(0x42A4299CUL)) -#define bFM3_USB1_EP1S_SIZE18 *((volatile unsigned int*)(0x42A429A0UL)) -#define bFM3_USB1_EP1S_SPK *((volatile unsigned int*)(0x42A429A4UL)) -#define bFM3_USB1_EP1S_DRQ *((volatile unsigned int*)(0x42A429A8UL)) -#define bFM3_USB1_EP1S_BUSY *((volatile unsigned int*)(0x42A429ACUL)) -#define bFM3_USB1_EP1S_SPKIE *((volatile unsigned int*)(0x42A429B4UL)) -#define bFM3_USB1_EP1S_DRQIE *((volatile unsigned int*)(0x42A429B8UL)) -#define bFM3_USB1_EP1S_BFINI *((volatile unsigned int*)(0x42A429BCUL)) -#define bFM3_USB1_EP2S_SIZE20 *((volatile unsigned int*)(0x42A42A00UL)) -#define bFM3_USB1_EP2S_SIZE21 *((volatile unsigned int*)(0x42A42A04UL)) -#define bFM3_USB1_EP2S_SIZE22 *((volatile unsigned int*)(0x42A42A08UL)) -#define bFM3_USB1_EP2S_SIZE23 *((volatile unsigned int*)(0x42A42A0CUL)) -#define bFM3_USB1_EP2S_SIZE24 *((volatile unsigned int*)(0x42A42A10UL)) -#define bFM3_USB1_EP2S_SIZE25 *((volatile unsigned int*)(0x42A42A14UL)) -#define bFM3_USB1_EP2S_SIZE26 *((volatile unsigned int*)(0x42A42A18UL)) -#define bFM3_USB1_EP2S_SPK *((volatile unsigned int*)(0x42A42A24UL)) -#define bFM3_USB1_EP2S_DRQ *((volatile unsigned int*)(0x42A42A28UL)) -#define bFM3_USB1_EP2S_BUSY *((volatile unsigned int*)(0x42A42A2CUL)) -#define bFM3_USB1_EP2S_SPKIE *((volatile unsigned int*)(0x42A42A34UL)) -#define bFM3_USB1_EP2S_DRQIE *((volatile unsigned int*)(0x42A42A38UL)) -#define bFM3_USB1_EP2S_BFINI *((volatile unsigned int*)(0x42A42A3CUL)) -#define bFM3_USB1_EP3S_SIZE30 *((volatile unsigned int*)(0x42A42A80UL)) -#define bFM3_USB1_EP3S_SIZE31 *((volatile unsigned int*)(0x42A42A84UL)) -#define bFM3_USB1_EP3S_SIZE32 *((volatile unsigned int*)(0x42A42A88UL)) -#define bFM3_USB1_EP3S_SIZE33 *((volatile unsigned int*)(0x42A42A8CUL)) -#define bFM3_USB1_EP3S_SIZE34 *((volatile unsigned int*)(0x42A42A90UL)) -#define bFM3_USB1_EP3S_SIZE35 *((volatile unsigned int*)(0x42A42A94UL)) -#define bFM3_USB1_EP3S_SIZE36 *((volatile unsigned int*)(0x42A42A98UL)) -#define bFM3_USB1_EP3S_SPK *((volatile unsigned int*)(0x42A42AA4UL)) -#define bFM3_USB1_EP3S_DRQ *((volatile unsigned int*)(0x42A42AA8UL)) -#define bFM3_USB1_EP3S_BUSY *((volatile unsigned int*)(0x42A42AACUL)) -#define bFM3_USB1_EP3S_SPKIE *((volatile unsigned int*)(0x42A42AB4UL)) -#define bFM3_USB1_EP3S_DRQIE *((volatile unsigned int*)(0x42A42AB8UL)) -#define bFM3_USB1_EP3S_BFINI *((volatile unsigned int*)(0x42A42ABCUL)) -#define bFM3_USB1_EP4S_SIZE40 *((volatile unsigned int*)(0x42A42B00UL)) -#define bFM3_USB1_EP4S_SIZE41 *((volatile unsigned int*)(0x42A42B04UL)) -#define bFM3_USB1_EP4S_SIZE42 *((volatile unsigned int*)(0x42A42B08UL)) -#define bFM3_USB1_EP4S_SIZE43 *((volatile unsigned int*)(0x42A42B0CUL)) -#define bFM3_USB1_EP4S_SIZE44 *((volatile unsigned int*)(0x42A42B10UL)) -#define bFM3_USB1_EP4S_SIZE45 *((volatile unsigned int*)(0x42A42B14UL)) -#define bFM3_USB1_EP4S_SIZE46 *((volatile unsigned int*)(0x42A42B18UL)) -#define bFM3_USB1_EP4S_SPK *((volatile unsigned int*)(0x42A42B24UL)) -#define bFM3_USB1_EP4S_DRQ *((volatile unsigned int*)(0x42A42B28UL)) -#define bFM3_USB1_EP4S_BUSY *((volatile unsigned int*)(0x42A42B2CUL)) -#define bFM3_USB1_EP4S_SPKIE *((volatile unsigned int*)(0x42A42B34UL)) -#define bFM3_USB1_EP4S_DRQIE *((volatile unsigned int*)(0x42A42B38UL)) -#define bFM3_USB1_EP4S_BFINI *((volatile unsigned int*)(0x42A42B3CUL)) -#define bFM3_USB1_EP5S_SIZE50 *((volatile unsigned int*)(0x42A42B80UL)) -#define bFM3_USB1_EP5S_SIZE51 *((volatile unsigned int*)(0x42A42B84UL)) -#define bFM3_USB1_EP5S_SIZE52 *((volatile unsigned int*)(0x42A42B88UL)) -#define bFM3_USB1_EP5S_SIZE53 *((volatile unsigned int*)(0x42A42B8CUL)) -#define bFM3_USB1_EP5S_SIZE54 *((volatile unsigned int*)(0x42A42B90UL)) -#define bFM3_USB1_EP5S_SIZE55 *((volatile unsigned int*)(0x42A42B94UL)) -#define bFM3_USB1_EP5S_SIZE56 *((volatile unsigned int*)(0x42A42B98UL)) -#define bFM3_USB1_EP5S_SPK *((volatile unsigned int*)(0x42A42BA4UL)) -#define bFM3_USB1_EP5S_DRQ *((volatile unsigned int*)(0x42A42BA8UL)) -#define bFM3_USB1_EP5S_BUSY *((volatile unsigned int*)(0x42A42BACUL)) -#define bFM3_USB1_EP5S_SPKIE *((volatile unsigned int*)(0x42A42BB4UL)) -#define bFM3_USB1_EP5S_DRQIE *((volatile unsigned int*)(0x42A42BB8UL)) -#define bFM3_USB1_EP5S_BFINI *((volatile unsigned int*)(0x42A42BBCUL)) - -/* DMA controller */ -#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* ETHERNET-MAC0 registers*/ -#define bFM3_ETHERNET_MAC0_MCR_RE *((volatile unsigned int*)(0x42C80008UL)) -#define bFM3_ETHERNET_MAC0_MCR_TE *((volatile unsigned int*)(0x42C8000CUL)) -#define bFM3_ETHERNET_MAC0_MCR_DC *((volatile unsigned int*)(0x42C80010UL)) -#define bFM3_ETHERNET_MAC0_MCR_BL0 *((volatile unsigned int*)(0x42C80014UL)) -#define bFM3_ETHERNET_MAC0_MCR_BL1 *((volatile unsigned int*)(0x42C80018UL)) -#define bFM3_ETHERNET_MAC0_MCR_ACS *((volatile unsigned int*)(0x42C8001CUL)) -#define bFM3_ETHERNET_MAC0_MCR_LUD *((volatile unsigned int*)(0x42C80020UL)) -#define bFM3_ETHERNET_MAC0_MCR_DR *((volatile unsigned int*)(0x42C80024UL)) -#define bFM3_ETHERNET_MAC0_MCR_IPC *((volatile unsigned int*)(0x42C80028UL)) -#define bFM3_ETHERNET_MAC0_MCR_DM *((volatile unsigned int*)(0x42C8002CUL)) -#define bFM3_ETHERNET_MAC0_MCR_LM *((volatile unsigned int*)(0x42C80030UL)) -#define bFM3_ETHERNET_MAC0_MCR_DO *((volatile unsigned int*)(0x42C80034UL)) -#define bFM3_ETHERNET_MAC0_MCR_FES *((volatile unsigned int*)(0x42C80038UL)) -#define bFM3_ETHERNET_MAC0_MCR_PS *((volatile unsigned int*)(0x42C8003CUL)) -#define bFM3_ETHERNET_MAC0_MCR_DCRS *((volatile unsigned int*)(0x42C80040UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG0 *((volatile unsigned int*)(0x42C80044UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG1 *((volatile unsigned int*)(0x42C80048UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG2 *((volatile unsigned int*)(0x42C8004CUL)) -#define bFM3_ETHERNET_MAC0_MCR_JE *((volatile unsigned int*)(0x42C80050UL)) -#define bFM3_ETHERNET_MAC0_MCR_BE *((volatile unsigned int*)(0x42C80054UL)) -#define bFM3_ETHERNET_MAC0_MCR_JD *((volatile unsigned int*)(0x42C80058UL)) -#define bFM3_ETHERNET_MAC0_MCR_WD *((volatile unsigned int*)(0x42C8005CUL)) -#define bFM3_ETHERNET_MAC0_MCR_TC *((volatile unsigned int*)(0x42C80060UL)) -#define bFM3_ETHERNET_MAC0_MCR_CST *((volatile unsigned int*)(0x42C80064UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PR *((volatile unsigned int*)(0x42C80080UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HUC *((volatile unsigned int*)(0x42C80084UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HMC *((volatile unsigned int*)(0x42C80088UL)) -#define bFM3_ETHERNET_MAC0_MFFR_DAIF *((volatile unsigned int*)(0x42C8008CUL)) -#define bFM3_ETHERNET_MAC0_MFFR_PM *((volatile unsigned int*)(0x42C80090UL)) -#define bFM3_ETHERNET_MAC0_MFFR_DB *((volatile unsigned int*)(0x42C80094UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PCF0 *((volatile unsigned int*)(0x42C80098UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PCF1 *((volatile unsigned int*)(0x42C8009CUL)) -#define bFM3_ETHERNET_MAC0_MFFR_SAIF *((volatile unsigned int*)(0x42C800A0UL)) -#define bFM3_ETHERNET_MAC0_MFFR_SAF *((volatile unsigned int*)(0x42C800A4UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HPF *((volatile unsigned int*)(0x42C800A8UL)) -#define bFM3_ETHERNET_MAC0_MFFR_RA *((volatile unsigned int*)(0x42C800FCUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH0 *((volatile unsigned int*)(0x42C80100UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH1 *((volatile unsigned int*)(0x42C80104UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH2 *((volatile unsigned int*)(0x42C80108UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH3 *((volatile unsigned int*)(0x42C8010CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH4 *((volatile unsigned int*)(0x42C80110UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH5 *((volatile unsigned int*)(0x42C80114UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH6 *((volatile unsigned int*)(0x42C80118UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH7 *((volatile unsigned int*)(0x42C8011CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH8 *((volatile unsigned int*)(0x42C80120UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH9 *((volatile unsigned int*)(0x42C80124UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH10 *((volatile unsigned int*)(0x42C80128UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH11 *((volatile unsigned int*)(0x42C8012CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH12 *((volatile unsigned int*)(0x42C80130UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH13 *((volatile unsigned int*)(0x42C80134UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH14 *((volatile unsigned int*)(0x42C80138UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH15 *((volatile unsigned int*)(0x42C8013CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH16 *((volatile unsigned int*)(0x42C80140UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH17 *((volatile unsigned int*)(0x42C80144UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH18 *((volatile unsigned int*)(0x42C80148UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH19 *((volatile unsigned int*)(0x42C8014CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH20 *((volatile unsigned int*)(0x42C80150UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH21 *((volatile unsigned int*)(0x42C80154UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH22 *((volatile unsigned int*)(0x42C80158UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH23 *((volatile unsigned int*)(0x42C8015CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH24 *((volatile unsigned int*)(0x42C80160UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH25 *((volatile unsigned int*)(0x42C80164UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH26 *((volatile unsigned int*)(0x42C80168UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH27 *((volatile unsigned int*)(0x42C8016CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH28 *((volatile unsigned int*)(0x42C80170UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH29 *((volatile unsigned int*)(0x42C80174UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH30 *((volatile unsigned int*)(0x42C80178UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH31 *((volatile unsigned int*)(0x42C8017CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL0 *((volatile unsigned int*)(0x42C80180UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL1 *((volatile unsigned int*)(0x42C80184UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL2 *((volatile unsigned int*)(0x42C80188UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL3 *((volatile unsigned int*)(0x42C8018CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL4 *((volatile unsigned int*)(0x42C80190UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL5 *((volatile unsigned int*)(0x42C80194UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL6 *((volatile unsigned int*)(0x42C80198UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL7 *((volatile unsigned int*)(0x42C8019CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL8 *((volatile unsigned int*)(0x42C801A0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL9 *((volatile unsigned int*)(0x42C801A4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL10 *((volatile unsigned int*)(0x42C801A8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL11 *((volatile unsigned int*)(0x42C801ACUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL12 *((volatile unsigned int*)(0x42C801B0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL13 *((volatile unsigned int*)(0x42C801B4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL14 *((volatile unsigned int*)(0x42C801B8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL15 *((volatile unsigned int*)(0x42C801BCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL16 *((volatile unsigned int*)(0x42C801C0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL17 *((volatile unsigned int*)(0x42C801C4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL18 *((volatile unsigned int*)(0x42C801C8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL19 *((volatile unsigned int*)(0x42C801CCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL20 *((volatile unsigned int*)(0x42C801D0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL21 *((volatile unsigned int*)(0x42C801D4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL22 *((volatile unsigned int*)(0x42C801D8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL23 *((volatile unsigned int*)(0x42C801DCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL24 *((volatile unsigned int*)(0x42C801E0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL25 *((volatile unsigned int*)(0x42C801E4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL26 *((volatile unsigned int*)(0x42C801E8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL27 *((volatile unsigned int*)(0x42C801ECUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL28 *((volatile unsigned int*)(0x42C801F0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL29 *((volatile unsigned int*)(0x42C801F4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL30 *((volatile unsigned int*)(0x42C801F8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL31 *((volatile unsigned int*)(0x42C801FCUL)) -#define bFM3_ETHERNET_MAC0_GAR_GB *((volatile unsigned int*)(0x42C80200UL)) -#define bFM3_ETHERNET_MAC0_GAR_GW *((volatile unsigned int*)(0x42C80204UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR0 *((volatile unsigned int*)(0x42C80208UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR1 *((volatile unsigned int*)(0x42C8020CUL)) -#define bFM3_ETHERNET_MAC0_GAR_CR2 *((volatile unsigned int*)(0x42C80210UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR3 *((volatile unsigned int*)(0x42C80214UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR0 *((volatile unsigned int*)(0x42C80218UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR1 *((volatile unsigned int*)(0x42C8021CUL)) -#define bFM3_ETHERNET_MAC0_GAR_GR2 *((volatile unsigned int*)(0x42C80220UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR3 *((volatile unsigned int*)(0x42C80224UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR4 *((volatile unsigned int*)(0x42C80228UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA0 *((volatile unsigned int*)(0x42C8022CUL)) -#define bFM3_ETHERNET_MAC0_GAR_PA1 *((volatile unsigned int*)(0x42C80230UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA2 *((volatile unsigned int*)(0x42C80234UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA3 *((volatile unsigned int*)(0x42C80238UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA4 *((volatile unsigned int*)(0x42C8023CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD0 *((volatile unsigned int*)(0x42C80280UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD1 *((volatile unsigned int*)(0x42C80284UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD2 *((volatile unsigned int*)(0x42C80288UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD3 *((volatile unsigned int*)(0x42C8028CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD4 *((volatile unsigned int*)(0x42C80290UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD5 *((volatile unsigned int*)(0x42C80294UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD6 *((volatile unsigned int*)(0x42C80298UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD7 *((volatile unsigned int*)(0x42C8029CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD8 *((volatile unsigned int*)(0x42C802A0UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD9 *((volatile unsigned int*)(0x42C802A4UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD10 *((volatile unsigned int*)(0x42C802A8UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD11 *((volatile unsigned int*)(0x42C802ACUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD12 *((volatile unsigned int*)(0x42C802B0UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD13 *((volatile unsigned int*)(0x42C802B4UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD14 *((volatile unsigned int*)(0x42C802B8UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD15 *((volatile unsigned int*)(0x42C802BCUL)) -#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA *((volatile unsigned int*)(0x42C80300UL)) -#define bFM3_ETHERNET_MAC0_FCR_TFE *((volatile unsigned int*)(0x42C80304UL)) -#define bFM3_ETHERNET_MAC0_FCR_RFE *((volatile unsigned int*)(0x42C80308UL)) -#define bFM3_ETHERNET_MAC0_FCR_UP *((volatile unsigned int*)(0x42C8030CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PLT0 *((volatile unsigned int*)(0x42C80310UL)) -#define bFM3_ETHERNET_MAC0_FCR_PLT1 *((volatile unsigned int*)(0x42C80314UL)) -#define bFM3_ETHERNET_MAC0_FCR_DZPQ *((volatile unsigned int*)(0x42C8031CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT0 *((volatile unsigned int*)(0x42C80340UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT1 *((volatile unsigned int*)(0x42C80344UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT2 *((volatile unsigned int*)(0x42C80348UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT3 *((volatile unsigned int*)(0x42C8034CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT4 *((volatile unsigned int*)(0x42C80350UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT5 *((volatile unsigned int*)(0x42C80354UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT6 *((volatile unsigned int*)(0x42C80358UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT7 *((volatile unsigned int*)(0x42C8035CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT8 *((volatile unsigned int*)(0x42C80360UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT9 *((volatile unsigned int*)(0x42C80364UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT10 *((volatile unsigned int*)(0x42C80368UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT11 *((volatile unsigned int*)(0x42C8036CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT12 *((volatile unsigned int*)(0x42C80370UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT13 *((volatile unsigned int*)(0x42C80374UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT14 *((volatile unsigned int*)(0x42C80378UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT15 *((volatile unsigned int*)(0x42C8037CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL0 *((volatile unsigned int*)(0x42C80380UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL1 *((volatile unsigned int*)(0x42C80384UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL2 *((volatile unsigned int*)(0x42C80388UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL3 *((volatile unsigned int*)(0x42C8038CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL4 *((volatile unsigned int*)(0x42C80390UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL5 *((volatile unsigned int*)(0x42C80394UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL6 *((volatile unsigned int*)(0x42C80398UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL7 *((volatile unsigned int*)(0x42C8039CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL8 *((volatile unsigned int*)(0x42C803A0UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL9 *((volatile unsigned int*)(0x42C803A4UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL10 *((volatile unsigned int*)(0x42C803A8UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL11 *((volatile unsigned int*)(0x42C803ACUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL12 *((volatile unsigned int*)(0x42C803B0UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL13 *((volatile unsigned int*)(0x42C803B4UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL14 *((volatile unsigned int*)(0x42C803B8UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL15 *((volatile unsigned int*)(0x42C803BCUL)) -#define bFM3_ETHERNET_MAC0_VTR_ETV *((volatile unsigned int*)(0x42C803C0UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42C80500UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42C80504UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42C80508UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42C8050CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42C80510UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42C80514UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42C80518UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42C8051CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42C80520UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42C80524UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42C80528UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42C8052CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42C80530UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42C80534UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42C80538UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42C8053CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42C80540UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42C80544UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42C80548UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42C8054CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42C80550UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42C80554UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42C80558UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42C8055CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42C80560UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42C80564UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42C80568UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42C8056CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42C80570UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42C80574UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42C80578UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42C8057CUL)) -#define bFM3_ETHERNET_MAC0_PMTR_PD *((volatile unsigned int*)(0x42C80580UL)) -#define bFM3_ETHERNET_MAC0_PMTR_MPE *((volatile unsigned int*)(0x42C80584UL)) -#define bFM3_ETHERNET_MAC0_PMTR_WFE *((volatile unsigned int*)(0x42C80588UL)) -#define bFM3_ETHERNET_MAC0_PMTR_MPR *((volatile unsigned int*)(0x42C80594UL)) -#define bFM3_ETHERNET_MAC0_PMTR_WPR *((volatile unsigned int*)(0x42C80598UL)) -#define bFM3_ETHERNET_MAC0_PMTR_GU *((volatile unsigned int*)(0x42C805A4UL)) -#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR *((volatile unsigned int*)(0x42C805FCUL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN *((volatile unsigned int*)(0x42C80600UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX *((volatile unsigned int*)(0x42C80604UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN *((volatile unsigned int*)(0x42C80608UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX *((volatile unsigned int*)(0x42C8060CUL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST *((volatile unsigned int*)(0x42C80620UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST *((volatile unsigned int*)(0x42C80624UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN *((volatile unsigned int*)(0x42C80640UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_PLS *((volatile unsigned int*)(0x42C80644UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN *((volatile unsigned int*)(0x42C80648UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA *((volatile unsigned int*)(0x42C8064CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT0 *((volatile unsigned int*)(0x42C80680UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT1 *((volatile unsigned int*)(0x42C80684UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT2 *((volatile unsigned int*)(0x42C80688UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT3 *((volatile unsigned int*)(0x42C8068CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT4 *((volatile unsigned int*)(0x42C80690UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT5 *((volatile unsigned int*)(0x42C80694UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT6 *((volatile unsigned int*)(0x42C80698UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT7 *((volatile unsigned int*)(0x42C8069CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT8 *((volatile unsigned int*)(0x42C806A0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT9 *((volatile unsigned int*)(0x42C806A4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT10 *((volatile unsigned int*)(0x42C806A8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT11 *((volatile unsigned int*)(0x42C806ACUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT12 *((volatile unsigned int*)(0x42C806B0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT13 *((volatile unsigned int*)(0x42C806B4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT14 *((volatile unsigned int*)(0x42C806B8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT15 *((volatile unsigned int*)(0x42C806BCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT0 *((volatile unsigned int*)(0x42C806C0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT1 *((volatile unsigned int*)(0x42C806C4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT2 *((volatile unsigned int*)(0x42C806C8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT3 *((volatile unsigned int*)(0x42C806CCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT4 *((volatile unsigned int*)(0x42C806D0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT5 *((volatile unsigned int*)(0x42C806D4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT6 *((volatile unsigned int*)(0x42C806D8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT7 *((volatile unsigned int*)(0x42C806DCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT8 *((volatile unsigned int*)(0x42C806E0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT9 *((volatile unsigned int*)(0x42C806E4UL)) -#define bFM3_ETHERNET_MAC0_ISR_RGIS *((volatile unsigned int*)(0x42C80700UL)) -#define bFM3_ETHERNET_MAC0_ISR_PIS *((volatile unsigned int*)(0x42C8070CUL)) -#define bFM3_ETHERNET_MAC0_ISR_MIS *((volatile unsigned int*)(0x42C80710UL)) -#define bFM3_ETHERNET_MAC0_ISR_RIS *((volatile unsigned int*)(0x42C80714UL)) -#define bFM3_ETHERNET_MAC0_ISR_TIS *((volatile unsigned int*)(0x42C80718UL)) -#define bFM3_ETHERNET_MAC0_ISR_COIS *((volatile unsigned int*)(0x42C8071CUL)) -#define bFM3_ETHERNET_MAC0_ISR_TSIS *((volatile unsigned int*)(0x42C80724UL)) -#define bFM3_ETHERNET_MAC0_ISR_LPIIS *((volatile unsigned int*)(0x42C80728UL)) -#define bFM3_ETHERNET_MAC0_IMR_RGIM *((volatile unsigned int*)(0x42C80780UL)) -#define bFM3_ETHERNET_MAC0_IMR_PIM *((volatile unsigned int*)(0x42C8078CUL)) -#define bFM3_ETHERNET_MAC0_IMR_TSIM *((volatile unsigned int*)(0x42C80794UL)) -#define bFM3_ETHERNET_MAC0_IMR_LPIIM *((volatile unsigned int*)(0x42C80798UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A32 *((volatile unsigned int*)(0x42C80800UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A33 *((volatile unsigned int*)(0x42C80804UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A34 *((volatile unsigned int*)(0x42C80808UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A35 *((volatile unsigned int*)(0x42C8080CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A36 *((volatile unsigned int*)(0x42C80810UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A37 *((volatile unsigned int*)(0x42C80814UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A38 *((volatile unsigned int*)(0x42C80818UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A39 *((volatile unsigned int*)(0x42C8081CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A40 *((volatile unsigned int*)(0x42C80820UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A41 *((volatile unsigned int*)(0x42C80824UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A42 *((volatile unsigned int*)(0x42C80828UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A43 *((volatile unsigned int*)(0x42C8082CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A44 *((volatile unsigned int*)(0x42C80830UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A45 *((volatile unsigned int*)(0x42C80834UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A46 *((volatile unsigned int*)(0x42C80838UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A47 *((volatile unsigned int*)(0x42C8083CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_MO *((volatile unsigned int*)(0x42C8087CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A0 *((volatile unsigned int*)(0x42C80880UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A1 *((volatile unsigned int*)(0x42C80884UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A2 *((volatile unsigned int*)(0x42C80888UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A3 *((volatile unsigned int*)(0x42C8088CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A4 *((volatile unsigned int*)(0x42C80890UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A5 *((volatile unsigned int*)(0x42C80894UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A6 *((volatile unsigned int*)(0x42C80898UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A7 *((volatile unsigned int*)(0x42C8089CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A8 *((volatile unsigned int*)(0x42C808A0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A9 *((volatile unsigned int*)(0x42C808A4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A10 *((volatile unsigned int*)(0x42C808A8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A11 *((volatile unsigned int*)(0x42C808ACUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A12 *((volatile unsigned int*)(0x42C808B0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A13 *((volatile unsigned int*)(0x42C808B4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A14 *((volatile unsigned int*)(0x42C808B8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A15 *((volatile unsigned int*)(0x42C808BCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A16 *((volatile unsigned int*)(0x42C808C0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A17 *((volatile unsigned int*)(0x42C808C4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A18 *((volatile unsigned int*)(0x42C808C8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A19 *((volatile unsigned int*)(0x42C808CCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A20 *((volatile unsigned int*)(0x42C808D0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A21 *((volatile unsigned int*)(0x42C808D4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A22 *((volatile unsigned int*)(0x42C808D8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A23 *((volatile unsigned int*)(0x42C808DCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A24 *((volatile unsigned int*)(0x42C808E0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A25 *((volatile unsigned int*)(0x42C808E4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A26 *((volatile unsigned int*)(0x42C808E8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A27 *((volatile unsigned int*)(0x42C808ECUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A28 *((volatile unsigned int*)(0x42C808F0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A29 *((volatile unsigned int*)(0x42C808F4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A30 *((volatile unsigned int*)(0x42C808F8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A31 *((volatile unsigned int*)(0x42C808FCUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A32 *((volatile unsigned int*)(0x42C80900UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A33 *((volatile unsigned int*)(0x42C80904UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A34 *((volatile unsigned int*)(0x42C80908UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A35 *((volatile unsigned int*)(0x42C8090CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A36 *((volatile unsigned int*)(0x42C80910UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A37 *((volatile unsigned int*)(0x42C80914UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A38 *((volatile unsigned int*)(0x42C80918UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A39 *((volatile unsigned int*)(0x42C8091CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A40 *((volatile unsigned int*)(0x42C80920UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A41 *((volatile unsigned int*)(0x42C80924UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A42 *((volatile unsigned int*)(0x42C80928UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A43 *((volatile unsigned int*)(0x42C8092CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A44 *((volatile unsigned int*)(0x42C80930UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A45 *((volatile unsigned int*)(0x42C80934UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A46 *((volatile unsigned int*)(0x42C80938UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A47 *((volatile unsigned int*)(0x42C8093CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC0 *((volatile unsigned int*)(0x42C80960UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC1 *((volatile unsigned int*)(0x42C80964UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC2 *((volatile unsigned int*)(0x42C80968UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC3 *((volatile unsigned int*)(0x42C8096CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC4 *((volatile unsigned int*)(0x42C80970UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC5 *((volatile unsigned int*)(0x42C80974UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_SA *((volatile unsigned int*)(0x42C80978UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_AE *((volatile unsigned int*)(0x42C8097CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A0 *((volatile unsigned int*)(0x42C80980UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A1 *((volatile unsigned int*)(0x42C80984UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A2 *((volatile unsigned int*)(0x42C80988UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A3 *((volatile unsigned int*)(0x42C8098CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A4 *((volatile unsigned int*)(0x42C80990UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A5 *((volatile unsigned int*)(0x42C80994UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A6 *((volatile unsigned int*)(0x42C80998UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A7 *((volatile unsigned int*)(0x42C8099CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A8 *((volatile unsigned int*)(0x42C809A0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A9 *((volatile unsigned int*)(0x42C809A4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A10 *((volatile unsigned int*)(0x42C809A8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A11 *((volatile unsigned int*)(0x42C809ACUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A12 *((volatile unsigned int*)(0x42C809B0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A13 *((volatile unsigned int*)(0x42C809B4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A14 *((volatile unsigned int*)(0x42C809B8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A15 *((volatile unsigned int*)(0x42C809BCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A16 *((volatile unsigned int*)(0x42C809C0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A17 *((volatile unsigned int*)(0x42C809C4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A18 *((volatile unsigned int*)(0x42C809C8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A19 *((volatile unsigned int*)(0x42C809CCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A20 *((volatile unsigned int*)(0x42C809D0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A21 *((volatile unsigned int*)(0x42C809D4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A22 *((volatile unsigned int*)(0x42C809D8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A23 *((volatile unsigned int*)(0x42C809DCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A24 *((volatile unsigned int*)(0x42C809E0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A25 *((volatile unsigned int*)(0x42C809E4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A26 *((volatile unsigned int*)(0x42C809E8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A27 *((volatile unsigned int*)(0x42C809ECUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A28 *((volatile unsigned int*)(0x42C809F0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A29 *((volatile unsigned int*)(0x42C809F4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A30 *((volatile unsigned int*)(0x42C809F8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A31 *((volatile unsigned int*)(0x42C809FCUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A32 *((volatile unsigned int*)(0x42C80A00UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A33 *((volatile unsigned int*)(0x42C80A04UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A34 *((volatile unsigned int*)(0x42C80A08UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A35 *((volatile unsigned int*)(0x42C80A0CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A36 *((volatile unsigned int*)(0x42C80A10UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A37 *((volatile unsigned int*)(0x42C80A14UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A38 *((volatile unsigned int*)(0x42C80A18UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A39 *((volatile unsigned int*)(0x42C80A1CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A40 *((volatile unsigned int*)(0x42C80A20UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A41 *((volatile unsigned int*)(0x42C80A24UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A42 *((volatile unsigned int*)(0x42C80A28UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A43 *((volatile unsigned int*)(0x42C80A2CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A44 *((volatile unsigned int*)(0x42C80A30UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A45 *((volatile unsigned int*)(0x42C80A34UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A46 *((volatile unsigned int*)(0x42C80A38UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A47 *((volatile unsigned int*)(0x42C80A3CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC0 *((volatile unsigned int*)(0x42C80A60UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC1 *((volatile unsigned int*)(0x42C80A64UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC2 *((volatile unsigned int*)(0x42C80A68UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC3 *((volatile unsigned int*)(0x42C80A6CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC4 *((volatile unsigned int*)(0x42C80A70UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC5 *((volatile unsigned int*)(0x42C80A74UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_SA *((volatile unsigned int*)(0x42C80A78UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_AE *((volatile unsigned int*)(0x42C80A7CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A0 *((volatile unsigned int*)(0x42C80A80UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A1 *((volatile unsigned int*)(0x42C80A84UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A2 *((volatile unsigned int*)(0x42C80A88UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A3 *((volatile unsigned int*)(0x42C80A8CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A4 *((volatile unsigned int*)(0x42C80A90UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A5 *((volatile unsigned int*)(0x42C80A94UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A6 *((volatile unsigned int*)(0x42C80A98UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A7 *((volatile unsigned int*)(0x42C80A9CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A8 *((volatile unsigned int*)(0x42C80AA0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A9 *((volatile unsigned int*)(0x42C80AA4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A10 *((volatile unsigned int*)(0x42C80AA8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A11 *((volatile unsigned int*)(0x42C80AACUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A12 *((volatile unsigned int*)(0x42C80AB0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A13 *((volatile unsigned int*)(0x42C80AB4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A14 *((volatile unsigned int*)(0x42C80AB8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A15 *((volatile unsigned int*)(0x42C80ABCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A16 *((volatile unsigned int*)(0x42C80AC0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A17 *((volatile unsigned int*)(0x42C80AC4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A18 *((volatile unsigned int*)(0x42C80AC8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A19 *((volatile unsigned int*)(0x42C80ACCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A20 *((volatile unsigned int*)(0x42C80AD0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A21 *((volatile unsigned int*)(0x42C80AD4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A22 *((volatile unsigned int*)(0x42C80AD8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A23 *((volatile unsigned int*)(0x42C80ADCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A24 *((volatile unsigned int*)(0x42C80AE0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A25 *((volatile unsigned int*)(0x42C80AE4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A26 *((volatile unsigned int*)(0x42C80AE8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A27 *((volatile unsigned int*)(0x42C80AECUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A28 *((volatile unsigned int*)(0x42C80AF0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A29 *((volatile unsigned int*)(0x42C80AF4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A30 *((volatile unsigned int*)(0x42C80AF8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A31 *((volatile unsigned int*)(0x42C80AFCUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A32 *((volatile unsigned int*)(0x42C80B00UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A33 *((volatile unsigned int*)(0x42C80B04UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A34 *((volatile unsigned int*)(0x42C80B08UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A35 *((volatile unsigned int*)(0x42C80B0CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A36 *((volatile unsigned int*)(0x42C80B10UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A37 *((volatile unsigned int*)(0x42C80B14UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A38 *((volatile unsigned int*)(0x42C80B18UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A39 *((volatile unsigned int*)(0x42C80B1CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A40 *((volatile unsigned int*)(0x42C80B20UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A41 *((volatile unsigned int*)(0x42C80B24UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A42 *((volatile unsigned int*)(0x42C80B28UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A43 *((volatile unsigned int*)(0x42C80B2CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A44 *((volatile unsigned int*)(0x42C80B30UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A45 *((volatile unsigned int*)(0x42C80B34UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A46 *((volatile unsigned int*)(0x42C80B38UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A47 *((volatile unsigned int*)(0x42C80B3CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC0 *((volatile unsigned int*)(0x42C80B60UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC1 *((volatile unsigned int*)(0x42C80B64UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC2 *((volatile unsigned int*)(0x42C80B68UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC3 *((volatile unsigned int*)(0x42C80B6CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC4 *((volatile unsigned int*)(0x42C80B70UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC5 *((volatile unsigned int*)(0x42C80B74UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_SA *((volatile unsigned int*)(0x42C80B78UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_AE *((volatile unsigned int*)(0x42C80B7CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A0 *((volatile unsigned int*)(0x42C80B80UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A1 *((volatile unsigned int*)(0x42C80B84UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A2 *((volatile unsigned int*)(0x42C80B88UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A3 *((volatile unsigned int*)(0x42C80B8CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A4 *((volatile unsigned int*)(0x42C80B90UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A5 *((volatile unsigned int*)(0x42C80B94UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A6 *((volatile unsigned int*)(0x42C80B98UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A7 *((volatile unsigned int*)(0x42C80B9CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A8 *((volatile unsigned int*)(0x42C80BA0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A9 *((volatile unsigned int*)(0x42C80BA4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A10 *((volatile unsigned int*)(0x42C80BA8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A11 *((volatile unsigned int*)(0x42C80BACUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A12 *((volatile unsigned int*)(0x42C80BB0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A13 *((volatile unsigned int*)(0x42C80BB4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A14 *((volatile unsigned int*)(0x42C80BB8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A15 *((volatile unsigned int*)(0x42C80BBCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A16 *((volatile unsigned int*)(0x42C80BC0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A17 *((volatile unsigned int*)(0x42C80BC4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A18 *((volatile unsigned int*)(0x42C80BC8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A19 *((volatile unsigned int*)(0x42C80BCCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A20 *((volatile unsigned int*)(0x42C80BD0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A21 *((volatile unsigned int*)(0x42C80BD4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A22 *((volatile unsigned int*)(0x42C80BD8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A23 *((volatile unsigned int*)(0x42C80BDCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A24 *((volatile unsigned int*)(0x42C80BE0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A25 *((volatile unsigned int*)(0x42C80BE4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A26 *((volatile unsigned int*)(0x42C80BE8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A27 *((volatile unsigned int*)(0x42C80BECUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A28 *((volatile unsigned int*)(0x42C80BF0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A29 *((volatile unsigned int*)(0x42C80BF4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A30 *((volatile unsigned int*)(0x42C80BF8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A31 *((volatile unsigned int*)(0x42C80BFCUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A32 *((volatile unsigned int*)(0x42C80C00UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A33 *((volatile unsigned int*)(0x42C80C04UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A34 *((volatile unsigned int*)(0x42C80C08UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A35 *((volatile unsigned int*)(0x42C80C0CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A36 *((volatile unsigned int*)(0x42C80C10UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A37 *((volatile unsigned int*)(0x42C80C14UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A38 *((volatile unsigned int*)(0x42C80C18UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A39 *((volatile unsigned int*)(0x42C80C1CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A40 *((volatile unsigned int*)(0x42C80C20UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A41 *((volatile unsigned int*)(0x42C80C24UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A42 *((volatile unsigned int*)(0x42C80C28UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A43 *((volatile unsigned int*)(0x42C80C2CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A44 *((volatile unsigned int*)(0x42C80C30UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A45 *((volatile unsigned int*)(0x42C80C34UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A46 *((volatile unsigned int*)(0x42C80C38UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A47 *((volatile unsigned int*)(0x42C80C3CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC0 *((volatile unsigned int*)(0x42C80C60UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC1 *((volatile unsigned int*)(0x42C80C64UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC2 *((volatile unsigned int*)(0x42C80C68UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC3 *((volatile unsigned int*)(0x42C80C6CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC4 *((volatile unsigned int*)(0x42C80C70UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC5 *((volatile unsigned int*)(0x42C80C74UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_SA *((volatile unsigned int*)(0x42C80C78UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_AE *((volatile unsigned int*)(0x42C80C7CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A0 *((volatile unsigned int*)(0x42C80C80UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A1 *((volatile unsigned int*)(0x42C80C84UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A2 *((volatile unsigned int*)(0x42C80C88UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A3 *((volatile unsigned int*)(0x42C80C8CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A4 *((volatile unsigned int*)(0x42C80C90UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A5 *((volatile unsigned int*)(0x42C80C94UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A6 *((volatile unsigned int*)(0x42C80C98UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A7 *((volatile unsigned int*)(0x42C80C9CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A8 *((volatile unsigned int*)(0x42C80CA0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A9 *((volatile unsigned int*)(0x42C80CA4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A10 *((volatile unsigned int*)(0x42C80CA8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A11 *((volatile unsigned int*)(0x42C80CACUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A12 *((volatile unsigned int*)(0x42C80CB0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A13 *((volatile unsigned int*)(0x42C80CB4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A14 *((volatile unsigned int*)(0x42C80CB8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A15 *((volatile unsigned int*)(0x42C80CBCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A16 *((volatile unsigned int*)(0x42C80CC0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A17 *((volatile unsigned int*)(0x42C80CC4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A18 *((volatile unsigned int*)(0x42C80CC8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A19 *((volatile unsigned int*)(0x42C80CCCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A20 *((volatile unsigned int*)(0x42C80CD0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A21 *((volatile unsigned int*)(0x42C80CD4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A22 *((volatile unsigned int*)(0x42C80CD8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A23 *((volatile unsigned int*)(0x42C80CDCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A24 *((volatile unsigned int*)(0x42C80CE0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A25 *((volatile unsigned int*)(0x42C80CE4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A26 *((volatile unsigned int*)(0x42C80CE8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A27 *((volatile unsigned int*)(0x42C80CECUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A28 *((volatile unsigned int*)(0x42C80CF0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A29 *((volatile unsigned int*)(0x42C80CF4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A30 *((volatile unsigned int*)(0x42C80CF8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A31 *((volatile unsigned int*)(0x42C80CFCUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A32 *((volatile unsigned int*)(0x42C80D00UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A33 *((volatile unsigned int*)(0x42C80D04UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A34 *((volatile unsigned int*)(0x42C80D08UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A35 *((volatile unsigned int*)(0x42C80D0CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A36 *((volatile unsigned int*)(0x42C80D10UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A37 *((volatile unsigned int*)(0x42C80D14UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A38 *((volatile unsigned int*)(0x42C80D18UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A39 *((volatile unsigned int*)(0x42C80D1CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A40 *((volatile unsigned int*)(0x42C80D20UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A41 *((volatile unsigned int*)(0x42C80D24UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A42 *((volatile unsigned int*)(0x42C80D28UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A43 *((volatile unsigned int*)(0x42C80D2CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A44 *((volatile unsigned int*)(0x42C80D30UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A45 *((volatile unsigned int*)(0x42C80D34UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A46 *((volatile unsigned int*)(0x42C80D38UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A47 *((volatile unsigned int*)(0x42C80D3CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC0 *((volatile unsigned int*)(0x42C80D60UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC1 *((volatile unsigned int*)(0x42C80D64UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC2 *((volatile unsigned int*)(0x42C80D68UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC3 *((volatile unsigned int*)(0x42C80D6CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC4 *((volatile unsigned int*)(0x42C80D70UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC5 *((volatile unsigned int*)(0x42C80D74UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_SA *((volatile unsigned int*)(0x42C80D78UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_AE *((volatile unsigned int*)(0x42C80D7CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A0 *((volatile unsigned int*)(0x42C80D80UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A1 *((volatile unsigned int*)(0x42C80D84UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A2 *((volatile unsigned int*)(0x42C80D88UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A3 *((volatile unsigned int*)(0x42C80D8CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A4 *((volatile unsigned int*)(0x42C80D90UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A5 *((volatile unsigned int*)(0x42C80D94UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A6 *((volatile unsigned int*)(0x42C80D98UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A7 *((volatile unsigned int*)(0x42C80D9CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A8 *((volatile unsigned int*)(0x42C80DA0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A9 *((volatile unsigned int*)(0x42C80DA4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A10 *((volatile unsigned int*)(0x42C80DA8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A11 *((volatile unsigned int*)(0x42C80DACUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A12 *((volatile unsigned int*)(0x42C80DB0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A13 *((volatile unsigned int*)(0x42C80DB4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A14 *((volatile unsigned int*)(0x42C80DB8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A15 *((volatile unsigned int*)(0x42C80DBCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A16 *((volatile unsigned int*)(0x42C80DC0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A17 *((volatile unsigned int*)(0x42C80DC4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A18 *((volatile unsigned int*)(0x42C80DC8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A19 *((volatile unsigned int*)(0x42C80DCCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A20 *((volatile unsigned int*)(0x42C80DD0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A21 *((volatile unsigned int*)(0x42C80DD4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A22 *((volatile unsigned int*)(0x42C80DD8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A23 *((volatile unsigned int*)(0x42C80DDCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A24 *((volatile unsigned int*)(0x42C80DE0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A25 *((volatile unsigned int*)(0x42C80DE4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A26 *((volatile unsigned int*)(0x42C80DE8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A27 *((volatile unsigned int*)(0x42C80DECUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A28 *((volatile unsigned int*)(0x42C80DF0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A29 *((volatile unsigned int*)(0x42C80DF4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A30 *((volatile unsigned int*)(0x42C80DF8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A31 *((volatile unsigned int*)(0x42C80DFCUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A32 *((volatile unsigned int*)(0x42C80E00UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A33 *((volatile unsigned int*)(0x42C80E04UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A34 *((volatile unsigned int*)(0x42C80E08UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A35 *((volatile unsigned int*)(0x42C80E0CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A36 *((volatile unsigned int*)(0x42C80E10UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A37 *((volatile unsigned int*)(0x42C80E14UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A38 *((volatile unsigned int*)(0x42C80E18UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A39 *((volatile unsigned int*)(0x42C80E1CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A40 *((volatile unsigned int*)(0x42C80E20UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A41 *((volatile unsigned int*)(0x42C80E24UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A42 *((volatile unsigned int*)(0x42C80E28UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A43 *((volatile unsigned int*)(0x42C80E2CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A44 *((volatile unsigned int*)(0x42C80E30UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A45 *((volatile unsigned int*)(0x42C80E34UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A46 *((volatile unsigned int*)(0x42C80E38UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A47 *((volatile unsigned int*)(0x42C80E3CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC0 *((volatile unsigned int*)(0x42C80E60UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC1 *((volatile unsigned int*)(0x42C80E64UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC2 *((volatile unsigned int*)(0x42C80E68UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC3 *((volatile unsigned int*)(0x42C80E6CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC4 *((volatile unsigned int*)(0x42C80E70UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC5 *((volatile unsigned int*)(0x42C80E74UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_SA *((volatile unsigned int*)(0x42C80E78UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_AE *((volatile unsigned int*)(0x42C80E7CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A0 *((volatile unsigned int*)(0x42C80E80UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A1 *((volatile unsigned int*)(0x42C80E84UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A2 *((volatile unsigned int*)(0x42C80E88UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A3 *((volatile unsigned int*)(0x42C80E8CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A4 *((volatile unsigned int*)(0x42C80E90UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A5 *((volatile unsigned int*)(0x42C80E94UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A6 *((volatile unsigned int*)(0x42C80E98UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A7 *((volatile unsigned int*)(0x42C80E9CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A8 *((volatile unsigned int*)(0x42C80EA0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A9 *((volatile unsigned int*)(0x42C80EA4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A10 *((volatile unsigned int*)(0x42C80EA8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A11 *((volatile unsigned int*)(0x42C80EACUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A12 *((volatile unsigned int*)(0x42C80EB0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A13 *((volatile unsigned int*)(0x42C80EB4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A14 *((volatile unsigned int*)(0x42C80EB8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A15 *((volatile unsigned int*)(0x42C80EBCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A16 *((volatile unsigned int*)(0x42C80EC0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A17 *((volatile unsigned int*)(0x42C80EC4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A18 *((volatile unsigned int*)(0x42C80EC8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A19 *((volatile unsigned int*)(0x42C80ECCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A20 *((volatile unsigned int*)(0x42C80ED0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A21 *((volatile unsigned int*)(0x42C80ED4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A22 *((volatile unsigned int*)(0x42C80ED8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A23 *((volatile unsigned int*)(0x42C80EDCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A24 *((volatile unsigned int*)(0x42C80EE0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A25 *((volatile unsigned int*)(0x42C80EE4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A26 *((volatile unsigned int*)(0x42C80EE8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A27 *((volatile unsigned int*)(0x42C80EECUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A28 *((volatile unsigned int*)(0x42C80EF0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A29 *((volatile unsigned int*)(0x42C80EF4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A30 *((volatile unsigned int*)(0x42C80EF8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A31 *((volatile unsigned int*)(0x42C80EFCUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A32 *((volatile unsigned int*)(0x42C80F00UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A33 *((volatile unsigned int*)(0x42C80F04UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A34 *((volatile unsigned int*)(0x42C80F08UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A35 *((volatile unsigned int*)(0x42C80F0CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A36 *((volatile unsigned int*)(0x42C80F10UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A37 *((volatile unsigned int*)(0x42C80F14UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A38 *((volatile unsigned int*)(0x42C80F18UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A39 *((volatile unsigned int*)(0x42C80F1CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A40 *((volatile unsigned int*)(0x42C80F20UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A41 *((volatile unsigned int*)(0x42C80F24UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A42 *((volatile unsigned int*)(0x42C80F28UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A43 *((volatile unsigned int*)(0x42C80F2CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A44 *((volatile unsigned int*)(0x42C80F30UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A45 *((volatile unsigned int*)(0x42C80F34UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A46 *((volatile unsigned int*)(0x42C80F38UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A47 *((volatile unsigned int*)(0x42C80F3CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC0 *((volatile unsigned int*)(0x42C80F60UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC1 *((volatile unsigned int*)(0x42C80F64UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC2 *((volatile unsigned int*)(0x42C80F68UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC3 *((volatile unsigned int*)(0x42C80F6CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC4 *((volatile unsigned int*)(0x42C80F70UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC5 *((volatile unsigned int*)(0x42C80F74UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_SA *((volatile unsigned int*)(0x42C80F78UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_AE *((volatile unsigned int*)(0x42C80F7CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A0 *((volatile unsigned int*)(0x42C80F80UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A1 *((volatile unsigned int*)(0x42C80F84UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A2 *((volatile unsigned int*)(0x42C80F88UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A3 *((volatile unsigned int*)(0x42C80F8CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A4 *((volatile unsigned int*)(0x42C80F90UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A5 *((volatile unsigned int*)(0x42C80F94UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A6 *((volatile unsigned int*)(0x42C80F98UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A7 *((volatile unsigned int*)(0x42C80F9CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A8 *((volatile unsigned int*)(0x42C80FA0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A9 *((volatile unsigned int*)(0x42C80FA4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A10 *((volatile unsigned int*)(0x42C80FA8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A11 *((volatile unsigned int*)(0x42C80FACUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A12 *((volatile unsigned int*)(0x42C80FB0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A13 *((volatile unsigned int*)(0x42C80FB4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A14 *((volatile unsigned int*)(0x42C80FB8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A15 *((volatile unsigned int*)(0x42C80FBCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A16 *((volatile unsigned int*)(0x42C80FC0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A17 *((volatile unsigned int*)(0x42C80FC4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A18 *((volatile unsigned int*)(0x42C80FC8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A19 *((volatile unsigned int*)(0x42C80FCCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A20 *((volatile unsigned int*)(0x42C80FD0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A21 *((volatile unsigned int*)(0x42C80FD4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A22 *((volatile unsigned int*)(0x42C80FD8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A23 *((volatile unsigned int*)(0x42C80FDCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A24 *((volatile unsigned int*)(0x42C80FE0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A25 *((volatile unsigned int*)(0x42C80FE4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A26 *((volatile unsigned int*)(0x42C80FE8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A27 *((volatile unsigned int*)(0x42C80FECUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A28 *((volatile unsigned int*)(0x42C80FF0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A29 *((volatile unsigned int*)(0x42C80FF4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A30 *((volatile unsigned int*)(0x42C80FF8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A31 *((volatile unsigned int*)(0x42C80FFCUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A32 *((volatile unsigned int*)(0x42C81000UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A33 *((volatile unsigned int*)(0x42C81004UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A34 *((volatile unsigned int*)(0x42C81008UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A35 *((volatile unsigned int*)(0x42C8100CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A36 *((volatile unsigned int*)(0x42C81010UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A37 *((volatile unsigned int*)(0x42C81014UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A38 *((volatile unsigned int*)(0x42C81018UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A39 *((volatile unsigned int*)(0x42C8101CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A40 *((volatile unsigned int*)(0x42C81020UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A41 *((volatile unsigned int*)(0x42C81024UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A42 *((volatile unsigned int*)(0x42C81028UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A43 *((volatile unsigned int*)(0x42C8102CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A44 *((volatile unsigned int*)(0x42C81030UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A45 *((volatile unsigned int*)(0x42C81034UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A46 *((volatile unsigned int*)(0x42C81038UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A47 *((volatile unsigned int*)(0x42C8103CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC0 *((volatile unsigned int*)(0x42C81060UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC1 *((volatile unsigned int*)(0x42C81064UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC2 *((volatile unsigned int*)(0x42C81068UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC3 *((volatile unsigned int*)(0x42C8106CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC4 *((volatile unsigned int*)(0x42C81070UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC5 *((volatile unsigned int*)(0x42C81074UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_SA *((volatile unsigned int*)(0x42C81078UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_AE *((volatile unsigned int*)(0x42C8107CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A0 *((volatile unsigned int*)(0x42C81080UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A1 *((volatile unsigned int*)(0x42C81084UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A2 *((volatile unsigned int*)(0x42C81088UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A3 *((volatile unsigned int*)(0x42C8108CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A4 *((volatile unsigned int*)(0x42C81090UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A5 *((volatile unsigned int*)(0x42C81094UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A6 *((volatile unsigned int*)(0x42C81098UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A7 *((volatile unsigned int*)(0x42C8109CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A8 *((volatile unsigned int*)(0x42C810A0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A9 *((volatile unsigned int*)(0x42C810A4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A10 *((volatile unsigned int*)(0x42C810A8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A11 *((volatile unsigned int*)(0x42C810ACUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A12 *((volatile unsigned int*)(0x42C810B0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A13 *((volatile unsigned int*)(0x42C810B4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A14 *((volatile unsigned int*)(0x42C810B8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A15 *((volatile unsigned int*)(0x42C810BCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A16 *((volatile unsigned int*)(0x42C810C0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A17 *((volatile unsigned int*)(0x42C810C4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A18 *((volatile unsigned int*)(0x42C810C8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A19 *((volatile unsigned int*)(0x42C810CCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A20 *((volatile unsigned int*)(0x42C810D0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A21 *((volatile unsigned int*)(0x42C810D4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A22 *((volatile unsigned int*)(0x42C810D8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A23 *((volatile unsigned int*)(0x42C810DCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A24 *((volatile unsigned int*)(0x42C810E0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A25 *((volatile unsigned int*)(0x42C810E4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A26 *((volatile unsigned int*)(0x42C810E8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A27 *((volatile unsigned int*)(0x42C810ECUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A28 *((volatile unsigned int*)(0x42C810F0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A29 *((volatile unsigned int*)(0x42C810F4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A30 *((volatile unsigned int*)(0x42C810F8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A31 *((volatile unsigned int*)(0x42C810FCUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A32 *((volatile unsigned int*)(0x42C81100UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A33 *((volatile unsigned int*)(0x42C81104UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A34 *((volatile unsigned int*)(0x42C81108UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A35 *((volatile unsigned int*)(0x42C8110CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A36 *((volatile unsigned int*)(0x42C81110UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A37 *((volatile unsigned int*)(0x42C81114UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A38 *((volatile unsigned int*)(0x42C81118UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A39 *((volatile unsigned int*)(0x42C8111CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A40 *((volatile unsigned int*)(0x42C81120UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A41 *((volatile unsigned int*)(0x42C81124UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A42 *((volatile unsigned int*)(0x42C81128UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A43 *((volatile unsigned int*)(0x42C8112CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A44 *((volatile unsigned int*)(0x42C81130UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A45 *((volatile unsigned int*)(0x42C81134UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A46 *((volatile unsigned int*)(0x42C81138UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A47 *((volatile unsigned int*)(0x42C8113CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC0 *((volatile unsigned int*)(0x42C81160UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC1 *((volatile unsigned int*)(0x42C81164UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC2 *((volatile unsigned int*)(0x42C81168UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC3 *((volatile unsigned int*)(0x42C8116CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC4 *((volatile unsigned int*)(0x42C81170UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC5 *((volatile unsigned int*)(0x42C81174UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_SA *((volatile unsigned int*)(0x42C81178UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_AE *((volatile unsigned int*)(0x42C8117CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A0 *((volatile unsigned int*)(0x42C81180UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A1 *((volatile unsigned int*)(0x42C81184UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A2 *((volatile unsigned int*)(0x42C81188UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A3 *((volatile unsigned int*)(0x42C8118CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A4 *((volatile unsigned int*)(0x42C81190UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A5 *((volatile unsigned int*)(0x42C81194UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A6 *((volatile unsigned int*)(0x42C81198UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A7 *((volatile unsigned int*)(0x42C8119CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A8 *((volatile unsigned int*)(0x42C811A0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A9 *((volatile unsigned int*)(0x42C811A4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A10 *((volatile unsigned int*)(0x42C811A8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A11 *((volatile unsigned int*)(0x42C811ACUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A12 *((volatile unsigned int*)(0x42C811B0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A13 *((volatile unsigned int*)(0x42C811B4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A14 *((volatile unsigned int*)(0x42C811B8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A15 *((volatile unsigned int*)(0x42C811BCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A16 *((volatile unsigned int*)(0x42C811C0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A17 *((volatile unsigned int*)(0x42C811C4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A18 *((volatile unsigned int*)(0x42C811C8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A19 *((volatile unsigned int*)(0x42C811CCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A20 *((volatile unsigned int*)(0x42C811D0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A21 *((volatile unsigned int*)(0x42C811D4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A22 *((volatile unsigned int*)(0x42C811D8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A23 *((volatile unsigned int*)(0x42C811DCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A24 *((volatile unsigned int*)(0x42C811E0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A25 *((volatile unsigned int*)(0x42C811E4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A26 *((volatile unsigned int*)(0x42C811E8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A27 *((volatile unsigned int*)(0x42C811ECUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A28 *((volatile unsigned int*)(0x42C811F0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A29 *((volatile unsigned int*)(0x42C811F4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A30 *((volatile unsigned int*)(0x42C811F8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A31 *((volatile unsigned int*)(0x42C811FCUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A32 *((volatile unsigned int*)(0x42C81200UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A33 *((volatile unsigned int*)(0x42C81204UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A34 *((volatile unsigned int*)(0x42C81208UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A35 *((volatile unsigned int*)(0x42C8120CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A36 *((volatile unsigned int*)(0x42C81210UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A37 *((volatile unsigned int*)(0x42C81214UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A38 *((volatile unsigned int*)(0x42C81218UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A39 *((volatile unsigned int*)(0x42C8121CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A40 *((volatile unsigned int*)(0x42C81220UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A41 *((volatile unsigned int*)(0x42C81224UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A42 *((volatile unsigned int*)(0x42C81228UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A43 *((volatile unsigned int*)(0x42C8122CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A44 *((volatile unsigned int*)(0x42C81230UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A45 *((volatile unsigned int*)(0x42C81234UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A46 *((volatile unsigned int*)(0x42C81238UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A47 *((volatile unsigned int*)(0x42C8123CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC0 *((volatile unsigned int*)(0x42C81260UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC1 *((volatile unsigned int*)(0x42C81264UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC2 *((volatile unsigned int*)(0x42C81268UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC3 *((volatile unsigned int*)(0x42C8126CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC4 *((volatile unsigned int*)(0x42C81270UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC5 *((volatile unsigned int*)(0x42C81274UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_SA *((volatile unsigned int*)(0x42C81278UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_AE *((volatile unsigned int*)(0x42C8127CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A0 *((volatile unsigned int*)(0x42C81280UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A1 *((volatile unsigned int*)(0x42C81284UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A2 *((volatile unsigned int*)(0x42C81288UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A3 *((volatile unsigned int*)(0x42C8128CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A4 *((volatile unsigned int*)(0x42C81290UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A5 *((volatile unsigned int*)(0x42C81294UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A6 *((volatile unsigned int*)(0x42C81298UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A7 *((volatile unsigned int*)(0x42C8129CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A8 *((volatile unsigned int*)(0x42C812A0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A9 *((volatile unsigned int*)(0x42C812A4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A10 *((volatile unsigned int*)(0x42C812A8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A11 *((volatile unsigned int*)(0x42C812ACUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A12 *((volatile unsigned int*)(0x42C812B0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A13 *((volatile unsigned int*)(0x42C812B4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A14 *((volatile unsigned int*)(0x42C812B8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A15 *((volatile unsigned int*)(0x42C812BCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A16 *((volatile unsigned int*)(0x42C812C0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A17 *((volatile unsigned int*)(0x42C812C4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A18 *((volatile unsigned int*)(0x42C812C8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A19 *((volatile unsigned int*)(0x42C812CCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A20 *((volatile unsigned int*)(0x42C812D0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A21 *((volatile unsigned int*)(0x42C812D4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A22 *((volatile unsigned int*)(0x42C812D8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A23 *((volatile unsigned int*)(0x42C812DCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A24 *((volatile unsigned int*)(0x42C812E0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A25 *((volatile unsigned int*)(0x42C812E4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A26 *((volatile unsigned int*)(0x42C812E8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A27 *((volatile unsigned int*)(0x42C812ECUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A28 *((volatile unsigned int*)(0x42C812F0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A29 *((volatile unsigned int*)(0x42C812F4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A30 *((volatile unsigned int*)(0x42C812F8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A31 *((volatile unsigned int*)(0x42C812FCUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A32 *((volatile unsigned int*)(0x42C81300UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A33 *((volatile unsigned int*)(0x42C81304UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A34 *((volatile unsigned int*)(0x42C81308UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A35 *((volatile unsigned int*)(0x42C8130CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A36 *((volatile unsigned int*)(0x42C81310UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A37 *((volatile unsigned int*)(0x42C81314UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A38 *((volatile unsigned int*)(0x42C81318UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A39 *((volatile unsigned int*)(0x42C8131CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A40 *((volatile unsigned int*)(0x42C81320UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A41 *((volatile unsigned int*)(0x42C81324UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A42 *((volatile unsigned int*)(0x42C81328UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A43 *((volatile unsigned int*)(0x42C8132CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A44 *((volatile unsigned int*)(0x42C81330UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A45 *((volatile unsigned int*)(0x42C81334UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A46 *((volatile unsigned int*)(0x42C81338UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A47 *((volatile unsigned int*)(0x42C8133CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC0 *((volatile unsigned int*)(0x42C81360UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC1 *((volatile unsigned int*)(0x42C81364UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC2 *((volatile unsigned int*)(0x42C81368UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC3 *((volatile unsigned int*)(0x42C8136CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC4 *((volatile unsigned int*)(0x42C81370UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC5 *((volatile unsigned int*)(0x42C81374UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_SA *((volatile unsigned int*)(0x42C81378UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_AE *((volatile unsigned int*)(0x42C8137CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A0 *((volatile unsigned int*)(0x42C81380UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A1 *((volatile unsigned int*)(0x42C81384UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A2 *((volatile unsigned int*)(0x42C81388UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A3 *((volatile unsigned int*)(0x42C8138CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A4 *((volatile unsigned int*)(0x42C81390UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A5 *((volatile unsigned int*)(0x42C81394UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A6 *((volatile unsigned int*)(0x42C81398UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A7 *((volatile unsigned int*)(0x42C8139CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A8 *((volatile unsigned int*)(0x42C813A0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A9 *((volatile unsigned int*)(0x42C813A4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A10 *((volatile unsigned int*)(0x42C813A8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A11 *((volatile unsigned int*)(0x42C813ACUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A12 *((volatile unsigned int*)(0x42C813B0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A13 *((volatile unsigned int*)(0x42C813B4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A14 *((volatile unsigned int*)(0x42C813B8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A15 *((volatile unsigned int*)(0x42C813BCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A16 *((volatile unsigned int*)(0x42C813C0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A17 *((volatile unsigned int*)(0x42C813C4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A18 *((volatile unsigned int*)(0x42C813C8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A19 *((volatile unsigned int*)(0x42C813CCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A20 *((volatile unsigned int*)(0x42C813D0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A21 *((volatile unsigned int*)(0x42C813D4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A22 *((volatile unsigned int*)(0x42C813D8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A23 *((volatile unsigned int*)(0x42C813DCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A24 *((volatile unsigned int*)(0x42C813E0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A25 *((volatile unsigned int*)(0x42C813E4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A26 *((volatile unsigned int*)(0x42C813E8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A27 *((volatile unsigned int*)(0x42C813ECUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A28 *((volatile unsigned int*)(0x42C813F0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A29 *((volatile unsigned int*)(0x42C813F4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A30 *((volatile unsigned int*)(0x42C813F8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A31 *((volatile unsigned int*)(0x42C813FCUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A32 *((volatile unsigned int*)(0x42C81400UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A33 *((volatile unsigned int*)(0x42C81404UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A34 *((volatile unsigned int*)(0x42C81408UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A35 *((volatile unsigned int*)(0x42C8140CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A36 *((volatile unsigned int*)(0x42C81410UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A37 *((volatile unsigned int*)(0x42C81414UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A38 *((volatile unsigned int*)(0x42C81418UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A39 *((volatile unsigned int*)(0x42C8141CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A40 *((volatile unsigned int*)(0x42C81420UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A41 *((volatile unsigned int*)(0x42C81424UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A42 *((volatile unsigned int*)(0x42C81428UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A43 *((volatile unsigned int*)(0x42C8142CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A44 *((volatile unsigned int*)(0x42C81430UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A45 *((volatile unsigned int*)(0x42C81434UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A46 *((volatile unsigned int*)(0x42C81438UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A47 *((volatile unsigned int*)(0x42C8143CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC0 *((volatile unsigned int*)(0x42C81460UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC1 *((volatile unsigned int*)(0x42C81464UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC2 *((volatile unsigned int*)(0x42C81468UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC3 *((volatile unsigned int*)(0x42C8146CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC4 *((volatile unsigned int*)(0x42C81470UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC5 *((volatile unsigned int*)(0x42C81474UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_SA *((volatile unsigned int*)(0x42C81478UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_AE *((volatile unsigned int*)(0x42C8147CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A0 *((volatile unsigned int*)(0x42C81480UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A1 *((volatile unsigned int*)(0x42C81484UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A2 *((volatile unsigned int*)(0x42C81488UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A3 *((volatile unsigned int*)(0x42C8148CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A4 *((volatile unsigned int*)(0x42C81490UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A5 *((volatile unsigned int*)(0x42C81494UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A6 *((volatile unsigned int*)(0x42C81498UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A7 *((volatile unsigned int*)(0x42C8149CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A8 *((volatile unsigned int*)(0x42C814A0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A9 *((volatile unsigned int*)(0x42C814A4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A10 *((volatile unsigned int*)(0x42C814A8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A11 *((volatile unsigned int*)(0x42C814ACUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A12 *((volatile unsigned int*)(0x42C814B0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A13 *((volatile unsigned int*)(0x42C814B4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A14 *((volatile unsigned int*)(0x42C814B8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A15 *((volatile unsigned int*)(0x42C814BCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A16 *((volatile unsigned int*)(0x42C814C0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A17 *((volatile unsigned int*)(0x42C814C4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A18 *((volatile unsigned int*)(0x42C814C8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A19 *((volatile unsigned int*)(0x42C814CCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A20 *((volatile unsigned int*)(0x42C814D0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A21 *((volatile unsigned int*)(0x42C814D4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A22 *((volatile unsigned int*)(0x42C814D8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A23 *((volatile unsigned int*)(0x42C814DCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A24 *((volatile unsigned int*)(0x42C814E0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A25 *((volatile unsigned int*)(0x42C814E4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A26 *((volatile unsigned int*)(0x42C814E8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A27 *((volatile unsigned int*)(0x42C814ECUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A28 *((volatile unsigned int*)(0x42C814F0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A29 *((volatile unsigned int*)(0x42C814F4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A30 *((volatile unsigned int*)(0x42C814F8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A31 *((volatile unsigned int*)(0x42C814FCUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A32 *((volatile unsigned int*)(0x42C81500UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A33 *((volatile unsigned int*)(0x42C81504UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A34 *((volatile unsigned int*)(0x42C81508UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A35 *((volatile unsigned int*)(0x42C8150CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A36 *((volatile unsigned int*)(0x42C81510UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A37 *((volatile unsigned int*)(0x42C81514UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A38 *((volatile unsigned int*)(0x42C81518UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A39 *((volatile unsigned int*)(0x42C8151CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A40 *((volatile unsigned int*)(0x42C81520UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A41 *((volatile unsigned int*)(0x42C81524UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A42 *((volatile unsigned int*)(0x42C81528UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A43 *((volatile unsigned int*)(0x42C8152CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A44 *((volatile unsigned int*)(0x42C81530UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A45 *((volatile unsigned int*)(0x42C81534UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A46 *((volatile unsigned int*)(0x42C81538UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A47 *((volatile unsigned int*)(0x42C8153CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC0 *((volatile unsigned int*)(0x42C81560UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC1 *((volatile unsigned int*)(0x42C81564UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC2 *((volatile unsigned int*)(0x42C81568UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC3 *((volatile unsigned int*)(0x42C8156CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC4 *((volatile unsigned int*)(0x42C81570UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC5 *((volatile unsigned int*)(0x42C81574UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_SA *((volatile unsigned int*)(0x42C81578UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_AE *((volatile unsigned int*)(0x42C8157CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A0 *((volatile unsigned int*)(0x42C81580UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A1 *((volatile unsigned int*)(0x42C81584UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A2 *((volatile unsigned int*)(0x42C81588UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A3 *((volatile unsigned int*)(0x42C8158CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A4 *((volatile unsigned int*)(0x42C81590UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A5 *((volatile unsigned int*)(0x42C81594UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A6 *((volatile unsigned int*)(0x42C81598UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A7 *((volatile unsigned int*)(0x42C8159CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A8 *((volatile unsigned int*)(0x42C815A0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A9 *((volatile unsigned int*)(0x42C815A4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A10 *((volatile unsigned int*)(0x42C815A8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A11 *((volatile unsigned int*)(0x42C815ACUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A12 *((volatile unsigned int*)(0x42C815B0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A13 *((volatile unsigned int*)(0x42C815B4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A14 *((volatile unsigned int*)(0x42C815B8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A15 *((volatile unsigned int*)(0x42C815BCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A16 *((volatile unsigned int*)(0x42C815C0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A17 *((volatile unsigned int*)(0x42C815C4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A18 *((volatile unsigned int*)(0x42C815C8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A19 *((volatile unsigned int*)(0x42C815CCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A20 *((volatile unsigned int*)(0x42C815D0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A21 *((volatile unsigned int*)(0x42C815D4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A22 *((volatile unsigned int*)(0x42C815D8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A23 *((volatile unsigned int*)(0x42C815DCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A24 *((volatile unsigned int*)(0x42C815E0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A25 *((volatile unsigned int*)(0x42C815E4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A26 *((volatile unsigned int*)(0x42C815E8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A27 *((volatile unsigned int*)(0x42C815ECUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A28 *((volatile unsigned int*)(0x42C815F0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A29 *((volatile unsigned int*)(0x42C815F4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A30 *((volatile unsigned int*)(0x42C815F8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A31 *((volatile unsigned int*)(0x42C815FCUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A32 *((volatile unsigned int*)(0x42C81600UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A33 *((volatile unsigned int*)(0x42C81604UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A34 *((volatile unsigned int*)(0x42C81608UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A35 *((volatile unsigned int*)(0x42C8160CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A36 *((volatile unsigned int*)(0x42C81610UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A37 *((volatile unsigned int*)(0x42C81614UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A38 *((volatile unsigned int*)(0x42C81618UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A39 *((volatile unsigned int*)(0x42C8161CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A40 *((volatile unsigned int*)(0x42C81620UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A41 *((volatile unsigned int*)(0x42C81624UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A42 *((volatile unsigned int*)(0x42C81628UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A43 *((volatile unsigned int*)(0x42C8162CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A44 *((volatile unsigned int*)(0x42C81630UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A45 *((volatile unsigned int*)(0x42C81634UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A46 *((volatile unsigned int*)(0x42C81638UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A47 *((volatile unsigned int*)(0x42C8163CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC0 *((volatile unsigned int*)(0x42C81660UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC1 *((volatile unsigned int*)(0x42C81664UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC2 *((volatile unsigned int*)(0x42C81668UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC3 *((volatile unsigned int*)(0x42C8166CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC4 *((volatile unsigned int*)(0x42C81670UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC5 *((volatile unsigned int*)(0x42C81674UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_SA *((volatile unsigned int*)(0x42C81678UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_AE *((volatile unsigned int*)(0x42C8167CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A0 *((volatile unsigned int*)(0x42C81680UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A1 *((volatile unsigned int*)(0x42C81684UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A2 *((volatile unsigned int*)(0x42C81688UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A3 *((volatile unsigned int*)(0x42C8168CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A4 *((volatile unsigned int*)(0x42C81690UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A5 *((volatile unsigned int*)(0x42C81694UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A6 *((volatile unsigned int*)(0x42C81698UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A7 *((volatile unsigned int*)(0x42C8169CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A8 *((volatile unsigned int*)(0x42C816A0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A9 *((volatile unsigned int*)(0x42C816A4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A10 *((volatile unsigned int*)(0x42C816A8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A11 *((volatile unsigned int*)(0x42C816ACUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A12 *((volatile unsigned int*)(0x42C816B0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A13 *((volatile unsigned int*)(0x42C816B4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A14 *((volatile unsigned int*)(0x42C816B8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A15 *((volatile unsigned int*)(0x42C816BCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A16 *((volatile unsigned int*)(0x42C816C0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A17 *((volatile unsigned int*)(0x42C816C4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A18 *((volatile unsigned int*)(0x42C816C8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A19 *((volatile unsigned int*)(0x42C816CCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A20 *((volatile unsigned int*)(0x42C816D0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A21 *((volatile unsigned int*)(0x42C816D4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A22 *((volatile unsigned int*)(0x42C816D8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A23 *((volatile unsigned int*)(0x42C816DCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A24 *((volatile unsigned int*)(0x42C816E0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A25 *((volatile unsigned int*)(0x42C816E4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A26 *((volatile unsigned int*)(0x42C816E8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A27 *((volatile unsigned int*)(0x42C816ECUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A28 *((volatile unsigned int*)(0x42C816F0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A29 *((volatile unsigned int*)(0x42C816F4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A30 *((volatile unsigned int*)(0x42C816F8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A31 *((volatile unsigned int*)(0x42C816FCUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A32 *((volatile unsigned int*)(0x42C81700UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A33 *((volatile unsigned int*)(0x42C81704UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A34 *((volatile unsigned int*)(0x42C81708UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A35 *((volatile unsigned int*)(0x42C8170CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A36 *((volatile unsigned int*)(0x42C81710UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A37 *((volatile unsigned int*)(0x42C81714UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A38 *((volatile unsigned int*)(0x42C81718UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A39 *((volatile unsigned int*)(0x42C8171CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A40 *((volatile unsigned int*)(0x42C81720UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A41 *((volatile unsigned int*)(0x42C81724UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A42 *((volatile unsigned int*)(0x42C81728UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A43 *((volatile unsigned int*)(0x42C8172CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A44 *((volatile unsigned int*)(0x42C81730UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A45 *((volatile unsigned int*)(0x42C81734UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A46 *((volatile unsigned int*)(0x42C81738UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A47 *((volatile unsigned int*)(0x42C8173CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC0 *((volatile unsigned int*)(0x42C81760UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC1 *((volatile unsigned int*)(0x42C81764UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC2 *((volatile unsigned int*)(0x42C81768UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC3 *((volatile unsigned int*)(0x42C8176CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC4 *((volatile unsigned int*)(0x42C81770UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC5 *((volatile unsigned int*)(0x42C81774UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_SA *((volatile unsigned int*)(0x42C81778UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_AE *((volatile unsigned int*)(0x42C8177CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A0 *((volatile unsigned int*)(0x42C81780UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A1 *((volatile unsigned int*)(0x42C81784UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A2 *((volatile unsigned int*)(0x42C81788UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A3 *((volatile unsigned int*)(0x42C8178CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A4 *((volatile unsigned int*)(0x42C81790UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A5 *((volatile unsigned int*)(0x42C81794UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A6 *((volatile unsigned int*)(0x42C81798UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A7 *((volatile unsigned int*)(0x42C8179CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A8 *((volatile unsigned int*)(0x42C817A0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A9 *((volatile unsigned int*)(0x42C817A4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A10 *((volatile unsigned int*)(0x42C817A8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A11 *((volatile unsigned int*)(0x42C817ACUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A12 *((volatile unsigned int*)(0x42C817B0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A13 *((volatile unsigned int*)(0x42C817B4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A14 *((volatile unsigned int*)(0x42C817B8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A15 *((volatile unsigned int*)(0x42C817BCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A16 *((volatile unsigned int*)(0x42C817C0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A17 *((volatile unsigned int*)(0x42C817C4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A18 *((volatile unsigned int*)(0x42C817C8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A19 *((volatile unsigned int*)(0x42C817CCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A20 *((volatile unsigned int*)(0x42C817D0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A21 *((volatile unsigned int*)(0x42C817D4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A22 *((volatile unsigned int*)(0x42C817D8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A23 *((volatile unsigned int*)(0x42C817DCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A24 *((volatile unsigned int*)(0x42C817E0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A25 *((volatile unsigned int*)(0x42C817E4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A26 *((volatile unsigned int*)(0x42C817E8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A27 *((volatile unsigned int*)(0x42C817ECUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A28 *((volatile unsigned int*)(0x42C817F0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A29 *((volatile unsigned int*)(0x42C817F4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A30 *((volatile unsigned int*)(0x42C817F8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A31 *((volatile unsigned int*)(0x42C817FCUL)) -#define bFM3_ETHERNET_MAC0_RGSR_LM *((volatile unsigned int*)(0x42C81B00UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LSP0 *((volatile unsigned int*)(0x42C81B04UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LSP1 *((volatile unsigned int*)(0x42C81B08UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LS *((volatile unsigned int*)(0x42C81B0CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSE *((volatile unsigned int*)(0x42C8E000UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TFCU *((volatile unsigned int*)(0x42C8E004UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSI *((volatile unsigned int*)(0x42C8E008UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSU *((volatile unsigned int*)(0x42C8E00CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TITE *((volatile unsigned int*)(0x42C8E010UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TARU *((volatile unsigned int*)(0x42C8E014UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSEA *((volatile unsigned int*)(0x42C8E020UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSDB *((volatile unsigned int*)(0x42C8E024UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSV2E *((volatile unsigned int*)(0x42C8E028UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TETSP *((volatile unsigned int*)(0x42C8E02CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E *((volatile unsigned int*)(0x42C8E030UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E *((volatile unsigned int*)(0x42C8E034UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TETSEM *((volatile unsigned int*)(0x42C8E038UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSMRM *((volatile unsigned int*)(0x42C8E03CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSPS0 *((volatile unsigned int*)(0x42C8E040UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSPS1 *((volatile unsigned int*)(0x42C8E044UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSENMF *((volatile unsigned int*)(0x42C8E048UL)) -#define bFM3_ETHERNET_MAC0_TSCR_ATSFC *((volatile unsigned int*)(0x42C8E060UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC0 *((volatile unsigned int*)(0x42C8E080UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC1 *((volatile unsigned int*)(0x42C8E084UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC2 *((volatile unsigned int*)(0x42C8E088UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC3 *((volatile unsigned int*)(0x42C8E08CUL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC4 *((volatile unsigned int*)(0x42C8E090UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC5 *((volatile unsigned int*)(0x42C8E094UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC6 *((volatile unsigned int*)(0x42C8E098UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC7 *((volatile unsigned int*)(0x42C8E09CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS0 *((volatile unsigned int*)(0x42C8E100UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS1 *((volatile unsigned int*)(0x42C8E104UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS2 *((volatile unsigned int*)(0x42C8E108UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS3 *((volatile unsigned int*)(0x42C8E10CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS4 *((volatile unsigned int*)(0x42C8E110UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS5 *((volatile unsigned int*)(0x42C8E114UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS6 *((volatile unsigned int*)(0x42C8E118UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS7 *((volatile unsigned int*)(0x42C8E11CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS8 *((volatile unsigned int*)(0x42C8E120UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS9 *((volatile unsigned int*)(0x42C8E124UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS10 *((volatile unsigned int*)(0x42C8E128UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS11 *((volatile unsigned int*)(0x42C8E12CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS12 *((volatile unsigned int*)(0x42C8E130UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS13 *((volatile unsigned int*)(0x42C8E134UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS14 *((volatile unsigned int*)(0x42C8E138UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS15 *((volatile unsigned int*)(0x42C8E13CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS16 *((volatile unsigned int*)(0x42C8E140UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS17 *((volatile unsigned int*)(0x42C8E144UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS18 *((volatile unsigned int*)(0x42C8E148UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS19 *((volatile unsigned int*)(0x42C8E14CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS20 *((volatile unsigned int*)(0x42C8E150UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS21 *((volatile unsigned int*)(0x42C8E154UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS22 *((volatile unsigned int*)(0x42C8E158UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS23 *((volatile unsigned int*)(0x42C8E15CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS24 *((volatile unsigned int*)(0x42C8E160UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS25 *((volatile unsigned int*)(0x42C8E164UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS26 *((volatile unsigned int*)(0x42C8E168UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS27 *((volatile unsigned int*)(0x42C8E16CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS28 *((volatile unsigned int*)(0x42C8E170UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS29 *((volatile unsigned int*)(0x42C8E174UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS30 *((volatile unsigned int*)(0x42C8E178UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS31 *((volatile unsigned int*)(0x42C8E17CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS0 *((volatile unsigned int*)(0x42C8E080UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS1 *((volatile unsigned int*)(0x42C8E084UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS2 *((volatile unsigned int*)(0x42C8E088UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS3 *((volatile unsigned int*)(0x42C8E08CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS4 *((volatile unsigned int*)(0x42C8E090UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS5 *((volatile unsigned int*)(0x42C8E094UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS6 *((volatile unsigned int*)(0x42C8E098UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS7 *((volatile unsigned int*)(0x42C8E09CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS8 *((volatile unsigned int*)(0x42C8E0A0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS9 *((volatile unsigned int*)(0x42C8E0A4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS10 *((volatile unsigned int*)(0x42C8E0A8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS11 *((volatile unsigned int*)(0x42C8E0ACUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS12 *((volatile unsigned int*)(0x42C8E0B0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS13 *((volatile unsigned int*)(0x42C8E0B4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS14 *((volatile unsigned int*)(0x42C8E0B8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS15 *((volatile unsigned int*)(0x42C8E0BCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS16 *((volatile unsigned int*)(0x42C8E0C0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS17 *((volatile unsigned int*)(0x42C8E0C4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS18 *((volatile unsigned int*)(0x42C8E0C8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS19 *((volatile unsigned int*)(0x42C8E0CCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS20 *((volatile unsigned int*)(0x42C8E0D0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS21 *((volatile unsigned int*)(0x42C8E0D4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS22 *((volatile unsigned int*)(0x42C8E0D8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS23 *((volatile unsigned int*)(0x42C8E0DCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS24 *((volatile unsigned int*)(0x42C8E0E0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS25 *((volatile unsigned int*)(0x42C8E0E4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS26 *((volatile unsigned int*)(0x42C8E0E8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS27 *((volatile unsigned int*)(0x42C8E0ECUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS28 *((volatile unsigned int*)(0x42C8E0F0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS29 *((volatile unsigned int*)(0x42C8E0F4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS30 *((volatile unsigned int*)(0x42C8E0F8UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS0 *((volatile unsigned int*)(0x42C8E200UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS1 *((volatile unsigned int*)(0x42C8E204UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS2 *((volatile unsigned int*)(0x42C8E208UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS3 *((volatile unsigned int*)(0x42C8E20CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS4 *((volatile unsigned int*)(0x42C8E210UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS5 *((volatile unsigned int*)(0x42C8E214UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS6 *((volatile unsigned int*)(0x42C8E218UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS7 *((volatile unsigned int*)(0x42C8E21CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS8 *((volatile unsigned int*)(0x42C8E220UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS9 *((volatile unsigned int*)(0x42C8E224UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS10 *((volatile unsigned int*)(0x42C8E228UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS11 *((volatile unsigned int*)(0x42C8E22CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS12 *((volatile unsigned int*)(0x42C8E230UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS13 *((volatile unsigned int*)(0x42C8E234UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS14 *((volatile unsigned int*)(0x42C8E238UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS15 *((volatile unsigned int*)(0x42C8E23CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS16 *((volatile unsigned int*)(0x42C8E240UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS17 *((volatile unsigned int*)(0x42C8E244UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS18 *((volatile unsigned int*)(0x42C8E248UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS19 *((volatile unsigned int*)(0x42C8E24CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS20 *((volatile unsigned int*)(0x42C8E250UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS21 *((volatile unsigned int*)(0x42C8E254UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS22 *((volatile unsigned int*)(0x42C8E258UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS23 *((volatile unsigned int*)(0x42C8E25CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS24 *((volatile unsigned int*)(0x42C8E260UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS25 *((volatile unsigned int*)(0x42C8E264UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS26 *((volatile unsigned int*)(0x42C8E268UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS27 *((volatile unsigned int*)(0x42C8E26CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS28 *((volatile unsigned int*)(0x42C8E270UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS29 *((volatile unsigned int*)(0x42C8E274UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS30 *((volatile unsigned int*)(0x42C8E278UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS31 *((volatile unsigned int*)(0x42C8E27CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS0 *((volatile unsigned int*)(0x42C8E280UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS1 *((volatile unsigned int*)(0x42C8E284UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS2 *((volatile unsigned int*)(0x42C8E288UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS3 *((volatile unsigned int*)(0x42C8E28CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS4 *((volatile unsigned int*)(0x42C8E290UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS5 *((volatile unsigned int*)(0x42C8E294UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS6 *((volatile unsigned int*)(0x42C8E298UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS7 *((volatile unsigned int*)(0x42C8E29CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS8 *((volatile unsigned int*)(0x42C8E2A0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS9 *((volatile unsigned int*)(0x42C8E2A4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS10 *((volatile unsigned int*)(0x42C8E2A8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS11 *((volatile unsigned int*)(0x42C8E2ACUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS12 *((volatile unsigned int*)(0x42C8E2B0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS13 *((volatile unsigned int*)(0x42C8E2B4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS14 *((volatile unsigned int*)(0x42C8E2B8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS15 *((volatile unsigned int*)(0x42C8E2BCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS16 *((volatile unsigned int*)(0x42C8E2C0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS17 *((volatile unsigned int*)(0x42C8E2C4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS18 *((volatile unsigned int*)(0x42C8E2C8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS19 *((volatile unsigned int*)(0x42C8E2CCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS20 *((volatile unsigned int*)(0x42C8E2D0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS21 *((volatile unsigned int*)(0x42C8E2D4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS22 *((volatile unsigned int*)(0x42C8E2D8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS23 *((volatile unsigned int*)(0x42C8E2DCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS24 *((volatile unsigned int*)(0x42C8E2E0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS25 *((volatile unsigned int*)(0x42C8E2E4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS26 *((volatile unsigned int*)(0x42C8E2E8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS27 *((volatile unsigned int*)(0x42C8E2ECUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS28 *((volatile unsigned int*)(0x42C8E2F0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS29 *((volatile unsigned int*)(0x42C8E2F4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS30 *((volatile unsigned int*)(0x42C8E2F8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB *((volatile unsigned int*)(0x42C8E2FCUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR0 *((volatile unsigned int*)(0x42C8E300UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR1 *((volatile unsigned int*)(0x42C8E304UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR2 *((volatile unsigned int*)(0x42C8E308UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR3 *((volatile unsigned int*)(0x42C8E30CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR4 *((volatile unsigned int*)(0x42C8E310UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR5 *((volatile unsigned int*)(0x42C8E314UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR6 *((volatile unsigned int*)(0x42C8E318UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR7 *((volatile unsigned int*)(0x42C8E31CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR8 *((volatile unsigned int*)(0x42C8E320UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR9 *((volatile unsigned int*)(0x42C8E324UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR10 *((volatile unsigned int*)(0x42C8E328UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR11 *((volatile unsigned int*)(0x42C8E32CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR12 *((volatile unsigned int*)(0x42C8E330UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR13 *((volatile unsigned int*)(0x42C8E334UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR14 *((volatile unsigned int*)(0x42C8E338UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR15 *((volatile unsigned int*)(0x42C8E33CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR16 *((volatile unsigned int*)(0x42C8E340UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR17 *((volatile unsigned int*)(0x42C8E344UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR18 *((volatile unsigned int*)(0x42C8E348UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR19 *((volatile unsigned int*)(0x42C8E34CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR20 *((volatile unsigned int*)(0x42C8E350UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR21 *((volatile unsigned int*)(0x42C8E354UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR22 *((volatile unsigned int*)(0x42C8E358UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR23 *((volatile unsigned int*)(0x42C8E35CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR24 *((volatile unsigned int*)(0x42C8E360UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR25 *((volatile unsigned int*)(0x42C8E364UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR26 *((volatile unsigned int*)(0x42C8E368UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR27 *((volatile unsigned int*)(0x42C8E36CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR28 *((volatile unsigned int*)(0x42C8E370UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR29 *((volatile unsigned int*)(0x42C8E374UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR30 *((volatile unsigned int*)(0x42C8E378UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR31 *((volatile unsigned int*)(0x42C8E37CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR0 *((volatile unsigned int*)(0x42C8E380UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR1 *((volatile unsigned int*)(0x42C8E384UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR2 *((volatile unsigned int*)(0x42C8E388UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR3 *((volatile unsigned int*)(0x42C8E38CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR4 *((volatile unsigned int*)(0x42C8E390UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR5 *((volatile unsigned int*)(0x42C8E394UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR6 *((volatile unsigned int*)(0x42C8E398UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR7 *((volatile unsigned int*)(0x42C8E39CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR8 *((volatile unsigned int*)(0x42C8E3A0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR9 *((volatile unsigned int*)(0x42C8E3A4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR10 *((volatile unsigned int*)(0x42C8E3A8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR11 *((volatile unsigned int*)(0x42C8E3ACUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR12 *((volatile unsigned int*)(0x42C8E3B0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR13 *((volatile unsigned int*)(0x42C8E3B4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR14 *((volatile unsigned int*)(0x42C8E3B8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR15 *((volatile unsigned int*)(0x42C8E3BCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR16 *((volatile unsigned int*)(0x42C8E3C0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR17 *((volatile unsigned int*)(0x42C8E3C4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR18 *((volatile unsigned int*)(0x42C8E3C8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR19 *((volatile unsigned int*)(0x42C8E3CCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR20 *((volatile unsigned int*)(0x42C8E3D0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR21 *((volatile unsigned int*)(0x42C8E3D4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR22 *((volatile unsigned int*)(0x42C8E3D8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR23 *((volatile unsigned int*)(0x42C8E3DCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR24 *((volatile unsigned int*)(0x42C8E3E0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR25 *((volatile unsigned int*)(0x42C8E3E4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR26 *((volatile unsigned int*)(0x42C8E3E8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR27 *((volatile unsigned int*)(0x42C8E3ECUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR28 *((volatile unsigned int*)(0x42C8E3F0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR29 *((volatile unsigned int*)(0x42C8E3F4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR30 *((volatile unsigned int*)(0x42C8E3F8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR31 *((volatile unsigned int*)(0x42C8E3FCUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR0 *((volatile unsigned int*)(0x42C8E400UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR1 *((volatile unsigned int*)(0x42C8E404UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR2 *((volatile unsigned int*)(0x42C8E408UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR3 *((volatile unsigned int*)(0x42C8E40CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR4 *((volatile unsigned int*)(0x42C8E410UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR5 *((volatile unsigned int*)(0x42C8E414UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR6 *((volatile unsigned int*)(0x42C8E418UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR7 *((volatile unsigned int*)(0x42C8E41CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR8 *((volatile unsigned int*)(0x42C8E420UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR9 *((volatile unsigned int*)(0x42C8E424UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR10 *((volatile unsigned int*)(0x42C8E428UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR11 *((volatile unsigned int*)(0x42C8E42CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR12 *((volatile unsigned int*)(0x42C8E430UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR13 *((volatile unsigned int*)(0x42C8E434UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR14 *((volatile unsigned int*)(0x42C8E438UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR15 *((volatile unsigned int*)(0x42C8E43CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR16 *((volatile unsigned int*)(0x42C8E440UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR17 *((volatile unsigned int*)(0x42C8E444UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR18 *((volatile unsigned int*)(0x42C8E448UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR19 *((volatile unsigned int*)(0x42C8E44CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR20 *((volatile unsigned int*)(0x42C8E450UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR21 *((volatile unsigned int*)(0x42C8E454UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR22 *((volatile unsigned int*)(0x42C8E458UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR23 *((volatile unsigned int*)(0x42C8E45CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR24 *((volatile unsigned int*)(0x42C8E460UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR25 *((volatile unsigned int*)(0x42C8E464UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR26 *((volatile unsigned int*)(0x42C8E468UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR27 *((volatile unsigned int*)(0x42C8E46CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR28 *((volatile unsigned int*)(0x42C8E470UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR29 *((volatile unsigned int*)(0x42C8E474UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR30 *((volatile unsigned int*)(0x42C8E478UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42C8E480UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42C8E484UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42C8E488UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42C8E48CUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42C8E490UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42C8E494UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42C8E498UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42C8E49CUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42C8E4A0UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42C8E4A4UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42C8E4A8UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42C8E4ACUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42C8E4B0UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42C8E4B4UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42C8E4B8UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42C8E4BCUL)) -#define bFM3_ETHERNET_MAC0_TSR_TSSOVF *((volatile unsigned int*)(0x42C8E500UL)) -#define bFM3_ETHERNET_MAC0_TSR_TSTART *((volatile unsigned int*)(0x42C8E504UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSTS *((volatile unsigned int*)(0x42C8E508UL)) -#define bFM3_ETHERNET_MAC0_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSSTM *((volatile unsigned int*)(0x42C8E560UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS0 *((volatile unsigned int*)(0x42C8E564UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS1 *((volatile unsigned int*)(0x42C8E568UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS2 *((volatile unsigned int*)(0x42C8E56CUL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42C8E580UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42C8E584UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42C8E588UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42C8E58CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN0 *((volatile unsigned int*)(0x42C8E600UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN1 *((volatile unsigned int*)(0x42C8E604UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN2 *((volatile unsigned int*)(0x42C8E608UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN3 *((volatile unsigned int*)(0x42C8E60CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN4 *((volatile unsigned int*)(0x42C8E610UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN5 *((volatile unsigned int*)(0x42C8E614UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN6 *((volatile unsigned int*)(0x42C8E618UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN7 *((volatile unsigned int*)(0x42C8E61CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN8 *((volatile unsigned int*)(0x42C8E620UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN9 *((volatile unsigned int*)(0x42C8E624UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN10 *((volatile unsigned int*)(0x42C8E628UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN11 *((volatile unsigned int*)(0x42C8E62CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN12 *((volatile unsigned int*)(0x42C8E630UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN13 *((volatile unsigned int*)(0x42C8E634UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN14 *((volatile unsigned int*)(0x42C8E638UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN15 *((volatile unsigned int*)(0x42C8E63CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN16 *((volatile unsigned int*)(0x42C8E640UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN17 *((volatile unsigned int*)(0x42C8E644UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN18 *((volatile unsigned int*)(0x42C8E648UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN19 *((volatile unsigned int*)(0x42C8E64CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN20 *((volatile unsigned int*)(0x42C8E650UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN21 *((volatile unsigned int*)(0x42C8E654UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN22 *((volatile unsigned int*)(0x42C8E658UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN23 *((volatile unsigned int*)(0x42C8E65CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN24 *((volatile unsigned int*)(0x42C8E660UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN25 *((volatile unsigned int*)(0x42C8E664UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN26 *((volatile unsigned int*)(0x42C8E668UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN27 *((volatile unsigned int*)(0x42C8E66CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN28 *((volatile unsigned int*)(0x42C8E670UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN29 *((volatile unsigned int*)(0x42C8E674UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN30 *((volatile unsigned int*)(0x42C8E678UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS0 *((volatile unsigned int*)(0x42C8E680UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS1 *((volatile unsigned int*)(0x42C8E684UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS2 *((volatile unsigned int*)(0x42C8E688UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS3 *((volatile unsigned int*)(0x42C8E68CUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS4 *((volatile unsigned int*)(0x42C8E690UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS5 *((volatile unsigned int*)(0x42C8E694UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS6 *((volatile unsigned int*)(0x42C8E698UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS7 *((volatile unsigned int*)(0x42C8E69CUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS8 *((volatile unsigned int*)(0x42C8E6A0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS9 *((volatile unsigned int*)(0x42C8E6A4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS10 *((volatile unsigned int*)(0x42C8E6A8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS11 *((volatile unsigned int*)(0x42C8E6ACUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS12 *((volatile unsigned int*)(0x42C8E6B0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS13 *((volatile unsigned int*)(0x42C8E6B4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS14 *((volatile unsigned int*)(0x42C8E6B8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS15 *((volatile unsigned int*)(0x42C8E6BCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS16 *((volatile unsigned int*)(0x42C8E6C0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS17 *((volatile unsigned int*)(0x42C8E6C4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS18 *((volatile unsigned int*)(0x42C8E6C8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS19 *((volatile unsigned int*)(0x42C8E6CCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS20 *((volatile unsigned int*)(0x42C8E6D0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS21 *((volatile unsigned int*)(0x42C8E6D4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS22 *((volatile unsigned int*)(0x42C8E6D8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS23 *((volatile unsigned int*)(0x42C8E6DCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS24 *((volatile unsigned int*)(0x42C8E6E0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS25 *((volatile unsigned int*)(0x42C8E6E4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS26 *((volatile unsigned int*)(0x42C8E6E8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS27 *((volatile unsigned int*)(0x42C8E6ECUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS28 *((volatile unsigned int*)(0x42C8E6F0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS29 *((volatile unsigned int*)(0x42C8E6F4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS30 *((volatile unsigned int*)(0x42C8E6F8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS31 *((volatile unsigned int*)(0x42C8E6FCUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A32 *((volatile unsigned int*)(0x42C90000UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A33 *((volatile unsigned int*)(0x42C90004UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A34 *((volatile unsigned int*)(0x42C90008UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A35 *((volatile unsigned int*)(0x42C9000CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A36 *((volatile unsigned int*)(0x42C90010UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A37 *((volatile unsigned int*)(0x42C90014UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A38 *((volatile unsigned int*)(0x42C90018UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A39 *((volatile unsigned int*)(0x42C9001CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A40 *((volatile unsigned int*)(0x42C90020UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A41 *((volatile unsigned int*)(0x42C90024UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A42 *((volatile unsigned int*)(0x42C90028UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A43 *((volatile unsigned int*)(0x42C9002CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A44 *((volatile unsigned int*)(0x42C90030UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A45 *((volatile unsigned int*)(0x42C90034UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A46 *((volatile unsigned int*)(0x42C90038UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A47 *((volatile unsigned int*)(0x42C9003CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC0 *((volatile unsigned int*)(0x42C90060UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC1 *((volatile unsigned int*)(0x42C90064UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC2 *((volatile unsigned int*)(0x42C90068UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC3 *((volatile unsigned int*)(0x42C9006CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC4 *((volatile unsigned int*)(0x42C90070UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC5 *((volatile unsigned int*)(0x42C90074UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_SA *((volatile unsigned int*)(0x42C90078UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_AE *((volatile unsigned int*)(0x42C9007CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A0 *((volatile unsigned int*)(0x42C90080UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A1 *((volatile unsigned int*)(0x42C90084UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A2 *((volatile unsigned int*)(0x42C90088UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A3 *((volatile unsigned int*)(0x42C9008CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A4 *((volatile unsigned int*)(0x42C90090UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A5 *((volatile unsigned int*)(0x42C90094UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A6 *((volatile unsigned int*)(0x42C90098UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A7 *((volatile unsigned int*)(0x42C9009CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A8 *((volatile unsigned int*)(0x42C900A0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A9 *((volatile unsigned int*)(0x42C900A4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A10 *((volatile unsigned int*)(0x42C900A8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A11 *((volatile unsigned int*)(0x42C900ACUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A12 *((volatile unsigned int*)(0x42C900B0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A13 *((volatile unsigned int*)(0x42C900B4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A14 *((volatile unsigned int*)(0x42C900B8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A15 *((volatile unsigned int*)(0x42C900BCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A16 *((volatile unsigned int*)(0x42C900C0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A17 *((volatile unsigned int*)(0x42C900C4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A18 *((volatile unsigned int*)(0x42C900C8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A19 *((volatile unsigned int*)(0x42C900CCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A20 *((volatile unsigned int*)(0x42C900D0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A21 *((volatile unsigned int*)(0x42C900D4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A22 *((volatile unsigned int*)(0x42C900D8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A23 *((volatile unsigned int*)(0x42C900DCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A24 *((volatile unsigned int*)(0x42C900E0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A25 *((volatile unsigned int*)(0x42C900E4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A26 *((volatile unsigned int*)(0x42C900E8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A27 *((volatile unsigned int*)(0x42C900ECUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A28 *((volatile unsigned int*)(0x42C900F0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A29 *((volatile unsigned int*)(0x42C900F4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A30 *((volatile unsigned int*)(0x42C900F8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A31 *((volatile unsigned int*)(0x42C900FCUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A32 *((volatile unsigned int*)(0x42C90100UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A33 *((volatile unsigned int*)(0x42C90104UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A34 *((volatile unsigned int*)(0x42C90108UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A35 *((volatile unsigned int*)(0x42C9010CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A36 *((volatile unsigned int*)(0x42C90110UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A37 *((volatile unsigned int*)(0x42C90114UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A38 *((volatile unsigned int*)(0x42C90118UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A39 *((volatile unsigned int*)(0x42C9011CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A40 *((volatile unsigned int*)(0x42C90120UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A41 *((volatile unsigned int*)(0x42C90124UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A42 *((volatile unsigned int*)(0x42C90128UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A43 *((volatile unsigned int*)(0x42C9012CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A44 *((volatile unsigned int*)(0x42C90130UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A45 *((volatile unsigned int*)(0x42C90134UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A46 *((volatile unsigned int*)(0x42C90138UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A47 *((volatile unsigned int*)(0x42C9013CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC0 *((volatile unsigned int*)(0x42C90160UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC1 *((volatile unsigned int*)(0x42C90164UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC2 *((volatile unsigned int*)(0x42C90168UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC3 *((volatile unsigned int*)(0x42C9016CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC4 *((volatile unsigned int*)(0x42C90170UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC5 *((volatile unsigned int*)(0x42C90174UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_SA *((volatile unsigned int*)(0x42C90178UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_AE *((volatile unsigned int*)(0x42C9017CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A0 *((volatile unsigned int*)(0x42C90180UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A1 *((volatile unsigned int*)(0x42C90184UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A2 *((volatile unsigned int*)(0x42C90188UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A3 *((volatile unsigned int*)(0x42C9018CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A4 *((volatile unsigned int*)(0x42C90190UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A5 *((volatile unsigned int*)(0x42C90194UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A6 *((volatile unsigned int*)(0x42C90198UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A7 *((volatile unsigned int*)(0x42C9019CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A8 *((volatile unsigned int*)(0x42C901A0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A9 *((volatile unsigned int*)(0x42C901A4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A10 *((volatile unsigned int*)(0x42C901A8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A11 *((volatile unsigned int*)(0x42C901ACUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A12 *((volatile unsigned int*)(0x42C901B0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A13 *((volatile unsigned int*)(0x42C901B4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A14 *((volatile unsigned int*)(0x42C901B8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A15 *((volatile unsigned int*)(0x42C901BCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A16 *((volatile unsigned int*)(0x42C901C0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A17 *((volatile unsigned int*)(0x42C901C4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A18 *((volatile unsigned int*)(0x42C901C8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A19 *((volatile unsigned int*)(0x42C901CCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A20 *((volatile unsigned int*)(0x42C901D0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A21 *((volatile unsigned int*)(0x42C901D4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A22 *((volatile unsigned int*)(0x42C901D8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A23 *((volatile unsigned int*)(0x42C901DCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A24 *((volatile unsigned int*)(0x42C901E0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A25 *((volatile unsigned int*)(0x42C901E4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A26 *((volatile unsigned int*)(0x42C901E8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A27 *((volatile unsigned int*)(0x42C901ECUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A28 *((volatile unsigned int*)(0x42C901F0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A29 *((volatile unsigned int*)(0x42C901F4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A30 *((volatile unsigned int*)(0x42C901F8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A31 *((volatile unsigned int*)(0x42C901FCUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A32 *((volatile unsigned int*)(0x42C90200UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A33 *((volatile unsigned int*)(0x42C90204UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A34 *((volatile unsigned int*)(0x42C90208UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A35 *((volatile unsigned int*)(0x42C9020CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A36 *((volatile unsigned int*)(0x42C90210UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A37 *((volatile unsigned int*)(0x42C90214UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A38 *((volatile unsigned int*)(0x42C90218UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A39 *((volatile unsigned int*)(0x42C9021CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A40 *((volatile unsigned int*)(0x42C90220UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A41 *((volatile unsigned int*)(0x42C90224UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A42 *((volatile unsigned int*)(0x42C90228UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A43 *((volatile unsigned int*)(0x42C9022CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A44 *((volatile unsigned int*)(0x42C90230UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A45 *((volatile unsigned int*)(0x42C90234UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A46 *((volatile unsigned int*)(0x42C90238UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A47 *((volatile unsigned int*)(0x42C9023CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC0 *((volatile unsigned int*)(0x42C90260UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC1 *((volatile unsigned int*)(0x42C90264UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC2 *((volatile unsigned int*)(0x42C90268UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC3 *((volatile unsigned int*)(0x42C9026CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC4 *((volatile unsigned int*)(0x42C90270UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC5 *((volatile unsigned int*)(0x42C90274UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_SA *((volatile unsigned int*)(0x42C90278UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_AE *((volatile unsigned int*)(0x42C9027CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A0 *((volatile unsigned int*)(0x42C90280UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A1 *((volatile unsigned int*)(0x42C90284UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A2 *((volatile unsigned int*)(0x42C90288UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A3 *((volatile unsigned int*)(0x42C9028CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A4 *((volatile unsigned int*)(0x42C90290UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A5 *((volatile unsigned int*)(0x42C90294UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A6 *((volatile unsigned int*)(0x42C90298UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A7 *((volatile unsigned int*)(0x42C9029CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A8 *((volatile unsigned int*)(0x42C902A0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A9 *((volatile unsigned int*)(0x42C902A4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A10 *((volatile unsigned int*)(0x42C902A8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A11 *((volatile unsigned int*)(0x42C902ACUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A12 *((volatile unsigned int*)(0x42C902B0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A13 *((volatile unsigned int*)(0x42C902B4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A14 *((volatile unsigned int*)(0x42C902B8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A15 *((volatile unsigned int*)(0x42C902BCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A16 *((volatile unsigned int*)(0x42C902C0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A17 *((volatile unsigned int*)(0x42C902C4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A18 *((volatile unsigned int*)(0x42C902C8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A19 *((volatile unsigned int*)(0x42C902CCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A20 *((volatile unsigned int*)(0x42C902D0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A21 *((volatile unsigned int*)(0x42C902D4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A22 *((volatile unsigned int*)(0x42C902D8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A23 *((volatile unsigned int*)(0x42C902DCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A24 *((volatile unsigned int*)(0x42C902E0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A25 *((volatile unsigned int*)(0x42C902E4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A26 *((volatile unsigned int*)(0x42C902E8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A27 *((volatile unsigned int*)(0x42C902ECUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A28 *((volatile unsigned int*)(0x42C902F0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A29 *((volatile unsigned int*)(0x42C902F4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A30 *((volatile unsigned int*)(0x42C902F8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A31 *((volatile unsigned int*)(0x42C902FCUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A32 *((volatile unsigned int*)(0x42C90300UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A33 *((volatile unsigned int*)(0x42C90304UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A34 *((volatile unsigned int*)(0x42C90308UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A35 *((volatile unsigned int*)(0x42C9030CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A36 *((volatile unsigned int*)(0x42C90310UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A37 *((volatile unsigned int*)(0x42C90314UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A38 *((volatile unsigned int*)(0x42C90318UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A39 *((volatile unsigned int*)(0x42C9031CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A40 *((volatile unsigned int*)(0x42C90320UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A41 *((volatile unsigned int*)(0x42C90324UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A42 *((volatile unsigned int*)(0x42C90328UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A43 *((volatile unsigned int*)(0x42C9032CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A44 *((volatile unsigned int*)(0x42C90330UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A45 *((volatile unsigned int*)(0x42C90334UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A46 *((volatile unsigned int*)(0x42C90338UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A47 *((volatile unsigned int*)(0x42C9033CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC0 *((volatile unsigned int*)(0x42C90360UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC1 *((volatile unsigned int*)(0x42C90364UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC2 *((volatile unsigned int*)(0x42C90368UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC3 *((volatile unsigned int*)(0x42C9036CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC4 *((volatile unsigned int*)(0x42C90370UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC5 *((volatile unsigned int*)(0x42C90374UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_SA *((volatile unsigned int*)(0x42C90378UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_AE *((volatile unsigned int*)(0x42C9037CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A0 *((volatile unsigned int*)(0x42C90380UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A1 *((volatile unsigned int*)(0x42C90384UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A2 *((volatile unsigned int*)(0x42C90388UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A3 *((volatile unsigned int*)(0x42C9038CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A4 *((volatile unsigned int*)(0x42C90390UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A5 *((volatile unsigned int*)(0x42C90394UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A6 *((volatile unsigned int*)(0x42C90398UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A7 *((volatile unsigned int*)(0x42C9039CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A8 *((volatile unsigned int*)(0x42C903A0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A9 *((volatile unsigned int*)(0x42C903A4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A10 *((volatile unsigned int*)(0x42C903A8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A11 *((volatile unsigned int*)(0x42C903ACUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A12 *((volatile unsigned int*)(0x42C903B0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A13 *((volatile unsigned int*)(0x42C903B4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A14 *((volatile unsigned int*)(0x42C903B8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A15 *((volatile unsigned int*)(0x42C903BCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A16 *((volatile unsigned int*)(0x42C903C0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A17 *((volatile unsigned int*)(0x42C903C4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A18 *((volatile unsigned int*)(0x42C903C8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A19 *((volatile unsigned int*)(0x42C903CCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A20 *((volatile unsigned int*)(0x42C903D0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A21 *((volatile unsigned int*)(0x42C903D4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A22 *((volatile unsigned int*)(0x42C903D8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A23 *((volatile unsigned int*)(0x42C903DCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A24 *((volatile unsigned int*)(0x42C903E0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A25 *((volatile unsigned int*)(0x42C903E4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A26 *((volatile unsigned int*)(0x42C903E8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A27 *((volatile unsigned int*)(0x42C903ECUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A28 *((volatile unsigned int*)(0x42C903F0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A29 *((volatile unsigned int*)(0x42C903F4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A30 *((volatile unsigned int*)(0x42C903F8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A31 *((volatile unsigned int*)(0x42C903FCUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A32 *((volatile unsigned int*)(0x42C90400UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A33 *((volatile unsigned int*)(0x42C90404UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A34 *((volatile unsigned int*)(0x42C90408UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A35 *((volatile unsigned int*)(0x42C9040CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A36 *((volatile unsigned int*)(0x42C90410UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A37 *((volatile unsigned int*)(0x42C90414UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A38 *((volatile unsigned int*)(0x42C90418UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A39 *((volatile unsigned int*)(0x42C9041CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A40 *((volatile unsigned int*)(0x42C90420UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A41 *((volatile unsigned int*)(0x42C90424UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A42 *((volatile unsigned int*)(0x42C90428UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A43 *((volatile unsigned int*)(0x42C9042CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A44 *((volatile unsigned int*)(0x42C90430UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A45 *((volatile unsigned int*)(0x42C90434UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A46 *((volatile unsigned int*)(0x42C90438UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A47 *((volatile unsigned int*)(0x42C9043CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC0 *((volatile unsigned int*)(0x42C90460UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC1 *((volatile unsigned int*)(0x42C90464UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC2 *((volatile unsigned int*)(0x42C90468UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC3 *((volatile unsigned int*)(0x42C9046CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC4 *((volatile unsigned int*)(0x42C90470UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC5 *((volatile unsigned int*)(0x42C90474UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_SA *((volatile unsigned int*)(0x42C90478UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_AE *((volatile unsigned int*)(0x42C9047CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A0 *((volatile unsigned int*)(0x42C90480UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A1 *((volatile unsigned int*)(0x42C90484UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A2 *((volatile unsigned int*)(0x42C90488UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A3 *((volatile unsigned int*)(0x42C9048CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A4 *((volatile unsigned int*)(0x42C90490UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A5 *((volatile unsigned int*)(0x42C90494UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A6 *((volatile unsigned int*)(0x42C90498UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A7 *((volatile unsigned int*)(0x42C9049CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A8 *((volatile unsigned int*)(0x42C904A0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A9 *((volatile unsigned int*)(0x42C904A4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A10 *((volatile unsigned int*)(0x42C904A8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A11 *((volatile unsigned int*)(0x42C904ACUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A12 *((volatile unsigned int*)(0x42C904B0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A13 *((volatile unsigned int*)(0x42C904B4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A14 *((volatile unsigned int*)(0x42C904B8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A15 *((volatile unsigned int*)(0x42C904BCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A16 *((volatile unsigned int*)(0x42C904C0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A17 *((volatile unsigned int*)(0x42C904C4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A18 *((volatile unsigned int*)(0x42C904C8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A19 *((volatile unsigned int*)(0x42C904CCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A20 *((volatile unsigned int*)(0x42C904D0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A21 *((volatile unsigned int*)(0x42C904D4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A22 *((volatile unsigned int*)(0x42C904D8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A23 *((volatile unsigned int*)(0x42C904DCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A24 *((volatile unsigned int*)(0x42C904E0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A25 *((volatile unsigned int*)(0x42C904E4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A26 *((volatile unsigned int*)(0x42C904E8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A27 *((volatile unsigned int*)(0x42C904ECUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A28 *((volatile unsigned int*)(0x42C904F0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A29 *((volatile unsigned int*)(0x42C904F4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A30 *((volatile unsigned int*)(0x42C904F8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A31 *((volatile unsigned int*)(0x42C904FCUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A32 *((volatile unsigned int*)(0x42C90500UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A33 *((volatile unsigned int*)(0x42C90504UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A34 *((volatile unsigned int*)(0x42C90508UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A35 *((volatile unsigned int*)(0x42C9050CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A36 *((volatile unsigned int*)(0x42C90510UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A37 *((volatile unsigned int*)(0x42C90514UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A38 *((volatile unsigned int*)(0x42C90518UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A39 *((volatile unsigned int*)(0x42C9051CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A40 *((volatile unsigned int*)(0x42C90520UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A41 *((volatile unsigned int*)(0x42C90524UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A42 *((volatile unsigned int*)(0x42C90528UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A43 *((volatile unsigned int*)(0x42C9052CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A44 *((volatile unsigned int*)(0x42C90530UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A45 *((volatile unsigned int*)(0x42C90534UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A46 *((volatile unsigned int*)(0x42C90538UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A47 *((volatile unsigned int*)(0x42C9053CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC0 *((volatile unsigned int*)(0x42C90560UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC1 *((volatile unsigned int*)(0x42C90564UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC2 *((volatile unsigned int*)(0x42C90568UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC3 *((volatile unsigned int*)(0x42C9056CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC4 *((volatile unsigned int*)(0x42C90570UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC5 *((volatile unsigned int*)(0x42C90574UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_SA *((volatile unsigned int*)(0x42C90578UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_AE *((volatile unsigned int*)(0x42C9057CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A0 *((volatile unsigned int*)(0x42C90580UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A1 *((volatile unsigned int*)(0x42C90584UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A2 *((volatile unsigned int*)(0x42C90588UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A3 *((volatile unsigned int*)(0x42C9058CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A4 *((volatile unsigned int*)(0x42C90590UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A5 *((volatile unsigned int*)(0x42C90594UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A6 *((volatile unsigned int*)(0x42C90598UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A7 *((volatile unsigned int*)(0x42C9059CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A8 *((volatile unsigned int*)(0x42C905A0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A9 *((volatile unsigned int*)(0x42C905A4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A10 *((volatile unsigned int*)(0x42C905A8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A11 *((volatile unsigned int*)(0x42C905ACUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A12 *((volatile unsigned int*)(0x42C905B0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A13 *((volatile unsigned int*)(0x42C905B4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A14 *((volatile unsigned int*)(0x42C905B8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A15 *((volatile unsigned int*)(0x42C905BCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A16 *((volatile unsigned int*)(0x42C905C0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A17 *((volatile unsigned int*)(0x42C905C4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A18 *((volatile unsigned int*)(0x42C905C8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A19 *((volatile unsigned int*)(0x42C905CCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A20 *((volatile unsigned int*)(0x42C905D0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A21 *((volatile unsigned int*)(0x42C905D4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A22 *((volatile unsigned int*)(0x42C905D8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A23 *((volatile unsigned int*)(0x42C905DCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A24 *((volatile unsigned int*)(0x42C905E0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A25 *((volatile unsigned int*)(0x42C905E4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A26 *((volatile unsigned int*)(0x42C905E8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A27 *((volatile unsigned int*)(0x42C905ECUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A28 *((volatile unsigned int*)(0x42C905F0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A29 *((volatile unsigned int*)(0x42C905F4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A30 *((volatile unsigned int*)(0x42C905F8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A31 *((volatile unsigned int*)(0x42C905FCUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A32 *((volatile unsigned int*)(0x42C90600UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A33 *((volatile unsigned int*)(0x42C90604UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A34 *((volatile unsigned int*)(0x42C90608UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A35 *((volatile unsigned int*)(0x42C9060CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A36 *((volatile unsigned int*)(0x42C90610UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A37 *((volatile unsigned int*)(0x42C90614UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A38 *((volatile unsigned int*)(0x42C90618UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A39 *((volatile unsigned int*)(0x42C9061CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A40 *((volatile unsigned int*)(0x42C90620UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A41 *((volatile unsigned int*)(0x42C90624UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A42 *((volatile unsigned int*)(0x42C90628UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A43 *((volatile unsigned int*)(0x42C9062CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A44 *((volatile unsigned int*)(0x42C90630UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A45 *((volatile unsigned int*)(0x42C90634UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A46 *((volatile unsigned int*)(0x42C90638UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A47 *((volatile unsigned int*)(0x42C9063CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC0 *((volatile unsigned int*)(0x42C90660UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC1 *((volatile unsigned int*)(0x42C90664UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC2 *((volatile unsigned int*)(0x42C90668UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC3 *((volatile unsigned int*)(0x42C9066CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC4 *((volatile unsigned int*)(0x42C90670UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC5 *((volatile unsigned int*)(0x42C90674UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_SA *((volatile unsigned int*)(0x42C90678UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_AE *((volatile unsigned int*)(0x42C9067CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A0 *((volatile unsigned int*)(0x42C90680UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A1 *((volatile unsigned int*)(0x42C90684UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A2 *((volatile unsigned int*)(0x42C90688UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A3 *((volatile unsigned int*)(0x42C9068CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A4 *((volatile unsigned int*)(0x42C90690UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A5 *((volatile unsigned int*)(0x42C90694UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A6 *((volatile unsigned int*)(0x42C90698UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A7 *((volatile unsigned int*)(0x42C9069CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A8 *((volatile unsigned int*)(0x42C906A0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A9 *((volatile unsigned int*)(0x42C906A4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A10 *((volatile unsigned int*)(0x42C906A8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A11 *((volatile unsigned int*)(0x42C906ACUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A12 *((volatile unsigned int*)(0x42C906B0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A13 *((volatile unsigned int*)(0x42C906B4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A14 *((volatile unsigned int*)(0x42C906B8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A15 *((volatile unsigned int*)(0x42C906BCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A16 *((volatile unsigned int*)(0x42C906C0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A17 *((volatile unsigned int*)(0x42C906C4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A18 *((volatile unsigned int*)(0x42C906C8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A19 *((volatile unsigned int*)(0x42C906CCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A20 *((volatile unsigned int*)(0x42C906D0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A21 *((volatile unsigned int*)(0x42C906D4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A22 *((volatile unsigned int*)(0x42C906D8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A23 *((volatile unsigned int*)(0x42C906DCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A24 *((volatile unsigned int*)(0x42C906E0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A25 *((volatile unsigned int*)(0x42C906E4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A26 *((volatile unsigned int*)(0x42C906E8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A27 *((volatile unsigned int*)(0x42C906ECUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A28 *((volatile unsigned int*)(0x42C906F0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A29 *((volatile unsigned int*)(0x42C906F4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A30 *((volatile unsigned int*)(0x42C906F8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A31 *((volatile unsigned int*)(0x42C906FCUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A32 *((volatile unsigned int*)(0x42C90700UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A33 *((volatile unsigned int*)(0x42C90704UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A34 *((volatile unsigned int*)(0x42C90708UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A35 *((volatile unsigned int*)(0x42C9070CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A36 *((volatile unsigned int*)(0x42C90710UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A37 *((volatile unsigned int*)(0x42C90714UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A38 *((volatile unsigned int*)(0x42C90718UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A39 *((volatile unsigned int*)(0x42C9071CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A40 *((volatile unsigned int*)(0x42C90720UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A41 *((volatile unsigned int*)(0x42C90724UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A42 *((volatile unsigned int*)(0x42C90728UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A43 *((volatile unsigned int*)(0x42C9072CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A44 *((volatile unsigned int*)(0x42C90730UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A45 *((volatile unsigned int*)(0x42C90734UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A46 *((volatile unsigned int*)(0x42C90738UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A47 *((volatile unsigned int*)(0x42C9073CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC0 *((volatile unsigned int*)(0x42C90760UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC1 *((volatile unsigned int*)(0x42C90764UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC2 *((volatile unsigned int*)(0x42C90768UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC3 *((volatile unsigned int*)(0x42C9076CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC4 *((volatile unsigned int*)(0x42C90770UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC5 *((volatile unsigned int*)(0x42C90774UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_SA *((volatile unsigned int*)(0x42C90778UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_AE *((volatile unsigned int*)(0x42C9077CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A0 *((volatile unsigned int*)(0x42C90780UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A1 *((volatile unsigned int*)(0x42C90784UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A2 *((volatile unsigned int*)(0x42C90788UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A3 *((volatile unsigned int*)(0x42C9078CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A4 *((volatile unsigned int*)(0x42C90790UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A5 *((volatile unsigned int*)(0x42C90794UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A6 *((volatile unsigned int*)(0x42C90798UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A7 *((volatile unsigned int*)(0x42C9079CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A8 *((volatile unsigned int*)(0x42C907A0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A9 *((volatile unsigned int*)(0x42C907A4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A10 *((volatile unsigned int*)(0x42C907A8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A11 *((volatile unsigned int*)(0x42C907ACUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A12 *((volatile unsigned int*)(0x42C907B0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A13 *((volatile unsigned int*)(0x42C907B4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A14 *((volatile unsigned int*)(0x42C907B8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A15 *((volatile unsigned int*)(0x42C907BCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A16 *((volatile unsigned int*)(0x42C907C0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A17 *((volatile unsigned int*)(0x42C907C4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A18 *((volatile unsigned int*)(0x42C907C8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A19 *((volatile unsigned int*)(0x42C907CCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A20 *((volatile unsigned int*)(0x42C907D0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A21 *((volatile unsigned int*)(0x42C907D4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A22 *((volatile unsigned int*)(0x42C907D8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A23 *((volatile unsigned int*)(0x42C907DCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A24 *((volatile unsigned int*)(0x42C907E0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A25 *((volatile unsigned int*)(0x42C907E4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A26 *((volatile unsigned int*)(0x42C907E8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A27 *((volatile unsigned int*)(0x42C907ECUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A28 *((volatile unsigned int*)(0x42C907F0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A29 *((volatile unsigned int*)(0x42C907F4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A30 *((volatile unsigned int*)(0x42C907F8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A31 *((volatile unsigned int*)(0x42C907FCUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A32 *((volatile unsigned int*)(0x42C90800UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A33 *((volatile unsigned int*)(0x42C90804UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A34 *((volatile unsigned int*)(0x42C90808UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A35 *((volatile unsigned int*)(0x42C9080CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A36 *((volatile unsigned int*)(0x42C90810UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A37 *((volatile unsigned int*)(0x42C90814UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A38 *((volatile unsigned int*)(0x42C90818UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A39 *((volatile unsigned int*)(0x42C9081CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A40 *((volatile unsigned int*)(0x42C90820UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A41 *((volatile unsigned int*)(0x42C90824UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A42 *((volatile unsigned int*)(0x42C90828UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A43 *((volatile unsigned int*)(0x42C9082CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A44 *((volatile unsigned int*)(0x42C90830UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A45 *((volatile unsigned int*)(0x42C90834UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A46 *((volatile unsigned int*)(0x42C90838UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A47 *((volatile unsigned int*)(0x42C9083CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC0 *((volatile unsigned int*)(0x42C90860UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC1 *((volatile unsigned int*)(0x42C90864UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC2 *((volatile unsigned int*)(0x42C90868UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC3 *((volatile unsigned int*)(0x42C9086CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC4 *((volatile unsigned int*)(0x42C90870UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC5 *((volatile unsigned int*)(0x42C90874UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_SA *((volatile unsigned int*)(0x42C90878UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_AE *((volatile unsigned int*)(0x42C9087CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A0 *((volatile unsigned int*)(0x42C90880UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A1 *((volatile unsigned int*)(0x42C90884UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A2 *((volatile unsigned int*)(0x42C90888UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A3 *((volatile unsigned int*)(0x42C9088CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A4 *((volatile unsigned int*)(0x42C90890UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A5 *((volatile unsigned int*)(0x42C90894UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A6 *((volatile unsigned int*)(0x42C90898UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A7 *((volatile unsigned int*)(0x42C9089CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A8 *((volatile unsigned int*)(0x42C908A0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A9 *((volatile unsigned int*)(0x42C908A4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A10 *((volatile unsigned int*)(0x42C908A8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A11 *((volatile unsigned int*)(0x42C908ACUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A12 *((volatile unsigned int*)(0x42C908B0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A13 *((volatile unsigned int*)(0x42C908B4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A14 *((volatile unsigned int*)(0x42C908B8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A15 *((volatile unsigned int*)(0x42C908BCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A16 *((volatile unsigned int*)(0x42C908C0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A17 *((volatile unsigned int*)(0x42C908C4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A18 *((volatile unsigned int*)(0x42C908C8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A19 *((volatile unsigned int*)(0x42C908CCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A20 *((volatile unsigned int*)(0x42C908D0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A21 *((volatile unsigned int*)(0x42C908D4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A22 *((volatile unsigned int*)(0x42C908D8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A23 *((volatile unsigned int*)(0x42C908DCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A24 *((volatile unsigned int*)(0x42C908E0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A25 *((volatile unsigned int*)(0x42C908E4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A26 *((volatile unsigned int*)(0x42C908E8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A27 *((volatile unsigned int*)(0x42C908ECUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A28 *((volatile unsigned int*)(0x42C908F0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A29 *((volatile unsigned int*)(0x42C908F4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A30 *((volatile unsigned int*)(0x42C908F8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A31 *((volatile unsigned int*)(0x42C908FCUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A32 *((volatile unsigned int*)(0x42C90900UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A33 *((volatile unsigned int*)(0x42C90904UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A34 *((volatile unsigned int*)(0x42C90908UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A35 *((volatile unsigned int*)(0x42C9090CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A36 *((volatile unsigned int*)(0x42C90910UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A37 *((volatile unsigned int*)(0x42C90914UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A38 *((volatile unsigned int*)(0x42C90918UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A39 *((volatile unsigned int*)(0x42C9091CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A40 *((volatile unsigned int*)(0x42C90920UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A41 *((volatile unsigned int*)(0x42C90924UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A42 *((volatile unsigned int*)(0x42C90928UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A43 *((volatile unsigned int*)(0x42C9092CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A44 *((volatile unsigned int*)(0x42C90930UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A45 *((volatile unsigned int*)(0x42C90934UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A46 *((volatile unsigned int*)(0x42C90938UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A47 *((volatile unsigned int*)(0x42C9093CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC0 *((volatile unsigned int*)(0x42C90960UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC1 *((volatile unsigned int*)(0x42C90964UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC2 *((volatile unsigned int*)(0x42C90968UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC3 *((volatile unsigned int*)(0x42C9096CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC4 *((volatile unsigned int*)(0x42C90970UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC5 *((volatile unsigned int*)(0x42C90974UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_SA *((volatile unsigned int*)(0x42C90978UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_AE *((volatile unsigned int*)(0x42C9097CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A0 *((volatile unsigned int*)(0x42C90980UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A1 *((volatile unsigned int*)(0x42C90984UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A2 *((volatile unsigned int*)(0x42C90988UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A3 *((volatile unsigned int*)(0x42C9098CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A4 *((volatile unsigned int*)(0x42C90990UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A5 *((volatile unsigned int*)(0x42C90994UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A6 *((volatile unsigned int*)(0x42C90998UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A7 *((volatile unsigned int*)(0x42C9099CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A8 *((volatile unsigned int*)(0x42C909A0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A9 *((volatile unsigned int*)(0x42C909A4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A10 *((volatile unsigned int*)(0x42C909A8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A11 *((volatile unsigned int*)(0x42C909ACUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A12 *((volatile unsigned int*)(0x42C909B0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A13 *((volatile unsigned int*)(0x42C909B4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A14 *((volatile unsigned int*)(0x42C909B8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A15 *((volatile unsigned int*)(0x42C909BCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A16 *((volatile unsigned int*)(0x42C909C0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A17 *((volatile unsigned int*)(0x42C909C4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A18 *((volatile unsigned int*)(0x42C909C8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A19 *((volatile unsigned int*)(0x42C909CCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A20 *((volatile unsigned int*)(0x42C909D0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A21 *((volatile unsigned int*)(0x42C909D4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A22 *((volatile unsigned int*)(0x42C909D8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A23 *((volatile unsigned int*)(0x42C909DCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A24 *((volatile unsigned int*)(0x42C909E0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A25 *((volatile unsigned int*)(0x42C909E4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A26 *((volatile unsigned int*)(0x42C909E8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A27 *((volatile unsigned int*)(0x42C909ECUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A28 *((volatile unsigned int*)(0x42C909F0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A29 *((volatile unsigned int*)(0x42C909F4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A30 *((volatile unsigned int*)(0x42C909F8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A31 *((volatile unsigned int*)(0x42C909FCUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A32 *((volatile unsigned int*)(0x42C90A00UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A33 *((volatile unsigned int*)(0x42C90A04UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A34 *((volatile unsigned int*)(0x42C90A08UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A35 *((volatile unsigned int*)(0x42C90A0CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A36 *((volatile unsigned int*)(0x42C90A10UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A37 *((volatile unsigned int*)(0x42C90A14UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A38 *((volatile unsigned int*)(0x42C90A18UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A39 *((volatile unsigned int*)(0x42C90A1CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A40 *((volatile unsigned int*)(0x42C90A20UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A41 *((volatile unsigned int*)(0x42C90A24UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A42 *((volatile unsigned int*)(0x42C90A28UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A43 *((volatile unsigned int*)(0x42C90A2CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A44 *((volatile unsigned int*)(0x42C90A30UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A45 *((volatile unsigned int*)(0x42C90A34UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A46 *((volatile unsigned int*)(0x42C90A38UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A47 *((volatile unsigned int*)(0x42C90A3CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC0 *((volatile unsigned int*)(0x42C90A60UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC1 *((volatile unsigned int*)(0x42C90A64UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC2 *((volatile unsigned int*)(0x42C90A68UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC3 *((volatile unsigned int*)(0x42C90A6CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC4 *((volatile unsigned int*)(0x42C90A70UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC5 *((volatile unsigned int*)(0x42C90A74UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_SA *((volatile unsigned int*)(0x42C90A78UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_AE *((volatile unsigned int*)(0x42C90A7CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A0 *((volatile unsigned int*)(0x42C90A80UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A1 *((volatile unsigned int*)(0x42C90A84UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A2 *((volatile unsigned int*)(0x42C90A88UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A3 *((volatile unsigned int*)(0x42C90A8CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A4 *((volatile unsigned int*)(0x42C90A90UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A5 *((volatile unsigned int*)(0x42C90A94UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A6 *((volatile unsigned int*)(0x42C90A98UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A7 *((volatile unsigned int*)(0x42C90A9CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A8 *((volatile unsigned int*)(0x42C90AA0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A9 *((volatile unsigned int*)(0x42C90AA4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A10 *((volatile unsigned int*)(0x42C90AA8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A11 *((volatile unsigned int*)(0x42C90AACUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A12 *((volatile unsigned int*)(0x42C90AB0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A13 *((volatile unsigned int*)(0x42C90AB4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A14 *((volatile unsigned int*)(0x42C90AB8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A15 *((volatile unsigned int*)(0x42C90ABCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A16 *((volatile unsigned int*)(0x42C90AC0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A17 *((volatile unsigned int*)(0x42C90AC4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A18 *((volatile unsigned int*)(0x42C90AC8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A19 *((volatile unsigned int*)(0x42C90ACCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A20 *((volatile unsigned int*)(0x42C90AD0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A21 *((volatile unsigned int*)(0x42C90AD4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A22 *((volatile unsigned int*)(0x42C90AD8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A23 *((volatile unsigned int*)(0x42C90ADCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A24 *((volatile unsigned int*)(0x42C90AE0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A25 *((volatile unsigned int*)(0x42C90AE4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A26 *((volatile unsigned int*)(0x42C90AE8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A27 *((volatile unsigned int*)(0x42C90AECUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A28 *((volatile unsigned int*)(0x42C90AF0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A29 *((volatile unsigned int*)(0x42C90AF4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A30 *((volatile unsigned int*)(0x42C90AF8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A31 *((volatile unsigned int*)(0x42C90AFCUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A32 *((volatile unsigned int*)(0x42C90B00UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A33 *((volatile unsigned int*)(0x42C90B04UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A34 *((volatile unsigned int*)(0x42C90B08UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A35 *((volatile unsigned int*)(0x42C90B0CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A36 *((volatile unsigned int*)(0x42C90B10UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A37 *((volatile unsigned int*)(0x42C90B14UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A38 *((volatile unsigned int*)(0x42C90B18UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A39 *((volatile unsigned int*)(0x42C90B1CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A40 *((volatile unsigned int*)(0x42C90B20UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A41 *((volatile unsigned int*)(0x42C90B24UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A42 *((volatile unsigned int*)(0x42C90B28UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A43 *((volatile unsigned int*)(0x42C90B2CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A44 *((volatile unsigned int*)(0x42C90B30UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A45 *((volatile unsigned int*)(0x42C90B34UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A46 *((volatile unsigned int*)(0x42C90B38UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A47 *((volatile unsigned int*)(0x42C90B3CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC0 *((volatile unsigned int*)(0x42C90B60UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC1 *((volatile unsigned int*)(0x42C90B64UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC2 *((volatile unsigned int*)(0x42C90B68UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC3 *((volatile unsigned int*)(0x42C90B6CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC4 *((volatile unsigned int*)(0x42C90B70UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC5 *((volatile unsigned int*)(0x42C90B74UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_SA *((volatile unsigned int*)(0x42C90B78UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_AE *((volatile unsigned int*)(0x42C90B7CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A0 *((volatile unsigned int*)(0x42C90B80UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A1 *((volatile unsigned int*)(0x42C90B84UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A2 *((volatile unsigned int*)(0x42C90B88UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A3 *((volatile unsigned int*)(0x42C90B8CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A4 *((volatile unsigned int*)(0x42C90B90UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A5 *((volatile unsigned int*)(0x42C90B94UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A6 *((volatile unsigned int*)(0x42C90B98UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A7 *((volatile unsigned int*)(0x42C90B9CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A8 *((volatile unsigned int*)(0x42C90BA0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A9 *((volatile unsigned int*)(0x42C90BA4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A10 *((volatile unsigned int*)(0x42C90BA8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A11 *((volatile unsigned int*)(0x42C90BACUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A12 *((volatile unsigned int*)(0x42C90BB0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A13 *((volatile unsigned int*)(0x42C90BB4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A14 *((volatile unsigned int*)(0x42C90BB8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A15 *((volatile unsigned int*)(0x42C90BBCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A16 *((volatile unsigned int*)(0x42C90BC0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A17 *((volatile unsigned int*)(0x42C90BC4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A18 *((volatile unsigned int*)(0x42C90BC8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A19 *((volatile unsigned int*)(0x42C90BCCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A20 *((volatile unsigned int*)(0x42C90BD0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A21 *((volatile unsigned int*)(0x42C90BD4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A22 *((volatile unsigned int*)(0x42C90BD8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A23 *((volatile unsigned int*)(0x42C90BDCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A24 *((volatile unsigned int*)(0x42C90BE0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A25 *((volatile unsigned int*)(0x42C90BE4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A26 *((volatile unsigned int*)(0x42C90BE8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A27 *((volatile unsigned int*)(0x42C90BECUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A28 *((volatile unsigned int*)(0x42C90BF0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A29 *((volatile unsigned int*)(0x42C90BF4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A30 *((volatile unsigned int*)(0x42C90BF8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A31 *((volatile unsigned int*)(0x42C90BFCUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A32 *((volatile unsigned int*)(0x42C90C00UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A33 *((volatile unsigned int*)(0x42C90C04UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A34 *((volatile unsigned int*)(0x42C90C08UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A35 *((volatile unsigned int*)(0x42C90C0CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A36 *((volatile unsigned int*)(0x42C90C10UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A37 *((volatile unsigned int*)(0x42C90C14UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A38 *((volatile unsigned int*)(0x42C90C18UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A39 *((volatile unsigned int*)(0x42C90C1CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A40 *((volatile unsigned int*)(0x42C90C20UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A41 *((volatile unsigned int*)(0x42C90C24UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A42 *((volatile unsigned int*)(0x42C90C28UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A43 *((volatile unsigned int*)(0x42C90C2CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A44 *((volatile unsigned int*)(0x42C90C30UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A45 *((volatile unsigned int*)(0x42C90C34UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A46 *((volatile unsigned int*)(0x42C90C38UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A47 *((volatile unsigned int*)(0x42C90C3CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC0 *((volatile unsigned int*)(0x42C90C60UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC1 *((volatile unsigned int*)(0x42C90C64UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC2 *((volatile unsigned int*)(0x42C90C68UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC3 *((volatile unsigned int*)(0x42C90C6CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC4 *((volatile unsigned int*)(0x42C90C70UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC5 *((volatile unsigned int*)(0x42C90C74UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_SA *((volatile unsigned int*)(0x42C90C78UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_AE *((volatile unsigned int*)(0x42C90C7CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A0 *((volatile unsigned int*)(0x42C90C80UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A1 *((volatile unsigned int*)(0x42C90C84UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A2 *((volatile unsigned int*)(0x42C90C88UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A3 *((volatile unsigned int*)(0x42C90C8CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A4 *((volatile unsigned int*)(0x42C90C90UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A5 *((volatile unsigned int*)(0x42C90C94UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A6 *((volatile unsigned int*)(0x42C90C98UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A7 *((volatile unsigned int*)(0x42C90C9CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A8 *((volatile unsigned int*)(0x42C90CA0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A9 *((volatile unsigned int*)(0x42C90CA4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A10 *((volatile unsigned int*)(0x42C90CA8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A11 *((volatile unsigned int*)(0x42C90CACUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A12 *((volatile unsigned int*)(0x42C90CB0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A13 *((volatile unsigned int*)(0x42C90CB4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A14 *((volatile unsigned int*)(0x42C90CB8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A15 *((volatile unsigned int*)(0x42C90CBCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A16 *((volatile unsigned int*)(0x42C90CC0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A17 *((volatile unsigned int*)(0x42C90CC4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A18 *((volatile unsigned int*)(0x42C90CC8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A19 *((volatile unsigned int*)(0x42C90CCCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A20 *((volatile unsigned int*)(0x42C90CD0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A21 *((volatile unsigned int*)(0x42C90CD4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A22 *((volatile unsigned int*)(0x42C90CD8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A23 *((volatile unsigned int*)(0x42C90CDCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A24 *((volatile unsigned int*)(0x42C90CE0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A25 *((volatile unsigned int*)(0x42C90CE4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A26 *((volatile unsigned int*)(0x42C90CE8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A27 *((volatile unsigned int*)(0x42C90CECUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A28 *((volatile unsigned int*)(0x42C90CF0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A29 *((volatile unsigned int*)(0x42C90CF4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A30 *((volatile unsigned int*)(0x42C90CF8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A31 *((volatile unsigned int*)(0x42C90CFCUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A32 *((volatile unsigned int*)(0x42C90D00UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A33 *((volatile unsigned int*)(0x42C90D04UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A34 *((volatile unsigned int*)(0x42C90D08UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A35 *((volatile unsigned int*)(0x42C90D0CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A36 *((volatile unsigned int*)(0x42C90D10UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A37 *((volatile unsigned int*)(0x42C90D14UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A38 *((volatile unsigned int*)(0x42C90D18UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A39 *((volatile unsigned int*)(0x42C90D1CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A40 *((volatile unsigned int*)(0x42C90D20UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A41 *((volatile unsigned int*)(0x42C90D24UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A42 *((volatile unsigned int*)(0x42C90D28UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A43 *((volatile unsigned int*)(0x42C90D2CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A44 *((volatile unsigned int*)(0x42C90D30UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A45 *((volatile unsigned int*)(0x42C90D34UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A46 *((volatile unsigned int*)(0x42C90D38UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A47 *((volatile unsigned int*)(0x42C90D3CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC0 *((volatile unsigned int*)(0x42C90D60UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC1 *((volatile unsigned int*)(0x42C90D64UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC2 *((volatile unsigned int*)(0x42C90D68UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC3 *((volatile unsigned int*)(0x42C90D6CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC4 *((volatile unsigned int*)(0x42C90D70UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC5 *((volatile unsigned int*)(0x42C90D74UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_SA *((volatile unsigned int*)(0x42C90D78UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_AE *((volatile unsigned int*)(0x42C90D7CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A0 *((volatile unsigned int*)(0x42C90D80UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A1 *((volatile unsigned int*)(0x42C90D84UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A2 *((volatile unsigned int*)(0x42C90D88UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A3 *((volatile unsigned int*)(0x42C90D8CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A4 *((volatile unsigned int*)(0x42C90D90UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A5 *((volatile unsigned int*)(0x42C90D94UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A6 *((volatile unsigned int*)(0x42C90D98UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A7 *((volatile unsigned int*)(0x42C90D9CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A8 *((volatile unsigned int*)(0x42C90DA0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A9 *((volatile unsigned int*)(0x42C90DA4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A10 *((volatile unsigned int*)(0x42C90DA8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A11 *((volatile unsigned int*)(0x42C90DACUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A12 *((volatile unsigned int*)(0x42C90DB0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A13 *((volatile unsigned int*)(0x42C90DB4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A14 *((volatile unsigned int*)(0x42C90DB8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A15 *((volatile unsigned int*)(0x42C90DBCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A16 *((volatile unsigned int*)(0x42C90DC0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A17 *((volatile unsigned int*)(0x42C90DC4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A18 *((volatile unsigned int*)(0x42C90DC8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A19 *((volatile unsigned int*)(0x42C90DCCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A20 *((volatile unsigned int*)(0x42C90DD0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A21 *((volatile unsigned int*)(0x42C90DD4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A22 *((volatile unsigned int*)(0x42C90DD8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A23 *((volatile unsigned int*)(0x42C90DDCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A24 *((volatile unsigned int*)(0x42C90DE0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A25 *((volatile unsigned int*)(0x42C90DE4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A26 *((volatile unsigned int*)(0x42C90DE8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A27 *((volatile unsigned int*)(0x42C90DECUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A28 *((volatile unsigned int*)(0x42C90DF0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A29 *((volatile unsigned int*)(0x42C90DF4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A30 *((volatile unsigned int*)(0x42C90DF8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A31 *((volatile unsigned int*)(0x42C90DFCUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A32 *((volatile unsigned int*)(0x42C90E00UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A33 *((volatile unsigned int*)(0x42C90E04UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A34 *((volatile unsigned int*)(0x42C90E08UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A35 *((volatile unsigned int*)(0x42C90E0CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A36 *((volatile unsigned int*)(0x42C90E10UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A37 *((volatile unsigned int*)(0x42C90E14UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A38 *((volatile unsigned int*)(0x42C90E18UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A39 *((volatile unsigned int*)(0x42C90E1CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A40 *((volatile unsigned int*)(0x42C90E20UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A41 *((volatile unsigned int*)(0x42C90E24UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A42 *((volatile unsigned int*)(0x42C90E28UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A43 *((volatile unsigned int*)(0x42C90E2CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A44 *((volatile unsigned int*)(0x42C90E30UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A45 *((volatile unsigned int*)(0x42C90E34UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A46 *((volatile unsigned int*)(0x42C90E38UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A47 *((volatile unsigned int*)(0x42C90E3CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC0 *((volatile unsigned int*)(0x42C90E60UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC1 *((volatile unsigned int*)(0x42C90E64UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC2 *((volatile unsigned int*)(0x42C90E68UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC3 *((volatile unsigned int*)(0x42C90E6CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC4 *((volatile unsigned int*)(0x42C90E70UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC5 *((volatile unsigned int*)(0x42C90E74UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_SA *((volatile unsigned int*)(0x42C90E78UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_AE *((volatile unsigned int*)(0x42C90E7CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A0 *((volatile unsigned int*)(0x42C90E80UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A1 *((volatile unsigned int*)(0x42C90E84UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A2 *((volatile unsigned int*)(0x42C90E88UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A3 *((volatile unsigned int*)(0x42C90E8CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A4 *((volatile unsigned int*)(0x42C90E90UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A5 *((volatile unsigned int*)(0x42C90E94UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A6 *((volatile unsigned int*)(0x42C90E98UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A7 *((volatile unsigned int*)(0x42C90E9CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A8 *((volatile unsigned int*)(0x42C90EA0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A9 *((volatile unsigned int*)(0x42C90EA4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A10 *((volatile unsigned int*)(0x42C90EA8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A11 *((volatile unsigned int*)(0x42C90EACUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A12 *((volatile unsigned int*)(0x42C90EB0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A13 *((volatile unsigned int*)(0x42C90EB4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A14 *((volatile unsigned int*)(0x42C90EB8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A15 *((volatile unsigned int*)(0x42C90EBCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A16 *((volatile unsigned int*)(0x42C90EC0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A17 *((volatile unsigned int*)(0x42C90EC4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A18 *((volatile unsigned int*)(0x42C90EC8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A19 *((volatile unsigned int*)(0x42C90ECCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A20 *((volatile unsigned int*)(0x42C90ED0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A21 *((volatile unsigned int*)(0x42C90ED4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A22 *((volatile unsigned int*)(0x42C90ED8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A23 *((volatile unsigned int*)(0x42C90EDCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A24 *((volatile unsigned int*)(0x42C90EE0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A25 *((volatile unsigned int*)(0x42C90EE4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A26 *((volatile unsigned int*)(0x42C90EE8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A27 *((volatile unsigned int*)(0x42C90EECUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A28 *((volatile unsigned int*)(0x42C90EF0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A29 *((volatile unsigned int*)(0x42C90EF4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A30 *((volatile unsigned int*)(0x42C90EF8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A31 *((volatile unsigned int*)(0x42C90EFCUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A32 *((volatile unsigned int*)(0x42C90F00UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A33 *((volatile unsigned int*)(0x42C90F04UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A34 *((volatile unsigned int*)(0x42C90F08UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A35 *((volatile unsigned int*)(0x42C90F0CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A36 *((volatile unsigned int*)(0x42C90F10UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A37 *((volatile unsigned int*)(0x42C90F14UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A38 *((volatile unsigned int*)(0x42C90F18UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A39 *((volatile unsigned int*)(0x42C90F1CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A40 *((volatile unsigned int*)(0x42C90F20UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A41 *((volatile unsigned int*)(0x42C90F24UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A42 *((volatile unsigned int*)(0x42C90F28UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A43 *((volatile unsigned int*)(0x42C90F2CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A44 *((volatile unsigned int*)(0x42C90F30UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A45 *((volatile unsigned int*)(0x42C90F34UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A46 *((volatile unsigned int*)(0x42C90F38UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A47 *((volatile unsigned int*)(0x42C90F3CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC0 *((volatile unsigned int*)(0x42C90F60UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC1 *((volatile unsigned int*)(0x42C90F64UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC2 *((volatile unsigned int*)(0x42C90F68UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC3 *((volatile unsigned int*)(0x42C90F6CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC4 *((volatile unsigned int*)(0x42C90F70UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC5 *((volatile unsigned int*)(0x42C90F74UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_SA *((volatile unsigned int*)(0x42C90F78UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_AE *((volatile unsigned int*)(0x42C90F7CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A0 *((volatile unsigned int*)(0x42C90F80UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A1 *((volatile unsigned int*)(0x42C90F84UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A2 *((volatile unsigned int*)(0x42C90F88UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A3 *((volatile unsigned int*)(0x42C90F8CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A4 *((volatile unsigned int*)(0x42C90F90UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A5 *((volatile unsigned int*)(0x42C90F94UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A6 *((volatile unsigned int*)(0x42C90F98UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A7 *((volatile unsigned int*)(0x42C90F9CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A8 *((volatile unsigned int*)(0x42C90FA0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A9 *((volatile unsigned int*)(0x42C90FA4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A10 *((volatile unsigned int*)(0x42C90FA8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A11 *((volatile unsigned int*)(0x42C90FACUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A12 *((volatile unsigned int*)(0x42C90FB0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A13 *((volatile unsigned int*)(0x42C90FB4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A14 *((volatile unsigned int*)(0x42C90FB8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A15 *((volatile unsigned int*)(0x42C90FBCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A16 *((volatile unsigned int*)(0x42C90FC0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A17 *((volatile unsigned int*)(0x42C90FC4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A18 *((volatile unsigned int*)(0x42C90FC8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A19 *((volatile unsigned int*)(0x42C90FCCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A20 *((volatile unsigned int*)(0x42C90FD0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A21 *((volatile unsigned int*)(0x42C90FD4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A22 *((volatile unsigned int*)(0x42C90FD8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A23 *((volatile unsigned int*)(0x42C90FDCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A24 *((volatile unsigned int*)(0x42C90FE0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A25 *((volatile unsigned int*)(0x42C90FE4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A26 *((volatile unsigned int*)(0x42C90FE8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A27 *((volatile unsigned int*)(0x42C90FECUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A28 *((volatile unsigned int*)(0x42C90FF0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A29 *((volatile unsigned int*)(0x42C90FF4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A30 *((volatile unsigned int*)(0x42C90FF8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A31 *((volatile unsigned int*)(0x42C90FFCUL)) -#define bFM3_ETHERNET_MAC0_BMR_SWR *((volatile unsigned int*)(0x42CA0000UL)) -#define bFM3_ETHERNET_MAC0_BMR_DA *((volatile unsigned int*)(0x42CA0004UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL0 *((volatile unsigned int*)(0x42CA0008UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL1 *((volatile unsigned int*)(0x42CA000CUL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL2 *((volatile unsigned int*)(0x42CA0010UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL3 *((volatile unsigned int*)(0x42CA0014UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL4 *((volatile unsigned int*)(0x42CA0018UL)) -#define bFM3_ETHERNET_MAC0_BMR_ATDS *((volatile unsigned int*)(0x42CA001CUL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL0 *((volatile unsigned int*)(0x42CA0020UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL1 *((volatile unsigned int*)(0x42CA0024UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL2 *((volatile unsigned int*)(0x42CA0028UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL3 *((volatile unsigned int*)(0x42CA002CUL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL4 *((volatile unsigned int*)(0x42CA0030UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL5 *((volatile unsigned int*)(0x42CA0034UL)) -#define bFM3_ETHERNET_MAC0_BMR_PR0 *((volatile unsigned int*)(0x42CA0038UL)) -#define bFM3_ETHERNET_MAC0_BMR_PR1 *((volatile unsigned int*)(0x42CA003CUL)) -#define bFM3_ETHERNET_MAC0_BMR_FB *((volatile unsigned int*)(0x42CA0040UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL0 *((volatile unsigned int*)(0x42CA0044UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL1 *((volatile unsigned int*)(0x42CA0048UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL2 *((volatile unsigned int*)(0x42CA004CUL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL3 *((volatile unsigned int*)(0x42CA0050UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL4 *((volatile unsigned int*)(0x42CA0054UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL5 *((volatile unsigned int*)(0x42CA0058UL)) -#define bFM3_ETHERNET_MAC0_BMR_USP *((volatile unsigned int*)(0x42CA005CUL)) -#define bFM3_ETHERNET_MAC0_BMR_8XPBL *((volatile unsigned int*)(0x42CA0060UL)) -#define bFM3_ETHERNET_MAC0_BMR_AAL *((volatile unsigned int*)(0x42CA0064UL)) -#define bFM3_ETHERNET_MAC0_BMR_MB *((volatile unsigned int*)(0x42CA0068UL)) -#define bFM3_ETHERNET_MAC0_BMR_TXPR *((volatile unsigned int*)(0x42CA006CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD0 *((volatile unsigned int*)(0x42CA0080UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD1 *((volatile unsigned int*)(0x42CA0084UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD2 *((volatile unsigned int*)(0x42CA0088UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD3 *((volatile unsigned int*)(0x42CA008CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD4 *((volatile unsigned int*)(0x42CA0090UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD5 *((volatile unsigned int*)(0x42CA0094UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD6 *((volatile unsigned int*)(0x42CA0098UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD7 *((volatile unsigned int*)(0x42CA009CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD8 *((volatile unsigned int*)(0x42CA00A0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD9 *((volatile unsigned int*)(0x42CA00A4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD10 *((volatile unsigned int*)(0x42CA00A8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD11 *((volatile unsigned int*)(0x42CA00ACUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD12 *((volatile unsigned int*)(0x42CA00B0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD13 *((volatile unsigned int*)(0x42CA00B4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD14 *((volatile unsigned int*)(0x42CA00B8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD15 *((volatile unsigned int*)(0x42CA00BCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD16 *((volatile unsigned int*)(0x42CA00C0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD17 *((volatile unsigned int*)(0x42CA00C4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD18 *((volatile unsigned int*)(0x42CA00C8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD19 *((volatile unsigned int*)(0x42CA00CCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD20 *((volatile unsigned int*)(0x42CA00D0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD21 *((volatile unsigned int*)(0x42CA00D4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD22 *((volatile unsigned int*)(0x42CA00D8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD23 *((volatile unsigned int*)(0x42CA00DCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD24 *((volatile unsigned int*)(0x42CA00E0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD25 *((volatile unsigned int*)(0x42CA00E4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD26 *((volatile unsigned int*)(0x42CA00E8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD27 *((volatile unsigned int*)(0x42CA00ECUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD28 *((volatile unsigned int*)(0x42CA00F0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD29 *((volatile unsigned int*)(0x42CA00F4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD30 *((volatile unsigned int*)(0x42CA00F8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD31 *((volatile unsigned int*)(0x42CA00FCUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD0 *((volatile unsigned int*)(0x42CA0100UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD1 *((volatile unsigned int*)(0x42CA0104UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD2 *((volatile unsigned int*)(0x42CA0108UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD3 *((volatile unsigned int*)(0x42CA010CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD4 *((volatile unsigned int*)(0x42CA0110UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD5 *((volatile unsigned int*)(0x42CA0114UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD6 *((volatile unsigned int*)(0x42CA0118UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD7 *((volatile unsigned int*)(0x42CA011CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD8 *((volatile unsigned int*)(0x42CA0120UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD9 *((volatile unsigned int*)(0x42CA0124UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD10 *((volatile unsigned int*)(0x42CA0128UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD11 *((volatile unsigned int*)(0x42CA012CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD12 *((volatile unsigned int*)(0x42CA0130UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD13 *((volatile unsigned int*)(0x42CA0134UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD14 *((volatile unsigned int*)(0x42CA0138UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD15 *((volatile unsigned int*)(0x42CA013CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD16 *((volatile unsigned int*)(0x42CA0140UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD17 *((volatile unsigned int*)(0x42CA0144UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD18 *((volatile unsigned int*)(0x42CA0148UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD19 *((volatile unsigned int*)(0x42CA014CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD20 *((volatile unsigned int*)(0x42CA0150UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD21 *((volatile unsigned int*)(0x42CA0154UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD22 *((volatile unsigned int*)(0x42CA0158UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD23 *((volatile unsigned int*)(0x42CA015CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD24 *((volatile unsigned int*)(0x42CA0160UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD25 *((volatile unsigned int*)(0x42CA0164UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD26 *((volatile unsigned int*)(0x42CA0168UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD27 *((volatile unsigned int*)(0x42CA016CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD28 *((volatile unsigned int*)(0x42CA0170UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD29 *((volatile unsigned int*)(0x42CA0174UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD30 *((volatile unsigned int*)(0x42CA0178UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD31 *((volatile unsigned int*)(0x42CA017CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL2 *((volatile unsigned int*)(0x42CA0188UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL3 *((volatile unsigned int*)(0x42CA018CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL4 *((volatile unsigned int*)(0x42CA0190UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL5 *((volatile unsigned int*)(0x42CA0194UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL6 *((volatile unsigned int*)(0x42CA0198UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL7 *((volatile unsigned int*)(0x42CA019CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL8 *((volatile unsigned int*)(0x42CA01A0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL9 *((volatile unsigned int*)(0x42CA01A4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL10 *((volatile unsigned int*)(0x42CA01A8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL11 *((volatile unsigned int*)(0x42CA01ACUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL12 *((volatile unsigned int*)(0x42CA01B0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL13 *((volatile unsigned int*)(0x42CA01B4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL14 *((volatile unsigned int*)(0x42CA01B8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL15 *((volatile unsigned int*)(0x42CA01BCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL16 *((volatile unsigned int*)(0x42CA01C0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL17 *((volatile unsigned int*)(0x42CA01C4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL18 *((volatile unsigned int*)(0x42CA01C8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL19 *((volatile unsigned int*)(0x42CA01CCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL20 *((volatile unsigned int*)(0x42CA01D0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL21 *((volatile unsigned int*)(0x42CA01D4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL22 *((volatile unsigned int*)(0x42CA01D8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL23 *((volatile unsigned int*)(0x42CA01DCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL24 *((volatile unsigned int*)(0x42CA01E0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL25 *((volatile unsigned int*)(0x42CA01E4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL26 *((volatile unsigned int*)(0x42CA01E8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL27 *((volatile unsigned int*)(0x42CA01ECUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL28 *((volatile unsigned int*)(0x42CA01F0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL29 *((volatile unsigned int*)(0x42CA01F4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL30 *((volatile unsigned int*)(0x42CA01F8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL31 *((volatile unsigned int*)(0x42CA01FCUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL2 *((volatile unsigned int*)(0x42CA0208UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL3 *((volatile unsigned int*)(0x42CA020CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL4 *((volatile unsigned int*)(0x42CA0210UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL5 *((volatile unsigned int*)(0x42CA0214UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL6 *((volatile unsigned int*)(0x42CA0218UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL7 *((volatile unsigned int*)(0x42CA021CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL8 *((volatile unsigned int*)(0x42CA0220UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL9 *((volatile unsigned int*)(0x42CA0224UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL10 *((volatile unsigned int*)(0x42CA0228UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL11 *((volatile unsigned int*)(0x42CA022CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL12 *((volatile unsigned int*)(0x42CA0230UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL13 *((volatile unsigned int*)(0x42CA0234UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL14 *((volatile unsigned int*)(0x42CA0238UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL15 *((volatile unsigned int*)(0x42CA023CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL16 *((volatile unsigned int*)(0x42CA0240UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL17 *((volatile unsigned int*)(0x42CA0244UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL18 *((volatile unsigned int*)(0x42CA0248UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL19 *((volatile unsigned int*)(0x42CA024CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL20 *((volatile unsigned int*)(0x42CA0250UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL21 *((volatile unsigned int*)(0x42CA0254UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL22 *((volatile unsigned int*)(0x42CA0258UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL23 *((volatile unsigned int*)(0x42CA025CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL24 *((volatile unsigned int*)(0x42CA0260UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL25 *((volatile unsigned int*)(0x42CA0264UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL26 *((volatile unsigned int*)(0x42CA0268UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL27 *((volatile unsigned int*)(0x42CA026CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL28 *((volatile unsigned int*)(0x42CA0270UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL29 *((volatile unsigned int*)(0x42CA0274UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL30 *((volatile unsigned int*)(0x42CA0278UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL31 *((volatile unsigned int*)(0x42CA027CUL)) -#define bFM3_ETHERNET_MAC0_SR_TI *((volatile unsigned int*)(0x42CA0280UL)) -#define bFM3_ETHERNET_MAC0_SR_TPS *((volatile unsigned int*)(0x42CA0284UL)) -#define bFM3_ETHERNET_MAC0_SR_TU *((volatile unsigned int*)(0x42CA0288UL)) -#define bFM3_ETHERNET_MAC0_SR_TJT *((volatile unsigned int*)(0x42CA028CUL)) -#define bFM3_ETHERNET_MAC0_SR_OVF *((volatile unsigned int*)(0x42CA0290UL)) -#define bFM3_ETHERNET_MAC0_SR_UNF *((volatile unsigned int*)(0x42CA0294UL)) -#define bFM3_ETHERNET_MAC0_SR_RI *((volatile unsigned int*)(0x42CA0298UL)) -#define bFM3_ETHERNET_MAC0_SR_RU *((volatile unsigned int*)(0x42CA029CUL)) -#define bFM3_ETHERNET_MAC0_SR_RPS *((volatile unsigned int*)(0x42CA02A0UL)) -#define bFM3_ETHERNET_MAC0_SR_RWT *((volatile unsigned int*)(0x42CA02A4UL)) -#define bFM3_ETHERNET_MAC0_SR_ETI *((volatile unsigned int*)(0x42CA02A8UL)) -#define bFM3_ETHERNET_MAC0_SR_FBI *((volatile unsigned int*)(0x42CA02B4UL)) -#define bFM3_ETHERNET_MAC0_SR_ERI *((volatile unsigned int*)(0x42CA02B8UL)) -#define bFM3_ETHERNET_MAC0_SR_AIS *((volatile unsigned int*)(0x42CA02BCUL)) -#define bFM3_ETHERNET_MAC0_SR_NIS *((volatile unsigned int*)(0x42CA02C0UL)) -#define bFM3_ETHERNET_MAC0_SR_RS0 *((volatile unsigned int*)(0x42CA02C4UL)) -#define bFM3_ETHERNET_MAC0_SR_RS1 *((volatile unsigned int*)(0x42CA02C8UL)) -#define bFM3_ETHERNET_MAC0_SR_RS2 *((volatile unsigned int*)(0x42CA02CCUL)) -#define bFM3_ETHERNET_MAC0_SR_TS0 *((volatile unsigned int*)(0x42CA02D0UL)) -#define bFM3_ETHERNET_MAC0_SR_TS1 *((volatile unsigned int*)(0x42CA02D4UL)) -#define bFM3_ETHERNET_MAC0_SR_TS2 *((volatile unsigned int*)(0x42CA02D8UL)) -#define bFM3_ETHERNET_MAC0_SR_EB0 *((volatile unsigned int*)(0x42CA02DCUL)) -#define bFM3_ETHERNET_MAC0_SR_EB1 *((volatile unsigned int*)(0x42CA02E0UL)) -#define bFM3_ETHERNET_MAC0_SR_EB2 *((volatile unsigned int*)(0x42CA02E4UL)) -#define bFM3_ETHERNET_MAC0_SR_GLI *((volatile unsigned int*)(0x42CA02E8UL)) -#define bFM3_ETHERNET_MAC0_SR_GMI *((volatile unsigned int*)(0x42CA02ECUL)) -#define bFM3_ETHERNET_MAC0_SR_GPI *((volatile unsigned int*)(0x42CA02F0UL)) -#define bFM3_ETHERNET_MAC0_SR_TTI *((volatile unsigned int*)(0x42CA02F4UL)) -#define bFM3_ETHERNET_MAC0_SR_GLPII *((volatile unsigned int*)(0x42CA02F8UL)) -#define bFM3_ETHERNET_MAC0_OMR_SR *((volatile unsigned int*)(0x42CA0304UL)) -#define bFM3_ETHERNET_MAC0_OMR_OSF *((volatile unsigned int*)(0x42CA0308UL)) -#define bFM3_ETHERNET_MAC0_OMR_RTC0 *((volatile unsigned int*)(0x42CA030CUL)) -#define bFM3_ETHERNET_MAC0_OMR_RTC1 *((volatile unsigned int*)(0x42CA0310UL)) -#define bFM3_ETHERNET_MAC0_OMR_FUF *((volatile unsigned int*)(0x42CA0318UL)) -#define bFM3_ETHERNET_MAC0_OMR_FEF *((volatile unsigned int*)(0x42CA031CUL)) -#define bFM3_ETHERNET_MAC0_OMR_ST *((volatile unsigned int*)(0x42CA0334UL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC0 *((volatile unsigned int*)(0x42CA0338UL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC1 *((volatile unsigned int*)(0x42CA033CUL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC2 *((volatile unsigned int*)(0x42CA0340UL)) -#define bFM3_ETHERNET_MAC0_OMR_FTF *((volatile unsigned int*)(0x42CA0350UL)) -#define bFM3_ETHERNET_MAC0_OMR_TSF *((volatile unsigned int*)(0x42CA0354UL)) -#define bFM3_ETHERNET_MAC0_OMR_DFF *((volatile unsigned int*)(0x42CA0360UL)) -#define bFM3_ETHERNET_MAC0_OMR_RSF *((volatile unsigned int*)(0x42CA0364UL)) -#define bFM3_ETHERNET_MAC0_OMR_DT *((volatile unsigned int*)(0x42CA0368UL)) -#define bFM3_ETHERNET_MAC0_IER_TIE *((volatile unsigned int*)(0x42CA0380UL)) -#define bFM3_ETHERNET_MAC0_IER_TSE *((volatile unsigned int*)(0x42CA0384UL)) -#define bFM3_ETHERNET_MAC0_IER_TUE *((volatile unsigned int*)(0x42CA0388UL)) -#define bFM3_ETHERNET_MAC0_IER_TJE *((volatile unsigned int*)(0x42CA038CUL)) -#define bFM3_ETHERNET_MAC0_IER_OVE *((volatile unsigned int*)(0x42CA0390UL)) -#define bFM3_ETHERNET_MAC0_IER_UNE *((volatile unsigned int*)(0x42CA0394UL)) -#define bFM3_ETHERNET_MAC0_IER_RIE *((volatile unsigned int*)(0x42CA0398UL)) -#define bFM3_ETHERNET_MAC0_IER_RUE *((volatile unsigned int*)(0x42CA039CUL)) -#define bFM3_ETHERNET_MAC0_IER_RSE *((volatile unsigned int*)(0x42CA03A0UL)) -#define bFM3_ETHERNET_MAC0_IER_RWE *((volatile unsigned int*)(0x42CA03A4UL)) -#define bFM3_ETHERNET_MAC0_IER_ETE *((volatile unsigned int*)(0x42CA03A8UL)) -#define bFM3_ETHERNET_MAC0_IER_FBE *((volatile unsigned int*)(0x42CA03B4UL)) -#define bFM3_ETHERNET_MAC0_IER_ERE *((volatile unsigned int*)(0x42CA03B8UL)) -#define bFM3_ETHERNET_MAC0_IER_AIE *((volatile unsigned int*)(0x42CA03BCUL)) -#define bFM3_ETHERNET_MAC0_IER_NIE *((volatile unsigned int*)(0x42CA03C0UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42CA0400UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42CA0404UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42CA0408UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42CA040CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42CA0410UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42CA0414UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42CA0418UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42CA041CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42CA0420UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42CA0424UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42CA0428UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42CA042CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42CA0430UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42CA0434UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42CA0438UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42CA043CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH *((volatile unsigned int*)(0x42CA0440UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42CA0444UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42CA0448UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42CA044CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42CA0450UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42CA0454UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42CA0458UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42CA045CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42CA0460UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42CA0464UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42CA0468UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42CA046CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF *((volatile unsigned int*)(0x42CA0470UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0 *((volatile unsigned int*)(0x42CA0480UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1 *((volatile unsigned int*)(0x42CA0484UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2 *((volatile unsigned int*)(0x42CA0488UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3 *((volatile unsigned int*)(0x42CA048CUL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4 *((volatile unsigned int*)(0x42CA0490UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5 *((volatile unsigned int*)(0x42CA0494UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6 *((volatile unsigned int*)(0x42CA0498UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7 *((volatile unsigned int*)(0x42CA049CUL)) -#define bFM3_ETHERNET_MAC0_AHBSR_AHBS *((volatile unsigned int*)(0x42CA0580UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42CA0900UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42CA0904UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42CA0908UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42CA090CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42CA0910UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42CA0914UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42CA0918UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42CA091CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42CA0920UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42CA0924UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42CA0928UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42CA092CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42CA0930UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42CA0934UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42CA0938UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42CA093CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42CA0940UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42CA0944UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42CA0948UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42CA094CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42CA0950UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42CA0954UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42CA0958UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42CA095CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42CA0960UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42CA0964UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42CA0968UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42CA096CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42CA0970UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42CA0974UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42CA0978UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42CA097CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42CA0980UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42CA0984UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42CA0988UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42CA098CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42CA0990UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42CA0994UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42CA0998UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42CA099CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42CA09A0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42CA09A4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42CA09A8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42CA09ACUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42CA09B0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42CA09B4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42CA09B8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42CA09BCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42CA09C0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42CA09C4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42CA09C8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42CA09CCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42CA09D0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42CA09D4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42CA09D8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42CA09DCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42CA09E0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42CA09E4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42CA09E8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42CA09ECUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42CA09F0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42CA09F4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42CA09F8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42CA09FCUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42CA0A00UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42CA0A04UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42CA0A08UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42CA0A0CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42CA0A10UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42CA0A14UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42CA0A18UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42CA0A1CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42CA0A20UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42CA0A24UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42CA0A28UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42CA0A2CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42CA0A30UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42CA0A34UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42CA0A38UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42CA0A3CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42CA0A40UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42CA0A44UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42CA0A48UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42CA0A4CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42CA0A50UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42CA0A54UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42CA0A58UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42CA0A5CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42CA0A60UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42CA0A64UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42CA0A68UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42CA0A6CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42CA0A70UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42CA0A74UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42CA0A78UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42CA0A7CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42CA0A80UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42CA0A84UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42CA0A88UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42CA0A8CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42CA0A90UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42CA0A94UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42CA0A98UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42CA0A9CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42CA0AA0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42CA0AA4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42CA0AA8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42CA0AACUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42CA0AB0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42CA0AB4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42CA0AB8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42CA0ABCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42CA0AC0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42CA0AC4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42CA0AC8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42CA0ACCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42CA0AD0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42CA0AD4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42CA0AD8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42CA0ADCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42CA0AE0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42CA0AE4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42CA0AE8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42CA0AECUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42CA0AF0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42CA0AF4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42CA0AF8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42CA0AFCUL)) - -/* ETHERNET-MAC-CONTROL registers */ -#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE *((volatile unsigned int*)(0x42CC0000UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0 *((volatile unsigned int*)(0x42CC0020UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1 *((volatile unsigned int*)(0x42CC0024UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL *((volatile unsigned int*)(0x42CC0070UL)) -#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0 *((volatile unsigned int*)(0x42CC0100UL)) -#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1 *((volatile unsigned int*)(0x42CC0104UL)) - -/* ETHERNET-MAC1 registers*/ -#define bFM3_ETHERNET_MAC1_MCR_RE *((volatile unsigned int*)(0x42CE0008UL)) -#define bFM3_ETHERNET_MAC1_MCR_TE *((volatile unsigned int*)(0x42CE000CUL)) -#define bFM3_ETHERNET_MAC1_MCR_DC *((volatile unsigned int*)(0x42CE0010UL)) -#define bFM3_ETHERNET_MAC1_MCR_BL0 *((volatile unsigned int*)(0x42CE0014UL)) -#define bFM3_ETHERNET_MAC1_MCR_BL1 *((volatile unsigned int*)(0x42CE0018UL)) -#define bFM3_ETHERNET_MAC1_MCR_ACS *((volatile unsigned int*)(0x42CE001CUL)) -#define bFM3_ETHERNET_MAC1_MCR_LUD *((volatile unsigned int*)(0x42CE0020UL)) -#define bFM3_ETHERNET_MAC1_MCR_DR *((volatile unsigned int*)(0x42CE0024UL)) -#define bFM3_ETHERNET_MAC1_MCR_IPC *((volatile unsigned int*)(0x42CE0028UL)) -#define bFM3_ETHERNET_MAC1_MCR_DM *((volatile unsigned int*)(0x42CE002CUL)) -#define bFM3_ETHERNET_MAC1_MCR_LM *((volatile unsigned int*)(0x42CE0030UL)) -#define bFM3_ETHERNET_MAC1_MCR_DO *((volatile unsigned int*)(0x42CE0034UL)) -#define bFM3_ETHERNET_MAC1_MCR_FES *((volatile unsigned int*)(0x42CE0038UL)) -#define bFM3_ETHERNET_MAC1_MCR_PS *((volatile unsigned int*)(0x42CE003CUL)) -#define bFM3_ETHERNET_MAC1_MCR_DCRS *((volatile unsigned int*)(0x42CE0040UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG0 *((volatile unsigned int*)(0x42CE0044UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG1 *((volatile unsigned int*)(0x42CE0048UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG2 *((volatile unsigned int*)(0x42CE004CUL)) -#define bFM3_ETHERNET_MAC1_MCR_JE *((volatile unsigned int*)(0x42CE0050UL)) -#define bFM3_ETHERNET_MAC1_MCR_BE *((volatile unsigned int*)(0x42CE0054UL)) -#define bFM3_ETHERNET_MAC1_MCR_JD *((volatile unsigned int*)(0x42CE0058UL)) -#define bFM3_ETHERNET_MAC1_MCR_WD *((volatile unsigned int*)(0x42CE005CUL)) -#define bFM3_ETHERNET_MAC1_MCR_TC *((volatile unsigned int*)(0x42CE0060UL)) -#define bFM3_ETHERNET_MAC1_MCR_CST *((volatile unsigned int*)(0x42CE0064UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PR *((volatile unsigned int*)(0x42CE0080UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HUC *((volatile unsigned int*)(0x42CE0084UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HMC *((volatile unsigned int*)(0x42CE0088UL)) -#define bFM3_ETHERNET_MAC1_MFFR_DAIF *((volatile unsigned int*)(0x42CE008CUL)) -#define bFM3_ETHERNET_MAC1_MFFR_PM *((volatile unsigned int*)(0x42CE0090UL)) -#define bFM3_ETHERNET_MAC1_MFFR_DB *((volatile unsigned int*)(0x42CE0094UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PCF0 *((volatile unsigned int*)(0x42CE0098UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PCF1 *((volatile unsigned int*)(0x42CE009CUL)) -#define bFM3_ETHERNET_MAC1_MFFR_SAIF *((volatile unsigned int*)(0x42CE00A0UL)) -#define bFM3_ETHERNET_MAC1_MFFR_SAF *((volatile unsigned int*)(0x42CE00A4UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HPF *((volatile unsigned int*)(0x42CE00A8UL)) -#define bFM3_ETHERNET_MAC1_MFFR_RA *((volatile unsigned int*)(0x42CE00FCUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH0 *((volatile unsigned int*)(0x42CE0100UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH1 *((volatile unsigned int*)(0x42CE0104UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH2 *((volatile unsigned int*)(0x42CE0108UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH3 *((volatile unsigned int*)(0x42CE010CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH4 *((volatile unsigned int*)(0x42CE0110UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH5 *((volatile unsigned int*)(0x42CE0114UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH6 *((volatile unsigned int*)(0x42CE0118UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH7 *((volatile unsigned int*)(0x42CE011CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH8 *((volatile unsigned int*)(0x42CE0120UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH9 *((volatile unsigned int*)(0x42CE0124UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH10 *((volatile unsigned int*)(0x42CE0128UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH11 *((volatile unsigned int*)(0x42CE012CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH12 *((volatile unsigned int*)(0x42CE0130UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH13 *((volatile unsigned int*)(0x42CE0134UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH14 *((volatile unsigned int*)(0x42CE0138UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH15 *((volatile unsigned int*)(0x42CE013CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH16 *((volatile unsigned int*)(0x42CE0140UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH17 *((volatile unsigned int*)(0x42CE0144UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH18 *((volatile unsigned int*)(0x42CE0148UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH19 *((volatile unsigned int*)(0x42CE014CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH20 *((volatile unsigned int*)(0x42CE0150UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH21 *((volatile unsigned int*)(0x42CE0154UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH22 *((volatile unsigned int*)(0x42CE0158UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH23 *((volatile unsigned int*)(0x42CE015CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH24 *((volatile unsigned int*)(0x42CE0160UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH25 *((volatile unsigned int*)(0x42CE0164UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH26 *((volatile unsigned int*)(0x42CE0168UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH27 *((volatile unsigned int*)(0x42CE016CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH28 *((volatile unsigned int*)(0x42CE0170UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH29 *((volatile unsigned int*)(0x42CE0174UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH30 *((volatile unsigned int*)(0x42CE0178UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH31 *((volatile unsigned int*)(0x42CE017CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL0 *((volatile unsigned int*)(0x42CE0180UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL1 *((volatile unsigned int*)(0x42CE0184UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL2 *((volatile unsigned int*)(0x42CE0188UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL3 *((volatile unsigned int*)(0x42CE018CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL4 *((volatile unsigned int*)(0x42CE0190UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL5 *((volatile unsigned int*)(0x42CE0194UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL6 *((volatile unsigned int*)(0x42CE0198UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL7 *((volatile unsigned int*)(0x42CE019CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL8 *((volatile unsigned int*)(0x42CE01A0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL9 *((volatile unsigned int*)(0x42CE01A4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL10 *((volatile unsigned int*)(0x42CE01A8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL11 *((volatile unsigned int*)(0x42CE01ACUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL12 *((volatile unsigned int*)(0x42CE01B0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL13 *((volatile unsigned int*)(0x42CE01B4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL14 *((volatile unsigned int*)(0x42CE01B8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL15 *((volatile unsigned int*)(0x42CE01BCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL16 *((volatile unsigned int*)(0x42CE01C0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL17 *((volatile unsigned int*)(0x42CE01C4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL18 *((volatile unsigned int*)(0x42CE01C8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL19 *((volatile unsigned int*)(0x42CE01CCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL20 *((volatile unsigned int*)(0x42CE01D0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL21 *((volatile unsigned int*)(0x42CE01D4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL22 *((volatile unsigned int*)(0x42CE01D8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL23 *((volatile unsigned int*)(0x42CE01DCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL24 *((volatile unsigned int*)(0x42CE01E0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL25 *((volatile unsigned int*)(0x42CE01E4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL26 *((volatile unsigned int*)(0x42CE01E8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL27 *((volatile unsigned int*)(0x42CE01ECUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL28 *((volatile unsigned int*)(0x42CE01F0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL29 *((volatile unsigned int*)(0x42CE01F4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL30 *((volatile unsigned int*)(0x42CE01F8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL31 *((volatile unsigned int*)(0x42CE01FCUL)) -#define bFM3_ETHERNET_MAC1_GAR_GB *((volatile unsigned int*)(0x42CE0200UL)) -#define bFM3_ETHERNET_MAC1_GAR_GW *((volatile unsigned int*)(0x42CE0204UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR0 *((volatile unsigned int*)(0x42CE0208UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR1 *((volatile unsigned int*)(0x42CE020CUL)) -#define bFM3_ETHERNET_MAC1_GAR_CR2 *((volatile unsigned int*)(0x42CE0210UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR3 *((volatile unsigned int*)(0x42CE0214UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR0 *((volatile unsigned int*)(0x42CE0218UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR1 *((volatile unsigned int*)(0x42CE021CUL)) -#define bFM3_ETHERNET_MAC1_GAR_GR2 *((volatile unsigned int*)(0x42CE0220UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR3 *((volatile unsigned int*)(0x42CE0224UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR4 *((volatile unsigned int*)(0x42CE0228UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA0 *((volatile unsigned int*)(0x42CE022CUL)) -#define bFM3_ETHERNET_MAC1_GAR_PA1 *((volatile unsigned int*)(0x42CE0230UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA2 *((volatile unsigned int*)(0x42CE0234UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA3 *((volatile unsigned int*)(0x42CE0238UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA4 *((volatile unsigned int*)(0x42CE023CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD0 *((volatile unsigned int*)(0x42CE0280UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD1 *((volatile unsigned int*)(0x42CE0284UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD2 *((volatile unsigned int*)(0x42CE0288UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD3 *((volatile unsigned int*)(0x42CE028CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD4 *((volatile unsigned int*)(0x42CE0290UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD5 *((volatile unsigned int*)(0x42CE0294UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD6 *((volatile unsigned int*)(0x42CE0298UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD7 *((volatile unsigned int*)(0x42CE029CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD8 *((volatile unsigned int*)(0x42CE02A0UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD9 *((volatile unsigned int*)(0x42CE02A4UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD10 *((volatile unsigned int*)(0x42CE02A8UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD11 *((volatile unsigned int*)(0x42CE02ACUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD12 *((volatile unsigned int*)(0x42CE02B0UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD13 *((volatile unsigned int*)(0x42CE02B4UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD14 *((volatile unsigned int*)(0x42CE02B8UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD15 *((volatile unsigned int*)(0x42CE02BCUL)) -#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA *((volatile unsigned int*)(0x42CE0300UL)) -#define bFM3_ETHERNET_MAC1_FCR_TFE *((volatile unsigned int*)(0x42CE0304UL)) -#define bFM3_ETHERNET_MAC1_FCR_RFE *((volatile unsigned int*)(0x42CE0308UL)) -#define bFM3_ETHERNET_MAC1_FCR_UP *((volatile unsigned int*)(0x42CE030CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PLT0 *((volatile unsigned int*)(0x42CE0310UL)) -#define bFM3_ETHERNET_MAC1_FCR_PLT1 *((volatile unsigned int*)(0x42CE0314UL)) -#define bFM3_ETHERNET_MAC1_FCR_DZPQ *((volatile unsigned int*)(0x42CE031CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT0 *((volatile unsigned int*)(0x42CE0340UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT1 *((volatile unsigned int*)(0x42CE0344UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT2 *((volatile unsigned int*)(0x42CE0348UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT3 *((volatile unsigned int*)(0x42CE034CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT4 *((volatile unsigned int*)(0x42CE0350UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT5 *((volatile unsigned int*)(0x42CE0354UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT6 *((volatile unsigned int*)(0x42CE0358UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT7 *((volatile unsigned int*)(0x42CE035CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT8 *((volatile unsigned int*)(0x42CE0360UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT9 *((volatile unsigned int*)(0x42CE0364UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT10 *((volatile unsigned int*)(0x42CE0368UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT11 *((volatile unsigned int*)(0x42CE036CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT12 *((volatile unsigned int*)(0x42CE0370UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT13 *((volatile unsigned int*)(0x42CE0374UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT14 *((volatile unsigned int*)(0x42CE0378UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT15 *((volatile unsigned int*)(0x42CE037CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL0 *((volatile unsigned int*)(0x42CE0380UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL1 *((volatile unsigned int*)(0x42CE0384UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL2 *((volatile unsigned int*)(0x42CE0388UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL3 *((volatile unsigned int*)(0x42CE038CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL4 *((volatile unsigned int*)(0x42CE0390UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL5 *((volatile unsigned int*)(0x42CE0394UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL6 *((volatile unsigned int*)(0x42CE0398UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL7 *((volatile unsigned int*)(0x42CE039CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL8 *((volatile unsigned int*)(0x42CE03A0UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL9 *((volatile unsigned int*)(0x42CE03A4UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL10 *((volatile unsigned int*)(0x42CE03A8UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL11 *((volatile unsigned int*)(0x42CE03ACUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL12 *((volatile unsigned int*)(0x42CE03B0UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL13 *((volatile unsigned int*)(0x42CE03B4UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL14 *((volatile unsigned int*)(0x42CE03B8UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL15 *((volatile unsigned int*)(0x42CE03BCUL)) -#define bFM3_ETHERNET_MAC1_VTR_ETV *((volatile unsigned int*)(0x42CE03C0UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42CE0500UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42CE0504UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42CE0508UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42CE050CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42CE0510UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42CE0514UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42CE0518UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42CE051CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42CE0520UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42CE0524UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42CE0528UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42CE052CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42CE0530UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42CE0534UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42CE0538UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42CE053CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42CE0540UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42CE0544UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42CE0548UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42CE054CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42CE0550UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42CE0554UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42CE0558UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42CE055CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42CE0560UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42CE0564UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42CE0568UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42CE056CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42CE0570UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42CE0574UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42CE0578UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42CE057CUL)) -#define bFM3_ETHERNET_MAC1_PMTR_PD *((volatile unsigned int*)(0x42CE0580UL)) -#define bFM3_ETHERNET_MAC1_PMTR_MPE *((volatile unsigned int*)(0x42CE0584UL)) -#define bFM3_ETHERNET_MAC1_PMTR_WFE *((volatile unsigned int*)(0x42CE0588UL)) -#define bFM3_ETHERNET_MAC1_PMTR_MPR *((volatile unsigned int*)(0x42CE0594UL)) -#define bFM3_ETHERNET_MAC1_PMTR_WPR *((volatile unsigned int*)(0x42CE0598UL)) -#define bFM3_ETHERNET_MAC1_PMTR_GU *((volatile unsigned int*)(0x42CE05A4UL)) -#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR *((volatile unsigned int*)(0x42CE05FCUL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN *((volatile unsigned int*)(0x42CE0600UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX *((volatile unsigned int*)(0x42CE0604UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN *((volatile unsigned int*)(0x42CE0608UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX *((volatile unsigned int*)(0x42CE060CUL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST *((volatile unsigned int*)(0x42CE0620UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST *((volatile unsigned int*)(0x42CE0624UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN *((volatile unsigned int*)(0x42CE0640UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_PLS *((volatile unsigned int*)(0x42CE0644UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN *((volatile unsigned int*)(0x42CE0648UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA *((volatile unsigned int*)(0x42CE064CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT0 *((volatile unsigned int*)(0x42CE0680UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT1 *((volatile unsigned int*)(0x42CE0684UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT2 *((volatile unsigned int*)(0x42CE0688UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT3 *((volatile unsigned int*)(0x42CE068CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT4 *((volatile unsigned int*)(0x42CE0690UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT5 *((volatile unsigned int*)(0x42CE0694UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT6 *((volatile unsigned int*)(0x42CE0698UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT7 *((volatile unsigned int*)(0x42CE069CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT8 *((volatile unsigned int*)(0x42CE06A0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT9 *((volatile unsigned int*)(0x42CE06A4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT10 *((volatile unsigned int*)(0x42CE06A8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT11 *((volatile unsigned int*)(0x42CE06ACUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT12 *((volatile unsigned int*)(0x42CE06B0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT13 *((volatile unsigned int*)(0x42CE06B4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT14 *((volatile unsigned int*)(0x42CE06B8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT15 *((volatile unsigned int*)(0x42CE06BCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT0 *((volatile unsigned int*)(0x42CE06C0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT1 *((volatile unsigned int*)(0x42CE06C4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT2 *((volatile unsigned int*)(0x42CE06C8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT3 *((volatile unsigned int*)(0x42CE06CCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT4 *((volatile unsigned int*)(0x42CE06D0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT5 *((volatile unsigned int*)(0x42CE06D4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT6 *((volatile unsigned int*)(0x42CE06D8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT7 *((volatile unsigned int*)(0x42CE06DCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT8 *((volatile unsigned int*)(0x42CE06E0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT9 *((volatile unsigned int*)(0x42CE06E4UL)) -#define bFM3_ETHERNET_MAC1_ISR_RGIS *((volatile unsigned int*)(0x42CE0700UL)) -#define bFM3_ETHERNET_MAC1_ISR_PIS *((volatile unsigned int*)(0x42CE070CUL)) -#define bFM3_ETHERNET_MAC1_ISR_MIS *((volatile unsigned int*)(0x42CE0710UL)) -#define bFM3_ETHERNET_MAC1_ISR_RIS *((volatile unsigned int*)(0x42CE0714UL)) -#define bFM3_ETHERNET_MAC1_ISR_TIS *((volatile unsigned int*)(0x42CE0718UL)) -#define bFM3_ETHERNET_MAC1_ISR_COIS *((volatile unsigned int*)(0x42CE071CUL)) -#define bFM3_ETHERNET_MAC1_ISR_TSIS *((volatile unsigned int*)(0x42CE0724UL)) -#define bFM3_ETHERNET_MAC1_ISR_LPIIS *((volatile unsigned int*)(0x42CE0728UL)) -#define bFM3_ETHERNET_MAC1_IMR_RGIM *((volatile unsigned int*)(0x42CE0780UL)) -#define bFM3_ETHERNET_MAC1_IMR_PIM *((volatile unsigned int*)(0x42CE078CUL)) -#define bFM3_ETHERNET_MAC1_IMR_TSIM *((volatile unsigned int*)(0x42CE0794UL)) -#define bFM3_ETHERNET_MAC1_IMR_LPIIM *((volatile unsigned int*)(0x42CE0798UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A32 *((volatile unsigned int*)(0x42CE0800UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A33 *((volatile unsigned int*)(0x42CE0804UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A34 *((volatile unsigned int*)(0x42CE0808UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A35 *((volatile unsigned int*)(0x42CE080CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A36 *((volatile unsigned int*)(0x42CE0810UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A37 *((volatile unsigned int*)(0x42CE0814UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A38 *((volatile unsigned int*)(0x42CE0818UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A39 *((volatile unsigned int*)(0x42CE081CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A40 *((volatile unsigned int*)(0x42CE0820UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A41 *((volatile unsigned int*)(0x42CE0824UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A42 *((volatile unsigned int*)(0x42CE0828UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A43 *((volatile unsigned int*)(0x42CE082CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A44 *((volatile unsigned int*)(0x42CE0830UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A45 *((volatile unsigned int*)(0x42CE0834UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A46 *((volatile unsigned int*)(0x42CE0838UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A47 *((volatile unsigned int*)(0x42CE083CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_MO *((volatile unsigned int*)(0x42CE087CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A0 *((volatile unsigned int*)(0x42CE0880UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A1 *((volatile unsigned int*)(0x42CE0884UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A2 *((volatile unsigned int*)(0x42CE0888UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A3 *((volatile unsigned int*)(0x42CE088CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A4 *((volatile unsigned int*)(0x42CE0890UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A5 *((volatile unsigned int*)(0x42CE0894UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A6 *((volatile unsigned int*)(0x42CE0898UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A7 *((volatile unsigned int*)(0x42CE089CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A8 *((volatile unsigned int*)(0x42CE08A0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A9 *((volatile unsigned int*)(0x42CE08A4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A10 *((volatile unsigned int*)(0x42CE08A8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A11 *((volatile unsigned int*)(0x42CE08ACUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A12 *((volatile unsigned int*)(0x42CE08B0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A13 *((volatile unsigned int*)(0x42CE08B4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A14 *((volatile unsigned int*)(0x42CE08B8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A15 *((volatile unsigned int*)(0x42CE08BCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A16 *((volatile unsigned int*)(0x42CE08C0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A17 *((volatile unsigned int*)(0x42CE08C4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A18 *((volatile unsigned int*)(0x42CE08C8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A19 *((volatile unsigned int*)(0x42CE08CCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A20 *((volatile unsigned int*)(0x42CE08D0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A21 *((volatile unsigned int*)(0x42CE08D4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A22 *((volatile unsigned int*)(0x42CE08D8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A23 *((volatile unsigned int*)(0x42CE08DCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A24 *((volatile unsigned int*)(0x42CE08E0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A25 *((volatile unsigned int*)(0x42CE08E4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A26 *((volatile unsigned int*)(0x42CE08E8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A27 *((volatile unsigned int*)(0x42CE08ECUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A28 *((volatile unsigned int*)(0x42CE08F0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A29 *((volatile unsigned int*)(0x42CE08F4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A30 *((volatile unsigned int*)(0x42CE08F8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A31 *((volatile unsigned int*)(0x42CE08FCUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A32 *((volatile unsigned int*)(0x42CE0900UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A33 *((volatile unsigned int*)(0x42CE0904UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A34 *((volatile unsigned int*)(0x42CE0908UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A35 *((volatile unsigned int*)(0x42CE090CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A36 *((volatile unsigned int*)(0x42CE0910UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A37 *((volatile unsigned int*)(0x42CE0914UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A38 *((volatile unsigned int*)(0x42CE0918UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A39 *((volatile unsigned int*)(0x42CE091CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A40 *((volatile unsigned int*)(0x42CE0920UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A41 *((volatile unsigned int*)(0x42CE0924UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A42 *((volatile unsigned int*)(0x42CE0928UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A43 *((volatile unsigned int*)(0x42CE092CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A44 *((volatile unsigned int*)(0x42CE0930UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A45 *((volatile unsigned int*)(0x42CE0934UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A46 *((volatile unsigned int*)(0x42CE0938UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A47 *((volatile unsigned int*)(0x42CE093CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC0 *((volatile unsigned int*)(0x42CE0960UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC1 *((volatile unsigned int*)(0x42CE0964UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC2 *((volatile unsigned int*)(0x42CE0968UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC3 *((volatile unsigned int*)(0x42CE096CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC4 *((volatile unsigned int*)(0x42CE0970UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC5 *((volatile unsigned int*)(0x42CE0974UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_SA *((volatile unsigned int*)(0x42CE0978UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_AE *((volatile unsigned int*)(0x42CE097CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A0 *((volatile unsigned int*)(0x42CE0980UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A1 *((volatile unsigned int*)(0x42CE0984UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A2 *((volatile unsigned int*)(0x42CE0988UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A3 *((volatile unsigned int*)(0x42CE098CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A4 *((volatile unsigned int*)(0x42CE0990UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A5 *((volatile unsigned int*)(0x42CE0994UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A6 *((volatile unsigned int*)(0x42CE0998UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A7 *((volatile unsigned int*)(0x42CE099CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A8 *((volatile unsigned int*)(0x42CE09A0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A9 *((volatile unsigned int*)(0x42CE09A4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A10 *((volatile unsigned int*)(0x42CE09A8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A11 *((volatile unsigned int*)(0x42CE09ACUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A12 *((volatile unsigned int*)(0x42CE09B0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A13 *((volatile unsigned int*)(0x42CE09B4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A14 *((volatile unsigned int*)(0x42CE09B8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A15 *((volatile unsigned int*)(0x42CE09BCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A16 *((volatile unsigned int*)(0x42CE09C0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A17 *((volatile unsigned int*)(0x42CE09C4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A18 *((volatile unsigned int*)(0x42CE09C8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A19 *((volatile unsigned int*)(0x42CE09CCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A20 *((volatile unsigned int*)(0x42CE09D0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A21 *((volatile unsigned int*)(0x42CE09D4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A22 *((volatile unsigned int*)(0x42CE09D8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A23 *((volatile unsigned int*)(0x42CE09DCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A24 *((volatile unsigned int*)(0x42CE09E0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A25 *((volatile unsigned int*)(0x42CE09E4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A26 *((volatile unsigned int*)(0x42CE09E8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A27 *((volatile unsigned int*)(0x42CE09ECUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A28 *((volatile unsigned int*)(0x42CE09F0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A29 *((volatile unsigned int*)(0x42CE09F4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A30 *((volatile unsigned int*)(0x42CE09F8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A31 *((volatile unsigned int*)(0x42CE09FCUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A32 *((volatile unsigned int*)(0x42CE0A00UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A33 *((volatile unsigned int*)(0x42CE0A04UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A34 *((volatile unsigned int*)(0x42CE0A08UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A35 *((volatile unsigned int*)(0x42CE0A0CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A36 *((volatile unsigned int*)(0x42CE0A10UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A37 *((volatile unsigned int*)(0x42CE0A14UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A38 *((volatile unsigned int*)(0x42CE0A18UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A39 *((volatile unsigned int*)(0x42CE0A1CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A40 *((volatile unsigned int*)(0x42CE0A20UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A41 *((volatile unsigned int*)(0x42CE0A24UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A42 *((volatile unsigned int*)(0x42CE0A28UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A43 *((volatile unsigned int*)(0x42CE0A2CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A44 *((volatile unsigned int*)(0x42CE0A30UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A45 *((volatile unsigned int*)(0x42CE0A34UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A46 *((volatile unsigned int*)(0x42CE0A38UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A47 *((volatile unsigned int*)(0x42CE0A3CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC0 *((volatile unsigned int*)(0x42CE0A60UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC1 *((volatile unsigned int*)(0x42CE0A64UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC2 *((volatile unsigned int*)(0x42CE0A68UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC3 *((volatile unsigned int*)(0x42CE0A6CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC4 *((volatile unsigned int*)(0x42CE0A70UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC5 *((volatile unsigned int*)(0x42CE0A74UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_SA *((volatile unsigned int*)(0x42CE0A78UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_AE *((volatile unsigned int*)(0x42CE0A7CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A0 *((volatile unsigned int*)(0x42CE0A80UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A1 *((volatile unsigned int*)(0x42CE0A84UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A2 *((volatile unsigned int*)(0x42CE0A88UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A3 *((volatile unsigned int*)(0x42CE0A8CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A4 *((volatile unsigned int*)(0x42CE0A90UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A5 *((volatile unsigned int*)(0x42CE0A94UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A6 *((volatile unsigned int*)(0x42CE0A98UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A7 *((volatile unsigned int*)(0x42CE0A9CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A8 *((volatile unsigned int*)(0x42CE0AA0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A9 *((volatile unsigned int*)(0x42CE0AA4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A10 *((volatile unsigned int*)(0x42CE0AA8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A11 *((volatile unsigned int*)(0x42CE0AACUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A12 *((volatile unsigned int*)(0x42CE0AB0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A13 *((volatile unsigned int*)(0x42CE0AB4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A14 *((volatile unsigned int*)(0x42CE0AB8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A15 *((volatile unsigned int*)(0x42CE0ABCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A16 *((volatile unsigned int*)(0x42CE0AC0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A17 *((volatile unsigned int*)(0x42CE0AC4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A18 *((volatile unsigned int*)(0x42CE0AC8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A19 *((volatile unsigned int*)(0x42CE0ACCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A20 *((volatile unsigned int*)(0x42CE0AD0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A21 *((volatile unsigned int*)(0x42CE0AD4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A22 *((volatile unsigned int*)(0x42CE0AD8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A23 *((volatile unsigned int*)(0x42CE0ADCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A24 *((volatile unsigned int*)(0x42CE0AE0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A25 *((volatile unsigned int*)(0x42CE0AE4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A26 *((volatile unsigned int*)(0x42CE0AE8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A27 *((volatile unsigned int*)(0x42CE0AECUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A28 *((volatile unsigned int*)(0x42CE0AF0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A29 *((volatile unsigned int*)(0x42CE0AF4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A30 *((volatile unsigned int*)(0x42CE0AF8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A31 *((volatile unsigned int*)(0x42CE0AFCUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A32 *((volatile unsigned int*)(0x42CE0B00UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A33 *((volatile unsigned int*)(0x42CE0B04UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A34 *((volatile unsigned int*)(0x42CE0B08UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A35 *((volatile unsigned int*)(0x42CE0B0CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A36 *((volatile unsigned int*)(0x42CE0B10UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A37 *((volatile unsigned int*)(0x42CE0B14UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A38 *((volatile unsigned int*)(0x42CE0B18UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A39 *((volatile unsigned int*)(0x42CE0B1CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A40 *((volatile unsigned int*)(0x42CE0B20UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A41 *((volatile unsigned int*)(0x42CE0B24UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A42 *((volatile unsigned int*)(0x42CE0B28UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A43 *((volatile unsigned int*)(0x42CE0B2CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A44 *((volatile unsigned int*)(0x42CE0B30UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A45 *((volatile unsigned int*)(0x42CE0B34UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A46 *((volatile unsigned int*)(0x42CE0B38UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A47 *((volatile unsigned int*)(0x42CE0B3CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC0 *((volatile unsigned int*)(0x42CE0B60UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC1 *((volatile unsigned int*)(0x42CE0B64UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC2 *((volatile unsigned int*)(0x42CE0B68UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC3 *((volatile unsigned int*)(0x42CE0B6CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC4 *((volatile unsigned int*)(0x42CE0B70UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC5 *((volatile unsigned int*)(0x42CE0B74UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_SA *((volatile unsigned int*)(0x42CE0B78UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_AE *((volatile unsigned int*)(0x42CE0B7CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A0 *((volatile unsigned int*)(0x42CE0B80UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A1 *((volatile unsigned int*)(0x42CE0B84UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A2 *((volatile unsigned int*)(0x42CE0B88UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A3 *((volatile unsigned int*)(0x42CE0B8CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A4 *((volatile unsigned int*)(0x42CE0B90UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A5 *((volatile unsigned int*)(0x42CE0B94UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A6 *((volatile unsigned int*)(0x42CE0B98UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A7 *((volatile unsigned int*)(0x42CE0B9CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A8 *((volatile unsigned int*)(0x42CE0BA0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A9 *((volatile unsigned int*)(0x42CE0BA4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A10 *((volatile unsigned int*)(0x42CE0BA8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A11 *((volatile unsigned int*)(0x42CE0BACUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A12 *((volatile unsigned int*)(0x42CE0BB0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A13 *((volatile unsigned int*)(0x42CE0BB4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A14 *((volatile unsigned int*)(0x42CE0BB8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A15 *((volatile unsigned int*)(0x42CE0BBCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A16 *((volatile unsigned int*)(0x42CE0BC0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A17 *((volatile unsigned int*)(0x42CE0BC4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A18 *((volatile unsigned int*)(0x42CE0BC8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A19 *((volatile unsigned int*)(0x42CE0BCCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A20 *((volatile unsigned int*)(0x42CE0BD0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A21 *((volatile unsigned int*)(0x42CE0BD4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A22 *((volatile unsigned int*)(0x42CE0BD8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A23 *((volatile unsigned int*)(0x42CE0BDCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A24 *((volatile unsigned int*)(0x42CE0BE0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A25 *((volatile unsigned int*)(0x42CE0BE4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A26 *((volatile unsigned int*)(0x42CE0BE8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A27 *((volatile unsigned int*)(0x42CE0BECUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A28 *((volatile unsigned int*)(0x42CE0BF0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A29 *((volatile unsigned int*)(0x42CE0BF4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A30 *((volatile unsigned int*)(0x42CE0BF8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A31 *((volatile unsigned int*)(0x42CE0BFCUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A32 *((volatile unsigned int*)(0x42CE0C00UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A33 *((volatile unsigned int*)(0x42CE0C04UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A34 *((volatile unsigned int*)(0x42CE0C08UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A35 *((volatile unsigned int*)(0x42CE0C0CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A36 *((volatile unsigned int*)(0x42CE0C10UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A37 *((volatile unsigned int*)(0x42CE0C14UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A38 *((volatile unsigned int*)(0x42CE0C18UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A39 *((volatile unsigned int*)(0x42CE0C1CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A40 *((volatile unsigned int*)(0x42CE0C20UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A41 *((volatile unsigned int*)(0x42CE0C24UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A42 *((volatile unsigned int*)(0x42CE0C28UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A43 *((volatile unsigned int*)(0x42CE0C2CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A44 *((volatile unsigned int*)(0x42CE0C30UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A45 *((volatile unsigned int*)(0x42CE0C34UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A46 *((volatile unsigned int*)(0x42CE0C38UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A47 *((volatile unsigned int*)(0x42CE0C3CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC0 *((volatile unsigned int*)(0x42CE0C60UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC1 *((volatile unsigned int*)(0x42CE0C64UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC2 *((volatile unsigned int*)(0x42CE0C68UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC3 *((volatile unsigned int*)(0x42CE0C6CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC4 *((volatile unsigned int*)(0x42CE0C70UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC5 *((volatile unsigned int*)(0x42CE0C74UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_SA *((volatile unsigned int*)(0x42CE0C78UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_AE *((volatile unsigned int*)(0x42CE0C7CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A0 *((volatile unsigned int*)(0x42CE0C80UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A1 *((volatile unsigned int*)(0x42CE0C84UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A2 *((volatile unsigned int*)(0x42CE0C88UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A3 *((volatile unsigned int*)(0x42CE0C8CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A4 *((volatile unsigned int*)(0x42CE0C90UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A5 *((volatile unsigned int*)(0x42CE0C94UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A6 *((volatile unsigned int*)(0x42CE0C98UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A7 *((volatile unsigned int*)(0x42CE0C9CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A8 *((volatile unsigned int*)(0x42CE0CA0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A9 *((volatile unsigned int*)(0x42CE0CA4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A10 *((volatile unsigned int*)(0x42CE0CA8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A11 *((volatile unsigned int*)(0x42CE0CACUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A12 *((volatile unsigned int*)(0x42CE0CB0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A13 *((volatile unsigned int*)(0x42CE0CB4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A14 *((volatile unsigned int*)(0x42CE0CB8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A15 *((volatile unsigned int*)(0x42CE0CBCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A16 *((volatile unsigned int*)(0x42CE0CC0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A17 *((volatile unsigned int*)(0x42CE0CC4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A18 *((volatile unsigned int*)(0x42CE0CC8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A19 *((volatile unsigned int*)(0x42CE0CCCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A20 *((volatile unsigned int*)(0x42CE0CD0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A21 *((volatile unsigned int*)(0x42CE0CD4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A22 *((volatile unsigned int*)(0x42CE0CD8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A23 *((volatile unsigned int*)(0x42CE0CDCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A24 *((volatile unsigned int*)(0x42CE0CE0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A25 *((volatile unsigned int*)(0x42CE0CE4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A26 *((volatile unsigned int*)(0x42CE0CE8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A27 *((volatile unsigned int*)(0x42CE0CECUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A28 *((volatile unsigned int*)(0x42CE0CF0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A29 *((volatile unsigned int*)(0x42CE0CF4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A30 *((volatile unsigned int*)(0x42CE0CF8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A31 *((volatile unsigned int*)(0x42CE0CFCUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A32 *((volatile unsigned int*)(0x42CE0D00UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A33 *((volatile unsigned int*)(0x42CE0D04UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A34 *((volatile unsigned int*)(0x42CE0D08UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A35 *((volatile unsigned int*)(0x42CE0D0CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A36 *((volatile unsigned int*)(0x42CE0D10UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A37 *((volatile unsigned int*)(0x42CE0D14UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A38 *((volatile unsigned int*)(0x42CE0D18UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A39 *((volatile unsigned int*)(0x42CE0D1CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A40 *((volatile unsigned int*)(0x42CE0D20UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A41 *((volatile unsigned int*)(0x42CE0D24UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A42 *((volatile unsigned int*)(0x42CE0D28UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A43 *((volatile unsigned int*)(0x42CE0D2CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A44 *((volatile unsigned int*)(0x42CE0D30UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A45 *((volatile unsigned int*)(0x42CE0D34UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A46 *((volatile unsigned int*)(0x42CE0D38UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A47 *((volatile unsigned int*)(0x42CE0D3CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC0 *((volatile unsigned int*)(0x42CE0D60UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC1 *((volatile unsigned int*)(0x42CE0D64UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC2 *((volatile unsigned int*)(0x42CE0D68UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC3 *((volatile unsigned int*)(0x42CE0D6CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC4 *((volatile unsigned int*)(0x42CE0D70UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC5 *((volatile unsigned int*)(0x42CE0D74UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_SA *((volatile unsigned int*)(0x42CE0D78UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_AE *((volatile unsigned int*)(0x42CE0D7CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A0 *((volatile unsigned int*)(0x42CE0D80UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A1 *((volatile unsigned int*)(0x42CE0D84UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A2 *((volatile unsigned int*)(0x42CE0D88UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A3 *((volatile unsigned int*)(0x42CE0D8CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A4 *((volatile unsigned int*)(0x42CE0D90UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A5 *((volatile unsigned int*)(0x42CE0D94UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A6 *((volatile unsigned int*)(0x42CE0D98UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A7 *((volatile unsigned int*)(0x42CE0D9CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A8 *((volatile unsigned int*)(0x42CE0DA0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A9 *((volatile unsigned int*)(0x42CE0DA4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A10 *((volatile unsigned int*)(0x42CE0DA8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A11 *((volatile unsigned int*)(0x42CE0DACUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A12 *((volatile unsigned int*)(0x42CE0DB0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A13 *((volatile unsigned int*)(0x42CE0DB4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A14 *((volatile unsigned int*)(0x42CE0DB8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A15 *((volatile unsigned int*)(0x42CE0DBCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A16 *((volatile unsigned int*)(0x42CE0DC0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A17 *((volatile unsigned int*)(0x42CE0DC4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A18 *((volatile unsigned int*)(0x42CE0DC8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A19 *((volatile unsigned int*)(0x42CE0DCCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A20 *((volatile unsigned int*)(0x42CE0DD0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A21 *((volatile unsigned int*)(0x42CE0DD4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A22 *((volatile unsigned int*)(0x42CE0DD8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A23 *((volatile unsigned int*)(0x42CE0DDCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A24 *((volatile unsigned int*)(0x42CE0DE0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A25 *((volatile unsigned int*)(0x42CE0DE4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A26 *((volatile unsigned int*)(0x42CE0DE8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A27 *((volatile unsigned int*)(0x42CE0DECUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A28 *((volatile unsigned int*)(0x42CE0DF0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A29 *((volatile unsigned int*)(0x42CE0DF4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A30 *((volatile unsigned int*)(0x42CE0DF8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A31 *((volatile unsigned int*)(0x42CE0DFCUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A32 *((volatile unsigned int*)(0x42CE0E00UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A33 *((volatile unsigned int*)(0x42CE0E04UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A34 *((volatile unsigned int*)(0x42CE0E08UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A35 *((volatile unsigned int*)(0x42CE0E0CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A36 *((volatile unsigned int*)(0x42CE0E10UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A37 *((volatile unsigned int*)(0x42CE0E14UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A38 *((volatile unsigned int*)(0x42CE0E18UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A39 *((volatile unsigned int*)(0x42CE0E1CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A40 *((volatile unsigned int*)(0x42CE0E20UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A41 *((volatile unsigned int*)(0x42CE0E24UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A42 *((volatile unsigned int*)(0x42CE0E28UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A43 *((volatile unsigned int*)(0x42CE0E2CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A44 *((volatile unsigned int*)(0x42CE0E30UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A45 *((volatile unsigned int*)(0x42CE0E34UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A46 *((volatile unsigned int*)(0x42CE0E38UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A47 *((volatile unsigned int*)(0x42CE0E3CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC0 *((volatile unsigned int*)(0x42CE0E60UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC1 *((volatile unsigned int*)(0x42CE0E64UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC2 *((volatile unsigned int*)(0x42CE0E68UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC3 *((volatile unsigned int*)(0x42CE0E6CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC4 *((volatile unsigned int*)(0x42CE0E70UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC5 *((volatile unsigned int*)(0x42CE0E74UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_SA *((volatile unsigned int*)(0x42CE0E78UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_AE *((volatile unsigned int*)(0x42CE0E7CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A0 *((volatile unsigned int*)(0x42CE0E80UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A1 *((volatile unsigned int*)(0x42CE0E84UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A2 *((volatile unsigned int*)(0x42CE0E88UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A3 *((volatile unsigned int*)(0x42CE0E8CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A4 *((volatile unsigned int*)(0x42CE0E90UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A5 *((volatile unsigned int*)(0x42CE0E94UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A6 *((volatile unsigned int*)(0x42CE0E98UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A7 *((volatile unsigned int*)(0x42CE0E9CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A8 *((volatile unsigned int*)(0x42CE0EA0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A9 *((volatile unsigned int*)(0x42CE0EA4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A10 *((volatile unsigned int*)(0x42CE0EA8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A11 *((volatile unsigned int*)(0x42CE0EACUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A12 *((volatile unsigned int*)(0x42CE0EB0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A13 *((volatile unsigned int*)(0x42CE0EB4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A14 *((volatile unsigned int*)(0x42CE0EB8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A15 *((volatile unsigned int*)(0x42CE0EBCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A16 *((volatile unsigned int*)(0x42CE0EC0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A17 *((volatile unsigned int*)(0x42CE0EC4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A18 *((volatile unsigned int*)(0x42CE0EC8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A19 *((volatile unsigned int*)(0x42CE0ECCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A20 *((volatile unsigned int*)(0x42CE0ED0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A21 *((volatile unsigned int*)(0x42CE0ED4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A22 *((volatile unsigned int*)(0x42CE0ED8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A23 *((volatile unsigned int*)(0x42CE0EDCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A24 *((volatile unsigned int*)(0x42CE0EE0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A25 *((volatile unsigned int*)(0x42CE0EE4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A26 *((volatile unsigned int*)(0x42CE0EE8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A27 *((volatile unsigned int*)(0x42CE0EECUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A28 *((volatile unsigned int*)(0x42CE0EF0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A29 *((volatile unsigned int*)(0x42CE0EF4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A30 *((volatile unsigned int*)(0x42CE0EF8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A31 *((volatile unsigned int*)(0x42CE0EFCUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A32 *((volatile unsigned int*)(0x42CE0F00UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A33 *((volatile unsigned int*)(0x42CE0F04UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A34 *((volatile unsigned int*)(0x42CE0F08UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A35 *((volatile unsigned int*)(0x42CE0F0CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A36 *((volatile unsigned int*)(0x42CE0F10UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A37 *((volatile unsigned int*)(0x42CE0F14UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A38 *((volatile unsigned int*)(0x42CE0F18UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A39 *((volatile unsigned int*)(0x42CE0F1CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A40 *((volatile unsigned int*)(0x42CE0F20UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A41 *((volatile unsigned int*)(0x42CE0F24UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A42 *((volatile unsigned int*)(0x42CE0F28UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A43 *((volatile unsigned int*)(0x42CE0F2CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A44 *((volatile unsigned int*)(0x42CE0F30UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A45 *((volatile unsigned int*)(0x42CE0F34UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A46 *((volatile unsigned int*)(0x42CE0F38UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A47 *((volatile unsigned int*)(0x42CE0F3CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC0 *((volatile unsigned int*)(0x42CE0F60UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC1 *((volatile unsigned int*)(0x42CE0F64UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC2 *((volatile unsigned int*)(0x42CE0F68UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC3 *((volatile unsigned int*)(0x42CE0F6CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC4 *((volatile unsigned int*)(0x42CE0F70UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC5 *((volatile unsigned int*)(0x42CE0F74UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_SA *((volatile unsigned int*)(0x42CE0F78UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_AE *((volatile unsigned int*)(0x42CE0F7CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A0 *((volatile unsigned int*)(0x42CE0F80UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A1 *((volatile unsigned int*)(0x42CE0F84UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A2 *((volatile unsigned int*)(0x42CE0F88UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A3 *((volatile unsigned int*)(0x42CE0F8CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A4 *((volatile unsigned int*)(0x42CE0F90UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A5 *((volatile unsigned int*)(0x42CE0F94UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A6 *((volatile unsigned int*)(0x42CE0F98UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A7 *((volatile unsigned int*)(0x42CE0F9CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A8 *((volatile unsigned int*)(0x42CE0FA0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A9 *((volatile unsigned int*)(0x42CE0FA4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A10 *((volatile unsigned int*)(0x42CE0FA8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A11 *((volatile unsigned int*)(0x42CE0FACUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A12 *((volatile unsigned int*)(0x42CE0FB0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A13 *((volatile unsigned int*)(0x42CE0FB4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A14 *((volatile unsigned int*)(0x42CE0FB8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A15 *((volatile unsigned int*)(0x42CE0FBCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A16 *((volatile unsigned int*)(0x42CE0FC0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A17 *((volatile unsigned int*)(0x42CE0FC4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A18 *((volatile unsigned int*)(0x42CE0FC8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A19 *((volatile unsigned int*)(0x42CE0FCCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A20 *((volatile unsigned int*)(0x42CE0FD0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A21 *((volatile unsigned int*)(0x42CE0FD4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A22 *((volatile unsigned int*)(0x42CE0FD8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A23 *((volatile unsigned int*)(0x42CE0FDCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A24 *((volatile unsigned int*)(0x42CE0FE0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A25 *((volatile unsigned int*)(0x42CE0FE4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A26 *((volatile unsigned int*)(0x42CE0FE8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A27 *((volatile unsigned int*)(0x42CE0FECUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A28 *((volatile unsigned int*)(0x42CE0FF0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A29 *((volatile unsigned int*)(0x42CE0FF4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A30 *((volatile unsigned int*)(0x42CE0FF8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A31 *((volatile unsigned int*)(0x42CE0FFCUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A32 *((volatile unsigned int*)(0x42CE1000UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A33 *((volatile unsigned int*)(0x42CE1004UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A34 *((volatile unsigned int*)(0x42CE1008UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A35 *((volatile unsigned int*)(0x42CE100CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A36 *((volatile unsigned int*)(0x42CE1010UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A37 *((volatile unsigned int*)(0x42CE1014UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A38 *((volatile unsigned int*)(0x42CE1018UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A39 *((volatile unsigned int*)(0x42CE101CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A40 *((volatile unsigned int*)(0x42CE1020UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A41 *((volatile unsigned int*)(0x42CE1024UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A42 *((volatile unsigned int*)(0x42CE1028UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A43 *((volatile unsigned int*)(0x42CE102CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A44 *((volatile unsigned int*)(0x42CE1030UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A45 *((volatile unsigned int*)(0x42CE1034UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A46 *((volatile unsigned int*)(0x42CE1038UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A47 *((volatile unsigned int*)(0x42CE103CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC0 *((volatile unsigned int*)(0x42CE1060UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC1 *((volatile unsigned int*)(0x42CE1064UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC2 *((volatile unsigned int*)(0x42CE1068UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC3 *((volatile unsigned int*)(0x42CE106CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC4 *((volatile unsigned int*)(0x42CE1070UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC5 *((volatile unsigned int*)(0x42CE1074UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_SA *((volatile unsigned int*)(0x42CE1078UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_AE *((volatile unsigned int*)(0x42CE107CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A0 *((volatile unsigned int*)(0x42CE1080UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A1 *((volatile unsigned int*)(0x42CE1084UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A2 *((volatile unsigned int*)(0x42CE1088UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A3 *((volatile unsigned int*)(0x42CE108CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A4 *((volatile unsigned int*)(0x42CE1090UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A5 *((volatile unsigned int*)(0x42CE1094UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A6 *((volatile unsigned int*)(0x42CE1098UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A7 *((volatile unsigned int*)(0x42CE109CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A8 *((volatile unsigned int*)(0x42CE10A0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A9 *((volatile unsigned int*)(0x42CE10A4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A10 *((volatile unsigned int*)(0x42CE10A8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A11 *((volatile unsigned int*)(0x42CE10ACUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A12 *((volatile unsigned int*)(0x42CE10B0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A13 *((volatile unsigned int*)(0x42CE10B4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A14 *((volatile unsigned int*)(0x42CE10B8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A15 *((volatile unsigned int*)(0x42CE10BCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A16 *((volatile unsigned int*)(0x42CE10C0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A17 *((volatile unsigned int*)(0x42CE10C4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A18 *((volatile unsigned int*)(0x42CE10C8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A19 *((volatile unsigned int*)(0x42CE10CCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A20 *((volatile unsigned int*)(0x42CE10D0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A21 *((volatile unsigned int*)(0x42CE10D4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A22 *((volatile unsigned int*)(0x42CE10D8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A23 *((volatile unsigned int*)(0x42CE10DCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A24 *((volatile unsigned int*)(0x42CE10E0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A25 *((volatile unsigned int*)(0x42CE10E4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A26 *((volatile unsigned int*)(0x42CE10E8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A27 *((volatile unsigned int*)(0x42CE10ECUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A28 *((volatile unsigned int*)(0x42CE10F0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A29 *((volatile unsigned int*)(0x42CE10F4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A30 *((volatile unsigned int*)(0x42CE10F8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A31 *((volatile unsigned int*)(0x42CE10FCUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A32 *((volatile unsigned int*)(0x42CE1100UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A33 *((volatile unsigned int*)(0x42CE1104UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A34 *((volatile unsigned int*)(0x42CE1108UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A35 *((volatile unsigned int*)(0x42CE110CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A36 *((volatile unsigned int*)(0x42CE1110UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A37 *((volatile unsigned int*)(0x42CE1114UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A38 *((volatile unsigned int*)(0x42CE1118UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A39 *((volatile unsigned int*)(0x42CE111CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A40 *((volatile unsigned int*)(0x42CE1120UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A41 *((volatile unsigned int*)(0x42CE1124UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A42 *((volatile unsigned int*)(0x42CE1128UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A43 *((volatile unsigned int*)(0x42CE112CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A44 *((volatile unsigned int*)(0x42CE1130UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A45 *((volatile unsigned int*)(0x42CE1134UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A46 *((volatile unsigned int*)(0x42CE1138UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A47 *((volatile unsigned int*)(0x42CE113CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC0 *((volatile unsigned int*)(0x42CE1160UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC1 *((volatile unsigned int*)(0x42CE1164UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC2 *((volatile unsigned int*)(0x42CE1168UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC3 *((volatile unsigned int*)(0x42CE116CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC4 *((volatile unsigned int*)(0x42CE1170UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC5 *((volatile unsigned int*)(0x42CE1174UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_SA *((volatile unsigned int*)(0x42CE1178UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_AE *((volatile unsigned int*)(0x42CE117CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A0 *((volatile unsigned int*)(0x42CE1180UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A1 *((volatile unsigned int*)(0x42CE1184UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A2 *((volatile unsigned int*)(0x42CE1188UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A3 *((volatile unsigned int*)(0x42CE118CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A4 *((volatile unsigned int*)(0x42CE1190UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A5 *((volatile unsigned int*)(0x42CE1194UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A6 *((volatile unsigned int*)(0x42CE1198UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A7 *((volatile unsigned int*)(0x42CE119CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A8 *((volatile unsigned int*)(0x42CE11A0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A9 *((volatile unsigned int*)(0x42CE11A4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A10 *((volatile unsigned int*)(0x42CE11A8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A11 *((volatile unsigned int*)(0x42CE11ACUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A12 *((volatile unsigned int*)(0x42CE11B0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A13 *((volatile unsigned int*)(0x42CE11B4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A14 *((volatile unsigned int*)(0x42CE11B8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A15 *((volatile unsigned int*)(0x42CE11BCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A16 *((volatile unsigned int*)(0x42CE11C0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A17 *((volatile unsigned int*)(0x42CE11C4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A18 *((volatile unsigned int*)(0x42CE11C8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A19 *((volatile unsigned int*)(0x42CE11CCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A20 *((volatile unsigned int*)(0x42CE11D0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A21 *((volatile unsigned int*)(0x42CE11D4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A22 *((volatile unsigned int*)(0x42CE11D8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A23 *((volatile unsigned int*)(0x42CE11DCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A24 *((volatile unsigned int*)(0x42CE11E0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A25 *((volatile unsigned int*)(0x42CE11E4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A26 *((volatile unsigned int*)(0x42CE11E8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A27 *((volatile unsigned int*)(0x42CE11ECUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A28 *((volatile unsigned int*)(0x42CE11F0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A29 *((volatile unsigned int*)(0x42CE11F4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A30 *((volatile unsigned int*)(0x42CE11F8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A31 *((volatile unsigned int*)(0x42CE11FCUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A32 *((volatile unsigned int*)(0x42CE1200UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A33 *((volatile unsigned int*)(0x42CE1204UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A34 *((volatile unsigned int*)(0x42CE1208UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A35 *((volatile unsigned int*)(0x42CE120CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A36 *((volatile unsigned int*)(0x42CE1210UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A37 *((volatile unsigned int*)(0x42CE1214UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A38 *((volatile unsigned int*)(0x42CE1218UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A39 *((volatile unsigned int*)(0x42CE121CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A40 *((volatile unsigned int*)(0x42CE1220UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A41 *((volatile unsigned int*)(0x42CE1224UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A42 *((volatile unsigned int*)(0x42CE1228UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A43 *((volatile unsigned int*)(0x42CE122CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A44 *((volatile unsigned int*)(0x42CE1230UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A45 *((volatile unsigned int*)(0x42CE1234UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A46 *((volatile unsigned int*)(0x42CE1238UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A47 *((volatile unsigned int*)(0x42CE123CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC0 *((volatile unsigned int*)(0x42CE1260UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC1 *((volatile unsigned int*)(0x42CE1264UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC2 *((volatile unsigned int*)(0x42CE1268UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC3 *((volatile unsigned int*)(0x42CE126CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC4 *((volatile unsigned int*)(0x42CE1270UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC5 *((volatile unsigned int*)(0x42CE1274UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_SA *((volatile unsigned int*)(0x42CE1278UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_AE *((volatile unsigned int*)(0x42CE127CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A0 *((volatile unsigned int*)(0x42CE1280UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A1 *((volatile unsigned int*)(0x42CE1284UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A2 *((volatile unsigned int*)(0x42CE1288UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A3 *((volatile unsigned int*)(0x42CE128CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A4 *((volatile unsigned int*)(0x42CE1290UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A5 *((volatile unsigned int*)(0x42CE1294UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A6 *((volatile unsigned int*)(0x42CE1298UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A7 *((volatile unsigned int*)(0x42CE129CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A8 *((volatile unsigned int*)(0x42CE12A0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A9 *((volatile unsigned int*)(0x42CE12A4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A10 *((volatile unsigned int*)(0x42CE12A8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A11 *((volatile unsigned int*)(0x42CE12ACUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A12 *((volatile unsigned int*)(0x42CE12B0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A13 *((volatile unsigned int*)(0x42CE12B4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A14 *((volatile unsigned int*)(0x42CE12B8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A15 *((volatile unsigned int*)(0x42CE12BCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A16 *((volatile unsigned int*)(0x42CE12C0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A17 *((volatile unsigned int*)(0x42CE12C4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A18 *((volatile unsigned int*)(0x42CE12C8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A19 *((volatile unsigned int*)(0x42CE12CCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A20 *((volatile unsigned int*)(0x42CE12D0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A21 *((volatile unsigned int*)(0x42CE12D4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A22 *((volatile unsigned int*)(0x42CE12D8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A23 *((volatile unsigned int*)(0x42CE12DCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A24 *((volatile unsigned int*)(0x42CE12E0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A25 *((volatile unsigned int*)(0x42CE12E4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A26 *((volatile unsigned int*)(0x42CE12E8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A27 *((volatile unsigned int*)(0x42CE12ECUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A28 *((volatile unsigned int*)(0x42CE12F0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A29 *((volatile unsigned int*)(0x42CE12F4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A30 *((volatile unsigned int*)(0x42CE12F8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A31 *((volatile unsigned int*)(0x42CE12FCUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A32 *((volatile unsigned int*)(0x42CE1300UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A33 *((volatile unsigned int*)(0x42CE1304UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A34 *((volatile unsigned int*)(0x42CE1308UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A35 *((volatile unsigned int*)(0x42CE130CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A36 *((volatile unsigned int*)(0x42CE1310UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A37 *((volatile unsigned int*)(0x42CE1314UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A38 *((volatile unsigned int*)(0x42CE1318UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A39 *((volatile unsigned int*)(0x42CE131CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A40 *((volatile unsigned int*)(0x42CE1320UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A41 *((volatile unsigned int*)(0x42CE1324UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A42 *((volatile unsigned int*)(0x42CE1328UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A43 *((volatile unsigned int*)(0x42CE132CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A44 *((volatile unsigned int*)(0x42CE1330UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A45 *((volatile unsigned int*)(0x42CE1334UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A46 *((volatile unsigned int*)(0x42CE1338UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A47 *((volatile unsigned int*)(0x42CE133CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC0 *((volatile unsigned int*)(0x42CE1360UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC1 *((volatile unsigned int*)(0x42CE1364UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC2 *((volatile unsigned int*)(0x42CE1368UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC3 *((volatile unsigned int*)(0x42CE136CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC4 *((volatile unsigned int*)(0x42CE1370UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC5 *((volatile unsigned int*)(0x42CE1374UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_SA *((volatile unsigned int*)(0x42CE1378UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_AE *((volatile unsigned int*)(0x42CE137CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A0 *((volatile unsigned int*)(0x42CE1380UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A1 *((volatile unsigned int*)(0x42CE1384UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A2 *((volatile unsigned int*)(0x42CE1388UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A3 *((volatile unsigned int*)(0x42CE138CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A4 *((volatile unsigned int*)(0x42CE1390UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A5 *((volatile unsigned int*)(0x42CE1394UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A6 *((volatile unsigned int*)(0x42CE1398UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A7 *((volatile unsigned int*)(0x42CE139CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A8 *((volatile unsigned int*)(0x42CE13A0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A9 *((volatile unsigned int*)(0x42CE13A4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A10 *((volatile unsigned int*)(0x42CE13A8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A11 *((volatile unsigned int*)(0x42CE13ACUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A12 *((volatile unsigned int*)(0x42CE13B0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A13 *((volatile unsigned int*)(0x42CE13B4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A14 *((volatile unsigned int*)(0x42CE13B8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A15 *((volatile unsigned int*)(0x42CE13BCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A16 *((volatile unsigned int*)(0x42CE13C0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A17 *((volatile unsigned int*)(0x42CE13C4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A18 *((volatile unsigned int*)(0x42CE13C8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A19 *((volatile unsigned int*)(0x42CE13CCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A20 *((volatile unsigned int*)(0x42CE13D0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A21 *((volatile unsigned int*)(0x42CE13D4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A22 *((volatile unsigned int*)(0x42CE13D8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A23 *((volatile unsigned int*)(0x42CE13DCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A24 *((volatile unsigned int*)(0x42CE13E0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A25 *((volatile unsigned int*)(0x42CE13E4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A26 *((volatile unsigned int*)(0x42CE13E8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A27 *((volatile unsigned int*)(0x42CE13ECUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A28 *((volatile unsigned int*)(0x42CE13F0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A29 *((volatile unsigned int*)(0x42CE13F4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A30 *((volatile unsigned int*)(0x42CE13F8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A31 *((volatile unsigned int*)(0x42CE13FCUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A32 *((volatile unsigned int*)(0x42CE1400UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A33 *((volatile unsigned int*)(0x42CE1404UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A34 *((volatile unsigned int*)(0x42CE1408UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A35 *((volatile unsigned int*)(0x42CE140CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A36 *((volatile unsigned int*)(0x42CE1410UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A37 *((volatile unsigned int*)(0x42CE1414UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A38 *((volatile unsigned int*)(0x42CE1418UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A39 *((volatile unsigned int*)(0x42CE141CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A40 *((volatile unsigned int*)(0x42CE1420UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A41 *((volatile unsigned int*)(0x42CE1424UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A42 *((volatile unsigned int*)(0x42CE1428UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A43 *((volatile unsigned int*)(0x42CE142CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A44 *((volatile unsigned int*)(0x42CE1430UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A45 *((volatile unsigned int*)(0x42CE1434UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A46 *((volatile unsigned int*)(0x42CE1438UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A47 *((volatile unsigned int*)(0x42CE143CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC0 *((volatile unsigned int*)(0x42CE1460UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC1 *((volatile unsigned int*)(0x42CE1464UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC2 *((volatile unsigned int*)(0x42CE1468UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC3 *((volatile unsigned int*)(0x42CE146CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC4 *((volatile unsigned int*)(0x42CE1470UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC5 *((volatile unsigned int*)(0x42CE1474UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_SA *((volatile unsigned int*)(0x42CE1478UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_AE *((volatile unsigned int*)(0x42CE147CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A0 *((volatile unsigned int*)(0x42CE1480UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A1 *((volatile unsigned int*)(0x42CE1484UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A2 *((volatile unsigned int*)(0x42CE1488UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A3 *((volatile unsigned int*)(0x42CE148CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A4 *((volatile unsigned int*)(0x42CE1490UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A5 *((volatile unsigned int*)(0x42CE1494UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A6 *((volatile unsigned int*)(0x42CE1498UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A7 *((volatile unsigned int*)(0x42CE149CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A8 *((volatile unsigned int*)(0x42CE14A0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A9 *((volatile unsigned int*)(0x42CE14A4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A10 *((volatile unsigned int*)(0x42CE14A8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A11 *((volatile unsigned int*)(0x42CE14ACUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A12 *((volatile unsigned int*)(0x42CE14B0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A13 *((volatile unsigned int*)(0x42CE14B4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A14 *((volatile unsigned int*)(0x42CE14B8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A15 *((volatile unsigned int*)(0x42CE14BCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A16 *((volatile unsigned int*)(0x42CE14C0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A17 *((volatile unsigned int*)(0x42CE14C4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A18 *((volatile unsigned int*)(0x42CE14C8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A19 *((volatile unsigned int*)(0x42CE14CCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A20 *((volatile unsigned int*)(0x42CE14D0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A21 *((volatile unsigned int*)(0x42CE14D4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A22 *((volatile unsigned int*)(0x42CE14D8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A23 *((volatile unsigned int*)(0x42CE14DCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A24 *((volatile unsigned int*)(0x42CE14E0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A25 *((volatile unsigned int*)(0x42CE14E4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A26 *((volatile unsigned int*)(0x42CE14E8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A27 *((volatile unsigned int*)(0x42CE14ECUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A28 *((volatile unsigned int*)(0x42CE14F0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A29 *((volatile unsigned int*)(0x42CE14F4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A30 *((volatile unsigned int*)(0x42CE14F8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A31 *((volatile unsigned int*)(0x42CE14FCUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A32 *((volatile unsigned int*)(0x42CE1500UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A33 *((volatile unsigned int*)(0x42CE1504UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A34 *((volatile unsigned int*)(0x42CE1508UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A35 *((volatile unsigned int*)(0x42CE150CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A36 *((volatile unsigned int*)(0x42CE1510UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A37 *((volatile unsigned int*)(0x42CE1514UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A38 *((volatile unsigned int*)(0x42CE1518UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A39 *((volatile unsigned int*)(0x42CE151CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A40 *((volatile unsigned int*)(0x42CE1520UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A41 *((volatile unsigned int*)(0x42CE1524UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A42 *((volatile unsigned int*)(0x42CE1528UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A43 *((volatile unsigned int*)(0x42CE152CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A44 *((volatile unsigned int*)(0x42CE1530UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A45 *((volatile unsigned int*)(0x42CE1534UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A46 *((volatile unsigned int*)(0x42CE1538UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A47 *((volatile unsigned int*)(0x42CE153CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC0 *((volatile unsigned int*)(0x42CE1560UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC1 *((volatile unsigned int*)(0x42CE1564UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC2 *((volatile unsigned int*)(0x42CE1568UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC3 *((volatile unsigned int*)(0x42CE156CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC4 *((volatile unsigned int*)(0x42CE1570UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC5 *((volatile unsigned int*)(0x42CE1574UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_SA *((volatile unsigned int*)(0x42CE1578UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_AE *((volatile unsigned int*)(0x42CE157CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A0 *((volatile unsigned int*)(0x42CE1580UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A1 *((volatile unsigned int*)(0x42CE1584UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A2 *((volatile unsigned int*)(0x42CE1588UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A3 *((volatile unsigned int*)(0x42CE158CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A4 *((volatile unsigned int*)(0x42CE1590UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A5 *((volatile unsigned int*)(0x42CE1594UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A6 *((volatile unsigned int*)(0x42CE1598UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A7 *((volatile unsigned int*)(0x42CE159CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A8 *((volatile unsigned int*)(0x42CE15A0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A9 *((volatile unsigned int*)(0x42CE15A4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A10 *((volatile unsigned int*)(0x42CE15A8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A11 *((volatile unsigned int*)(0x42CE15ACUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A12 *((volatile unsigned int*)(0x42CE15B0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A13 *((volatile unsigned int*)(0x42CE15B4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A14 *((volatile unsigned int*)(0x42CE15B8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A15 *((volatile unsigned int*)(0x42CE15BCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A16 *((volatile unsigned int*)(0x42CE15C0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A17 *((volatile unsigned int*)(0x42CE15C4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A18 *((volatile unsigned int*)(0x42CE15C8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A19 *((volatile unsigned int*)(0x42CE15CCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A20 *((volatile unsigned int*)(0x42CE15D0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A21 *((volatile unsigned int*)(0x42CE15D4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A22 *((volatile unsigned int*)(0x42CE15D8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A23 *((volatile unsigned int*)(0x42CE15DCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A24 *((volatile unsigned int*)(0x42CE15E0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A25 *((volatile unsigned int*)(0x42CE15E4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A26 *((volatile unsigned int*)(0x42CE15E8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A27 *((volatile unsigned int*)(0x42CE15ECUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A28 *((volatile unsigned int*)(0x42CE15F0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A29 *((volatile unsigned int*)(0x42CE15F4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A30 *((volatile unsigned int*)(0x42CE15F8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A31 *((volatile unsigned int*)(0x42CE15FCUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A32 *((volatile unsigned int*)(0x42CE1600UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A33 *((volatile unsigned int*)(0x42CE1604UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A34 *((volatile unsigned int*)(0x42CE1608UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A35 *((volatile unsigned int*)(0x42CE160CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A36 *((volatile unsigned int*)(0x42CE1610UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A37 *((volatile unsigned int*)(0x42CE1614UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A38 *((volatile unsigned int*)(0x42CE1618UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A39 *((volatile unsigned int*)(0x42CE161CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A40 *((volatile unsigned int*)(0x42CE1620UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A41 *((volatile unsigned int*)(0x42CE1624UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A42 *((volatile unsigned int*)(0x42CE1628UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A43 *((volatile unsigned int*)(0x42CE162CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A44 *((volatile unsigned int*)(0x42CE1630UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A45 *((volatile unsigned int*)(0x42CE1634UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A46 *((volatile unsigned int*)(0x42CE1638UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A47 *((volatile unsigned int*)(0x42CE163CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC0 *((volatile unsigned int*)(0x42CE1660UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC1 *((volatile unsigned int*)(0x42CE1664UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC2 *((volatile unsigned int*)(0x42CE1668UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC3 *((volatile unsigned int*)(0x42CE166CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC4 *((volatile unsigned int*)(0x42CE1670UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC5 *((volatile unsigned int*)(0x42CE1674UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_SA *((volatile unsigned int*)(0x42CE1678UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_AE *((volatile unsigned int*)(0x42CE167CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A0 *((volatile unsigned int*)(0x42CE1680UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A1 *((volatile unsigned int*)(0x42CE1684UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A2 *((volatile unsigned int*)(0x42CE1688UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A3 *((volatile unsigned int*)(0x42CE168CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A4 *((volatile unsigned int*)(0x42CE1690UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A5 *((volatile unsigned int*)(0x42CE1694UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A6 *((volatile unsigned int*)(0x42CE1698UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A7 *((volatile unsigned int*)(0x42CE169CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A8 *((volatile unsigned int*)(0x42CE16A0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A9 *((volatile unsigned int*)(0x42CE16A4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A10 *((volatile unsigned int*)(0x42CE16A8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A11 *((volatile unsigned int*)(0x42CE16ACUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A12 *((volatile unsigned int*)(0x42CE16B0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A13 *((volatile unsigned int*)(0x42CE16B4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A14 *((volatile unsigned int*)(0x42CE16B8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A15 *((volatile unsigned int*)(0x42CE16BCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A16 *((volatile unsigned int*)(0x42CE16C0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A17 *((volatile unsigned int*)(0x42CE16C4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A18 *((volatile unsigned int*)(0x42CE16C8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A19 *((volatile unsigned int*)(0x42CE16CCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A20 *((volatile unsigned int*)(0x42CE16D0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A21 *((volatile unsigned int*)(0x42CE16D4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A22 *((volatile unsigned int*)(0x42CE16D8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A23 *((volatile unsigned int*)(0x42CE16DCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A24 *((volatile unsigned int*)(0x42CE16E0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A25 *((volatile unsigned int*)(0x42CE16E4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A26 *((volatile unsigned int*)(0x42CE16E8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A27 *((volatile unsigned int*)(0x42CE16ECUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A28 *((volatile unsigned int*)(0x42CE16F0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A29 *((volatile unsigned int*)(0x42CE16F4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A30 *((volatile unsigned int*)(0x42CE16F8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A31 *((volatile unsigned int*)(0x42CE16FCUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A32 *((volatile unsigned int*)(0x42CE1700UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A33 *((volatile unsigned int*)(0x42CE1704UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A34 *((volatile unsigned int*)(0x42CE1708UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A35 *((volatile unsigned int*)(0x42CE170CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A36 *((volatile unsigned int*)(0x42CE1710UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A37 *((volatile unsigned int*)(0x42CE1714UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A38 *((volatile unsigned int*)(0x42CE1718UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A39 *((volatile unsigned int*)(0x42CE171CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A40 *((volatile unsigned int*)(0x42CE1720UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A41 *((volatile unsigned int*)(0x42CE1724UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A42 *((volatile unsigned int*)(0x42CE1728UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A43 *((volatile unsigned int*)(0x42CE172CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A44 *((volatile unsigned int*)(0x42CE1730UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A45 *((volatile unsigned int*)(0x42CE1734UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A46 *((volatile unsigned int*)(0x42CE1738UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A47 *((volatile unsigned int*)(0x42CE173CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC0 *((volatile unsigned int*)(0x42CE1760UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC1 *((volatile unsigned int*)(0x42CE1764UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC2 *((volatile unsigned int*)(0x42CE1768UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC3 *((volatile unsigned int*)(0x42CE176CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC4 *((volatile unsigned int*)(0x42CE1770UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC5 *((volatile unsigned int*)(0x42CE1774UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_SA *((volatile unsigned int*)(0x42CE1778UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_AE *((volatile unsigned int*)(0x42CE177CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A0 *((volatile unsigned int*)(0x42CE1780UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A1 *((volatile unsigned int*)(0x42CE1784UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A2 *((volatile unsigned int*)(0x42CE1788UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A3 *((volatile unsigned int*)(0x42CE178CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A4 *((volatile unsigned int*)(0x42CE1790UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A5 *((volatile unsigned int*)(0x42CE1794UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A6 *((volatile unsigned int*)(0x42CE1798UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A7 *((volatile unsigned int*)(0x42CE179CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A8 *((volatile unsigned int*)(0x42CE17A0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A9 *((volatile unsigned int*)(0x42CE17A4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A10 *((volatile unsigned int*)(0x42CE17A8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A11 *((volatile unsigned int*)(0x42CE17ACUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A12 *((volatile unsigned int*)(0x42CE17B0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A13 *((volatile unsigned int*)(0x42CE17B4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A14 *((volatile unsigned int*)(0x42CE17B8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A15 *((volatile unsigned int*)(0x42CE17BCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A16 *((volatile unsigned int*)(0x42CE17C0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A17 *((volatile unsigned int*)(0x42CE17C4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A18 *((volatile unsigned int*)(0x42CE17C8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A19 *((volatile unsigned int*)(0x42CE17CCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A20 *((volatile unsigned int*)(0x42CE17D0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A21 *((volatile unsigned int*)(0x42CE17D4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A22 *((volatile unsigned int*)(0x42CE17D8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A23 *((volatile unsigned int*)(0x42CE17DCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A24 *((volatile unsigned int*)(0x42CE17E0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A25 *((volatile unsigned int*)(0x42CE17E4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A26 *((volatile unsigned int*)(0x42CE17E8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A27 *((volatile unsigned int*)(0x42CE17ECUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A28 *((volatile unsigned int*)(0x42CE17F0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A29 *((volatile unsigned int*)(0x42CE17F4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A30 *((volatile unsigned int*)(0x42CE17F8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A31 *((volatile unsigned int*)(0x42CE17FCUL)) -#define bFM3_ETHERNET_MAC1_RGSR_LM *((volatile unsigned int*)(0x42CE1B00UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LSP0 *((volatile unsigned int*)(0x42CE1B04UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LSP1 *((volatile unsigned int*)(0x42CE1B08UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LS *((volatile unsigned int*)(0x42CE1B0CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSE *((volatile unsigned int*)(0x42CEE000UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TFCU *((volatile unsigned int*)(0x42CEE004UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSI *((volatile unsigned int*)(0x42CEE008UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSU *((volatile unsigned int*)(0x42CEE00CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TITE *((volatile unsigned int*)(0x42CEE010UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TARU *((volatile unsigned int*)(0x42CEE014UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSEA *((volatile unsigned int*)(0x42CEE020UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSDB *((volatile unsigned int*)(0x42CEE024UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSV2E *((volatile unsigned int*)(0x42CEE028UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TETSP *((volatile unsigned int*)(0x42CEE02CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E *((volatile unsigned int*)(0x42CEE030UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E *((volatile unsigned int*)(0x42CEE034UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TETSEM *((volatile unsigned int*)(0x42CEE038UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSMRM *((volatile unsigned int*)(0x42CEE03CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSPS0 *((volatile unsigned int*)(0x42CEE040UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSPS1 *((volatile unsigned int*)(0x42CEE044UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSENMF *((volatile unsigned int*)(0x42CEE048UL)) -#define bFM3_ETHERNET_MAC1_TSCR_ATSFC *((volatile unsigned int*)(0x42CEE060UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC0 *((volatile unsigned int*)(0x42CEE080UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC1 *((volatile unsigned int*)(0x42CEE084UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC2 *((volatile unsigned int*)(0x42CEE088UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC3 *((volatile unsigned int*)(0x42CEE08CUL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC4 *((volatile unsigned int*)(0x42CEE090UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC5 *((volatile unsigned int*)(0x42CEE094UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC6 *((volatile unsigned int*)(0x42CEE098UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC7 *((volatile unsigned int*)(0x42CEE09CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS0 *((volatile unsigned int*)(0x42CEE100UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS1 *((volatile unsigned int*)(0x42CEE104UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS2 *((volatile unsigned int*)(0x42CEE108UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS3 *((volatile unsigned int*)(0x42CEE10CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS4 *((volatile unsigned int*)(0x42CEE110UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS5 *((volatile unsigned int*)(0x42CEE114UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS6 *((volatile unsigned int*)(0x42CEE118UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS7 *((volatile unsigned int*)(0x42CEE11CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS8 *((volatile unsigned int*)(0x42CEE120UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS9 *((volatile unsigned int*)(0x42CEE124UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS10 *((volatile unsigned int*)(0x42CEE128UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS11 *((volatile unsigned int*)(0x42CEE12CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS12 *((volatile unsigned int*)(0x42CEE130UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS13 *((volatile unsigned int*)(0x42CEE134UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS14 *((volatile unsigned int*)(0x42CEE138UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS15 *((volatile unsigned int*)(0x42CEE13CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS16 *((volatile unsigned int*)(0x42CEE140UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS17 *((volatile unsigned int*)(0x42CEE144UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS18 *((volatile unsigned int*)(0x42CEE148UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS19 *((volatile unsigned int*)(0x42CEE14CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS20 *((volatile unsigned int*)(0x42CEE150UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS21 *((volatile unsigned int*)(0x42CEE154UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS22 *((volatile unsigned int*)(0x42CEE158UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS23 *((volatile unsigned int*)(0x42CEE15CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS24 *((volatile unsigned int*)(0x42CEE160UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS25 *((volatile unsigned int*)(0x42CEE164UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS26 *((volatile unsigned int*)(0x42CEE168UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS27 *((volatile unsigned int*)(0x42CEE16CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS28 *((volatile unsigned int*)(0x42CEE170UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS29 *((volatile unsigned int*)(0x42CEE174UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS30 *((volatile unsigned int*)(0x42CEE178UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS31 *((volatile unsigned int*)(0x42CEE17CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS0 *((volatile unsigned int*)(0x42CEE080UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS1 *((volatile unsigned int*)(0x42CEE084UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS2 *((volatile unsigned int*)(0x42CEE088UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS3 *((volatile unsigned int*)(0x42CEE08CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS4 *((volatile unsigned int*)(0x42CEE090UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS5 *((volatile unsigned int*)(0x42CEE094UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS6 *((volatile unsigned int*)(0x42CEE098UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS7 *((volatile unsigned int*)(0x42CEE09CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS8 *((volatile unsigned int*)(0x42CEE0A0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS9 *((volatile unsigned int*)(0x42CEE0A4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS10 *((volatile unsigned int*)(0x42CEE0A8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS11 *((volatile unsigned int*)(0x42CEE0ACUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS12 *((volatile unsigned int*)(0x42CEE0B0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS13 *((volatile unsigned int*)(0x42CEE0B4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS14 *((volatile unsigned int*)(0x42CEE0B8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS15 *((volatile unsigned int*)(0x42CEE0BCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS16 *((volatile unsigned int*)(0x42CEE0C0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS17 *((volatile unsigned int*)(0x42CEE0C4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS18 *((volatile unsigned int*)(0x42CEE0C8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS19 *((volatile unsigned int*)(0x42CEE0CCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS20 *((volatile unsigned int*)(0x42CEE0D0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS21 *((volatile unsigned int*)(0x42CEE0D4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS22 *((volatile unsigned int*)(0x42CEE0D8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS23 *((volatile unsigned int*)(0x42CEE0DCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS24 *((volatile unsigned int*)(0x42CEE0E0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS25 *((volatile unsigned int*)(0x42CEE0E4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS26 *((volatile unsigned int*)(0x42CEE0E8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS27 *((volatile unsigned int*)(0x42CEE0ECUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS28 *((volatile unsigned int*)(0x42CEE0F0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS29 *((volatile unsigned int*)(0x42CEE0F4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS30 *((volatile unsigned int*)(0x42CEE0F8UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS0 *((volatile unsigned int*)(0x42CEE200UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS1 *((volatile unsigned int*)(0x42CEE204UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS2 *((volatile unsigned int*)(0x42CEE208UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS3 *((volatile unsigned int*)(0x42CEE20CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS4 *((volatile unsigned int*)(0x42CEE210UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS5 *((volatile unsigned int*)(0x42CEE214UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS6 *((volatile unsigned int*)(0x42CEE218UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS7 *((volatile unsigned int*)(0x42CEE21CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS8 *((volatile unsigned int*)(0x42CEE220UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS9 *((volatile unsigned int*)(0x42CEE224UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS10 *((volatile unsigned int*)(0x42CEE228UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS11 *((volatile unsigned int*)(0x42CEE22CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS12 *((volatile unsigned int*)(0x42CEE230UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS13 *((volatile unsigned int*)(0x42CEE234UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS14 *((volatile unsigned int*)(0x42CEE238UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS15 *((volatile unsigned int*)(0x42CEE23CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS16 *((volatile unsigned int*)(0x42CEE240UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS17 *((volatile unsigned int*)(0x42CEE244UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS18 *((volatile unsigned int*)(0x42CEE248UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS19 *((volatile unsigned int*)(0x42CEE24CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS20 *((volatile unsigned int*)(0x42CEE250UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS21 *((volatile unsigned int*)(0x42CEE254UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS22 *((volatile unsigned int*)(0x42CEE258UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS23 *((volatile unsigned int*)(0x42CEE25CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS24 *((volatile unsigned int*)(0x42CEE260UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS25 *((volatile unsigned int*)(0x42CEE264UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS26 *((volatile unsigned int*)(0x42CEE268UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS27 *((volatile unsigned int*)(0x42CEE26CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS28 *((volatile unsigned int*)(0x42CEE270UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS29 *((volatile unsigned int*)(0x42CEE274UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS30 *((volatile unsigned int*)(0x42CEE278UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS31 *((volatile unsigned int*)(0x42CEE27CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS0 *((volatile unsigned int*)(0x42CEE280UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS1 *((volatile unsigned int*)(0x42CEE284UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS2 *((volatile unsigned int*)(0x42CEE288UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS3 *((volatile unsigned int*)(0x42CEE28CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS4 *((volatile unsigned int*)(0x42CEE290UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS5 *((volatile unsigned int*)(0x42CEE294UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS6 *((volatile unsigned int*)(0x42CEE298UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS7 *((volatile unsigned int*)(0x42CEE29CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS8 *((volatile unsigned int*)(0x42CEE2A0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS9 *((volatile unsigned int*)(0x42CEE2A4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS10 *((volatile unsigned int*)(0x42CEE2A8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS11 *((volatile unsigned int*)(0x42CEE2ACUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS12 *((volatile unsigned int*)(0x42CEE2B0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS13 *((volatile unsigned int*)(0x42CEE2B4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS14 *((volatile unsigned int*)(0x42CEE2B8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS15 *((volatile unsigned int*)(0x42CEE2BCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS16 *((volatile unsigned int*)(0x42CEE2C0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS17 *((volatile unsigned int*)(0x42CEE2C4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS18 *((volatile unsigned int*)(0x42CEE2C8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS19 *((volatile unsigned int*)(0x42CEE2CCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS20 *((volatile unsigned int*)(0x42CEE2D0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS21 *((volatile unsigned int*)(0x42CEE2D4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS22 *((volatile unsigned int*)(0x42CEE2D8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS23 *((volatile unsigned int*)(0x42CEE2DCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS24 *((volatile unsigned int*)(0x42CEE2E0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS25 *((volatile unsigned int*)(0x42CEE2E4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS26 *((volatile unsigned int*)(0x42CEE2E8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS27 *((volatile unsigned int*)(0x42CEE2ECUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS28 *((volatile unsigned int*)(0x42CEE2F0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS29 *((volatile unsigned int*)(0x42CEE2F4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS30 *((volatile unsigned int*)(0x42CEE2F8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB *((volatile unsigned int*)(0x42CEE2FCUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR0 *((volatile unsigned int*)(0x42CEE300UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR1 *((volatile unsigned int*)(0x42CEE304UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR2 *((volatile unsigned int*)(0x42CEE308UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR3 *((volatile unsigned int*)(0x42CEE30CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR4 *((volatile unsigned int*)(0x42CEE310UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR5 *((volatile unsigned int*)(0x42CEE314UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR6 *((volatile unsigned int*)(0x42CEE318UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR7 *((volatile unsigned int*)(0x42CEE31CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR8 *((volatile unsigned int*)(0x42CEE320UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR9 *((volatile unsigned int*)(0x42CEE324UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR10 *((volatile unsigned int*)(0x42CEE328UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR11 *((volatile unsigned int*)(0x42CEE32CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR12 *((volatile unsigned int*)(0x42CEE330UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR13 *((volatile unsigned int*)(0x42CEE334UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR14 *((volatile unsigned int*)(0x42CEE338UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR15 *((volatile unsigned int*)(0x42CEE33CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR16 *((volatile unsigned int*)(0x42CEE340UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR17 *((volatile unsigned int*)(0x42CEE344UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR18 *((volatile unsigned int*)(0x42CEE348UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR19 *((volatile unsigned int*)(0x42CEE34CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR20 *((volatile unsigned int*)(0x42CEE350UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR21 *((volatile unsigned int*)(0x42CEE354UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR22 *((volatile unsigned int*)(0x42CEE358UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR23 *((volatile unsigned int*)(0x42CEE35CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR24 *((volatile unsigned int*)(0x42CEE360UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR25 *((volatile unsigned int*)(0x42CEE364UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR26 *((volatile unsigned int*)(0x42CEE368UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR27 *((volatile unsigned int*)(0x42CEE36CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR28 *((volatile unsigned int*)(0x42CEE370UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR29 *((volatile unsigned int*)(0x42CEE374UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR30 *((volatile unsigned int*)(0x42CEE378UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR31 *((volatile unsigned int*)(0x42CEE37CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR0 *((volatile unsigned int*)(0x42CEE380UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR1 *((volatile unsigned int*)(0x42CEE384UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR2 *((volatile unsigned int*)(0x42CEE388UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR3 *((volatile unsigned int*)(0x42CEE38CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR4 *((volatile unsigned int*)(0x42CEE390UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR5 *((volatile unsigned int*)(0x42CEE394UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR6 *((volatile unsigned int*)(0x42CEE398UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR7 *((volatile unsigned int*)(0x42CEE39CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR8 *((volatile unsigned int*)(0x42CEE3A0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR9 *((volatile unsigned int*)(0x42CEE3A4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR10 *((volatile unsigned int*)(0x42CEE3A8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR11 *((volatile unsigned int*)(0x42CEE3ACUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR12 *((volatile unsigned int*)(0x42CEE3B0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR13 *((volatile unsigned int*)(0x42CEE3B4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR14 *((volatile unsigned int*)(0x42CEE3B8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR15 *((volatile unsigned int*)(0x42CEE3BCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR16 *((volatile unsigned int*)(0x42CEE3C0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR17 *((volatile unsigned int*)(0x42CEE3C4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR18 *((volatile unsigned int*)(0x42CEE3C8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR19 *((volatile unsigned int*)(0x42CEE3CCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR20 *((volatile unsigned int*)(0x42CEE3D0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR21 *((volatile unsigned int*)(0x42CEE3D4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR22 *((volatile unsigned int*)(0x42CEE3D8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR23 *((volatile unsigned int*)(0x42CEE3DCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR24 *((volatile unsigned int*)(0x42CEE3E0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR25 *((volatile unsigned int*)(0x42CEE3E4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR26 *((volatile unsigned int*)(0x42CEE3E8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR27 *((volatile unsigned int*)(0x42CEE3ECUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR28 *((volatile unsigned int*)(0x42CEE3F0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR29 *((volatile unsigned int*)(0x42CEE3F4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR30 *((volatile unsigned int*)(0x42CEE3F8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR31 *((volatile unsigned int*)(0x42CEE3FCUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR0 *((volatile unsigned int*)(0x42CEE400UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR1 *((volatile unsigned int*)(0x42CEE404UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR2 *((volatile unsigned int*)(0x42CEE408UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR3 *((volatile unsigned int*)(0x42CEE40CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR4 *((volatile unsigned int*)(0x42CEE410UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR5 *((volatile unsigned int*)(0x42CEE414UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR6 *((volatile unsigned int*)(0x42CEE418UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR7 *((volatile unsigned int*)(0x42CEE41CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR8 *((volatile unsigned int*)(0x42CEE420UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR9 *((volatile unsigned int*)(0x42CEE424UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR10 *((volatile unsigned int*)(0x42CEE428UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR11 *((volatile unsigned int*)(0x42CEE42CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR12 *((volatile unsigned int*)(0x42CEE430UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR13 *((volatile unsigned int*)(0x42CEE434UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR14 *((volatile unsigned int*)(0x42CEE438UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR15 *((volatile unsigned int*)(0x42CEE43CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR16 *((volatile unsigned int*)(0x42CEE440UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR17 *((volatile unsigned int*)(0x42CEE444UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR18 *((volatile unsigned int*)(0x42CEE448UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR19 *((volatile unsigned int*)(0x42CEE44CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR20 *((volatile unsigned int*)(0x42CEE450UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR21 *((volatile unsigned int*)(0x42CEE454UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR22 *((volatile unsigned int*)(0x42CEE458UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR23 *((volatile unsigned int*)(0x42CEE45CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR24 *((volatile unsigned int*)(0x42CEE460UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR25 *((volatile unsigned int*)(0x42CEE464UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR26 *((volatile unsigned int*)(0x42CEE468UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR27 *((volatile unsigned int*)(0x42CEE46CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR28 *((volatile unsigned int*)(0x42CEE470UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR29 *((volatile unsigned int*)(0x42CEE474UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR30 *((volatile unsigned int*)(0x42CEE478UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42CEE480UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42CEE484UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42CEE488UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42CEE48CUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42CEE490UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42CEE494UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42CEE498UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42CEE49CUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42CEE4A0UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42CEE4A4UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42CEE4A8UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42CEE4ACUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42CEE4B0UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42CEE4B4UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42CEE4B8UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42CEE4BCUL)) -#define bFM3_ETHERNET_MAC1_TSR_TSSOVF *((volatile unsigned int*)(0x42CEE500UL)) -#define bFM3_ETHERNET_MAC1_TSR_TSTART *((volatile unsigned int*)(0x42CEE504UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSTS *((volatile unsigned int*)(0x42CEE508UL)) -#define bFM3_ETHERNET_MAC1_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSSTM *((volatile unsigned int*)(0x42CEE560UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS0 *((volatile unsigned int*)(0x42CEE564UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS1 *((volatile unsigned int*)(0x42CEE568UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS2 *((volatile unsigned int*)(0x42CEE56CUL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42CEE580UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42CEE584UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42CEE588UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42CEE58CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN0 *((volatile unsigned int*)(0x42CEE600UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN1 *((volatile unsigned int*)(0x42CEE604UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN2 *((volatile unsigned int*)(0x42CEE608UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN3 *((volatile unsigned int*)(0x42CEE60CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN4 *((volatile unsigned int*)(0x42CEE610UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN5 *((volatile unsigned int*)(0x42CEE614UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN6 *((volatile unsigned int*)(0x42CEE618UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN7 *((volatile unsigned int*)(0x42CEE61CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN8 *((volatile unsigned int*)(0x42CEE620UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN9 *((volatile unsigned int*)(0x42CEE624UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN10 *((volatile unsigned int*)(0x42CEE628UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN11 *((volatile unsigned int*)(0x42CEE62CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN12 *((volatile unsigned int*)(0x42CEE630UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN13 *((volatile unsigned int*)(0x42CEE634UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN14 *((volatile unsigned int*)(0x42CEE638UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN15 *((volatile unsigned int*)(0x42CEE63CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN16 *((volatile unsigned int*)(0x42CEE640UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN17 *((volatile unsigned int*)(0x42CEE644UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN18 *((volatile unsigned int*)(0x42CEE648UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN19 *((volatile unsigned int*)(0x42CEE64CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN20 *((volatile unsigned int*)(0x42CEE650UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN21 *((volatile unsigned int*)(0x42CEE654UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN22 *((volatile unsigned int*)(0x42CEE658UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN23 *((volatile unsigned int*)(0x42CEE65CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN24 *((volatile unsigned int*)(0x42CEE660UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN25 *((volatile unsigned int*)(0x42CEE664UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN26 *((volatile unsigned int*)(0x42CEE668UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN27 *((volatile unsigned int*)(0x42CEE66CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN28 *((volatile unsigned int*)(0x42CEE670UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN29 *((volatile unsigned int*)(0x42CEE674UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN30 *((volatile unsigned int*)(0x42CEE678UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS0 *((volatile unsigned int*)(0x42CEE680UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS1 *((volatile unsigned int*)(0x42CEE684UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS2 *((volatile unsigned int*)(0x42CEE688UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS3 *((volatile unsigned int*)(0x42CEE68CUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS4 *((volatile unsigned int*)(0x42CEE690UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS5 *((volatile unsigned int*)(0x42CEE694UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS6 *((volatile unsigned int*)(0x42CEE698UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS7 *((volatile unsigned int*)(0x42CEE69CUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS8 *((volatile unsigned int*)(0x42CEE6A0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS9 *((volatile unsigned int*)(0x42CEE6A4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS10 *((volatile unsigned int*)(0x42CEE6A8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS11 *((volatile unsigned int*)(0x42CEE6ACUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS12 *((volatile unsigned int*)(0x42CEE6B0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS13 *((volatile unsigned int*)(0x42CEE6B4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS14 *((volatile unsigned int*)(0x42CEE6B8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS15 *((volatile unsigned int*)(0x42CEE6BCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS16 *((volatile unsigned int*)(0x42CEE6C0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS17 *((volatile unsigned int*)(0x42CEE6C4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS18 *((volatile unsigned int*)(0x42CEE6C8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS19 *((volatile unsigned int*)(0x42CEE6CCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS20 *((volatile unsigned int*)(0x42CEE6D0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS21 *((volatile unsigned int*)(0x42CEE6D4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS22 *((volatile unsigned int*)(0x42CEE6D8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS23 *((volatile unsigned int*)(0x42CEE6DCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS24 *((volatile unsigned int*)(0x42CEE6E0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS25 *((volatile unsigned int*)(0x42CEE6E4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS26 *((volatile unsigned int*)(0x42CEE6E8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS27 *((volatile unsigned int*)(0x42CEE6ECUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS28 *((volatile unsigned int*)(0x42CEE6F0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS29 *((volatile unsigned int*)(0x42CEE6F4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS30 *((volatile unsigned int*)(0x42CEE6F8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS31 *((volatile unsigned int*)(0x42CEE6FCUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A32 *((volatile unsigned int*)(0x42CF0000UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A33 *((volatile unsigned int*)(0x42CF0004UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A34 *((volatile unsigned int*)(0x42CF0008UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A35 *((volatile unsigned int*)(0x42CF000CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A36 *((volatile unsigned int*)(0x42CF0010UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A37 *((volatile unsigned int*)(0x42CF0014UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A38 *((volatile unsigned int*)(0x42CF0018UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A39 *((volatile unsigned int*)(0x42CF001CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A40 *((volatile unsigned int*)(0x42CF0020UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A41 *((volatile unsigned int*)(0x42CF0024UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A42 *((volatile unsigned int*)(0x42CF0028UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A43 *((volatile unsigned int*)(0x42CF002CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A44 *((volatile unsigned int*)(0x42CF0030UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A45 *((volatile unsigned int*)(0x42CF0034UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A46 *((volatile unsigned int*)(0x42CF0038UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A47 *((volatile unsigned int*)(0x42CF003CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC0 *((volatile unsigned int*)(0x42CF0060UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC1 *((volatile unsigned int*)(0x42CF0064UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC2 *((volatile unsigned int*)(0x42CF0068UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC3 *((volatile unsigned int*)(0x42CF006CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC4 *((volatile unsigned int*)(0x42CF0070UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC5 *((volatile unsigned int*)(0x42CF0074UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_SA *((volatile unsigned int*)(0x42CF0078UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_AE *((volatile unsigned int*)(0x42CF007CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A0 *((volatile unsigned int*)(0x42CF0080UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A1 *((volatile unsigned int*)(0x42CF0084UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A2 *((volatile unsigned int*)(0x42CF0088UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A3 *((volatile unsigned int*)(0x42CF008CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A4 *((volatile unsigned int*)(0x42CF0090UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A5 *((volatile unsigned int*)(0x42CF0094UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A6 *((volatile unsigned int*)(0x42CF0098UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A7 *((volatile unsigned int*)(0x42CF009CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A8 *((volatile unsigned int*)(0x42CF00A0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A9 *((volatile unsigned int*)(0x42CF00A4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A10 *((volatile unsigned int*)(0x42CF00A8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A11 *((volatile unsigned int*)(0x42CF00ACUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A12 *((volatile unsigned int*)(0x42CF00B0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A13 *((volatile unsigned int*)(0x42CF00B4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A14 *((volatile unsigned int*)(0x42CF00B8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A15 *((volatile unsigned int*)(0x42CF00BCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A16 *((volatile unsigned int*)(0x42CF00C0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A17 *((volatile unsigned int*)(0x42CF00C4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A18 *((volatile unsigned int*)(0x42CF00C8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A19 *((volatile unsigned int*)(0x42CF00CCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A20 *((volatile unsigned int*)(0x42CF00D0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A21 *((volatile unsigned int*)(0x42CF00D4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A22 *((volatile unsigned int*)(0x42CF00D8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A23 *((volatile unsigned int*)(0x42CF00DCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A24 *((volatile unsigned int*)(0x42CF00E0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A25 *((volatile unsigned int*)(0x42CF00E4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A26 *((volatile unsigned int*)(0x42CF00E8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A27 *((volatile unsigned int*)(0x42CF00ECUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A28 *((volatile unsigned int*)(0x42CF00F0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A29 *((volatile unsigned int*)(0x42CF00F4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A30 *((volatile unsigned int*)(0x42CF00F8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A31 *((volatile unsigned int*)(0x42CF00FCUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A32 *((volatile unsigned int*)(0x42CF0100UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A33 *((volatile unsigned int*)(0x42CF0104UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A34 *((volatile unsigned int*)(0x42CF0108UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A35 *((volatile unsigned int*)(0x42CF010CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A36 *((volatile unsigned int*)(0x42CF0110UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A37 *((volatile unsigned int*)(0x42CF0114UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A38 *((volatile unsigned int*)(0x42CF0118UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A39 *((volatile unsigned int*)(0x42CF011CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A40 *((volatile unsigned int*)(0x42CF0120UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A41 *((volatile unsigned int*)(0x42CF0124UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A42 *((volatile unsigned int*)(0x42CF0128UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A43 *((volatile unsigned int*)(0x42CF012CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A44 *((volatile unsigned int*)(0x42CF0130UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A45 *((volatile unsigned int*)(0x42CF0134UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A46 *((volatile unsigned int*)(0x42CF0138UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A47 *((volatile unsigned int*)(0x42CF013CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC0 *((volatile unsigned int*)(0x42CF0160UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC1 *((volatile unsigned int*)(0x42CF0164UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC2 *((volatile unsigned int*)(0x42CF0168UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC3 *((volatile unsigned int*)(0x42CF016CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC4 *((volatile unsigned int*)(0x42CF0170UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC5 *((volatile unsigned int*)(0x42CF0174UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_SA *((volatile unsigned int*)(0x42CF0178UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_AE *((volatile unsigned int*)(0x42CF017CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A0 *((volatile unsigned int*)(0x42CF0180UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A1 *((volatile unsigned int*)(0x42CF0184UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A2 *((volatile unsigned int*)(0x42CF0188UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A3 *((volatile unsigned int*)(0x42CF018CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A4 *((volatile unsigned int*)(0x42CF0190UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A5 *((volatile unsigned int*)(0x42CF0194UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A6 *((volatile unsigned int*)(0x42CF0198UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A7 *((volatile unsigned int*)(0x42CF019CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A8 *((volatile unsigned int*)(0x42CF01A0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A9 *((volatile unsigned int*)(0x42CF01A4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A10 *((volatile unsigned int*)(0x42CF01A8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A11 *((volatile unsigned int*)(0x42CF01ACUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A12 *((volatile unsigned int*)(0x42CF01B0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A13 *((volatile unsigned int*)(0x42CF01B4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A14 *((volatile unsigned int*)(0x42CF01B8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A15 *((volatile unsigned int*)(0x42CF01BCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A16 *((volatile unsigned int*)(0x42CF01C0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A17 *((volatile unsigned int*)(0x42CF01C4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A18 *((volatile unsigned int*)(0x42CF01C8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A19 *((volatile unsigned int*)(0x42CF01CCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A20 *((volatile unsigned int*)(0x42CF01D0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A21 *((volatile unsigned int*)(0x42CF01D4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A22 *((volatile unsigned int*)(0x42CF01D8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A23 *((volatile unsigned int*)(0x42CF01DCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A24 *((volatile unsigned int*)(0x42CF01E0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A25 *((volatile unsigned int*)(0x42CF01E4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A26 *((volatile unsigned int*)(0x42CF01E8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A27 *((volatile unsigned int*)(0x42CF01ECUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A28 *((volatile unsigned int*)(0x42CF01F0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A29 *((volatile unsigned int*)(0x42CF01F4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A30 *((volatile unsigned int*)(0x42CF01F8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A31 *((volatile unsigned int*)(0x42CF01FCUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A32 *((volatile unsigned int*)(0x42CF0200UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A33 *((volatile unsigned int*)(0x42CF0204UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A34 *((volatile unsigned int*)(0x42CF0208UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A35 *((volatile unsigned int*)(0x42CF020CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A36 *((volatile unsigned int*)(0x42CF0210UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A37 *((volatile unsigned int*)(0x42CF0214UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A38 *((volatile unsigned int*)(0x42CF0218UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A39 *((volatile unsigned int*)(0x42CF021CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A40 *((volatile unsigned int*)(0x42CF0220UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A41 *((volatile unsigned int*)(0x42CF0224UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A42 *((volatile unsigned int*)(0x42CF0228UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A43 *((volatile unsigned int*)(0x42CF022CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A44 *((volatile unsigned int*)(0x42CF0230UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A45 *((volatile unsigned int*)(0x42CF0234UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A46 *((volatile unsigned int*)(0x42CF0238UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A47 *((volatile unsigned int*)(0x42CF023CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC0 *((volatile unsigned int*)(0x42CF0260UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC1 *((volatile unsigned int*)(0x42CF0264UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC2 *((volatile unsigned int*)(0x42CF0268UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC3 *((volatile unsigned int*)(0x42CF026CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC4 *((volatile unsigned int*)(0x42CF0270UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC5 *((volatile unsigned int*)(0x42CF0274UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_SA *((volatile unsigned int*)(0x42CF0278UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_AE *((volatile unsigned int*)(0x42CF027CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A0 *((volatile unsigned int*)(0x42CF0280UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A1 *((volatile unsigned int*)(0x42CF0284UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A2 *((volatile unsigned int*)(0x42CF0288UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A3 *((volatile unsigned int*)(0x42CF028CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A4 *((volatile unsigned int*)(0x42CF0290UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A5 *((volatile unsigned int*)(0x42CF0294UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A6 *((volatile unsigned int*)(0x42CF0298UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A7 *((volatile unsigned int*)(0x42CF029CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A8 *((volatile unsigned int*)(0x42CF02A0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A9 *((volatile unsigned int*)(0x42CF02A4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A10 *((volatile unsigned int*)(0x42CF02A8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A11 *((volatile unsigned int*)(0x42CF02ACUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A12 *((volatile unsigned int*)(0x42CF02B0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A13 *((volatile unsigned int*)(0x42CF02B4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A14 *((volatile unsigned int*)(0x42CF02B8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A15 *((volatile unsigned int*)(0x42CF02BCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A16 *((volatile unsigned int*)(0x42CF02C0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A17 *((volatile unsigned int*)(0x42CF02C4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A18 *((volatile unsigned int*)(0x42CF02C8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A19 *((volatile unsigned int*)(0x42CF02CCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A20 *((volatile unsigned int*)(0x42CF02D0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A21 *((volatile unsigned int*)(0x42CF02D4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A22 *((volatile unsigned int*)(0x42CF02D8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A23 *((volatile unsigned int*)(0x42CF02DCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A24 *((volatile unsigned int*)(0x42CF02E0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A25 *((volatile unsigned int*)(0x42CF02E4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A26 *((volatile unsigned int*)(0x42CF02E8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A27 *((volatile unsigned int*)(0x42CF02ECUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A28 *((volatile unsigned int*)(0x42CF02F0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A29 *((volatile unsigned int*)(0x42CF02F4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A30 *((volatile unsigned int*)(0x42CF02F8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A31 *((volatile unsigned int*)(0x42CF02FCUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A32 *((volatile unsigned int*)(0x42CF0300UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A33 *((volatile unsigned int*)(0x42CF0304UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A34 *((volatile unsigned int*)(0x42CF0308UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A35 *((volatile unsigned int*)(0x42CF030CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A36 *((volatile unsigned int*)(0x42CF0310UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A37 *((volatile unsigned int*)(0x42CF0314UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A38 *((volatile unsigned int*)(0x42CF0318UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A39 *((volatile unsigned int*)(0x42CF031CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A40 *((volatile unsigned int*)(0x42CF0320UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A41 *((volatile unsigned int*)(0x42CF0324UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A42 *((volatile unsigned int*)(0x42CF0328UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A43 *((volatile unsigned int*)(0x42CF032CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A44 *((volatile unsigned int*)(0x42CF0330UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A45 *((volatile unsigned int*)(0x42CF0334UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A46 *((volatile unsigned int*)(0x42CF0338UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A47 *((volatile unsigned int*)(0x42CF033CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC0 *((volatile unsigned int*)(0x42CF0360UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC1 *((volatile unsigned int*)(0x42CF0364UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC2 *((volatile unsigned int*)(0x42CF0368UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC3 *((volatile unsigned int*)(0x42CF036CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC4 *((volatile unsigned int*)(0x42CF0370UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC5 *((volatile unsigned int*)(0x42CF0374UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_SA *((volatile unsigned int*)(0x42CF0378UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_AE *((volatile unsigned int*)(0x42CF037CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A0 *((volatile unsigned int*)(0x42CF0380UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A1 *((volatile unsigned int*)(0x42CF0384UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A2 *((volatile unsigned int*)(0x42CF0388UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A3 *((volatile unsigned int*)(0x42CF038CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A4 *((volatile unsigned int*)(0x42CF0390UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A5 *((volatile unsigned int*)(0x42CF0394UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A6 *((volatile unsigned int*)(0x42CF0398UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A7 *((volatile unsigned int*)(0x42CF039CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A8 *((volatile unsigned int*)(0x42CF03A0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A9 *((volatile unsigned int*)(0x42CF03A4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A10 *((volatile unsigned int*)(0x42CF03A8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A11 *((volatile unsigned int*)(0x42CF03ACUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A12 *((volatile unsigned int*)(0x42CF03B0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A13 *((volatile unsigned int*)(0x42CF03B4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A14 *((volatile unsigned int*)(0x42CF03B8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A15 *((volatile unsigned int*)(0x42CF03BCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A16 *((volatile unsigned int*)(0x42CF03C0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A17 *((volatile unsigned int*)(0x42CF03C4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A18 *((volatile unsigned int*)(0x42CF03C8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A19 *((volatile unsigned int*)(0x42CF03CCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A20 *((volatile unsigned int*)(0x42CF03D0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A21 *((volatile unsigned int*)(0x42CF03D4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A22 *((volatile unsigned int*)(0x42CF03D8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A23 *((volatile unsigned int*)(0x42CF03DCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A24 *((volatile unsigned int*)(0x42CF03E0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A25 *((volatile unsigned int*)(0x42CF03E4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A26 *((volatile unsigned int*)(0x42CF03E8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A27 *((volatile unsigned int*)(0x42CF03ECUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A28 *((volatile unsigned int*)(0x42CF03F0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A29 *((volatile unsigned int*)(0x42CF03F4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A30 *((volatile unsigned int*)(0x42CF03F8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A31 *((volatile unsigned int*)(0x42CF03FCUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A32 *((volatile unsigned int*)(0x42CF0400UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A33 *((volatile unsigned int*)(0x42CF0404UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A34 *((volatile unsigned int*)(0x42CF0408UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A35 *((volatile unsigned int*)(0x42CF040CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A36 *((volatile unsigned int*)(0x42CF0410UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A37 *((volatile unsigned int*)(0x42CF0414UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A38 *((volatile unsigned int*)(0x42CF0418UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A39 *((volatile unsigned int*)(0x42CF041CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A40 *((volatile unsigned int*)(0x42CF0420UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A41 *((volatile unsigned int*)(0x42CF0424UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A42 *((volatile unsigned int*)(0x42CF0428UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A43 *((volatile unsigned int*)(0x42CF042CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A44 *((volatile unsigned int*)(0x42CF0430UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A45 *((volatile unsigned int*)(0x42CF0434UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A46 *((volatile unsigned int*)(0x42CF0438UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A47 *((volatile unsigned int*)(0x42CF043CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC0 *((volatile unsigned int*)(0x42CF0460UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC1 *((volatile unsigned int*)(0x42CF0464UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC2 *((volatile unsigned int*)(0x42CF0468UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC3 *((volatile unsigned int*)(0x42CF046CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC4 *((volatile unsigned int*)(0x42CF0470UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC5 *((volatile unsigned int*)(0x42CF0474UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_SA *((volatile unsigned int*)(0x42CF0478UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_AE *((volatile unsigned int*)(0x42CF047CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A0 *((volatile unsigned int*)(0x42CF0480UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A1 *((volatile unsigned int*)(0x42CF0484UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A2 *((volatile unsigned int*)(0x42CF0488UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A3 *((volatile unsigned int*)(0x42CF048CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A4 *((volatile unsigned int*)(0x42CF0490UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A5 *((volatile unsigned int*)(0x42CF0494UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A6 *((volatile unsigned int*)(0x42CF0498UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A7 *((volatile unsigned int*)(0x42CF049CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A8 *((volatile unsigned int*)(0x42CF04A0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A9 *((volatile unsigned int*)(0x42CF04A4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A10 *((volatile unsigned int*)(0x42CF04A8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A11 *((volatile unsigned int*)(0x42CF04ACUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A12 *((volatile unsigned int*)(0x42CF04B0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A13 *((volatile unsigned int*)(0x42CF04B4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A14 *((volatile unsigned int*)(0x42CF04B8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A15 *((volatile unsigned int*)(0x42CF04BCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A16 *((volatile unsigned int*)(0x42CF04C0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A17 *((volatile unsigned int*)(0x42CF04C4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A18 *((volatile unsigned int*)(0x42CF04C8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A19 *((volatile unsigned int*)(0x42CF04CCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A20 *((volatile unsigned int*)(0x42CF04D0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A21 *((volatile unsigned int*)(0x42CF04D4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A22 *((volatile unsigned int*)(0x42CF04D8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A23 *((volatile unsigned int*)(0x42CF04DCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A24 *((volatile unsigned int*)(0x42CF04E0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A25 *((volatile unsigned int*)(0x42CF04E4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A26 *((volatile unsigned int*)(0x42CF04E8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A27 *((volatile unsigned int*)(0x42CF04ECUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A28 *((volatile unsigned int*)(0x42CF04F0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A29 *((volatile unsigned int*)(0x42CF04F4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A30 *((volatile unsigned int*)(0x42CF04F8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A31 *((volatile unsigned int*)(0x42CF04FCUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A32 *((volatile unsigned int*)(0x42CF0500UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A33 *((volatile unsigned int*)(0x42CF0504UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A34 *((volatile unsigned int*)(0x42CF0508UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A35 *((volatile unsigned int*)(0x42CF050CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A36 *((volatile unsigned int*)(0x42CF0510UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A37 *((volatile unsigned int*)(0x42CF0514UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A38 *((volatile unsigned int*)(0x42CF0518UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A39 *((volatile unsigned int*)(0x42CF051CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A40 *((volatile unsigned int*)(0x42CF0520UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A41 *((volatile unsigned int*)(0x42CF0524UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A42 *((volatile unsigned int*)(0x42CF0528UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A43 *((volatile unsigned int*)(0x42CF052CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A44 *((volatile unsigned int*)(0x42CF0530UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A45 *((volatile unsigned int*)(0x42CF0534UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A46 *((volatile unsigned int*)(0x42CF0538UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A47 *((volatile unsigned int*)(0x42CF053CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC0 *((volatile unsigned int*)(0x42CF0560UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC1 *((volatile unsigned int*)(0x42CF0564UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC2 *((volatile unsigned int*)(0x42CF0568UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC3 *((volatile unsigned int*)(0x42CF056CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC4 *((volatile unsigned int*)(0x42CF0570UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC5 *((volatile unsigned int*)(0x42CF0574UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_SA *((volatile unsigned int*)(0x42CF0578UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_AE *((volatile unsigned int*)(0x42CF057CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A0 *((volatile unsigned int*)(0x42CF0580UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A1 *((volatile unsigned int*)(0x42CF0584UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A2 *((volatile unsigned int*)(0x42CF0588UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A3 *((volatile unsigned int*)(0x42CF058CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A4 *((volatile unsigned int*)(0x42CF0590UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A5 *((volatile unsigned int*)(0x42CF0594UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A6 *((volatile unsigned int*)(0x42CF0598UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A7 *((volatile unsigned int*)(0x42CF059CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A8 *((volatile unsigned int*)(0x42CF05A0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A9 *((volatile unsigned int*)(0x42CF05A4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A10 *((volatile unsigned int*)(0x42CF05A8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A11 *((volatile unsigned int*)(0x42CF05ACUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A12 *((volatile unsigned int*)(0x42CF05B0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A13 *((volatile unsigned int*)(0x42CF05B4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A14 *((volatile unsigned int*)(0x42CF05B8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A15 *((volatile unsigned int*)(0x42CF05BCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A16 *((volatile unsigned int*)(0x42CF05C0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A17 *((volatile unsigned int*)(0x42CF05C4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A18 *((volatile unsigned int*)(0x42CF05C8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A19 *((volatile unsigned int*)(0x42CF05CCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A20 *((volatile unsigned int*)(0x42CF05D0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A21 *((volatile unsigned int*)(0x42CF05D4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A22 *((volatile unsigned int*)(0x42CF05D8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A23 *((volatile unsigned int*)(0x42CF05DCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A24 *((volatile unsigned int*)(0x42CF05E0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A25 *((volatile unsigned int*)(0x42CF05E4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A26 *((volatile unsigned int*)(0x42CF05E8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A27 *((volatile unsigned int*)(0x42CF05ECUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A28 *((volatile unsigned int*)(0x42CF05F0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A29 *((volatile unsigned int*)(0x42CF05F4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A30 *((volatile unsigned int*)(0x42CF05F8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A31 *((volatile unsigned int*)(0x42CF05FCUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A32 *((volatile unsigned int*)(0x42CF0600UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A33 *((volatile unsigned int*)(0x42CF0604UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A34 *((volatile unsigned int*)(0x42CF0608UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A35 *((volatile unsigned int*)(0x42CF060CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A36 *((volatile unsigned int*)(0x42CF0610UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A37 *((volatile unsigned int*)(0x42CF0614UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A38 *((volatile unsigned int*)(0x42CF0618UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A39 *((volatile unsigned int*)(0x42CF061CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A40 *((volatile unsigned int*)(0x42CF0620UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A41 *((volatile unsigned int*)(0x42CF0624UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A42 *((volatile unsigned int*)(0x42CF0628UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A43 *((volatile unsigned int*)(0x42CF062CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A44 *((volatile unsigned int*)(0x42CF0630UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A45 *((volatile unsigned int*)(0x42CF0634UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A46 *((volatile unsigned int*)(0x42CF0638UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A47 *((volatile unsigned int*)(0x42CF063CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC0 *((volatile unsigned int*)(0x42CF0660UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC1 *((volatile unsigned int*)(0x42CF0664UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC2 *((volatile unsigned int*)(0x42CF0668UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC3 *((volatile unsigned int*)(0x42CF066CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC4 *((volatile unsigned int*)(0x42CF0670UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC5 *((volatile unsigned int*)(0x42CF0674UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_SA *((volatile unsigned int*)(0x42CF0678UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_AE *((volatile unsigned int*)(0x42CF067CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A0 *((volatile unsigned int*)(0x42CF0680UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A1 *((volatile unsigned int*)(0x42CF0684UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A2 *((volatile unsigned int*)(0x42CF0688UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A3 *((volatile unsigned int*)(0x42CF068CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A4 *((volatile unsigned int*)(0x42CF0690UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A5 *((volatile unsigned int*)(0x42CF0694UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A6 *((volatile unsigned int*)(0x42CF0698UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A7 *((volatile unsigned int*)(0x42CF069CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A8 *((volatile unsigned int*)(0x42CF06A0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A9 *((volatile unsigned int*)(0x42CF06A4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A10 *((volatile unsigned int*)(0x42CF06A8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A11 *((volatile unsigned int*)(0x42CF06ACUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A12 *((volatile unsigned int*)(0x42CF06B0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A13 *((volatile unsigned int*)(0x42CF06B4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A14 *((volatile unsigned int*)(0x42CF06B8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A15 *((volatile unsigned int*)(0x42CF06BCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A16 *((volatile unsigned int*)(0x42CF06C0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A17 *((volatile unsigned int*)(0x42CF06C4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A18 *((volatile unsigned int*)(0x42CF06C8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A19 *((volatile unsigned int*)(0x42CF06CCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A20 *((volatile unsigned int*)(0x42CF06D0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A21 *((volatile unsigned int*)(0x42CF06D4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A22 *((volatile unsigned int*)(0x42CF06D8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A23 *((volatile unsigned int*)(0x42CF06DCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A24 *((volatile unsigned int*)(0x42CF06E0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A25 *((volatile unsigned int*)(0x42CF06E4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A26 *((volatile unsigned int*)(0x42CF06E8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A27 *((volatile unsigned int*)(0x42CF06ECUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A28 *((volatile unsigned int*)(0x42CF06F0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A29 *((volatile unsigned int*)(0x42CF06F4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A30 *((volatile unsigned int*)(0x42CF06F8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A31 *((volatile unsigned int*)(0x42CF06FCUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A32 *((volatile unsigned int*)(0x42CF0700UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A33 *((volatile unsigned int*)(0x42CF0704UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A34 *((volatile unsigned int*)(0x42CF0708UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A35 *((volatile unsigned int*)(0x42CF070CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A36 *((volatile unsigned int*)(0x42CF0710UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A37 *((volatile unsigned int*)(0x42CF0714UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A38 *((volatile unsigned int*)(0x42CF0718UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A39 *((volatile unsigned int*)(0x42CF071CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A40 *((volatile unsigned int*)(0x42CF0720UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A41 *((volatile unsigned int*)(0x42CF0724UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A42 *((volatile unsigned int*)(0x42CF0728UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A43 *((volatile unsigned int*)(0x42CF072CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A44 *((volatile unsigned int*)(0x42CF0730UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A45 *((volatile unsigned int*)(0x42CF0734UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A46 *((volatile unsigned int*)(0x42CF0738UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A47 *((volatile unsigned int*)(0x42CF073CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC0 *((volatile unsigned int*)(0x42CF0760UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC1 *((volatile unsigned int*)(0x42CF0764UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC2 *((volatile unsigned int*)(0x42CF0768UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC3 *((volatile unsigned int*)(0x42CF076CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC4 *((volatile unsigned int*)(0x42CF0770UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC5 *((volatile unsigned int*)(0x42CF0774UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_SA *((volatile unsigned int*)(0x42CF0778UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_AE *((volatile unsigned int*)(0x42CF077CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A0 *((volatile unsigned int*)(0x42CF0780UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A1 *((volatile unsigned int*)(0x42CF0784UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A2 *((volatile unsigned int*)(0x42CF0788UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A3 *((volatile unsigned int*)(0x42CF078CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A4 *((volatile unsigned int*)(0x42CF0790UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A5 *((volatile unsigned int*)(0x42CF0794UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A6 *((volatile unsigned int*)(0x42CF0798UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A7 *((volatile unsigned int*)(0x42CF079CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A8 *((volatile unsigned int*)(0x42CF07A0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A9 *((volatile unsigned int*)(0x42CF07A4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A10 *((volatile unsigned int*)(0x42CF07A8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A11 *((volatile unsigned int*)(0x42CF07ACUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A12 *((volatile unsigned int*)(0x42CF07B0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A13 *((volatile unsigned int*)(0x42CF07B4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A14 *((volatile unsigned int*)(0x42CF07B8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A15 *((volatile unsigned int*)(0x42CF07BCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A16 *((volatile unsigned int*)(0x42CF07C0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A17 *((volatile unsigned int*)(0x42CF07C4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A18 *((volatile unsigned int*)(0x42CF07C8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A19 *((volatile unsigned int*)(0x42CF07CCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A20 *((volatile unsigned int*)(0x42CF07D0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A21 *((volatile unsigned int*)(0x42CF07D4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A22 *((volatile unsigned int*)(0x42CF07D8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A23 *((volatile unsigned int*)(0x42CF07DCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A24 *((volatile unsigned int*)(0x42CF07E0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A25 *((volatile unsigned int*)(0x42CF07E4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A26 *((volatile unsigned int*)(0x42CF07E8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A27 *((volatile unsigned int*)(0x42CF07ECUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A28 *((volatile unsigned int*)(0x42CF07F0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A29 *((volatile unsigned int*)(0x42CF07F4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A30 *((volatile unsigned int*)(0x42CF07F8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A31 *((volatile unsigned int*)(0x42CF07FCUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A32 *((volatile unsigned int*)(0x42CF0800UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A33 *((volatile unsigned int*)(0x42CF0804UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A34 *((volatile unsigned int*)(0x42CF0808UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A35 *((volatile unsigned int*)(0x42CF080CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A36 *((volatile unsigned int*)(0x42CF0810UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A37 *((volatile unsigned int*)(0x42CF0814UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A38 *((volatile unsigned int*)(0x42CF0818UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A39 *((volatile unsigned int*)(0x42CF081CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A40 *((volatile unsigned int*)(0x42CF0820UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A41 *((volatile unsigned int*)(0x42CF0824UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A42 *((volatile unsigned int*)(0x42CF0828UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A43 *((volatile unsigned int*)(0x42CF082CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A44 *((volatile unsigned int*)(0x42CF0830UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A45 *((volatile unsigned int*)(0x42CF0834UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A46 *((volatile unsigned int*)(0x42CF0838UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A47 *((volatile unsigned int*)(0x42CF083CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC0 *((volatile unsigned int*)(0x42CF0860UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC1 *((volatile unsigned int*)(0x42CF0864UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC2 *((volatile unsigned int*)(0x42CF0868UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC3 *((volatile unsigned int*)(0x42CF086CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC4 *((volatile unsigned int*)(0x42CF0870UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC5 *((volatile unsigned int*)(0x42CF0874UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_SA *((volatile unsigned int*)(0x42CF0878UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_AE *((volatile unsigned int*)(0x42CF087CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A0 *((volatile unsigned int*)(0x42CF0880UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A1 *((volatile unsigned int*)(0x42CF0884UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A2 *((volatile unsigned int*)(0x42CF0888UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A3 *((volatile unsigned int*)(0x42CF088CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A4 *((volatile unsigned int*)(0x42CF0890UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A5 *((volatile unsigned int*)(0x42CF0894UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A6 *((volatile unsigned int*)(0x42CF0898UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A7 *((volatile unsigned int*)(0x42CF089CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A8 *((volatile unsigned int*)(0x42CF08A0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A9 *((volatile unsigned int*)(0x42CF08A4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A10 *((volatile unsigned int*)(0x42CF08A8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A11 *((volatile unsigned int*)(0x42CF08ACUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A12 *((volatile unsigned int*)(0x42CF08B0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A13 *((volatile unsigned int*)(0x42CF08B4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A14 *((volatile unsigned int*)(0x42CF08B8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A15 *((volatile unsigned int*)(0x42CF08BCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A16 *((volatile unsigned int*)(0x42CF08C0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A17 *((volatile unsigned int*)(0x42CF08C4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A18 *((volatile unsigned int*)(0x42CF08C8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A19 *((volatile unsigned int*)(0x42CF08CCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A20 *((volatile unsigned int*)(0x42CF08D0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A21 *((volatile unsigned int*)(0x42CF08D4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A22 *((volatile unsigned int*)(0x42CF08D8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A23 *((volatile unsigned int*)(0x42CF08DCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A24 *((volatile unsigned int*)(0x42CF08E0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A25 *((volatile unsigned int*)(0x42CF08E4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A26 *((volatile unsigned int*)(0x42CF08E8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A27 *((volatile unsigned int*)(0x42CF08ECUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A28 *((volatile unsigned int*)(0x42CF08F0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A29 *((volatile unsigned int*)(0x42CF08F4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A30 *((volatile unsigned int*)(0x42CF08F8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A31 *((volatile unsigned int*)(0x42CF08FCUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A32 *((volatile unsigned int*)(0x42CF0900UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A33 *((volatile unsigned int*)(0x42CF0904UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A34 *((volatile unsigned int*)(0x42CF0908UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A35 *((volatile unsigned int*)(0x42CF090CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A36 *((volatile unsigned int*)(0x42CF0910UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A37 *((volatile unsigned int*)(0x42CF0914UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A38 *((volatile unsigned int*)(0x42CF0918UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A39 *((volatile unsigned int*)(0x42CF091CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A40 *((volatile unsigned int*)(0x42CF0920UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A41 *((volatile unsigned int*)(0x42CF0924UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A42 *((volatile unsigned int*)(0x42CF0928UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A43 *((volatile unsigned int*)(0x42CF092CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A44 *((volatile unsigned int*)(0x42CF0930UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A45 *((volatile unsigned int*)(0x42CF0934UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A46 *((volatile unsigned int*)(0x42CF0938UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A47 *((volatile unsigned int*)(0x42CF093CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC0 *((volatile unsigned int*)(0x42CF0960UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC1 *((volatile unsigned int*)(0x42CF0964UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC2 *((volatile unsigned int*)(0x42CF0968UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC3 *((volatile unsigned int*)(0x42CF096CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC4 *((volatile unsigned int*)(0x42CF0970UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC5 *((volatile unsigned int*)(0x42CF0974UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_SA *((volatile unsigned int*)(0x42CF0978UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_AE *((volatile unsigned int*)(0x42CF097CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A0 *((volatile unsigned int*)(0x42CF0980UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A1 *((volatile unsigned int*)(0x42CF0984UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A2 *((volatile unsigned int*)(0x42CF0988UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A3 *((volatile unsigned int*)(0x42CF098CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A4 *((volatile unsigned int*)(0x42CF0990UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A5 *((volatile unsigned int*)(0x42CF0994UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A6 *((volatile unsigned int*)(0x42CF0998UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A7 *((volatile unsigned int*)(0x42CF099CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A8 *((volatile unsigned int*)(0x42CF09A0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A9 *((volatile unsigned int*)(0x42CF09A4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A10 *((volatile unsigned int*)(0x42CF09A8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A11 *((volatile unsigned int*)(0x42CF09ACUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A12 *((volatile unsigned int*)(0x42CF09B0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A13 *((volatile unsigned int*)(0x42CF09B4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A14 *((volatile unsigned int*)(0x42CF09B8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A15 *((volatile unsigned int*)(0x42CF09BCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A16 *((volatile unsigned int*)(0x42CF09C0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A17 *((volatile unsigned int*)(0x42CF09C4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A18 *((volatile unsigned int*)(0x42CF09C8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A19 *((volatile unsigned int*)(0x42CF09CCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A20 *((volatile unsigned int*)(0x42CF09D0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A21 *((volatile unsigned int*)(0x42CF09D4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A22 *((volatile unsigned int*)(0x42CF09D8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A23 *((volatile unsigned int*)(0x42CF09DCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A24 *((volatile unsigned int*)(0x42CF09E0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A25 *((volatile unsigned int*)(0x42CF09E4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A26 *((volatile unsigned int*)(0x42CF09E8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A27 *((volatile unsigned int*)(0x42CF09ECUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A28 *((volatile unsigned int*)(0x42CF09F0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A29 *((volatile unsigned int*)(0x42CF09F4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A30 *((volatile unsigned int*)(0x42CF09F8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A31 *((volatile unsigned int*)(0x42CF09FCUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A32 *((volatile unsigned int*)(0x42CF0A00UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A33 *((volatile unsigned int*)(0x42CF0A04UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A34 *((volatile unsigned int*)(0x42CF0A08UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A35 *((volatile unsigned int*)(0x42CF0A0CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A36 *((volatile unsigned int*)(0x42CF0A10UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A37 *((volatile unsigned int*)(0x42CF0A14UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A38 *((volatile unsigned int*)(0x42CF0A18UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A39 *((volatile unsigned int*)(0x42CF0A1CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A40 *((volatile unsigned int*)(0x42CF0A20UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A41 *((volatile unsigned int*)(0x42CF0A24UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A42 *((volatile unsigned int*)(0x42CF0A28UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A43 *((volatile unsigned int*)(0x42CF0A2CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A44 *((volatile unsigned int*)(0x42CF0A30UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A45 *((volatile unsigned int*)(0x42CF0A34UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A46 *((volatile unsigned int*)(0x42CF0A38UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A47 *((volatile unsigned int*)(0x42CF0A3CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC0 *((volatile unsigned int*)(0x42CF0A60UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC1 *((volatile unsigned int*)(0x42CF0A64UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC2 *((volatile unsigned int*)(0x42CF0A68UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC3 *((volatile unsigned int*)(0x42CF0A6CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC4 *((volatile unsigned int*)(0x42CF0A70UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC5 *((volatile unsigned int*)(0x42CF0A74UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_SA *((volatile unsigned int*)(0x42CF0A78UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_AE *((volatile unsigned int*)(0x42CF0A7CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A0 *((volatile unsigned int*)(0x42CF0A80UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A1 *((volatile unsigned int*)(0x42CF0A84UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A2 *((volatile unsigned int*)(0x42CF0A88UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A3 *((volatile unsigned int*)(0x42CF0A8CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A4 *((volatile unsigned int*)(0x42CF0A90UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A5 *((volatile unsigned int*)(0x42CF0A94UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A6 *((volatile unsigned int*)(0x42CF0A98UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A7 *((volatile unsigned int*)(0x42CF0A9CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A8 *((volatile unsigned int*)(0x42CF0AA0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A9 *((volatile unsigned int*)(0x42CF0AA4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A10 *((volatile unsigned int*)(0x42CF0AA8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A11 *((volatile unsigned int*)(0x42CF0AACUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A12 *((volatile unsigned int*)(0x42CF0AB0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A13 *((volatile unsigned int*)(0x42CF0AB4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A14 *((volatile unsigned int*)(0x42CF0AB8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A15 *((volatile unsigned int*)(0x42CF0ABCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A16 *((volatile unsigned int*)(0x42CF0AC0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A17 *((volatile unsigned int*)(0x42CF0AC4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A18 *((volatile unsigned int*)(0x42CF0AC8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A19 *((volatile unsigned int*)(0x42CF0ACCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A20 *((volatile unsigned int*)(0x42CF0AD0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A21 *((volatile unsigned int*)(0x42CF0AD4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A22 *((volatile unsigned int*)(0x42CF0AD8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A23 *((volatile unsigned int*)(0x42CF0ADCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A24 *((volatile unsigned int*)(0x42CF0AE0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A25 *((volatile unsigned int*)(0x42CF0AE4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A26 *((volatile unsigned int*)(0x42CF0AE8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A27 *((volatile unsigned int*)(0x42CF0AECUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A28 *((volatile unsigned int*)(0x42CF0AF0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A29 *((volatile unsigned int*)(0x42CF0AF4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A30 *((volatile unsigned int*)(0x42CF0AF8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A31 *((volatile unsigned int*)(0x42CF0AFCUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A32 *((volatile unsigned int*)(0x42CF0B00UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A33 *((volatile unsigned int*)(0x42CF0B04UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A34 *((volatile unsigned int*)(0x42CF0B08UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A35 *((volatile unsigned int*)(0x42CF0B0CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A36 *((volatile unsigned int*)(0x42CF0B10UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A37 *((volatile unsigned int*)(0x42CF0B14UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A38 *((volatile unsigned int*)(0x42CF0B18UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A39 *((volatile unsigned int*)(0x42CF0B1CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A40 *((volatile unsigned int*)(0x42CF0B20UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A41 *((volatile unsigned int*)(0x42CF0B24UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A42 *((volatile unsigned int*)(0x42CF0B28UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A43 *((volatile unsigned int*)(0x42CF0B2CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A44 *((volatile unsigned int*)(0x42CF0B30UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A45 *((volatile unsigned int*)(0x42CF0B34UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A46 *((volatile unsigned int*)(0x42CF0B38UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A47 *((volatile unsigned int*)(0x42CF0B3CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC0 *((volatile unsigned int*)(0x42CF0B60UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC1 *((volatile unsigned int*)(0x42CF0B64UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC2 *((volatile unsigned int*)(0x42CF0B68UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC3 *((volatile unsigned int*)(0x42CF0B6CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC4 *((volatile unsigned int*)(0x42CF0B70UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC5 *((volatile unsigned int*)(0x42CF0B74UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_SA *((volatile unsigned int*)(0x42CF0B78UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_AE *((volatile unsigned int*)(0x42CF0B7CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A0 *((volatile unsigned int*)(0x42CF0B80UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A1 *((volatile unsigned int*)(0x42CF0B84UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A2 *((volatile unsigned int*)(0x42CF0B88UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A3 *((volatile unsigned int*)(0x42CF0B8CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A4 *((volatile unsigned int*)(0x42CF0B90UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A5 *((volatile unsigned int*)(0x42CF0B94UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A6 *((volatile unsigned int*)(0x42CF0B98UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A7 *((volatile unsigned int*)(0x42CF0B9CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A8 *((volatile unsigned int*)(0x42CF0BA0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A9 *((volatile unsigned int*)(0x42CF0BA4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A10 *((volatile unsigned int*)(0x42CF0BA8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A11 *((volatile unsigned int*)(0x42CF0BACUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A12 *((volatile unsigned int*)(0x42CF0BB0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A13 *((volatile unsigned int*)(0x42CF0BB4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A14 *((volatile unsigned int*)(0x42CF0BB8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A15 *((volatile unsigned int*)(0x42CF0BBCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A16 *((volatile unsigned int*)(0x42CF0BC0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A17 *((volatile unsigned int*)(0x42CF0BC4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A18 *((volatile unsigned int*)(0x42CF0BC8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A19 *((volatile unsigned int*)(0x42CF0BCCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A20 *((volatile unsigned int*)(0x42CF0BD0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A21 *((volatile unsigned int*)(0x42CF0BD4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A22 *((volatile unsigned int*)(0x42CF0BD8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A23 *((volatile unsigned int*)(0x42CF0BDCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A24 *((volatile unsigned int*)(0x42CF0BE0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A25 *((volatile unsigned int*)(0x42CF0BE4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A26 *((volatile unsigned int*)(0x42CF0BE8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A27 *((volatile unsigned int*)(0x42CF0BECUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A28 *((volatile unsigned int*)(0x42CF0BF0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A29 *((volatile unsigned int*)(0x42CF0BF4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A30 *((volatile unsigned int*)(0x42CF0BF8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A31 *((volatile unsigned int*)(0x42CF0BFCUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A32 *((volatile unsigned int*)(0x42CF0C00UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A33 *((volatile unsigned int*)(0x42CF0C04UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A34 *((volatile unsigned int*)(0x42CF0C08UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A35 *((volatile unsigned int*)(0x42CF0C0CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A36 *((volatile unsigned int*)(0x42CF0C10UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A37 *((volatile unsigned int*)(0x42CF0C14UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A38 *((volatile unsigned int*)(0x42CF0C18UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A39 *((volatile unsigned int*)(0x42CF0C1CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A40 *((volatile unsigned int*)(0x42CF0C20UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A41 *((volatile unsigned int*)(0x42CF0C24UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A42 *((volatile unsigned int*)(0x42CF0C28UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A43 *((volatile unsigned int*)(0x42CF0C2CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A44 *((volatile unsigned int*)(0x42CF0C30UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A45 *((volatile unsigned int*)(0x42CF0C34UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A46 *((volatile unsigned int*)(0x42CF0C38UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A47 *((volatile unsigned int*)(0x42CF0C3CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC0 *((volatile unsigned int*)(0x42CF0C60UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC1 *((volatile unsigned int*)(0x42CF0C64UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC2 *((volatile unsigned int*)(0x42CF0C68UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC3 *((volatile unsigned int*)(0x42CF0C6CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC4 *((volatile unsigned int*)(0x42CF0C70UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC5 *((volatile unsigned int*)(0x42CF0C74UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_SA *((volatile unsigned int*)(0x42CF0C78UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_AE *((volatile unsigned int*)(0x42CF0C7CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A0 *((volatile unsigned int*)(0x42CF0C80UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A1 *((volatile unsigned int*)(0x42CF0C84UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A2 *((volatile unsigned int*)(0x42CF0C88UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A3 *((volatile unsigned int*)(0x42CF0C8CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A4 *((volatile unsigned int*)(0x42CF0C90UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A5 *((volatile unsigned int*)(0x42CF0C94UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A6 *((volatile unsigned int*)(0x42CF0C98UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A7 *((volatile unsigned int*)(0x42CF0C9CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A8 *((volatile unsigned int*)(0x42CF0CA0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A9 *((volatile unsigned int*)(0x42CF0CA4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A10 *((volatile unsigned int*)(0x42CF0CA8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A11 *((volatile unsigned int*)(0x42CF0CACUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A12 *((volatile unsigned int*)(0x42CF0CB0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A13 *((volatile unsigned int*)(0x42CF0CB4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A14 *((volatile unsigned int*)(0x42CF0CB8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A15 *((volatile unsigned int*)(0x42CF0CBCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A16 *((volatile unsigned int*)(0x42CF0CC0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A17 *((volatile unsigned int*)(0x42CF0CC4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A18 *((volatile unsigned int*)(0x42CF0CC8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A19 *((volatile unsigned int*)(0x42CF0CCCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A20 *((volatile unsigned int*)(0x42CF0CD0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A21 *((volatile unsigned int*)(0x42CF0CD4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A22 *((volatile unsigned int*)(0x42CF0CD8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A23 *((volatile unsigned int*)(0x42CF0CDCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A24 *((volatile unsigned int*)(0x42CF0CE0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A25 *((volatile unsigned int*)(0x42CF0CE4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A26 *((volatile unsigned int*)(0x42CF0CE8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A27 *((volatile unsigned int*)(0x42CF0CECUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A28 *((volatile unsigned int*)(0x42CF0CF0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A29 *((volatile unsigned int*)(0x42CF0CF4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A30 *((volatile unsigned int*)(0x42CF0CF8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A31 *((volatile unsigned int*)(0x42CF0CFCUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A32 *((volatile unsigned int*)(0x42CF0D00UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A33 *((volatile unsigned int*)(0x42CF0D04UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A34 *((volatile unsigned int*)(0x42CF0D08UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A35 *((volatile unsigned int*)(0x42CF0D0CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A36 *((volatile unsigned int*)(0x42CF0D10UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A37 *((volatile unsigned int*)(0x42CF0D14UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A38 *((volatile unsigned int*)(0x42CF0D18UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A39 *((volatile unsigned int*)(0x42CF0D1CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A40 *((volatile unsigned int*)(0x42CF0D20UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A41 *((volatile unsigned int*)(0x42CF0D24UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A42 *((volatile unsigned int*)(0x42CF0D28UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A43 *((volatile unsigned int*)(0x42CF0D2CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A44 *((volatile unsigned int*)(0x42CF0D30UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A45 *((volatile unsigned int*)(0x42CF0D34UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A46 *((volatile unsigned int*)(0x42CF0D38UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A47 *((volatile unsigned int*)(0x42CF0D3CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC0 *((volatile unsigned int*)(0x42CF0D60UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC1 *((volatile unsigned int*)(0x42CF0D64UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC2 *((volatile unsigned int*)(0x42CF0D68UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC3 *((volatile unsigned int*)(0x42CF0D6CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC4 *((volatile unsigned int*)(0x42CF0D70UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC5 *((volatile unsigned int*)(0x42CF0D74UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_SA *((volatile unsigned int*)(0x42CF0D78UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_AE *((volatile unsigned int*)(0x42CF0D7CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A0 *((volatile unsigned int*)(0x42CF0D80UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A1 *((volatile unsigned int*)(0x42CF0D84UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A2 *((volatile unsigned int*)(0x42CF0D88UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A3 *((volatile unsigned int*)(0x42CF0D8CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A4 *((volatile unsigned int*)(0x42CF0D90UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A5 *((volatile unsigned int*)(0x42CF0D94UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A6 *((volatile unsigned int*)(0x42CF0D98UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A7 *((volatile unsigned int*)(0x42CF0D9CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A8 *((volatile unsigned int*)(0x42CF0DA0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A9 *((volatile unsigned int*)(0x42CF0DA4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A10 *((volatile unsigned int*)(0x42CF0DA8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A11 *((volatile unsigned int*)(0x42CF0DACUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A12 *((volatile unsigned int*)(0x42CF0DB0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A13 *((volatile unsigned int*)(0x42CF0DB4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A14 *((volatile unsigned int*)(0x42CF0DB8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A15 *((volatile unsigned int*)(0x42CF0DBCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A16 *((volatile unsigned int*)(0x42CF0DC0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A17 *((volatile unsigned int*)(0x42CF0DC4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A18 *((volatile unsigned int*)(0x42CF0DC8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A19 *((volatile unsigned int*)(0x42CF0DCCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A20 *((volatile unsigned int*)(0x42CF0DD0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A21 *((volatile unsigned int*)(0x42CF0DD4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A22 *((volatile unsigned int*)(0x42CF0DD8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A23 *((volatile unsigned int*)(0x42CF0DDCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A24 *((volatile unsigned int*)(0x42CF0DE0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A25 *((volatile unsigned int*)(0x42CF0DE4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A26 *((volatile unsigned int*)(0x42CF0DE8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A27 *((volatile unsigned int*)(0x42CF0DECUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A28 *((volatile unsigned int*)(0x42CF0DF0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A29 *((volatile unsigned int*)(0x42CF0DF4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A30 *((volatile unsigned int*)(0x42CF0DF8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A31 *((volatile unsigned int*)(0x42CF0DFCUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A32 *((volatile unsigned int*)(0x42CF0E00UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A33 *((volatile unsigned int*)(0x42CF0E04UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A34 *((volatile unsigned int*)(0x42CF0E08UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A35 *((volatile unsigned int*)(0x42CF0E0CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A36 *((volatile unsigned int*)(0x42CF0E10UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A37 *((volatile unsigned int*)(0x42CF0E14UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A38 *((volatile unsigned int*)(0x42CF0E18UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A39 *((volatile unsigned int*)(0x42CF0E1CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A40 *((volatile unsigned int*)(0x42CF0E20UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A41 *((volatile unsigned int*)(0x42CF0E24UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A42 *((volatile unsigned int*)(0x42CF0E28UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A43 *((volatile unsigned int*)(0x42CF0E2CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A44 *((volatile unsigned int*)(0x42CF0E30UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A45 *((volatile unsigned int*)(0x42CF0E34UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A46 *((volatile unsigned int*)(0x42CF0E38UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A47 *((volatile unsigned int*)(0x42CF0E3CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC0 *((volatile unsigned int*)(0x42CF0E60UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC1 *((volatile unsigned int*)(0x42CF0E64UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC2 *((volatile unsigned int*)(0x42CF0E68UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC3 *((volatile unsigned int*)(0x42CF0E6CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC4 *((volatile unsigned int*)(0x42CF0E70UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC5 *((volatile unsigned int*)(0x42CF0E74UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_SA *((volatile unsigned int*)(0x42CF0E78UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_AE *((volatile unsigned int*)(0x42CF0E7CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A0 *((volatile unsigned int*)(0x42CF0E80UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A1 *((volatile unsigned int*)(0x42CF0E84UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A2 *((volatile unsigned int*)(0x42CF0E88UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A3 *((volatile unsigned int*)(0x42CF0E8CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A4 *((volatile unsigned int*)(0x42CF0E90UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A5 *((volatile unsigned int*)(0x42CF0E94UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A6 *((volatile unsigned int*)(0x42CF0E98UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A7 *((volatile unsigned int*)(0x42CF0E9CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A8 *((volatile unsigned int*)(0x42CF0EA0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A9 *((volatile unsigned int*)(0x42CF0EA4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A10 *((volatile unsigned int*)(0x42CF0EA8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A11 *((volatile unsigned int*)(0x42CF0EACUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A12 *((volatile unsigned int*)(0x42CF0EB0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A13 *((volatile unsigned int*)(0x42CF0EB4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A14 *((volatile unsigned int*)(0x42CF0EB8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A15 *((volatile unsigned int*)(0x42CF0EBCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A16 *((volatile unsigned int*)(0x42CF0EC0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A17 *((volatile unsigned int*)(0x42CF0EC4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A18 *((volatile unsigned int*)(0x42CF0EC8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A19 *((volatile unsigned int*)(0x42CF0ECCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A20 *((volatile unsigned int*)(0x42CF0ED0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A21 *((volatile unsigned int*)(0x42CF0ED4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A22 *((volatile unsigned int*)(0x42CF0ED8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A23 *((volatile unsigned int*)(0x42CF0EDCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A24 *((volatile unsigned int*)(0x42CF0EE0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A25 *((volatile unsigned int*)(0x42CF0EE4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A26 *((volatile unsigned int*)(0x42CF0EE8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A27 *((volatile unsigned int*)(0x42CF0EECUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A28 *((volatile unsigned int*)(0x42CF0EF0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A29 *((volatile unsigned int*)(0x42CF0EF4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A30 *((volatile unsigned int*)(0x42CF0EF8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A31 *((volatile unsigned int*)(0x42CF0EFCUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A32 *((volatile unsigned int*)(0x42CF0F00UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A33 *((volatile unsigned int*)(0x42CF0F04UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A34 *((volatile unsigned int*)(0x42CF0F08UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A35 *((volatile unsigned int*)(0x42CF0F0CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A36 *((volatile unsigned int*)(0x42CF0F10UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A37 *((volatile unsigned int*)(0x42CF0F14UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A38 *((volatile unsigned int*)(0x42CF0F18UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A39 *((volatile unsigned int*)(0x42CF0F1CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A40 *((volatile unsigned int*)(0x42CF0F20UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A41 *((volatile unsigned int*)(0x42CF0F24UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A42 *((volatile unsigned int*)(0x42CF0F28UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A43 *((volatile unsigned int*)(0x42CF0F2CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A44 *((volatile unsigned int*)(0x42CF0F30UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A45 *((volatile unsigned int*)(0x42CF0F34UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A46 *((volatile unsigned int*)(0x42CF0F38UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A47 *((volatile unsigned int*)(0x42CF0F3CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC0 *((volatile unsigned int*)(0x42CF0F60UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC1 *((volatile unsigned int*)(0x42CF0F64UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC2 *((volatile unsigned int*)(0x42CF0F68UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC3 *((volatile unsigned int*)(0x42CF0F6CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC4 *((volatile unsigned int*)(0x42CF0F70UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC5 *((volatile unsigned int*)(0x42CF0F74UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_SA *((volatile unsigned int*)(0x42CF0F78UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_AE *((volatile unsigned int*)(0x42CF0F7CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A0 *((volatile unsigned int*)(0x42CF0F80UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A1 *((volatile unsigned int*)(0x42CF0F84UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A2 *((volatile unsigned int*)(0x42CF0F88UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A3 *((volatile unsigned int*)(0x42CF0F8CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A4 *((volatile unsigned int*)(0x42CF0F90UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A5 *((volatile unsigned int*)(0x42CF0F94UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A6 *((volatile unsigned int*)(0x42CF0F98UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A7 *((volatile unsigned int*)(0x42CF0F9CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A8 *((volatile unsigned int*)(0x42CF0FA0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A9 *((volatile unsigned int*)(0x42CF0FA4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A10 *((volatile unsigned int*)(0x42CF0FA8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A11 *((volatile unsigned int*)(0x42CF0FACUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A12 *((volatile unsigned int*)(0x42CF0FB0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A13 *((volatile unsigned int*)(0x42CF0FB4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A14 *((volatile unsigned int*)(0x42CF0FB8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A15 *((volatile unsigned int*)(0x42CF0FBCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A16 *((volatile unsigned int*)(0x42CF0FC0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A17 *((volatile unsigned int*)(0x42CF0FC4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A18 *((volatile unsigned int*)(0x42CF0FC8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A19 *((volatile unsigned int*)(0x42CF0FCCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A20 *((volatile unsigned int*)(0x42CF0FD0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A21 *((volatile unsigned int*)(0x42CF0FD4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A22 *((volatile unsigned int*)(0x42CF0FD8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A23 *((volatile unsigned int*)(0x42CF0FDCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A24 *((volatile unsigned int*)(0x42CF0FE0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A25 *((volatile unsigned int*)(0x42CF0FE4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A26 *((volatile unsigned int*)(0x42CF0FE8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A27 *((volatile unsigned int*)(0x42CF0FECUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A28 *((volatile unsigned int*)(0x42CF0FF0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A29 *((volatile unsigned int*)(0x42CF0FF4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A30 *((volatile unsigned int*)(0x42CF0FF8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A31 *((volatile unsigned int*)(0x42CF0FFCUL)) -#define bFM3_ETHERNET_MAC1_BMR_SWR *((volatile unsigned int*)(0x42D00000UL)) -#define bFM3_ETHERNET_MAC1_BMR_DA *((volatile unsigned int*)(0x42D00004UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL0 *((volatile unsigned int*)(0x42D00008UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL1 *((volatile unsigned int*)(0x42D0000CUL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL2 *((volatile unsigned int*)(0x42D00010UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL3 *((volatile unsigned int*)(0x42D00014UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL4 *((volatile unsigned int*)(0x42D00018UL)) -#define bFM3_ETHERNET_MAC1_BMR_ATDS *((volatile unsigned int*)(0x42D0001CUL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL0 *((volatile unsigned int*)(0x42D00020UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL1 *((volatile unsigned int*)(0x42D00024UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL2 *((volatile unsigned int*)(0x42D00028UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL3 *((volatile unsigned int*)(0x42D0002CUL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL4 *((volatile unsigned int*)(0x42D00030UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL5 *((volatile unsigned int*)(0x42D00034UL)) -#define bFM3_ETHERNET_MAC1_BMR_PR0 *((volatile unsigned int*)(0x42D00038UL)) -#define bFM3_ETHERNET_MAC1_BMR_PR1 *((volatile unsigned int*)(0x42D0003CUL)) -#define bFM3_ETHERNET_MAC1_BMR_FB *((volatile unsigned int*)(0x42D00040UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL0 *((volatile unsigned int*)(0x42D00044UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL1 *((volatile unsigned int*)(0x42D00048UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL2 *((volatile unsigned int*)(0x42D0004CUL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL3 *((volatile unsigned int*)(0x42D00050UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL4 *((volatile unsigned int*)(0x42D00054UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL5 *((volatile unsigned int*)(0x42D00058UL)) -#define bFM3_ETHERNET_MAC1_BMR_USP *((volatile unsigned int*)(0x42D0005CUL)) -#define bFM3_ETHERNET_MAC1_BMR_8XPBL *((volatile unsigned int*)(0x42D00060UL)) -#define bFM3_ETHERNET_MAC1_BMR_AAL *((volatile unsigned int*)(0x42D00064UL)) -#define bFM3_ETHERNET_MAC1_BMR_MB *((volatile unsigned int*)(0x42D00068UL)) -#define bFM3_ETHERNET_MAC1_BMR_TXPR *((volatile unsigned int*)(0x42D0006CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD0 *((volatile unsigned int*)(0x42D00080UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD1 *((volatile unsigned int*)(0x42D00084UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD2 *((volatile unsigned int*)(0x42D00088UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD3 *((volatile unsigned int*)(0x42D0008CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD4 *((volatile unsigned int*)(0x42D00090UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD5 *((volatile unsigned int*)(0x42D00094UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD6 *((volatile unsigned int*)(0x42D00098UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD7 *((volatile unsigned int*)(0x42D0009CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD8 *((volatile unsigned int*)(0x42D000A0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD9 *((volatile unsigned int*)(0x42D000A4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD10 *((volatile unsigned int*)(0x42D000A8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD11 *((volatile unsigned int*)(0x42D000ACUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD12 *((volatile unsigned int*)(0x42D000B0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD13 *((volatile unsigned int*)(0x42D000B4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD14 *((volatile unsigned int*)(0x42D000B8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD15 *((volatile unsigned int*)(0x42D000BCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD16 *((volatile unsigned int*)(0x42D000C0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD17 *((volatile unsigned int*)(0x42D000C4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD18 *((volatile unsigned int*)(0x42D000C8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD19 *((volatile unsigned int*)(0x42D000CCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD20 *((volatile unsigned int*)(0x42D000D0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD21 *((volatile unsigned int*)(0x42D000D4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD22 *((volatile unsigned int*)(0x42D000D8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD23 *((volatile unsigned int*)(0x42D000DCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD24 *((volatile unsigned int*)(0x42D000E0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD25 *((volatile unsigned int*)(0x42D000E4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD26 *((volatile unsigned int*)(0x42D000E8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD27 *((volatile unsigned int*)(0x42D000ECUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD28 *((volatile unsigned int*)(0x42D000F0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD29 *((volatile unsigned int*)(0x42D000F4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD30 *((volatile unsigned int*)(0x42D000F8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD31 *((volatile unsigned int*)(0x42D000FCUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD0 *((volatile unsigned int*)(0x42D00100UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD1 *((volatile unsigned int*)(0x42D00104UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD2 *((volatile unsigned int*)(0x42D00108UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD3 *((volatile unsigned int*)(0x42D0010CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD4 *((volatile unsigned int*)(0x42D00110UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD5 *((volatile unsigned int*)(0x42D00114UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD6 *((volatile unsigned int*)(0x42D00118UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD7 *((volatile unsigned int*)(0x42D0011CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD8 *((volatile unsigned int*)(0x42D00120UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD9 *((volatile unsigned int*)(0x42D00124UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD10 *((volatile unsigned int*)(0x42D00128UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD11 *((volatile unsigned int*)(0x42D0012CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD12 *((volatile unsigned int*)(0x42D00130UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD13 *((volatile unsigned int*)(0x42D00134UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD14 *((volatile unsigned int*)(0x42D00138UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD15 *((volatile unsigned int*)(0x42D0013CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD16 *((volatile unsigned int*)(0x42D00140UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD17 *((volatile unsigned int*)(0x42D00144UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD18 *((volatile unsigned int*)(0x42D00148UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD19 *((volatile unsigned int*)(0x42D0014CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD20 *((volatile unsigned int*)(0x42D00150UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD21 *((volatile unsigned int*)(0x42D00154UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD22 *((volatile unsigned int*)(0x42D00158UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD23 *((volatile unsigned int*)(0x42D0015CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD24 *((volatile unsigned int*)(0x42D00160UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD25 *((volatile unsigned int*)(0x42D00164UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD26 *((volatile unsigned int*)(0x42D00168UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD27 *((volatile unsigned int*)(0x42D0016CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD28 *((volatile unsigned int*)(0x42D00170UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD29 *((volatile unsigned int*)(0x42D00174UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD30 *((volatile unsigned int*)(0x42D00178UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD31 *((volatile unsigned int*)(0x42D0017CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL2 *((volatile unsigned int*)(0x42D00188UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL3 *((volatile unsigned int*)(0x42D0018CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL4 *((volatile unsigned int*)(0x42D00190UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL5 *((volatile unsigned int*)(0x42D00194UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL6 *((volatile unsigned int*)(0x42D00198UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL7 *((volatile unsigned int*)(0x42D0019CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL8 *((volatile unsigned int*)(0x42D001A0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL9 *((volatile unsigned int*)(0x42D001A4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL10 *((volatile unsigned int*)(0x42D001A8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL11 *((volatile unsigned int*)(0x42D001ACUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL12 *((volatile unsigned int*)(0x42D001B0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL13 *((volatile unsigned int*)(0x42D001B4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL14 *((volatile unsigned int*)(0x42D001B8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL15 *((volatile unsigned int*)(0x42D001BCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL16 *((volatile unsigned int*)(0x42D001C0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL17 *((volatile unsigned int*)(0x42D001C4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL18 *((volatile unsigned int*)(0x42D001C8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL19 *((volatile unsigned int*)(0x42D001CCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL20 *((volatile unsigned int*)(0x42D001D0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL21 *((volatile unsigned int*)(0x42D001D4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL22 *((volatile unsigned int*)(0x42D001D8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL23 *((volatile unsigned int*)(0x42D001DCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL24 *((volatile unsigned int*)(0x42D001E0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL25 *((volatile unsigned int*)(0x42D001E4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL26 *((volatile unsigned int*)(0x42D001E8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL27 *((volatile unsigned int*)(0x42D001ECUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL28 *((volatile unsigned int*)(0x42D001F0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL29 *((volatile unsigned int*)(0x42D001F4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL30 *((volatile unsigned int*)(0x42D001F8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL31 *((volatile unsigned int*)(0x42D001FCUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL2 *((volatile unsigned int*)(0x42D00208UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL3 *((volatile unsigned int*)(0x42D0020CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL4 *((volatile unsigned int*)(0x42D00210UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL5 *((volatile unsigned int*)(0x42D00214UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL6 *((volatile unsigned int*)(0x42D00218UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL7 *((volatile unsigned int*)(0x42D0021CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL8 *((volatile unsigned int*)(0x42D00220UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL9 *((volatile unsigned int*)(0x42D00224UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL10 *((volatile unsigned int*)(0x42D00228UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL11 *((volatile unsigned int*)(0x42D0022CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL12 *((volatile unsigned int*)(0x42D00230UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL13 *((volatile unsigned int*)(0x42D00234UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL14 *((volatile unsigned int*)(0x42D00238UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL15 *((volatile unsigned int*)(0x42D0023CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL16 *((volatile unsigned int*)(0x42D00240UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL17 *((volatile unsigned int*)(0x42D00244UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL18 *((volatile unsigned int*)(0x42D00248UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL19 *((volatile unsigned int*)(0x42D0024CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL20 *((volatile unsigned int*)(0x42D00250UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL21 *((volatile unsigned int*)(0x42D00254UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL22 *((volatile unsigned int*)(0x42D00258UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL23 *((volatile unsigned int*)(0x42D0025CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL24 *((volatile unsigned int*)(0x42D00260UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL25 *((volatile unsigned int*)(0x42D00264UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL26 *((volatile unsigned int*)(0x42D00268UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL27 *((volatile unsigned int*)(0x42D0026CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL28 *((volatile unsigned int*)(0x42D00270UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL29 *((volatile unsigned int*)(0x42D00274UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL30 *((volatile unsigned int*)(0x42D00278UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL31 *((volatile unsigned int*)(0x42D0027CUL)) -#define bFM3_ETHERNET_MAC1_SR_TI *((volatile unsigned int*)(0x42D00280UL)) -#define bFM3_ETHERNET_MAC1_SR_TPS *((volatile unsigned int*)(0x42D00284UL)) -#define bFM3_ETHERNET_MAC1_SR_TU *((volatile unsigned int*)(0x42D00288UL)) -#define bFM3_ETHERNET_MAC1_SR_TJT *((volatile unsigned int*)(0x42D0028CUL)) -#define bFM3_ETHERNET_MAC1_SR_OVF *((volatile unsigned int*)(0x42D00290UL)) -#define bFM3_ETHERNET_MAC1_SR_UNF *((volatile unsigned int*)(0x42D00294UL)) -#define bFM3_ETHERNET_MAC1_SR_RI *((volatile unsigned int*)(0x42D00298UL)) -#define bFM3_ETHERNET_MAC1_SR_RU *((volatile unsigned int*)(0x42D0029CUL)) -#define bFM3_ETHERNET_MAC1_SR_RPS *((volatile unsigned int*)(0x42D002A0UL)) -#define bFM3_ETHERNET_MAC1_SR_RWT *((volatile unsigned int*)(0x42D002A4UL)) -#define bFM3_ETHERNET_MAC1_SR_ETI *((volatile unsigned int*)(0x42D002A8UL)) -#define bFM3_ETHERNET_MAC1_SR_FBI *((volatile unsigned int*)(0x42D002B4UL)) -#define bFM3_ETHERNET_MAC1_SR_ERI *((volatile unsigned int*)(0x42D002B8UL)) -#define bFM3_ETHERNET_MAC1_SR_AIS *((volatile unsigned int*)(0x42D002BCUL)) -#define bFM3_ETHERNET_MAC1_SR_NIS *((volatile unsigned int*)(0x42D002C0UL)) -#define bFM3_ETHERNET_MAC1_SR_RS0 *((volatile unsigned int*)(0x42D002C4UL)) -#define bFM3_ETHERNET_MAC1_SR_RS1 *((volatile unsigned int*)(0x42D002C8UL)) -#define bFM3_ETHERNET_MAC1_SR_RS2 *((volatile unsigned int*)(0x42D002CCUL)) -#define bFM3_ETHERNET_MAC1_SR_TS0 *((volatile unsigned int*)(0x42D002D0UL)) -#define bFM3_ETHERNET_MAC1_SR_TS1 *((volatile unsigned int*)(0x42D002D4UL)) -#define bFM3_ETHERNET_MAC1_SR_TS2 *((volatile unsigned int*)(0x42D002D8UL)) -#define bFM3_ETHERNET_MAC1_SR_EB0 *((volatile unsigned int*)(0x42D002DCUL)) -#define bFM3_ETHERNET_MAC1_SR_EB1 *((volatile unsigned int*)(0x42D002E0UL)) -#define bFM3_ETHERNET_MAC1_SR_EB2 *((volatile unsigned int*)(0x42D002E4UL)) -#define bFM3_ETHERNET_MAC1_SR_GLI *((volatile unsigned int*)(0x42D002E8UL)) -#define bFM3_ETHERNET_MAC1_SR_GMI *((volatile unsigned int*)(0x42D002ECUL)) -#define bFM3_ETHERNET_MAC1_SR_GPI *((volatile unsigned int*)(0x42D002F0UL)) -#define bFM3_ETHERNET_MAC1_SR_TTI *((volatile unsigned int*)(0x42D002F4UL)) -#define bFM3_ETHERNET_MAC1_SR_GLPII *((volatile unsigned int*)(0x42D002F8UL)) -#define bFM3_ETHERNET_MAC1_OMR_SR *((volatile unsigned int*)(0x42D00304UL)) -#define bFM3_ETHERNET_MAC1_OMR_OSF *((volatile unsigned int*)(0x42D00308UL)) -#define bFM3_ETHERNET_MAC1_OMR_RTC0 *((volatile unsigned int*)(0x42D0030CUL)) -#define bFM3_ETHERNET_MAC1_OMR_RTC1 *((volatile unsigned int*)(0x42D00310UL)) -#define bFM3_ETHERNET_MAC1_OMR_FUF *((volatile unsigned int*)(0x42D00318UL)) -#define bFM3_ETHERNET_MAC1_OMR_FEF *((volatile unsigned int*)(0x42D0031CUL)) -#define bFM3_ETHERNET_MAC1_OMR_ST *((volatile unsigned int*)(0x42D00334UL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC0 *((volatile unsigned int*)(0x42D00338UL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC1 *((volatile unsigned int*)(0x42D0033CUL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC2 *((volatile unsigned int*)(0x42D00340UL)) -#define bFM3_ETHERNET_MAC1_OMR_FTF *((volatile unsigned int*)(0x42D00350UL)) -#define bFM3_ETHERNET_MAC1_OMR_TSF *((volatile unsigned int*)(0x42D00354UL)) -#define bFM3_ETHERNET_MAC1_OMR_DFF *((volatile unsigned int*)(0x42D00360UL)) -#define bFM3_ETHERNET_MAC1_OMR_RSF *((volatile unsigned int*)(0x42D00364UL)) -#define bFM3_ETHERNET_MAC1_OMR_DT *((volatile unsigned int*)(0x42D00368UL)) -#define bFM3_ETHERNET_MAC1_IER_TIE *((volatile unsigned int*)(0x42D00380UL)) -#define bFM3_ETHERNET_MAC1_IER_TSE *((volatile unsigned int*)(0x42D00384UL)) -#define bFM3_ETHERNET_MAC1_IER_TUE *((volatile unsigned int*)(0x42D00388UL)) -#define bFM3_ETHERNET_MAC1_IER_TJE *((volatile unsigned int*)(0x42D0038CUL)) -#define bFM3_ETHERNET_MAC1_IER_OVE *((volatile unsigned int*)(0x42D00390UL)) -#define bFM3_ETHERNET_MAC1_IER_UNE *((volatile unsigned int*)(0x42D00394UL)) -#define bFM3_ETHERNET_MAC1_IER_RIE *((volatile unsigned int*)(0x42D00398UL)) -#define bFM3_ETHERNET_MAC1_IER_RUE *((volatile unsigned int*)(0x42D0039CUL)) -#define bFM3_ETHERNET_MAC1_IER_RSE *((volatile unsigned int*)(0x42D003A0UL)) -#define bFM3_ETHERNET_MAC1_IER_RWE *((volatile unsigned int*)(0x42D003A4UL)) -#define bFM3_ETHERNET_MAC1_IER_ETE *((volatile unsigned int*)(0x42D003A8UL)) -#define bFM3_ETHERNET_MAC1_IER_FBE *((volatile unsigned int*)(0x42D003B4UL)) -#define bFM3_ETHERNET_MAC1_IER_ERE *((volatile unsigned int*)(0x42D003B8UL)) -#define bFM3_ETHERNET_MAC1_IER_AIE *((volatile unsigned int*)(0x42D003BCUL)) -#define bFM3_ETHERNET_MAC1_IER_NIE *((volatile unsigned int*)(0x42D003C0UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42D00400UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42D00404UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42D00408UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42D0040CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42D00410UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42D00414UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42D00418UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42D0041CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42D00420UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42D00424UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42D00428UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42D0042CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42D00430UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42D00434UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42D00438UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42D0043CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH *((volatile unsigned int*)(0x42D00440UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42D00444UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42D00448UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42D0044CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42D00450UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42D00454UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42D00458UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42D0045CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42D00460UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42D00464UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42D00468UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42D0046CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF *((volatile unsigned int*)(0x42D00470UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0 *((volatile unsigned int*)(0x42D00480UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1 *((volatile unsigned int*)(0x42D00484UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2 *((volatile unsigned int*)(0x42D00488UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3 *((volatile unsigned int*)(0x42D0048CUL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4 *((volatile unsigned int*)(0x42D00490UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5 *((volatile unsigned int*)(0x42D00494UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6 *((volatile unsigned int*)(0x42D00498UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7 *((volatile unsigned int*)(0x42D0049CUL)) -#define bFM3_ETHERNET_MAC1_AHBSR_AHBS *((volatile unsigned int*)(0x42D00580UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42D00900UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42D00904UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42D00908UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42D0090CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42D00910UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42D00914UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42D00918UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42D0091CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42D00920UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42D00924UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42D00928UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42D0092CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42D00930UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42D00934UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42D00938UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42D0093CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42D00940UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42D00944UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42D00948UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42D0094CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42D00950UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42D00954UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42D00958UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42D0095CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42D00960UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42D00964UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42D00968UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42D0096CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42D00970UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42D00974UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42D00978UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42D0097CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42D00980UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42D00984UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42D00988UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42D0098CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42D00990UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42D00994UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42D00998UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42D0099CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42D009A0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42D009A4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42D009A8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42D009ACUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42D009B0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42D009B4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42D009B8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42D009BCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42D009C0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42D009C4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42D009C8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42D009CCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42D009D0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42D009D4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42D009D8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42D009DCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42D009E0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42D009E4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42D009E8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42D009ECUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42D009F0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42D009F4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42D009F8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42D009FCUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42D00A00UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42D00A04UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42D00A08UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42D00A0CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42D00A10UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42D00A14UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42D00A18UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42D00A1CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42D00A20UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42D00A24UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42D00A28UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42D00A2CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42D00A30UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42D00A34UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42D00A38UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42D00A3CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42D00A40UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42D00A44UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42D00A48UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42D00A4CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42D00A50UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42D00A54UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42D00A58UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42D00A5CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42D00A60UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42D00A64UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42D00A68UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42D00A6CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42D00A70UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42D00A74UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42D00A78UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42D00A7CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42D00A80UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42D00A84UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42D00A88UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42D00A8CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42D00A90UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42D00A94UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42D00A98UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42D00A9CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42D00AA0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42D00AA4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42D00AA8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42D00AACUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42D00AB0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42D00AB4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42D00AB8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42D00ABCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42D00AC0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42D00AC4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42D00AC8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42D00ACCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42D00AD0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42D00AD4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42D00AD8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42D00ADCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42D00AE0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42D00AE4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42D00AE8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42D00AECUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42D00AF0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42D00AF4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42D00AF8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42D00AFCUL)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9BF618S_H_ */ - diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h deleted file mode 100644 index b75c77ba6b..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h +++ /dev/null @@ -1,29338 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/* */ -/* Header File for Device MB9B610T */ -/* Version V1.2 */ -/* Date 2012-02-23 */ -/* */ -/************************************************************************/ - -/****************************************************************************** - * History - * Date Ver Description - * 2011-08-04 1.0 Initial - * 2011-10-04 1.1 Added FBFCR register - * Removed the following bits from the bit fields - * - TMD bits of WFSAxx register in MFT - * - MD bits of PPGCx register in PPG - * - FMD bits of TMCR register in BT - * - MD bits of SMR register in MFS - * 2012-02-23 1.2 Added the following bits to the bit fields - * - TMD bits of WFSAxx register in MFT - * - MD bits of PPGCx register in PPG - * - FMD bits of TMCR register in BT - * - MD bits of SMR register in MFS - * - ******************************************************************************/ - -#ifndef _MB9B610T_H_ -#define _MB9B610T_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - - -/****************************************************************************** - * Interrupt Number Definition - ******************************************************************************/ -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Super Visor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detector */ - WFG_IRQn = 3, /* Wave Form Generator */ - EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ - EXINT8_31_IRQn = 5, /* External Interrupt Request ch.8 to ch.31 */ - DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ - MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */ - MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */ - MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */ - MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */ - MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */ - MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */ - MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */ - MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */ - MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */ - MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */ - MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */ - MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */ - MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */ - MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */ - MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */ - MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */ - PPG_IRQn = 23, /* PPG */ - OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ - ADC0_IRQn = 25, /* ADC0 */ - ADC1_IRQn = 26, /* ADC1 */ - ADC2_IRQn = 27, /* ADC2 */ - FRTIM_IRQn = 28, /* Free-run Timer */ - INCAP_IRQn = 29, /* Input Capture */ - OUTCOMP_IRQn = 30, /* Output Compare */ - BTIM0_7_IRQn = 31, /* Base Timer ch.0 to ch.7 */ - ETHER_MAC0_IRQn = 32, /* Ethernet MAC ch.0 */ - ETHER_MAC1_IRQn = 33, /* Ethernet MAC ch.1 */ - USB0F_IRQn = 34, /* USB Function ch.0 */ - USB0F_USB0H_IRQn = 35, /* USB Function ch.0 / USB Host ch.0 */ - USB1F_IRQn = 36, /* USB Function ch.1 */ - USB1F_USB1H_IRQn = 37, /* USB Function ch.1 / USB Host ch.1 */ - DMAC0_IRQn = 38, /* DMAC ch.0 */ - DMAC1_IRQn = 39, /* DMAC ch.1 */ - DMAC2_IRQn = 40, /* DMAC ch.2 */ - DMAC3_IRQn = 41, /* DMAC ch.3 */ - DMAC4_IRQn = 42, /* DMAC ch.4 */ - DMAC5_IRQn = 43, /* DMAC ch.5 */ - DMAC6_IRQn = 44, /* DMAC ch.6 */ - DMAC7_IRQn = 45, /* DMAC ch.7 */ - BTIM8_15_IRQn = 46 /* Base Timer ch.8 to ch.15 */ - /* Reserved = 47 */ -} IRQn_Type; - - -#include -#include "system_mb9bf61x.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * Peripheral register bit fields - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash_IF_MODULE register bit fields */ -typedef struct stc_flash_if_faszr_field -{ - __IO uint32_t ASZ0 : 1; - __IO uint32_t ASZ1 : 1; -} stc_flash_if_faszr_field_t; - -typedef struct stc_flash_if_frwtr_field -{ - __IO uint32_t RWT0 : 1; - __IO uint32_t RWT1 : 1; -} stc_flash_if_frwtr_field_t; - -typedef struct stc_flash_if_fstr_field -{ - __IO uint32_t RDY : 1; - __IO uint32_t HNG : 1; - __IO uint32_t EER : 1; -} stc_flash_if_fstr_field_t; - -typedef struct stc_flash_if_fsyndn_field -{ - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; -} stc_flash_if_fsyndn_field_t; - -typedef struct stc_flash_if_fbfcr_field -{ - __IO uint32_t BE : 1; - __IO uint32_t BS : 1; -} stc_flash_if_fbfcr_field_t; - -typedef struct stc_flash_if_crtrmm_field -{ - __IO uint32_t TRMM0 : 1; - __IO uint32_t TRMM1 : 1; - __IO uint32_t TRMM2 : 1; - __IO uint32_t TRMM3 : 1; - __IO uint32_t TRMM4 : 1; - __IO uint32_t TRMM5 : 1; - __IO uint32_t TRMM6 : 1; - __IO uint32_t TRMM7 : 1; - __IO uint32_t TRMM8 : 1; - __IO uint32_t TRMM9 : 1; -} stc_flash_if_crtrmm_field_t; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock_Reset_MODULE register bit fields */ -typedef struct stc_crg_scm_ctl_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MOSCE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SOSCE : 1; - __IO uint8_t PLLE : 1; - __IO uint8_t RCS0 : 1; - __IO uint8_t RCS1 : 1; - __IO uint8_t RCS2 : 1; -} stc_crg_scm_ctl_field_t; - -typedef struct stc_crg_scm_str_field -{ - uint8_t RESERVED1 : 1; - __IO uint8_t MORDY : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t SORDY : 1; - __IO uint8_t PLRDY : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t RCM2 : 1; -} stc_crg_scm_str_field_t; - -typedef struct stc_crg_rst_str_field -{ - __IO uint16_t PONR : 1; - __IO uint16_t INITX : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SWDT : 1; - __IO uint16_t HWDT : 1; - __IO uint16_t CSVR : 1; - __IO uint16_t FCSR : 1; - __IO uint16_t SRST : 1; -} stc_crg_rst_str_field_t; - -typedef struct stc_crg_bsc_psr_field -{ - __IO uint8_t BSR0 : 1; - __IO uint8_t BSR1 : 1; - __IO uint8_t BSR2 : 1; -} stc_crg_bsc_psr_field_t; - -typedef struct stc_crg_apbc0_psr_field -{ - __IO uint8_t APBC00 : 1; - __IO uint8_t APBC01 : 1; -} stc_crg_apbc0_psr_field_t; - -typedef struct stc_crg_apbc1_psr_field -{ - __IO uint8_t APBC10 : 1; - __IO uint8_t APBC11 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC1RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC1EN : 1; -} stc_crg_apbc1_psr_field_t; - -typedef struct stc_crg_apbc2_psr_field -{ - __IO uint8_t APBC20 : 1; - __IO uint8_t APBC21 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t APBC2RST : 1; - uint8_t RESERVED2 : 2; - __IO uint8_t APBC2EN : 1; -} stc_crg_apbc2_psr_field_t; - -typedef struct stc_crg_swc_psr_field -{ - __IO uint8_t SWDS0 : 1; - __IO uint8_t SWDS1 : 1; - uint8_t RESERVED1 : 5; - __IO uint8_t TESTB : 1; -} stc_crg_swc_psr_field_t; - -typedef struct stc_crg_ttc_psr_field -{ - __IO uint8_t TTC0 : 1; - __IO uint8_t TTC1 : 1; -} stc_crg_ttc_psr_field_t; - -typedef struct stc_crg_csw_tmr_field -{ - __IO uint8_t MOWT0 : 1; - __IO uint8_t MOWT1 : 1; - __IO uint8_t MOWT2 : 1; - __IO uint8_t MOWT3 : 1; - __IO uint8_t SOWT0 : 1; - __IO uint8_t SOWT1 : 1; - __IO uint8_t SOWT2 : 1; -} stc_crg_csw_tmr_field_t; - -typedef struct stc_crg_psw_tmr_field -{ - __IO uint8_t POWT0 : 1; - __IO uint8_t POWT1 : 1; - __IO uint8_t POWT2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t PINC : 1; -} stc_crg_psw_tmr_field_t; - -typedef struct stc_crg_pll_ctl1_field -{ - __IO uint8_t PLLM0 : 1; - __IO uint8_t PLLM1 : 1; - __IO uint8_t PLLM2 : 1; - __IO uint8_t PLLM3 : 1; - __IO uint8_t PLLK0 : 1; - __IO uint8_t PLLK1 : 1; - __IO uint8_t PLLK2 : 1; - __IO uint8_t PLLK3 : 1; -} stc_crg_pll_ctl1_field_t; - -typedef struct stc_crg_pll_ctl2_field -{ - __IO uint8_t PLLN0 : 1; - __IO uint8_t PLLN1 : 1; - __IO uint8_t PLLN2 : 1; - __IO uint8_t PLLN3 : 1; - __IO uint8_t PLLN4 : 1; - __IO uint8_t PLLN5 : 1; -} stc_crg_pll_ctl2_field_t; - -typedef struct stc_crg_csv_ctl_field -{ - __IO uint16_t MCSVE : 1; - __IO uint16_t SCSVE : 1; - uint16_t RESERVED1 : 6; - __IO uint16_t FCSDE : 1; - __IO uint16_t FCSRE : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t FCD0 : 1; - __IO uint16_t FCD1 : 1; - __IO uint16_t FCD2 : 1; -} stc_crg_csv_ctl_field_t; - -typedef struct stc_crg_csv_str_field -{ - __IO uint8_t MCMF : 1; - __IO uint8_t SCMF : 1; -} stc_crg_csv_str_field_t; - -typedef struct stc_crg_dbwdt_ctl_field -{ - uint8_t RESERVED1 : 5; - __IO uint8_t DPSWBE : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t DPHWBE : 1; -} stc_crg_dbwdt_ctl_field_t; - -typedef struct stc_crg_int_enr_field -{ - __IO uint8_t MCSE : 1; - __IO uint8_t SCSE : 1; - __IO uint8_t PCSE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSE : 1; -} stc_crg_int_enr_field_t; - -typedef struct stc_crg_int_str_field -{ - __IO uint8_t MCSI : 1; - __IO uint8_t SCSI : 1; - __IO uint8_t PCSI : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSI : 1; -} stc_crg_int_str_field_t; - -typedef struct stc_crg_int_clr_field -{ - __IO uint8_t MCSC : 1; - __IO uint8_t SCSC : 1; - __IO uint8_t PCSC : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t FCSC : 1; -} stc_crg_int_clr_field_t; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* HWWDT_MODULE register bit fields */ -typedef struct stc_hwwdt_wdg_ctl_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_hwwdt_wdg_ctl_field_t; - -typedef struct stc_hwwdt_wdg_ris_field -{ - __IO uint8_t RIS : 1; -} stc_hwwdt_wdg_ris_field_t; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* SWWDT_MODULE register bit fields */ -typedef struct stc_swwdt_wdogcontrol_field -{ - __IO uint8_t INTEN : 1; - __IO uint8_t RESEN : 1; -} stc_swwdt_wdogcontrol_field_t; - -typedef struct stc_swwdt_wdogris_field -{ - __IO uint8_t RIS : 1; -} stc_swwdt_wdogris_field_t; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* DTIM_MODULE register bit fields */ -typedef struct stc_dtim_timer1control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer1control_field_t; - -typedef struct stc_dtim_timer1ris_field -{ - __IO uint32_t TIMER1RIS : 1; -} stc_dtim_timer1ris_field_t; - -typedef struct stc_dtim_timer1mis_field -{ - __IO uint32_t TIMER1MIS : 1; -} stc_dtim_timer1mis_field_t; - -typedef struct stc_dtim_timer2control_field -{ - __IO uint32_t ONESHOT : 1; - __IO uint32_t TIMERSIZE : 1; - __IO uint32_t TIMERPRE0 : 1; - __IO uint32_t TIMERPRE1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t INTENABLE : 1; - __IO uint32_t TIMERMODE : 1; - __IO uint32_t TIMEREN : 1; -} stc_dtim_timer2control_field_t; - -typedef struct stc_dtim_timer2ris_field -{ - __IO uint32_t TIMER2RIS : 1; -} stc_dtim_timer2ris_field_t; - -typedef struct stc_dtim_timer2mis_field -{ - __IO uint32_t TIMER2MIS : 1; -} stc_dtim_timer2mis_field_t; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* MFT_FRT_MODULE register bit fields */ -typedef struct stc_mft_frt_tcsa0_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa0_field_t; - -typedef struct stc_mft_frt_tcsb0_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb0_field_t; - -typedef struct stc_mft_frt_tcsa1_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa1_field_t; - -typedef struct stc_mft_frt_tcsb1_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb1_field_t; - -typedef struct stc_mft_frt_tcsa2_field -{ - __IO uint16_t CLK0 : 1; - __IO uint16_t CLK1 : 1; - __IO uint16_t CLK2 : 1; - __IO uint16_t CLK3 : 1; - __IO uint16_t SCLR : 1; - __IO uint16_t MODE : 1; - __IO uint16_t STOP : 1; - __IO uint16_t BFE : 1; - __IO uint16_t ICRE : 1; - __IO uint16_t ICLR : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t IRQZE : 1; - __IO uint16_t IRQZF : 1; - __IO uint16_t ECKE : 1; -} stc_mft_frt_tcsa2_field_t; - -typedef struct stc_mft_frt_tcsb2_field -{ - __IO uint16_t AD0E : 1; - __IO uint16_t AD1E : 1; - __IO uint16_t AD2E : 1; -} stc_mft_frt_tcsb2_field_t; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* MFT_OCU_MODULE register bit fields */ -typedef struct stc_mft_ocu_ocsa10_field -{ - __IO uint8_t CST0 : 1; - __IO uint8_t CST1 : 1; - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t IOE0 : 1; - __IO uint8_t IOE1 : 1; - __IO uint8_t IOP0 : 1; - __IO uint8_t IOP1 : 1; -} stc_mft_ocu_ocsa10_field_t; - -typedef struct stc_mft_ocu_ocsb10_field -{ - __IO uint8_t OTD0 : 1; - __IO uint8_t OTD1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; -} stc_mft_ocu_ocsb10_field_t; - -typedef struct stc_mft_ocu_ocsa32_field -{ - __IO uint8_t CST2 : 1; - __IO uint8_t CST3 : 1; - __IO uint8_t BDIS2 : 1; - __IO uint8_t BDIS3 : 1; - __IO uint8_t IOE2 : 1; - __IO uint8_t IOE3 : 1; - __IO uint8_t IOP2 : 1; - __IO uint8_t IOP3 : 1; -} stc_mft_ocu_ocsa32_field_t; - -typedef struct stc_mft_ocu_ocsb32_field -{ - __IO uint8_t OTD2 : 1; - __IO uint8_t OTD3 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS2 : 1; - __IO uint8_t BTS3 : 1; -} stc_mft_ocu_ocsb32_field_t; - -typedef struct stc_mft_ocu_ocsa54_field -{ - __IO uint8_t CST4 : 1; - __IO uint8_t CST5 : 1; - __IO uint8_t BDIS4 : 1; - __IO uint8_t BDIS5 : 1; - __IO uint8_t IOE4 : 1; - __IO uint8_t IOE5 : 1; - __IO uint8_t IOP4 : 1; - __IO uint8_t IOP5 : 1; -} stc_mft_ocu_ocsa54_field_t; - -typedef struct stc_mft_ocu_ocsb54_field -{ - __IO uint8_t OTD4 : 1; - __IO uint8_t OTD5 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CMOD : 1; - __IO uint8_t BTS4 : 1; - __IO uint8_t BTS5 : 1; -} stc_mft_ocu_ocsb54_field_t; - -typedef struct stc_mft_ocu_ocsc_field -{ - __IO uint8_t MOD0 : 1; - __IO uint8_t MOD1 : 1; - __IO uint8_t MOD2 : 1; - __IO uint8_t MOD3 : 1; - __IO uint8_t MOD4 : 1; - __IO uint8_t MOD5 : 1; -} stc_mft_ocu_ocsc_field_t; - -typedef struct stc_mft_ocu_ocfs10_field -{ - __IO uint8_t FSO00 : 1; - __IO uint8_t FSO01 : 1; - __IO uint8_t FSO02 : 1; - __IO uint8_t FSO03 : 1; - __IO uint8_t FSO10 : 1; - __IO uint8_t FSO11 : 1; - __IO uint8_t FSO12 : 1; - __IO uint8_t FSO13 : 1; -} stc_mft_ocu_ocfs10_field_t; - -typedef struct stc_mft_ocu_ocfs32_field -{ - __IO uint8_t FSO20 : 1; - __IO uint8_t FSO21 : 1; - __IO uint8_t FSO22 : 1; - __IO uint8_t FSO23 : 1; - __IO uint8_t FSO30 : 1; - __IO uint8_t FSO31 : 1; - __IO uint8_t FSO32 : 1; - __IO uint8_t FSO33 : 1; -} stc_mft_ocu_ocfs32_field_t; - -typedef struct stc_mft_ocu_ocfs54_field -{ - __IO uint8_t FSO40 : 1; - __IO uint8_t FSO41 : 1; - __IO uint8_t FSO42 : 1; - __IO uint8_t FSO43 : 1; - __IO uint8_t FSO50 : 1; - __IO uint8_t FSO51 : 1; - __IO uint8_t FSO52 : 1; - __IO uint8_t FSO53 : 1; -} stc_mft_ocu_ocfs54_field_t; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* MFT_WFG_MODULE register bit fields */ -typedef struct stc_mft_wfg_wfsa10_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa10_field_t; - -typedef struct stc_mft_wfg_wfsa32_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa32_field_t; - -typedef struct stc_mft_wfg_wfsa54_field -{ - __IO uint16_t DCK0 : 1; - __IO uint16_t DCK1 : 1; - __IO uint16_t DCK2 : 1; - __IO uint16_t TMD : 3; - __IO uint16_t GTEN0 : 1; - __IO uint16_t GTEN1 : 1; - __IO uint16_t PSEL0 : 1; - __IO uint16_t PSEL1 : 1; - __IO uint16_t PGEN0 : 1; - __IO uint16_t PGEN1 : 1; - __IO uint16_t DMOD : 1; -} stc_mft_wfg_wfsa54_field_t; - -typedef struct stc_mft_wfg_wfir_field -{ - __IO uint16_t DTIF : 1; - __IO uint16_t DTIC : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t TMIF10 : 1; - __IO uint16_t TMIC10 : 1; - __IO uint16_t TMIE10 : 1; - __IO uint16_t TMIS10 : 1; - __IO uint16_t TMIF32 : 1; - __IO uint16_t TMIC32 : 1; - __IO uint16_t TMIE32 : 1; - __IO uint16_t TMIS32 : 1; - __IO uint16_t TMIF54 : 1; - __IO uint16_t TMIC54 : 1; - __IO uint16_t TMIE54 : 1; - __IO uint16_t TMIS54 : 1; -} stc_mft_wfg_wfir_field_t; - -typedef struct stc_mft_wfg_nzcl_field -{ - __IO uint16_t DTIE : 1; - __IO uint16_t NWS0 : 1; - __IO uint16_t NWS1 : 1; - __IO uint16_t NWS2 : 1; - __IO uint16_t SDTI : 1; -} stc_mft_wfg_nzcl_field_t; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* MFT_ICU_MODULE register bit fields */ -typedef struct stc_mft_icu_icfs10_field -{ - __IO uint8_t FSI00 : 1; - __IO uint8_t FSI01 : 1; - __IO uint8_t FSI02 : 1; - __IO uint8_t FSI03 : 1; - __IO uint8_t FSI10 : 1; - __IO uint8_t FSI11 : 1; - __IO uint8_t FSI12 : 1; - __IO uint8_t FSI13 : 1; -} stc_mft_icu_icfs10_field_t; - -typedef struct stc_mft_icu_icfs32_field -{ - __IO uint8_t FSI20 : 1; - __IO uint8_t FSI21 : 1; - __IO uint8_t FSI22 : 1; - __IO uint8_t FSI23 : 1; - __IO uint8_t FSI30 : 1; - __IO uint8_t FSI31 : 1; - __IO uint8_t FSI32 : 1; - __IO uint8_t FSI33 : 1; -} stc_mft_icu_icfs32_field_t; - -typedef struct stc_mft_icu_icsa10_field -{ - __IO uint8_t EG00 : 1; - __IO uint8_t EG01 : 1; - __IO uint8_t EG10 : 1; - __IO uint8_t EG11 : 1; - __IO uint8_t ICE0 : 1; - __IO uint8_t ICE1 : 1; - __IO uint8_t ICP0 : 1; - __IO uint8_t ICP1 : 1; -} stc_mft_icu_icsa10_field_t; - -typedef struct stc_mft_icu_icsb10_field -{ - __IO uint8_t IEI0 : 1; - __IO uint8_t IEI1 : 1; -} stc_mft_icu_icsb10_field_t; - -typedef struct stc_mft_icu_icsa32_field -{ - __IO uint8_t EG20 : 1; - __IO uint8_t EG21 : 1; - __IO uint8_t EG30 : 1; - __IO uint8_t EG31 : 1; - __IO uint8_t ICE2 : 1; - __IO uint8_t ICE3 : 1; - __IO uint8_t ICP2 : 1; - __IO uint8_t ICP3 : 1; -} stc_mft_icu_icsa32_field_t; - -typedef struct stc_mft_icu_icsb32_field -{ - __IO uint8_t IEI2 : 1; - __IO uint8_t IEI3 : 1; -} stc_mft_icu_icsb32_field_t; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* MFT_ADCMP_MODULE register bit fields */ -typedef struct stc_mft_adcmp_acsb_field -{ - __IO uint8_t BDIS0 : 1; - __IO uint8_t BDIS1 : 1; - __IO uint8_t BDIS2 : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BTS0 : 1; - __IO uint8_t BTS1 : 1; - __IO uint8_t BTS2 : 1; -} stc_mft_adcmp_acsb_field_t; - -typedef struct stc_mft_adcmp_acsa_field -{ - __IO uint16_t CE00 : 1; - __IO uint16_t CE01 : 1; - __IO uint16_t CE10 : 1; - __IO uint16_t CE11 : 1; - __IO uint16_t CE20 : 1; - __IO uint16_t CE21 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SEL00 : 1; - __IO uint16_t SEL01 : 1; - __IO uint16_t SEL10 : 1; - __IO uint16_t SEL11 : 1; - __IO uint16_t SEL20 : 1; - __IO uint16_t SEL21 : 1; -} stc_mft_adcmp_acsa_field_t; - -typedef struct stc_mft_adcmp_atsa_field -{ - __IO uint16_t AD0S0 : 1; - __IO uint16_t AD0S1 : 1; - __IO uint16_t AD1S0 : 1; - __IO uint16_t AD1S1 : 1; - __IO uint16_t AD2S0 : 1; - __IO uint16_t AD2S1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t AD0P0 : 1; - __IO uint16_t AD0P1 : 1; - __IO uint16_t AD1P0 : 1; - __IO uint16_t AD1P1 : 1; - __IO uint16_t AD2P0 : 1; - __IO uint16_t AD2P1 : 1; -} stc_mft_adcmp_atsa_field_t; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* MFT_PPG_MODULE register bit fields */ -typedef struct stc_mft_ppg_ttcr0_field -{ - __IO uint8_t STR0 : 1; - __IO uint8_t MONI0 : 1; - __IO uint8_t CS00 : 1; - __IO uint8_t CS01 : 1; - __IO uint8_t TRG0O : 1; - __IO uint8_t TRG2O : 1; - __IO uint8_t TRG4O : 1; - __IO uint8_t TRG6O : 1; -} stc_mft_ppg_ttcr0_field_t; - -typedef struct stc_mft_ppg_ttcr1_field -{ - __IO uint8_t STR1 : 1; - __IO uint8_t MONI1 : 1; - __IO uint8_t CS10 : 1; - __IO uint8_t CS11 : 1; - __IO uint8_t TRG1O : 1; - __IO uint8_t TRG3O : 1; - __IO uint8_t TRG5O : 1; - __IO uint8_t TRG7O : 1; -} stc_mft_ppg_ttcr1_field_t; - -typedef struct stc_mft_ppg_ttcr2_field -{ - __IO uint8_t STR2 : 1; - __IO uint8_t MONI2 : 1; - __IO uint8_t CS20 : 1; - __IO uint8_t CS21 : 1; - __IO uint8_t TRG16O : 1; - __IO uint8_t TRG18O : 1; - __IO uint8_t TRG20O : 1; - __IO uint8_t TRG22O : 1; -} stc_mft_ppg_ttcr2_field_t; - -typedef struct stc_mft_ppg_trg_field -{ - __IO uint16_t PEN00 : 1; - __IO uint16_t PEN01 : 1; - __IO uint16_t PEN02 : 1; - __IO uint16_t PEN03 : 1; - __IO uint16_t PEN04 : 1; - __IO uint16_t PEN05 : 1; - __IO uint16_t PEN06 : 1; - __IO uint16_t PEN07 : 1; - __IO uint16_t PEN08 : 1; - __IO uint16_t PEN09 : 1; - __IO uint16_t PEN10 : 1; - __IO uint16_t PEN11 : 1; - __IO uint16_t PEN12 : 1; - __IO uint16_t PEN13 : 1; - __IO uint16_t PEN14 : 1; - __IO uint16_t PEN15 : 1; -} stc_mft_ppg_trg_field_t; - -typedef struct stc_mft_ppg_trg1_field -{ - __IO uint16_t PEN16 : 1; - __IO uint16_t PEN17 : 1; - __IO uint16_t PEN18 : 1; - __IO uint16_t PEN19 : 1; - __IO uint16_t PEN20 : 1; - __IO uint16_t PEN21 : 1; - __IO uint16_t PEN22 : 1; - __IO uint16_t PEN23 : 1; -} stc_mft_ppg_trg1_field_t; - -typedef struct stc_mft_ppg_revc_field -{ - __IO uint16_t REV00 : 1; - __IO uint16_t REV01 : 1; - __IO uint16_t REV02 : 1; - __IO uint16_t REV03 : 1; - __IO uint16_t REV04 : 1; - __IO uint16_t REV05 : 1; - __IO uint16_t REV06 : 1; - __IO uint16_t REV07 : 1; - __IO uint16_t REV08 : 1; - __IO uint16_t REV09 : 1; - __IO uint16_t REV10 : 1; - __IO uint16_t REV11 : 1; - __IO uint16_t REV12 : 1; - __IO uint16_t REV13 : 1; - __IO uint16_t REV14 : 1; - __IO uint16_t REV15 : 1; -} stc_mft_ppg_revc_field_t; - -typedef struct stc_mft_ppg_revc1_field -{ - __IO uint16_t REV16 : 1; - __IO uint16_t REV17 : 1; - __IO uint16_t REV18 : 1; - __IO uint16_t REV19 : 1; - __IO uint16_t REV20 : 1; - __IO uint16_t REV21 : 1; - __IO uint16_t REV22 : 1; - __IO uint16_t REV23 : 1; -} stc_mft_ppg_revc1_field_t; - -typedef struct stc_mft_ppg_ppgc1_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc1_field_t; - -typedef struct stc_mft_ppg_ppgc0_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc0_field_t; - -typedef struct stc_mft_ppg_ppgc3_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc3_field_t; - -typedef struct stc_mft_ppg_ppgc2_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc2_field_t; - -typedef struct stc_mft_ppg_gatec0_field -{ - __IO uint8_t EDGE0 : 1; - __IO uint8_t STRG0 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE2 : 1; - __IO uint8_t STRG2 : 1; -} stc_mft_ppg_gatec0_field_t; - -typedef struct stc_mft_ppg_ppgc5_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc5_field_t; - -typedef struct stc_mft_ppg_ppgc4_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc4_field_t; - -typedef struct stc_mft_ppg_ppgc7_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc7_field_t; - -typedef struct stc_mft_ppg_ppgc6_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc6_field_t; - -typedef struct stc_mft_ppg_gatec4_field -{ - __IO uint8_t EDGE4 : 1; - __IO uint8_t STRG4 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE6 : 1; - __IO uint8_t STRG6 : 1; -} stc_mft_ppg_gatec4_field_t; - -typedef struct stc_mft_ppg_ppgc9_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc9_field_t; - -typedef struct stc_mft_ppg_ppgc8_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc8_field_t; - -typedef struct stc_mft_ppg_ppgc11_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc11_field_t; - -typedef struct stc_mft_ppg_ppgc10_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc10_field_t; - -typedef struct stc_mft_ppg_gatec8_field -{ - __IO uint8_t EDGE8 : 1; - __IO uint8_t STRG8 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE10 : 1; - __IO uint8_t STRG10 : 1; -} stc_mft_ppg_gatec8_field_t; - -typedef struct stc_mft_ppg_ppgc13_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc13_field_t; - -typedef struct stc_mft_ppg_ppgc12_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc12_field_t; - -typedef struct stc_mft_ppg_ppgc15_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc15_field_t; - -typedef struct stc_mft_ppg_ppgc14_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc14_field_t; - -typedef struct stc_mft_ppg_gatec12_field -{ - __IO uint8_t EDGE12 : 1; - __IO uint8_t STRG12 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE14 : 1; - __IO uint8_t STRG14 : 1; -} stc_mft_ppg_gatec12_field_t; - -typedef struct stc_mft_ppg_ppgc17_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc17_field_t; - -typedef struct stc_mft_ppg_ppgc16_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc16_field_t; - -typedef struct stc_mft_ppg_ppgc19_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc19_field_t; - -typedef struct stc_mft_ppg_ppgc18_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc18_field_t; - -typedef struct stc_mft_ppg_gatec16_field -{ - __IO uint8_t EDGE16 : 1; - __IO uint8_t STRG16 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE18 : 1; - __IO uint8_t STRG18 : 1; -} stc_mft_ppg_gatec16_field_t; - -typedef struct stc_mft_ppg_ppgc21_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc21_field_t; - -typedef struct stc_mft_ppg_ppgc20_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc20_field_t; - -typedef struct stc_mft_ppg_ppgc23_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc23_field_t; - -typedef struct stc_mft_ppg_ppgc22_field -{ - __IO uint8_t TTRG : 1; - __IO uint8_t MD : 2; - __IO uint8_t PCS0 : 1; - __IO uint8_t PCS1 : 1; - __IO uint8_t INTM : 1; - __IO uint8_t PUF : 1; - __IO uint8_t PIE : 1; -} stc_mft_ppg_ppgc22_field_t; - -typedef struct stc_mft_ppg_gatec20_field -{ - __IO uint8_t EDGE20 : 1; - __IO uint8_t STRG20 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t EDGE22 : 1; - __IO uint8_t STRG22 : 1; -} stc_mft_ppg_gatec20_field_t; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* BT_PPG_MODULE register bit fields */ -typedef struct stc_bt_ppg_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD : 3; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_ppg_tmcr_field_t; - -typedef struct stc_bt_ppg_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_ppg_stc_field_t; - -typedef struct stc_bt_ppg_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_ppg_tmcr2_field_t; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* BT_PWM_MODULE register bit fields */ -typedef struct stc_bt_pwm_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD : 3; - uint16_t RESERVED1 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t PMSK : 1; - __IO uint16_t RTGEN : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwm_tmcr_field_t; - -typedef struct stc_bt_pwm_stc_field -{ - __IO uint8_t UDIR : 1; - __IO uint8_t DTIR : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t UDIE : 1; - __IO uint8_t DTIE : 1; - __IO uint8_t TGIE : 1; -} stc_bt_pwm_stc_field_t; - -typedef struct stc_bt_pwm_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwm_tmcr2_field_t; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* BT_RT_MODULE register bit fields */ -typedef struct stc_bt_rt_tmcr_field -{ - __IO uint16_t STRG : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - __IO uint16_t OSEL : 1; - __IO uint16_t FMD : 3; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_rt_tmcr_field_t; - -typedef struct stc_bt_rt_stc_field -{ - __IO uint8_t UDIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TGIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t UDIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t TGIE : 1; -} stc_bt_rt_stc_field_t; - -typedef struct stc_bt_rt_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_rt_tmcr2_field_t; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* BT_PWC_MODULE register bit fields */ -typedef struct stc_bt_pwc_tmcr_field -{ - uint16_t RESERVED1 : 1; - __IO uint16_t CTEN : 1; - __IO uint16_t MDSE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FMD : 3; - __IO uint16_t T32 : 1; - __IO uint16_t EGS0 : 1; - __IO uint16_t EGS1 : 1; - __IO uint16_t EGS2 : 1; - uint16_t RESERVED3 : 1; - __IO uint16_t CKS0 : 1; - __IO uint16_t CKS1 : 1; - __IO uint16_t CKS2 : 1; -} stc_bt_pwc_tmcr_field_t; - -typedef struct stc_bt_pwc_stc_field -{ - __IO uint8_t OVIR : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t EDIR : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t OVIE : 1; - uint8_t RESERVED3 : 1; - __IO uint8_t EDIE : 1; - __IO uint8_t ERR : 1; -} stc_bt_pwc_stc_field_t; - -typedef struct stc_bt_pwc_tmcr2_field -{ - __IO uint8_t CKS3 : 1; -} stc_bt_pwc_tmcr2_field_t; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* BTIOSEL03_MODULE register bit fields */ -typedef struct stc_btiosel03_btsel0123_field -{ - __IO uint8_t SEL01_0 : 1; - __IO uint8_t SEL01_1 : 1; - __IO uint8_t SEL01_2 : 1; - __IO uint8_t SEL01_3 : 1; - __IO uint8_t SEL23_0 : 1; - __IO uint8_t SEL23_1 : 1; - __IO uint8_t SEL23_2 : 1; - __IO uint8_t SEL23_3 : 1; -} stc_btiosel03_btsel0123_field_t; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* BTIOSEL47_MODULE register bit fields */ -typedef struct stc_btiosel47_btsel4567_field -{ - __IO uint8_t SEL45_0 : 1; - __IO uint8_t SEL45_1 : 1; - __IO uint8_t SEL45_2 : 1; - __IO uint8_t SEL45_3 : 1; - __IO uint8_t SEL67_0 : 1; - __IO uint8_t SEL67_1 : 1; - __IO uint8_t SEL67_2 : 1; - __IO uint8_t SEL67_3 : 1; -} stc_btiosel47_btsel4567_field_t; - -/****************************************************************************** - * BTIOSEL811_MODULE - ******************************************************************************/ -/* BTIOSEL811_MODULE register bit fields */ -typedef struct stc_btiosel8b_btsel89ab_field -{ - __IO uint8_t SEL89_0 : 1; - __IO uint8_t SEL89_1 : 1; - __IO uint8_t SEL89_2 : 1; - __IO uint8_t SEL89_3 : 1; - __IO uint8_t SELAB_0 : 1; - __IO uint8_t SELAB_1 : 1; - __IO uint8_t SELAB_2 : 1; - __IO uint8_t SELAB_3 : 1; -} stc_btiosel8b_btsel89ab_field_t; - -/****************************************************************************** - * BTIOSEL1215_MODULE - ******************************************************************************/ -/* BTIOSEL1215_MODULE register bit fields */ -typedef struct stc_btioselcf_btselcdef_field -{ - __IO uint8_t SELCD_0 : 1; - __IO uint8_t SELCD_1 : 1; - __IO uint8_t SELCD_2 : 1; - __IO uint8_t SELCD_3 : 1; - __IO uint8_t SELEF_0 : 1; - __IO uint8_t SELEF_1 : 1; - __IO uint8_t SELEF_2 : 1; - __IO uint8_t SELEF_3 : 1; -} stc_btioselcf_btselcdef_field_t; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* SBSSR_MODULE register bit fields */ -typedef struct stc_sbssr_btsssr_field -{ - __IO uint16_t SSR0 : 1; - __IO uint16_t SSR1 : 1; - __IO uint16_t SSR2 : 1; - __IO uint16_t SSR3 : 1; - __IO uint16_t SSR4 : 1; - __IO uint16_t SSR5 : 1; - __IO uint16_t SSR6 : 1; - __IO uint16_t SSR7 : 1; - __IO uint16_t SSR8 : 1; - __IO uint16_t SSR9 : 1; - __IO uint16_t SSR10 : 1; - __IO uint16_t SSR11 : 1; - __IO uint16_t SSR12 : 1; - __IO uint16_t SSR13 : 1; - __IO uint16_t SSR14 : 1; - __IO uint16_t SSR15 : 1; -} stc_sbssr_btsssr_field_t; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* QPRC_MODULE register bit fields */ -typedef struct stc_qprc_qicr_field -{ - __IO uint16_t QPCMIE : 1; - __IO uint16_t QPCMF : 1; - __IO uint16_t QPRCMIE : 1; - __IO uint16_t QPRCMF : 1; - __IO uint16_t OUZIE : 1; - __IO uint16_t UFDF : 1; - __IO uint16_t OFDF : 1; - __IO uint16_t ZIIF : 1; - __IO uint16_t CDCIE : 1; - __IO uint16_t CDCF : 1; - __IO uint16_t DIRPC : 1; - __IO uint16_t DIROU : 1; - __IO uint16_t QPCNRCMIE : 1; - __IO uint16_t QPCNRCMF : 1; -} stc_qprc_qicr_field_t; - -typedef struct stc_qprc_qicrl_field -{ - __IO uint8_t QPCMIE : 1; - __IO uint8_t QPCMF : 1; - __IO uint8_t QPRCMIE : 1; - __IO uint8_t QPRCMF : 1; - __IO uint8_t OUZIE : 1; - __IO uint8_t UFDF : 1; - __IO uint8_t OFDF : 1; - __IO uint8_t ZIIF : 1; -} stc_qprc_qicrl_field_t; - -typedef struct stc_qprc_qicrh_field -{ - __IO uint8_t CDCIE : 1; - __IO uint8_t CDCF : 1; - __IO uint8_t DIRPC : 1; - __IO uint8_t DIROU : 1; - __IO uint8_t QPCNRCMIE : 1; - __IO uint8_t QPCNRCMF : 1; -} stc_qprc_qicrh_field_t; - -typedef struct stc_qprc_qcr_field -{ - __IO uint16_t PCM0 : 1; - __IO uint16_t PCM1 : 1; - __IO uint16_t RCM0 : 1; - __IO uint16_t RCM1 : 1; - __IO uint16_t PSTP : 1; - __IO uint16_t CGSC : 1; - __IO uint16_t RSEL : 1; - __IO uint16_t SWAP : 1; - __IO uint16_t PCRM0 : 1; - __IO uint16_t PCRM1 : 1; - __IO uint16_t AES0 : 1; - __IO uint16_t AES1 : 1; - __IO uint16_t BES0 : 1; - __IO uint16_t BES1 : 1; - __IO uint16_t CGE0 : 1; - __IO uint16_t CGE1 : 1; -} stc_qprc_qcr_field_t; - -typedef struct stc_qprc_qcrl_field -{ - __IO uint8_t PCM0 : 1; - __IO uint8_t PCM1 : 1; - __IO uint8_t RCM0 : 1; - __IO uint8_t RCM1 : 1; - __IO uint8_t PSTP : 1; - __IO uint8_t CGSC : 1; - __IO uint8_t RSEL : 1; - __IO uint8_t SWAP : 1; -} stc_qprc_qcrl_field_t; - -typedef struct stc_qprc_qcrh_field -{ - __IO uint8_t PCRM0 : 1; - __IO uint8_t PCRM1 : 1; - __IO uint8_t AES0 : 1; - __IO uint8_t AES1 : 1; - __IO uint8_t BES0 : 1; - __IO uint8_t BES1 : 1; - __IO uint8_t CGE0 : 1; - __IO uint8_t CGE1 : 1; -} stc_qprc_qcrh_field_t; - -typedef struct stc_qprc_qecr_field -{ - __IO uint16_t ORNGMD : 1; - __IO uint16_t ORNGF : 1; - __IO uint16_t ORNGIE : 1; -} stc_qprc_qecr_field_t; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* ADC12_MODULE register bit fields */ -typedef struct stc_adc_adsr_field -{ - __IO uint8_t SCS : 1; - __IO uint8_t PCS : 1; - __IO uint8_t PCNS : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t FDAS : 1; - __IO uint8_t ADSTP : 1; -} stc_adc_adsr_field_t; - -typedef struct stc_adc_adcr_field -{ - __IO uint8_t OVRIE : 1; - __IO uint8_t CMPIE : 1; - __IO uint8_t PCIE : 1; - __IO uint8_t SCIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t CMPIF : 1; - __IO uint8_t PCIF : 1; - __IO uint8_t SCIF : 1; -} stc_adc_adcr_field_t; - -typedef struct stc_adc_sfns_field -{ - __IO uint8_t SFS0 : 1; - __IO uint8_t SFS1 : 1; - __IO uint8_t SFS2 : 1; - __IO uint8_t SFS3 : 1; -} stc_adc_sfns_field_t; - -typedef struct stc_adc_sccr_field -{ - __IO uint8_t SSTR : 1; - __IO uint8_t SHEN : 1; - __IO uint8_t RPT : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t SFCLR : 1; - __IO uint8_t SOVR : 1; - __IO uint8_t SFUL : 1; - __IO uint8_t SEMP : 1; -} stc_adc_sccr_field_t; - -typedef struct stc_adc_scfd_field -{ - __IO uint32_t SC0 : 1; - __IO uint32_t SC1 : 1; - __IO uint32_t SC2 : 1; - __IO uint32_t SC3 : 1; - __IO uint32_t SC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t SD0 : 1; - __IO uint32_t SD1 : 1; - __IO uint32_t SD2 : 1; - __IO uint32_t SD3 : 1; - __IO uint32_t SD4 : 1; - __IO uint32_t SD5 : 1; - __IO uint32_t SD6 : 1; - __IO uint32_t SD7 : 1; - __IO uint32_t SD8 : 1; - __IO uint32_t SD9 : 1; - __IO uint32_t SD10 : 1; - __IO uint32_t SD11 : 1; -} stc_adc_scfd_field_t; - -typedef struct stc_adc_scfdl_field -{ - __IO uint16_t SC0 : 1; - __IO uint16_t SC1 : 1; - __IO uint16_t SC2 : 1; - __IO uint16_t SC3 : 1; - __IO uint16_t SC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t INVL : 1; -} stc_adc_scfdl_field_t; - -typedef struct stc_adc_scfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t SD0 : 1; - __IO uint16_t SD1 : 1; - __IO uint16_t SD2 : 1; - __IO uint16_t SD3 : 1; - __IO uint16_t SD4 : 1; - __IO uint16_t SD5 : 1; - __IO uint16_t SD6 : 1; - __IO uint16_t SD7 : 1; - __IO uint16_t SD8 : 1; - __IO uint16_t SD9 : 1; - __IO uint16_t SD10 : 1; - __IO uint16_t SD11 : 1; -} stc_adc_scfdh_field_t; - -typedef struct stc_adc_scis23_field -{ - __IO uint16_t AN16 : 1; - __IO uint16_t AN17 : 1; - __IO uint16_t AN18 : 1; - __IO uint16_t AN19 : 1; - __IO uint16_t AN20 : 1; - __IO uint16_t AN21 : 1; - __IO uint16_t AN22 : 1; - __IO uint16_t AN23 : 1; - __IO uint16_t AN24 : 1; - __IO uint16_t AN25 : 1; - __IO uint16_t AN26 : 1; - __IO uint16_t AN27 : 1; - __IO uint16_t AN28 : 1; - __IO uint16_t AN29 : 1; - __IO uint16_t AN30 : 1; - __IO uint16_t AN31 : 1; -} stc_adc_scis23_field_t; - -typedef struct stc_adc_scis2_field -{ - __IO uint8_t AN16 : 1; - __IO uint8_t AN17 : 1; - __IO uint8_t AN18 : 1; - __IO uint8_t AN19 : 1; - __IO uint8_t AN20 : 1; - __IO uint8_t AN21 : 1; - __IO uint8_t AN22 : 1; - __IO uint8_t AN23 : 1; -} stc_adc_scis2_field_t; - -typedef struct stc_adc_scis3_field -{ - __IO uint8_t AN24 : 1; - __IO uint8_t AN25 : 1; - __IO uint8_t AN26 : 1; - __IO uint8_t AN27 : 1; - __IO uint8_t AN28 : 1; - __IO uint8_t AN29 : 1; - __IO uint8_t AN30 : 1; - __IO uint8_t AN31 : 1; -} stc_adc_scis3_field_t; - -typedef struct stc_adc_scis01_field -{ - __IO uint16_t AN0 : 1; - __IO uint16_t AN1 : 1; - __IO uint16_t AN2 : 1; - __IO uint16_t AN3 : 1; - __IO uint16_t AN4 : 1; - __IO uint16_t AN5 : 1; - __IO uint16_t AN6 : 1; - __IO uint16_t AN7 : 1; - __IO uint16_t AN8 : 1; - __IO uint16_t AN9 : 1; - __IO uint16_t AN10 : 1; - __IO uint16_t AN11 : 1; - __IO uint16_t AN12 : 1; - __IO uint16_t AN13 : 1; - __IO uint16_t AN14 : 1; - __IO uint16_t AN15 : 1; -} stc_adc_scis01_field_t; - -typedef struct stc_adc_scis0_field -{ - __IO uint8_t AN0 : 1; - __IO uint8_t AN1 : 1; - __IO uint8_t AN2 : 1; - __IO uint8_t AN3 : 1; - __IO uint8_t AN4 : 1; - __IO uint8_t AN5 : 1; - __IO uint8_t AN6 : 1; - __IO uint8_t AN7 : 1; -} stc_adc_scis0_field_t; - -typedef struct stc_adc_scis1_field -{ - __IO uint8_t AN8 : 1; - __IO uint8_t AN9 : 1; - __IO uint8_t AN10 : 1; - __IO uint8_t AN11 : 1; - __IO uint8_t AN12 : 1; - __IO uint8_t AN13 : 1; - __IO uint8_t AN14 : 1; - __IO uint8_t AN15 : 1; -} stc_adc_scis1_field_t; - -typedef struct stc_adc_pfns_field -{ - __IO uint8_t PFS0 : 1; - __IO uint8_t PFS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t TEST0 : 1; - __IO uint8_t TEST1 : 1; -} stc_adc_pfns_field_t; - -typedef struct stc_adc_pccr_field -{ - __IO uint8_t PSTR : 1; - __IO uint8_t PHEN : 1; - __IO uint8_t PEEN : 1; - __IO uint8_t ESCE : 1; - __IO uint8_t PFCLR : 1; - __IO uint8_t POVR : 1; - __IO uint8_t PFUL : 1; - __IO uint8_t PEMP : 1; -} stc_adc_pccr_field_t; - -typedef struct stc_adc_pcfd_field -{ - __IO uint32_t PC0 : 1; - __IO uint32_t PC1 : 1; - __IO uint32_t PC2 : 1; - __IO uint32_t PC3 : 1; - __IO uint32_t PC4 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t INVL : 1; - uint32_t RESERVED3 : 7; - __IO uint32_t PD0 : 1; - __IO uint32_t PD1 : 1; - __IO uint32_t PD2 : 1; - __IO uint32_t PD3 : 1; - __IO uint32_t PD4 : 1; - __IO uint32_t PD5 : 1; - __IO uint32_t PD6 : 1; - __IO uint32_t PD7 : 1; - __IO uint32_t PD8 : 1; - __IO uint32_t PD9 : 1; - __IO uint32_t PD10 : 1; - __IO uint32_t PD11 : 1; -} stc_adc_pcfd_field_t; - -typedef struct stc_adc_pcfdl_field -{ - __IO uint16_t PC0 : 1; - __IO uint16_t PC1 : 1; - __IO uint16_t PC2 : 1; - __IO uint16_t PC3 : 1; - __IO uint16_t PC4 : 1; - uint16_t RESERVED1 : 3; - __IO uint16_t RS0 : 1; - __IO uint16_t RS1 : 1; - __IO uint16_t RS2 : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t INVL : 1; -} stc_adc_pcfdl_field_t; - -typedef struct stc_adc_pcfdh_field -{ - uint16_t RESERVED1 : 4; - __IO uint16_t PD0 : 1; - __IO uint16_t PD1 : 1; - __IO uint16_t PD2 : 1; - __IO uint16_t PD3 : 1; - __IO uint16_t PD4 : 1; - __IO uint16_t PD5 : 1; - __IO uint16_t PD6 : 1; - __IO uint16_t PD7 : 1; - __IO uint16_t PD8 : 1; - __IO uint16_t PD9 : 1; - __IO uint16_t PD10 : 1; - __IO uint16_t PD11 : 1; -} stc_adc_pcfdh_field_t; - -typedef struct stc_adc_pcis_field -{ - __IO uint8_t P1A0 : 1; - __IO uint8_t P1A1 : 1; - __IO uint8_t P1A2 : 1; - __IO uint8_t P2A0 : 1; - __IO uint8_t P2A1 : 1; - __IO uint8_t P2A2 : 1; - __IO uint8_t P2A3 : 1; - __IO uint8_t P2A4 : 1; -} stc_adc_pcis_field_t; - -typedef struct stc_adc_cmpcr_field -{ - __IO uint8_t CCH0 : 1; - __IO uint8_t CCH1 : 1; - __IO uint8_t CCH2 : 1; - __IO uint8_t CCH3 : 1; - __IO uint8_t CCH4 : 1; - __IO uint8_t CMD0 : 1; - __IO uint8_t CMD1 : 1; - __IO uint8_t CMPEN : 1; -} stc_adc_cmpcr_field_t; - -typedef struct stc_adc_cmpd_field -{ - uint16_t RESERVED1 : 6; - __IO uint16_t CMAD2 : 1; - __IO uint16_t CMAD3 : 1; - __IO uint16_t CMAD4 : 1; - __IO uint16_t CMAD5 : 1; - __IO uint16_t CMAD6 : 1; - __IO uint16_t CMAD7 : 1; - __IO uint16_t CMAD8 : 1; - __IO uint16_t CMAD9 : 1; - __IO uint16_t CMAD10 : 1; - __IO uint16_t CMAD11 : 1; -} stc_adc_cmpd_field_t; - -typedef struct stc_adc_adss23_field -{ - __IO uint16_t TS16 : 1; - __IO uint16_t TS17 : 1; - __IO uint16_t TS18 : 1; - __IO uint16_t TS19 : 1; - __IO uint16_t TS20 : 1; - __IO uint16_t TS21 : 1; - __IO uint16_t TS22 : 1; - __IO uint16_t TS23 : 1; - __IO uint16_t TS24 : 1; - __IO uint16_t TS25 : 1; - __IO uint16_t TS26 : 1; - __IO uint16_t TS27 : 1; - __IO uint16_t TS28 : 1; - __IO uint16_t TS29 : 1; - __IO uint16_t TS30 : 1; - __IO uint16_t TS31 : 1; -} stc_adc_adss23_field_t; - -typedef struct stc_adc_adss2_field -{ - __IO uint8_t TS16 : 1; - __IO uint8_t TS17 : 1; - __IO uint8_t TS18 : 1; - __IO uint8_t TS19 : 1; - __IO uint8_t TS20 : 1; - __IO uint8_t TS21 : 1; - __IO uint8_t TS22 : 1; - __IO uint8_t TS23 : 1; -} stc_adc_adss2_field_t; - -typedef struct stc_adc_adss3_field -{ - __IO uint8_t TS24 : 1; - __IO uint8_t TS25 : 1; - __IO uint8_t TS26 : 1; - __IO uint8_t TS27 : 1; - __IO uint8_t TS28 : 1; - __IO uint8_t TS29 : 1; - __IO uint8_t TS30 : 1; - __IO uint8_t TS31 : 1; -} stc_adc_adss3_field_t; - -typedef struct stc_adc_adss01_field -{ - __IO uint16_t TS0 : 1; - __IO uint16_t TS1 : 1; - __IO uint16_t TS2 : 1; - __IO uint16_t TS3 : 1; - __IO uint16_t TS4 : 1; - __IO uint16_t TS5 : 1; - __IO uint16_t TS6 : 1; - __IO uint16_t TS7 : 1; - __IO uint16_t TS8 : 1; - __IO uint16_t TS9 : 1; - __IO uint16_t TS10 : 1; - __IO uint16_t TS11 : 1; - __IO uint16_t TS12 : 1; - __IO uint16_t TS13 : 1; - __IO uint16_t TS14 : 1; - __IO uint16_t TS15 : 1; -} stc_adc_adss01_field_t; - -typedef struct stc_adc_adss0_field -{ - __IO uint8_t TS0 : 1; - __IO uint8_t TS1 : 1; - __IO uint8_t TS2 : 1; - __IO uint8_t TS3 : 1; - __IO uint8_t TS4 : 1; - __IO uint8_t TS5 : 1; - __IO uint8_t TS6 : 1; - __IO uint8_t TS7 : 1; -} stc_adc_adss0_field_t; - -typedef struct stc_adc_adss1_field -{ - __IO uint8_t TS8 : 1; - __IO uint8_t TS9 : 1; - __IO uint8_t TS10 : 1; - __IO uint8_t TS11 : 1; - __IO uint8_t TS12 : 1; - __IO uint8_t TS13 : 1; - __IO uint8_t TS14 : 1; - __IO uint8_t TS15 : 1; -} stc_adc_adss1_field_t; - -typedef struct stc_adc_adst01_field -{ - __IO uint16_t ST10 : 1; - __IO uint16_t ST11 : 1; - __IO uint16_t ST12 : 1; - __IO uint16_t ST13 : 1; - __IO uint16_t ST14 : 1; - __IO uint16_t STX10 : 1; - __IO uint16_t STX11 : 1; - __IO uint16_t STX12 : 1; - __IO uint16_t ST00 : 1; - __IO uint16_t ST01 : 1; - __IO uint16_t ST02 : 1; - __IO uint16_t ST03 : 1; - __IO uint16_t ST04 : 1; - __IO uint16_t STX00 : 1; - __IO uint16_t STX01 : 1; - __IO uint16_t STX02 : 1; -} stc_adc_adst01_field_t; - -typedef struct stc_adc_adst1_field -{ - __IO uint8_t ST10 : 1; - __IO uint8_t ST11 : 1; - __IO uint8_t ST12 : 1; - __IO uint8_t ST13 : 1; - __IO uint8_t ST14 : 1; - __IO uint8_t STX10 : 1; - __IO uint8_t STX11 : 1; - __IO uint8_t STX12 : 1; -} stc_adc_adst1_field_t; - -typedef struct stc_adc_adst0_field -{ - __IO uint8_t ST00 : 1; - __IO uint8_t ST01 : 1; - __IO uint8_t ST02 : 1; - __IO uint8_t ST03 : 1; - __IO uint8_t ST04 : 1; - __IO uint8_t STX00 : 1; - __IO uint8_t STX01 : 1; - __IO uint8_t STX02 : 1; -} stc_adc_adst0_field_t; - -typedef struct stc_adc_adct_field -{ - __IO uint8_t CT0 : 1; - __IO uint8_t CT1 : 1; - __IO uint8_t CT2 : 1; - __IO uint8_t CT3 : 1; - __IO uint8_t CT4 : 1; - __IO uint8_t CT5 : 1; - __IO uint8_t CT6 : 1; - __IO uint8_t CT7 : 1; -} stc_adc_adct_field_t; - -typedef struct stc_adc_prtsl_field -{ - __IO uint8_t PRTSL0 : 1; - __IO uint8_t PRTSL1 : 1; - __IO uint8_t PRTSL2 : 1; - __IO uint8_t PRTSL3 : 1; -} stc_adc_prtsl_field_t; - -typedef struct stc_adc_sctsl_field -{ - __IO uint8_t SCTSL0 : 1; - __IO uint8_t SCTSL1 : 1; - __IO uint8_t SCTSL2 : 1; - __IO uint8_t SCTSL3 : 1; -} stc_adc_sctsl_field_t; - -typedef struct stc_adc_adcen_field -{ - __IO uint8_t ENBL : 1; - __IO uint8_t READY : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t CYCLSL0 : 1; - __IO uint8_t CYCLSL1 : 1; -} stc_adc_adcen_field_t; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CRTRIM_MODULE register bit fields */ -typedef struct stc_crtrim_mcr_psr_field -{ - __IO uint8_t CSR0 : 1; - __IO uint8_t CSR1 : 1; -} stc_crtrim_mcr_psr_field_t; - -typedef struct stc_crtrim_mcr_ftrm_field -{ - __IO uint16_t TRD0 : 1; - __IO uint16_t TRD1 : 1; - __IO uint16_t TRD2 : 1; - __IO uint16_t TRD3 : 1; - __IO uint16_t TRD4 : 1; - __IO uint16_t TRD5 : 1; - __IO uint16_t TRD6 : 1; - __IO uint16_t TRD7 : 1; -} stc_crtrim_mcr_ftrm_field_t; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* EXTI_MODULE registEN bit fields */ -typedef struct stc_exti_enir_field -{ - __IO uint16_t EN0 : 1; - __IO uint16_t EN1 : 1; - __IO uint16_t EN2 : 1; - __IO uint16_t EN3 : 1; - __IO uint16_t EN4 : 1; - __IO uint16_t EN5 : 1; - __IO uint16_t EN6 : 1; - __IO uint16_t EN7 : 1; - __IO uint16_t EN8 : 1; - __IO uint16_t EN9 : 1; - __IO uint16_t EN10 : 1; - __IO uint16_t EN11 : 1; - __IO uint16_t EN12 : 1; - __IO uint16_t EN13 : 1; - __IO uint16_t EN14 : 1; - __IO uint16_t EN15 : 1; - __IO uint16_t EN16 : 1; - __IO uint16_t EN17 : 1; - __IO uint16_t EN18 : 1; - __IO uint16_t EN19 : 1; - __IO uint16_t EN20 : 1; - __IO uint16_t EN21 : 1; - __IO uint16_t EN22 : 1; - __IO uint16_t EN23 : 1; - __IO uint16_t EN24 : 1; - __IO uint16_t EN25 : 1; - __IO uint16_t EN26 : 1; - __IO uint16_t EN27 : 1; - __IO uint16_t EN28 : 1; - __IO uint16_t EN29 : 1; - __IO uint16_t EN30 : 1; - __IO uint16_t EN31 : 1; -} stc_exti_enir_field_t; - -typedef struct stc_exti_eirr_field -{ - __IO uint16_t ER0 : 1; - __IO uint16_t ER1 : 1; - __IO uint16_t ER2 : 1; - __IO uint16_t ER3 : 1; - __IO uint16_t ER4 : 1; - __IO uint16_t ER5 : 1; - __IO uint16_t ER6 : 1; - __IO uint16_t ER7 : 1; - __IO uint16_t ER8 : 1; - __IO uint16_t ER9 : 1; - __IO uint16_t ER10 : 1; - __IO uint16_t ER11 : 1; - __IO uint16_t ER12 : 1; - __IO uint16_t ER13 : 1; - __IO uint16_t ER14 : 1; - __IO uint16_t ER15 : 1; - __IO uint16_t ER16 : 1; - __IO uint16_t ER17 : 1; - __IO uint16_t ER18 : 1; - __IO uint16_t ER19 : 1; - __IO uint16_t ER20 : 1; - __IO uint16_t ER21 : 1; - __IO uint16_t ER22 : 1; - __IO uint16_t ER23 : 1; - __IO uint16_t ER24 : 1; - __IO uint16_t ER25 : 1; - __IO uint16_t ER26 : 1; - __IO uint16_t ER27 : 1; - __IO uint16_t ER28 : 1; - __IO uint16_t ER29 : 1; - __IO uint16_t ER30 : 1; - __IO uint16_t ER31 : 1; -} stc_exti_eirr_field_t; - -typedef struct stc_exti_eicl_field -{ - __IO uint16_t ECL0 : 1; - __IO uint16_t ECL1 : 1; - __IO uint16_t ECL2 : 1; - __IO uint16_t ECL3 : 1; - __IO uint16_t ECL4 : 1; - __IO uint16_t ECL5 : 1; - __IO uint16_t ECL6 : 1; - __IO uint16_t ECL7 : 1; - __IO uint16_t ECL8 : 1; - __IO uint16_t ECL9 : 1; - __IO uint16_t ECL10 : 1; - __IO uint16_t ECL11 : 1; - __IO uint16_t ECL12 : 1; - __IO uint16_t ECL13 : 1; - __IO uint16_t ECL14 : 1; - __IO uint16_t ECL15 : 1; - __IO uint16_t ECL16 : 1; - __IO uint16_t ECL17 : 1; - __IO uint16_t ECL18 : 1; - __IO uint16_t ECL19 : 1; - __IO uint16_t ECL20 : 1; - __IO uint16_t ECL21 : 1; - __IO uint16_t ECL22 : 1; - __IO uint16_t ECL23 : 1; - __IO uint16_t ECL24 : 1; - __IO uint16_t ECL25 : 1; - __IO uint16_t ECL26 : 1; - __IO uint16_t ECL27 : 1; - __IO uint16_t ECL28 : 1; - __IO uint16_t ECL29 : 1; - __IO uint16_t ECL30 : 1; - __IO uint16_t ECL31 : 1; -} stc_exti_eicl_field_t; - -typedef struct stc_exti_elvr_field -{ - __IO uint32_t LA0 : 1; - __IO uint32_t LB0 : 1; - __IO uint32_t LA1 : 1; - __IO uint32_t LB1 : 1; - __IO uint32_t LA2 : 1; - __IO uint32_t LB2 : 1; - __IO uint32_t LA3 : 1; - __IO uint32_t LB3 : 1; - __IO uint32_t LA4 : 1; - __IO uint32_t LB4 : 1; - __IO uint32_t LA5 : 1; - __IO uint32_t LB5 : 1; - __IO uint32_t LA6 : 1; - __IO uint32_t LB6 : 1; - __IO uint32_t LA7 : 1; - __IO uint32_t LB7 : 1; - __IO uint32_t LA8 : 1; - __IO uint32_t LB8 : 1; - __IO uint32_t LA9 : 1; - __IO uint32_t LB9 : 1; - __IO uint32_t LA10 : 1; - __IO uint32_t LB10 : 1; - __IO uint32_t LA11 : 1; - __IO uint32_t LB11 : 1; - __IO uint32_t LA12 : 1; - __IO uint32_t LB12 : 1; - __IO uint32_t LA13 : 1; - __IO uint32_t LB13 : 1; - __IO uint32_t LA14 : 1; - __IO uint32_t LB14 : 1; - __IO uint32_t LA15 : 1; - __IO uint32_t LB15 : 1; -} stc_exti_elvr_field_t; - -typedef struct stc_exti_elvr1_field -{ - __IO uint32_t LA16 : 1; - __IO uint32_t LB16 : 1; - __IO uint32_t LA17 : 1; - __IO uint32_t LB17 : 1; - __IO uint32_t LA18 : 1; - __IO uint32_t LB18 : 1; - __IO uint32_t LA19 : 1; - __IO uint32_t LB19 : 1; - __IO uint32_t LA20 : 1; - __IO uint32_t LB20 : 1; - __IO uint32_t LA21 : 1; - __IO uint32_t LB21 : 1; - __IO uint32_t LA22 : 1; - __IO uint32_t LB22 : 1; - __IO uint32_t LA23 : 1; - __IO uint32_t LB23 : 1; - __IO uint32_t LA24 : 1; - __IO uint32_t LB24 : 1; - __IO uint32_t LA25 : 1; - __IO uint32_t LB25 : 1; - __IO uint32_t LA26 : 1; - __IO uint32_t LB26 : 1; - __IO uint32_t LA27 : 1; - __IO uint32_t LB27 : 1; - __IO uint32_t LA28 : 1; - __IO uint32_t LB28 : 1; - __IO uint32_t LA29 : 1; - __IO uint32_t LB29 : 1; - __IO uint32_t LA30 : 1; - __IO uint32_t LB30 : 1; - __IO uint32_t LA31 : 1; - __IO uint32_t LB31 : 1; -} stc_exti_elvr1_field_t; - -typedef struct stc_exti_nmirr_field -{ - __IO uint8_t NR0 : 1; -} stc_exti_nmirr_field_t; - -typedef struct stc_exti_nmicl_field -{ - __IO uint8_t NCL0 : 1; -} stc_exti_nmicl_field_t; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* INTREQ_MODULE register bit fields */ -typedef struct stc_intreq_drqsel_field -{ - __IO uint32_t DRQSEL0 : 1; - __IO uint32_t DRQSEL1 : 1; - __IO uint32_t DRQSEL2 : 1; - __IO uint32_t DRQSEL3 : 1; - __IO uint32_t DRQSEL4 : 1; - __IO uint32_t DRQSEL5 : 1; - __IO uint32_t DRQSEL6 : 1; - __IO uint32_t DRQSEL7 : 1; - __IO uint32_t DRQSEL8 : 1; - __IO uint32_t DRQSEL9 : 1; - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; - __IO uint32_t DRQSEL15 : 1; - __IO uint32_t DRQSEL16 : 1; - __IO uint32_t DRQSEL17 : 1; - __IO uint32_t DRQSEL18 : 1; - __IO uint32_t DRQSEL19 : 1; - __IO uint32_t DRQSEL20 : 1; - __IO uint32_t DRQSEL21 : 1; - __IO uint32_t DRQSEL22 : 1; - __IO uint32_t DRQSEL23 : 1; - __IO uint32_t DRQSEL24 : 1; - __IO uint32_t DRQSEL25 : 1; - __IO uint32_t DRQSEL26 : 1; - __IO uint32_t DRQSEL27 : 1; - __IO uint32_t DRQSEL28 : 1; - __IO uint32_t DRQSEL29 : 1; - __IO uint32_t DRQSEL30 : 1; - __IO uint32_t DRQSEL31 : 1; -} stc_intreq_drqsel_field_t; - -typedef struct stc_intreq_oddpks_field -{ - __IO uint8_t ODDPKS0 : 1; - __IO uint8_t ODDPKS1 : 1; - __IO uint8_t ODDPKS2 : 1; - __IO uint8_t ODDPKS3 : 1; - __IO uint8_t ODDPKS4 : 1; -} stc_intreq_oddpks_field_t; - -typedef struct stc_intreq_exc02mon_field -{ - __IO uint32_t NMI : 1; - __IO uint32_t HWINT : 1; -} stc_intreq_exc02mon_field_t; - -typedef struct stc_intreq_irq00mon_field -{ - __IO uint32_t FCSINT : 1; -} stc_intreq_irq00mon_field_t; - -typedef struct stc_intreq_irq01mon_field -{ - __IO uint32_t SWWDTINT : 1; -} stc_intreq_irq01mon_field_t; - -typedef struct stc_intreq_irq02mon_field -{ - __IO uint32_t LVDINT : 1; -} stc_intreq_irq02mon_field_t; - -typedef struct stc_intreq_irq03mon_field -{ - __IO uint32_t WAVE0INT0 : 1; - __IO uint32_t WAVE0INT1 : 1; - __IO uint32_t WAVE0INT2 : 1; - __IO uint32_t WAVE0INT3 : 1; - __IO uint32_t WAVE1INT0 : 1; - __IO uint32_t WAVE1INT1 : 1; - __IO uint32_t WAVE1INT2 : 1; - __IO uint32_t WAVE1INT3 : 1; - __IO uint32_t WAVE2INT0 : 1; - __IO uint32_t WAVE2INT1 : 1; - __IO uint32_t WAVE2INT2 : 1; - __IO uint32_t WAVE2INT3 : 1; -} stc_intreq_irq03mon_field_t; - -typedef struct stc_intreq_irq04mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; -} stc_intreq_irq04mon_field_t; - -typedef struct stc_intreq_irq05mon_field -{ - __IO uint32_t EXTINT0 : 1; - __IO uint32_t EXTINT1 : 1; - __IO uint32_t EXTINT2 : 1; - __IO uint32_t EXTINT3 : 1; - __IO uint32_t EXTINT4 : 1; - __IO uint32_t EXTINT5 : 1; - __IO uint32_t EXTINT6 : 1; - __IO uint32_t EXTINT7 : 1; - __IO uint32_t EXTINT8 : 1; - __IO uint32_t EXTINT9 : 1; - __IO uint32_t EXTINT10 : 1; - __IO uint32_t EXTINT11 : 1; - __IO uint32_t EXTINT12 : 1; - __IO uint32_t EXTINT13 : 1; - __IO uint32_t EXTINT14 : 1; - __IO uint32_t EXTINT15 : 1; - __IO uint32_t EXTINT16 : 1; - __IO uint32_t EXTINT17 : 1; - __IO uint32_t EXTINT18 : 1; - __IO uint32_t EXTINT19 : 1; - __IO uint32_t EXTINT20 : 1; - __IO uint32_t EXTINT21 : 1; - __IO uint32_t EXTINT22 : 1; - __IO uint32_t EXTINT23 : 1; -} stc_intreq_irq05mon_field_t; - -typedef struct stc_intreq_irq06mon_field -{ - __IO uint32_t TIMINT1 : 1; - __IO uint32_t TIMINT2 : 1; - __IO uint32_t QUD0INT0 : 1; - __IO uint32_t QUD0INT1 : 1; - __IO uint32_t QUD0INT2 : 1; - __IO uint32_t QUD0INT3 : 1; - __IO uint32_t QUD0INT4 : 1; - __IO uint32_t QUD0INT5 : 1; - __IO uint32_t QUD1INT0 : 1; - __IO uint32_t QUD1INT1 : 1; - __IO uint32_t QUD1INT2 : 1; - __IO uint32_t QUD1INT3 : 1; - __IO uint32_t QUD1INT4 : 1; - __IO uint32_t QUD1INT5 : 1; - __IO uint32_t QUD2INT0 : 1; - __IO uint32_t QUD2INT1 : 1; - __IO uint32_t QUD2INT2 : 1; - __IO uint32_t QUD2INT3 : 1; - __IO uint32_t QUD2INT4 : 1; - __IO uint32_t QUD2INT5 : 1; -} stc_intreq_irq06mon_field_t; - -typedef struct stc_intreq_irq07mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq07mon_field_t; - -typedef struct stc_intreq_irq08mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq08mon_field_t; - -typedef struct stc_intreq_irq09mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq09mon_field_t; - -typedef struct stc_intreq_irq10mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq10mon_field_t; - -typedef struct stc_intreq_irq11mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq11mon_field_t; - -typedef struct stc_intreq_irq12mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq12mon_field_t; - -typedef struct stc_intreq_irq13mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq13mon_field_t; - -typedef struct stc_intreq_irq14mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq14mon_field_t; - -typedef struct stc_intreq_irq15mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq15mon_field_t; - -typedef struct stc_intreq_irq16mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq16mon_field_t; - -typedef struct stc_intreq_irq17mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq17mon_field_t; - -typedef struct stc_intreq_irq18mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq18mon_field_t; - -typedef struct stc_intreq_irq19mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq19mon_field_t; - -typedef struct stc_intreq_irq20mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq20mon_field_t; - -typedef struct stc_intreq_irq21mon_field -{ - __IO uint32_t FMSINT : 1; -} stc_intreq_irq21mon_field_t; - -typedef struct stc_intreq_irq22mon_field -{ - __IO uint32_t MFSINT0 : 1; - __IO uint32_t MFSINT1 : 1; -} stc_intreq_irq22mon_field_t; - -typedef struct stc_intreq_irq23mon_field -{ - __IO uint32_t PPGINT0 : 1; - __IO uint32_t PPGINT1 : 1; - __IO uint32_t PPGINT2 : 1; - __IO uint32_t PPGINT3 : 1; - __IO uint32_t PPGINT4 : 1; - __IO uint32_t PPGINT5 : 1; - __IO uint32_t PPGINT6 : 1; - __IO uint32_t PPGINT7 : 1; - __IO uint32_t PPGINT8 : 1; -} stc_intreq_irq23mon_field_t; - -typedef struct stc_intreq_irq24mon_field -{ - __IO uint32_t MOSCINT : 1; - __IO uint32_t SOSCINT : 1; - __IO uint32_t MPLLINT : 1; - __IO uint32_t UPLLINT : 1; - __IO uint32_t WCINT : 1; -} stc_intreq_irq24mon_field_t; - -typedef struct stc_intreq_irq25mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq25mon_field_t; - -typedef struct stc_intreq_irq26mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq26mon_field_t; - -typedef struct stc_intreq_irq27mon_field -{ - __IO uint32_t ADCINT0 : 1; - __IO uint32_t ADCINT1 : 1; - __IO uint32_t ADCINT2 : 1; - __IO uint32_t ADCINT3 : 1; -} stc_intreq_irq27mon_field_t; - -typedef struct stc_intreq_irq28mon_field -{ - __IO uint32_t FRT0INT0 : 1; - __IO uint32_t FRT0INT1 : 1; - __IO uint32_t FRT0INT2 : 1; - __IO uint32_t FRT0INT3 : 1; - __IO uint32_t FRT0INT4 : 1; - __IO uint32_t FRT0INT5 : 1; - __IO uint32_t FRT1INT0 : 1; - __IO uint32_t FRT1INT1 : 1; - __IO uint32_t FRT1INT2 : 1; - __IO uint32_t FRT1INT3 : 1; - __IO uint32_t FRT1INT4 : 1; - __IO uint32_t FRT1INT5 : 1; - __IO uint32_t FRT2INT0 : 1; - __IO uint32_t FRT2INT1 : 1; - __IO uint32_t FRT2INT2 : 1; - __IO uint32_t FRT2INT3 : 1; - __IO uint32_t FRT2INT4 : 1; - __IO uint32_t FRT2INT5 : 1; -} stc_intreq_irq28mon_field_t; - -typedef struct stc_intreq_irq29mon_field -{ - __IO uint32_t ICU0INT0 : 1; - __IO uint32_t ICU0INT1 : 1; - __IO uint32_t ICU0INT2 : 1; - __IO uint32_t ICU0INT3 : 1; - __IO uint32_t ICU1INT0 : 1; - __IO uint32_t ICU1INT1 : 1; - __IO uint32_t ICU1INT2 : 1; - __IO uint32_t ICU1INT3 : 1; - __IO uint32_t ICU2INT0 : 1; - __IO uint32_t ICU2INT1 : 1; - __IO uint32_t ICU2INT2 : 1; - __IO uint32_t ICU2INT3 : 1; -} stc_intreq_irq29mon_field_t; - -typedef struct stc_intreq_irq30mon_field -{ - __IO uint32_t OCU0INT0 : 1; - __IO uint32_t OCU0INT1 : 1; - __IO uint32_t OCU0INT2 : 1; - __IO uint32_t OCU0INT3 : 1; - __IO uint32_t OCU0INT4 : 1; - __IO uint32_t OCU0INT5 : 1; - __IO uint32_t OCU1INT0 : 1; - __IO uint32_t OCU1INT1 : 1; - __IO uint32_t OCU1INT2 : 1; - __IO uint32_t OCU1INT3 : 1; - __IO uint32_t OCU1INT4 : 1; - __IO uint32_t OCU1INT5 : 1; - __IO uint32_t OCU2INT0 : 1; - __IO uint32_t OCU2INT1 : 1; - __IO uint32_t OCU2INT2 : 1; - __IO uint32_t OCU2INT3 : 1; - __IO uint32_t OCU2INT4 : 1; - __IO uint32_t OCU2INT5 : 1; -} stc_intreq_irq30mon_field_t; - -typedef struct stc_intreq_irq31mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; - __IO uint32_t BTINT8 : 1; - __IO uint32_t BTINT9 : 1; - __IO uint32_t BTINT10 : 1; - __IO uint32_t BTINT11 : 1; - __IO uint32_t BTINT12 : 1; - __IO uint32_t BTINT13 : 1; - __IO uint32_t BTINT14 : 1; - __IO uint32_t BTINT15 : 1; -} stc_intreq_irq31mon_field_t; - -typedef struct stc_intreq_irq32mon_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t MAC0SBD : 1; - __IO uint32_t MAC0PMI : 1; - __IO uint32_t MAC0LPI : 1; -} stc_intreq_irq32mon_field_t; - -typedef struct stc_intreq_irq33mon_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t MAC1SBD : 1; - __IO uint32_t MAC1PMI : 1; -} stc_intreq_irq33mon_field_t; - -typedef struct stc_intreq_irq34mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; -} stc_intreq_irq34mon_field_t; - -typedef struct stc_intreq_irq35mon_field -{ - __IO uint32_t USB0INT0 : 1; - __IO uint32_t USB0INT1 : 1; - __IO uint32_t USB0INT2 : 1; - __IO uint32_t USB0INT3 : 1; - __IO uint32_t USB0INT4 : 1; - __IO uint32_t USB0INT5 : 1; -} stc_intreq_irq35mon_field_t; - -typedef struct stc_intreq_irq36mon_field -{ - __IO uint32_t USB1INT0 : 1; - __IO uint32_t USB1INT1 : 1; - __IO uint32_t USB1INT2 : 1; - __IO uint32_t USB1INT3 : 1; - __IO uint32_t USB1INT4 : 1; -} stc_intreq_irq36mon_field_t; - -typedef struct stc_intreq_irq37mon_field -{ - __IO uint32_t USB1INT0 : 1; - __IO uint32_t USB1INT1 : 1; - __IO uint32_t USB1INT2 : 1; - __IO uint32_t USB1INT3 : 1; - __IO uint32_t USB1INT4 : 1; - __IO uint32_t USB1INT5 : 1; -} stc_intreq_irq37mon_field_t; - -typedef struct stc_intreq_irq38mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq38mon_field_t; - -typedef struct stc_intreq_irq39mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq39mon_field_t; - -typedef struct stc_intreq_irq40mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq40mon_field_t; - -typedef struct stc_intreq_irq41mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq41mon_field_t; - -typedef struct stc_intreq_irq42mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq42mon_field_t; - -typedef struct stc_intreq_irq43mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq43mon_field_t; - -typedef struct stc_intreq_irq44mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq44mon_field_t; - -typedef struct stc_intreq_irq45mon_field -{ - __IO uint32_t DMAINT : 1; -} stc_intreq_irq45mon_field_t; - -typedef struct stc_intreq_irq46mon_field -{ - __IO uint32_t BTINT0 : 1; - __IO uint32_t BTINT1 : 1; - __IO uint32_t BTINT2 : 1; - __IO uint32_t BTINT3 : 1; - __IO uint32_t BTINT4 : 1; - __IO uint32_t BTINT5 : 1; - __IO uint32_t BTINT6 : 1; - __IO uint32_t BTINT7 : 1; - __IO uint32_t BTINT8 : 1; - __IO uint32_t BTINT9 : 1; - __IO uint32_t BTINT10 : 1; - __IO uint32_t BTINT11 : 1; - __IO uint32_t BTINT12 : 1; - __IO uint32_t BTINT13 : 1; - __IO uint32_t BTINT14 : 1; - __IO uint32_t BTINT15 : 1; -} stc_intreq_irq46mon_field_t; - -typedef struct stc_intreq_drqsel1_field -{ - __IO uint32_t DRQSEL10 : 1; - __IO uint32_t DRQSEL11 : 1; - __IO uint32_t DRQSEL12 : 1; - __IO uint32_t DRQSEL13 : 1; - __IO uint32_t DRQSEL14 : 1; -} stc_intreq_drqsel1_field_t; - -typedef struct stc_intreq_dqesel_field -{ - __IO uint32_t ESEL100 : 1; - __IO uint32_t ESEL101 : 1; - __IO uint32_t ESEL102 : 1; - __IO uint32_t ESEL103 : 1; - __IO uint32_t ESEL110 : 1; - __IO uint32_t ESEL111 : 1; - __IO uint32_t ESEL112 : 1; - __IO uint32_t ESEL113 : 1; - __IO uint32_t ESEL240 : 1; - __IO uint32_t ESEL241 : 1; - __IO uint32_t ESEL242 : 1; - __IO uint32_t ESEL243 : 1; - __IO uint32_t ESEL250 : 1; - __IO uint32_t ESEL251 : 1; - __IO uint32_t ESEL252 : 1; - __IO uint32_t ESEL253 : 1; - __IO uint32_t ESEL260 : 1; - __IO uint32_t ESEL261 : 1; - __IO uint32_t ESEL262 : 1; - __IO uint32_t ESEL263 : 1; - __IO uint32_t ESEL270 : 1; - __IO uint32_t ESEL271 : 1; - __IO uint32_t ESEL272 : 1; - __IO uint32_t ESEL273 : 1; - __IO uint32_t ESEL300 : 1; - __IO uint32_t ESEL301 : 1; - __IO uint32_t ESEL302 : 1; - __IO uint32_t ESEL303 : 1; - __IO uint32_t ESEL310 : 1; - __IO uint32_t ESEL311 : 1; - __IO uint32_t ESEL312 : 1; - __IO uint32_t ESEL313 : 1; -} stc_intreq_dqesel_field_t; - -typedef struct stc_intreq_oddpks1_field -{ - __IO uint8_t ODDPKS10 : 1; - __IO uint8_t ODDPKS11 : 1; - __IO uint8_t ODDPKS12 : 1; - __IO uint8_t ODDPKS13 : 1; - __IO uint8_t ODDPKS14 : 1; -} stc_intreq_oddpks1_field_t; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* GPIO_MODULE register bit fields */ -typedef struct stc_gpio_pfr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pfr0_field_t; - -typedef struct stc_gpio_pfr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr1_field_t; - -typedef struct stc_gpio_pfr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pfr2_field_t; - -typedef struct stc_gpio_pfr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr3_field_t; - -typedef struct stc_gpio_pfr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pfr4_field_t; - -typedef struct stc_gpio_pfr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_pfr5_field_t; - -typedef struct stc_gpio_pfr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pfr6_field_t; - -typedef struct stc_gpio_pfr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfr7_field_t; - -typedef struct stc_gpio_pfr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfr8_field_t; - -typedef struct stc_gpio_pfr9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pfr9_field_t; - -typedef struct stc_gpio_pfra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pfra_field_t; - -typedef struct stc_gpio_pfrb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_pfrb_field_t; - -typedef struct stc_gpio_pfrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pfrc_field_t; - -typedef struct stc_gpio_pfrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfrd_field_t; - -typedef struct stc_gpio_pfre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pfre_field_t; - -typedef struct stc_gpio_pfrf_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pfrf_field_t; - -typedef struct stc_gpio_pcr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pcr0_field_t; - -typedef struct stc_gpio_pcr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr1_field_t; - -typedef struct stc_gpio_pcr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pcr2_field_t; - -typedef struct stc_gpio_pcr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr3_field_t; - -typedef struct stc_gpio_pcr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pcr4_field_t; - -typedef struct stc_gpio_pcr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_pcr5_field_t; - -typedef struct stc_gpio_pcr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pcr6_field_t; - -typedef struct stc_gpio_pcr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcr7_field_t; - -typedef struct stc_gpio_pcr9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pcr9_field_t; - -typedef struct stc_gpio_pcra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pcra_field_t; - -typedef struct stc_gpio_pcrb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_pcrb_field_t; - -typedef struct stc_gpio_pcrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pcrc_field_t; - -typedef struct stc_gpio_pcrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pcrd_field_t; - -typedef struct stc_gpio_pcre_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pcre_field_t; - -typedef struct stc_gpio_ddr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_ddr0_field_t; - -typedef struct stc_gpio_ddr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr1_field_t; - -typedef struct stc_gpio_ddr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_ddr2_field_t; - -typedef struct stc_gpio_ddr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr3_field_t; - -typedef struct stc_gpio_ddr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_ddr4_field_t; - -typedef struct stc_gpio_ddr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_ddr5_field_t; - -typedef struct stc_gpio_ddr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_ddr6_field_t; - -typedef struct stc_gpio_ddr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddr7_field_t; - -typedef struct stc_gpio_ddr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddr8_field_t; - -typedef struct stc_gpio_ddr9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_ddr9_field_t; - -typedef struct stc_gpio_ddra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_ddra_field_t; - -typedef struct stc_gpio_ddrb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_ddrb_field_t; - -typedef struct stc_gpio_ddrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_ddrc_field_t; - -typedef struct stc_gpio_ddrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddrd_field_t; - -typedef struct stc_gpio_ddre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_ddre_field_t; - -typedef struct stc_gpio_ddrf_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_ddrf_field_t; - -typedef struct stc_gpio_pdir0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdir0_field_t; - -typedef struct stc_gpio_pdir1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir1_field_t; - -typedef struct stc_gpio_pdir2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdir2_field_t; - -typedef struct stc_gpio_pdir3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir3_field_t; - -typedef struct stc_gpio_pdir4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdir4_field_t; - -typedef struct stc_gpio_pdir5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_pdir5_field_t; - -typedef struct stc_gpio_pdir6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pdir6_field_t; - -typedef struct stc_gpio_pdir7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdir7_field_t; - -typedef struct stc_gpio_pdir8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdir8_field_t; - -typedef struct stc_gpio_pdir9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdir9_field_t; - -typedef struct stc_gpio_pdira_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdira_field_t; - -typedef struct stc_gpio_pdirb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_pdirb_field_t; - -typedef struct stc_gpio_pdirc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdirc_field_t; - -typedef struct stc_gpio_pdird_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdird_field_t; - -typedef struct stc_gpio_pdire_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdire_field_t; - -typedef struct stc_gpio_pdirf_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pdirf_field_t; - -typedef struct stc_gpio_pdor0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdor0_field_t; - -typedef struct stc_gpio_pdor1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor1_field_t; - -typedef struct stc_gpio_pdor2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pdor2_field_t; - -typedef struct stc_gpio_pdor3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor3_field_t; - -typedef struct stc_gpio_pdor4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pdor4_field_t; - -typedef struct stc_gpio_pdor5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_pdor5_field_t; - -typedef struct stc_gpio_pdor6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pdor6_field_t; - -typedef struct stc_gpio_pdor7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdor7_field_t; - -typedef struct stc_gpio_pdor8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdor8_field_t; - -typedef struct stc_gpio_pdor9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdor9_field_t; - -typedef struct stc_gpio_pdora_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pdora_field_t; - -typedef struct stc_gpio_pdorb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_pdorb_field_t; - -typedef struct stc_gpio_pdorc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pdorc_field_t; - -typedef struct stc_gpio_pdord_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdord_field_t; - -typedef struct stc_gpio_pdore_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pdore_field_t; - -typedef struct stc_gpio_pdorf_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pdorf_field_t; - -typedef struct stc_gpio_ade_field -{ - __IO uint32_t AN0 : 1; - __IO uint32_t AN1 : 1; - __IO uint32_t AN2 : 1; - __IO uint32_t AN3 : 1; - __IO uint32_t AN4 : 1; - __IO uint32_t AN5 : 1; - __IO uint32_t AN6 : 1; - __IO uint32_t AN7 : 1; - __IO uint32_t AN8 : 1; - __IO uint32_t AN9 : 1; - __IO uint32_t AN10 : 1; - __IO uint32_t AN11 : 1; - __IO uint32_t AN12 : 1; - __IO uint32_t AN13 : 1; - __IO uint32_t AN14 : 1; - __IO uint32_t AN15 : 1; - __IO uint32_t AN16 : 1; - __IO uint32_t AN17 : 1; - __IO uint32_t AN18 : 1; - __IO uint32_t AN19 : 1; - __IO uint32_t AN20 : 1; - __IO uint32_t AN21 : 1; - __IO uint32_t AN22 : 1; - __IO uint32_t AN23 : 1; - __IO uint32_t AN24 : 1; - __IO uint32_t AN25 : 1; - __IO uint32_t AN26 : 1; - __IO uint32_t AN27 : 1; - __IO uint32_t AN28 : 1; - __IO uint32_t AN29 : 1; - __IO uint32_t AN30 : 1; - __IO uint32_t AN31 : 1; -} stc_gpio_ade_field_t; - -typedef struct stc_gpio_spsr_field -{ - __IO uint32_t SUBXC : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MAINXC : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t USB0C : 1; - __IO uint32_t USB1C : 1; -} stc_gpio_spsr_field_t; - -typedef struct stc_gpio_epfr00_field -{ - __IO uint32_t NMIS : 1; - __IO uint32_t CROUTE0 : 1; - __IO uint32_t CROUTE1 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t SUBOUTE0 : 1; - __IO uint32_t SUBOUTE1 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t USBP0E : 1; - uint32_t RESERVED3 : 3; - __IO uint32_t USBP1E : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t JTAGEN0B : 1; - __IO uint32_t JTAGEN1S : 1; - uint32_t RESERVED5 : 6; - __IO uint32_t TRC0E : 1; - __IO uint32_t TRC1E : 1; -} stc_gpio_epfr00_field_t; - -typedef struct stc_gpio_epfr01_field -{ - __IO uint32_t RTO00E0 : 1; - __IO uint32_t RTO00E1 : 1; - __IO uint32_t RTO01E0 : 1; - __IO uint32_t RTO01E1 : 1; - __IO uint32_t RTO02E0 : 1; - __IO uint32_t RTO02E1 : 1; - __IO uint32_t RTO03E0 : 1; - __IO uint32_t RTO03E1 : 1; - __IO uint32_t RTO04E0 : 1; - __IO uint32_t RTO04E1 : 1; - __IO uint32_t RTO05E0 : 1; - __IO uint32_t RTO05E1 : 1; - __IO uint32_t DTTI0C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI0S0 : 1; - __IO uint32_t DTTI0S1 : 1; - __IO uint32_t FRCK0S0 : 1; - __IO uint32_t FRCK0S1 : 1; - __IO uint32_t IC00S0 : 1; - __IO uint32_t IC00S1 : 1; - __IO uint32_t IC00S2 : 1; - __IO uint32_t IC01S0 : 1; - __IO uint32_t IC01S1 : 1; - __IO uint32_t IC01S2 : 1; - __IO uint32_t IC02S0 : 1; - __IO uint32_t IC02S1 : 1; - __IO uint32_t IC02S2 : 1; - __IO uint32_t IC03S0 : 1; - __IO uint32_t IC03S1 : 1; - __IO uint32_t IC03S2 : 1; -} stc_gpio_epfr01_field_t; - -typedef struct stc_gpio_epfr02_field -{ - __IO uint32_t RTO10E0 : 1; - __IO uint32_t RTO10E1 : 1; - __IO uint32_t RTO11E0 : 1; - __IO uint32_t RTO11E1 : 1; - __IO uint32_t RTO12E0 : 1; - __IO uint32_t RTO12E1 : 1; - __IO uint32_t RTO13E0 : 1; - __IO uint32_t RTO13E1 : 1; - __IO uint32_t RTO14E0 : 1; - __IO uint32_t RTO14E1 : 1; - __IO uint32_t RTO15E0 : 1; - __IO uint32_t RTO15E1 : 1; - __IO uint32_t DTTI1C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI1S0 : 1; - __IO uint32_t DTTI1S1 : 1; - __IO uint32_t FRCK1S0 : 1; - __IO uint32_t FRCK1S1 : 1; - __IO uint32_t IC10S0 : 1; - __IO uint32_t IC10S1 : 1; - __IO uint32_t IC10S2 : 1; - __IO uint32_t IC11S0 : 1; - __IO uint32_t IC11S1 : 1; - __IO uint32_t IC11S2 : 1; - __IO uint32_t IC12S0 : 1; - __IO uint32_t IC12S1 : 1; - __IO uint32_t IC12S2 : 1; - __IO uint32_t IC13S0 : 1; - __IO uint32_t IC13S1 : 1; - __IO uint32_t IC13S2 : 1; -} stc_gpio_epfr02_field_t; - -typedef struct stc_gpio_epfr03_field -{ - __IO uint32_t RTO20E0 : 1; - __IO uint32_t RTO20E1 : 1; - __IO uint32_t RTO21E0 : 1; - __IO uint32_t RTO21E1 : 1; - __IO uint32_t RTO22E0 : 1; - __IO uint32_t RTO22E1 : 1; - __IO uint32_t RTO23E0 : 1; - __IO uint32_t RTO23E1 : 1; - __IO uint32_t RTO24E0 : 1; - __IO uint32_t RTO24E1 : 1; - __IO uint32_t RTO25E0 : 1; - __IO uint32_t RTO25E1 : 1; - __IO uint32_t DTTI2C : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t DTTI2S0 : 1; - __IO uint32_t DTTI2S1 : 1; - __IO uint32_t FRCK2S0 : 1; - __IO uint32_t FRCK2S1 : 1; - __IO uint32_t IC20S0 : 1; - __IO uint32_t IC20S1 : 1; - __IO uint32_t IC20S2 : 1; - __IO uint32_t IC21S0 : 1; - __IO uint32_t IC21S1 : 1; - __IO uint32_t IC21S2 : 1; - __IO uint32_t IC22S0 : 1; - __IO uint32_t IC22S1 : 1; - __IO uint32_t IC22S2 : 1; - __IO uint32_t IC23S0 : 1; - __IO uint32_t IC23S1 : 1; - __IO uint32_t IC23S2 : 1; -} stc_gpio_epfr03_field_t; - -typedef struct stc_gpio_epfr04_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA0E0 : 1; - __IO uint32_t TIOA0E1 : 1; - __IO uint32_t TIOB0S0 : 1; - __IO uint32_t TIOB0S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA1S0 : 1; - __IO uint32_t TIOA1S1 : 1; - __IO uint32_t TIOA1E0 : 1; - __IO uint32_t TIOA1E1 : 1; - __IO uint32_t TIOB1S0 : 1; - __IO uint32_t TIOB1S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA2E0 : 1; - __IO uint32_t TIOA2E1 : 1; - __IO uint32_t TIOB2S0 : 1; - __IO uint32_t TIOB2S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA3S0 : 1; - __IO uint32_t TIOA3S1 : 1; - __IO uint32_t TIOA3E0 : 1; - __IO uint32_t TIOA3E1 : 1; - __IO uint32_t TIOB3S0 : 1; - __IO uint32_t TIOB3S1 : 1; -} stc_gpio_epfr04_field_t; - -typedef struct stc_gpio_epfr05_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA4E0 : 1; - __IO uint32_t TIOA4E1 : 1; - __IO uint32_t TIOB4S0 : 1; - __IO uint32_t TIOB4S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA5S0 : 1; - __IO uint32_t TIOA5S1 : 1; - __IO uint32_t TIOA5E0 : 1; - __IO uint32_t TIOA5E1 : 1; - __IO uint32_t TIOB5S0 : 1; - __IO uint32_t TIOB5S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA6E0 : 1; - __IO uint32_t TIOA6E1 : 1; - __IO uint32_t TIOB6S0 : 1; - __IO uint32_t TIOB6S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA7S0 : 1; - __IO uint32_t TIOA7S1 : 1; - __IO uint32_t TIOA7E0 : 1; - __IO uint32_t TIOA7E1 : 1; - __IO uint32_t TIOB7S0 : 1; - __IO uint32_t TIOB7S1 : 1; -} stc_gpio_epfr05_field_t; - -typedef struct stc_gpio_epfr06_field -{ - __IO uint32_t EINT00S0 : 1; - __IO uint32_t EINT00S1 : 1; - __IO uint32_t EINT01S0 : 1; - __IO uint32_t EINT01S1 : 1; - __IO uint32_t EINT02S0 : 1; - __IO uint32_t EINT02S1 : 1; - __IO uint32_t EINT03S0 : 1; - __IO uint32_t EINT03S1 : 1; - __IO uint32_t EINT04S0 : 1; - __IO uint32_t EINT04S1 : 1; - __IO uint32_t EINT05S0 : 1; - __IO uint32_t EINT05S1 : 1; - __IO uint32_t EINT06S0 : 1; - __IO uint32_t EINT06S1 : 1; - __IO uint32_t EINT07S0 : 1; - __IO uint32_t EINT07S1 : 1; - __IO uint32_t EINT08S0 : 1; - __IO uint32_t EINT08S1 : 1; - __IO uint32_t EINT09S0 : 1; - __IO uint32_t EINT09S1 : 1; - __IO uint32_t EINT10S0 : 1; - __IO uint32_t EINT10S1 : 1; - __IO uint32_t EINT11S0 : 1; - __IO uint32_t EINT11S1 : 1; - __IO uint32_t EINT12S0 : 1; - __IO uint32_t EINT12S1 : 1; - __IO uint32_t EINT13S0 : 1; - __IO uint32_t EINT13S1 : 1; - __IO uint32_t EINT14S0 : 1; - __IO uint32_t EINT14S1 : 1; - __IO uint32_t EINT15S0 : 1; - __IO uint32_t EINT15S1 : 1; -} stc_gpio_epfr06_field_t; - -typedef struct stc_gpio_epfr07_field -{ - uint32_t RESERVED1 : 4; - __IO uint32_t SIN0S0 : 1; - __IO uint32_t SIN0S1 : 1; - __IO uint32_t SOT0B0 : 1; - __IO uint32_t SOT0B1 : 1; - __IO uint32_t SCK0B0 : 1; - __IO uint32_t SCK0B1 : 1; - __IO uint32_t SIN1S0 : 1; - __IO uint32_t SIN1S1 : 1; - __IO uint32_t SOT1B0 : 1; - __IO uint32_t SOT1B1 : 1; - __IO uint32_t SCK1B0 : 1; - __IO uint32_t SCK1B1 : 1; - __IO uint32_t SIN2S0 : 1; - __IO uint32_t SIN2S1 : 1; - __IO uint32_t SOT2B0 : 1; - __IO uint32_t SOT2B1 : 1; - __IO uint32_t SCK2B0 : 1; - __IO uint32_t SCK2B1 : 1; - __IO uint32_t SIN3S0 : 1; - __IO uint32_t SIN3S1 : 1; - __IO uint32_t SOT3B0 : 1; - __IO uint32_t SOT3B1 : 1; - __IO uint32_t SCK3B0 : 1; - __IO uint32_t SCK3B1 : 1; -} stc_gpio_epfr07_field_t; - -typedef struct stc_gpio_epfr08_field -{ - __IO uint32_t RTS4E0 : 1; - __IO uint32_t RTS4E1 : 1; - __IO uint32_t CTS4S0 : 1; - __IO uint32_t CTS4S1 : 1; - __IO uint32_t SIN4S0 : 1; - __IO uint32_t SIN4S1 : 1; - __IO uint32_t SOT4B0 : 1; - __IO uint32_t SOT4B1 : 1; - __IO uint32_t SCK4B0 : 1; - __IO uint32_t SCK4B1 : 1; - __IO uint32_t SIN5S0 : 1; - __IO uint32_t SIN5S1 : 1; - __IO uint32_t SOT5B0 : 1; - __IO uint32_t SOT5B1 : 1; - __IO uint32_t SCK5B0 : 1; - __IO uint32_t SCK5B1 : 1; - __IO uint32_t SIN6S0 : 1; - __IO uint32_t SIN6S1 : 1; - __IO uint32_t SOT6B0 : 1; - __IO uint32_t SOT6B1 : 1; - __IO uint32_t SCK6B0 : 1; - __IO uint32_t SCK6B1 : 1; - __IO uint32_t SIN7S0 : 1; - __IO uint32_t SIN7S1 : 1; - __IO uint32_t SOT7B0 : 1; - __IO uint32_t SOT7B1 : 1; - __IO uint32_t SCK7B0 : 1; - __IO uint32_t SCK7B1 : 1; -} stc_gpio_epfr08_field_t; - -typedef struct stc_gpio_epfr09_field -{ - __IO uint32_t QAIN0S0 : 1; - __IO uint32_t QAIN0S1 : 1; - __IO uint32_t QBIN0S0 : 1; - __IO uint32_t QBIN0S1 : 1; - __IO uint32_t QZIN0S0 : 1; - __IO uint32_t QZIN0S1 : 1; - __IO uint32_t QAIN1S0 : 1; - __IO uint32_t QAIN1S1 : 1; - __IO uint32_t QBIN1S0 : 1; - __IO uint32_t QBIN1S1 : 1; - __IO uint32_t QZIN1S0 : 1; - __IO uint32_t QZIN1S1 : 1; - __IO uint32_t ADTRG0S0 : 1; - __IO uint32_t ADTRG0S1 : 1; - __IO uint32_t ADTRG0S2 : 1; - __IO uint32_t ADTRG0S3 : 1; - __IO uint32_t ADTRG1S0 : 1; - __IO uint32_t ADTRG1S1 : 1; - __IO uint32_t ADTRG1S2 : 1; - __IO uint32_t ADTRG1S3 : 1; - __IO uint32_t ADTRG2S0 : 1; - __IO uint32_t ADTRG2S1 : 1; - __IO uint32_t ADTRG2S2 : 1; - __IO uint32_t ADTRG2S3 : 1; -} stc_gpio_epfr09_field_t; - -typedef struct stc_gpio_epfr10_field -{ - __IO uint32_t UEDEFB : 1; - __IO uint32_t UEDTHB : 1; - __IO uint32_t UECLKE : 1; - __IO uint32_t UEWEXE : 1; - __IO uint32_t UEDQME : 1; - __IO uint32_t UEOEXE : 1; - __IO uint32_t UEFLSE : 1; - __IO uint32_t UECS1E : 1; - __IO uint32_t UECS2E : 1; - __IO uint32_t UECS3E : 1; - __IO uint32_t UECS4E : 1; - __IO uint32_t UECS5E : 1; - __IO uint32_t UECS6E : 1; - __IO uint32_t UECS7E : 1; - __IO uint32_t UEAOOE : 1; - __IO uint32_t UEA08E : 1; - __IO uint32_t UEA09E : 1; - __IO uint32_t UEA10E : 1; - __IO uint32_t UEA11E : 1; - __IO uint32_t UEA12E : 1; - __IO uint32_t UEA13E : 1; - __IO uint32_t UEA14E : 1; - __IO uint32_t UEA15E : 1; - __IO uint32_t UEA16E : 1; - __IO uint32_t UEA17E : 1; - __IO uint32_t UEA18E : 1; - __IO uint32_t UEA19E : 1; - __IO uint32_t UEA20E : 1; - __IO uint32_t UEA21E : 1; - __IO uint32_t UEA22E : 1; - __IO uint32_t UEA23E : 1; - __IO uint32_t UEA24E : 1; -} stc_gpio_epfr10_field_t; - -typedef struct stc_gpio_epfr11_field -{ - __IO uint32_t UEALEE : 1; - __IO uint32_t UECS0E : 1; - __IO uint32_t UEA01E : 1; - __IO uint32_t UEA02E : 1; - __IO uint32_t UEA03E : 1; - __IO uint32_t UEA04E : 1; - __IO uint32_t UEA05E : 1; - __IO uint32_t UEA06E : 1; - __IO uint32_t UEA07E : 1; - __IO uint32_t UED00B : 1; - __IO uint32_t UED01B : 1; - __IO uint32_t UED02B : 1; - __IO uint32_t UED03B : 1; - __IO uint32_t UED04B : 1; - __IO uint32_t UED05B : 1; - __IO uint32_t UED06B : 1; - __IO uint32_t UED07B : 1; - __IO uint32_t UED08B : 1; - __IO uint32_t UED09B : 1; - __IO uint32_t UED10B : 1; - __IO uint32_t UED11B : 1; - __IO uint32_t UED12B : 1; - __IO uint32_t UED13B : 1; - __IO uint32_t UED14B : 1; - __IO uint32_t UED15B : 1; - __IO uint32_t UERLC : 1; -} stc_gpio_epfr11_field_t; - -typedef struct stc_gpio_epfr12_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA8E0 : 1; - __IO uint32_t TIOA8E1 : 1; - __IO uint32_t TIOB8S0 : 1; - __IO uint32_t TIOB8S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA9S0 : 1; - __IO uint32_t TIOA9S1 : 1; - __IO uint32_t TIOA9E0 : 1; - __IO uint32_t TIOA9E1 : 1; - __IO uint32_t TIOB9S0 : 1; - __IO uint32_t TIOB9S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA10E0 : 1; - __IO uint32_t TIOA10E1 : 1; - __IO uint32_t TIOB10S0 : 1; - __IO uint32_t TIOB10S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA11S0 : 1; - __IO uint32_t TIOA11S1 : 1; - __IO uint32_t TIOA11E0 : 1; - __IO uint32_t TIOA11E1 : 1; - __IO uint32_t TIOB11S0 : 1; - __IO uint32_t TIOB11S1 : 1; -} stc_gpio_epfr12_field_t; - -typedef struct stc_gpio_epfr13_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t TIOA12E0 : 1; - __IO uint32_t TIOA12E1 : 1; - __IO uint32_t TIOB12S0 : 1; - __IO uint32_t TIOB12S1 : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t TIOA13S0 : 1; - __IO uint32_t TIOA13S1 : 1; - __IO uint32_t TIOA13E0 : 1; - __IO uint32_t TIOA13E1 : 1; - __IO uint32_t TIOB13S0 : 1; - __IO uint32_t TIOB13S1 : 1; - uint32_t RESERVED3 : 4; - __IO uint32_t TIOA14E0 : 1; - __IO uint32_t TIOA14E1 : 1; - __IO uint32_t TIOB14S0 : 1; - __IO uint32_t TIOB14S1 : 1; - uint32_t RESERVED4 : 2; - __IO uint32_t TIOA15S0 : 1; - __IO uint32_t TIOA15S1 : 1; - __IO uint32_t TIOA15E0 : 1; - __IO uint32_t TIOA15E1 : 1; - __IO uint32_t TIOB15S0 : 1; - __IO uint32_t TIOB15S1 : 1; -} stc_gpio_epfr13_field_t; - -typedef struct stc_gpio_epfr14_field -{ - __IO uint32_t QAIN2S0 : 1; - __IO uint32_t QAIN2S1 : 1; - __IO uint32_t QBIN2S0 : 1; - __IO uint32_t QBIN2S1 : 1; - __IO uint32_t QZIN2S0 : 1; - __IO uint32_t QZIN2S1 : 1; - uint32_t RESERVED1 : 12; - __IO uint32_t E_TD0E : 1; - __IO uint32_t E_TD1E : 1; - __IO uint32_t E_TE0E : 1; - __IO uint32_t E_TE1E : 1; - __IO uint32_t E_MC0E : 1; - __IO uint32_t E_MC1B : 1; - __IO uint32_t E_MD0B : 1; - __IO uint32_t E_MD1B : 1; - __IO uint32_t E_CKE : 1; - __IO uint32_t E_PSE : 1; - __IO uint32_t E_SPLC0 : 1; - __IO uint32_t E_SPLC1 : 1; -} stc_gpio_epfr14_field_t; - -typedef struct stc_gpio_epfr15_field -{ - __IO uint32_t EINT16S0 : 1; - __IO uint32_t EINT16S1 : 1; - __IO uint32_t EINT17S0 : 1; - __IO uint32_t EINT17S1 : 1; - __IO uint32_t EINT18S0 : 1; - __IO uint32_t EINT18S1 : 1; - __IO uint32_t EINT19S0 : 1; - __IO uint32_t EINT19S1 : 1; - __IO uint32_t EINT20S0 : 1; - __IO uint32_t EINT20S1 : 1; - __IO uint32_t EINT21S0 : 1; - __IO uint32_t EINT21S1 : 1; - __IO uint32_t EINT22S0 : 1; - __IO uint32_t EINT22S1 : 1; - __IO uint32_t EINT23S0 : 1; - __IO uint32_t EINT23S1 : 1; - __IO uint32_t EINT24S0 : 1; - __IO uint32_t EINT24S1 : 1; - __IO uint32_t EINT25S0 : 1; - __IO uint32_t EINT25S1 : 1; - __IO uint32_t EINT26S0 : 1; - __IO uint32_t EINT26S1 : 1; - __IO uint32_t EINT27S0 : 1; - __IO uint32_t EINT27S1 : 1; - __IO uint32_t EINT28S0 : 1; - __IO uint32_t EINT28S1 : 1; - __IO uint32_t EINT29S0 : 1; - __IO uint32_t EINT29S1 : 1; - __IO uint32_t EINT30S0 : 1; - __IO uint32_t EINT30S1 : 1; - __IO uint32_t EINT31S0 : 1; - __IO uint32_t EINT31S1 : 1; -} stc_gpio_epfr15_field_t; - -typedef struct stc_gpio_pzr0_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pzr0_field_t; - -typedef struct stc_gpio_pzr1_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzr1_field_t; - -typedef struct stc_gpio_pzr2_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; -} stc_gpio_pzr2_field_t; - -typedef struct stc_gpio_pzr3_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzr3_field_t; - -typedef struct stc_gpio_pzr4_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; -} stc_gpio_pzr4_field_t; - -typedef struct stc_gpio_pzr5_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; -} stc_gpio_pzr5_field_t; - -typedef struct stc_gpio_pzr6_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; -} stc_gpio_pzr6_field_t; - -typedef struct stc_gpio_pzr7_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzr7_field_t; - -typedef struct stc_gpio_pzr8_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzr8_field_t; - -typedef struct stc_gpio_pzr9_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pzr9_field_t; - -typedef struct stc_gpio_pzra_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; -} stc_gpio_pzra_field_t; - -typedef struct stc_gpio_pzrb_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; -} stc_gpio_pzrb_field_t; - -typedef struct stc_gpio_pzrc_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; - __IO uint32_t P7 : 1; - __IO uint32_t P8 : 1; - __IO uint32_t P9 : 1; - __IO uint32_t PA : 1; - __IO uint32_t PB : 1; - __IO uint32_t PC : 1; - __IO uint32_t PD : 1; - __IO uint32_t PE : 1; - __IO uint32_t PF : 1; -} stc_gpio_pzrc_field_t; - -typedef struct stc_gpio_pzrd_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzrd_field_t; - -typedef struct stc_gpio_pzre_field -{ - __IO uint32_t P0 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; -} stc_gpio_pzre_field_t; - -typedef struct stc_gpio_pzrf_field -{ - __IO uint32_t P0 : 1; - __IO uint32_t P1 : 1; - __IO uint32_t P2 : 1; - __IO uint32_t P3 : 1; - __IO uint32_t P4 : 1; - __IO uint32_t P5 : 1; - __IO uint32_t P6 : 1; -} stc_gpio_pzrf_field_t; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* LVD_MODULE register bit fields */ -typedef struct stc_lvd_lvd_ctl_field -{ - uint8_t RESERVED1 : 2; - __IO uint8_t SVHI0 : 1; - __IO uint8_t SVHI1 : 1; - __IO uint8_t SVHI2 : 1; - __IO uint8_t SVHI3 : 1; - uint8_t RESERVED2 : 1; - __IO uint8_t LVDIE : 1; -} stc_lvd_lvd_ctl_field_t; - -typedef struct stc_lvd_lvd_str_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIR : 1; -} stc_lvd_lvd_str_field_t; - -typedef struct stc_lvd_lvd_clr_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDCL : 1; -} stc_lvd_lvd_clr_field_t; - -typedef struct stc_lvd_lvd_str2_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t LVDIRDY : 1; -} stc_lvd_lvd_str2_field_t; - -/****************************************************************************** - * USB Ethernet CLK - ******************************************************************************/ -/* USB ETHERNET CLK register bit fields */ -typedef struct stc_usbethernetclk_uccr_field -{ - __IO uint8_t UCEN0 : 1; - __IO uint8_t UCSEL0 : 1; - __IO uint8_t UCSEL1 : 1; - __IO uint8_t UCEN1 : 1; - __IO uint8_t ECEN : 1; - __IO uint8_t ECSEL0 : 1; - __IO uint8_t ECSEL1 : 1; -} stc_usbethernetclk_uccr_field_t; - -typedef struct stc_usbethernetclk_upcr1_field -{ - __IO uint8_t UPLLEN : 1; - __IO uint8_t UPINC : 1; -} stc_usbethernetclk_upcr1_field_t; - -typedef struct stc_usbethernetclk_upcr2_field -{ - __IO uint8_t UPOWT0 : 1; - __IO uint8_t UPOWT1 : 1; - __IO uint8_t UPOWT2 : 1; -} stc_usbethernetclk_upcr2_field_t; - -typedef struct stc_usbethernetclk_upcr3_field -{ - __IO uint8_t UPLLK0 : 1; - __IO uint8_t UPLLK1 : 1; - __IO uint8_t UPLLK2 : 1; - __IO uint8_t UPLLK3 : 1; - __IO uint8_t UPLLK4 : 1; -} stc_usbethernetclk_upcr3_field_t; - -typedef struct stc_usbethernetclk_upcr4_field -{ - __IO uint8_t UPLLN0 : 1; - __IO uint8_t UPLLN1 : 1; - __IO uint8_t UPLLN2 : 1; - __IO uint8_t UPLLN3 : 1; - __IO uint8_t UPLLN4 : 1; - __IO uint8_t UPLLN5 : 1; - __IO uint8_t UPLLN6 : 1; -} stc_usbethernetclk_upcr4_field_t; - -typedef struct stc_usbethernetclk_up_str_field -{ - __IO uint8_t UPRDY : 1; -} stc_usbethernetclk_up_str_field_t; - -typedef struct stc_usbethernetclk_upint_enr_field -{ - __IO uint8_t UPCSE : 1; -} stc_usbethernetclk_upint_enr_field_t; - -typedef struct stc_usbethernetclk_upint_clr_field -{ - __IO uint8_t UPCSC : 1; -} stc_usbethernetclk_upint_clr_field_t; - -typedef struct stc_usbethernetclk_upint_str_field -{ - __IO uint8_t UPCSI : 1; -} stc_usbethernetclk_upint_str_field_t; - -typedef struct stc_usbethernetclk_upcr5_field -{ - __IO uint8_t UPLLM0 : 1; - __IO uint8_t UPLLM1 : 1; - __IO uint8_t UPLLM2 : 1; - __IO uint8_t UPLLM3 : 1; -} stc_usbethernetclk_upcr5_field_t; - -typedef struct stc_usbethernetclk_upcr6_field -{ - __IO uint8_t UBSR0 : 1; - __IO uint8_t UBSR1 : 1; - __IO uint8_t UBSR2 : 1; - __IO uint8_t UBSR3 : 1; -} stc_usbethernetclk_upcr6_field_t; - -typedef struct stc_usbethernetclk_upcr7_field -{ - __IO uint8_t EPLLEN : 1; -} stc_usbethernetclk_upcr7_field_t; - -typedef struct stc_usbethernetclk_usben0_field -{ - __IO uint8_t USBEN0 : 1; -} stc_usbethernetclk_usben0_field_t; - -typedef struct stc_usbethernetclk_usben1_field -{ - __IO uint8_t USBEN1 : 1; -} stc_usbethernetclk_usben1_field_t; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* MFS03_UART_MODULE register bit fields */ -typedef struct stc_mfs03_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs03_uart_smr_field_t; - -typedef struct stc_mfs03_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs03_uart_scr_field_t; - -typedef struct stc_mfs03_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs03_uart_escr_field_t; - -typedef struct stc_mfs03_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_uart_ssr_field_t; - -typedef struct stc_mfs03_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_rdr_field_t; - -typedef struct stc_mfs03_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs03_uart_tdr_field_t; - -typedef struct stc_mfs03_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_uart_bgr_field_t; - -typedef struct stc_mfs03_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_uart_bgr1_field_t; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* MFS03_CSIO_MODULE register bit fields */ -typedef struct stc_mfs03_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs03_csio_smr_field_t; - -typedef struct stc_mfs03_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_csio_scr_field_t; - -typedef struct stc_mfs03_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs03_csio_escr_field_t; - -typedef struct stc_mfs03_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs03_csio_ssr_field_t; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* MFS03_LIN_MODULE register bit fields */ -typedef struct stc_mfs03_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs03_lin_smr_field_t; - -typedef struct stc_mfs03_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs03_lin_scr_field_t; - -typedef struct stc_mfs03_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs03_lin_escr_field_t; - -typedef struct stc_mfs03_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs03_lin_ssr_field_t; - -typedef struct stc_mfs03_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs03_lin_bgr_field_t; - -typedef struct stc_mfs03_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs03_lin_bgr1_field_t; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* MFS03_I2C_MODULE register bit fields */ -typedef struct stc_mfs03_i2c_smr_field -{ - uint8_t RESERVED1 : 2; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs03_i2c_smr_field_t; - -typedef struct stc_mfs03_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs03_i2c_ibcr_field_t; - -typedef struct stc_mfs03_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs03_i2c_ibsr_field_t; - -typedef struct stc_mfs03_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs03_i2c_ssr_field_t; - -typedef struct stc_mfs03_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs03_i2c_isba_field_t; - -typedef struct stc_mfs03_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs03_i2c_ismk_field_t; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* MFS47_UART_MODULE register bit fields */ -typedef struct stc_mfs47_uart_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs47_uart_smr_field_t; - -typedef struct stc_mfs47_uart_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t UPCL : 1; -} stc_mfs47_uart_scr_field_t; - -typedef struct stc_mfs47_uart_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t P : 1; - __IO uint8_t PEN : 1; - __IO uint8_t INV : 1; - __IO uint8_t ESBL : 1; - __IO uint8_t FLWEN : 1; -} stc_mfs47_uart_escr_field_t; - -typedef struct stc_mfs47_uart_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t PE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_uart_ssr_field_t; - -typedef struct stc_mfs47_uart_rdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_rdr_field_t; - -typedef struct stc_mfs47_uart_tdr_field -{ - uint16_t RESERVED1 : 8; - __IO uint16_t AD : 1; -} stc_mfs47_uart_tdr_field_t; - -typedef struct stc_mfs47_uart_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_uart_bgr_field_t; - -typedef struct stc_mfs47_uart_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_uart_bgr1_field_t; - -typedef struct stc_mfs47_uart_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_uart_fcr_field_t; - -typedef struct stc_mfs47_uart_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_uart_fcr0_field_t; - -typedef struct stc_mfs47_uart_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_uart_fcr1_field_t; - -typedef struct stc_mfs47_uart_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_uart_fbyte_field_t; - -typedef struct stc_mfs47_uart_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_uart_fbyte1_field_t; - -typedef struct stc_mfs47_uart_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_uart_fbyte2_field_t; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* MFS47_CSIO_MODULE register bit fields */ -typedef struct stc_mfs47_csio_smr_field -{ - __IO uint8_t SOE : 1; - __IO uint8_t SCKE : 1; - __IO uint8_t BDS : 1; - __IO uint8_t SCINV : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs47_csio_smr_field_t; - -typedef struct stc_mfs47_csio_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t SPI : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_csio_scr_field_t; - -typedef struct stc_mfs47_csio_escr_field -{ - __IO uint8_t L0 : 1; - __IO uint8_t L1 : 1; - __IO uint8_t L2 : 1; - __IO uint8_t WT0 : 1; - __IO uint8_t WT1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SOP : 1; -} stc_mfs47_csio_escr_field_t; - -typedef struct stc_mfs47_csio_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - uint8_t RESERVED1 : 3; - __IO uint8_t REC : 1; -} stc_mfs47_csio_ssr_field_t; - -typedef struct stc_mfs47_csio_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_csio_fcr_field_t; - -typedef struct stc_mfs47_csio_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_csio_fcr0_field_t; - -typedef struct stc_mfs47_csio_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_csio_fcr1_field_t; - -typedef struct stc_mfs47_csio_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_csio_fbyte_field_t; - -typedef struct stc_mfs47_csio_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_csio_fbyte1_field_t; - -typedef struct stc_mfs47_csio_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_csio_fbyte2_field_t; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* MFS47_LIN_MODULE register bit fields */ -typedef struct stc_mfs47_lin_smr_field -{ - __IO uint8_t SOE : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t SBL : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs47_lin_smr_field_t; - -typedef struct stc_mfs47_lin_scr_field -{ - __IO uint8_t TXE : 1; - __IO uint8_t RXE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t LBR : 1; - __IO uint8_t MS : 1; - __IO uint8_t UPCL : 1; -} stc_mfs47_lin_scr_field_t; - -typedef struct stc_mfs47_lin_escr_field -{ - __IO uint8_t DEL0 : 1; - __IO uint8_t DEL1 : 1; - __IO uint8_t LBL0 : 1; - __IO uint8_t LBL1 : 1; - __IO uint8_t LBIE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t ESBL : 1; -} stc_mfs47_lin_escr_field_t; - -typedef struct stc_mfs47_lin_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t FRE : 1; - __IO uint8_t LBD : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t REC : 1; -} stc_mfs47_lin_ssr_field_t; - -typedef struct stc_mfs47_lin_bgr_field -{ - uint16_t RESERVED1 : 15; - __IO uint16_t EXT : 1; -} stc_mfs47_lin_bgr_field_t; - -typedef struct stc_mfs47_lin_bgr1_field -{ - uint8_t RESERVED1 : 7; - __IO uint8_t EXT : 1; -} stc_mfs47_lin_bgr1_field_t; - -typedef struct stc_mfs47_lin_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_lin_fcr_field_t; - -typedef struct stc_mfs47_lin_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_lin_fcr0_field_t; - -typedef struct stc_mfs47_lin_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_lin_fcr1_field_t; - -typedef struct stc_mfs47_lin_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_lin_fbyte_field_t; - -typedef struct stc_mfs47_lin_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_lin_fbyte1_field_t; - -typedef struct stc_mfs47_lin_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_lin_fbyte2_field_t; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* MFS47_I2C_MODULE register bit fields */ -typedef struct stc_mfs47_i2c_smr_field -{ - uint8_t RESERVED1 : 2; - __IO uint8_t TIE : 1; - __IO uint8_t RIE : 1; - __IO uint8_t WUCR : 1; - __IO uint8_t MD : 3; -} stc_mfs47_i2c_smr_field_t; - -typedef struct stc_mfs47_i2c_ibcr_field -{ - __IO uint8_t INT : 1; - __IO uint8_t BER : 1; - __IO uint8_t INTE : 1; - __IO uint8_t CNDE : 1; - __IO uint8_t WSEL : 1; - __IO uint8_t ACKE : 1; - __IO uint8_t SCC : 1; - __IO uint8_t MSS : 1; -} stc_mfs47_i2c_ibcr_field_t; - -typedef struct stc_mfs47_i2c_ibsr_field -{ - __IO uint8_t BB : 1; - __IO uint8_t SPC : 1; - __IO uint8_t RSC : 1; - __IO uint8_t AL : 1; - __IO uint8_t TRX : 1; - __IO uint8_t RSA : 1; - __IO uint8_t RACK : 1; - __IO uint8_t FBT : 1; -} stc_mfs47_i2c_ibsr_field_t; - -typedef struct stc_mfs47_i2c_ssr_field -{ - __IO uint8_t TBI : 1; - __IO uint8_t TDRE : 1; - __IO uint8_t RDRF : 1; - __IO uint8_t ORE : 1; - __IO uint8_t TBIE : 1; - __IO uint8_t DMA : 1; - __IO uint8_t TSET : 1; - __IO uint8_t REC : 1; -} stc_mfs47_i2c_ssr_field_t; - -typedef struct stc_mfs47_i2c_isba_field -{ - __IO uint8_t SA0 : 1; - __IO uint8_t SA1 : 1; - __IO uint8_t SA2 : 1; - __IO uint8_t SA3 : 1; - __IO uint8_t SA4 : 1; - __IO uint8_t SA5 : 1; - __IO uint8_t SA6 : 1; - __IO uint8_t SAEN : 1; -} stc_mfs47_i2c_isba_field_t; - -typedef struct stc_mfs47_i2c_ismk_field -{ - __IO uint8_t SM0 : 1; - __IO uint8_t SM1 : 1; - __IO uint8_t SM2 : 1; - __IO uint8_t SM3 : 1; - __IO uint8_t SM4 : 1; - __IO uint8_t SM5 : 1; - __IO uint8_t SM6 : 1; - __IO uint8_t EN : 1; -} stc_mfs47_i2c_ismk_field_t; - -typedef struct stc_mfs47_i2c_fcr_field -{ - __IO uint16_t FE1 : 1; - __IO uint16_t FE2 : 1; - __IO uint16_t FCL1 : 1; - __IO uint16_t FCL2 : 1; - __IO uint16_t FSET : 1; - __IO uint16_t FLD : 1; - __IO uint16_t FLST : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t FSEL : 1; - __IO uint16_t FTIE : 1; - __IO uint16_t FDRQ : 1; - __IO uint16_t FRIE : 1; - __IO uint16_t FLSTE : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t FTST0 : 1; - __IO uint16_t FTST1 : 1; -} stc_mfs47_i2c_fcr_field_t; - -typedef struct stc_mfs47_i2c_fcr0_field -{ - __IO uint8_t FE1 : 1; - __IO uint8_t FE2 : 1; - __IO uint8_t FCL1 : 1; - __IO uint8_t FCL2 : 1; - __IO uint8_t FSET : 1; - __IO uint8_t FLD : 1; - __IO uint8_t FLST : 1; -} stc_mfs47_i2c_fcr0_field_t; - -typedef struct stc_mfs47_i2c_fcr1_field -{ - __IO uint8_t FSEL : 1; - __IO uint8_t FTIE : 1; - __IO uint8_t FDRQ : 1; - __IO uint8_t FRIE : 1; - __IO uint8_t FLSTE : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t FTST0 : 1; - __IO uint8_t FTST1 : 1; -} stc_mfs47_i2c_fcr1_field_t; - -typedef struct stc_mfs47_i2c_fbyte_field -{ - __IO uint16_t FD0 : 1; - __IO uint16_t FD1 : 1; - __IO uint16_t FD2 : 1; - __IO uint16_t FD3 : 1; - __IO uint16_t FD4 : 1; - __IO uint16_t FD5 : 1; - __IO uint16_t FD6 : 1; - __IO uint16_t FD7 : 1; - __IO uint16_t FD8 : 1; - __IO uint16_t FD9 : 1; - __IO uint16_t FD10 : 1; - __IO uint16_t FD11 : 1; - __IO uint16_t FD12 : 1; - __IO uint16_t FD13 : 1; - __IO uint16_t FD14 : 1; - __IO uint16_t FD15 : 1; -} stc_mfs47_i2c_fbyte_field_t; - -typedef struct stc_mfs47_i2c_fbyte1_field -{ - __IO uint8_t FD0 : 1; - __IO uint8_t FD1 : 1; - __IO uint8_t FD2 : 1; - __IO uint8_t FD3 : 1; - __IO uint8_t FD4 : 1; - __IO uint8_t FD5 : 1; - __IO uint8_t FD6 : 1; - __IO uint8_t FD7 : 1; -} stc_mfs47_i2c_fbyte1_field_t; - -typedef struct stc_mfs47_i2c_fbyte2_field -{ - __IO uint8_t FD8 : 1; - __IO uint8_t FD9 : 1; - __IO uint8_t FD10 : 1; - __IO uint8_t FD11 : 1; - __IO uint8_t FD12 : 1; - __IO uint8_t FD13 : 1; - __IO uint8_t FD14 : 1; - __IO uint8_t FD15 : 1; -} stc_mfs47_i2c_fbyte2_field_t; - -/****************************************************************************** - * MFS_NFC_MODULE - ******************************************************************************/ -/* MFS_NFC_MODULE register bit fields */ -typedef struct stc_mfs_nfc_i2cdnf_field -{ - __IO uint16_t I2CDNF00 : 1; - __IO uint16_t I2CDNF01 : 1; - __IO uint16_t I2CDNF10 : 1; - __IO uint16_t I2CDNF11 : 1; - __IO uint16_t I2CDNF20 : 1; - __IO uint16_t I2CDNF21 : 1; - __IO uint16_t I2CDNF30 : 1; - __IO uint16_t I2CDNF31 : 1; - __IO uint16_t I2CDNF40 : 1; - __IO uint16_t I2CDNF41 : 1; - __IO uint16_t I2CDNF50 : 1; - __IO uint16_t I2CDNF51 : 1; - __IO uint16_t I2CDNF60 : 1; - __IO uint16_t I2CDNF61 : 1; - __IO uint16_t I2CDNF70 : 1; - __IO uint16_t I2CDNF71 : 1; -} stc_mfs_nfc_i2cdnf_field_t; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC_MODULE register bit fields */ -typedef struct stc_crc_crccr_field -{ - __IO uint8_t INIT : 1; - __IO uint8_t CRC32 : 1; - __IO uint8_t LTLEND : 1; - __IO uint8_t LSBFST : 1; - __IO uint8_t CRCLTE : 1; - __IO uint8_t CRCLSF : 1; - __IO uint8_t FXOR : 1; -} stc_crc_crccr_field_t; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* WC_MODULE register bit fields */ -typedef struct stc_wc_wcrd_field -{ - __IO uint8_t CTR0 : 1; - __IO uint8_t CTR1 : 1; - __IO uint8_t CTR2 : 1; - __IO uint8_t CTR3 : 1; - __IO uint8_t CTR4 : 1; - __IO uint8_t CTR5 : 1; -} stc_wc_wcrd_field_t; - -typedef struct stc_wc_wcrl_field -{ - __IO uint8_t RLC0 : 1; - __IO uint8_t RLC1 : 1; - __IO uint8_t RLC2 : 1; - __IO uint8_t RLC3 : 1; - __IO uint8_t RLC4 : 1; - __IO uint8_t RLC5 : 1; -} stc_wc_wcrl_field_t; - -typedef struct stc_wc_wccr_field -{ - __IO uint8_t WCIF : 1; - __IO uint8_t WCIE : 1; - __IO uint8_t CS0 : 1; - __IO uint8_t CS1 : 1; - uint8_t RESERVED1 : 2; - __IO uint8_t WCOP : 1; - __IO uint8_t WCEN : 1; -} stc_wc_wccr_field_t; - -typedef struct stc_wc_clk_sel_field -{ - __IO uint16_t SEL_IN : 1; - uint16_t RESERVED1 : 7; - __IO uint16_t SEL_OUT : 1; -} stc_wc_clk_sel_field_t; - -typedef struct stc_wc_clk_en_field -{ - __IO uint8_t CLK_EN : 1; - __IO uint8_t CLK_EN_R : 1; -} stc_wc_clk_en_field_t; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* EXBUS_MODULE register bit fields */ -typedef struct stc_exbus_mode0_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode0_field_t; - -typedef struct stc_exbus_mode1_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode1_field_t; - -typedef struct stc_exbus_mode2_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode2_field_t; - -typedef struct stc_exbus_mode3_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode3_field_t; - -typedef struct stc_exbus_mode4_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode4_field_t; - -typedef struct stc_exbus_mode5_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode5_field_t; - -typedef struct stc_exbus_mode6_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode6_field_t; - -typedef struct stc_exbus_mode7_field -{ - __IO uint32_t WDTH0 : 1; - __IO uint32_t WDTH1 : 1; - __IO uint32_t RBMON : 1; - __IO uint32_t WEOFF : 1; - __IO uint32_t NAND : 1; - __IO uint32_t PAGE : 1; - __IO uint32_t RDY : 1; - __IO uint32_t SHRTDOUT : 1; - __IO uint32_t MPXMODE : 1; - __IO uint32_t ALEINV : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t MPXDOFF : 1; - __IO uint32_t MPXCSOF : 1; - __IO uint32_t MOEXEUP : 1; -} stc_exbus_mode7_field_t; - -typedef struct stc_exbus_tim0_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim0_field_t; - -typedef struct stc_exbus_tim1_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim1_field_t; - -typedef struct stc_exbus_tim2_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim2_field_t; - -typedef struct stc_exbus_tim3_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim3_field_t; - -typedef struct stc_exbus_tim4_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim4_field_t; - -typedef struct stc_exbus_tim5_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim5_field_t; - -typedef struct stc_exbus_tim6_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim6_field_t; - -typedef struct stc_exbus_tim7_field -{ - __IO uint32_t RACC0 : 1; - __IO uint32_t RACC1 : 1; - __IO uint32_t RACC2 : 1; - __IO uint32_t RACC3 : 1; - __IO uint32_t RADC0 : 1; - __IO uint32_t RADC1 : 1; - __IO uint32_t RADC2 : 1; - __IO uint32_t RADC3 : 1; - __IO uint32_t FRADC0 : 1; - __IO uint32_t FRADC1 : 1; - __IO uint32_t FRADC2 : 1; - __IO uint32_t FRADC3 : 1; - __IO uint32_t RIDLC0 : 1; - __IO uint32_t RIDLC1 : 1; - __IO uint32_t RIDLC2 : 1; - __IO uint32_t RIDLC3 : 1; - __IO uint32_t WACC0 : 1; - __IO uint32_t WACC1 : 1; - __IO uint32_t WACC2 : 1; - __IO uint32_t WACC3 : 1; - __IO uint32_t WADC0 : 1; - __IO uint32_t WADC1 : 1; - __IO uint32_t WADC2 : 1; - __IO uint32_t WADC3 : 1; - __IO uint32_t WWEC0 : 1; - __IO uint32_t WWEC1 : 1; - __IO uint32_t WWEC2 : 1; - __IO uint32_t WWEC3 : 1; - __IO uint32_t WIDLC0 : 1; - __IO uint32_t WIDLC1 : 1; - __IO uint32_t WIDLC2 : 1; - __IO uint32_t WIDLC3 : 1; -} stc_exbus_tim7_field_t; - -typedef struct stc_exbus_area0_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area0_field_t; - -typedef struct stc_exbus_area1_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area1_field_t; - -typedef struct stc_exbus_area2_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area2_field_t; - -typedef struct stc_exbus_area3_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area3_field_t; - -typedef struct stc_exbus_area4_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area4_field_t; - -typedef struct stc_exbus_area5_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area5_field_t; - -typedef struct stc_exbus_area6_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area6_field_t; - -typedef struct stc_exbus_area7_field -{ - __IO uint32_t ADDR0 : 1; - __IO uint32_t ADDR1 : 1; - __IO uint32_t ADDR2 : 1; - __IO uint32_t ADDR3 : 1; - __IO uint32_t ADDR4 : 1; - __IO uint32_t ADDR5 : 1; - __IO uint32_t ADDR6 : 1; - __IO uint32_t ADDR7 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MASK0 : 1; - __IO uint32_t MASK1 : 1; - __IO uint32_t MASK2 : 1; - __IO uint32_t MASK3 : 1; - __IO uint32_t MASK4 : 1; - __IO uint32_t MASK5 : 1; - __IO uint32_t MASK6 : 1; -} stc_exbus_area7_field_t; - -typedef struct stc_exbus_atim0_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim0_field_t; - -typedef struct stc_exbus_atim1_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim1_field_t; - -typedef struct stc_exbus_atim2_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim2_field_t; - -typedef struct stc_exbus_atim3_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim3_field_t; - -typedef struct stc_exbus_atim4_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim4_field_t; - -typedef struct stc_exbus_atim5_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim5_field_t; - -typedef struct stc_exbus_atim6_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim6_field_t; - -typedef struct stc_exbus_atim7_field -{ - __IO uint16_t ALC0 : 1; - __IO uint16_t ALC1 : 1; - __IO uint16_t ALC2 : 1; - __IO uint16_t ALC3 : 1; - __IO uint16_t ALES0 : 1; - __IO uint16_t ALES1 : 1; - __IO uint16_t ALES2 : 1; - __IO uint16_t ALES3 : 1; - __IO uint16_t ALEW0 : 1; - __IO uint16_t ALEW1 : 1; - __IO uint16_t ALEW2 : 1; - __IO uint16_t ALEW3 : 1; -} stc_exbus_atim7_field_t; - -typedef struct stc_exbus_dclkr_field -{ - __IO uint8_t MDIV0 : 1; - __IO uint8_t MDIV1 : 1; - __IO uint8_t MDIV2 : 1; - __IO uint8_t MDIV3 : 1; - __IO uint8_t MCLKON : 1; -} stc_exbus_dclkr_field_t; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB_MODULE register bit fields */ -typedef struct stc_usb_hcnt_field -{ - __IO uint16_t HOST : 1; - __IO uint16_t URST : 1; - __IO uint16_t SOFIRE : 1; - __IO uint16_t DIRE : 1; - __IO uint16_t CNNIRE : 1; - __IO uint16_t CMPIRE : 1; - __IO uint16_t URIRE : 1; - __IO uint16_t RWKIRE : 1; - __IO uint16_t RETRY : 1; - __IO uint16_t CANCEL : 1; - __IO uint16_t SOFSTEP : 1; -} stc_usb_hcnt_field_t; - -typedef struct stc_usb_hcnt0_field -{ - __IO uint8_t HOST : 1; - __IO uint8_t URST : 1; - __IO uint8_t SOFIRE : 1; - __IO uint8_t DIRE : 1; - __IO uint8_t CNNIRE : 1; - __IO uint8_t CMPIRE : 1; - __IO uint8_t URIRE : 1; - __IO uint8_t RWKIRE : 1; -} stc_usb_hcnt0_field_t; - -typedef struct stc_usb_hcnt1_field -{ - __IO uint8_t RETRY : 1; - __IO uint8_t CANCEL : 1; - __IO uint8_t SOFSTEP : 1; -} stc_usb_hcnt1_field_t; - -typedef struct stc_usb_hirq_field -{ - __IO uint8_t SOFIRQ : 1; - __IO uint8_t DIRQ : 1; - __IO uint8_t CNNIRQ : 1; - __IO uint8_t CMPIRQ : 1; - __IO uint8_t URIRQ : 1; - __IO uint8_t RWKIRQ : 1; - uint8_t RESERVED1 : 1; - __IO uint8_t TCAN : 1; -} stc_usb_hirq_field_t; - -typedef struct stc_usb_herr_field -{ - __IO uint8_t HS0 : 1; - __IO uint8_t HS1 : 1; - __IO uint8_t STUFF : 1; - __IO uint8_t TGERR : 1; - __IO uint8_t CRC : 1; - __IO uint8_t TOUT : 1; - __IO uint8_t RERR : 1; - __IO uint8_t LSTOF : 1; -} stc_usb_herr_field_t; - -typedef struct stc_usb_hstate_field -{ - __IO uint8_t CSTAT : 1; - __IO uint8_t TMODE : 1; - __IO uint8_t SUSP : 1; - __IO uint8_t SOFBUSY : 1; - __IO uint8_t CLKSEL : 1; - __IO uint8_t ALIVE : 1; -} stc_usb_hstate_field_t; - -typedef struct stc_usb_hfcomp_field -{ - __IO uint8_t FRAMECOMP0 : 1; - __IO uint8_t FRAMECOMP1 : 1; - __IO uint8_t FRAMECOMP2 : 1; - __IO uint8_t FRAMECOMP3 : 1; - __IO uint8_t FRAMECOMP4 : 1; - __IO uint8_t FRAMECOMP5 : 1; - __IO uint8_t FRAMECOMP6 : 1; - __IO uint8_t FRAMECOMP7 : 1; -} stc_usb_hfcomp_field_t; - -typedef struct stc_usb_hrtimer_field -{ - __IO uint16_t RTIMER0 : 1; - __IO uint16_t RTIMER1 : 1; - __IO uint16_t RTIMER2 : 1; - __IO uint16_t RTIMER3 : 1; - __IO uint16_t RTIMER4 : 1; - __IO uint16_t RTIMER5 : 1; - __IO uint16_t RTIMER6 : 1; - __IO uint16_t RTIMER7 : 1; - __IO uint16_t RTIMER8 : 1; - __IO uint16_t RTIMER9 : 1; - __IO uint16_t RTIMER10 : 1; - __IO uint16_t RTIMER11 : 1; - __IO uint16_t RTIMER12 : 1; - __IO uint16_t RTIMER13 : 1; - __IO uint16_t RTIMER14 : 1; - __IO uint16_t RTIMER15 : 1; -} stc_usb_hrtimer_field_t; - -typedef struct stc_usb_hrtimer0_field -{ - __IO uint8_t RTIMER00 : 1; - __IO uint8_t RTIMER01 : 1; - __IO uint8_t RTIMER02 : 1; - __IO uint8_t RTIMER03 : 1; - __IO uint8_t RTIMER04 : 1; - __IO uint8_t RTIMER05 : 1; - __IO uint8_t RTIMER06 : 1; - __IO uint8_t RTIMER07 : 1; -} stc_usb_hrtimer0_field_t; - -typedef struct stc_usb_hrtimer1_field -{ - __IO uint8_t RTIMER10 : 1; - __IO uint8_t RTIMER11 : 1; - __IO uint8_t RTIMER12 : 1; - __IO uint8_t RTIMER13 : 1; - __IO uint8_t RTIMER14 : 1; - __IO uint8_t RTIMER15 : 1; - __IO uint8_t RTIMER16 : 1; - __IO uint8_t RTIMER17 : 1; -} stc_usb_hrtimer1_field_t; - -typedef struct stc_usb_hrtimer2_field -{ - __IO uint8_t RTIMER20 : 1; - __IO uint8_t RTIMER21 : 1; - __IO uint8_t RTIMER22 : 1; -} stc_usb_hrtimer2_field_t; - -typedef struct stc_usb_hadr_field -{ - __IO uint8_t ADDRESS0 : 1; - __IO uint8_t ADDRESS1 : 1; - __IO uint8_t ADDRESS2 : 1; - __IO uint8_t ADDRESS3 : 1; - __IO uint8_t ADDRESS4 : 1; - __IO uint8_t ADDRESS5 : 1; - __IO uint8_t ADDRESS6 : 1; -} stc_usb_hadr_field_t; - -typedef struct stc_usb_heof_field -{ - __IO uint16_t EOF0 : 1; - __IO uint16_t EOF1 : 1; - __IO uint16_t EOF2 : 1; - __IO uint16_t EOF3 : 1; - __IO uint16_t EOF4 : 1; - __IO uint16_t EOF5 : 1; - __IO uint16_t EOF6 : 1; - __IO uint16_t EOF7 : 1; - __IO uint16_t EOF8 : 1; - __IO uint16_t EOF9 : 1; - __IO uint16_t EOF10 : 1; - __IO uint16_t EOF11 : 1; - __IO uint16_t EOF12 : 1; - __IO uint16_t EOF13 : 1; - __IO uint16_t EOF14 : 1; - __IO uint16_t EOF15 : 1; -} stc_usb_heof_field_t; - -typedef struct stc_usb_heof0_field -{ - __IO uint8_t EOF00 : 1; - __IO uint8_t EOF01 : 1; - __IO uint8_t EOF02 : 1; - __IO uint8_t EOF03 : 1; - __IO uint8_t EOF04 : 1; - __IO uint8_t EOF05 : 1; - __IO uint8_t EOF06 : 1; - __IO uint8_t EOF07 : 1; -} stc_usb_heof0_field_t; - -typedef struct stc_usb_heof1_field -{ - __IO uint8_t EOF10 : 1; - __IO uint8_t EOF11 : 1; - __IO uint8_t EOF12 : 1; - __IO uint8_t EOF13 : 1; - __IO uint8_t EOF14 : 1; - __IO uint8_t EOF15 : 1; -} stc_usb_heof1_field_t; - -typedef struct stc_usb_hframe_field -{ - __IO uint16_t FRAME0 : 1; - __IO uint16_t FRAME1 : 1; - __IO uint16_t FRAME2 : 1; - __IO uint16_t FRAME3 : 1; - __IO uint16_t FRAME4 : 1; - __IO uint16_t FRAME5 : 1; - __IO uint16_t FRAME6 : 1; - __IO uint16_t FRAME7 : 1; - __IO uint16_t FRAME8 : 1; - __IO uint16_t FRAME9 : 1; - __IO uint16_t FRAME10 : 1; -} stc_usb_hframe_field_t; - -typedef struct stc_usb_hframe0_field -{ - __IO uint8_t FRAME00 : 1; - __IO uint8_t FRAME01 : 1; - __IO uint8_t FRAME02 : 1; - __IO uint8_t FRAME03 : 1; - __IO uint8_t FRAME04 : 1; - __IO uint8_t FRAME05 : 1; - __IO uint8_t FRAME06 : 1; - __IO uint8_t FRAME07 : 1; -} stc_usb_hframe0_field_t; - -typedef struct stc_usb_hframe1_field -{ - __IO uint8_t FRAME10 : 1; - __IO uint8_t FRAME11 : 1; - __IO uint8_t FRAME12 : 1; - __IO uint8_t FRAME13 : 1; -} stc_usb_hframe1_field_t; - -typedef struct stc_usb_htoken_field -{ - __IO uint8_t ENDPT0 : 1; - __IO uint8_t ENDPT1 : 1; - __IO uint8_t ENDPT2 : 1; - __IO uint8_t ENDPT3 : 1; - __IO uint8_t TKNEN0 : 1; - __IO uint8_t TKNEN1 : 1; - __IO uint8_t TKNEN2 : 1; - __IO uint8_t TGGL : 1; -} stc_usb_htoken_field_t; - -typedef struct stc_usb_udcc_field -{ - __IO uint16_t PWC : 1; - __IO uint16_t RFBK : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t STALCLREN : 1; - __IO uint16_t USTP : 1; - __IO uint16_t HCONX : 1; - __IO uint16_t RESUM : 1; - __IO uint16_t RST : 1; -} stc_usb_udcc_field_t; - -typedef struct stc_usb_ep0c_field -{ - __IO uint16_t PKS00 : 1; - __IO uint16_t PKS01 : 1; - __IO uint16_t PKS02 : 1; - __IO uint16_t PKS03 : 1; - __IO uint16_t PKS04 : 1; - __IO uint16_t PKS05 : 1; - __IO uint16_t PKS06 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; -} stc_usb_ep0c_field_t; - -typedef struct stc_usb_ep1c_field -{ - __IO uint16_t PKS10 : 1; - __IO uint16_t PKS11 : 1; - __IO uint16_t PKS12 : 1; - __IO uint16_t PKS13 : 1; - __IO uint16_t PKS14 : 1; - __IO uint16_t PKS15 : 1; - __IO uint16_t PKS16 : 1; - __IO uint16_t PKS17 : 1; - __IO uint16_t PKS18 : 1; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep1c_field_t; - -typedef struct stc_usb_ep2c_field -{ - __IO uint16_t PKS20 : 1; - __IO uint16_t PKS21 : 1; - __IO uint16_t PKS22 : 1; - __IO uint16_t PKS23 : 1; - __IO uint16_t PKS24 : 1; - __IO uint16_t PKS25 : 1; - __IO uint16_t PKS26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep2c_field_t; - -typedef struct stc_usb_ep3c_field -{ - __IO uint16_t PKS30 : 1; - __IO uint16_t PKS31 : 1; - __IO uint16_t PKS32 : 1; - __IO uint16_t PKS33 : 1; - __IO uint16_t PKS34 : 1; - __IO uint16_t PKS35 : 1; - __IO uint16_t PKS36 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep3c_field_t; - -typedef struct stc_usb_ep4c_field -{ - __IO uint16_t PKS40 : 1; - __IO uint16_t PKS41 : 1; - __IO uint16_t PKS42 : 1; - __IO uint16_t PKS43 : 1; - __IO uint16_t PKS44 : 1; - __IO uint16_t PKS45 : 1; - __IO uint16_t PKS46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep4c_field_t; - -typedef struct stc_usb_ep5c_field -{ - __IO uint16_t PKS50 : 1; - __IO uint16_t PKS51 : 1; - __IO uint16_t PKS52 : 1; - __IO uint16_t PKS53 : 1; - __IO uint16_t PKS54 : 1; - __IO uint16_t PKS55 : 1; - __IO uint16_t PKS56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t STAL : 1; - __IO uint16_t NULE : 1; - __IO uint16_t DMAE : 1; - __IO uint16_t DIR : 1; - __IO uint16_t TYPE0 : 1; - __IO uint16_t TYPE1 : 1; - __IO uint16_t EPEN : 1; -} stc_usb_ep5c_field_t; - -typedef struct stc_usb_tmsp_field -{ - __IO uint16_t TMSP0 : 1; - __IO uint16_t TMSP1 : 1; - __IO uint16_t TMSP2 : 1; - __IO uint16_t TMSP3 : 1; - __IO uint16_t TMSP4 : 1; - __IO uint16_t TMSP5 : 1; - __IO uint16_t TMSP6 : 1; - __IO uint16_t TMSP7 : 1; - __IO uint16_t TMSP8 : 1; - __IO uint16_t TMSP9 : 1; - __IO uint16_t TMSP10 : 1; -} stc_usb_tmsp_field_t; - -typedef struct stc_usb_udcs_field -{ - __IO uint8_t CONF : 1; - __IO uint8_t SETP : 1; - __IO uint8_t WKUP : 1; - __IO uint8_t BRST : 1; - __IO uint8_t SOF : 1; - __IO uint8_t SUSP : 1; -} stc_usb_udcs_field_t; - -typedef struct stc_usb_udcie_field -{ - __IO uint8_t CONFIE : 1; - __IO uint8_t CONFN : 1; - __IO uint8_t WKUPIE : 1; - __IO uint8_t BRSTIE : 1; - __IO uint8_t SOFIE : 1; - __IO uint8_t SUSPIE : 1; -} stc_usb_udcie_field_t; - -typedef struct stc_usb_ep0is_field -{ - uint16_t RESERVED1 : 10; - __IO uint16_t DRQI : 1; - uint16_t RESERVED2 : 3; - __IO uint16_t DRQIIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0is_field_t; - -typedef struct stc_usb_ep0os_field -{ - __IO uint16_t SIZE0 : 1; - __IO uint16_t SIZE1 : 1; - __IO uint16_t SIZE2 : 1; - __IO uint16_t SIZE3 : 1; - __IO uint16_t SIZE4 : 1; - __IO uint16_t SIZE5 : 1; - __IO uint16_t SIZE6 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQO : 1; - uint16_t RESERVED2 : 2; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQOIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep0os_field_t; - -typedef struct stc_usb_ep1s_field -{ - __IO uint16_t SIZE10 : 1; - __IO uint16_t SIZE11 : 1; - __IO uint16_t SIZE12 : 1; - __IO uint16_t SIZE13 : 1; - __IO uint16_t SIZE14 : 1; - __IO uint16_t SIZE15 : 1; - __IO uint16_t SIZE16 : 1; - __IO uint16_t SIZE17 : 1; - __IO uint16_t SIZE18 : 1; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED1 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep1s_field_t; - -typedef struct stc_usb_ep2s_field -{ - __IO uint16_t SIZE20 : 1; - __IO uint16_t SIZE21 : 1; - __IO uint16_t SIZE22 : 1; - __IO uint16_t SIZE23 : 1; - __IO uint16_t SIZE24 : 1; - __IO uint16_t SIZE25 : 1; - __IO uint16_t SIZE26 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep2s_field_t; - -typedef struct stc_usb_ep4s_field -{ - __IO uint16_t SIZE40 : 1; - __IO uint16_t SIZE41 : 1; - __IO uint16_t SIZE42 : 1; - __IO uint16_t SIZE43 : 1; - __IO uint16_t SIZE44 : 1; - __IO uint16_t SIZE45 : 1; - __IO uint16_t SIZE46 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep4s_field_t; - -typedef struct stc_usb_ep5s_field -{ - __IO uint16_t SIZE50 : 1; - __IO uint16_t SIZE51 : 1; - __IO uint16_t SIZE52 : 1; - __IO uint16_t SIZE53 : 1; - __IO uint16_t SIZE54 : 1; - __IO uint16_t SIZE55 : 1; - __IO uint16_t SIZE56 : 1; - uint16_t RESERVED1 : 2; - __IO uint16_t SPK : 1; - __IO uint16_t DRQ : 1; - __IO uint16_t BUSY : 1; - uint16_t RESERVED2 : 1; - __IO uint16_t SPKIE : 1; - __IO uint16_t DRQIE : 1; - __IO uint16_t BFINI : 1; -} stc_usb_ep5s_field_t; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMAC_MODULE register bit fields */ -typedef struct stc_dmac_dmacr_field -{ - uint32_t RESERVED1 : 24; - __IO uint32_t DH0 : 1; - __IO uint32_t DH1 : 1; - __IO uint32_t DH2 : 1; - __IO uint32_t DH3 : 1; - __IO uint32_t PR : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t DS : 1; - __IO uint32_t DE : 1; -} stc_dmac_dmacr_field_t; - -typedef struct stc_dmac_dmaca0_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca0_field_t; - -typedef struct stc_dmac_dmacb0_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb0_field_t; - -typedef struct stc_dmac_dmaca1_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca1_field_t; - -typedef struct stc_dmac_dmacb1_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb1_field_t; - -typedef struct stc_dmac_dmaca2_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca2_field_t; - -typedef struct stc_dmac_dmacb2_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb2_field_t; - -typedef struct stc_dmac_dmaca3_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca3_field_t; - -typedef struct stc_dmac_dmacb3_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb3_field_t; - -typedef struct stc_dmac_dmaca4_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca4_field_t; - -typedef struct stc_dmac_dmacb4_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb4_field_t; - -typedef struct stc_dmac_dmaca5_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca5_field_t; - -typedef struct stc_dmac_dmacb5_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb5_field_t; - -typedef struct stc_dmac_dmaca6_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca6_field_t; - -typedef struct stc_dmac_dmacb6_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb6_field_t; - -typedef struct stc_dmac_dmaca7_field -{ - __IO uint32_t TC0 : 1; - __IO uint32_t TC1 : 1; - __IO uint32_t TC2 : 1; - __IO uint32_t TC3 : 1; - __IO uint32_t TC4 : 1; - __IO uint32_t TC5 : 1; - __IO uint32_t TC6 : 1; - __IO uint32_t TC7 : 1; - __IO uint32_t TC8 : 1; - __IO uint32_t TC9 : 1; - __IO uint32_t TC10 : 1; - __IO uint32_t TC11 : 1; - __IO uint32_t TC12 : 1; - __IO uint32_t TC13 : 1; - __IO uint32_t TC14 : 1; - __IO uint32_t TC15 : 1; - __IO uint32_t BC0 : 1; - __IO uint32_t BC1 : 1; - __IO uint32_t BC2 : 1; - __IO uint32_t BC3 : 1; - uint32_t RESERVED1 : 3; - __IO uint32_t IS0 : 1; - __IO uint32_t IS1 : 1; - __IO uint32_t IS2 : 1; - __IO uint32_t IS3 : 1; - __IO uint32_t IS4 : 1; - __IO uint32_t IS5 : 1; - __IO uint32_t ST : 1; - __IO uint32_t PB : 1; - __IO uint32_t EB : 1; -} stc_dmac_dmaca7_field_t; - -typedef struct stc_dmac_dmacb7_field -{ - __IO uint32_t EM : 1; - uint32_t RESERVED1 : 15; - __IO uint32_t SS0 : 1; - __IO uint32_t SS1 : 1; - __IO uint32_t SS2 : 1; - __IO uint32_t CI : 1; - __IO uint32_t EI : 1; - __IO uint32_t RD : 1; - __IO uint32_t RS : 1; - __IO uint32_t RC : 1; - __IO uint32_t FD : 1; - __IO uint32_t FS : 1; - __IO uint32_t TW0 : 1; - __IO uint32_t TW1 : 1; - __IO uint32_t MS0 : 1; - __IO uint32_t MS1 : 1; -} stc_dmac_dmacb7_field_t; - -/****************************************************************************** - * ETHERNET_MAC_MODULE - ******************************************************************************/ -/* ETHERNET_MAC_MODULE register bit fields */ -typedef struct stc_ethernet_mac_mcr_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t RE : 1; - __IO uint32_t TE : 1; - __IO uint32_t DC : 1; - __IO uint32_t BL0 : 1; - __IO uint32_t BL1 : 1; - __IO uint32_t ACS : 1; - __IO uint32_t LUD : 1; - __IO uint32_t DR : 1; - __IO uint32_t IPC : 1; - __IO uint32_t DM : 1; - __IO uint32_t LM : 1; - __IO uint32_t DO : 1; - __IO uint32_t FES : 1; - __IO uint32_t PS : 1; - __IO uint32_t DCRS : 1; - __IO uint32_t IFG0 : 1; - __IO uint32_t IFG1 : 1; - __IO uint32_t IFG2 : 1; - __IO uint32_t JE : 1; - __IO uint32_t BE : 1; - __IO uint32_t JD : 1; - __IO uint32_t WD : 1; - __IO uint32_t TC : 1; - __IO uint32_t CST : 1; -} stc_ethernet_mac_mcr_field_t; - -typedef struct stc_ethernet_mac_mffr_field -{ - __IO uint32_t PR : 1; - __IO uint32_t HUC : 1; - __IO uint32_t HMC : 1; - __IO uint32_t DAIF : 1; - __IO uint32_t PM : 1; - __IO uint32_t DB : 1; - __IO uint32_t PCF0 : 1; - __IO uint32_t PCF1 : 1; - __IO uint32_t SAIF : 1; - __IO uint32_t SAF : 1; - __IO uint32_t HPF : 1; - uint32_t RESERVED1 :20; - __IO uint32_t RA : 1; -} stc_ethernet_mac_mffr_field_t; - -typedef struct stc_ethernet_mac_mhtrh_field -{ - __IO uint32_t HTH0 : 1; - __IO uint32_t HTH1 : 1; - __IO uint32_t HTH2 : 1; - __IO uint32_t HTH3 : 1; - __IO uint32_t HTH4 : 1; - __IO uint32_t HTH5 : 1; - __IO uint32_t HTH6 : 1; - __IO uint32_t HTH7 : 1; - __IO uint32_t HTH8 : 1; - __IO uint32_t HTH9 : 1; - __IO uint32_t HTH10 : 1; - __IO uint32_t HTH11 : 1; - __IO uint32_t HTH12 : 1; - __IO uint32_t HTH13 : 1; - __IO uint32_t HTH14 : 1; - __IO uint32_t HTH15 : 1; - __IO uint32_t HTH16 : 1; - __IO uint32_t HTH17 : 1; - __IO uint32_t HTH18 : 1; - __IO uint32_t HTH19 : 1; - __IO uint32_t HTH20 : 1; - __IO uint32_t HTH21 : 1; - __IO uint32_t HTH22 : 1; - __IO uint32_t HTH23 : 1; - __IO uint32_t HTH24 : 1; - __IO uint32_t HTH25 : 1; - __IO uint32_t HTH26 : 1; - __IO uint32_t HTH27 : 1; - __IO uint32_t HTH28 : 1; - __IO uint32_t HTH29 : 1; - __IO uint32_t HTH30 : 1; - __IO uint32_t HTH31 : 1; -} stc_ethernet_mac_mhtrh_field_t; - -typedef struct stc_ethernet_mac_mhtrl_field -{ - __IO uint32_t HTL0 : 1; - __IO uint32_t HTL1 : 1; - __IO uint32_t HTL2 : 1; - __IO uint32_t HTL3 : 1; - __IO uint32_t HTL4 : 1; - __IO uint32_t HTL5 : 1; - __IO uint32_t HTL6 : 1; - __IO uint32_t HTL7 : 1; - __IO uint32_t HTL8 : 1; - __IO uint32_t HTL9 : 1; - __IO uint32_t HTL10 : 1; - __IO uint32_t HTL11 : 1; - __IO uint32_t HTL12 : 1; - __IO uint32_t HTL13 : 1; - __IO uint32_t HTL14 : 1; - __IO uint32_t HTL15 : 1; - __IO uint32_t HTL16 : 1; - __IO uint32_t HTL17 : 1; - __IO uint32_t HTL18 : 1; - __IO uint32_t HTL19 : 1; - __IO uint32_t HTL20 : 1; - __IO uint32_t HTL21 : 1; - __IO uint32_t HTL22 : 1; - __IO uint32_t HTL23 : 1; - __IO uint32_t HTL24 : 1; - __IO uint32_t HTL25 : 1; - __IO uint32_t HTL26 : 1; - __IO uint32_t HTL27 : 1; - __IO uint32_t HTL28 : 1; - __IO uint32_t HTL29 : 1; - __IO uint32_t HTL30 : 1; - __IO uint32_t HTL31 : 1; -} stc_ethernet_mac_mhtrl_field_t; - -typedef struct stc_ethernet_mac_gar_field -{ - __IO uint32_t GB : 1; - __IO uint32_t GW : 1; - __IO uint32_t CR0 : 1; - __IO uint32_t CR1 : 1; - __IO uint32_t CR2 : 1; - __IO uint32_t CR3 : 1; - __IO uint32_t GR0 : 1; - __IO uint32_t GR1 : 1; - __IO uint32_t GR2 : 1; - __IO uint32_t GR3 : 1; - __IO uint32_t GR4 : 1; - __IO uint32_t PA0 : 1; - __IO uint32_t PA1 : 1; - __IO uint32_t PA2 : 1; - __IO uint32_t PA3 : 1; - __IO uint32_t PA4 : 1; -} stc_ethernet_mac_gar_field_t; - -typedef struct stc_ethernet_mac_gdr_field -{ - __IO uint32_t GD0 : 1; - __IO uint32_t GD1 : 1; - __IO uint32_t GD2 : 1; - __IO uint32_t GD3 : 1; - __IO uint32_t GD4 : 1; - __IO uint32_t GD5 : 1; - __IO uint32_t GD6 : 1; - __IO uint32_t GD7 : 1; - __IO uint32_t GD8 : 1; - __IO uint32_t GD9 : 1; - __IO uint32_t GD10 : 1; - __IO uint32_t GD11 : 1; - __IO uint32_t GD12 : 1; - __IO uint32_t GD13 : 1; - __IO uint32_t GD14 : 1; - __IO uint32_t GD15 : 1; -} stc_ethernet_mac_gdr_field_t; - -typedef struct stc_ethernet_mac_fcr_field -{ - __IO uint32_t FCB_BPA : 1; - __IO uint32_t TFE : 1; - __IO uint32_t RFE : 1; - __IO uint32_t UP : 1; - __IO uint32_t PLT0 : 1; - __IO uint32_t PLT1 : 1; - uint32_t RESERVED1 : 1; - __IO uint32_t DZPQ : 1; - uint32_t RESERVED2 : 8; - __IO uint32_t PT0 : 1; - __IO uint32_t PT1 : 1; - __IO uint32_t PT2 : 1; - __IO uint32_t PT3 : 1; - __IO uint32_t PT4 : 1; - __IO uint32_t PT5 : 1; - __IO uint32_t PT6 : 1; - __IO uint32_t PT7 : 1; - __IO uint32_t PT8 : 1; - __IO uint32_t PT9 : 1; - __IO uint32_t PT10 : 1; - __IO uint32_t PT11 : 1; - __IO uint32_t PT12 : 1; - __IO uint32_t PT13 : 1; - __IO uint32_t PT14 : 1; - __IO uint32_t PT15 : 1; -} stc_ethernet_mac_fcr_field_t; - -typedef struct stc_ethernet_mac_vtr_field -{ - __IO uint32_t VL0 : 1; - __IO uint32_t VL1 : 1; - __IO uint32_t VL2 : 1; - __IO uint32_t VL3 : 1; - __IO uint32_t VL4 : 1; - __IO uint32_t VL5 : 1; - __IO uint32_t VL6 : 1; - __IO uint32_t VL7 : 1; - __IO uint32_t VL8 : 1; - __IO uint32_t VL9 : 1; - __IO uint32_t VL10 : 1; - __IO uint32_t VL11 : 1; - __IO uint32_t VL12 : 1; - __IO uint32_t VL13 : 1; - __IO uint32_t VL14 : 1; - __IO uint32_t VL15 : 1; - __IO uint32_t ETV : 1; -} stc_ethernet_mac_vtr_field_t; - -typedef struct stc_ethernet_mac_rwffr_field -{ - __IO uint32_t RWFFR0 : 1; - __IO uint32_t RWFFR1 : 1; - __IO uint32_t RWFFR2 : 1; - __IO uint32_t RWFFR3 : 1; - __IO uint32_t RWFFR4 : 1; - __IO uint32_t RWFFR5 : 1; - __IO uint32_t RWFFR6 : 1; - __IO uint32_t RWFFR7 : 1; - __IO uint32_t RWFFR8 : 1; - __IO uint32_t RWFFR9 : 1; - __IO uint32_t RWFFR10 : 1; - __IO uint32_t RWFFR11 : 1; - __IO uint32_t RWFFR12 : 1; - __IO uint32_t RWFFR13 : 1; - __IO uint32_t RWFFR14 : 1; - __IO uint32_t RWFFR15 : 1; - __IO uint32_t RWFFR16 : 1; - __IO uint32_t RWFFR17 : 1; - __IO uint32_t RWFFR18 : 1; - __IO uint32_t RWFFR19 : 1; - __IO uint32_t RWFFR20 : 1; - __IO uint32_t RWFFR21 : 1; - __IO uint32_t RWFFR22 : 1; - __IO uint32_t RWFFR23 : 1; - __IO uint32_t RWFFR24 : 1; - __IO uint32_t RWFFR25 : 1; - __IO uint32_t RWFFR26 : 1; - __IO uint32_t RWFFR27 : 1; - __IO uint32_t RWFFR28 : 1; - __IO uint32_t RWFFR29 : 1; - __IO uint32_t RWFFR30 : 1; - __IO uint32_t RWFFR31 : 1; -} stc_ethernet_mac_rwffr_field_t; - -typedef struct stc_ethernet_mac_pmtr_field -{ - __IO uint32_t PD : 1; - __IO uint32_t MPE : 1; - __IO uint32_t WFE : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t MPR : 1; - __IO uint32_t WPR : 1; - uint32_t RESERVED2 : 2; - __IO uint32_t GU : 1; - uint32_t RESERVED3 :21; - __IO uint32_t RWFFRPR : 1; -} stc_ethernet_mac_pmtr_field_t; - -typedef struct stc_ethernet_mac_lpicsr_field -{ - __IO uint32_t TLPIEN : 1; - __IO uint32_t TLPIEX : 1; - __IO uint32_t RLPIEN : 1; - __IO uint32_t RLPIEX : 1; - uint32_t RESERVED1 : 4; - __IO uint32_t TLPIST : 1; - __IO uint32_t RLPIST : 1; - uint32_t RESERVED2 : 6; - __IO uint32_t LPIEN : 1; - __IO uint32_t PLS : 1; - __IO uint32_t PLSEN : 1; - __IO uint32_t LPITXA : 1; -} stc_ethernet_mac_lpicsr_field_t; - -typedef struct stc_ethernet_mac_lpitcr_field -{ - __IO uint32_t TWT0 : 1; - __IO uint32_t TWT1 : 1; - __IO uint32_t TWT2 : 1; - __IO uint32_t TWT3 : 1; - __IO uint32_t TWT4 : 1; - __IO uint32_t TWT5 : 1; - __IO uint32_t TWT6 : 1; - __IO uint32_t TWT7 : 1; - __IO uint32_t TWT8 : 1; - __IO uint32_t TWT9 : 1; - __IO uint32_t TWT10 : 1; - __IO uint32_t TWT11 : 1; - __IO uint32_t TWT12 : 1; - __IO uint32_t TWT13 : 1; - __IO uint32_t TWT14 : 1; - __IO uint32_t TWT15 : 1; - __IO uint32_t LIT0 : 1; - __IO uint32_t LIT1 : 1; - __IO uint32_t LIT2 : 1; - __IO uint32_t LIT3 : 1; - __IO uint32_t LIT4 : 1; - __IO uint32_t LIT5 : 1; - __IO uint32_t LIT6 : 1; - __IO uint32_t LIT7 : 1; - __IO uint32_t LIT8 : 1; - __IO uint32_t LIT9 : 1; -} stc_ethernet_mac_lpitcr_field_t; - -typedef struct stc_ethernet_mac_isr_field -{ - __IO uint32_t RGIS : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t PIS : 1; - __IO uint32_t MIS : 1; - __IO uint32_t RIS : 1; - __IO uint32_t TIS : 1; - __IO uint32_t COIS : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t TSIS : 1; - __IO uint32_t LPIIS : 1; -} stc_ethernet_mac_isr_field_t; - -typedef struct stc_ethernet_mac_imr_field -{ - __IO uint32_t RGIM : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t PIM : 1; - uint32_t RESERVED2 : 5; - __IO uint32_t TSIM : 1; - __IO uint32_t LPIIM : 1; -} stc_ethernet_mac_imr_field_t; - -typedef struct stc_ethernet_mac_mar0h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 :15; - __IO uint32_t MO : 1; -} stc_ethernet_mac_mar0h_field_t; - -typedef struct stc_ethernet_mac_mar0l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar0l_field_t; - -typedef struct stc_ethernet_mac_mar1h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar1h_field_t; - -typedef struct stc_ethernet_mac_mar1l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar1l_field_t; - -typedef struct stc_ethernet_mac_mar2h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar2h_field_t; - -typedef struct stc_ethernet_mac_mar2l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar2l_field_t; - -typedef struct stc_ethernet_mac_mar3h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar3h_field_t; - -typedef struct stc_ethernet_mac_mar3l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar3l_field_t; - -typedef struct stc_ethernet_mac_mar4h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar4h_field_t; - -typedef struct stc_ethernet_mac_mar4l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar4l_field_t; - -typedef struct stc_ethernet_mac_mar5h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar5h_field_t; - -typedef struct stc_ethernet_mac_mar5l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar5l_field_t; - -typedef struct stc_ethernet_mac_mar6h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar6h_field_t; - -typedef struct stc_ethernet_mac_mar6l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar6l_field_t; - -typedef struct stc_ethernet_mac_mar7h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar7h_field_t; - -typedef struct stc_ethernet_mac_mar7l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar7l_field_t; - -typedef struct stc_ethernet_mac_mar8h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar8h_field_t; - -typedef struct stc_ethernet_mac_mar8l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar8l_field_t; - -typedef struct stc_ethernet_mac_mar9h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar9h_field_t; - -typedef struct stc_ethernet_mac_mar9l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar9l_field_t; - -typedef struct stc_ethernet_mac_mar10h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar10h_field_t; - -typedef struct stc_ethernet_mac_mar10l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar10l_field_t; - -typedef struct stc_ethernet_mac_mar11h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar11h_field_t; - -typedef struct stc_ethernet_mac_mar11l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar11l_field_t; - -typedef struct stc_ethernet_mac_mar12h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar12h_field_t; - -typedef struct stc_ethernet_mac_mar12l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar12l_field_t; - -typedef struct stc_ethernet_mac_mar13h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar13h_field_t; - -typedef struct stc_ethernet_mac_mar13l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar13l_field_t; - -typedef struct stc_ethernet_mac_mar14h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar14h_field_t; - -typedef struct stc_ethernet_mac_mar14l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar14l_field_t; - -typedef struct stc_ethernet_mac_mar15h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar15h_field_t; - -typedef struct stc_ethernet_mac_mar15l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar15l_field_t; - -typedef struct stc_ethernet_mac_rgsr_field -{ - __IO uint32_t LM : 1; - __IO uint32_t LSP0 : 1; - __IO uint32_t LSP1 : 1; - __IO uint32_t LS : 1; -} stc_ethernet_mac_rgsr_field_t; - -typedef struct stc_ethernet_mac_tscr_field -{ - __IO uint32_t TSE : 1; - __IO uint32_t TFCU : 1; - __IO uint32_t TSI : 1; - __IO uint32_t TSU : 1; - __IO uint32_t TITE : 1; - __IO uint32_t TARU : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t TSEA : 1; - __IO uint32_t TSDB : 1; - __IO uint32_t TSV2E : 1; - __IO uint32_t TETSP : 1; - __IO uint32_t TSIP6E : 1; - __IO uint32_t TSIP4E : 1; - __IO uint32_t TETSEM : 1; - __IO uint32_t TSMRM : 1; - __IO uint32_t TSPS0 : 1; - __IO uint32_t TSPS1 : 1; - __IO uint32_t TSENMF : 1; - uint32_t RESERVED2 : 5; - __IO uint32_t ATSFC : 1; -} stc_ethernet_mac_tscr_field_t; - -typedef struct stc_ethernet_mac_ssir_field -{ - __IO uint32_t SSINC0 : 1; - __IO uint32_t SSINC1 : 1; - __IO uint32_t SSINC2 : 1; - __IO uint32_t SSINC3 : 1; - __IO uint32_t SSINC4 : 1; - __IO uint32_t SSINC5 : 1; - __IO uint32_t SSINC6 : 1; - __IO uint32_t SSINC7 : 1; -} stc_ethernet_mac_ssir_field_t; - -typedef struct stc_ethernet_mac_stsr_field -{ - __IO uint32_t TSS0 : 1; - __IO uint32_t TSS1 : 1; - __IO uint32_t TSS2 : 1; - __IO uint32_t TSS3 : 1; - __IO uint32_t TSS4 : 1; - __IO uint32_t TSS5 : 1; - __IO uint32_t TSS6 : 1; - __IO uint32_t TSS7 : 1; - __IO uint32_t TSS8 : 1; - __IO uint32_t TSS9 : 1; - __IO uint32_t TSS10 : 1; - __IO uint32_t TSS11 : 1; - __IO uint32_t TSS12 : 1; - __IO uint32_t TSS13 : 1; - __IO uint32_t TSS14 : 1; - __IO uint32_t TSS15 : 1; - __IO uint32_t TSS16 : 1; - __IO uint32_t TSS17 : 1; - __IO uint32_t TSS18 : 1; - __IO uint32_t TSS19 : 1; - __IO uint32_t TSS20 : 1; - __IO uint32_t TSS21 : 1; - __IO uint32_t TSS22 : 1; - __IO uint32_t TSS23 : 1; - __IO uint32_t TSS24 : 1; - __IO uint32_t TSS25 : 1; - __IO uint32_t TSS26 : 1; - __IO uint32_t TSS27 : 1; - __IO uint32_t TSS28 : 1; - __IO uint32_t TSS29 : 1; - __IO uint32_t TSS30 : 1; - __IO uint32_t TSS31 : 1; -} stc_ethernet_mac_stsr_field_t; - -typedef struct stc_ethernet_mac_stnr_field -{ - __IO uint32_t TSSS0 : 1; - __IO uint32_t TSSS1 : 1; - __IO uint32_t TSSS2 : 1; - __IO uint32_t TSSS3 : 1; - __IO uint32_t TSSS4 : 1; - __IO uint32_t TSSS5 : 1; - __IO uint32_t TSSS6 : 1; - __IO uint32_t TSSS7 : 1; - __IO uint32_t TSSS8 : 1; - __IO uint32_t TSSS9 : 1; - __IO uint32_t TSSS10 : 1; - __IO uint32_t TSSS11 : 1; - __IO uint32_t TSSS12 : 1; - __IO uint32_t TSSS13 : 1; - __IO uint32_t TSSS14 : 1; - __IO uint32_t TSSS15 : 1; - __IO uint32_t TSSS16 : 1; - __IO uint32_t TSSS17 : 1; - __IO uint32_t TSSS18 : 1; - __IO uint32_t TSSS19 : 1; - __IO uint32_t TSSS20 : 1; - __IO uint32_t TSSS21 : 1; - __IO uint32_t TSSS22 : 1; - __IO uint32_t TSSS23 : 1; - __IO uint32_t TSSS24 : 1; - __IO uint32_t TSSS25 : 1; - __IO uint32_t TSSS26 : 1; - __IO uint32_t TSSS27 : 1; - __IO uint32_t TSSS28 : 1; - __IO uint32_t TSSS29 : 1; - __IO uint32_t TSSS30 : 1; -} stc_ethernet_mac_stnr_field_t; - -typedef struct stc_ethernet_mac_stsur_field -{ - __IO uint32_t TSS0 : 1; - __IO uint32_t TSS1 : 1; - __IO uint32_t TSS2 : 1; - __IO uint32_t TSS3 : 1; - __IO uint32_t TSS4 : 1; - __IO uint32_t TSS5 : 1; - __IO uint32_t TSS6 : 1; - __IO uint32_t TSS7 : 1; - __IO uint32_t TSS8 : 1; - __IO uint32_t TSS9 : 1; - __IO uint32_t TSS10 : 1; - __IO uint32_t TSS11 : 1; - __IO uint32_t TSS12 : 1; - __IO uint32_t TSS13 : 1; - __IO uint32_t TSS14 : 1; - __IO uint32_t TSS15 : 1; - __IO uint32_t TSS16 : 1; - __IO uint32_t TSS17 : 1; - __IO uint32_t TSS18 : 1; - __IO uint32_t TSS19 : 1; - __IO uint32_t TSS20 : 1; - __IO uint32_t TSS21 : 1; - __IO uint32_t TSS22 : 1; - __IO uint32_t TSS23 : 1; - __IO uint32_t TSS24 : 1; - __IO uint32_t TSS25 : 1; - __IO uint32_t TSS26 : 1; - __IO uint32_t TSS27 : 1; - __IO uint32_t TSS28 : 1; - __IO uint32_t TSS29 : 1; - __IO uint32_t TSS30 : 1; - __IO uint32_t TSS31 : 1; -} stc_ethernet_mac_stsur_field_t; - -typedef struct stc_ethernet_mac_stnur_field -{ - __IO uint32_t TSSS0 : 1; - __IO uint32_t TSSS1 : 1; - __IO uint32_t TSSS2 : 1; - __IO uint32_t TSSS3 : 1; - __IO uint32_t TSSS4 : 1; - __IO uint32_t TSSS5 : 1; - __IO uint32_t TSSS6 : 1; - __IO uint32_t TSSS7 : 1; - __IO uint32_t TSSS8 : 1; - __IO uint32_t TSSS9 : 1; - __IO uint32_t TSSS10 : 1; - __IO uint32_t TSSS11 : 1; - __IO uint32_t TSSS12 : 1; - __IO uint32_t TSSS13 : 1; - __IO uint32_t TSSS14 : 1; - __IO uint32_t TSSS15 : 1; - __IO uint32_t TSSS16 : 1; - __IO uint32_t TSSS17 : 1; - __IO uint32_t TSSS18 : 1; - __IO uint32_t TSSS19 : 1; - __IO uint32_t TSSS20 : 1; - __IO uint32_t TSSS21 : 1; - __IO uint32_t TSSS22 : 1; - __IO uint32_t TSSS23 : 1; - __IO uint32_t TSSS24 : 1; - __IO uint32_t TSSS25 : 1; - __IO uint32_t TSSS26 : 1; - __IO uint32_t TSSS27 : 1; - __IO uint32_t TSSS28 : 1; - __IO uint32_t TSSS29 : 1; - __IO uint32_t TSSS30 : 1; - __IO uint32_t ADDSUB : 1; -} stc_ethernet_mac_stnur_field_t; - -typedef struct stc_ethernet_mac_tsar_field -{ - __IO uint32_t TSAR0 : 1; - __IO uint32_t TSAR1 : 1; - __IO uint32_t TSAR2 : 1; - __IO uint32_t TSAR3 : 1; - __IO uint32_t TSAR4 : 1; - __IO uint32_t TSAR5 : 1; - __IO uint32_t TSAR6 : 1; - __IO uint32_t TSAR7 : 1; - __IO uint32_t TSAR8 : 1; - __IO uint32_t TSAR9 : 1; - __IO uint32_t TSAR10 : 1; - __IO uint32_t TSAR11 : 1; - __IO uint32_t TSAR12 : 1; - __IO uint32_t TSAR13 : 1; - __IO uint32_t TSAR14 : 1; - __IO uint32_t TSAR15 : 1; - __IO uint32_t TSAR16 : 1; - __IO uint32_t TSAR17 : 1; - __IO uint32_t TSAR18 : 1; - __IO uint32_t TSAR19 : 1; - __IO uint32_t TSAR20 : 1; - __IO uint32_t TSAR21 : 1; - __IO uint32_t TSAR22 : 1; - __IO uint32_t TSAR23 : 1; - __IO uint32_t TSAR24 : 1; - __IO uint32_t TSAR25 : 1; - __IO uint32_t TSAR26 : 1; - __IO uint32_t TSAR27 : 1; - __IO uint32_t TSAR28 : 1; - __IO uint32_t TSAR29 : 1; - __IO uint32_t TSAR30 : 1; - __IO uint32_t TSAR31 : 1; -} stc_ethernet_mac_tsar_field_t; - -typedef struct stc_ethernet_mac_ttsr_field -{ - __IO uint32_t TSTR0 : 1; - __IO uint32_t TSTR1 : 1; - __IO uint32_t TSTR2 : 1; - __IO uint32_t TSTR3 : 1; - __IO uint32_t TSTR4 : 1; - __IO uint32_t TSTR5 : 1; - __IO uint32_t TSTR6 : 1; - __IO uint32_t TSTR7 : 1; - __IO uint32_t TSTR8 : 1; - __IO uint32_t TSTR9 : 1; - __IO uint32_t TSTR10 : 1; - __IO uint32_t TSTR11 : 1; - __IO uint32_t TSTR12 : 1; - __IO uint32_t TSTR13 : 1; - __IO uint32_t TSTR14 : 1; - __IO uint32_t TSTR15 : 1; - __IO uint32_t TSTR16 : 1; - __IO uint32_t TSTR17 : 1; - __IO uint32_t TSTR18 : 1; - __IO uint32_t TSTR19 : 1; - __IO uint32_t TSTR20 : 1; - __IO uint32_t TSTR21 : 1; - __IO uint32_t TSTR22 : 1; - __IO uint32_t TSTR23 : 1; - __IO uint32_t TSTR24 : 1; - __IO uint32_t TSTR25 : 1; - __IO uint32_t TSTR26 : 1; - __IO uint32_t TSTR27 : 1; - __IO uint32_t TSTR28 : 1; - __IO uint32_t TSTR29 : 1; - __IO uint32_t TSTR30 : 1; - __IO uint32_t TSTR31 : 1; -} stc_ethernet_mac_ttsr_field_t; - -typedef struct stc_ethernet_mac_ttnr_field -{ - __IO uint32_t TSTR0 : 1; - __IO uint32_t TSTR1 : 1; - __IO uint32_t TSTR2 : 1; - __IO uint32_t TSTR3 : 1; - __IO uint32_t TSTR4 : 1; - __IO uint32_t TSTR5 : 1; - __IO uint32_t TSTR6 : 1; - __IO uint32_t TSTR7 : 1; - __IO uint32_t TSTR8 : 1; - __IO uint32_t TSTR9 : 1; - __IO uint32_t TSTR10 : 1; - __IO uint32_t TSTR11 : 1; - __IO uint32_t TSTR12 : 1; - __IO uint32_t TSTR13 : 1; - __IO uint32_t TSTR14 : 1; - __IO uint32_t TSTR15 : 1; - __IO uint32_t TSTR16 : 1; - __IO uint32_t TSTR17 : 1; - __IO uint32_t TSTR18 : 1; - __IO uint32_t TSTR19 : 1; - __IO uint32_t TSTR20 : 1; - __IO uint32_t TSTR21 : 1; - __IO uint32_t TSTR22 : 1; - __IO uint32_t TSTR23 : 1; - __IO uint32_t TSTR24 : 1; - __IO uint32_t TSTR25 : 1; - __IO uint32_t TSTR26 : 1; - __IO uint32_t TSTR27 : 1; - __IO uint32_t TSTR28 : 1; - __IO uint32_t TSTR29 : 1; - __IO uint32_t TSTR30 : 1; -} stc_ethernet_mac_ttnr_field_t; - -typedef struct stc_ethernet_mac_sthwsr_field -{ - __IO uint32_t TSHWR0 : 1; - __IO uint32_t TSHWR1 : 1; - __IO uint32_t TSHWR2 : 1; - __IO uint32_t TSHWR3 : 1; - __IO uint32_t TSHWR4 : 1; - __IO uint32_t TSHWR5 : 1; - __IO uint32_t TSHWR6 : 1; - __IO uint32_t TSHWR7 : 1; - __IO uint32_t TSHWR8 : 1; - __IO uint32_t TSHWR9 : 1; - __IO uint32_t TSHWR10 : 1; - __IO uint32_t TSHWR11 : 1; - __IO uint32_t TSHWR12 : 1; - __IO uint32_t TSHWR13 : 1; - __IO uint32_t TSHWR14 : 1; - __IO uint32_t TSHWR15 : 1; -} stc_ethernet_mac_sthwsr_field_t; - -typedef struct stc_ethernet_mac_tsr_field -{ - __IO uint32_t TSSOVF : 1; - __IO uint32_t TSTART : 1; - __IO uint32_t ATSTS : 1; - __IO uint32_t TRGTER : 1; - uint32_t RESERVED1 :20; - __IO uint32_t ATSSTM : 1; - __IO uint32_t ATSNS0 : 1; - __IO uint32_t ATSNS1 : 1; - __IO uint32_t ATSNS2 : 1; -} stc_ethernet_mac_tsr_field_t; - -typedef struct stc_ethernet_mac_ppscr_field -{ - __IO uint32_t PPSCTRL0 : 1; - __IO uint32_t PPSCTRL1 : 1; - __IO uint32_t PPSCTRL2 : 1; - __IO uint32_t PPSCTRL3 : 1; -} stc_ethernet_mac_ppscr_field_t; - -typedef struct stc_ethernet_mac_atnr_field -{ - __IO uint32_t ATN0 : 1; - __IO uint32_t ATN1 : 1; - __IO uint32_t ATN2 : 1; - __IO uint32_t ATN3 : 1; - __IO uint32_t ATN4 : 1; - __IO uint32_t ATN5 : 1; - __IO uint32_t ATN6 : 1; - __IO uint32_t ATN7 : 1; - __IO uint32_t ATN8 : 1; - __IO uint32_t ATN9 : 1; - __IO uint32_t ATN10 : 1; - __IO uint32_t ATN11 : 1; - __IO uint32_t ATN12 : 1; - __IO uint32_t ATN13 : 1; - __IO uint32_t ATN14 : 1; - __IO uint32_t ATN15 : 1; - __IO uint32_t ATN16 : 1; - __IO uint32_t ATN17 : 1; - __IO uint32_t ATN18 : 1; - __IO uint32_t ATN19 : 1; - __IO uint32_t ATN20 : 1; - __IO uint32_t ATN21 : 1; - __IO uint32_t ATN22 : 1; - __IO uint32_t ATN23 : 1; - __IO uint32_t ATN24 : 1; - __IO uint32_t ATN25 : 1; - __IO uint32_t ATN26 : 1; - __IO uint32_t ATN27 : 1; - __IO uint32_t ATN28 : 1; - __IO uint32_t ATN29 : 1; - __IO uint32_t ATN30 : 1; -} stc_ethernet_mac_atnr_field_t; - -typedef struct stc_ethernet_mac_atsr_field -{ - __IO uint32_t ATS0 : 1; - __IO uint32_t ATS1 : 1; - __IO uint32_t ATS2 : 1; - __IO uint32_t ATS3 : 1; - __IO uint32_t ATS4 : 1; - __IO uint32_t ATS5 : 1; - __IO uint32_t ATS6 : 1; - __IO uint32_t ATS7 : 1; - __IO uint32_t ATS8 : 1; - __IO uint32_t ATS9 : 1; - __IO uint32_t ATS10 : 1; - __IO uint32_t ATS11 : 1; - __IO uint32_t ATS12 : 1; - __IO uint32_t ATS13 : 1; - __IO uint32_t ATS14 : 1; - __IO uint32_t ATS15 : 1; - __IO uint32_t ATS16 : 1; - __IO uint32_t ATS17 : 1; - __IO uint32_t ATS18 : 1; - __IO uint32_t ATS19 : 1; - __IO uint32_t ATS20 : 1; - __IO uint32_t ATS21 : 1; - __IO uint32_t ATS22 : 1; - __IO uint32_t ATS23 : 1; - __IO uint32_t ATS24 : 1; - __IO uint32_t ATS25 : 1; - __IO uint32_t ATS26 : 1; - __IO uint32_t ATS27 : 1; - __IO uint32_t ATS28 : 1; - __IO uint32_t ATS29 : 1; - __IO uint32_t ATS30 : 1; - __IO uint32_t ATS31 : 1; -} stc_ethernet_mac_atsr_field_t; - -typedef struct stc_ethernet_mac_mar16h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar16h_field_t; - -typedef struct stc_ethernet_mac_mar16l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar16l_field_t; - -typedef struct stc_ethernet_mac_mar17h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar17h_field_t; - -typedef struct stc_ethernet_mac_mar17l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar17l_field_t; - -typedef struct stc_ethernet_mac_mar18h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar18h_field_t; - -typedef struct stc_ethernet_mac_mar18l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar18l_field_t; - -typedef struct stc_ethernet_mac_mar19h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar19h_field_t; - -typedef struct stc_ethernet_mac_mar19l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar19l_field_t; - -typedef struct stc_ethernet_mac_mar20h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar20h_field_t; - -typedef struct stc_ethernet_mac_mar20l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar20l_field_t; - -typedef struct stc_ethernet_mac_mar21h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar21h_field_t; - -typedef struct stc_ethernet_mac_mar21l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar21l_field_t; - -typedef struct stc_ethernet_mac_mar22h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar22h_field_t; - -typedef struct stc_ethernet_mac_mar22l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar22l_field_t; - -typedef struct stc_ethernet_mac_mar23h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar23h_field_t; - -typedef struct stc_ethernet_mac_mar23l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar23l_field_t; - -typedef struct stc_ethernet_mac_mar24h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar24h_field_t; - -typedef struct stc_ethernet_mac_mar24l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar24l_field_t; - -typedef struct stc_ethernet_mac_mar25h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar25h_field_t; - -typedef struct stc_ethernet_mac_mar25l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar25l_field_t; - -typedef struct stc_ethernet_mac_mar26h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar26h_field_t; - -typedef struct stc_ethernet_mac_mar26l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar26l_field_t; - -typedef struct stc_ethernet_mac_mar27h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar27h_field_t; - -typedef struct stc_ethernet_mac_mar27l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar27l_field_t; - -typedef struct stc_ethernet_mac_mar28h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar28h_field_t; - -typedef struct stc_ethernet_mac_mar28l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar28l_field_t; - -typedef struct stc_ethernet_mac_mar29h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar29h_field_t; - -typedef struct stc_ethernet_mac_mar29l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar29l_field_t; - -typedef struct stc_ethernet_mac_mar30h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar30h_field_t; - -typedef struct stc_ethernet_mac_mar30l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar30l_field_t; - -typedef struct stc_ethernet_mac_mar31h_field -{ - __IO uint32_t A32 : 1; - __IO uint32_t A33 : 1; - __IO uint32_t A34 : 1; - __IO uint32_t A35 : 1; - __IO uint32_t A36 : 1; - __IO uint32_t A37 : 1; - __IO uint32_t A38 : 1; - __IO uint32_t A39 : 1; - __IO uint32_t A40 : 1; - __IO uint32_t A41 : 1; - __IO uint32_t A42 : 1; - __IO uint32_t A43 : 1; - __IO uint32_t A44 : 1; - __IO uint32_t A45 : 1; - __IO uint32_t A46 : 1; - __IO uint32_t A47 : 1; - uint32_t RESERVED1 : 8; - __IO uint32_t MBC0 : 1; - __IO uint32_t MBC1 : 1; - __IO uint32_t MBC2 : 1; - __IO uint32_t MBC3 : 1; - __IO uint32_t MBC4 : 1; - __IO uint32_t MBC5 : 1; - __IO uint32_t SA : 1; - __IO uint32_t AE : 1; -} stc_ethernet_mac_mar31h_field_t; - -typedef struct stc_ethernet_mac_mar31l_field -{ - __IO uint32_t A0 : 1; - __IO uint32_t A1 : 1; - __IO uint32_t A2 : 1; - __IO uint32_t A3 : 1; - __IO uint32_t A4 : 1; - __IO uint32_t A5 : 1; - __IO uint32_t A6 : 1; - __IO uint32_t A7 : 1; - __IO uint32_t A8 : 1; - __IO uint32_t A9 : 1; - __IO uint32_t A10 : 1; - __IO uint32_t A11 : 1; - __IO uint32_t A12 : 1; - __IO uint32_t A13 : 1; - __IO uint32_t A14 : 1; - __IO uint32_t A15 : 1; - __IO uint32_t A16 : 1; - __IO uint32_t A17 : 1; - __IO uint32_t A18 : 1; - __IO uint32_t A19 : 1; - __IO uint32_t A20 : 1; - __IO uint32_t A21 : 1; - __IO uint32_t A22 : 1; - __IO uint32_t A23 : 1; - __IO uint32_t A24 : 1; - __IO uint32_t A25 : 1; - __IO uint32_t A26 : 1; - __IO uint32_t A27 : 1; - __IO uint32_t A28 : 1; - __IO uint32_t A29 : 1; - __IO uint32_t A30 : 1; - __IO uint32_t A31 : 1; -} stc_ethernet_mac_mar31l_field_t; - -typedef struct stc_ethernet_mac_bmr_field -{ - __IO uint32_t SWR : 1; - __IO uint32_t DA : 1; - __IO uint32_t DSL0 : 1; - __IO uint32_t DSL1 : 1; - __IO uint32_t DSL2 : 1; - __IO uint32_t DSL3 : 1; - __IO uint32_t DSL4 : 1; - __IO uint32_t ATDS : 1; - __IO uint32_t PBL0 : 1; - __IO uint32_t PBL1 : 1; - __IO uint32_t PBL2 : 1; - __IO uint32_t PBL3 : 1; - __IO uint32_t PBL4 : 1; - __IO uint32_t PBL5 : 1; - __IO uint32_t PR0 : 1; - __IO uint32_t PR1 : 1; - __IO uint32_t FB : 1; - __IO uint32_t RPBL0 : 1; - __IO uint32_t RPBL1 : 1; - __IO uint32_t RPBL2 : 1; - __IO uint32_t RPBL3 : 1; - __IO uint32_t RPBL4 : 1; - __IO uint32_t RPBL5 : 1; - __IO uint32_t USP : 1; - __IO uint32_t _8XPBL : 1; - __IO uint32_t AAL : 1; - __IO uint32_t MB : 1; - __IO uint32_t TXPR : 1; -} stc_ethernet_mac_bmr_field_t; - -typedef struct stc_ethernet_mac_tpdr_field -{ - __IO uint32_t TPD0 : 1; - __IO uint32_t TPD1 : 1; - __IO uint32_t TPD2 : 1; - __IO uint32_t TPD3 : 1; - __IO uint32_t TPD4 : 1; - __IO uint32_t TPD5 : 1; - __IO uint32_t TPD6 : 1; - __IO uint32_t TPD7 : 1; - __IO uint32_t TPD8 : 1; - __IO uint32_t TPD9 : 1; - __IO uint32_t TPD10 : 1; - __IO uint32_t TPD11 : 1; - __IO uint32_t TPD12 : 1; - __IO uint32_t TPD13 : 1; - __IO uint32_t TPD14 : 1; - __IO uint32_t TPD15 : 1; - __IO uint32_t TPD16 : 1; - __IO uint32_t TPD17 : 1; - __IO uint32_t TPD18 : 1; - __IO uint32_t TPD19 : 1; - __IO uint32_t TPD20 : 1; - __IO uint32_t TPD21 : 1; - __IO uint32_t TPD22 : 1; - __IO uint32_t TPD23 : 1; - __IO uint32_t TPD24 : 1; - __IO uint32_t TPD25 : 1; - __IO uint32_t TPD26 : 1; - __IO uint32_t TPD27 : 1; - __IO uint32_t TPD28 : 1; - __IO uint32_t TPD29 : 1; - __IO uint32_t TPD30 : 1; - __IO uint32_t TPD31 : 1; -} stc_ethernet_mac_tpdr_field_t; - -typedef struct stc_ethernet_mac_rpdr_field -{ - __IO uint32_t RPD0 : 1; - __IO uint32_t RPD1 : 1; - __IO uint32_t RPD2 : 1; - __IO uint32_t RPD3 : 1; - __IO uint32_t RPD4 : 1; - __IO uint32_t RPD5 : 1; - __IO uint32_t RPD6 : 1; - __IO uint32_t RPD7 : 1; - __IO uint32_t RPD8 : 1; - __IO uint32_t RPD9 : 1; - __IO uint32_t RPD10 : 1; - __IO uint32_t RPD11 : 1; - __IO uint32_t RPD12 : 1; - __IO uint32_t RPD13 : 1; - __IO uint32_t RPD14 : 1; - __IO uint32_t RPD15 : 1; - __IO uint32_t RPD16 : 1; - __IO uint32_t RPD17 : 1; - __IO uint32_t RPD18 : 1; - __IO uint32_t RPD19 : 1; - __IO uint32_t RPD20 : 1; - __IO uint32_t RPD21 : 1; - __IO uint32_t RPD22 : 1; - __IO uint32_t RPD23 : 1; - __IO uint32_t RPD24 : 1; - __IO uint32_t RPD25 : 1; - __IO uint32_t RPD26 : 1; - __IO uint32_t RPD27 : 1; - __IO uint32_t RPD28 : 1; - __IO uint32_t RPD29 : 1; - __IO uint32_t RPD30 : 1; - __IO uint32_t RPD31 : 1; -} stc_ethernet_mac_rpdr_field_t; - -typedef struct stc_ethernet_mac_rdlar_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t SRL2 : 1; - __IO uint32_t SRL3 : 1; - __IO uint32_t SRL4 : 1; - __IO uint32_t SRL5 : 1; - __IO uint32_t SRL6 : 1; - __IO uint32_t SRL7 : 1; - __IO uint32_t SRL8 : 1; - __IO uint32_t SRL9 : 1; - __IO uint32_t SRL10 : 1; - __IO uint32_t SRL11 : 1; - __IO uint32_t SRL12 : 1; - __IO uint32_t SRL13 : 1; - __IO uint32_t SRL14 : 1; - __IO uint32_t SRL15 : 1; - __IO uint32_t SRL16 : 1; - __IO uint32_t SRL17 : 1; - __IO uint32_t SRL18 : 1; - __IO uint32_t SRL19 : 1; - __IO uint32_t SRL20 : 1; - __IO uint32_t SRL21 : 1; - __IO uint32_t SRL22 : 1; - __IO uint32_t SRL23 : 1; - __IO uint32_t SRL24 : 1; - __IO uint32_t SRL25 : 1; - __IO uint32_t SRL26 : 1; - __IO uint32_t SRL27 : 1; - __IO uint32_t SRL28 : 1; - __IO uint32_t SRL29 : 1; - __IO uint32_t SRL30 : 1; - __IO uint32_t SRL31 : 1; -} stc_ethernet_mac_rdlar_field_t; - -typedef struct stc_ethernet_mac_tdlar_field -{ - uint32_t RESERVED1 : 2; - __IO uint32_t STL2 : 1; - __IO uint32_t STL3 : 1; - __IO uint32_t STL4 : 1; - __IO uint32_t STL5 : 1; - __IO uint32_t STL6 : 1; - __IO uint32_t STL7 : 1; - __IO uint32_t STL8 : 1; - __IO uint32_t STL9 : 1; - __IO uint32_t STL10 : 1; - __IO uint32_t STL11 : 1; - __IO uint32_t STL12 : 1; - __IO uint32_t STL13 : 1; - __IO uint32_t STL14 : 1; - __IO uint32_t STL15 : 1; - __IO uint32_t STL16 : 1; - __IO uint32_t STL17 : 1; - __IO uint32_t STL18 : 1; - __IO uint32_t STL19 : 1; - __IO uint32_t STL20 : 1; - __IO uint32_t STL21 : 1; - __IO uint32_t STL22 : 1; - __IO uint32_t STL23 : 1; - __IO uint32_t STL24 : 1; - __IO uint32_t STL25 : 1; - __IO uint32_t STL26 : 1; - __IO uint32_t STL27 : 1; - __IO uint32_t STL28 : 1; - __IO uint32_t STL29 : 1; - __IO uint32_t STL30 : 1; - __IO uint32_t STL31 : 1; -} stc_ethernet_mac_tdlar_field_t; - -typedef struct stc_ethernet_mac_sr_field -{ - __IO uint32_t TI : 1; - __IO uint32_t TPS : 1; - __IO uint32_t TU : 1; - __IO uint32_t TJT : 1; - __IO uint32_t OVF : 1; - __IO uint32_t UNF : 1; - __IO uint32_t RI : 1; - __IO uint32_t RU : 1; - __IO uint32_t RPS : 1; - __IO uint32_t RWT : 1; - __IO uint32_t ETI : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t FBI : 1; - __IO uint32_t ERI : 1; - __IO uint32_t AIS : 1; - __IO uint32_t NIS : 1; - __IO uint32_t RS0 : 1; - __IO uint32_t RS1 : 1; - __IO uint32_t RS2 : 1; - __IO uint32_t TS0 : 1; - __IO uint32_t TS1 : 1; - __IO uint32_t TS2 : 1; - __IO uint32_t EB0 : 1; - __IO uint32_t EB1 : 1; - __IO uint32_t EB2 : 1; - __IO uint32_t GLI : 1; - __IO uint32_t GMI : 1; - __IO uint32_t GPI : 1; - __IO uint32_t TTI : 1; - __IO uint32_t GLPII : 1; -} stc_ethernet_mac_sr_field_t; - -typedef struct stc_ethernet_mac_omr_field -{ - uint32_t RESERVED1 : 1; - __IO uint32_t SR : 1; - __IO uint32_t OSF : 1; - __IO uint32_t RTC0 : 1; - __IO uint32_t RTC1 : 1; - uint32_t RESERVED2 : 1; - __IO uint32_t FUF : 1; - __IO uint32_t FEF : 1; - uint32_t RESERVED3 : 5; - __IO uint32_t ST : 1; - __IO uint32_t TTC0 : 1; - __IO uint32_t TTC1 : 1; - __IO uint32_t TTC2 : 1; - uint32_t RESERVED4 : 3; - __IO uint32_t FTF : 1; - __IO uint32_t TSF : 1; - uint32_t RESERVED5 : 2; - __IO uint32_t DFF : 1; - __IO uint32_t RSF : 1; - __IO uint32_t DT : 1; -} stc_ethernet_mac_omr_field_t; - -typedef struct stc_ethernet_mac_ier_field -{ - __IO uint32_t TIE : 1; - __IO uint32_t TSE : 1; - __IO uint32_t TUE : 1; - __IO uint32_t TJE : 1; - __IO uint32_t OVE : 1; - __IO uint32_t UNE : 1; - __IO uint32_t RIE : 1; - __IO uint32_t RUE : 1; - __IO uint32_t RSE : 1; - __IO uint32_t RWE : 1; - __IO uint32_t ETE : 1; - uint32_t RESERVED1 : 2; - __IO uint32_t FBE : 1; - __IO uint32_t ERE : 1; - __IO uint32_t AIE : 1; - __IO uint32_t NIE : 1; -} stc_ethernet_mac_ier_field_t; - -typedef struct stc_ethernet_mac_mfbocr_field -{ - __IO uint32_t NMFH0 : 1; - __IO uint32_t NMFH1 : 1; - __IO uint32_t NMFH2 : 1; - __IO uint32_t NMFH3 : 1; - __IO uint32_t NMFH4 : 1; - __IO uint32_t NMFH5 : 1; - __IO uint32_t NMFH6 : 1; - __IO uint32_t NMFH7 : 1; - __IO uint32_t NMFH8 : 1; - __IO uint32_t NMFH9 : 1; - __IO uint32_t NMFH10 : 1; - __IO uint32_t NMFH11 : 1; - __IO uint32_t NMFH12 : 1; - __IO uint32_t NMFH13 : 1; - __IO uint32_t NMFH14 : 1; - __IO uint32_t NMFH15 : 1; - __IO uint32_t ONMFH : 1; - __IO uint32_t NMFF0 : 1; - __IO uint32_t NMFF1 : 1; - __IO uint32_t NMFF2 : 1; - __IO uint32_t NMFF3 : 1; - __IO uint32_t NMFF4 : 1; - __IO uint32_t NMFF5 : 1; - __IO uint32_t NMFF6 : 1; - __IO uint32_t NMFF7 : 1; - __IO uint32_t NMFF8 : 1; - __IO uint32_t NMFF9 : 1; - __IO uint32_t NMFF10 : 1; - __IO uint32_t ONMFF : 1; -} stc_ethernet_mac_mfbocr_field_t; - -typedef struct stc_ethernet_mac_riwtr_field -{ - __IO uint32_t RIWT0 : 1; - __IO uint32_t RIWT1 : 1; - __IO uint32_t RIWT2 : 1; - __IO uint32_t RIWT3 : 1; - __IO uint32_t RIWT4 : 1; - __IO uint32_t RIWT5 : 1; - __IO uint32_t RIWT6 : 1; - __IO uint32_t RIWT7 : 1; -} stc_ethernet_mac_riwtr_field_t; - -typedef struct stc_ethernet_mac_ahbsr_field -{ - __IO uint32_t AHBS : 1; -} stc_ethernet_mac_ahbsr_field_t; - -typedef struct stc_ethernet_mac_chtdr_field -{ - __IO uint32_t HTDAP0 : 1; - __IO uint32_t HTDAP1 : 1; - __IO uint32_t HTDAP2 : 1; - __IO uint32_t HTDAP3 : 1; - __IO uint32_t HTDAP4 : 1; - __IO uint32_t HTDAP5 : 1; - __IO uint32_t HTDAP6 : 1; - __IO uint32_t HTDAP7 : 1; - __IO uint32_t HTDAP8 : 1; - __IO uint32_t HTDAP9 : 1; - __IO uint32_t HTDAP10 : 1; - __IO uint32_t HTDAP11 : 1; - __IO uint32_t HTDAP12 : 1; - __IO uint32_t HTDAP13 : 1; - __IO uint32_t HTDAP14 : 1; - __IO uint32_t HTDAP15 : 1; - __IO uint32_t HTDAP16 : 1; - __IO uint32_t HTDAP17 : 1; - __IO uint32_t HTDAP18 : 1; - __IO uint32_t HTDAP19 : 1; - __IO uint32_t HTDAP20 : 1; - __IO uint32_t HTDAP21 : 1; - __IO uint32_t HTDAP22 : 1; - __IO uint32_t HTDAP23 : 1; - __IO uint32_t HTDAP24 : 1; - __IO uint32_t HTDAP25 : 1; - __IO uint32_t HTDAP26 : 1; - __IO uint32_t HTDAP27 : 1; - __IO uint32_t HTDAP28 : 1; - __IO uint32_t HTDAP29 : 1; - __IO uint32_t HTDAP30 : 1; - __IO uint32_t HTDAP31 : 1; -} stc_ethernet_mac_chtdr_field_t; - -typedef struct stc_ethernet_mac_chrdr_field -{ - __IO uint32_t HRDAP0 : 1; - __IO uint32_t HRDAP1 : 1; - __IO uint32_t HRDAP2 : 1; - __IO uint32_t HRDAP3 : 1; - __IO uint32_t HRDAP4 : 1; - __IO uint32_t HRDAP5 : 1; - __IO uint32_t HRDAP6 : 1; - __IO uint32_t HRDAP7 : 1; - __IO uint32_t HRDAP8 : 1; - __IO uint32_t HRDAP9 : 1; - __IO uint32_t HRDAP10 : 1; - __IO uint32_t HRDAP11 : 1; - __IO uint32_t HRDAP12 : 1; - __IO uint32_t HRDAP13 : 1; - __IO uint32_t HRDAP14 : 1; - __IO uint32_t HRDAP15 : 1; - __IO uint32_t HRDAP16 : 1; - __IO uint32_t HRDAP17 : 1; - __IO uint32_t HRDAP18 : 1; - __IO uint32_t HRDAP19 : 1; - __IO uint32_t HRDAP20 : 1; - __IO uint32_t HRDAP21 : 1; - __IO uint32_t HRDAP22 : 1; - __IO uint32_t HRDAP23 : 1; - __IO uint32_t HRDAP24 : 1; - __IO uint32_t HRDAP25 : 1; - __IO uint32_t HRDAP26 : 1; - __IO uint32_t HRDAP27 : 1; - __IO uint32_t HRDAP28 : 1; - __IO uint32_t HRDAP29 : 1; - __IO uint32_t HRDAP30 : 1; - __IO uint32_t HRDAP31 : 1; -} stc_ethernet_mac_chrdr_field_t; - -typedef struct stc_ethernet_mac_chtbar_field -{ - __IO uint32_t HTBAR0 : 1; - __IO uint32_t HTBAR1 : 1; - __IO uint32_t HTBAR2 : 1; - __IO uint32_t HTBAR3 : 1; - __IO uint32_t HTBAR4 : 1; - __IO uint32_t HTBAR5 : 1; - __IO uint32_t HTBAR6 : 1; - __IO uint32_t HTBAR7 : 1; - __IO uint32_t HTBAR8 : 1; - __IO uint32_t HTBAR9 : 1; - __IO uint32_t HTBAR10 : 1; - __IO uint32_t HTBAR11 : 1; - __IO uint32_t HTBAR12 : 1; - __IO uint32_t HTBAR13 : 1; - __IO uint32_t HTBAR14 : 1; - __IO uint32_t HTBAR15 : 1; - __IO uint32_t HTBAR16 : 1; - __IO uint32_t HTBAR17 : 1; - __IO uint32_t HTBAR18 : 1; - __IO uint32_t HTBAR19 : 1; - __IO uint32_t HTBAR20 : 1; - __IO uint32_t HTBAR21 : 1; - __IO uint32_t HTBAR22 : 1; - __IO uint32_t HTBAR23 : 1; - __IO uint32_t HTBAR24 : 1; - __IO uint32_t HTBAR25 : 1; - __IO uint32_t HTBAR26 : 1; - __IO uint32_t HTBAR27 : 1; - __IO uint32_t HTBAR28 : 1; - __IO uint32_t HTBAR29 : 1; - __IO uint32_t HTBAR30 : 1; - __IO uint32_t HTBAR31 : 1; -} stc_ethernet_mac_chtbar_field_t; - -typedef struct stc_ethernet_mac_chrbar_field -{ - __IO uint32_t HRBAR0 : 1; - __IO uint32_t HRBAR1 : 1; - __IO uint32_t HRBAR2 : 1; - __IO uint32_t HRBAR3 : 1; - __IO uint32_t HRBAR4 : 1; - __IO uint32_t HRBAR5 : 1; - __IO uint32_t HRBAR6 : 1; - __IO uint32_t HRBAR7 : 1; - __IO uint32_t HRBAR8 : 1; - __IO uint32_t HRBAR9 : 1; - __IO uint32_t HRBAR10 : 1; - __IO uint32_t HRBAR11 : 1; - __IO uint32_t HRBAR12 : 1; - __IO uint32_t HRBAR13 : 1; - __IO uint32_t HRBAR14 : 1; - __IO uint32_t HRBAR15 : 1; - __IO uint32_t HRBAR16 : 1; - __IO uint32_t HRBAR17 : 1; - __IO uint32_t HRBAR18 : 1; - __IO uint32_t HRBAR19 : 1; - __IO uint32_t HRBAR20 : 1; - __IO uint32_t HRBAR21 : 1; - __IO uint32_t HRBAR22 : 1; - __IO uint32_t HRBAR23 : 1; - __IO uint32_t HRBAR24 : 1; - __IO uint32_t HRBAR25 : 1; - __IO uint32_t HRBAR26 : 1; - __IO uint32_t HRBAR27 : 1; - __IO uint32_t HRBAR28 : 1; - __IO uint32_t HRBAR29 : 1; - __IO uint32_t HRBAR30 : 1; - __IO uint32_t HRBAR31 : 1; -} stc_ethernet_mac_chrbar_field_t; - -/* ETHERNET_CONTROL_MODULE register bit fields */ -typedef struct stc_ethernet_control_eth_mode_field -{ - __IO uint32_t IFMODE : 1; - uint32_t RESERVED1 : 7; - __IO uint32_t RST0 : 1; - __IO uint32_t RST1 : 1; - uint32_t RESERVED2 :18; - __IO uint32_t ASZPPSSEL : 1; -} stc_ethernet_control_eth_mode_field_t; - -typedef struct stc_ethernet_control_eth_clkg_field -{ - __IO uint32_t MACEN0 : 1; - __IO uint32_t MACEN1 : 1; -} stc_ethernet_control_eth_clkg_field_t; - -/****************************************************************************** - * Peripheral register structures - ******************************************************************************/ - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - union { - __IO uint32_t FASZR; - stc_flash_if_faszr_field_t FASZR_f; - }; - union { - __IO uint32_t FRWTR; - stc_flash_if_frwtr_field_t FRWTR_f; - }; - union { - __IO uint32_t FSTR; - stc_flash_if_fstr_field_t FSTR_f; - }; - uint8_t RESERVED0[4]; - union { - __IO uint32_t FSYNDN; - stc_flash_if_fsyndn_field_t FSYNDN_f; - }; - union { - __IO uint32_t FBFCR; - stc_flash_if_fbfcr_field_t FBFCR_f; - }; - uint8_t RESERVED1[232]; - union { - __IO uint32_t CRTRMM; - stc_flash_if_crtrmm_field_t CRTRMM_f; - }; -}FM3_FLASH_IF_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - union { - __IO uint8_t SCM_CTL; - stc_crg_scm_ctl_field_t SCM_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t SCM_STR; - stc_crg_scm_str_field_t SCM_STR_f; - }; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - union { - __IO uint16_t RST_STR; - stc_crg_rst_str_field_t RST_STR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t BSC_PSR; - stc_crg_bsc_psr_field_t BSC_PSR_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t APBC0_PSR; - stc_crg_apbc0_psr_field_t APBC0_PSR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t APBC1_PSR; - stc_crg_apbc1_psr_field_t APBC1_PSR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t APBC2_PSR; - stc_crg_apbc2_psr_field_t APBC2_PSR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t SWC_PSR; - stc_crg_swc_psr_field_t SWC_PSR_f; - }; - uint8_t RESERVED7[7]; - union { - __IO uint8_t TTC_PSR; - stc_crg_ttc_psr_field_t TTC_PSR_f; - }; - uint8_t RESERVED8[7]; - union { - __IO uint8_t CSW_TMR; - stc_crg_csw_tmr_field_t CSW_TMR_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t PSW_TMR; - stc_crg_psw_tmr_field_t PSW_TMR_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PLL_CTL1; - stc_crg_pll_ctl1_field_t PLL_CTL1_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t PLL_CTL2; - stc_crg_pll_ctl2_field_t PLL_CTL2_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint16_t CSV_CTL; - stc_crg_csv_ctl_field_t CSV_CTL_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint8_t CSV_STR; - stc_crg_csv_str_field_t CSV_STR_f; - }; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - union { - __IO uint8_t DBWDT_CTL; - stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; - }; - uint8_t RESERVED18[11]; - union { - __IO uint8_t INT_ENR; - stc_crg_int_enr_field_t INT_ENR_f; - }; - uint8_t RESERVED19[3]; - union { - __IO uint8_t INT_STR; - stc_crg_int_str_field_t INT_STR_f; - }; - uint8_t RESERVED20[3]; - union { - __IO uint8_t INT_CLR; - stc_crg_int_clr_field_t INT_CLR_f; - }; -}FM3_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - union { - __IO uint8_t WDG_CTL; - stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; - }; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - union { - __IO uint8_t WDG_RIS; - stc_hwwdt_wdg_ris_field_t WDG_RIS_f; - }; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM3_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - union { - __IO uint8_t WDOGCONTROL; - stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - union { - __IO uint8_t WDOGRIS; - stc_swwdt_wdogris_field_t WDOGRIS_f; - }; - uint8_t RESERVED1[3055]; - __IO uint32_t WDOGLOCK; -}FM3_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMER1LOAD; - __IO uint32_t TIMER1VALUE; - union { - __IO uint32_t TIMER1CONTROL; - stc_dtim_timer1control_field_t TIMER1CONTROL_f; - }; - __IO uint32_t TIMER1INTCLR; - union { - __IO uint32_t TIMER1RIS; - stc_dtim_timer1ris_field_t TIMER1RIS_f; - }; - union { - __IO uint32_t TIMER1MIS; - stc_dtim_timer1mis_field_t TIMER1MIS_f; - }; - __IO uint32_t TIMER1BGLOAD; - uint8_t RESERVED0[4]; - __IO uint32_t TIMER2LOAD; - __IO uint32_t TIMER2VALUE; - union { - __IO uint32_t TIMER2CONTROL; - stc_dtim_timer2control_field_t TIMER2CONTROL_f; - }; - __IO uint32_t TIMER2INTCLR; - union { - __IO uint32_t TIMER2RIS; - stc_dtim_timer2ris_field_t TIMER2RIS_f; - }; - union { - __IO uint32_t TIMER2MIS; - stc_dtim_timer2mis_field_t TIMER2MIS_f; - }; - __IO uint32_t TIMER2BGLOAD; -}FM3_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[40]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TCSA0; - stc_mft_frt_tcsa0_field_t TCSA0_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t TCSB0; - stc_mft_frt_tcsb0_field_t TCSB0_f; - }; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT1; - uint8_t RESERVED6[2]; - union { - __IO uint16_t TCSA1; - stc_mft_frt_tcsa1_field_t TCSA1_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t TCSB1; - stc_mft_frt_tcsb1_field_t TCSB1_f; - }; - uint8_t RESERVED8[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED9[2]; - __IO uint16_t TCDT2; - uint8_t RESERVED10[2]; - union { - __IO uint16_t TCSA2; - stc_mft_frt_tcsa2_field_t TCSA2_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t TCSB2; - stc_mft_frt_tcsb2_field_t TCSB2_f; - }; -}FM3_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - __IO uint16_t OCCP0; - uint8_t RESERVED0[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP5; - uint8_t RESERVED5[2]; - union { - __IO uint8_t OCSA10; - stc_mft_ocu_ocsa10_field_t OCSA10_f; - }; - union { - __IO uint8_t OCSB10; - stc_mft_ocu_ocsb10_field_t OCSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t OCSA32; - stc_mft_ocu_ocsa32_field_t OCSA32_f; - }; - union { - __IO uint8_t OCSB32; - stc_mft_ocu_ocsb32_field_t OCSB32_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint8_t OCSA54; - stc_mft_ocu_ocsa54_field_t OCSA54_f; - }; - union { - __IO uint8_t OCSB54; - stc_mft_ocu_ocsb54_field_t OCSB54_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t OCSC; - stc_mft_ocu_ocsc_field_t OCSC_f; - }; - uint8_t RESERVED9[50]; - union { - __IO uint8_t OCFS10; - stc_mft_ocu_ocfs10_field_t OCFS10_f; - }; - union { - __IO uint8_t OCFS32; - stc_mft_ocu_ocfs32_field_t OCFS32_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint8_t OCFS54; - stc_mft_ocu_ocfs54_field_t OCFS54_f; - }; -}FM3_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[128]; - __IO uint16_t WFTM10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTM32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTM54; - uint8_t RESERVED3[2]; - union { - __IO uint16_t WFSA10; - stc_mft_wfg_wfsa10_field_t WFSA10_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t WFSA32; - stc_mft_wfg_wfsa32_field_t WFSA32_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t WFSA54; - stc_mft_wfg_wfsa54_field_t WFSA54_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t WFIR; - stc_mft_wfg_wfir_field_t WFIR_f; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t NZCL; - stc_mft_wfg_nzcl_field_t NZCL_f; - }; -}FM3_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[96]; - union { - __IO uint8_t ICFS10; - stc_mft_icu_icfs10_field_t ICFS10_f; - }; - union { - __IO uint8_t ICFS32; - stc_mft_icu_icfs32_field_t ICFS32_f; - }; - uint8_t RESERVED1[6]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - uint8_t RESERVED5[2]; - union { - __IO uint8_t ICSA10; - stc_mft_icu_icsa10_field_t ICSA10_f; - }; - union { - __IO uint8_t ICSB10; - stc_mft_icu_icsb10_field_t ICSB10_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ICSA32; - stc_mft_icu_icsa32_field_t ICSA32_f; - }; - union { - __IO uint8_t ICSB32; - stc_mft_icu_icsb32_field_t ICSB32_f; - }; -}FM3_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[160]; - __IO uint16_t ACCP0; - uint8_t RESERVED1[2]; - __IO uint16_t ACCPDN0; - uint8_t RESERVED2[2]; - __IO uint16_t ACCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACCPDN1; - uint8_t RESERVED4[2]; - __IO uint16_t ACCP2; - uint8_t RESERVED5[2]; - __IO uint16_t ACCPDN2; - uint8_t RESERVED6[2]; - union { - __IO uint8_t ACSB; - stc_mft_adcmp_acsb_field_t ACSB_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t ACSA; - stc_mft_adcmp_acsa_field_t ACSA_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t ATSA; - stc_mft_adcmp_atsa_field_t ATSA_f; - }; -}FM3_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t TTCR0; - stc_mft_ppg_ttcr0_field_t TTCR0_f; - }; - uint8_t RESERVED1[7]; - __IO uint8_t COMP0; - uint8_t RESERVED2[2]; - __IO uint8_t COMP2; - uint8_t RESERVED3[4]; - __IO uint8_t COMP4; - uint8_t RESERVED4[2]; - __IO uint8_t COMP6; - uint8_t RESERVED5[12]; - union { - __IO uint8_t TTCR1; - stc_mft_ppg_ttcr1_field_t TTCR1_f; - }; - uint8_t RESERVED6[7]; - __IO uint8_t COMP1; - uint8_t RESERVED7[2]; - __IO uint8_t COMP3; - uint8_t RESERVED8[4]; - __IO uint8_t COMP5; - uint8_t RESERVED9[2]; - __IO uint8_t COMP7; - uint8_t RESERVED10[12]; - union { - __IO uint8_t TTCR2; - stc_mft_ppg_ttcr2_field_t TTCR2_f; - }; - uint8_t RESERVED11[7]; - __IO uint8_t COMP8; - uint8_t RESERVED12[2]; - __IO uint8_t COMP10; - uint8_t RESERVED13[4]; - __IO uint8_t COMP12; - uint8_t RESERVED14[2]; - __IO uint8_t COMP14; - uint8_t RESERVED15[171]; - union { - __IO uint16_t TRG; - stc_mft_ppg_trg_field_t TRG_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t REVC; - stc_mft_ppg_revc_field_t REVC_f; - }; - uint8_t RESERVED17[58]; - union { - __IO uint16_t TRG1; - stc_mft_ppg_trg1_field_t TRG1_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t REVC1; - stc_mft_ppg_revc1_field_t REVC1_f; - }; - uint8_t RESERVED19[186]; - union { - __IO uint8_t PPGC1; - stc_mft_ppg_ppgc1_field_t PPGC1_f; - }; - union { - __IO uint8_t PPGC0; - stc_mft_ppg_ppgc0_field_t PPGC0_f; - }; - uint8_t RESERVED20[2]; - union { - __IO uint8_t PPGC3; - stc_mft_ppg_ppgc3_field_t PPGC3_f; - }; - union { - __IO uint8_t PPGC2; - stc_mft_ppg_ppgc2_field_t PPGC2_f; - }; - uint8_t RESERVED21[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint8_t GATEC0; - stc_mft_ppg_gatec0_field_t GATEC0_f; - }; - uint8_t RESERVED26[39]; - union { - __IO uint8_t PPGC5; - stc_mft_ppg_ppgc5_field_t PPGC5_f; - }; - union { - __IO uint8_t PPGC4; - stc_mft_ppg_ppgc4_field_t PPGC4_f; - }; - uint8_t RESERVED27[2]; - union { - __IO uint8_t PPGC7; - stc_mft_ppg_ppgc7_field_t PPGC7_f; - }; - union { - __IO uint8_t PPGC6; - stc_mft_ppg_ppgc6_field_t PPGC6_f; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED30[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED31[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED32[2]; - union { - __IO uint8_t GATEC4; - stc_mft_ppg_gatec4_field_t GATEC4_f; - }; - uint8_t RESERVED33[39]; - union { - __IO uint8_t PPGC9; - stc_mft_ppg_ppgc9_field_t PPGC9_f; - }; - union { - __IO uint8_t PPGC8; - stc_mft_ppg_ppgc8_field_t PPGC8_f; - }; - uint8_t RESERVED34[2]; - union { - __IO uint8_t PPGC11; - stc_mft_ppg_ppgc11_field_t PPGC11_f; - }; - union { - __IO uint8_t PPGC10; - stc_mft_ppg_ppgc10_field_t PPGC10_f; - }; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED37[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED38[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED39[2]; - union { - __IO uint8_t GATEC8; - stc_mft_ppg_gatec8_field_t GATEC8_f; - }; - uint8_t RESERVED40[39]; - union { - __IO uint8_t PPGC13; - stc_mft_ppg_ppgc13_field_t PPGC13_f; - }; - union { - __IO uint8_t PPGC12; - stc_mft_ppg_ppgc12_field_t PPGC12_f; - }; - uint8_t RESERVED41[2]; - union { - __IO uint8_t PPGC15; - stc_mft_ppg_ppgc15_field_t PPGC15_f; - }; - union { - __IO uint8_t PPGC14; - stc_mft_ppg_ppgc14_field_t PPGC14_f; - }; - uint8_t RESERVED42[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED43[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED44[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED45[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED46[2]; - union { - __IO uint8_t GATEC12; - stc_mft_ppg_gatec12_field_t GATEC12_f; - }; - uint8_t RESERVED47[39]; - union { - __IO uint8_t PPGC17; - stc_mft_ppg_ppgc17_field_t PPGC17_f; - }; - union { - __IO uint8_t PPGC16; - stc_mft_ppg_ppgc16_field_t PPGC16_f; - }; - uint8_t RESERVED48[2]; - union { - __IO uint8_t PPGC19; - stc_mft_ppg_ppgc19_field_t PPGC19_f; - }; - union { - __IO uint8_t PPGC18; - stc_mft_ppg_ppgc18_field_t PPGC18_f; - }; - uint8_t RESERVED49[2]; - union { - __IO uint16_t PRL16; - struct { - __IO uint8_t PRLL16; - __IO uint8_t PRLH16; - }; - }; - uint8_t RESERVED50[2]; - union { - __IO uint16_t PRL17; - struct { - __IO uint8_t PRLL17; - __IO uint8_t PRLH17; - }; - }; - uint8_t RESERVED51[2]; - union { - __IO uint16_t PRL18; - struct { - __IO uint8_t PRLL18; - __IO uint8_t PRLH18; - }; - }; - uint8_t RESERVED52[2]; - union { - __IO uint16_t PRL19; - struct { - __IO uint8_t PRLL19; - __IO uint8_t PRLH19; - }; - }; - uint8_t RESERVED53[2]; - union { - __IO uint8_t GATEC16; - stc_mft_ppg_gatec16_field_t GATEC16_f; - }; - uint8_t RESERVED54[39]; - union { - __IO uint8_t PPGC21; - stc_mft_ppg_ppgc21_field_t PPGC21_f; - }; - union { - __IO uint8_t PPGC20; - stc_mft_ppg_ppgc20_field_t PPGC20_f; - }; - uint8_t RESERVED55[2]; - union { - __IO uint8_t PPGC23; - stc_mft_ppg_ppgc23_field_t PPGC23_f; - }; - union { - __IO uint8_t PPGC22; - stc_mft_ppg_ppgc22_field_t PPGC22_f; - }; - uint8_t RESERVED56[2]; - union { - __IO uint16_t PRL20; - struct { - __IO uint8_t PRLL20; - __IO uint8_t PRLH20; - }; - }; - uint8_t RESERVED57[2]; - union { - __IO uint16_t PRL21; - struct { - __IO uint8_t PRLL21; - __IO uint8_t PRLH21; - }; - }; - uint8_t RESERVED58[2]; - union { - __IO uint16_t PRL22; - struct { - __IO uint8_t PRLL22; - __IO uint8_t PRLH22; - }; - }; - uint8_t RESERVED59[2]; - union { - __IO uint16_t PRL23; - struct { - __IO uint8_t PRLL23; - __IO uint8_t PRLH23; - }; - }; - uint8_t RESERVED60[2]; - union { - __IO uint8_t GATEC20; - stc_mft_ppg_gatec20_field_t GATEC20_f; - }; -}FM3_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_ppg_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_ppg_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_ppg_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - union { - __IO uint16_t TMCR; - stc_bt_pwm_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t STC; - stc_bt_pwm_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwm_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t TMCR; - stc_bt_rt_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_rt_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_rt_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - union { - __IO uint16_t TMCR; - stc_bt_pwc_tmcr_field_t TMCR_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint8_t STC; - stc_bt_pwc_stc_field_t STC_f; - }; - union { - __IO uint8_t TMCR2; - stc_bt_pwc_tmcr2_field_t TMCR2_f; - }; -}FM3_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL0123; - stc_btiosel03_btsel0123_field_t BTSEL0123_f; - }; -}FM3_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL4567; - stc_btiosel47_btsel4567_field_t BTSEL4567_f; - }; -}FM3_BTIOSEL47_TypeDef; - -/****************************************************************************** - * BTIOSEL8B_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 8 - channel 11 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSEL89AB; - stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; - }; -}FM3_BTIOSEL8B_TypeDef; - -/****************************************************************************** - * BTIOSELCF_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 12 - channel 15 registers */ -typedef struct -{ - uint8_t RESERVED0; - union { - __IO uint8_t BTSELCDEF; - stc_btioselcf_btselcdef_field_t BTSELCDEF_f; - }; -}FM3_BTIOSELCF_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - union { - __IO uint16_t BTSSSR; - stc_sbssr_btsssr_field_t BTSSSR_f; - }; -}FM3_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t QICR; - stc_qprc_qicr_field_t QICR_f; - }; - struct { - union { - __IO uint8_t QICRL; - stc_qprc_qicrl_field_t QICRL_f; - }; - union { - __IO uint8_t QICRH; - stc_qprc_qicrh_field_t QICRH_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t QCR; - stc_qprc_qcr_field_t QCR_f; - }; - struct { - union { - __IO uint8_t QCRL; - stc_qprc_qcrl_field_t QCRL_f; - }; - union { - __IO uint8_t QCRH; - stc_qprc_qcrh_field_t QCRH_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t QECR; - stc_qprc_qecr_field_t QECR_f; - }; - uint8_t RESERVED7[30]; - __IO uint16_t QRCRR; - __IO uint16_t QPCRR; -}FM3_QPRC_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - union { - __IO uint8_t ADSR; - stc_adc_adsr_field_t ADSR_f; - }; - union { - __IO uint8_t ADCR; - stc_adc_adcr_field_t ADCR_f; - }; - uint8_t RESERVED0[6]; - union { - __IO uint8_t SFNS; - stc_adc_sfns_field_t SFNS_f; - }; - union { - __IO uint8_t SCCR; - stc_adc_sccr_field_t SCCR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint32_t SCFD; - stc_adc_scfd_field_t SCFD_f; - }; - struct { - union { - __IO uint16_t SCFDL; - stc_adc_scfdl_field_t SCFDL_f; - }; - union { - __IO uint16_t SCFDH; - stc_adc_scfdh_field_t SCFDH_f; - }; - }; - }; - union { - union { - __IO uint16_t SCIS23; - stc_adc_scis23_field_t SCIS23_f; - }; - struct { - union { - __IO uint8_t SCIS2; - stc_adc_scis2_field_t SCIS2_f; - }; - union { - __IO uint8_t SCIS3; - stc_adc_scis3_field_t SCIS3_f; - }; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t SCIS01; - stc_adc_scis01_field_t SCIS01_f; - }; - struct { - union { - __IO uint8_t SCIS0; - stc_adc_scis0_field_t SCIS0_f; - }; - union { - __IO uint8_t SCIS1; - stc_adc_scis1_field_t SCIS1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t PFNS; - stc_adc_pfns_field_t PFNS_f; - }; - union { - __IO uint8_t PCCR; - stc_adc_pccr_field_t PCCR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint32_t PCFD; - stc_adc_pcfd_field_t PCFD_f; - }; - struct { - union { - __IO uint16_t PCFDL; - stc_adc_pcfdl_field_t PCFDL_f; - }; - union { - __IO uint16_t PCFDH; - stc_adc_pcfdh_field_t PCFDH_f; - }; - }; - }; - union { - __IO uint8_t PCIS; - stc_adc_pcis_field_t PCIS_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t CMPCR; - stc_adc_cmpcr_field_t CMPCR_f; - }; - uint8_t RESERVED6; - union { - __IO uint16_t CMPD; - stc_adc_cmpd_field_t CMPD_f; - }; - union { - union { - __IO uint16_t ADSS23; - stc_adc_adss23_field_t ADSS23_f; - }; - struct { - union { - __IO uint8_t ADSS2; - stc_adc_adss2_field_t ADSS2_f; - }; - union { - __IO uint8_t ADSS3; - stc_adc_adss3_field_t ADSS3_f; - }; - }; - }; - uint8_t RESERVED7[2]; - union { - union { - __IO uint16_t ADSS01; - stc_adc_adss01_field_t ADSS01_f; - }; - struct { - union { - __IO uint8_t ADSS0; - stc_adc_adss0_field_t ADSS0_f; - }; - union { - __IO uint8_t ADSS1; - stc_adc_adss1_field_t ADSS1_f; - }; - }; - }; - uint8_t RESERVED8[2]; - union { - union { - __IO uint16_t ADST01; - stc_adc_adst01_field_t ADST01_f; - }; - struct { - union { - __IO uint8_t ADST1; - stc_adc_adst1_field_t ADST1_f; - }; - union { - __IO uint8_t ADST0; - stc_adc_adst0_field_t ADST0_f; - }; - }; - }; - uint8_t RESERVED9[2]; - union { - __IO uint8_t ADCT; - stc_adc_adct_field_t ADCT_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t PRTSL; - stc_adc_prtsl_field_t PRTSL_f; - }; - union { - __IO uint8_t SCTSL; - stc_adc_sctsl_field_t SCTSL_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint8_t ADCEN; - stc_adc_adcen_field_t ADCEN_f; - }; -}FM3_ADC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - union { - __IO uint8_t MCR_PSR; - stc_crtrim_mcr_psr_field_t MCR_PSR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint16_t MCR_FTRM; - stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; - }; - uint8_t RESERVED1[6]; - __IO uint32_t MCR_RLR; -}FM3_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - union { - __IO uint32_t ENIR; - stc_exti_enir_field_t ENIR_f; - }; - union { - __IO uint32_t EIRR; - stc_exti_eirr_field_t EIRR_f; - }; - union { - __IO uint32_t EICL; - stc_exti_eicl_field_t EICL_f; - }; - union { - __IO uint32_t ELVR; - stc_exti_elvr_field_t ELVR_f; - }; - union { - __IO uint32_t ELVR1; - stc_exti_elvr1_field_t ELVR1_f; - }; - union { - __IO uint8_t NMIRR; - stc_exti_nmirr_field_t NMIRR_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t NMICL; - stc_exti_nmicl_field_t NMICL_f; - }; -}FM3_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - union { - __IO uint32_t DRQSEL; - stc_intreq_drqsel_field_t DRQSEL_f; - }; - uint8_t RESERVED0[7]; - union { - __IO uint8_t ODDPKS; - stc_intreq_oddpks_field_t ODDPKS_f; - }; - uint8_t RESERVED1[4]; - union { - __IO uint32_t EXC02MON; - stc_intreq_exc02mon_field_t EXC02MON_f; - }; - union { - __IO uint32_t IRQ00MON; - stc_intreq_irq00mon_field_t IRQ00MON_f; - }; - union { - __IO uint32_t IRQ01MON; - stc_intreq_irq01mon_field_t IRQ01MON_f; - }; - union { - __IO uint32_t IRQ02MON; - stc_intreq_irq02mon_field_t IRQ02MON_f; - }; - union { - __IO uint32_t IRQ03MON; - stc_intreq_irq03mon_field_t IRQ03MON_f; - }; - union { - __IO uint32_t IRQ04MON; - stc_intreq_irq04mon_field_t IRQ04MON_f; - }; - union { - __IO uint32_t IRQ05MON; - stc_intreq_irq05mon_field_t IRQ05MON_f; - }; - union { - __IO uint32_t IRQ06MON; - stc_intreq_irq06mon_field_t IRQ06MON_f; - }; - union { - __IO uint32_t IRQ07MON; - stc_intreq_irq07mon_field_t IRQ07MON_f; - }; - union { - __IO uint32_t IRQ08MON; - stc_intreq_irq08mon_field_t IRQ08MON_f; - }; - union { - __IO uint32_t IRQ09MON; - stc_intreq_irq09mon_field_t IRQ09MON_f; - }; - union { - __IO uint32_t IRQ10MON; - stc_intreq_irq10mon_field_t IRQ10MON_f; - }; - union { - __IO uint32_t IRQ11MON; - stc_intreq_irq11mon_field_t IRQ11MON_f; - }; - union { - __IO uint32_t IRQ12MON; - stc_intreq_irq12mon_field_t IRQ12MON_f; - }; - union { - __IO uint32_t IRQ13MON; - stc_intreq_irq13mon_field_t IRQ13MON_f; - }; - union { - __IO uint32_t IRQ14MON; - stc_intreq_irq14mon_field_t IRQ14MON_f; - }; - union { - __IO uint32_t IRQ15MON; - stc_intreq_irq15mon_field_t IRQ15MON_f; - }; - union { - __IO uint32_t IRQ16MON; - stc_intreq_irq16mon_field_t IRQ16MON_f; - }; - union { - __IO uint32_t IRQ17MON; - stc_intreq_irq17mon_field_t IRQ17MON_f; - }; - union { - __IO uint32_t IRQ18MON; - stc_intreq_irq18mon_field_t IRQ18MON_f; - }; - union { - __IO uint32_t IRQ19MON; - stc_intreq_irq19mon_field_t IRQ19MON_f; - }; - union { - __IO uint32_t IRQ20MON; - stc_intreq_irq20mon_field_t IRQ20MON_f; - }; - union { - __IO uint32_t IRQ21MON; - stc_intreq_irq21mon_field_t IRQ21MON_f; - }; - union { - __IO uint32_t IRQ22MON; - stc_intreq_irq22mon_field_t IRQ22MON_f; - }; - union { - __IO uint32_t IRQ23MON; - stc_intreq_irq23mon_field_t IRQ23MON_f; - }; - union { - __IO uint32_t IRQ24MON; - stc_intreq_irq24mon_field_t IRQ24MON_f; - }; - union { - __IO uint32_t IRQ25MON; - stc_intreq_irq25mon_field_t IRQ25MON_f; - }; - union { - __IO uint32_t IRQ26MON; - stc_intreq_irq26mon_field_t IRQ26MON_f; - }; - union { - __IO uint32_t IRQ27MON; - stc_intreq_irq27mon_field_t IRQ27MON_f; - }; - union { - __IO uint32_t IRQ28MON; - stc_intreq_irq28mon_field_t IRQ28MON_f; - }; - union { - __IO uint32_t IRQ29MON; - stc_intreq_irq29mon_field_t IRQ29MON_f; - }; - union { - __IO uint32_t IRQ30MON; - stc_intreq_irq30mon_field_t IRQ30MON_f; - }; - union { - __IO uint32_t IRQ31MON; - stc_intreq_irq31mon_field_t IRQ31MON_f; - }; - union { - __IO uint32_t IRQ32MON; - stc_intreq_irq32mon_field_t IRQ32MON_f; - }; - union { - __IO uint32_t IRQ33MON; - stc_intreq_irq33mon_field_t IRQ33MON_f; - }; - union { - __IO uint32_t IRQ34MON; - stc_intreq_irq34mon_field_t IRQ34MON_f; - }; - union { - __IO uint32_t IRQ35MON; - stc_intreq_irq35mon_field_t IRQ35MON_f; - }; - union { - __IO uint32_t IRQ36MON; - stc_intreq_irq36mon_field_t IRQ36MON_f; - }; - union { - __IO uint32_t IRQ37MON; - stc_intreq_irq37mon_field_t IRQ37MON_f; - }; - union { - __IO uint32_t IRQ38MON; - stc_intreq_irq38mon_field_t IRQ38MON_f; - }; - union { - __IO uint32_t IRQ39MON; - stc_intreq_irq39mon_field_t IRQ39MON_f; - }; - union { - __IO uint32_t IRQ40MON; - stc_intreq_irq40mon_field_t IRQ40MON_f; - }; - union { - __IO uint32_t IRQ41MON; - stc_intreq_irq41mon_field_t IRQ41MON_f; - }; - union { - __IO uint32_t IRQ42MON; - stc_intreq_irq42mon_field_t IRQ42MON_f; - }; - union { - __IO uint32_t IRQ43MON; - stc_intreq_irq43mon_field_t IRQ43MON_f; - }; - union { - __IO uint32_t IRQ44MON; - stc_intreq_irq44mon_field_t IRQ44MON_f; - }; - union { - __IO uint32_t IRQ45MON; - stc_intreq_irq45mon_field_t IRQ45MON_f; - }; - union { - __IO uint32_t IRQ46MON; - stc_intreq_irq46mon_field_t IRQ46MON_f; - }; - __IO uint32_t IRQ47MON; - uint8_t RESERVED2[300]; - union { - __IO uint32_t DRQSEL1; - stc_intreq_drqsel1_field_t DRQSEL1_f; - }; - union { - __IO uint32_t DQESEL; - stc_intreq_dqesel_field_t DQESEL_f; - }; - uint8_t RESERVED3[7]; - union { - __IO uint8_t ODDPKS1; - stc_intreq_oddpks1_field_t ODDPKS1_f; - }; -}FM3_INTREQ_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - union { - __IO uint32_t PFR0; - stc_gpio_pfr0_field_t PFR0_f; - }; - union { - __IO uint32_t PFR1; - stc_gpio_pfr1_field_t PFR1_f; - }; - union { - __IO uint32_t PFR2; - stc_gpio_pfr2_field_t PFR2_f; - }; - union { - __IO uint32_t PFR3; - stc_gpio_pfr3_field_t PFR3_f; - }; - union { - __IO uint32_t PFR4; - stc_gpio_pfr4_field_t PFR4_f; - }; - union { - __IO uint32_t PFR5; - stc_gpio_pfr5_field_t PFR5_f; - }; - union { - __IO uint32_t PFR6; - stc_gpio_pfr6_field_t PFR6_f; - }; - union { - __IO uint32_t PFR7; - stc_gpio_pfr7_field_t PFR7_f; - }; - union { - __IO uint32_t PFR8; - stc_gpio_pfr8_field_t PFR8_f; - }; - union { - __IO uint32_t PFR9; - stc_gpio_pfr9_field_t PFR9_f; - }; - union { - __IO uint32_t PFRA; - stc_gpio_pfra_field_t PFRA_f; - }; - union { - __IO uint32_t PFRB; - stc_gpio_pfrb_field_t PFRB_f; - }; - union { - __IO uint32_t PFRC; - stc_gpio_pfrc_field_t PFRC_f; - }; - union { - __IO uint32_t PFRD; - stc_gpio_pfrd_field_t PFRD_f; - }; - union { - __IO uint32_t PFRE; - stc_gpio_pfre_field_t PFRE_f; - }; - union { - __IO uint32_t PFRF; - stc_gpio_pfrf_field_t PFRF_f; - }; - uint8_t RESERVED0[192]; - union { - __IO uint32_t PCR0; - stc_gpio_pcr0_field_t PCR0_f; - }; - union { - __IO uint32_t PCR1; - stc_gpio_pcr1_field_t PCR1_f; - }; - union { - __IO uint32_t PCR2; - stc_gpio_pcr2_field_t PCR2_f; - }; - union { - __IO uint32_t PCR3; - stc_gpio_pcr3_field_t PCR3_f; - }; - union { - __IO uint32_t PCR4; - stc_gpio_pcr4_field_t PCR4_f; - }; - union { - __IO uint32_t PCR5; - stc_gpio_pcr5_field_t PCR5_f; - }; - union { - __IO uint32_t PCR6; - stc_gpio_pcr6_field_t PCR6_f; - }; - union { - __IO uint32_t PCR7; - stc_gpio_pcr7_field_t PCR7_f; - }; - __IO uint32_t PCR8; - union { - __IO uint32_t PCR9; - stc_gpio_pcr9_field_t PCR9_f; - }; - union { - __IO uint32_t PCRA; - stc_gpio_pcra_field_t PCRA_f; - }; - union { - __IO uint32_t PCRB; - stc_gpio_pcrb_field_t PCRB_f; - }; - union { - __IO uint32_t PCRC; - stc_gpio_pcrc_field_t PCRC_f; - }; - union { - __IO uint32_t PCRD; - stc_gpio_pcrd_field_t PCRD_f; - }; - union { - __IO uint32_t PCRE; - stc_gpio_pcre_field_t PCRE_f; - }; - __IO uint32_t PCRF; - uint8_t RESERVED1[192]; - union { - __IO uint32_t DDR0; - stc_gpio_ddr0_field_t DDR0_f; - }; - union { - __IO uint32_t DDR1; - stc_gpio_ddr1_field_t DDR1_f; - }; - union { - __IO uint32_t DDR2; - stc_gpio_ddr2_field_t DDR2_f; - }; - union { - __IO uint32_t DDR3; - stc_gpio_ddr3_field_t DDR3_f; - }; - union { - __IO uint32_t DDR4; - stc_gpio_ddr4_field_t DDR4_f; - }; - union { - __IO uint32_t DDR5; - stc_gpio_ddr5_field_t DDR5_f; - }; - union { - __IO uint32_t DDR6; - stc_gpio_ddr6_field_t DDR6_f; - }; - union { - __IO uint32_t DDR7; - stc_gpio_ddr7_field_t DDR7_f; - }; - union { - __IO uint32_t DDR8; - stc_gpio_ddr8_field_t DDR8_f; - }; - union { - __IO uint32_t DDR9; - stc_gpio_ddr9_field_t DDR9_f; - }; - union { - __IO uint32_t DDRA; - stc_gpio_ddra_field_t DDRA_f; - }; - union { - __IO uint32_t DDRB; - stc_gpio_ddrb_field_t DDRB_f; - }; - union { - __IO uint32_t DDRC; - stc_gpio_ddrc_field_t DDRC_f; - }; - union { - __IO uint32_t DDRD; - stc_gpio_ddrd_field_t DDRD_f; - }; - union { - __IO uint32_t DDRE; - stc_gpio_ddre_field_t DDRE_f; - }; - union { - __IO uint32_t DDRF; - stc_gpio_ddrf_field_t DDRF_f; - }; - uint8_t RESERVED2[192]; - union { - __IO uint32_t PDIR0; - stc_gpio_pdir0_field_t PDIR0_f; - }; - union { - __IO uint32_t PDIR1; - stc_gpio_pdir1_field_t PDIR1_f; - }; - union { - __IO uint32_t PDIR2; - stc_gpio_pdir2_field_t PDIR2_f; - }; - union { - __IO uint32_t PDIR3; - stc_gpio_pdir3_field_t PDIR3_f; - }; - union { - __IO uint32_t PDIR4; - stc_gpio_pdir4_field_t PDIR4_f; - }; - union { - __IO uint32_t PDIR5; - stc_gpio_pdir5_field_t PDIR5_f; - }; - union { - __IO uint32_t PDIR6; - stc_gpio_pdir6_field_t PDIR6_f; - }; - union { - __IO uint32_t PDIR7; - stc_gpio_pdir7_field_t PDIR7_f; - }; - union { - __IO uint32_t PDIR8; - stc_gpio_pdir8_field_t PDIR8_f; - }; - union { - __IO uint32_t PDIR9; - stc_gpio_pdir9_field_t PDIR9_f; - }; - union { - __IO uint32_t PDIRA; - stc_gpio_pdira_field_t PDIRA_f; - }; - union { - __IO uint32_t PDIRB; - stc_gpio_pdirb_field_t PDIRB_f; - }; - union { - __IO uint32_t PDIRC; - stc_gpio_pdirc_field_t PDIRC_f; - }; - union { - __IO uint32_t PDIRD; - stc_gpio_pdird_field_t PDIRD_f; - }; - union { - __IO uint32_t PDIRE; - stc_gpio_pdire_field_t PDIRE_f; - }; - union { - __IO uint32_t PDIRF; - stc_gpio_pdirf_field_t PDIRF_f; - }; - uint8_t RESERVED3[192]; - union { - __IO uint32_t PDOR0; - stc_gpio_pdor0_field_t PDOR0_f; - }; - union { - __IO uint32_t PDOR1; - stc_gpio_pdor1_field_t PDOR1_f; - }; - union { - __IO uint32_t PDOR2; - stc_gpio_pdor2_field_t PDOR2_f; - }; - union { - __IO uint32_t PDOR3; - stc_gpio_pdor3_field_t PDOR3_f; - }; - union { - __IO uint32_t PDOR4; - stc_gpio_pdor4_field_t PDOR4_f; - }; - union { - __IO uint32_t PDOR5; - stc_gpio_pdor5_field_t PDOR5_f; - }; - union { - __IO uint32_t PDOR6; - stc_gpio_pdor6_field_t PDOR6_f; - }; - union { - __IO uint32_t PDOR7; - stc_gpio_pdor7_field_t PDOR7_f; - }; - union { - __IO uint32_t PDOR8; - stc_gpio_pdor8_field_t PDOR8_f; - }; - union { - __IO uint32_t PDOR9; - stc_gpio_pdor9_field_t PDOR9_f; - }; - union { - __IO uint32_t PDORA; - stc_gpio_pdora_field_t PDORA_f; - }; - union { - __IO uint32_t PDORB; - stc_gpio_pdorb_field_t PDORB_f; - }; - union { - __IO uint32_t PDORC; - stc_gpio_pdorc_field_t PDORC_f; - }; - union { - __IO uint32_t PDORD; - stc_gpio_pdord_field_t PDORD_f; - }; - union { - __IO uint32_t PDORE; - stc_gpio_pdore_field_t PDORE_f; - }; - union { - __IO uint32_t PDORF; - stc_gpio_pdorf_field_t PDORF_f; - }; - uint8_t RESERVED4[192]; - union { - __IO uint32_t ADE; - stc_gpio_ade_field_t ADE_f; - }; - uint8_t RESERVED5[124]; - union { - __IO uint32_t SPSR; - stc_gpio_spsr_field_t SPSR_f; - }; - uint8_t RESERVED6[124]; - union { - __IO uint32_t EPFR00; - stc_gpio_epfr00_field_t EPFR00_f; - }; - union { - __IO uint32_t EPFR01; - stc_gpio_epfr01_field_t EPFR01_f; - }; - union { - __IO uint32_t EPFR02; - stc_gpio_epfr02_field_t EPFR02_f; - }; - union { - __IO uint32_t EPFR03; - stc_gpio_epfr03_field_t EPFR03_f; - }; - union { - __IO uint32_t EPFR04; - stc_gpio_epfr04_field_t EPFR04_f; - }; - union { - __IO uint32_t EPFR05; - stc_gpio_epfr05_field_t EPFR05_f; - }; - union { - __IO uint32_t EPFR06; - stc_gpio_epfr06_field_t EPFR06_f; - }; - union { - __IO uint32_t EPFR07; - stc_gpio_epfr07_field_t EPFR07_f; - }; - union { - __IO uint32_t EPFR08; - stc_gpio_epfr08_field_t EPFR08_f; - }; - union { - __IO uint32_t EPFR09; - stc_gpio_epfr09_field_t EPFR09_f; - }; - union { - __IO uint32_t EPFR10; - stc_gpio_epfr10_field_t EPFR10_f; - }; - union { - __IO uint32_t EPFR11; - stc_gpio_epfr11_field_t EPFR11_f; - }; - union { - __IO uint32_t EPFR12; - stc_gpio_epfr12_field_t EPFR12_f; - }; - union { - __IO uint32_t EPFR13; - stc_gpio_epfr13_field_t EPFR13_f; - }; - union { - __IO uint32_t EPFR14; - stc_gpio_epfr14_field_t EPFR14_f; - }; - union { - __IO uint32_t EPFR15; - stc_gpio_epfr15_field_t EPFR15_f; - }; - uint8_t RESERVED7[192]; - union { - __IO uint32_t PZR0; - stc_gpio_pzr0_field_t PZR0_f; - }; - union { - __IO uint32_t PZR1; - stc_gpio_pzr1_field_t PZR1_f; - }; - union { - __IO uint32_t PZR2; - stc_gpio_pzr2_field_t PZR2_f; - }; - union { - __IO uint32_t PZR3; - stc_gpio_pzr3_field_t PZR3_f; - }; - union { - __IO uint32_t PZR4; - stc_gpio_pzr4_field_t PZR4_f; - }; - union { - __IO uint32_t PZR5; - stc_gpio_pzr5_field_t PZR5_f; - }; - union { - __IO uint32_t PZR6; - stc_gpio_pzr6_field_t PZR6_f; - }; - union { - __IO uint32_t PZR7; - stc_gpio_pzr7_field_t PZR7_f; - }; - union { - __IO uint32_t PZR8; - stc_gpio_pzr8_field_t PZR8_f; - }; - union { - __IO uint32_t PZR9; - stc_gpio_pzr9_field_t PZR9_f; - }; - union { - __IO uint32_t PZRA; - stc_gpio_pzra_field_t PZRA_f; - }; - union { - __IO uint32_t PZRB; - stc_gpio_pzrb_field_t PZRB_f; - }; - union { - __IO uint32_t PZRC; - stc_gpio_pzrc_field_t PZRC_f; - }; - union { - __IO uint32_t PZRD; - stc_gpio_pzrd_field_t PZRD_f; - }; - union { - __IO uint32_t PZRE; - stc_gpio_pzre_field_t PZRE_f; - }; - union { - __IO uint32_t PZRF; - stc_gpio_pzrf_field_t PZRF_f; - }; -}FM3_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - union { - __IO uint8_t LVD_CTL; - stc_lvd_lvd_ctl_field_t LVD_CTL_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t LVD_STR; - stc_lvd_lvd_str_field_t LVD_STR_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t LVD_CLR; - stc_lvd_lvd_clr_field_t LVD_CLR_f; - }; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - union { - __IO uint8_t LVD_STR2; - stc_lvd_lvd_str2_field_t LVD_STR2_f; - }; -}FM3_LVD_TypeDef; - -/****************************************************************************** - * USBETHERNETCLK - ******************************************************************************/ -/* USB Ethernet clock registers */ -typedef struct -{ - union { - __IO uint8_t UCCR; - stc_usbethernetclk_uccr_field_t UCCR_f; - }; - uint8_t RESERVED0[3]; - union { - __IO uint8_t UPCR1; - stc_usbethernetclk_upcr1_field_t UPCR1_f; - }; - uint8_t RESERVED1[3]; - union { - __IO uint8_t UPCR2; - stc_usbethernetclk_upcr2_field_t UPCR2_f; - }; - uint8_t RESERVED2[3]; - union { - __IO uint8_t UPCR3; - stc_usbethernetclk_upcr3_field_t UPCR3_f; - }; - uint8_t RESERVED3[3]; - union { - __IO uint8_t UPCR4; - stc_usbethernetclk_upcr4_field_t UPCR4_f; - }; - uint8_t RESERVED4[3]; - union { - __IO uint8_t UP_STR; - stc_usbethernetclk_up_str_field_t UP_STR_f; - }; - uint8_t RESERVED5[3]; - union { - __IO uint8_t UPINT_ENR; - stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f; - }; - uint8_t RESERVED6[3]; - union { - __IO uint8_t UPINT_CLR; - stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint8_t UPINT_STR; - stc_usbethernetclk_upint_str_field_t UPINT_STR_f; - }; - uint8_t RESERVED8[3]; - union { - __IO uint8_t UPCR5; - stc_usbethernetclk_upcr5_field_t UPCR5_f; - }; - uint8_t RESERVED9[3]; - union { - __IO uint8_t UPCR6; - stc_usbethernetclk_upcr6_field_t UPCR6_f; - }; - uint8_t RESERVED10[3]; - union { - __IO uint8_t UPCR7; - stc_usbethernetclk_upcr7_field_t UPCR7_f; - }; - uint8_t RESERVED11[3]; - union { - __IO uint8_t USBEN0; - stc_usbethernetclk_usben0_field_t USBEN0_f; - }; - uint8_t RESERVED12[3]; - union { - __IO uint8_t USBEN1; - stc_usbethernetclk_usben1_field_t USBEN1_f; - }; -}FM3_USBETHERNETCLK_TypeDef; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs03_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs03_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_uart_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_UART_TypeDef; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_CSIO_TypeDef; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs03_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs03_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs03_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs03_lin_bgr1_field_t BGR1_f; - }; - }; - }; -}FM3_MFS03_LIN_TypeDef; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* I2C channel 0 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs03_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs03_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs03_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs03_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs03_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs03_i2c_ismk_field_t ISMK_f; - }; -}FM3_MFS03_I2C_TypeDef; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_uart_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_uart_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_uart_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_uart_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - union { - __IO uint16_t RDR; - stc_mfs47_uart_rdr_field_t RDR_f; - }; - union { - __IO uint16_t TDR; - stc_mfs47_uart_tdr_field_t TDR_f; - }; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_uart_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_uart_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_uart_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_uart_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_uart_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_uart_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_uart_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_uart_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_UART_TypeDef; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_csio_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_csio_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_csio_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_csio_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_csio_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_csio_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_csio_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_csio_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_csio_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_csio_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_CSIO_TypeDef; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_lin_smr_field_t SMR_f; - }; - union { - __IO uint8_t SCR; - stc_mfs47_lin_scr_field_t SCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t ESCR; - stc_mfs47_lin_escr_field_t ESCR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_lin_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t BGR; - stc_mfs47_lin_bgr_field_t BGR_f; - }; - struct { - __IO uint8_t BGR0; - union { - __IO uint8_t BGR1; - stc_mfs47_lin_bgr1_field_t BGR1_f; - }; - }; - }; - uint8_t RESERVED3[6]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_lin_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_lin_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_lin_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_lin_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_lin_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_lin_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_LIN_TypeDef; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* I2C channel 4 registers */ -typedef struct -{ - union { - __IO uint8_t SMR; - stc_mfs47_i2c_smr_field_t SMR_f; - }; - union { - __IO uint8_t IBCR; - stc_mfs47_i2c_ibcr_field_t IBCR_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t IBSR; - stc_mfs47_i2c_ibsr_field_t IBSR_f; - }; - union { - __IO uint8_t SSR; - stc_mfs47_i2c_ssr_field_t SSR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t ISBA; - stc_mfs47_i2c_isba_field_t ISBA_f; - }; - union { - __IO uint8_t ISMK; - stc_mfs47_i2c_ismk_field_t ISMK_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t FCR; - stc_mfs47_i2c_fcr_field_t FCR_f; - }; - struct { - union { - __IO uint8_t FCR0; - stc_mfs47_i2c_fcr0_field_t FCR0_f; - }; - union { - __IO uint8_t FCR1; - stc_mfs47_i2c_fcr1_field_t FCR1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t FBYTE; - stc_mfs47_i2c_fbyte_field_t FBYTE_f; - }; - struct { - union { - __IO uint8_t FBYTE1; - stc_mfs47_i2c_fbyte1_field_t FBYTE1_f; - }; - union { - __IO uint8_t FBYTE2; - stc_mfs47_i2c_fbyte2_field_t FBYTE2_f; - }; - }; - }; -}FM3_MFS47_I2C_TypeDef; - -/****************************************************************************** - * MFS_NFC_MODULE - ******************************************************************************/ -/* MFS_NFC_MODULE register bit fields */ -typedef struct -{ - union { - __IO uint16_t I2CDNF; - stc_mfs_nfc_i2cdnf_field_t I2CDNF_f; - }; -}FM3_MFS_NFC_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - union { - __IO uint8_t CRCCR; - stc_crc_crccr_field_t CRCCR_f; - }; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM3_CRC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - union { - __IO uint8_t WCRD; - stc_wc_wcrd_field_t WCRD_f; - }; - union { - __IO uint8_t WCRL; - stc_wc_wcrl_field_t WCRL_f; - }; - union { - __IO uint8_t WCCR; - stc_wc_wccr_field_t WCCR_f; - }; - uint8_t RESERVED0[13]; - union { - __IO uint16_t CLK_SEL; - stc_wc_clk_sel_field_t CLK_SEL_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t CLK_EN; - stc_wc_clk_en_field_t CLK_EN_f; - }; -}FM3_WC_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - union { - __IO uint32_t MODE0; - stc_exbus_mode0_field_t MODE0_f; - }; - union { - __IO uint32_t MODE1; - stc_exbus_mode1_field_t MODE1_f; - }; - union { - __IO uint32_t MODE2; - stc_exbus_mode2_field_t MODE2_f; - }; - union { - __IO uint32_t MODE3; - stc_exbus_mode3_field_t MODE3_f; - }; - union { - __IO uint32_t MODE4; - stc_exbus_mode4_field_t MODE4_f; - }; - union { - __IO uint32_t MODE5; - stc_exbus_mode5_field_t MODE5_f; - }; - union { - __IO uint32_t MODE6; - stc_exbus_mode6_field_t MODE6_f; - }; - union { - __IO uint32_t MODE7; - stc_exbus_mode7_field_t MODE7_f; - }; - union { - __IO uint32_t TIM0; - stc_exbus_tim0_field_t TIM0_f; - }; - union { - __IO uint32_t TIM1; - stc_exbus_tim1_field_t TIM1_f; - }; - union { - __IO uint32_t TIM2; - stc_exbus_tim2_field_t TIM2_f; - }; - union { - __IO uint32_t TIM3; - stc_exbus_tim3_field_t TIM3_f; - }; - union { - __IO uint32_t TIM4; - stc_exbus_tim4_field_t TIM4_f; - }; - union { - __IO uint32_t TIM5; - stc_exbus_tim5_field_t TIM5_f; - }; - union { - __IO uint32_t TIM6; - stc_exbus_tim6_field_t TIM6_f; - }; - union { - __IO uint32_t TIM7; - stc_exbus_tim7_field_t TIM7_f; - }; - union { - __IO uint32_t AREA0; - stc_exbus_area0_field_t AREA0_f; - }; - union { - __IO uint32_t AREA1; - stc_exbus_area1_field_t AREA1_f; - }; - union { - __IO uint32_t AREA2; - stc_exbus_area2_field_t AREA2_f; - }; - union { - __IO uint32_t AREA3; - stc_exbus_area3_field_t AREA3_f; - }; - union { - __IO uint32_t AREA4; - stc_exbus_area4_field_t AREA4_f; - }; - union { - __IO uint32_t AREA5; - stc_exbus_area5_field_t AREA5_f; - }; - union { - __IO uint32_t AREA6; - stc_exbus_area6_field_t AREA6_f; - }; - union { - __IO uint32_t AREA7; - stc_exbus_area7_field_t AREA7_f; - }; - union { - __IO uint16_t ATIM0; - stc_exbus_atim0_field_t ATIM0_f; - }; - uint8_t RESERVED0[2]; - union { - __IO uint16_t ATIM1; - stc_exbus_atim1_field_t ATIM1_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint16_t ATIM2; - stc_exbus_atim2_field_t ATIM2_f; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t ATIM3; - stc_exbus_atim3_field_t ATIM3_f; - }; - uint8_t RESERVED3[2]; - union { - __IO uint16_t ATIM4; - stc_exbus_atim4_field_t ATIM4_f; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t ATIM5; - stc_exbus_atim5_field_t ATIM5_f; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t ATIM6; - stc_exbus_atim6_field_t ATIM6_f; - }; - uint8_t RESERVED6[2]; - union { - __IO uint16_t ATIM7; - stc_exbus_atim7_field_t ATIM7_f; - }; - uint8_t RESERVED7[642]; - union { - __IO uint8_t DCLKR; - stc_exbus_dclkr_field_t DCLKR_f; - }; -}FM3_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - union { - __IO uint16_t HCNT; - stc_usb_hcnt_field_t HCNT_f; - }; - struct { - union { - __IO uint8_t HCNT0; - stc_usb_hcnt0_field_t HCNT0_f; - }; - union { - __IO uint8_t HCNT1; - stc_usb_hcnt1_field_t HCNT1_f; - }; - }; - }; - uint8_t RESERVED0[2]; - union { - __IO uint8_t HIRQ; - stc_usb_hirq_field_t HIRQ_f; - }; - union { - __IO uint8_t HERR; - stc_usb_herr_field_t HERR_f; - }; - uint8_t RESERVED1[2]; - union { - __IO uint8_t HSTATE; - stc_usb_hstate_field_t HSTATE_f; - }; - union { - __IO uint8_t HFCOMP; - stc_usb_hfcomp_field_t HFCOMP_f; - }; - uint8_t RESERVED2[2]; - union { - union { - __IO uint16_t HRTIMER; - stc_usb_hrtimer_field_t HRTIMER_f; - }; - struct { - union { - __IO uint8_t HRTIMER0; - stc_usb_hrtimer0_field_t HRTIMER0_f; - }; - union { - __IO uint8_t HRTIMER1; - stc_usb_hrtimer1_field_t HRTIMER1_f; - }; - }; - }; - uint8_t RESERVED3[2]; - union { - __IO uint8_t HRTIMER2; - stc_usb_hrtimer2_field_t HRTIMER2_f; - }; - union { - __IO uint8_t HADR; - stc_usb_hadr_field_t HADR_f; - }; - uint8_t RESERVED4[2]; - union { - union { - __IO uint16_t HEOF; - stc_usb_heof_field_t HEOF_f; - }; - struct { - union { - __IO uint8_t HEOF0; - stc_usb_heof0_field_t HEOF0_f; - }; - union { - __IO uint8_t HEOF1; - stc_usb_heof1_field_t HEOF1_f; - }; - }; - }; - uint8_t RESERVED5[2]; - union { - union { - __IO uint16_t HFRAME; - stc_usb_hframe_field_t HFRAME_f; - }; - struct { - union { - __IO uint8_t HFRAME0; - stc_usb_hframe0_field_t HFRAME0_f; - }; - union { - __IO uint8_t HFRAME1; - stc_usb_hframe1_field_t HFRAME1_f; - }; - }; - }; - uint8_t RESERVED6[2]; - union { - __IO uint8_t HTOKEN; - stc_usb_htoken_field_t HTOKEN_f; - }; - uint8_t RESERVED7[3]; - union { - __IO uint16_t UDCC; - stc_usb_udcc_field_t UDCC_f; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t EP0C; - stc_usb_ep0c_field_t EP0C_f; - }; - uint8_t RESERVED9[2]; - union { - __IO uint16_t EP1C; - stc_usb_ep1c_field_t EP1C_f; - }; - uint8_t RESERVED10[2]; - union { - __IO uint16_t EP2C; - stc_usb_ep2c_field_t EP2C_f; - }; - uint8_t RESERVED11[2]; - union { - __IO uint16_t EP3C; - stc_usb_ep3c_field_t EP3C_f; - }; - uint8_t RESERVED12[2]; - union { - __IO uint16_t EP4C; - stc_usb_ep4c_field_t EP4C_f; - }; - uint8_t RESERVED13[2]; - union { - __IO uint16_t EP5C; - stc_usb_ep5c_field_t EP5C_f; - }; - uint8_t RESERVED14[2]; - union { - __IO uint16_t TMSP; - stc_usb_tmsp_field_t TMSP_f; - }; - uint8_t RESERVED15[2]; - union { - __IO uint8_t UDCS; - stc_usb_udcs_field_t UDCS_f; - }; - union { - __IO uint8_t UDCIE; - stc_usb_udcie_field_t UDCIE_f; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t EP0IS; - stc_usb_ep0is_field_t EP0IS_f; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t EP0OS; - stc_usb_ep0os_field_t EP0OS_f; - }; - uint8_t RESERVED18[2]; - union { - __IO uint16_t EP1S; - stc_usb_ep1s_field_t EP1S_f; - }; - uint8_t RESERVED19[2]; - union { - __IO uint16_t EP2S; - stc_usb_ep2s_field_t EP2S_f; - }; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - union { - __IO uint16_t EP4S; - stc_usb_ep4s_field_t EP4S_f; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t EP5S; - stc_usb_ep5s_field_t EP5S_f; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM3_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - union { - __IO uint32_t DMACR; - stc_dmac_dmacr_field_t DMACR_f; - }; - uint8_t RESERVED0[12]; - union { - __IO uint32_t DMACA0; - stc_dmac_dmaca0_field_t DMACA0_f; - }; - union { - __IO uint32_t DMACB0; - stc_dmac_dmacb0_field_t DMACB0_f; - }; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - union { - __IO uint32_t DMACA1; - stc_dmac_dmaca1_field_t DMACA1_f; - }; - union { - __IO uint32_t DMACB1; - stc_dmac_dmacb1_field_t DMACB1_f; - }; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - union { - __IO uint32_t DMACA2; - stc_dmac_dmaca2_field_t DMACA2_f; - }; - union { - __IO uint32_t DMACB2; - stc_dmac_dmacb2_field_t DMACB2_f; - }; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - union { - __IO uint32_t DMACA3; - stc_dmac_dmaca3_field_t DMACA3_f; - }; - union { - __IO uint32_t DMACB3; - stc_dmac_dmacb3_field_t DMACB3_f; - }; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - union { - __IO uint32_t DMACA4; - stc_dmac_dmaca4_field_t DMACA4_f; - }; - union { - __IO uint32_t DMACB4; - stc_dmac_dmacb4_field_t DMACB4_f; - }; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - union { - __IO uint32_t DMACA5; - stc_dmac_dmaca5_field_t DMACA5_f; - }; - union { - __IO uint32_t DMACB5; - stc_dmac_dmacb5_field_t DMACB5_f; - }; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - union { - __IO uint32_t DMACA6; - stc_dmac_dmaca6_field_t DMACA6_f; - }; - union { - __IO uint32_t DMACB6; - stc_dmac_dmacb6_field_t DMACB6_f; - }; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - union { - __IO uint32_t DMACA7; - stc_dmac_dmaca7_field_t DMACA7_f; - }; - union { - __IO uint32_t DMACB7; - stc_dmac_dmacb7_field_t DMACB7_f; - }; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM3_DMAC_TypeDef; - -/****************************************************************************** - * ETHERNET_MAC_MODULE - ******************************************************************************/ -/* ETHERNET-MAC registers */ -typedef struct -{ - union { - __IO uint32_t MCR; - stc_ethernet_mac_mcr_field_t MCR_f; - }; - union { - __IO uint32_t MFFR; - stc_ethernet_mac_mffr_field_t MFFR_f; - }; - union { - __IO uint32_t MHTRH; - stc_ethernet_mac_mhtrh_field_t MHTRH_f; - }; - union { - __IO uint32_t MHTRL; - stc_ethernet_mac_mhtrl_field_t MHTRL_f; - }; - union { - __IO uint32_t GAR; - stc_ethernet_mac_gar_field_t GAR_f; - }; - union { - __IO uint32_t GDR; - stc_ethernet_mac_gdr_field_t GDR_f; - }; - union { - __IO uint32_t FCR; - stc_ethernet_mac_fcr_field_t FCR_f; - }; - union { - __IO uint32_t VTR; - stc_ethernet_mac_vtr_field_t VTR_f; - }; - uint8_t RESERVED0[8]; - union { - __IO uint32_t RWFFR; - stc_ethernet_mac_rwffr_field_t RWFFR_f; - }; - union { - __IO uint32_t PMTR; - stc_ethernet_mac_pmtr_field_t PMTR_f; - }; - union { - __IO uint32_t LPICSR; - stc_ethernet_mac_lpicsr_field_t LPICSR_f; - }; - union { - __IO uint32_t LPITCR; - stc_ethernet_mac_lpitcr_field_t LPITCR_f; - }; - union { - __IO uint32_t ISR; - stc_ethernet_mac_isr_field_t ISR_f; - }; - union { - __IO uint32_t IMR; - stc_ethernet_mac_imr_field_t IMR_f; - }; - union { - __IO uint32_t MAR0H; - stc_ethernet_mac_mar0h_field_t MAR0H_f; - }; - union { - __IO uint32_t MAR0L; - stc_ethernet_mac_mar0l_field_t MAR0L_f; - }; - union { - __IO uint32_t MAR1H; - stc_ethernet_mac_mar1h_field_t MAR1H_f; - }; - union { - __IO uint32_t MAR1L; - stc_ethernet_mac_mar1l_field_t MAR1L_f; - }; - union { - __IO uint32_t MAR2H; - stc_ethernet_mac_mar2h_field_t MAR2H_f; - }; - union { - __IO uint32_t MAR2L; - stc_ethernet_mac_mar2l_field_t MAR2L_f; - }; - union { - __IO uint32_t MAR3H; - stc_ethernet_mac_mar3h_field_t MAR3H_f; - }; - union { - __IO uint32_t MAR3L; - stc_ethernet_mac_mar3l_field_t MAR3L_f; - }; - union { - __IO uint32_t MAR4H; - stc_ethernet_mac_mar4h_field_t MAR4H_f; - }; - union { - __IO uint32_t MAR4L; - stc_ethernet_mac_mar4l_field_t MAR4L_f; - }; - union { - __IO uint32_t MAR5H; - stc_ethernet_mac_mar5h_field_t MAR5H_f; - }; - union { - __IO uint32_t MAR5L; - stc_ethernet_mac_mar5l_field_t MAR5L_f; - }; - union { - __IO uint32_t MAR6H; - stc_ethernet_mac_mar6h_field_t MAR6H_f; - }; - union { - __IO uint32_t MAR6L; - stc_ethernet_mac_mar6l_field_t MAR6L_f; - }; - union { - __IO uint32_t MAR7H; - stc_ethernet_mac_mar7h_field_t MAR7H_f; - }; - union { - __IO uint32_t MAR7L; - stc_ethernet_mac_mar7l_field_t MAR7L_f; - }; - union { - __IO uint32_t MAR8H; - stc_ethernet_mac_mar8h_field_t MAR8H_f; - }; - union { - __IO uint32_t MAR8L; - stc_ethernet_mac_mar8l_field_t MAR8L_f; - }; - union { - __IO uint32_t MAR9H; - stc_ethernet_mac_mar9h_field_t MAR9H_f; - }; - union { - __IO uint32_t MAR9L; - stc_ethernet_mac_mar9l_field_t MAR9L_f; - }; - union { - __IO uint32_t MAR10H; - stc_ethernet_mac_mar10h_field_t MAR10H_f; - }; - union { - __IO uint32_t MAR10L; - stc_ethernet_mac_mar10l_field_t MAR10L_f; - }; - union { - __IO uint32_t MAR11H; - stc_ethernet_mac_mar11h_field_t MAR11H_f; - }; - union { - __IO uint32_t MAR11L; - stc_ethernet_mac_mar11l_field_t MAR11L_f; - }; - union { - __IO uint32_t MAR12H; - stc_ethernet_mac_mar12h_field_t MAR12H_f; - }; - union { - __IO uint32_t MAR12L; - stc_ethernet_mac_mar12l_field_t MAR12L_f; - }; - union { - __IO uint32_t MAR13H; - stc_ethernet_mac_mar13h_field_t MAR13H_f; - }; - union { - __IO uint32_t MAR13L; - stc_ethernet_mac_mar13l_field_t MAR13L_f; - }; - union { - __IO uint32_t MAR14H; - stc_ethernet_mac_mar14h_field_t MAR14H_f; - }; - union { - __IO uint32_t MAR14L; - stc_ethernet_mac_mar14l_field_t MAR14L_f; - }; - union { - __IO uint32_t MAR15H; - stc_ethernet_mac_mar15h_field_t MAR15H_f; - }; - union { - __IO uint32_t MAR15L; - stc_ethernet_mac_mar15l_field_t MAR15L_f; - }; - uint8_t RESERVED1[24]; - union { - __IO uint32_t RGSR; - stc_ethernet_mac_rgsr_field_t RGSR_f; - }; - uint8_t RESERVED2[36]; - __IO uint32_t mmc_cntl; - __IO uint32_t mmc_intr_rx; - __IO uint32_t mmc_intr_tx; - __IO uint32_t mmc_intr_mask_rx; - __IO uint32_t mmc_intr_mask_tx; - __IO uint32_t txoctetcount_gb; - __IO uint32_t txframecount_gb; - __IO uint32_t txbroadcastframes_g; - __IO uint32_t txmulticastframes_g; - __IO uint32_t tx64octets_gb; - __IO uint32_t tx65to127octets_gb; - __IO uint32_t tx128to255octets_gb; - __IO uint32_t tx256to511octets_gb; - __IO uint32_t tx512to1023octets_gb; - __IO uint32_t tx1024tomaxoctets_gb; - __IO uint32_t txunicastframes_gb; - __IO uint32_t txmulticastframes_gb; - __IO uint32_t txbroadcastframes_gb; - __IO uint32_t txunderflowerror; - __IO uint32_t txsinglecol_g; - __IO uint32_t txmulticol_g; - __IO uint32_t txdeferred; - __IO uint32_t txlatecol; - __IO uint32_t txexesscol; - __IO uint32_t txcarriererror; - __IO uint32_t txoctetcount_g; - __IO uint32_t txframecount_g; - __IO uint32_t txexecessdef_g; - __IO uint32_t txpauseframes; - __IO uint32_t txvlanframes_g; - uint8_t RESERVED3[8]; - __IO uint32_t rxframecount_gb; - __IO uint32_t rxoctetcount_gb; - __IO uint32_t rxoctetcount_g; - __IO uint32_t rxbroadcastframes_g; - __IO uint32_t rxmulticastframes_g; - __IO uint32_t rxcrcerror; - __IO uint32_t rxallignmenterror; - __IO uint32_t rxrunterror; - __IO uint32_t rxjabbererror; - __IO uint32_t rxundersize_g; - __IO uint32_t rxoversize_g; - __IO uint32_t rx64octets_gb; - __IO uint32_t rx65to127octets_gb; - __IO uint32_t rx128to255octets_gb; - __IO uint32_t rx256to511octets_gb; - __IO uint32_t rx512to1023octets_gb; - __IO uint32_t rx1024tomaxoctets_gb; - __IO uint32_t rxunicastframes_g; - __IO uint32_t rxlengtherror; - __IO uint32_t rxoutofrangetype; - __IO uint32_t rxpauseframes; - __IO uint32_t rxfifooverflow; - __IO uint32_t rxvlanframes_gb; - __IO uint32_t rxwatchdogerror; - uint8_t RESERVED4[32]; - __IO uint32_t mmc_ipc_intr_mask_rx; - uint8_t RESERVED5[4]; - __IO uint32_t mmc_ipc_intr_rx; - uint8_t RESERVED6[4]; - __IO uint32_t rxipv4_gd_frms; - __IO uint32_t rxipv4_hdrerr_frms; - __IO uint32_t rxipv4_nopay_frms; - __IO uint32_t rxipv4_frag_frms; - __IO uint32_t rxipv4_udsbl_frms; - __IO uint32_t rxipv6_gd_frms; - __IO uint32_t rxipv6_hdrerr_frms; - __IO uint32_t rxipv6_nopay_frms; - __IO uint32_t rxudp_gd_frms; - __IO uint32_t rxudp_err_frms; - __IO uint32_t rxtcp_gd_frms; - __IO uint32_t rxtcp_err_frms; - __IO uint32_t rxicmp_gd_frms; - __IO uint32_t rxicmp_err_frms; - uint8_t RESERVED7[8]; - __IO uint32_t rxipv4_gd_octets; - __IO uint32_t rxipv4_hdrerr_octets; - __IO uint32_t rxipv4_nopay_octets; - __IO uint32_t rxipv4_frag_octets; - __IO uint32_t rxipv4_udsbl_octets; - __IO uint32_t rxipv6_gd_octets; - __IO uint32_t rxipv6_hdrerr_octets; - __IO uint32_t rxipv6_nopay_octets; - __IO uint32_t rxudp_gd_octets; - __IO uint32_t rxudp_err_octets; - __IO uint32_t rxtcp_gd_octets; - __IO uint32_t rxtcp_err_octets; - __IO uint32_t rxicmp_gd_octets; - __IO uint32_t rxicmp_err_octets; - uint8_t RESERVED8[1144]; - union { - __IO uint32_t TSCR; - stc_ethernet_mac_tscr_field_t TSCR_f; - }; - union { - __IO uint32_t SSIR; - stc_ethernet_mac_ssir_field_t SSIR_f; - }; - union { - __IO uint32_t STSR; - stc_ethernet_mac_stsr_field_t STSR_f; - }; - union { - __IO uint32_t STNR; - stc_ethernet_mac_stnr_field_t STNR_f; - }; - union { - __IO uint32_t STSUR; - stc_ethernet_mac_stsur_field_t STSUR_f; - }; - union { - __IO uint32_t STNUR; - stc_ethernet_mac_stnur_field_t STNUR_f; - }; - union { - __IO uint32_t TSAR; - stc_ethernet_mac_tsar_field_t TSAR_f; - }; - union { - __IO uint32_t TTSR; - stc_ethernet_mac_ttsr_field_t TTSR_f; - }; - union { - __IO uint32_t TTNR; - stc_ethernet_mac_ttnr_field_t TTNR_f; - }; - union { - __IO uint32_t STHWSR; - stc_ethernet_mac_sthwsr_field_t STHWSR_f; - }; - union { - __IO uint32_t TSR; - stc_ethernet_mac_tsr_field_t TSR_f; - }; - union { - __IO uint32_t PPSCR; - stc_ethernet_mac_ppscr_field_t PPSCR_f; - }; - union { - __IO uint32_t ATNR; - stc_ethernet_mac_atnr_field_t ATNR_f; - }; - union { - __IO uint32_t ATSR; - stc_ethernet_mac_atsr_field_t ATSR_f; - }; - uint8_t RESERVED9[200]; - union { - __IO uint32_t MAR16H; - stc_ethernet_mac_mar16h_field_t MAR16H_f; - }; - union { - __IO uint32_t MAR16L; - stc_ethernet_mac_mar16l_field_t MAR16L_f; - }; - union { - __IO uint32_t MAR17H; - stc_ethernet_mac_mar17h_field_t MAR17H_f; - }; - union { - __IO uint32_t MAR17L; - stc_ethernet_mac_mar17l_field_t MAR17L_f; - }; - union { - __IO uint32_t MAR18H; - stc_ethernet_mac_mar18h_field_t MAR18H_f; - }; - union { - __IO uint32_t MAR18L; - stc_ethernet_mac_mar18l_field_t MAR18L_f; - }; - union { - __IO uint32_t MAR19H; - stc_ethernet_mac_mar19h_field_t MAR19H_f; - }; - union { - __IO uint32_t MAR19L; - stc_ethernet_mac_mar19l_field_t MAR19L_f; - }; - union { - __IO uint32_t MAR20H; - stc_ethernet_mac_mar20h_field_t MAR20H_f; - }; - union { - __IO uint32_t MAR20L; - stc_ethernet_mac_mar20l_field_t MAR20L_f; - }; - union { - __IO uint32_t MAR21H; - stc_ethernet_mac_mar21h_field_t MAR21H_f; - }; - union { - __IO uint32_t MAR21L; - stc_ethernet_mac_mar21l_field_t MAR21L_f; - }; - union { - __IO uint32_t MAR22H; - stc_ethernet_mac_mar22h_field_t MAR22H_f; - }; - union { - __IO uint32_t MAR22L; - stc_ethernet_mac_mar22l_field_t MAR22L_f; - }; - union { - __IO uint32_t MAR23H; - stc_ethernet_mac_mar23h_field_t MAR23H_f; - }; - union { - __IO uint32_t MAR23L; - stc_ethernet_mac_mar23l_field_t MAR23L_f; - }; - union { - __IO uint32_t MAR24H; - stc_ethernet_mac_mar24h_field_t MAR24H_f; - }; - union { - __IO uint32_t MAR24L; - stc_ethernet_mac_mar24l_field_t MAR24L_f; - }; - union { - __IO uint32_t MAR25H; - stc_ethernet_mac_mar25h_field_t MAR25H_f; - }; - union { - __IO uint32_t MAR25L; - stc_ethernet_mac_mar25l_field_t MAR25L_f; - }; - union { - __IO uint32_t MAR26H; - stc_ethernet_mac_mar26h_field_t MAR26H_f; - }; - union { - __IO uint32_t MAR26L; - stc_ethernet_mac_mar26l_field_t MAR26L_f; - }; - union { - __IO uint32_t MAR27H; - stc_ethernet_mac_mar27h_field_t MAR27H_f; - }; - union { - __IO uint32_t MAR27L; - stc_ethernet_mac_mar27l_field_t MAR27L_f; - }; - union { - __IO uint32_t MAR28H; - stc_ethernet_mac_mar28h_field_t MAR28H_f; - }; - union { - __IO uint32_t MAR28L; - stc_ethernet_mac_mar28l_field_t MAR28L_f; - }; - union { - __IO uint32_t MAR29H; - stc_ethernet_mac_mar29h_field_t MAR29H_f; - }; - union { - __IO uint32_t MAR29L; - stc_ethernet_mac_mar29l_field_t MAR29L_f; - }; - union { - __IO uint32_t MAR30H; - stc_ethernet_mac_mar30h_field_t MAR30H_f; - }; - union { - __IO uint32_t MAR30L; - stc_ethernet_mac_mar30l_field_t MAR30L_f; - }; - union { - __IO uint32_t MAR31H; - stc_ethernet_mac_mar31h_field_t MAR31H_f; - }; - union { - __IO uint32_t MAR31L; - stc_ethernet_mac_mar31l_field_t MAR31L_f; - }; - uint8_t RESERVED10[1920]; - union { - __IO uint32_t BMR; - stc_ethernet_mac_bmr_field_t BMR_f; - }; - union { - __IO uint32_t TPDR; - stc_ethernet_mac_tpdr_field_t TPDR_f; - }; - union { - __IO uint32_t RPDR; - stc_ethernet_mac_rpdr_field_t RPDR_f; - }; - union { - __IO uint32_t RDLAR; - stc_ethernet_mac_rdlar_field_t RDLAR_f; - }; - union { - __IO uint32_t TDLAR; - stc_ethernet_mac_tdlar_field_t TDLAR_f; - }; - union { - __IO uint32_t SR; - stc_ethernet_mac_sr_field_t SR_f; - }; - union { - __IO uint32_t OMR; - stc_ethernet_mac_omr_field_t OMR_f; - }; - union { - __IO uint32_t IER; - stc_ethernet_mac_ier_field_t IER_f; - }; - union { - __IO uint32_t MFBOCR; - stc_ethernet_mac_mfbocr_field_t MFBOCR_f; - }; - union { - __IO uint32_t RIWTR; - stc_ethernet_mac_riwtr_field_t RIWTR_f; - }; - uint8_t RESERVED11[4]; - union { - __IO uint32_t AHBSR; - stc_ethernet_mac_ahbsr_field_t AHBSR_f; - }; - uint8_t RESERVED12[24]; - union { - __IO uint32_t CHTDR; - stc_ethernet_mac_chtdr_field_t CHTDR_f; - }; - union { - __IO uint32_t CHRDR; - stc_ethernet_mac_chrdr_field_t CHRDR_f; - }; - union { - __IO uint32_t CHTBAR; - stc_ethernet_mac_chtbar_field_t CHTBAR_f; - }; - union { - __IO uint32_t CHRBAR; - stc_ethernet_mac_chrbar_field_t CHRBAR_f; - }; -}FM3_ETHERNET_MAC_TypeDef; - -/* ETHERNET-CONTROL registers */ -typedef struct -{ - union { - __IO uint32_t ETH_MODE; - stc_ethernet_control_eth_mode_field_t ETH_MODE_f; - }; - uint8_t RESERVED1[4]; - union { - __IO uint32_t ETH_CLKG; - stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f; - }; -}FM3_ETHERNET_CONTROL_TypeDef; - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM3_MFT2_FRT_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Free Running Timer registers */ -#define FM3_MFT2_OCU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Output Compare Unit registers */ -#define FM3_MFT2_WFG_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT2_ICU_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 Input Capture Unit registers */ -#define FM3_MFT2_ADCMP_BASE (FM3_PERIPH_BASE + 0x22000UL) /* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM3_BT8_PPG_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PPG registers */ -#define FM3_BT8_PWM_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWM registers */ -#define FM3_BT8_RT_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 RT registers */ -#define FM3_BT8_PWC_BASE (FM3_PERIPH_BASE + 0x25400UL) /* Base Timer 8 PWC registers */ -#define FM3_BT9_PPG_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PPG registers */ -#define FM3_BT9_PWM_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWM registers */ -#define FM3_BT9_RT_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 RT registers */ -#define FM3_BT9_PWC_BASE (FM3_PERIPH_BASE + 0x25440UL) /* Base Timer 9 PWC registers */ -#define FM3_BT10_PPG_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PPG registers */ -#define FM3_BT10_PWM_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWM registers */ -#define FM3_BT10_RT_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 RT registers */ -#define FM3_BT10_PWC_BASE (FM3_PERIPH_BASE + 0x25480UL) /* Base Timer 10 PWC registers */ -#define FM3_BT11_PPG_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PPG registers */ -#define FM3_BT11_PWM_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWM registers */ -#define FM3_BT11_RT_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 RT registers */ -#define FM3_BT11_PWC_BASE (FM3_PERIPH_BASE + 0x254C0UL) /* Base Timer 11 PWC registers */ -#define FM3_BT12_PPG_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PPG registers */ -#define FM3_BT12_PWM_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWM registers */ -#define FM3_BT12_RT_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 RT registers */ -#define FM3_BT12_PWC_BASE (FM3_PERIPH_BASE + 0x25600UL) /* Base Timer 8 PWC registers */ -#define FM3_BT13_PPG_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PPG registers */ -#define FM3_BT13_PWM_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWM registers */ -#define FM3_BT13_RT_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 RT registers */ -#define FM3_BT13_PWC_BASE (FM3_PERIPH_BASE + 0x25640UL) /* Base Timer 9 PWC registers */ -#define FM3_BT14_PPG_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PPG registers */ -#define FM3_BT14_PWM_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWM registers */ -#define FM3_BT14_RT_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 RT registers */ -#define FM3_BT14_PWC_BASE (FM3_PERIPH_BASE + 0x25680UL) /* Base Timer 10 PWC registers */ -#define FM3_BT15_PPG_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PPG registers */ -#define FM3_BT15_PWM_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWM registers */ -#define FM3_BT15_RT_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 RT registers */ -#define FM3_BT15_PWC_BASE (FM3_PERIPH_BASE + 0x256C0UL) /* Base Timer 11 PWC registers */ -#define FM3_BTIOSEL8B_BASE (FM3_PERIPH_BASE + 0x25500UL) /* Base Timer I/O selector channel 8 - channel 11 registers */ -#define FM3_BTIOSELCF_BASE (FM3_PERIPH_BASE + 0x25700UL) /* Base Timer I/O selector channel 12 - channel 15 registers */ -#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM3_QPRC2_BASE (FM3_PERIPH_BASE + 0x26080UL) /* Quad position and revolution counter channel 2 registers */ -#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ -#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ -#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ -#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ -#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ -#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ -#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ -#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ -#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ -#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ -#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ -#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ -#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ -#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ -#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ -#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ -#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ -#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ -#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ -#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ -#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ -#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ -#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ -#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ -#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ -#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ -#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ -#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ -#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ -#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ -#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ -#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ -#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ -#define FM3_MFS_NFC_BASE (FM3_PERIPH_BASE + 0x38800UL) /* MFS Noise Filter Control register */ -#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM3_USB1_BASE (FM3_PERIPH_BASE + 0x52100UL) /* USB channel 1 registers */ -#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM3_ETHERNET_MAC0_BASE (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers */ -#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers */ -#define FM3_ETHERNET_MAC1_BASE (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE) -#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) -#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) -#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) -#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) -#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) -#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) -#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) -#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) -#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) -#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) -#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) -#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) -#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) -#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) -#define FM3_MFT2_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE) -#define FM3_MFT2_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE) -#define FM3_MFT2_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE) -#define FM3_MFT2_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE) -#define FM3_MFT2_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE) -#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) -#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) -#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) -#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) -#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) -#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) -#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) -#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) -#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) -#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) -#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) -#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) -#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) -#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) -#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) -#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) -#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) -#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) -#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) -#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) -#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) -#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) -#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) -#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) -#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) -#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) -#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) -#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) -#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) -#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) -#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) -#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) -#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) -#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) -#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) -#define FM3_BT8_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE) -#define FM3_BT8_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE) -#define FM3_BT8_RT ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE) -#define FM3_BT8_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE) -#define FM3_BT9_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE) -#define FM3_BT9_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE) -#define FM3_BT9_RT ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE) -#define FM3_BT9_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE) -#define FM3_BT10_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE) -#define FM3_BT10_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE) -#define FM3_BT10_RT ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE) -#define FM3_BT10_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE) -#define FM3_BT11_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE) -#define FM3_BT11_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE) -#define FM3_BT11_RT ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE) -#define FM3_BT11_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE) -#define FM3_BT12_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE) -#define FM3_BT12_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE) -#define FM3_BT12_RT ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE) -#define FM3_BT12_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE) -#define FM3_BT13_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE) -#define FM3_BT13_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE) -#define FM3_BT13_RT ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE) -#define FM3_BT13_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE) -#define FM3_BT14_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE) -#define FM3_BT14_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE) -#define FM3_BT14_RT ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE) -#define FM3_BT14_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE) -#define FM3_BT15_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE) -#define FM3_BT15_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE) -#define FM3_BT15_RT ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE) -#define FM3_BT15_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE) -#define FM3_BTIOSEL8B ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE) -#define FM3_BTIOSELCF ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE) -#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) -#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) -#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) -#define FM3_QPRC2 ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE) -#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) -#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) -#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) -#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) -#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) -#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) -#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) -#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) -#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE) -#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) -#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) -#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) -#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) -#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) -#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) -#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) -#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) -#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) -#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) -#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) -#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) -#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) -#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) -#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) -#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) -#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) -#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) -#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) -#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) -#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) -#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) -#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) -#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) -#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) -#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) -#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) -#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) -#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) -#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) -#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) -#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) -#define FM3_MFS_NFC ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE) -#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) -#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) -#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) -#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) -#define FM3_USB1 ((FM3_USB_TypeDef *)FM3_USB1_BASE) -#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) -#define FM3_ETHERNET_MAC0 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE) -#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_SET_TypeDef *)FM3_ETHERNET_SET_BASE) -#define FM3_ETHERNET_MAC1 ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Flash interface registers */ -#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL)) -#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM3_FLASH_IF_FBFCR_BE *((volatile unsigned int*)(0x42000280UL)) -#define bFM3_FLASH_IF_FBFCR_BS *((volatile unsigned int*)(0x42000284UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) - -/* Clock and reset registers */ -#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM3_CRG_TTC_PSR_TTC0 *((volatile unsigned int*)(0x42200500UL)) -#define bFM3_CRG_TTC_PSR_TTC1 *((volatile unsigned int*)(0x42200504UL)) -#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL)) -#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) - -/* Dual timer 1/2 registers */ -#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM3_DTIM_TIMER1RIS_TIMER1RIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM3_DTIM_TIMER1MIS_TIMER1MIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM3_DTIM_TIMER2RIS_TIMER2RIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM3_DTIM_TIMER2MIS_TIMER2MIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) -#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) -#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) -#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) -#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) -#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) -#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) -#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) -#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) -#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) -#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) -#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) -#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) -#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) -#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) -#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) -#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) -#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) -#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) -#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) -#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) -#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) -#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) -#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) -#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) -#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) -#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) -#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) -#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) -#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) -#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) -#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) -#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) -#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) -#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) -#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) -#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) -#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) -#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) -#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) -#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) -#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) -#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) -#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) -#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) -#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) -#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) -#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) -#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) -#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) -#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) -#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) -#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) -#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) -#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) -#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) -#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) -#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) -#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) -#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) -#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) -#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) -#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) -#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) -#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) -#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) -#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) -#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) -#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) -#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) -#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) -#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) -#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) -#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL)) -#define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL)) -#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) -#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) -#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) -#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) -#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) -#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) -#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) -#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL)) -#define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL)) -#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) -#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) -#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) -#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) -#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) -#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) -#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) -#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) -#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) -#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) -#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) -#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) -#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) -#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) -#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) -#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) -#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) -#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) -#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) -#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) -#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) -#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) -#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) -#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) -#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) -#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) -#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) -#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) -#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) -#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) -#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) -#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) -#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) -#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) -#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) -#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) -#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) -#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) -#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) -#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) -#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) -#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) -#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) -#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) -#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) -#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) -#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) -#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) -#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) -#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) -#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) -#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) -#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) -#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) -#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) -#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) -#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) -#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) -#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) -#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) -#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) -#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) -#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) -#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) -#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) -#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) -#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) -#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) -#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) -#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) -#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) -#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) -#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) -#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) -#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) -#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL)) -#define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL)) -#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) -#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) -#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) -#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) -#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) -#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) -#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) -#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL)) -#define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL)) -#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) -#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) -#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) - -/* Multifunction Timer unit 2 Free Running Timer registers */ -#define bFM3_MFT2_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42440600UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42440604UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42440608UL)) -#define bFM3_MFT2_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4244060CUL)) -#define bFM3_MFT2_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42440610UL)) -#define bFM3_MFT2_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42440614UL)) -#define bFM3_MFT2_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42440618UL)) -#define bFM3_MFT2_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4244061CUL)) -#define bFM3_MFT2_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42440620UL)) -#define bFM3_MFT2_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42440624UL)) -#define bFM3_MFT2_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42440634UL)) -#define bFM3_MFT2_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42440638UL)) -#define bFM3_MFT2_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4244063CUL)) -#define bFM3_MFT2_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42440680UL)) -#define bFM3_MFT2_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42440684UL)) -#define bFM3_MFT2_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42440688UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42440800UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42440804UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42440808UL)) -#define bFM3_MFT2_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4244080CUL)) -#define bFM3_MFT2_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42440810UL)) -#define bFM3_MFT2_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42440814UL)) -#define bFM3_MFT2_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42440818UL)) -#define bFM3_MFT2_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4244081CUL)) -#define bFM3_MFT2_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42440820UL)) -#define bFM3_MFT2_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42440824UL)) -#define bFM3_MFT2_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42440834UL)) -#define bFM3_MFT2_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42440838UL)) -#define bFM3_MFT2_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4244083CUL)) -#define bFM3_MFT2_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42440880UL)) -#define bFM3_MFT2_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42440884UL)) -#define bFM3_MFT2_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42440888UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42440A00UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42440A04UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42440A08UL)) -#define bFM3_MFT2_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42440A0CUL)) -#define bFM3_MFT2_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42440A10UL)) -#define bFM3_MFT2_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42440A14UL)) -#define bFM3_MFT2_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42440A18UL)) -#define bFM3_MFT2_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42440A1CUL)) -#define bFM3_MFT2_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42440A20UL)) -#define bFM3_MFT2_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42440A24UL)) -#define bFM3_MFT2_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42440A34UL)) -#define bFM3_MFT2_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42440A38UL)) -#define bFM3_MFT2_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42440A3CUL)) -#define bFM3_MFT2_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42440A80UL)) -#define bFM3_MFT2_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42440A84UL)) -#define bFM3_MFT2_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42440A88UL)) - -/* Multifunction Timer unit 2 Output Compare Unit registers */ -#define bFM3_MFT2_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42440300UL)) -#define bFM3_MFT2_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42440304UL)) -#define bFM3_MFT2_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42440308UL)) -#define bFM3_MFT2_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4244030CUL)) -#define bFM3_MFT2_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42440310UL)) -#define bFM3_MFT2_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42440314UL)) -#define bFM3_MFT2_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42440318UL)) -#define bFM3_MFT2_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4244031CUL)) -#define bFM3_MFT2_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42440320UL)) -#define bFM3_MFT2_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42440324UL)) -#define bFM3_MFT2_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42440330UL)) -#define bFM3_MFT2_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42440334UL)) -#define bFM3_MFT2_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42440338UL)) -#define bFM3_MFT2_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42440380UL)) -#define bFM3_MFT2_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42440384UL)) -#define bFM3_MFT2_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42440388UL)) -#define bFM3_MFT2_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4244038CUL)) -#define bFM3_MFT2_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42440390UL)) -#define bFM3_MFT2_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42440394UL)) -#define bFM3_MFT2_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42440398UL)) -#define bFM3_MFT2_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4244039CUL)) -#define bFM3_MFT2_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424403A0UL)) -#define bFM3_MFT2_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424403A4UL)) -#define bFM3_MFT2_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424403B0UL)) -#define bFM3_MFT2_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424403B4UL)) -#define bFM3_MFT2_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424403B8UL)) -#define bFM3_MFT2_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42440400UL)) -#define bFM3_MFT2_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42440404UL)) -#define bFM3_MFT2_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42440408UL)) -#define bFM3_MFT2_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4244040CUL)) -#define bFM3_MFT2_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42440410UL)) -#define bFM3_MFT2_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42440414UL)) -#define bFM3_MFT2_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42440418UL)) -#define bFM3_MFT2_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4244041CUL)) -#define bFM3_MFT2_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42440420UL)) -#define bFM3_MFT2_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42440424UL)) -#define bFM3_MFT2_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42440430UL)) -#define bFM3_MFT2_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42440434UL)) -#define bFM3_MFT2_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42440438UL)) -#define bFM3_MFT2_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424404A0UL)) -#define bFM3_MFT2_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424404A4UL)) -#define bFM3_MFT2_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424404A8UL)) -#define bFM3_MFT2_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424404ACUL)) -#define bFM3_MFT2_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424404B0UL)) -#define bFM3_MFT2_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424404B4UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42440B00UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42440B04UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42440B08UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42440B0CUL)) -#define bFM3_MFT2_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42440B10UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42440B14UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42440B18UL)) -#define bFM3_MFT2_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42440B1CUL)) -#define bFM3_MFT2_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42440B20UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42440B24UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42440B28UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42440B2CUL)) -#define bFM3_MFT2_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42440B30UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42440B34UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42440B38UL)) -#define bFM3_MFT2_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42440B3CUL)) -#define bFM3_MFT2_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42440B80UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42440B84UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42440B88UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42440B8CUL)) -#define bFM3_MFT2_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42440B90UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42440B94UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42440B98UL)) -#define bFM3_MFT2_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42440B9CUL)) - -/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT2_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42441180UL)) -#define bFM3_MFT2_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42441184UL)) -#define bFM3_MFT2_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42441188UL)) -#define bFM3_MFT2_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42441198UL)) -#define bFM3_MFT2_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4244119CUL)) -#define bFM3_MFT2_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424411A0UL)) -#define bFM3_MFT2_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424411A4UL)) -#define bFM3_MFT2_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424411A8UL)) -#define bFM3_MFT2_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424411ACUL)) -#define bFM3_MFT2_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424411B0UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42441200UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42441204UL)) -#define bFM3_MFT2_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42441208UL)) -#define bFM3_MFT2_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42441218UL)) -#define bFM3_MFT2_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4244121CUL)) -#define bFM3_MFT2_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42441220UL)) -#define bFM3_MFT2_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42441224UL)) -#define bFM3_MFT2_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42441228UL)) -#define bFM3_MFT2_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4244122CUL)) -#define bFM3_MFT2_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42441230UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42441280UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42441284UL)) -#define bFM3_MFT2_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42441288UL)) -#define bFM3_MFT2_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42441298UL)) -#define bFM3_MFT2_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4244129CUL)) -#define bFM3_MFT2_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424412A0UL)) -#define bFM3_MFT2_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424412A4UL)) -#define bFM3_MFT2_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424412A8UL)) -#define bFM3_MFT2_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424412ACUL)) -#define bFM3_MFT2_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424412B0UL)) -#define bFM3_MFT2_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42441300UL)) -#define bFM3_MFT2_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42441304UL)) -#define bFM3_MFT2_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42441310UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42441314UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42441318UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4244131CUL)) -#define bFM3_MFT2_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42441320UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42441324UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42441328UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4244132CUL)) -#define bFM3_MFT2_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42441330UL)) -#define bFM3_MFT2_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42441334UL)) -#define bFM3_MFT2_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42441338UL)) -#define bFM3_MFT2_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4244133CUL)) -#define bFM3_MFT2_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42441380UL)) -#define bFM3_MFT2_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42441384UL)) -#define bFM3_MFT2_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42441388UL)) -#define bFM3_MFT2_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4244138CUL)) -#define bFM3_MFT2_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42441390UL)) - -/* Multifunction Timer unit 2 Input Capture Unit registers */ -#define bFM3_MFT2_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42440C00UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42440C04UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42440C08UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42440C0CUL)) -#define bFM3_MFT2_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42440C10UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42440C14UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42440C18UL)) -#define bFM3_MFT2_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42440C1CUL)) -#define bFM3_MFT2_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42440C20UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42440C24UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42440C28UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42440C2CUL)) -#define bFM3_MFT2_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42440C30UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42440C34UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42440C38UL)) -#define bFM3_MFT2_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42440C3CUL)) -#define bFM3_MFT2_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42440F00UL)) -#define bFM3_MFT2_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42440F04UL)) -#define bFM3_MFT2_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42440F08UL)) -#define bFM3_MFT2_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42440F0CUL)) -#define bFM3_MFT2_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42440F10UL)) -#define bFM3_MFT2_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42440F14UL)) -#define bFM3_MFT2_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42440F18UL)) -#define bFM3_MFT2_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42440F1CUL)) -#define bFM3_MFT2_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42440F20UL)) -#define bFM3_MFT2_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42440F24UL)) -#define bFM3_MFT2_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42440F80UL)) -#define bFM3_MFT2_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42440F84UL)) -#define bFM3_MFT2_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42440F88UL)) -#define bFM3_MFT2_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42440F8CUL)) -#define bFM3_MFT2_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42440F90UL)) -#define bFM3_MFT2_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42440F94UL)) -#define bFM3_MFT2_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42440F98UL)) -#define bFM3_MFT2_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42440F9CUL)) -#define bFM3_MFT2_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42440FA0UL)) -#define bFM3_MFT2_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42440FA4UL)) - -/* Multifunction Timer unit 2 ADC Start Compare Unit registers */ -#define bFM3_MFT2_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42441700UL)) -#define bFM3_MFT2_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42441704UL)) -#define bFM3_MFT2_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42441708UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42441710UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42441714UL)) -#define bFM3_MFT2_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42441718UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42441780UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42441784UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42441788UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4244178CUL)) -#define bFM3_MFT2_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42441790UL)) -#define bFM3_MFT2_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42441794UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424417A0UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424417A4UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424417A8UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424417ACUL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424417B0UL)) -#define bFM3_MFT2_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424417B4UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42441800UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42441804UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42441808UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4244180CUL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42441810UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42441814UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42441820UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42441824UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42441828UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4244182CUL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42441830UL)) -#define bFM3_MFT2_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42441834UL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TTCR2_STR2 *((volatile unsigned int*)(0x42480820UL)) -#define bFM3_MFT_PPG_TTCR2_MONI2 *((volatile unsigned int*)(0x42480824UL)) -#define bFM3_MFT_PPG_TTCR2_CS20 *((volatile unsigned int*)(0x42480828UL)) -#define bFM3_MFT_PPG_TTCR2_CS21 *((volatile unsigned int*)(0x4248082CUL)) -#define bFM3_MFT_PPG_TTCR2_TRG16O *((volatile unsigned int*)(0x42480830UL)) -#define bFM3_MFT_PPG_TTCR2_TRG18O *((volatile unsigned int*)(0x42480834UL)) -#define bFM3_MFT_PPG_TTCR2_TRG20O *((volatile unsigned int*)(0x42480838UL)) -#define bFM3_MFT_PPG_TTCR2_TRG22O *((volatile unsigned int*)(0x4248083CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_TRG1_PEN16 *((volatile unsigned int*)(0x42482800UL)) -#define bFM3_MFT_PPG_TRG1_PEN17 *((volatile unsigned int*)(0x42482804UL)) -#define bFM3_MFT_PPG_TRG1_PEN18 *((volatile unsigned int*)(0x42482808UL)) -#define bFM3_MFT_PPG_TRG1_PEN19 *((volatile unsigned int*)(0x4248280CUL)) -#define bFM3_MFT_PPG_TRG1_PEN20 *((volatile unsigned int*)(0x42482810UL)) -#define bFM3_MFT_PPG_TRG1_PEN21 *((volatile unsigned int*)(0x42482814UL)) -#define bFM3_MFT_PPG_TRG1_PEN22 *((volatile unsigned int*)(0x42482818UL)) -#define bFM3_MFT_PPG_TRG1_PEN23 *((volatile unsigned int*)(0x4248281CUL)) -#define bFM3_MFT_PPG_REVC1_REV16 *((volatile unsigned int*)(0x42482880UL)) -#define bFM3_MFT_PPG_REVC1_REV17 *((volatile unsigned int*)(0x42482884UL)) -#define bFM3_MFT_PPG_REVC1_REV18 *((volatile unsigned int*)(0x42482888UL)) -#define bFM3_MFT_PPG_REVC1_REV19 *((volatile unsigned int*)(0x4248288CUL)) -#define bFM3_MFT_PPG_REVC1_REV20 *((volatile unsigned int*)(0x42482890UL)) -#define bFM3_MFT_PPG_REVC1_REV21 *((volatile unsigned int*)(0x42482894UL)) -#define bFM3_MFT_PPG_REVC1_REV22 *((volatile unsigned int*)(0x42482898UL)) -#define bFM3_MFT_PPG_REVC1_REV23 *((volatile unsigned int*)(0x4248289CUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) -#define bFM3_MFT_PPG_PPGC17_TTRG *((volatile unsigned int*)(0x42486000UL)) -#define bFM3_MFT_PPG_PPGC17_PCS0 *((volatile unsigned int*)(0x4248600CUL)) -#define bFM3_MFT_PPG_PPGC17_PCS1 *((volatile unsigned int*)(0x42486010UL)) -#define bFM3_MFT_PPG_PPGC17_INTM *((volatile unsigned int*)(0x42486014UL)) -#define bFM3_MFT_PPG_PPGC17_PUF *((volatile unsigned int*)(0x42486018UL)) -#define bFM3_MFT_PPG_PPGC17_PIE *((volatile unsigned int*)(0x4248601CUL)) -#define bFM3_MFT_PPG_PPGC16_TTRG *((volatile unsigned int*)(0x42486020UL)) -#define bFM3_MFT_PPG_PPGC16_PCS0 *((volatile unsigned int*)(0x4248602CUL)) -#define bFM3_MFT_PPG_PPGC16_PCS1 *((volatile unsigned int*)(0x42486030UL)) -#define bFM3_MFT_PPG_PPGC16_INTM *((volatile unsigned int*)(0x42486034UL)) -#define bFM3_MFT_PPG_PPGC16_PUF *((volatile unsigned int*)(0x42486038UL)) -#define bFM3_MFT_PPG_PPGC16_PIE *((volatile unsigned int*)(0x4248603CUL)) -#define bFM3_MFT_PPG_PPGC19_TTRG *((volatile unsigned int*)(0x42486080UL)) -#define bFM3_MFT_PPG_PPGC19_PCS0 *((volatile unsigned int*)(0x4248608CUL)) -#define bFM3_MFT_PPG_PPGC19_PCS1 *((volatile unsigned int*)(0x42486090UL)) -#define bFM3_MFT_PPG_PPGC19_INTM *((volatile unsigned int*)(0x42486094UL)) -#define bFM3_MFT_PPG_PPGC19_PUF *((volatile unsigned int*)(0x42486098UL)) -#define bFM3_MFT_PPG_PPGC19_PIE *((volatile unsigned int*)(0x4248609CUL)) -#define bFM3_MFT_PPG_PPGC18_TTRG *((volatile unsigned int*)(0x424860A0UL)) -#define bFM3_MFT_PPG_PPGC18_PCS0 *((volatile unsigned int*)(0x424860ACUL)) -#define bFM3_MFT_PPG_PPGC18_PCS1 *((volatile unsigned int*)(0x424860B0UL)) -#define bFM3_MFT_PPG_PPGC18_INTM *((volatile unsigned int*)(0x424860B4UL)) -#define bFM3_MFT_PPG_PPGC18_PUF *((volatile unsigned int*)(0x424860B8UL)) -#define bFM3_MFT_PPG_PPGC18_PIE *((volatile unsigned int*)(0x424860BCUL)) -#define bFM3_MFT_PPG_GATEC16_EDGE16 *((volatile unsigned int*)(0x42486300UL)) -#define bFM3_MFT_PPG_GATEC16_STRG16 *((volatile unsigned int*)(0x42486304UL)) -#define bFM3_MFT_PPG_GATEC16_EDGE18 *((volatile unsigned int*)(0x42486310UL)) -#define bFM3_MFT_PPG_GATEC16_STRG18 *((volatile unsigned int*)(0x42486314UL)) -#define bFM3_MFT_PPG_PPGC21_TTRG *((volatile unsigned int*)(0x42486800UL)) -#define bFM3_MFT_PPG_PPGC21_PCS0 *((volatile unsigned int*)(0x4248680CUL)) -#define bFM3_MFT_PPG_PPGC21_PCS1 *((volatile unsigned int*)(0x42486810UL)) -#define bFM3_MFT_PPG_PPGC21_INTM *((volatile unsigned int*)(0x42486814UL)) -#define bFM3_MFT_PPG_PPGC21_PUF *((volatile unsigned int*)(0x42486818UL)) -#define bFM3_MFT_PPG_PPGC21_PIE *((volatile unsigned int*)(0x4248681CUL)) -#define bFM3_MFT_PPG_PPGC20_TTRG *((volatile unsigned int*)(0x42486820UL)) -#define bFM3_MFT_PPG_PPGC20_PCS0 *((volatile unsigned int*)(0x4248682CUL)) -#define bFM3_MFT_PPG_PPGC20_PCS1 *((volatile unsigned int*)(0x42486830UL)) -#define bFM3_MFT_PPG_PPGC20_INTM *((volatile unsigned int*)(0x42486834UL)) -#define bFM3_MFT_PPG_PPGC20_PUF *((volatile unsigned int*)(0x42486838UL)) -#define bFM3_MFT_PPG_PPGC20_PIE *((volatile unsigned int*)(0x4248683CUL)) -#define bFM3_MFT_PPG_PPGC23_TTRG *((volatile unsigned int*)(0x42486880UL)) -#define bFM3_MFT_PPG_PPGC23_PCS0 *((volatile unsigned int*)(0x4248688CUL)) -#define bFM3_MFT_PPG_PPGC23_PCS1 *((volatile unsigned int*)(0x42486890UL)) -#define bFM3_MFT_PPG_PPGC23_INTM *((volatile unsigned int*)(0x42486894UL)) -#define bFM3_MFT_PPG_PPGC23_PUF *((volatile unsigned int*)(0x42486898UL)) -#define bFM3_MFT_PPG_PPGC23_PIE *((volatile unsigned int*)(0x4248689CUL)) -#define bFM3_MFT_PPG_PPGC22_TTRG *((volatile unsigned int*)(0x424868A0UL)) -#define bFM3_MFT_PPG_PPGC22_PCS0 *((volatile unsigned int*)(0x424868ACUL)) -#define bFM3_MFT_PPG_PPGC22_PCS1 *((volatile unsigned int*)(0x424868B0UL)) -#define bFM3_MFT_PPG_PPGC22_INTM *((volatile unsigned int*)(0x424868B4UL)) -#define bFM3_MFT_PPG_PPGC22_PUF *((volatile unsigned int*)(0x424868B8UL)) -#define bFM3_MFT_PPG_PPGC22_PIE *((volatile unsigned int*)(0x424868BCUL)) -#define bFM3_MFT_PPG_GATEC20_EDGE20 *((volatile unsigned int*)(0x42486B00UL)) -#define bFM3_MFT_PPG_GATEC20_STRG20 *((volatile unsigned int*)(0x42486B04UL)) -#define bFM3_MFT_PPG_GATEC20_EDGE22 *((volatile unsigned int*)(0x42486B10UL)) -#define bFM3_MFT_PPG_GATEC20_STRG22 *((volatile unsigned int*)(0x42486B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Base Timer 8 PPG registers */ -#define bFM3_BT8_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM3_BT8_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWM registers */ -#define bFM3_BT8_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A81ACUL)) -#define bFM3_BT8_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8204UL)) -#define bFM3_BT8_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8214UL)) -#define bFM3_BT8_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 RT registers */ -#define bFM3_BT8_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8180UL)) -#define bFM3_BT8_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A818CUL)) -#define bFM3_BT8_RT_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM3_BT8_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_RT_STC_UDIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_RT_STC_TGIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_RT_STC_UDIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_RT_STC_TGIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 8 PWC registers */ -#define bFM3_BT8_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8184UL)) -#define bFM3_BT8_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8188UL)) -#define bFM3_BT8_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A819CUL)) -#define bFM3_BT8_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A81A0UL)) -#define bFM3_BT8_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A81A4UL)) -#define bFM3_BT8_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A81A8UL)) -#define bFM3_BT8_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A81B0UL)) -#define bFM3_BT8_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A81B4UL)) -#define bFM3_BT8_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A81B8UL)) -#define bFM3_BT8_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8200UL)) -#define bFM3_BT8_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8208UL)) -#define bFM3_BT8_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8210UL)) -#define bFM3_BT8_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8218UL)) -#define bFM3_BT8_PWC_STC_ERR *((volatile unsigned int*)(0x424A821CUL)) -#define bFM3_BT8_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8220UL)) - -/* Base Timer 9 PPG registers */ -#define bFM3_BT9_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM3_BT9_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PPG_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PPG_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PPG_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PPG_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWM registers */ -#define bFM3_BT9_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A89ACUL)) -#define bFM3_BT9_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PWM_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PWM_STC_DTIR *((volatile unsigned int*)(0x424A8A04UL)) -#define bFM3_BT9_PWM_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PWM_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PWM_STC_DTIE *((volatile unsigned int*)(0x424A8A14UL)) -#define bFM3_BT9_PWM_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 RT registers */ -#define bFM3_BT9_RT_TMCR_STRG *((volatile unsigned int*)(0x424A8980UL)) -#define bFM3_BT9_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A898CUL)) -#define bFM3_BT9_RT_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM3_BT9_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_RT_STC_UDIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_RT_STC_TGIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_RT_STC_UDIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_RT_STC_TGIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 9 PWC registers */ -#define bFM3_BT9_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A8984UL)) -#define bFM3_BT9_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A8988UL)) -#define bFM3_BT9_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A899CUL)) -#define bFM3_BT9_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A89A0UL)) -#define bFM3_BT9_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A89A4UL)) -#define bFM3_BT9_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A89A8UL)) -#define bFM3_BT9_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A89B0UL)) -#define bFM3_BT9_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A89B4UL)) -#define bFM3_BT9_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A89B8UL)) -#define bFM3_BT9_PWC_STC_OVIR *((volatile unsigned int*)(0x424A8A00UL)) -#define bFM3_BT9_PWC_STC_EDIR *((volatile unsigned int*)(0x424A8A08UL)) -#define bFM3_BT9_PWC_STC_OVIE *((volatile unsigned int*)(0x424A8A10UL)) -#define bFM3_BT9_PWC_STC_EDIE *((volatile unsigned int*)(0x424A8A18UL)) -#define bFM3_BT9_PWC_STC_ERR *((volatile unsigned int*)(0x424A8A1CUL)) -#define bFM3_BT9_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A8A20UL)) - -/* Base Timer 10 PPG registers */ -#define bFM3_BT10_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM3_BT10_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWM registers */ -#define bFM3_BT10_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A91ACUL)) -#define bFM3_BT10_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9204UL)) -#define bFM3_BT10_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9214UL)) -#define bFM3_BT10_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 RT registers */ -#define bFM3_BT10_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9180UL)) -#define bFM3_BT10_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A918CUL)) -#define bFM3_BT10_RT_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM3_BT10_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_RT_STC_UDIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_RT_STC_TGIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_RT_STC_UDIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_RT_STC_TGIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 10 PWC registers */ -#define bFM3_BT10_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9184UL)) -#define bFM3_BT10_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9188UL)) -#define bFM3_BT10_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A919CUL)) -#define bFM3_BT10_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A91A0UL)) -#define bFM3_BT10_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A91A4UL)) -#define bFM3_BT10_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A91A8UL)) -#define bFM3_BT10_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A91B0UL)) -#define bFM3_BT10_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A91B4UL)) -#define bFM3_BT10_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A91B8UL)) -#define bFM3_BT10_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9200UL)) -#define bFM3_BT10_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9208UL)) -#define bFM3_BT10_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9210UL)) -#define bFM3_BT10_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9218UL)) -#define bFM3_BT10_PWC_STC_ERR *((volatile unsigned int*)(0x424A921CUL)) -#define bFM3_BT10_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9220UL)) - -/* Base Timer 11 PPG registers */ -#define bFM3_BT11_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM3_BT11_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PPG_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PPG_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PPG_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PPG_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWM registers */ -#define bFM3_BT11_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A99ACUL)) -#define bFM3_BT11_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PWM_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PWM_STC_DTIR *((volatile unsigned int*)(0x424A9A04UL)) -#define bFM3_BT11_PWM_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PWM_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PWM_STC_DTIE *((volatile unsigned int*)(0x424A9A14UL)) -#define bFM3_BT11_PWM_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 RT registers */ -#define bFM3_BT11_RT_TMCR_STRG *((volatile unsigned int*)(0x424A9980UL)) -#define bFM3_BT11_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A998CUL)) -#define bFM3_BT11_RT_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM3_BT11_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_RT_STC_UDIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_RT_STC_TGIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_RT_STC_UDIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_RT_STC_TGIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 11 PWC registers */ -#define bFM3_BT11_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A9984UL)) -#define bFM3_BT11_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A9988UL)) -#define bFM3_BT11_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A999CUL)) -#define bFM3_BT11_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A99A0UL)) -#define bFM3_BT11_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A99A4UL)) -#define bFM3_BT11_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A99A8UL)) -#define bFM3_BT11_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A99B0UL)) -#define bFM3_BT11_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A99B4UL)) -#define bFM3_BT11_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A99B8UL)) -#define bFM3_BT11_PWC_STC_OVIR *((volatile unsigned int*)(0x424A9A00UL)) -#define bFM3_BT11_PWC_STC_EDIR *((volatile unsigned int*)(0x424A9A08UL)) -#define bFM3_BT11_PWC_STC_OVIE *((volatile unsigned int*)(0x424A9A10UL)) -#define bFM3_BT11_PWC_STC_EDIE *((volatile unsigned int*)(0x424A9A18UL)) -#define bFM3_BT11_PWC_STC_ERR *((volatile unsigned int*)(0x424A9A1CUL)) -#define bFM3_BT11_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A9A20UL)) - -/* Base Timer 12 PPG registers */ -#define bFM3_BT12_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM3_BT12_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PPG_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PPG_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PPG_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PPG_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWM registers */ -#define bFM3_BT12_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC1ACUL)) -#define bFM3_BT12_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PWM_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PWM_STC_DTIR *((volatile unsigned int*)(0x424AC204UL)) -#define bFM3_BT12_PWM_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PWM_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PWM_STC_DTIE *((volatile unsigned int*)(0x424AC214UL)) -#define bFM3_BT12_PWM_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 RT registers */ -#define bFM3_BT12_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC180UL)) -#define bFM3_BT12_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC18CUL)) -#define bFM3_BT12_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM3_BT12_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_RT_STC_UDIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_RT_STC_TGIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_RT_STC_UDIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_RT_STC_TGIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 12 PWC registers */ -#define bFM3_BT12_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC184UL)) -#define bFM3_BT12_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC188UL)) -#define bFM3_BT12_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC19CUL)) -#define bFM3_BT12_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC1A0UL)) -#define bFM3_BT12_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC1A4UL)) -#define bFM3_BT12_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC1A8UL)) -#define bFM3_BT12_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC1B0UL)) -#define bFM3_BT12_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC1B4UL)) -#define bFM3_BT12_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC1B8UL)) -#define bFM3_BT12_PWC_STC_OVIR *((volatile unsigned int*)(0x424AC200UL)) -#define bFM3_BT12_PWC_STC_EDIR *((volatile unsigned int*)(0x424AC208UL)) -#define bFM3_BT12_PWC_STC_OVIE *((volatile unsigned int*)(0x424AC210UL)) -#define bFM3_BT12_PWC_STC_EDIE *((volatile unsigned int*)(0x424AC218UL)) -#define bFM3_BT12_PWC_STC_ERR *((volatile unsigned int*)(0x424AC21CUL)) -#define bFM3_BT12_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AC220UL)) - -/* Base Timer 13 PPG registers */ -#define bFM3_BT13_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM3_BT13_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PPG_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PPG_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PPG_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PPG_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWM registers */ -#define bFM3_BT13_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AC9ACUL)) -#define bFM3_BT13_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PWM_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PWM_STC_DTIR *((volatile unsigned int*)(0x424ACA04UL)) -#define bFM3_BT13_PWM_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PWM_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PWM_STC_DTIE *((volatile unsigned int*)(0x424ACA14UL)) -#define bFM3_BT13_PWM_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 RT registers */ -#define bFM3_BT13_RT_TMCR_STRG *((volatile unsigned int*)(0x424AC980UL)) -#define bFM3_BT13_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AC98CUL)) -#define bFM3_BT13_RT_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM3_BT13_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_RT_STC_UDIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_RT_STC_TGIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_RT_STC_UDIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_RT_STC_TGIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 13 PWC registers */ -#define bFM3_BT13_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AC984UL)) -#define bFM3_BT13_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AC988UL)) -#define bFM3_BT13_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AC99CUL)) -#define bFM3_BT13_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AC9A0UL)) -#define bFM3_BT13_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AC9A4UL)) -#define bFM3_BT13_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AC9A8UL)) -#define bFM3_BT13_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AC9B0UL)) -#define bFM3_BT13_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AC9B4UL)) -#define bFM3_BT13_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AC9B8UL)) -#define bFM3_BT13_PWC_STC_OVIR *((volatile unsigned int*)(0x424ACA00UL)) -#define bFM3_BT13_PWC_STC_EDIR *((volatile unsigned int*)(0x424ACA08UL)) -#define bFM3_BT13_PWC_STC_OVIE *((volatile unsigned int*)(0x424ACA10UL)) -#define bFM3_BT13_PWC_STC_EDIE *((volatile unsigned int*)(0x424ACA18UL)) -#define bFM3_BT13_PWC_STC_ERR *((volatile unsigned int*)(0x424ACA1CUL)) -#define bFM3_BT13_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ACA20UL)) - -/* Base Timer 14 PPG registers */ -#define bFM3_BT14_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM3_BT14_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PPG_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PPG_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PPG_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PPG_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWM registers */ -#define bFM3_BT14_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD1ACUL)) -#define bFM3_BT14_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PWM_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PWM_STC_DTIR *((volatile unsigned int*)(0x424AD204UL)) -#define bFM3_BT14_PWM_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PWM_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PWM_STC_DTIE *((volatile unsigned int*)(0x424AD214UL)) -#define bFM3_BT14_PWM_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 RT registers */ -#define bFM3_BT14_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD180UL)) -#define bFM3_BT14_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD18CUL)) -#define bFM3_BT14_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM3_BT14_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_RT_STC_UDIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_RT_STC_TGIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_RT_STC_UDIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_RT_STC_TGIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 14 PWC registers */ -#define bFM3_BT14_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD184UL)) -#define bFM3_BT14_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD188UL)) -#define bFM3_BT14_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD19CUL)) -#define bFM3_BT14_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD1A0UL)) -#define bFM3_BT14_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD1A4UL)) -#define bFM3_BT14_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD1A8UL)) -#define bFM3_BT14_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD1B0UL)) -#define bFM3_BT14_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD1B4UL)) -#define bFM3_BT14_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD1B8UL)) -#define bFM3_BT14_PWC_STC_OVIR *((volatile unsigned int*)(0x424AD200UL)) -#define bFM3_BT14_PWC_STC_EDIR *((volatile unsigned int*)(0x424AD208UL)) -#define bFM3_BT14_PWC_STC_OVIE *((volatile unsigned int*)(0x424AD210UL)) -#define bFM3_BT14_PWC_STC_EDIE *((volatile unsigned int*)(0x424AD218UL)) -#define bFM3_BT14_PWC_STC_ERR *((volatile unsigned int*)(0x424AD21CUL)) -#define bFM3_BT14_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424AD220UL)) - -/* Base Timer 15 PPG registers */ -#define bFM3_BT15_PPG_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM3_BT15_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PPG_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PPG_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PPG_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PPG_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWM registers */ -#define bFM3_BT15_PWM_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424AD9ACUL)) -#define bFM3_BT15_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PWM_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PWM_STC_DTIR *((volatile unsigned int*)(0x424ADA04UL)) -#define bFM3_BT15_PWM_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PWM_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PWM_STC_DTIE *((volatile unsigned int*)(0x424ADA14UL)) -#define bFM3_BT15_PWM_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 RT registers */ -#define bFM3_BT15_RT_TMCR_STRG *((volatile unsigned int*)(0x424AD980UL)) -#define bFM3_BT15_RT_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_RT_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_RT_TMCR_OSEL *((volatile unsigned int*)(0x424AD98CUL)) -#define bFM3_BT15_RT_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM3_BT15_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_RT_STC_UDIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_RT_STC_TGIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_RT_STC_UDIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_RT_STC_TGIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer 15 PWC registers */ -#define bFM3_BT15_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424AD984UL)) -#define bFM3_BT15_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424AD988UL)) -#define bFM3_BT15_PWC_TMCR_T32 *((volatile unsigned int*)(0x424AD99CUL)) -#define bFM3_BT15_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424AD9A0UL)) -#define bFM3_BT15_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424AD9A4UL)) -#define bFM3_BT15_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424AD9A8UL)) -#define bFM3_BT15_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424AD9B0UL)) -#define bFM3_BT15_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424AD9B4UL)) -#define bFM3_BT15_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424AD9B8UL)) -#define bFM3_BT15_PWC_STC_OVIR *((volatile unsigned int*)(0x424ADA00UL)) -#define bFM3_BT15_PWC_STC_EDIR *((volatile unsigned int*)(0x424ADA08UL)) -#define bFM3_BT15_PWC_STC_OVIE *((volatile unsigned int*)(0x424ADA10UL)) -#define bFM3_BT15_PWC_STC_EDIE *((volatile unsigned int*)(0x424ADA18UL)) -#define bFM3_BT15_PWC_STC_ERR *((volatile unsigned int*)(0x424ADA1CUL)) -#define bFM3_BT15_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424ADA20UL)) - -/* Base Timer I/O selector channel 8 - channel 11 registers */ -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0 *((volatile unsigned int*)(0x424AA020UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1 *((volatile unsigned int*)(0x424AA024UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2 *((volatile unsigned int*)(0x424AA028UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3 *((volatile unsigned int*)(0x424AA02CUL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0 *((volatile unsigned int*)(0x424AA030UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1 *((volatile unsigned int*)(0x424AA034UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2 *((volatile unsigned int*)(0x424AA038UL)) -#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3 *((volatile unsigned int*)(0x424AA03CUL)) - -/* Base Timer I/O selector channel 12 - channel 15 registers */ -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0 *((volatile unsigned int*)(0x424AE020UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1 *((volatile unsigned int*)(0x424AE024UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2 *((volatile unsigned int*)(0x424AE028UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3 *((volatile unsigned int*)(0x424AE02CUL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0 *((volatile unsigned int*)(0x424AE030UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1 *((volatile unsigned int*)(0x424AE034UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2 *((volatile unsigned int*)(0x424AE038UL)) -#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3 *((volatile unsigned int*)(0x424AE03CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* Quad position and revolution counter channel 2 registers */ -#define bFM3_QPRC2_QICR_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM3_QPRC2_QICR_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM3_QPRC2_QICR_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM3_QPRC2_QICR_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM3_QPRC2_QICR_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM3_QPRC2_QICR_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM3_QPRC2_QICR_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM3_QPRC2_QICR_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM3_QPRC2_QICR_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM3_QPRC2_QICR_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM3_QPRC2_QICR_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM3_QPRC2_QICR_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM3_QPRC2_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM3_QPRC2_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM3_QPRC2_QICRL_QPCMIE *((volatile unsigned int*)(0x424C1280UL)) -#define bFM3_QPRC2_QICRL_QPCMF *((volatile unsigned int*)(0x424C1284UL)) -#define bFM3_QPRC2_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C1288UL)) -#define bFM3_QPRC2_QICRL_QPRCMF *((volatile unsigned int*)(0x424C128CUL)) -#define bFM3_QPRC2_QICRL_OUZIE *((volatile unsigned int*)(0x424C1290UL)) -#define bFM3_QPRC2_QICRL_UFDF *((volatile unsigned int*)(0x424C1294UL)) -#define bFM3_QPRC2_QICRL_OFDF *((volatile unsigned int*)(0x424C1298UL)) -#define bFM3_QPRC2_QICRL_ZIIF *((volatile unsigned int*)(0x424C129CUL)) -#define bFM3_QPRC2_QICRH_CDCIE *((volatile unsigned int*)(0x424C12A0UL)) -#define bFM3_QPRC2_QICRH_CDCF *((volatile unsigned int*)(0x424C12A4UL)) -#define bFM3_QPRC2_QICRH_DIRPC *((volatile unsigned int*)(0x424C12A8UL)) -#define bFM3_QPRC2_QICRH_DIROU *((volatile unsigned int*)(0x424C12ACUL)) -#define bFM3_QPRC2_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C12B0UL)) -#define bFM3_QPRC2_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C12B4UL)) -#define bFM3_QPRC2_QCR_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM3_QPRC2_QCR_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM3_QPRC2_QCR_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM3_QPRC2_QCR_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM3_QPRC2_QCR_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM3_QPRC2_QCR_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM3_QPRC2_QCR_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM3_QPRC2_QCR_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM3_QPRC2_QCR_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM3_QPRC2_QCR_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM3_QPRC2_QCR_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM3_QPRC2_QCR_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM3_QPRC2_QCR_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM3_QPRC2_QCR_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM3_QPRC2_QCR_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM3_QPRC2_QCR_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM3_QPRC2_QCRL_PCM0 *((volatile unsigned int*)(0x424C1300UL)) -#define bFM3_QPRC2_QCRL_PCM1 *((volatile unsigned int*)(0x424C1304UL)) -#define bFM3_QPRC2_QCRL_RCM0 *((volatile unsigned int*)(0x424C1308UL)) -#define bFM3_QPRC2_QCRL_RCM1 *((volatile unsigned int*)(0x424C130CUL)) -#define bFM3_QPRC2_QCRL_PSTP *((volatile unsigned int*)(0x424C1310UL)) -#define bFM3_QPRC2_QCRL_CGSC *((volatile unsigned int*)(0x424C1314UL)) -#define bFM3_QPRC2_QCRL_RSEL *((volatile unsigned int*)(0x424C1318UL)) -#define bFM3_QPRC2_QCRL_SWAP *((volatile unsigned int*)(0x424C131CUL)) -#define bFM3_QPRC2_QCRH_PCRM0 *((volatile unsigned int*)(0x424C1320UL)) -#define bFM3_QPRC2_QCRH_PCRM1 *((volatile unsigned int*)(0x424C1324UL)) -#define bFM3_QPRC2_QCRH_AES0 *((volatile unsigned int*)(0x424C1328UL)) -#define bFM3_QPRC2_QCRH_AES1 *((volatile unsigned int*)(0x424C132CUL)) -#define bFM3_QPRC2_QCRH_BES0 *((volatile unsigned int*)(0x424C1330UL)) -#define bFM3_QPRC2_QCRH_BES1 *((volatile unsigned int*)(0x424C1334UL)) -#define bFM3_QPRC2_QCRH_CGE0 *((volatile unsigned int*)(0x424C1338UL)) -#define bFM3_QPRC2_QCRH_CGE1 *((volatile unsigned int*)(0x424C133CUL)) -#define bFM3_QPRC2_QECR_ORNGMD *((volatile unsigned int*)(0x424C1380UL)) -#define bFM3_QPRC2_QECR_ORNGF *((volatile unsigned int*)(0x424C1384UL)) -#define bFM3_QPRC2_QECR_ORNGIE *((volatile unsigned int*)(0x424C1388UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL)) -#define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL)) -#define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL)) -#define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL)) -#define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL)) -#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) -#define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL)) -#define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL)) -#define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL)) -#define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL)) -#define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL)) -#define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL)) -#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) -#define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL)) -#define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM3_ADC2_ADCT_CT3 *((volatile unsigned int*)(0x424E468CUL)) -#define bFM3_ADC2_ADCT_CT4 *((volatile unsigned int*)(0x424E4690UL)) -#define bFM3_ADC2_ADCT_CT5 *((volatile unsigned int*)(0x424E4694UL)) -#define bFM3_ADC2_ADCT_CT6 *((volatile unsigned int*)(0x424E4698UL)) -#define bFM3_ADC2_ADCT_CT7 *((volatile unsigned int*)(0x424E469CUL)) -#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) -#define bFM3_ADC2_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E4790UL)) -#define bFM3_ADC2_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E4794UL)) - -/* CR trimming registers */ -#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) - -/* External interrupt registers */ -#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM3_EXTI_ENIR_EN16 *((volatile unsigned int*)(0x42600040UL)) -#define bFM3_EXTI_ENIR_EN17 *((volatile unsigned int*)(0x42600044UL)) -#define bFM3_EXTI_ENIR_EN18 *((volatile unsigned int*)(0x42600048UL)) -#define bFM3_EXTI_ENIR_EN19 *((volatile unsigned int*)(0x4260004CUL)) -#define bFM3_EXTI_ENIR_EN20 *((volatile unsigned int*)(0x42600050UL)) -#define bFM3_EXTI_ENIR_EN21 *((volatile unsigned int*)(0x42600054UL)) -#define bFM3_EXTI_ENIR_EN22 *((volatile unsigned int*)(0x42600058UL)) -#define bFM3_EXTI_ENIR_EN23 *((volatile unsigned int*)(0x4260005CUL)) -#define bFM3_EXTI_ENIR_EN24 *((volatile unsigned int*)(0x42600060UL)) -#define bFM3_EXTI_ENIR_EN25 *((volatile unsigned int*)(0x42600064UL)) -#define bFM3_EXTI_ENIR_EN26 *((volatile unsigned int*)(0x42600068UL)) -#define bFM3_EXTI_ENIR_EN27 *((volatile unsigned int*)(0x4260006CUL)) -#define bFM3_EXTI_ENIR_EN28 *((volatile unsigned int*)(0x42600070UL)) -#define bFM3_EXTI_ENIR_EN29 *((volatile unsigned int*)(0x42600074UL)) -#define bFM3_EXTI_ENIR_EN30 *((volatile unsigned int*)(0x42600078UL)) -#define bFM3_EXTI_ENIR_EN31 *((volatile unsigned int*)(0x4260007CUL)) -#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM3_EXTI_EIRR_ER16 *((volatile unsigned int*)(0x426000C0UL)) -#define bFM3_EXTI_EIRR_ER17 *((volatile unsigned int*)(0x426000C4UL)) -#define bFM3_EXTI_EIRR_ER18 *((volatile unsigned int*)(0x426000C8UL)) -#define bFM3_EXTI_EIRR_ER19 *((volatile unsigned int*)(0x426000CCUL)) -#define bFM3_EXTI_EIRR_ER20 *((volatile unsigned int*)(0x426000D0UL)) -#define bFM3_EXTI_EIRR_ER21 *((volatile unsigned int*)(0x426000D4UL)) -#define bFM3_EXTI_EIRR_ER22 *((volatile unsigned int*)(0x426000D8UL)) -#define bFM3_EXTI_EIRR_ER23 *((volatile unsigned int*)(0x426000DCUL)) -#define bFM3_EXTI_EIRR_ER24 *((volatile unsigned int*)(0x426000E0UL)) -#define bFM3_EXTI_EIRR_ER25 *((volatile unsigned int*)(0x426000E4UL)) -#define bFM3_EXTI_EIRR_ER26 *((volatile unsigned int*)(0x426000E8UL)) -#define bFM3_EXTI_EIRR_ER27 *((volatile unsigned int*)(0x426000ECUL)) -#define bFM3_EXTI_EIRR_ER28 *((volatile unsigned int*)(0x426000F0UL)) -#define bFM3_EXTI_EIRR_ER29 *((volatile unsigned int*)(0x426000F4UL)) -#define bFM3_EXTI_EIRR_ER30 *((volatile unsigned int*)(0x426000F8UL)) -#define bFM3_EXTI_EIRR_ER31 *((volatile unsigned int*)(0x426000FCUL)) -#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM3_EXTI_EICL_ECL16 *((volatile unsigned int*)(0x42600140UL)) -#define bFM3_EXTI_EICL_ECL17 *((volatile unsigned int*)(0x42600144UL)) -#define bFM3_EXTI_EICL_ECL18 *((volatile unsigned int*)(0x42600148UL)) -#define bFM3_EXTI_EICL_ECL19 *((volatile unsigned int*)(0x4260014CUL)) -#define bFM3_EXTI_EICL_ECL20 *((volatile unsigned int*)(0x42600150UL)) -#define bFM3_EXTI_EICL_ECL21 *((volatile unsigned int*)(0x42600154UL)) -#define bFM3_EXTI_EICL_ECL22 *((volatile unsigned int*)(0x42600158UL)) -#define bFM3_EXTI_EICL_ECL23 *((volatile unsigned int*)(0x4260015CUL)) -#define bFM3_EXTI_EICL_ECL24 *((volatile unsigned int*)(0x42600160UL)) -#define bFM3_EXTI_EICL_ECL25 *((volatile unsigned int*)(0x42600164UL)) -#define bFM3_EXTI_EICL_ECL26 *((volatile unsigned int*)(0x42600168UL)) -#define bFM3_EXTI_EICL_ECL27 *((volatile unsigned int*)(0x4260016CUL)) -#define bFM3_EXTI_EICL_ECL28 *((volatile unsigned int*)(0x42600170UL)) -#define bFM3_EXTI_EICL_ECL29 *((volatile unsigned int*)(0x42600174UL)) -#define bFM3_EXTI_EICL_ECL30 *((volatile unsigned int*)(0x42600178UL)) -#define bFM3_EXTI_EICL_ECL31 *((volatile unsigned int*)(0x4260017CUL)) -#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM3_EXTI_ELVR_LA16 *((volatile unsigned int*)(0x42600200UL)) -#define bFM3_EXTI_ELVR_LB16 *((volatile unsigned int*)(0x42600204UL)) -#define bFM3_EXTI_ELVR_LA17 *((volatile unsigned int*)(0x42600208UL)) -#define bFM3_EXTI_ELVR_LB17 *((volatile unsigned int*)(0x4260020CUL)) -#define bFM3_EXTI_ELVR_LA18 *((volatile unsigned int*)(0x42600210UL)) -#define bFM3_EXTI_ELVR_LB18 *((volatile unsigned int*)(0x42600214UL)) -#define bFM3_EXTI_ELVR_LA19 *((volatile unsigned int*)(0x42600218UL)) -#define bFM3_EXTI_ELVR_LB19 *((volatile unsigned int*)(0x4260021CUL)) -#define bFM3_EXTI_ELVR_LA20 *((volatile unsigned int*)(0x42600220UL)) -#define bFM3_EXTI_ELVR_LB20 *((volatile unsigned int*)(0x42600224UL)) -#define bFM3_EXTI_ELVR_LA21 *((volatile unsigned int*)(0x42600228UL)) -#define bFM3_EXTI_ELVR_LB21 *((volatile unsigned int*)(0x4260022CUL)) -#define bFM3_EXTI_ELVR_LA22 *((volatile unsigned int*)(0x42600230UL)) -#define bFM3_EXTI_ELVR_LB22 *((volatile unsigned int*)(0x42600234UL)) -#define bFM3_EXTI_ELVR_LA23 *((volatile unsigned int*)(0x42600238UL)) -#define bFM3_EXTI_ELVR_LB23 *((volatile unsigned int*)(0x4260023CUL)) -#define bFM3_EXTI_ELVR_LA24 *((volatile unsigned int*)(0x42600240UL)) -#define bFM3_EXTI_ELVR_LB24 *((volatile unsigned int*)(0x42600244UL)) -#define bFM3_EXTI_ELVR_LA25 *((volatile unsigned int*)(0x42600248UL)) -#define bFM3_EXTI_ELVR_LB25 *((volatile unsigned int*)(0x4260024CUL)) -#define bFM3_EXTI_ELVR_LA26 *((volatile unsigned int*)(0x42600250UL)) -#define bFM3_EXTI_ELVR_LB26 *((volatile unsigned int*)(0x42600254UL)) -#define bFM3_EXTI_ELVR_LA27 *((volatile unsigned int*)(0x42600258UL)) -#define bFM3_EXTI_ELVR_LB27 *((volatile unsigned int*)(0x4260025CUL)) -#define bFM3_EXTI_ELVR_LA28 *((volatile unsigned int*)(0x42600260UL)) -#define bFM3_EXTI_ELVR_LB28 *((volatile unsigned int*)(0x42600264UL)) -#define bFM3_EXTI_ELVR_LA29 *((volatile unsigned int*)(0x42600268UL)) -#define bFM3_EXTI_ELVR_LB29 *((volatile unsigned int*)(0x4260026CUL)) -#define bFM3_EXTI_ELVR_LA30 *((volatile unsigned int*)(0x42600270UL)) -#define bFM3_EXTI_ELVR_LB30 *((volatile unsigned int*)(0x42600274UL)) -#define bFM3_EXTI_ELVR_LA31 *((volatile unsigned int*)(0x42600278UL)) -#define bFM3_EXTI_ELVR_LB31 *((volatile unsigned int*)(0x4260027CUL)) -#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) -#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned char*)(0x42620160UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned char*)(0x42620164UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned char*)(0x42620168UL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned char*)(0x4262016CUL)) -#define bFM3_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned char*)(0x42620170UL)) -#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) -#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) -#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) -#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) -#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT0 *((volatile unsigned int*)(0x42620420UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT1 *((volatile unsigned int*)(0x42620424UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT2 *((volatile unsigned int*)(0x42620428UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE2INT3 *((volatile unsigned int*)(0x4262042CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT8 *((volatile unsigned int*)(0x42620520UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT9 *((volatile unsigned int*)(0x42620524UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT10 *((volatile unsigned int*)(0x42620528UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT11 *((volatile unsigned int*)(0x4262052CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT12 *((volatile unsigned int*)(0x42620530UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT13 *((volatile unsigned int*)(0x42620534UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT14 *((volatile unsigned int*)(0x42620538UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT15 *((volatile unsigned int*)(0x4262053CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT16 *((volatile unsigned int*)(0x42620540UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT17 *((volatile unsigned int*)(0x42620544UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT18 *((volatile unsigned int*)(0x42620548UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT19 *((volatile unsigned int*)(0x4262054CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT20 *((volatile unsigned int*)(0x42620550UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT21 *((volatile unsigned int*)(0x42620554UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT22 *((volatile unsigned int*)(0x42620558UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT23 *((volatile unsigned int*)(0x4262055CUL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620580UL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT2 *((volatile unsigned int*)(0x42620584UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT0 *((volatile unsigned int*)(0x426205B8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT1 *((volatile unsigned int*)(0x426205BCUL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT2 *((volatile unsigned int*)(0x426205C0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT3 *((volatile unsigned int*)(0x426205C4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT4 *((volatile unsigned int*)(0x426205C8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD2INT5 *((volatile unsigned int*)(0x426205CCUL)) -#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) -#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) -#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) -#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) -#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) -#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) -#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) -#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT6 *((volatile unsigned int*)(0x42620E18UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT7 *((volatile unsigned int*)(0x42620E1CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT8 *((volatile unsigned int*)(0x42620E20UL)) -#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) -#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) -#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) -#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) -#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT0 *((volatile unsigned int*)(0x426210B0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT1 *((volatile unsigned int*)(0x426210B4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT2 *((volatile unsigned int*)(0x426210B8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT3 *((volatile unsigned int*)(0x426210BCUL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT4 *((volatile unsigned int*)(0x426210C0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT2INT5 *((volatile unsigned int*)(0x426210C4UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT0 *((volatile unsigned int*)(0x42621120UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT1 *((volatile unsigned int*)(0x42621124UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT2 *((volatile unsigned int*)(0x42621128UL)) -#define bFM3_INTREQ_IRQ29MON_ICU2INT3 *((volatile unsigned int*)(0x4262112CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT0 *((volatile unsigned int*)(0x426211B0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT1 *((volatile unsigned int*)(0x426211B4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT2 *((volatile unsigned int*)(0x426211B8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT3 *((volatile unsigned int*)(0x426211BCUL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT4 *((volatile unsigned int*)(0x426211C0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU2INT5 *((volatile unsigned int*)(0x426211C4UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) -#define bFM3_INTREQ_IRQ32MON_MAC0SBD *((volatile unsigned int*)(0x42621284UL)) -#define bFM3_INTREQ_IRQ32MON_MAC0PMI *((volatile unsigned int*)(0x42621288UL)) -#define bFM3_INTREQ_IRQ32MON_MAC0LPI *((volatile unsigned int*)(0x4262128CUL)) -#define bFM3_INTREQ_IRQ33MON_MAC1SBD *((volatile unsigned int*)(0x42621304UL)) -#define bFM3_INTREQ_IRQ33MON_MAC1PMI *((volatile unsigned int*)(0x42621308UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT0 *((volatile unsigned int*)(0x42621480UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT1 *((volatile unsigned int*)(0x42621484UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT2 *((volatile unsigned int*)(0x42621488UL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT3 *((volatile unsigned int*)(0x4262148CUL)) -#define bFM3_INTREQ_IRQ36MON_USB1INT4 *((volatile unsigned int*)(0x42621490UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT0 *((volatile unsigned int*)(0x42621500UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT1 *((volatile unsigned int*)(0x42621504UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT2 *((volatile unsigned int*)(0x42621508UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT3 *((volatile unsigned int*)(0x4262150CUL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT4 *((volatile unsigned int*)(0x42621510UL)) -#define bFM3_INTREQ_IRQ37MON_USB1INT5 *((volatile unsigned int*)(0x42621514UL)) -#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) -#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) -#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) -#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) -#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) -#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) -#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) -#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT0 *((volatile unsigned int*)(0x42621980UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT1 *((volatile unsigned int*)(0x42621984UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT2 *((volatile unsigned int*)(0x42621988UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT3 *((volatile unsigned int*)(0x4262198CUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT4 *((volatile unsigned int*)(0x42621990UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT5 *((volatile unsigned int*)(0x42621994UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT6 *((volatile unsigned int*)(0x42621998UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT7 *((volatile unsigned int*)(0x4262199CUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT8 *((volatile unsigned int*)(0x426219A0UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT9 *((volatile unsigned int*)(0x426219A4UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT10 *((volatile unsigned int*)(0x426219A8UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT11 *((volatile unsigned int*)(0x426219ACUL)) -#define bFM3_INTREQ_IRQ46MON_BTINT12 *((volatile unsigned int*)(0x426219B0UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT13 *((volatile unsigned int*)(0x426219B4UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT14 *((volatile unsigned int*)(0x426219B8UL)) -#define bFM3_INTREQ_IRQ46MON_BTINT15 *((volatile unsigned int*)(0x426219BCUL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL10 *((volatile unsigned int*)(0x42624000UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL11 *((volatile unsigned int*)(0x42624004UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL12 *((volatile unsigned int*)(0x42624008UL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL13 *((volatile unsigned int*)(0x4262400CUL)) -#define bFM3_INTREQ_DRQSEL1_DRQSEL14 *((volatile unsigned int*)(0x42624010UL)) -#define bFM3_INTREQ_DQESEL_ESEL100 *((volatile unsigned int*)(0x42624080UL)) -#define bFM3_INTREQ_DQESEL_ESEL101 *((volatile unsigned int*)(0x42624084UL)) -#define bFM3_INTREQ_DQESEL_ESEL102 *((volatile unsigned int*)(0x42624088UL)) -#define bFM3_INTREQ_DQESEL_ESEL103 *((volatile unsigned int*)(0x4262408CUL)) -#define bFM3_INTREQ_DQESEL_ESEL110 *((volatile unsigned int*)(0x42624090UL)) -#define bFM3_INTREQ_DQESEL_ESEL111 *((volatile unsigned int*)(0x42624094UL)) -#define bFM3_INTREQ_DQESEL_ESEL112 *((volatile unsigned int*)(0x42624098UL)) -#define bFM3_INTREQ_DQESEL_ESEL113 *((volatile unsigned int*)(0x4262409CUL)) -#define bFM3_INTREQ_DQESEL_ESEL240 *((volatile unsigned int*)(0x426240A0UL)) -#define bFM3_INTREQ_DQESEL_ESEL241 *((volatile unsigned int*)(0x426240A4UL)) -#define bFM3_INTREQ_DQESEL_ESEL242 *((volatile unsigned int*)(0x426240A8UL)) -#define bFM3_INTREQ_DQESEL_ESEL243 *((volatile unsigned int*)(0x426240ACUL)) -#define bFM3_INTREQ_DQESEL_ESEL250 *((volatile unsigned int*)(0x426240B0UL)) -#define bFM3_INTREQ_DQESEL_ESEL251 *((volatile unsigned int*)(0x426240B4UL)) -#define bFM3_INTREQ_DQESEL_ESEL252 *((volatile unsigned int*)(0x426240B8UL)) -#define bFM3_INTREQ_DQESEL_ESEL253 *((volatile unsigned int*)(0x426240BCUL)) -#define bFM3_INTREQ_DQESEL_ESEL260 *((volatile unsigned int*)(0x426240C0UL)) -#define bFM3_INTREQ_DQESEL_ESEL261 *((volatile unsigned int*)(0x426240C4UL)) -#define bFM3_INTREQ_DQESEL_ESEL262 *((volatile unsigned int*)(0x426240C8UL)) -#define bFM3_INTREQ_DQESEL_ESEL263 *((volatile unsigned int*)(0x426240CCUL)) -#define bFM3_INTREQ_DQESEL_ESEL270 *((volatile unsigned int*)(0x426240D0UL)) -#define bFM3_INTREQ_DQESEL_ESEL271 *((volatile unsigned int*)(0x426240D4UL)) -#define bFM3_INTREQ_DQESEL_ESEL272 *((volatile unsigned int*)(0x426240D8UL)) -#define bFM3_INTREQ_DQESEL_ESEL273 *((volatile unsigned int*)(0x426240DCUL)) -#define bFM3_INTREQ_DQESEL_ESEL300 *((volatile unsigned int*)(0x426240E0UL)) -#define bFM3_INTREQ_DQESEL_ESEL301 *((volatile unsigned int*)(0x426240E4UL)) -#define bFM3_INTREQ_DQESEL_ESEL302 *((volatile unsigned int*)(0x426240E8UL)) -#define bFM3_INTREQ_DQESEL_ESEL303 *((volatile unsigned int*)(0x426240ECUL)) -#define bFM3_INTREQ_DQESEL_ESEL310 *((volatile unsigned int*)(0x426240F0UL)) -#define bFM3_INTREQ_DQESEL_ESEL311 *((volatile unsigned int*)(0x426240F4UL)) -#define bFM3_INTREQ_DQESEL_ESEL312 *((volatile unsigned int*)(0x426240F8UL)) -#define bFM3_INTREQ_DQESEL_ESEL313 *((volatile unsigned int*)(0x426240FCUL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS10 *((volatile unsigned char*)(0x426241E0UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS11 *((volatile unsigned char*)(0x426241E4UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS12 *((volatile unsigned char*)(0x426241E8UL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS13 *((volatile unsigned char*)(0x426241ECUL)) -#define bFM3_INTREQ_ODDPKS1_ODDPKS14 *((volatile unsigned char*)(0x426241F0UL)) - -/* General purpose I/O registers */ -#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) -#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) -#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) -#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) -#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) -#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) -#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) -#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) -#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) -#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) -#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) -#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) -#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) -#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) -#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) -#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) -#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) -#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) -#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) -#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) -#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) -#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) -#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) -#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) -#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) -#define bFM3_GPIO_PFR2_P9 *((volatile unsigned int*)(0x42660124UL)) -#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) -#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) -#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) -#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) -#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) -#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) -#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) -#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) -#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) -#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) -#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) -#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) -#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) -#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) -#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) -#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) -#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) -#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) -#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) -#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) -#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) -#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) -#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) -#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) -#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) -#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) -#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) -#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) -#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) -#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) -#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) -#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) -#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) -#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) -#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) -#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) -#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) -#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) -#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) -#define bFM3_GPIO_PFR5_PC *((volatile unsigned int*)(0x426602B0UL)) -#define bFM3_GPIO_PFR5_PD *((volatile unsigned int*)(0x426602B4UL)) -#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) -#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) -#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) -#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) -#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) -#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) -#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) -#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) -#define bFM3_GPIO_PFR7_P5 *((volatile unsigned int*)(0x42660394UL)) -#define bFM3_GPIO_PFR7_P6 *((volatile unsigned int*)(0x42660398UL)) -#define bFM3_GPIO_PFR7_P7 *((volatile unsigned int*)(0x4266039CUL)) -#define bFM3_GPIO_PFR7_P8 *((volatile unsigned int*)(0x426603A0UL)) -#define bFM3_GPIO_PFR7_P9 *((volatile unsigned int*)(0x426603A4UL)) -#define bFM3_GPIO_PFR7_PA *((volatile unsigned int*)(0x426603A8UL)) -#define bFM3_GPIO_PFR7_PB *((volatile unsigned int*)(0x426603ACUL)) -#define bFM3_GPIO_PFR7_PC *((volatile unsigned int*)(0x426603B0UL)) -#define bFM3_GPIO_PFR7_PD *((volatile unsigned int*)(0x426603B4UL)) -#define bFM3_GPIO_PFR7_PE *((volatile unsigned int*)(0x426603B8UL)) -#define bFM3_GPIO_PFR7_PF *((volatile unsigned int*)(0x426603BCUL)) -#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) -#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) -#define bFM3_GPIO_PFR8_P2 *((volatile unsigned int*)(0x42660408UL)) -#define bFM3_GPIO_PFR8_P3 *((volatile unsigned int*)(0x4266040CUL)) -#define bFM3_GPIO_PFR9_P0 *((volatile unsigned int*)(0x42660480UL)) -#define bFM3_GPIO_PFR9_P1 *((volatile unsigned int*)(0x42660484UL)) -#define bFM3_GPIO_PFR9_P2 *((volatile unsigned int*)(0x42660488UL)) -#define bFM3_GPIO_PFR9_P3 *((volatile unsigned int*)(0x4266048CUL)) -#define bFM3_GPIO_PFR9_P4 *((volatile unsigned int*)(0x42660490UL)) -#define bFM3_GPIO_PFR9_P5 *((volatile unsigned int*)(0x42660494UL)) -#define bFM3_GPIO_PFRA_P0 *((volatile unsigned int*)(0x42660500UL)) -#define bFM3_GPIO_PFRA_P1 *((volatile unsigned int*)(0x42660504UL)) -#define bFM3_GPIO_PFRA_P2 *((volatile unsigned int*)(0x42660508UL)) -#define bFM3_GPIO_PFRA_P3 *((volatile unsigned int*)(0x4266050CUL)) -#define bFM3_GPIO_PFRA_P4 *((volatile unsigned int*)(0x42660510UL)) -#define bFM3_GPIO_PFRA_P5 *((volatile unsigned int*)(0x42660514UL)) -#define bFM3_GPIO_PFRB_P0 *((volatile unsigned int*)(0x42660580UL)) -#define bFM3_GPIO_PFRB_P1 *((volatile unsigned int*)(0x42660584UL)) -#define bFM3_GPIO_PFRB_P2 *((volatile unsigned int*)(0x42660588UL)) -#define bFM3_GPIO_PFRB_P3 *((volatile unsigned int*)(0x4266058CUL)) -#define bFM3_GPIO_PFRB_P4 *((volatile unsigned int*)(0x42660590UL)) -#define bFM3_GPIO_PFRB_P5 *((volatile unsigned int*)(0x42660594UL)) -#define bFM3_GPIO_PFRB_P6 *((volatile unsigned int*)(0x42660598UL)) -#define bFM3_GPIO_PFRB_P7 *((volatile unsigned int*)(0x4266059CUL)) -#define bFM3_GPIO_PFRC_P0 *((volatile unsigned int*)(0x42660600UL)) -#define bFM3_GPIO_PFRC_P1 *((volatile unsigned int*)(0x42660604UL)) -#define bFM3_GPIO_PFRC_P2 *((volatile unsigned int*)(0x42660608UL)) -#define bFM3_GPIO_PFRC_P3 *((volatile unsigned int*)(0x4266060CUL)) -#define bFM3_GPIO_PFRC_P4 *((volatile unsigned int*)(0x42660610UL)) -#define bFM3_GPIO_PFRC_P5 *((volatile unsigned int*)(0x42660614UL)) -#define bFM3_GPIO_PFRC_P6 *((volatile unsigned int*)(0x42660618UL)) -#define bFM3_GPIO_PFRC_P7 *((volatile unsigned int*)(0x4266061CUL)) -#define bFM3_GPIO_PFRC_P8 *((volatile unsigned int*)(0x42660620UL)) -#define bFM3_GPIO_PFRC_P9 *((volatile unsigned int*)(0x42660624UL)) -#define bFM3_GPIO_PFRC_PA *((volatile unsigned int*)(0x42660628UL)) -#define bFM3_GPIO_PFRC_PB *((volatile unsigned int*)(0x4266062CUL)) -#define bFM3_GPIO_PFRC_PC *((volatile unsigned int*)(0x42660630UL)) -#define bFM3_GPIO_PFRC_PD *((volatile unsigned int*)(0x42660634UL)) -#define bFM3_GPIO_PFRC_PE *((volatile unsigned int*)(0x42660638UL)) -#define bFM3_GPIO_PFRC_PF *((volatile unsigned int*)(0x4266063CUL)) -#define bFM3_GPIO_PFRD_P0 *((volatile unsigned int*)(0x42660680UL)) -#define bFM3_GPIO_PFRD_P1 *((volatile unsigned int*)(0x42660684UL)) -#define bFM3_GPIO_PFRD_P2 *((volatile unsigned int*)(0x42660688UL)) -#define bFM3_GPIO_PFRD_P3 *((volatile unsigned int*)(0x4266068CUL)) -#define bFM3_GPIO_PFRE_P0 *((volatile unsigned int*)(0x42660700UL)) -#define bFM3_GPIO_PFRE_P2 *((volatile unsigned int*)(0x42660708UL)) -#define bFM3_GPIO_PFRE_P3 *((volatile unsigned int*)(0x4266070CUL)) -#define bFM3_GPIO_PFRF_P0 *((volatile unsigned int*)(0x42660780UL)) -#define bFM3_GPIO_PFRF_P1 *((volatile unsigned int*)(0x42660784UL)) -#define bFM3_GPIO_PFRF_P2 *((volatile unsigned int*)(0x42660788UL)) -#define bFM3_GPIO_PFRF_P3 *((volatile unsigned int*)(0x4266078CUL)) -#define bFM3_GPIO_PFRF_P4 *((volatile unsigned int*)(0x42660790UL)) -#define bFM3_GPIO_PFRF_P5 *((volatile unsigned int*)(0x42660794UL)) -#define bFM3_GPIO_PFRF_P6 *((volatile unsigned int*)(0x42660798UL)) -#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) -#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) -#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) -#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) -#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) -#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) -#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) -#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) -#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) -#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) -#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) -#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) -#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) -#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) -#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) -#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) -#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) -#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) -#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) -#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) -#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) -#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) -#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) -#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) -#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) -#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) -#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) -#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) -#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) -#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) -#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) -#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) -#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) -#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) -#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) -#define bFM3_GPIO_PCR2_P9 *((volatile unsigned int*)(0x42662124UL)) -#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) -#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) -#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) -#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) -#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) -#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) -#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) -#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) -#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) -#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) -#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) -#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) -#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) -#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) -#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) -#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) -#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) -#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) -#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) -#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) -#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) -#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) -#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) -#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) -#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) -#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) -#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) -#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) -#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) -#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) -#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) -#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) -#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) -#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) -#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) -#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) -#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) -#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) -#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) -#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) -#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) -#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) -#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) -#define bFM3_GPIO_PCR5_PC *((volatile unsigned int*)(0x426622B0UL)) -#define bFM3_GPIO_PCR5_PD *((volatile unsigned int*)(0x426622B4UL)) -#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) -#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) -#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) -#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) -#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) -#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) -#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) -#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) -#define bFM3_GPIO_PCR7_P5 *((volatile unsigned int*)(0x42662394UL)) -#define bFM3_GPIO_PCR7_P6 *((volatile unsigned int*)(0x42662398UL)) -#define bFM3_GPIO_PCR7_P7 *((volatile unsigned int*)(0x4266239CUL)) -#define bFM3_GPIO_PCR7_P8 *((volatile unsigned int*)(0x426623A0UL)) -#define bFM3_GPIO_PCR7_P9 *((volatile unsigned int*)(0x426623A4UL)) -#define bFM3_GPIO_PCR7_PA *((volatile unsigned int*)(0x426623A8UL)) -#define bFM3_GPIO_PCR7_PB *((volatile unsigned int*)(0x426623ACUL)) -#define bFM3_GPIO_PCR7_PC *((volatile unsigned int*)(0x426623B0UL)) -#define bFM3_GPIO_PCR7_PD *((volatile unsigned int*)(0x426623B4UL)) -#define bFM3_GPIO_PCR7_PE *((volatile unsigned int*)(0x426623B8UL)) -#define bFM3_GPIO_PCR7_PF *((volatile unsigned int*)(0x426623BCUL)) -#define bFM3_GPIO_PCR9_P0 *((volatile unsigned int*)(0x42662480UL)) -#define bFM3_GPIO_PCR9_P1 *((volatile unsigned int*)(0x42662484UL)) -#define bFM3_GPIO_PCR9_P2 *((volatile unsigned int*)(0x42662488UL)) -#define bFM3_GPIO_PCR9_P3 *((volatile unsigned int*)(0x4266248CUL)) -#define bFM3_GPIO_PCR9_P4 *((volatile unsigned int*)(0x42662490UL)) -#define bFM3_GPIO_PCR9_P5 *((volatile unsigned int*)(0x42662494UL)) -#define bFM3_GPIO_PCRA_P0 *((volatile unsigned int*)(0x42662500UL)) -#define bFM3_GPIO_PCRA_P1 *((volatile unsigned int*)(0x42662504UL)) -#define bFM3_GPIO_PCRA_P2 *((volatile unsigned int*)(0x42662508UL)) -#define bFM3_GPIO_PCRA_P3 *((volatile unsigned int*)(0x4266250CUL)) -#define bFM3_GPIO_PCRA_P4 *((volatile unsigned int*)(0x42662510UL)) -#define bFM3_GPIO_PCRA_P5 *((volatile unsigned int*)(0x42662514UL)) -#define bFM3_GPIO_PCRB_P0 *((volatile unsigned int*)(0x42662580UL)) -#define bFM3_GPIO_PCRB_P1 *((volatile unsigned int*)(0x42662584UL)) -#define bFM3_GPIO_PCRB_P2 *((volatile unsigned int*)(0x42662588UL)) -#define bFM3_GPIO_PCRB_P3 *((volatile unsigned int*)(0x4266258CUL)) -#define bFM3_GPIO_PCRB_P4 *((volatile unsigned int*)(0x42662590UL)) -#define bFM3_GPIO_PCRB_P5 *((volatile unsigned int*)(0x42662594UL)) -#define bFM3_GPIO_PCRB_P6 *((volatile unsigned int*)(0x42662598UL)) -#define bFM3_GPIO_PCRB_P7 *((volatile unsigned int*)(0x4266259CUL)) -#define bFM3_GPIO_PCRC_P0 *((volatile unsigned int*)(0x42662600UL)) -#define bFM3_GPIO_PCRC_P1 *((volatile unsigned int*)(0x42662604UL)) -#define bFM3_GPIO_PCRC_P2 *((volatile unsigned int*)(0x42662608UL)) -#define bFM3_GPIO_PCRC_P3 *((volatile unsigned int*)(0x4266260CUL)) -#define bFM3_GPIO_PCRC_P4 *((volatile unsigned int*)(0x42662610UL)) -#define bFM3_GPIO_PCRC_P5 *((volatile unsigned int*)(0x42662614UL)) -#define bFM3_GPIO_PCRC_P6 *((volatile unsigned int*)(0x42662618UL)) -#define bFM3_GPIO_PCRC_P7 *((volatile unsigned int*)(0x4266261CUL)) -#define bFM3_GPIO_PCRC_P8 *((volatile unsigned int*)(0x42662620UL)) -#define bFM3_GPIO_PCRC_P9 *((volatile unsigned int*)(0x42662624UL)) -#define bFM3_GPIO_PCRC_PA *((volatile unsigned int*)(0x42662628UL)) -#define bFM3_GPIO_PCRC_PB *((volatile unsigned int*)(0x4266262CUL)) -#define bFM3_GPIO_PCRC_PC *((volatile unsigned int*)(0x42662630UL)) -#define bFM3_GPIO_PCRC_PD *((volatile unsigned int*)(0x42662634UL)) -#define bFM3_GPIO_PCRC_PE *((volatile unsigned int*)(0x42662638UL)) -#define bFM3_GPIO_PCRC_PF *((volatile unsigned int*)(0x4266263CUL)) -#define bFM3_GPIO_PCRD_P0 *((volatile unsigned int*)(0x42662680UL)) -#define bFM3_GPIO_PCRD_P1 *((volatile unsigned int*)(0x42662684UL)) -#define bFM3_GPIO_PCRD_P2 *((volatile unsigned int*)(0x42662688UL)) -#define bFM3_GPIO_PCRD_P3 *((volatile unsigned int*)(0x4266268CUL)) -#define bFM3_GPIO_PCRE_P2 *((volatile unsigned int*)(0x42662708UL)) -#define bFM3_GPIO_PCRE_P3 *((volatile unsigned int*)(0x4266270CUL)) -#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) -#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) -#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) -#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) -#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) -#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) -#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) -#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) -#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) -#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) -#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) -#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) -#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) -#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) -#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) -#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) -#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) -#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) -#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) -#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) -#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) -#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) -#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) -#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) -#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) -#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) -#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) -#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) -#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) -#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) -#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) -#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) -#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) -#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) -#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) -#define bFM3_GPIO_DDR2_P9 *((volatile unsigned int*)(0x42664124UL)) -#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) -#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) -#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) -#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) -#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) -#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) -#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) -#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) -#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) -#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) -#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) -#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) -#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) -#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) -#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) -#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) -#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) -#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) -#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) -#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) -#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) -#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) -#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) -#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) -#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) -#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) -#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) -#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) -#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) -#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) -#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) -#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) -#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) -#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) -#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) -#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) -#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) -#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) -#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) -#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) -#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) -#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) -#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) -#define bFM3_GPIO_DDR5_PC *((volatile unsigned int*)(0x426642B0UL)) -#define bFM3_GPIO_DDR5_PD *((volatile unsigned int*)(0x426642B4UL)) -#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) -#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) -#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) -#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) -#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) -#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) -#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) -#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) -#define bFM3_GPIO_DDR7_P5 *((volatile unsigned int*)(0x42664394UL)) -#define bFM3_GPIO_DDR7_P6 *((volatile unsigned int*)(0x42664398UL)) -#define bFM3_GPIO_DDR7_P7 *((volatile unsigned int*)(0x4266439CUL)) -#define bFM3_GPIO_DDR7_P8 *((volatile unsigned int*)(0x426643A0UL)) -#define bFM3_GPIO_DDR7_P9 *((volatile unsigned int*)(0x426643A4UL)) -#define bFM3_GPIO_DDR7_PA *((volatile unsigned int*)(0x426643A8UL)) -#define bFM3_GPIO_DDR7_PB *((volatile unsigned int*)(0x426643ACUL)) -#define bFM3_GPIO_DDR7_PC *((volatile unsigned int*)(0x426643B0UL)) -#define bFM3_GPIO_DDR7_PD *((volatile unsigned int*)(0x426643B4UL)) -#define bFM3_GPIO_DDR7_PE *((volatile unsigned int*)(0x426643B8UL)) -#define bFM3_GPIO_DDR7_PF *((volatile unsigned int*)(0x426643BCUL)) -#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) -#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) -#define bFM3_GPIO_DDR8_P2 *((volatile unsigned int*)(0x42664408UL)) -#define bFM3_GPIO_DDR8_P3 *((volatile unsigned int*)(0x4266440CUL)) -#define bFM3_GPIO_DDR9_P0 *((volatile unsigned int*)(0x42664480UL)) -#define bFM3_GPIO_DDR9_P1 *((volatile unsigned int*)(0x42664484UL)) -#define bFM3_GPIO_DDR9_P2 *((volatile unsigned int*)(0x42664488UL)) -#define bFM3_GPIO_DDR9_P3 *((volatile unsigned int*)(0x4266448CUL)) -#define bFM3_GPIO_DDR9_P4 *((volatile unsigned int*)(0x42664490UL)) -#define bFM3_GPIO_DDR9_P5 *((volatile unsigned int*)(0x42664494UL)) -#define bFM3_GPIO_DDRA_P0 *((volatile unsigned int*)(0x42664500UL)) -#define bFM3_GPIO_DDRA_P1 *((volatile unsigned int*)(0x42664504UL)) -#define bFM3_GPIO_DDRA_P2 *((volatile unsigned int*)(0x42664508UL)) -#define bFM3_GPIO_DDRA_P3 *((volatile unsigned int*)(0x4266450CUL)) -#define bFM3_GPIO_DDRA_P4 *((volatile unsigned int*)(0x42664510UL)) -#define bFM3_GPIO_DDRA_P5 *((volatile unsigned int*)(0x42664514UL)) -#define bFM3_GPIO_DDRB_P0 *((volatile unsigned int*)(0x42664580UL)) -#define bFM3_GPIO_DDRB_P1 *((volatile unsigned int*)(0x42664584UL)) -#define bFM3_GPIO_DDRB_P2 *((volatile unsigned int*)(0x42664588UL)) -#define bFM3_GPIO_DDRB_P3 *((volatile unsigned int*)(0x4266458CUL)) -#define bFM3_GPIO_DDRB_P4 *((volatile unsigned int*)(0x42664590UL)) -#define bFM3_GPIO_DDRB_P5 *((volatile unsigned int*)(0x42664594UL)) -#define bFM3_GPIO_DDRB_P6 *((volatile unsigned int*)(0x42664598UL)) -#define bFM3_GPIO_DDRB_P7 *((volatile unsigned int*)(0x4266459CUL)) -#define bFM3_GPIO_DDRC_P0 *((volatile unsigned int*)(0x42664600UL)) -#define bFM3_GPIO_DDRC_P1 *((volatile unsigned int*)(0x42664604UL)) -#define bFM3_GPIO_DDRC_P2 *((volatile unsigned int*)(0x42664608UL)) -#define bFM3_GPIO_DDRC_P3 *((volatile unsigned int*)(0x4266460CUL)) -#define bFM3_GPIO_DDRC_P4 *((volatile unsigned int*)(0x42664610UL)) -#define bFM3_GPIO_DDRC_P5 *((volatile unsigned int*)(0x42664614UL)) -#define bFM3_GPIO_DDRC_P6 *((volatile unsigned int*)(0x42664618UL)) -#define bFM3_GPIO_DDRC_P7 *((volatile unsigned int*)(0x4266461CUL)) -#define bFM3_GPIO_DDRC_P8 *((volatile unsigned int*)(0x42664620UL)) -#define bFM3_GPIO_DDRC_P9 *((volatile unsigned int*)(0x42664624UL)) -#define bFM3_GPIO_DDRC_PA *((volatile unsigned int*)(0x42664628UL)) -#define bFM3_GPIO_DDRC_PB *((volatile unsigned int*)(0x4266462CUL)) -#define bFM3_GPIO_DDRC_PC *((volatile unsigned int*)(0x42664630UL)) -#define bFM3_GPIO_DDRC_PD *((volatile unsigned int*)(0x42664634UL)) -#define bFM3_GPIO_DDRC_PE *((volatile unsigned int*)(0x42664638UL)) -#define bFM3_GPIO_DDRC_PF *((volatile unsigned int*)(0x4266463CUL)) -#define bFM3_GPIO_DDRD_P0 *((volatile unsigned int*)(0x42664680UL)) -#define bFM3_GPIO_DDRD_P1 *((volatile unsigned int*)(0x42664684UL)) -#define bFM3_GPIO_DDRD_P2 *((volatile unsigned int*)(0x42664688UL)) -#define bFM3_GPIO_DDRD_P3 *((volatile unsigned int*)(0x4266468CUL)) -#define bFM3_GPIO_DDRE_P0 *((volatile unsigned int*)(0x42664700UL)) -#define bFM3_GPIO_DDRE_P2 *((volatile unsigned int*)(0x42664708UL)) -#define bFM3_GPIO_DDRE_P3 *((volatile unsigned int*)(0x4266470CUL)) -#define bFM3_GPIO_DDRF_P0 *((volatile unsigned int*)(0x42664780UL)) -#define bFM3_GPIO_DDRF_P1 *((volatile unsigned int*)(0x42664784UL)) -#define bFM3_GPIO_DDRF_P2 *((volatile unsigned int*)(0x42664788UL)) -#define bFM3_GPIO_DDRF_P3 *((volatile unsigned int*)(0x4266478CUL)) -#define bFM3_GPIO_DDRF_P4 *((volatile unsigned int*)(0x42664790UL)) -#define bFM3_GPIO_DDRF_P5 *((volatile unsigned int*)(0x42664794UL)) -#define bFM3_GPIO_DDRF_P6 *((volatile unsigned int*)(0x42664798UL)) -#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) -#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) -#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) -#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) -#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) -#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) -#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) -#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) -#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) -#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) -#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) -#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) -#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) -#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) -#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) -#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) -#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) -#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) -#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) -#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) -#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) -#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) -#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) -#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) -#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) -#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) -#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) -#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) -#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) -#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) -#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) -#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) -#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) -#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) -#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) -#define bFM3_GPIO_PDIR2_P9 *((volatile unsigned int*)(0x42666124UL)) -#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) -#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) -#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) -#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) -#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) -#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) -#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) -#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) -#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) -#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) -#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) -#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) -#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) -#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) -#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) -#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) -#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) -#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) -#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) -#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) -#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) -#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) -#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) -#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) -#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) -#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) -#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) -#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) -#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) -#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) -#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) -#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) -#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) -#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) -#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) -#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) -#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) -#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) -#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) -#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) -#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) -#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) -#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) -#define bFM3_GPIO_PDIR5_PC *((volatile unsigned int*)(0x426662B0UL)) -#define bFM3_GPIO_PDIR5_PD *((volatile unsigned int*)(0x426662B4UL)) -#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) -#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) -#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) -#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) -#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) -#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) -#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) -#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) -#define bFM3_GPIO_PDIR7_P5 *((volatile unsigned int*)(0x42666394UL)) -#define bFM3_GPIO_PDIR7_P6 *((volatile unsigned int*)(0x42666398UL)) -#define bFM3_GPIO_PDIR7_P7 *((volatile unsigned int*)(0x4266639CUL)) -#define bFM3_GPIO_PDIR7_P8 *((volatile unsigned int*)(0x426663A0UL)) -#define bFM3_GPIO_PDIR7_P9 *((volatile unsigned int*)(0x426663A4UL)) -#define bFM3_GPIO_PDIR7_PA *((volatile unsigned int*)(0x426663A8UL)) -#define bFM3_GPIO_PDIR7_PB *((volatile unsigned int*)(0x426663ACUL)) -#define bFM3_GPIO_PDIR7_PC *((volatile unsigned int*)(0x426663B0UL)) -#define bFM3_GPIO_PDIR7_PD *((volatile unsigned int*)(0x426663B4UL)) -#define bFM3_GPIO_PDIR7_PE *((volatile unsigned int*)(0x426663B8UL)) -#define bFM3_GPIO_PDIR7_PF *((volatile unsigned int*)(0x426663BCUL)) -#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) -#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) -#define bFM3_GPIO_PDIR8_P2 *((volatile unsigned int*)(0x42666408UL)) -#define bFM3_GPIO_PDIR8_P3 *((volatile unsigned int*)(0x4266640CUL)) -#define bFM3_GPIO_PDIR9_P0 *((volatile unsigned int*)(0x42666480UL)) -#define bFM3_GPIO_PDIR9_P1 *((volatile unsigned int*)(0x42666484UL)) -#define bFM3_GPIO_PDIR9_P2 *((volatile unsigned int*)(0x42666488UL)) -#define bFM3_GPIO_PDIR9_P3 *((volatile unsigned int*)(0x4266648CUL)) -#define bFM3_GPIO_PDIR9_P4 *((volatile unsigned int*)(0x42666490UL)) -#define bFM3_GPIO_PDIR9_P5 *((volatile unsigned int*)(0x42666494UL)) -#define bFM3_GPIO_PDIRA_P0 *((volatile unsigned int*)(0x42666500UL)) -#define bFM3_GPIO_PDIRA_P1 *((volatile unsigned int*)(0x42666504UL)) -#define bFM3_GPIO_PDIRA_P2 *((volatile unsigned int*)(0x42666508UL)) -#define bFM3_GPIO_PDIRA_P3 *((volatile unsigned int*)(0x4266650CUL)) -#define bFM3_GPIO_PDIRA_P4 *((volatile unsigned int*)(0x42666510UL)) -#define bFM3_GPIO_PDIRA_P5 *((volatile unsigned int*)(0x42666514UL)) -#define bFM3_GPIO_PDIRB_P0 *((volatile unsigned int*)(0x42666580UL)) -#define bFM3_GPIO_PDIRB_P1 *((volatile unsigned int*)(0x42666584UL)) -#define bFM3_GPIO_PDIRB_P2 *((volatile unsigned int*)(0x42666588UL)) -#define bFM3_GPIO_PDIRB_P3 *((volatile unsigned int*)(0x4266658CUL)) -#define bFM3_GPIO_PDIRB_P4 *((volatile unsigned int*)(0x42666590UL)) -#define bFM3_GPIO_PDIRB_P5 *((volatile unsigned int*)(0x42666594UL)) -#define bFM3_GPIO_PDIRB_P6 *((volatile unsigned int*)(0x42666598UL)) -#define bFM3_GPIO_PDIRB_P7 *((volatile unsigned int*)(0x4266659CUL)) -#define bFM3_GPIO_PDIRC_P0 *((volatile unsigned int*)(0x42666600UL)) -#define bFM3_GPIO_PDIRC_P1 *((volatile unsigned int*)(0x42666604UL)) -#define bFM3_GPIO_PDIRC_P2 *((volatile unsigned int*)(0x42666608UL)) -#define bFM3_GPIO_PDIRC_P3 *((volatile unsigned int*)(0x4266660CUL)) -#define bFM3_GPIO_PDIRC_P4 *((volatile unsigned int*)(0x42666610UL)) -#define bFM3_GPIO_PDIRC_P5 *((volatile unsigned int*)(0x42666614UL)) -#define bFM3_GPIO_PDIRC_P6 *((volatile unsigned int*)(0x42666618UL)) -#define bFM3_GPIO_PDIRC_P7 *((volatile unsigned int*)(0x4266661CUL)) -#define bFM3_GPIO_PDIRC_P8 *((volatile unsigned int*)(0x42666620UL)) -#define bFM3_GPIO_PDIRC_P9 *((volatile unsigned int*)(0x42666624UL)) -#define bFM3_GPIO_PDIRC_PA *((volatile unsigned int*)(0x42666628UL)) -#define bFM3_GPIO_PDIRC_PB *((volatile unsigned int*)(0x4266662CUL)) -#define bFM3_GPIO_PDIRC_PC *((volatile unsigned int*)(0x42666630UL)) -#define bFM3_GPIO_PDIRC_PD *((volatile unsigned int*)(0x42666634UL)) -#define bFM3_GPIO_PDIRC_PE *((volatile unsigned int*)(0x42666638UL)) -#define bFM3_GPIO_PDIRC_PF *((volatile unsigned int*)(0x4266663CUL)) -#define bFM3_GPIO_PDIRD_P0 *((volatile unsigned int*)(0x42666680UL)) -#define bFM3_GPIO_PDIRD_P1 *((volatile unsigned int*)(0x42666684UL)) -#define bFM3_GPIO_PDIRD_P2 *((volatile unsigned int*)(0x42666688UL)) -#define bFM3_GPIO_PDIRD_P3 *((volatile unsigned int*)(0x4266668CUL)) -#define bFM3_GPIO_PDIRE_P0 *((volatile unsigned int*)(0x42666700UL)) -#define bFM3_GPIO_PDIRE_P2 *((volatile unsigned int*)(0x42666708UL)) -#define bFM3_GPIO_PDIRE_P3 *((volatile unsigned int*)(0x4266670CUL)) -#define bFM3_GPIO_PDIRF_P0 *((volatile unsigned int*)(0x42666780UL)) -#define bFM3_GPIO_PDIRF_P1 *((volatile unsigned int*)(0x42666784UL)) -#define bFM3_GPIO_PDIRF_P2 *((volatile unsigned int*)(0x42666788UL)) -#define bFM3_GPIO_PDIRF_P3 *((volatile unsigned int*)(0x4266678CUL)) -#define bFM3_GPIO_PDIRF_P4 *((volatile unsigned int*)(0x42666790UL)) -#define bFM3_GPIO_PDIRF_P5 *((volatile unsigned int*)(0x42666794UL)) -#define bFM3_GPIO_PDIRF_P6 *((volatile unsigned int*)(0x42666798UL)) -#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) -#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) -#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) -#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) -#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) -#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) -#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) -#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) -#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) -#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) -#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) -#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) -#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) -#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) -#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) -#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) -#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) -#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) -#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) -#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) -#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) -#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) -#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) -#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) -#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) -#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) -#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) -#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) -#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) -#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) -#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) -#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) -#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) -#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) -#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) -#define bFM3_GPIO_PDOR2_P9 *((volatile unsigned int*)(0x42668124UL)) -#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) -#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) -#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) -#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) -#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) -#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) -#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) -#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) -#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) -#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) -#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) -#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) -#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) -#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) -#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) -#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) -#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) -#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) -#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) -#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) -#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) -#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) -#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) -#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) -#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) -#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) -#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) -#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) -#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) -#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) -#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) -#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) -#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) -#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) -#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) -#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) -#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) -#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) -#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) -#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) -#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) -#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) -#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) -#define bFM3_GPIO_PDOR5_PC *((volatile unsigned int*)(0x426682B0UL)) -#define bFM3_GPIO_PDOR5_PD *((volatile unsigned int*)(0x426682B4UL)) -#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) -#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) -#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) -#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) -#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) -#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) -#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) -#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) -#define bFM3_GPIO_PDOR7_P5 *((volatile unsigned int*)(0x42668394UL)) -#define bFM3_GPIO_PDOR7_P6 *((volatile unsigned int*)(0x42668398UL)) -#define bFM3_GPIO_PDOR7_P7 *((volatile unsigned int*)(0x4266839CUL)) -#define bFM3_GPIO_PDOR7_P8 *((volatile unsigned int*)(0x426683A0UL)) -#define bFM3_GPIO_PDOR7_P9 *((volatile unsigned int*)(0x426683A4UL)) -#define bFM3_GPIO_PDOR7_PA *((volatile unsigned int*)(0x426683A8UL)) -#define bFM3_GPIO_PDOR7_PB *((volatile unsigned int*)(0x426683ACUL)) -#define bFM3_GPIO_PDOR7_PC *((volatile unsigned int*)(0x426683B0UL)) -#define bFM3_GPIO_PDOR7_PD *((volatile unsigned int*)(0x426683B4UL)) -#define bFM3_GPIO_PDOR7_PE *((volatile unsigned int*)(0x426683B8UL)) -#define bFM3_GPIO_PDOR7_PF *((volatile unsigned int*)(0x426683BCUL)) -#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) -#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) -#define bFM3_GPIO_PDOR8_P2 *((volatile unsigned int*)(0x42668408UL)) -#define bFM3_GPIO_PDOR8_P3 *((volatile unsigned int*)(0x4266840CUL)) -#define bFM3_GPIO_PDOR9_P0 *((volatile unsigned int*)(0x42668480UL)) -#define bFM3_GPIO_PDOR9_P1 *((volatile unsigned int*)(0x42668484UL)) -#define bFM3_GPIO_PDOR9_P2 *((volatile unsigned int*)(0x42668488UL)) -#define bFM3_GPIO_PDOR9_P3 *((volatile unsigned int*)(0x4266848CUL)) -#define bFM3_GPIO_PDOR9_P4 *((volatile unsigned int*)(0x42668490UL)) -#define bFM3_GPIO_PDOR9_P5 *((volatile unsigned int*)(0x42668494UL)) -#define bFM3_GPIO_PDORA_P0 *((volatile unsigned int*)(0x42668500UL)) -#define bFM3_GPIO_PDORA_P1 *((volatile unsigned int*)(0x42668504UL)) -#define bFM3_GPIO_PDORA_P2 *((volatile unsigned int*)(0x42668508UL)) -#define bFM3_GPIO_PDORA_P3 *((volatile unsigned int*)(0x4266850CUL)) -#define bFM3_GPIO_PDORA_P4 *((volatile unsigned int*)(0x42668510UL)) -#define bFM3_GPIO_PDORA_P5 *((volatile unsigned int*)(0x42668514UL)) -#define bFM3_GPIO_PDORB_P0 *((volatile unsigned int*)(0x42668580UL)) -#define bFM3_GPIO_PDORB_P1 *((volatile unsigned int*)(0x42668584UL)) -#define bFM3_GPIO_PDORB_P2 *((volatile unsigned int*)(0x42668588UL)) -#define bFM3_GPIO_PDORB_P3 *((volatile unsigned int*)(0x4266858CUL)) -#define bFM3_GPIO_PDORB_P4 *((volatile unsigned int*)(0x42668590UL)) -#define bFM3_GPIO_PDORB_P5 *((volatile unsigned int*)(0x42668594UL)) -#define bFM3_GPIO_PDORB_P6 *((volatile unsigned int*)(0x42668598UL)) -#define bFM3_GPIO_PDORB_P7 *((volatile unsigned int*)(0x4266859CUL)) -#define bFM3_GPIO_PDORC_P0 *((volatile unsigned int*)(0x42668600UL)) -#define bFM3_GPIO_PDORC_P1 *((volatile unsigned int*)(0x42668604UL)) -#define bFM3_GPIO_PDORC_P2 *((volatile unsigned int*)(0x42668608UL)) -#define bFM3_GPIO_PDORC_P3 *((volatile unsigned int*)(0x4266860CUL)) -#define bFM3_GPIO_PDORC_P4 *((volatile unsigned int*)(0x42668610UL)) -#define bFM3_GPIO_PDORC_P5 *((volatile unsigned int*)(0x42668614UL)) -#define bFM3_GPIO_PDORC_P6 *((volatile unsigned int*)(0x42668618UL)) -#define bFM3_GPIO_PDORC_P7 *((volatile unsigned int*)(0x4266861CUL)) -#define bFM3_GPIO_PDORC_P8 *((volatile unsigned int*)(0x42668620UL)) -#define bFM3_GPIO_PDORC_P9 *((volatile unsigned int*)(0x42668624UL)) -#define bFM3_GPIO_PDORC_PA *((volatile unsigned int*)(0x42668628UL)) -#define bFM3_GPIO_PDORC_PB *((volatile unsigned int*)(0x4266862CUL)) -#define bFM3_GPIO_PDORC_PC *((volatile unsigned int*)(0x42668630UL)) -#define bFM3_GPIO_PDORC_PD *((volatile unsigned int*)(0x42668634UL)) -#define bFM3_GPIO_PDORC_PE *((volatile unsigned int*)(0x42668638UL)) -#define bFM3_GPIO_PDORC_PF *((volatile unsigned int*)(0x4266863CUL)) -#define bFM3_GPIO_PDORD_P0 *((volatile unsigned int*)(0x42668680UL)) -#define bFM3_GPIO_PDORD_P1 *((volatile unsigned int*)(0x42668684UL)) -#define bFM3_GPIO_PDORD_P2 *((volatile unsigned int*)(0x42668688UL)) -#define bFM3_GPIO_PDORD_P3 *((volatile unsigned int*)(0x4266868CUL)) -#define bFM3_GPIO_PDORE_P0 *((volatile unsigned int*)(0x42668700UL)) -#define bFM3_GPIO_PDORE_P2 *((volatile unsigned int*)(0x42668708UL)) -#define bFM3_GPIO_PDORE_P3 *((volatile unsigned int*)(0x4266870CUL)) -#define bFM3_GPIO_PDORF_P0 *((volatile unsigned int*)(0x42668780UL)) -#define bFM3_GPIO_PDORF_P1 *((volatile unsigned int*)(0x42668784UL)) -#define bFM3_GPIO_PDORF_P2 *((volatile unsigned int*)(0x42668788UL)) -#define bFM3_GPIO_PDORF_P3 *((volatile unsigned int*)(0x4266878CUL)) -#define bFM3_GPIO_PDORF_P4 *((volatile unsigned int*)(0x42668790UL)) -#define bFM3_GPIO_PDORF_P5 *((volatile unsigned int*)(0x42668794UL)) -#define bFM3_GPIO_PDORF_P6 *((volatile unsigned int*)(0x42668798UL)) -#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) -#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) -#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) -#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) -#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) -#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) -#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) -#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) -#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) -#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) -#define bFM3_GPIO_ADE_AN10 *((volatile unsigned int*)(0x4266A028UL)) -#define bFM3_GPIO_ADE_AN11 *((volatile unsigned int*)(0x4266A02CUL)) -#define bFM3_GPIO_ADE_AN12 *((volatile unsigned int*)(0x4266A030UL)) -#define bFM3_GPIO_ADE_AN13 *((volatile unsigned int*)(0x4266A034UL)) -#define bFM3_GPIO_ADE_AN14 *((volatile unsigned int*)(0x4266A038UL)) -#define bFM3_GPIO_ADE_AN15 *((volatile unsigned int*)(0x4266A03CUL)) -#define bFM3_GPIO_ADE_AN16 *((volatile unsigned int*)(0x4266A040UL)) -#define bFM3_GPIO_ADE_AN17 *((volatile unsigned int*)(0x4266A044UL)) -#define bFM3_GPIO_ADE_AN18 *((volatile unsigned int*)(0x4266A048UL)) -#define bFM3_GPIO_ADE_AN19 *((volatile unsigned int*)(0x4266A04CUL)) -#define bFM3_GPIO_ADE_AN20 *((volatile unsigned int*)(0x4266A050UL)) -#define bFM3_GPIO_ADE_AN21 *((volatile unsigned int*)(0x4266A054UL)) -#define bFM3_GPIO_ADE_AN22 *((volatile unsigned int*)(0x4266A058UL)) -#define bFM3_GPIO_ADE_AN23 *((volatile unsigned int*)(0x4266A05CUL)) -#define bFM3_GPIO_ADE_AN24 *((volatile unsigned int*)(0x4266A060UL)) -#define bFM3_GPIO_ADE_AN25 *((volatile unsigned int*)(0x4266A064UL)) -#define bFM3_GPIO_ADE_AN26 *((volatile unsigned int*)(0x4266A068UL)) -#define bFM3_GPIO_ADE_AN27 *((volatile unsigned int*)(0x4266A06CUL)) -#define bFM3_GPIO_ADE_AN28 *((volatile unsigned int*)(0x4266A070UL)) -#define bFM3_GPIO_ADE_AN29 *((volatile unsigned int*)(0x4266A074UL)) -#define bFM3_GPIO_ADE_AN30 *((volatile unsigned int*)(0x4266A078UL)) -#define bFM3_GPIO_ADE_AN31 *((volatile unsigned int*)(0x4266A07CUL)) -#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) -#define bFM3_GPIO_SPSR_MAINXC *((volatile unsigned int*)(0x4266B008UL)) -#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) -#define bFM3_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x4266B014UL)) -#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) -#define bFM3_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x4266C004UL)) -#define bFM3_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x4266C008UL)) -#define bFM3_GPIO_EPFR00_SUBOUTE0 *((volatile unsigned int*)(0x4266C018UL)) -#define bFM3_GPIO_EPFR00_SUBOUTE1 *((volatile unsigned int*)(0x4266C01CUL)) -#define bFM3_GPIO_EPFR00_USBP0E *((volatile unsigned int*)(0x4266C024UL)) -#define bFM3_GPIO_EPFR00_USBP1E *((volatile unsigned int*)(0x4266C034UL)) -#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) -#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) -#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) -#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) -#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) -#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) -#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) -#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) -#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) -#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) -#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) -#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) -#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) -#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) -#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) -#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) -#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) -#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) -#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) -#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) -#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) -#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) -#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) -#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) -#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) -#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) -#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) -#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) -#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) -#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) -#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) -#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) -#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) -#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) -#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) -#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) -#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) -#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) -#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) -#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) -#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) -#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) -#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) -#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) -#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) -#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) -#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) -#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) -#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) -#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) -#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) -#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) -#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) -#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) -#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) -#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) -#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) -#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) -#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) -#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) -#define bFM3_GPIO_EPFR03_RTO20E0 *((volatile unsigned int*)(0x4266C180UL)) -#define bFM3_GPIO_EPFR03_RTO20E1 *((volatile unsigned int*)(0x4266C184UL)) -#define bFM3_GPIO_EPFR03_RTO21E0 *((volatile unsigned int*)(0x4266C188UL)) -#define bFM3_GPIO_EPFR03_RTO21E1 *((volatile unsigned int*)(0x4266C18CUL)) -#define bFM3_GPIO_EPFR03_RTO22E0 *((volatile unsigned int*)(0x4266C190UL)) -#define bFM3_GPIO_EPFR03_RTO22E1 *((volatile unsigned int*)(0x4266C194UL)) -#define bFM3_GPIO_EPFR03_RTO23E0 *((volatile unsigned int*)(0x4266C198UL)) -#define bFM3_GPIO_EPFR03_RTO23E1 *((volatile unsigned int*)(0x4266C19CUL)) -#define bFM3_GPIO_EPFR03_RTO24E0 *((volatile unsigned int*)(0x4266C1A0UL)) -#define bFM3_GPIO_EPFR03_RTO24E1 *((volatile unsigned int*)(0x4266C1A4UL)) -#define bFM3_GPIO_EPFR03_RTO25E0 *((volatile unsigned int*)(0x4266C1A8UL)) -#define bFM3_GPIO_EPFR03_RTO25E1 *((volatile unsigned int*)(0x4266C1ACUL)) -#define bFM3_GPIO_EPFR03_DTTI2C *((volatile unsigned int*)(0x4266C1B0UL)) -#define bFM3_GPIO_EPFR03_DTTI2S0 *((volatile unsigned int*)(0x4266C1C0UL)) -#define bFM3_GPIO_EPFR03_DTTI2S1 *((volatile unsigned int*)(0x4266C1C4UL)) -#define bFM3_GPIO_EPFR03_FRCK2S0 *((volatile unsigned int*)(0x4266C1C8UL)) -#define bFM3_GPIO_EPFR03_FRCK2S1 *((volatile unsigned int*)(0x4266C1CCUL)) -#define bFM3_GPIO_EPFR03_IC20S0 *((volatile unsigned int*)(0x4266C1D0UL)) -#define bFM3_GPIO_EPFR03_IC20S1 *((volatile unsigned int*)(0x4266C1D4UL)) -#define bFM3_GPIO_EPFR03_IC20S2 *((volatile unsigned int*)(0x4266C1D8UL)) -#define bFM3_GPIO_EPFR03_IC21S0 *((volatile unsigned int*)(0x4266C1DCUL)) -#define bFM3_GPIO_EPFR03_IC21S1 *((volatile unsigned int*)(0x4266C1E0UL)) -#define bFM3_GPIO_EPFR03_IC21S2 *((volatile unsigned int*)(0x4266C1E4UL)) -#define bFM3_GPIO_EPFR03_IC22S0 *((volatile unsigned int*)(0x4266C1E8UL)) -#define bFM3_GPIO_EPFR03_IC22S1 *((volatile unsigned int*)(0x4266C1ECUL)) -#define bFM3_GPIO_EPFR03_IC22S2 *((volatile unsigned int*)(0x4266C1F0UL)) -#define bFM3_GPIO_EPFR03_IC23S0 *((volatile unsigned int*)(0x4266C1F4UL)) -#define bFM3_GPIO_EPFR03_IC23S1 *((volatile unsigned int*)(0x4266C1F8UL)) -#define bFM3_GPIO_EPFR03_IC23S2 *((volatile unsigned int*)(0x4266C1FCUL)) -#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) -#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) -#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) -#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) -#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) -#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) -#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) -#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) -#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) -#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) -#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) -#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) -#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) -#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) -#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) -#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) -#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) -#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) -#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) -#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) -#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) -#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) -#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) -#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) -#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) -#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) -#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) -#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) -#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) -#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) -#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) -#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) -#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) -#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) -#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) -#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) -#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) -#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) -#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) -#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) -#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) -#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) -#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) -#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) -#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) -#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) -#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) -#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) -#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) -#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) -#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) -#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) -#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) -#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) -#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) -#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) -#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) -#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) -#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) -#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) -#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) -#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) -#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) -#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) -#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) -#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) -#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) -#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) -#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) -#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) -#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) -#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) -#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) -#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) -#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) -#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) -#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) -#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) -#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) -#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) -#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) -#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) -#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) -#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) -#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) -#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) -#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) -#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) -#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) -#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) -#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) -#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) -#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) -#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) -#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) -#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) -#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) -#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) -#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) -#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) -#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) -#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) -#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) -#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) -#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) -#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) -#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) -#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) -#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) -#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) -#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) -#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) -#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) -#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) -#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) -#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) -#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) -#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) -#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) -#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) -#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) -#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) -#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) -#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) -#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) -#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) -#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) -#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) -#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) -#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) -#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) -#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) -#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) -#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) -#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) -#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) -#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) -#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) -#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) -#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) -#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) -#define bFM3_GPIO_EPFR10_UECLKE *((volatile unsigned int*)(0x4266C508UL)) -#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) -#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) -#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) -#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) -#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) -#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) -#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) -#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) -#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) -#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) -#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) -#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) -#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) -#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) -#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) -#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) -#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) -#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) -#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) -#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) -#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) -#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) -#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) -#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) -#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) -#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) -#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) -#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) -#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) -#define bFM3_GPIO_EPFR11_UEALEE *((volatile unsigned int*)(0x4266C580UL)) -#define bFM3_GPIO_EPFR11_UECS0E *((volatile unsigned int*)(0x4266C584UL)) -#define bFM3_GPIO_EPFR11_UEA01E *((volatile unsigned int*)(0x4266C588UL)) -#define bFM3_GPIO_EPFR11_UEA02E *((volatile unsigned int*)(0x4266C58CUL)) -#define bFM3_GPIO_EPFR11_UEA03E *((volatile unsigned int*)(0x4266C590UL)) -#define bFM3_GPIO_EPFR11_UEA04E *((volatile unsigned int*)(0x4266C594UL)) -#define bFM3_GPIO_EPFR11_UEA05E *((volatile unsigned int*)(0x4266C598UL)) -#define bFM3_GPIO_EPFR11_UEA06E *((volatile unsigned int*)(0x4266C59CUL)) -#define bFM3_GPIO_EPFR11_UEA07E *((volatile unsigned int*)(0x4266C5A0UL)) -#define bFM3_GPIO_EPFR11_UED00B *((volatile unsigned int*)(0x4266C5A4UL)) -#define bFM3_GPIO_EPFR11_UED01B *((volatile unsigned int*)(0x4266C5A8UL)) -#define bFM3_GPIO_EPFR11_UED02B *((volatile unsigned int*)(0x4266C5ACUL)) -#define bFM3_GPIO_EPFR11_UED03B *((volatile unsigned int*)(0x4266C5B0UL)) -#define bFM3_GPIO_EPFR11_UED04B *((volatile unsigned int*)(0x4266C5B4UL)) -#define bFM3_GPIO_EPFR11_UED05B *((volatile unsigned int*)(0x4266C5B8UL)) -#define bFM3_GPIO_EPFR11_UED06B *((volatile unsigned int*)(0x4266C5BCUL)) -#define bFM3_GPIO_EPFR11_UED07B *((volatile unsigned int*)(0x4266C5C0UL)) -#define bFM3_GPIO_EPFR11_UED08B *((volatile unsigned int*)(0x4266C5C4UL)) -#define bFM3_GPIO_EPFR11_UED09B *((volatile unsigned int*)(0x4266C5C8UL)) -#define bFM3_GPIO_EPFR11_UED10B *((volatile unsigned int*)(0x4266C5CCUL)) -#define bFM3_GPIO_EPFR11_UED11B *((volatile unsigned int*)(0x4266C5D0UL)) -#define bFM3_GPIO_EPFR11_UED12B *((volatile unsigned int*)(0x4266C5D4UL)) -#define bFM3_GPIO_EPFR11_UED13B *((volatile unsigned int*)(0x4266C5D8UL)) -#define bFM3_GPIO_EPFR11_UED14B *((volatile unsigned int*)(0x4266C5DCUL)) -#define bFM3_GPIO_EPFR11_UED15B *((volatile unsigned int*)(0x4266C5E0UL)) -#define bFM3_GPIO_EPFR11_UERLC *((volatile unsigned int*)(0x4266C5E4UL)) -#define bFM3_GPIO_EPFR12_TIOA8E0 *((volatile unsigned int*)(0x4266C608UL)) -#define bFM3_GPIO_EPFR12_TIOA8E1 *((volatile unsigned int*)(0x4266C60CUL)) -#define bFM3_GPIO_EPFR12_TIOB8S0 *((volatile unsigned int*)(0x4266C610UL)) -#define bFM3_GPIO_EPFR12_TIOB8S1 *((volatile unsigned int*)(0x4266C614UL)) -#define bFM3_GPIO_EPFR12_TIOA9S0 *((volatile unsigned int*)(0x4266C620UL)) -#define bFM3_GPIO_EPFR12_TIOA9S1 *((volatile unsigned int*)(0x4266C624UL)) -#define bFM3_GPIO_EPFR12_TIOA9E0 *((volatile unsigned int*)(0x4266C628UL)) -#define bFM3_GPIO_EPFR12_TIOA9E1 *((volatile unsigned int*)(0x4266C62CUL)) -#define bFM3_GPIO_EPFR12_TIOB9S0 *((volatile unsigned int*)(0x4266C630UL)) -#define bFM3_GPIO_EPFR12_TIOB9S1 *((volatile unsigned int*)(0x4266C634UL)) -#define bFM3_GPIO_EPFR12_TIOA10E0 *((volatile unsigned int*)(0x4266C648UL)) -#define bFM3_GPIO_EPFR12_TIOA10E1 *((volatile unsigned int*)(0x4266C64CUL)) -#define bFM3_GPIO_EPFR12_TIOB10S0 *((volatile unsigned int*)(0x4266C650UL)) -#define bFM3_GPIO_EPFR12_TIOB10S1 *((volatile unsigned int*)(0x4266C654UL)) -#define bFM3_GPIO_EPFR12_TIOA11S0 *((volatile unsigned int*)(0x4266C660UL)) -#define bFM3_GPIO_EPFR12_TIOA11S1 *((volatile unsigned int*)(0x4266C664UL)) -#define bFM3_GPIO_EPFR12_TIOA11E0 *((volatile unsigned int*)(0x4266C668UL)) -#define bFM3_GPIO_EPFR12_TIOA11E1 *((volatile unsigned int*)(0x4266C66CUL)) -#define bFM3_GPIO_EPFR12_TIOB11S0 *((volatile unsigned int*)(0x4266C670UL)) -#define bFM3_GPIO_EPFR12_TIOB11S1 *((volatile unsigned int*)(0x4266C674UL)) -#define bFM3_GPIO_EPFR13_TIOA12E0 *((volatile unsigned int*)(0x4266C688UL)) -#define bFM3_GPIO_EPFR13_TIOA12E1 *((volatile unsigned int*)(0x4266C68CUL)) -#define bFM3_GPIO_EPFR13_TIOB12S0 *((volatile unsigned int*)(0x4266C690UL)) -#define bFM3_GPIO_EPFR13_TIOB12S1 *((volatile unsigned int*)(0x4266C694UL)) -#define bFM3_GPIO_EPFR13_TIOA13S0 *((volatile unsigned int*)(0x4266C6A0UL)) -#define bFM3_GPIO_EPFR13_TIOA13S1 *((volatile unsigned int*)(0x4266C6A4UL)) -#define bFM3_GPIO_EPFR13_TIOA13E0 *((volatile unsigned int*)(0x4266C6A8UL)) -#define bFM3_GPIO_EPFR13_TIOA13E1 *((volatile unsigned int*)(0x4266C6ACUL)) -#define bFM3_GPIO_EPFR13_TIOB13S0 *((volatile unsigned int*)(0x4266C6B0UL)) -#define bFM3_GPIO_EPFR13_TIOB13S1 *((volatile unsigned int*)(0x4266C6B4UL)) -#define bFM3_GPIO_EPFR13_TIOA14E0 *((volatile unsigned int*)(0x4266C6C8UL)) -#define bFM3_GPIO_EPFR13_TIOA14E1 *((volatile unsigned int*)(0x4266C6CCUL)) -#define bFM3_GPIO_EPFR13_TIOB14S0 *((volatile unsigned int*)(0x4266C6D0UL)) -#define bFM3_GPIO_EPFR13_TIOB14S1 *((volatile unsigned int*)(0x4266C6D4UL)) -#define bFM3_GPIO_EPFR13_TIOA15S0 *((volatile unsigned int*)(0x4266C6E0UL)) -#define bFM3_GPIO_EPFR13_TIOA15S1 *((volatile unsigned int*)(0x4266C6E4UL)) -#define bFM3_GPIO_EPFR13_TIOA15E0 *((volatile unsigned int*)(0x4266C6E8UL)) -#define bFM3_GPIO_EPFR13_TIOA15E1 *((volatile unsigned int*)(0x4266C6ECUL)) -#define bFM3_GPIO_EPFR13_TIOB15S0 *((volatile unsigned int*)(0x4266C6F0UL)) -#define bFM3_GPIO_EPFR13_TIOB15S1 *((volatile unsigned int*)(0x4266C6F4UL)) -#define bFM3_GPIO_EPFR14_QAIN2S0 *((volatile unsigned int*)(0x4266C700UL)) -#define bFM3_GPIO_EPFR14_QAIN2S1 *((volatile unsigned int*)(0x4266C704UL)) -#define bFM3_GPIO_EPFR14_QBIN2S0 *((volatile unsigned int*)(0x4266C708UL)) -#define bFM3_GPIO_EPFR14_QBIN2S1 *((volatile unsigned int*)(0x4266C70CUL)) -#define bFM3_GPIO_EPFR14_QZIN2S0 *((volatile unsigned int*)(0x4266C710UL)) -#define bFM3_GPIO_EPFR14_QZIN2S1 *((volatile unsigned int*)(0x4266C714UL)) -#define bFM3_GPIO_EPFR14_E_TD0E *((volatile unsigned int*)(0x4266C748UL)) -#define bFM3_GPIO_EPFR14_E_TD1E *((volatile unsigned int*)(0x4266C74CUL)) -#define bFM3_GPIO_EPFR14_E_TE0E *((volatile unsigned int*)(0x4266C750UL)) -#define bFM3_GPIO_EPFR14_E_TE1E *((volatile unsigned int*)(0x4266C754UL)) -#define bFM3_GPIO_EPFR14_E_MC0E *((volatile unsigned int*)(0x4266C758UL)) -#define bFM3_GPIO_EPFR14_E_MC1B *((volatile unsigned int*)(0x4266C75CUL)) -#define bFM3_GPIO_EPFR14_E_MD0B *((volatile unsigned int*)(0x4266C760UL)) -#define bFM3_GPIO_EPFR14_E_MD1B *((volatile unsigned int*)(0x4266C764UL)) -#define bFM3_GPIO_EPFR14_E_CKE *((volatile unsigned int*)(0x4266C768UL)) -#define bFM3_GPIO_EPFR14_E_PSE *((volatile unsigned int*)(0x4266C76CUL)) -#define bFM3_GPIO_EPFR14_E_SPLC0 *((volatile unsigned int*)(0x4266C770UL)) -#define bFM3_GPIO_EPFR14_E_SPLC1 *((volatile unsigned int*)(0x4266C774UL)) -#define bFM3_GPIO_EPFR15_EINT16S0 *((volatile unsigned int*)(0x4266C780UL)) -#define bFM3_GPIO_EPFR15_EINT16S1 *((volatile unsigned int*)(0x4266C784UL)) -#define bFM3_GPIO_EPFR15_EINT17S0 *((volatile unsigned int*)(0x4266C788UL)) -#define bFM3_GPIO_EPFR15_EINT17S1 *((volatile unsigned int*)(0x4266C78CUL)) -#define bFM3_GPIO_EPFR15_EINT18S0 *((volatile unsigned int*)(0x4266C790UL)) -#define bFM3_GPIO_EPFR15_EINT18S1 *((volatile unsigned int*)(0x4266C794UL)) -#define bFM3_GPIO_EPFR15_EINT19S0 *((volatile unsigned int*)(0x4266C798UL)) -#define bFM3_GPIO_EPFR15_EINT19S1 *((volatile unsigned int*)(0x4266C79CUL)) -#define bFM3_GPIO_EPFR15_EINT20S0 *((volatile unsigned int*)(0x4266C7A0UL)) -#define bFM3_GPIO_EPFR15_EINT20S1 *((volatile unsigned int*)(0x4266C7A4UL)) -#define bFM3_GPIO_EPFR15_EINT21S0 *((volatile unsigned int*)(0x4266C7A8UL)) -#define bFM3_GPIO_EPFR15_EINT21S1 *((volatile unsigned int*)(0x4266C7ACUL)) -#define bFM3_GPIO_EPFR15_EINT22S0 *((volatile unsigned int*)(0x4266C7B0UL)) -#define bFM3_GPIO_EPFR15_EINT22S1 *((volatile unsigned int*)(0x4266C7B4UL)) -#define bFM3_GPIO_EPFR15_EINT23S0 *((volatile unsigned int*)(0x4266C7B8UL)) -#define bFM3_GPIO_EPFR15_EINT23S1 *((volatile unsigned int*)(0x4266C7BCUL)) -#define bFM3_GPIO_EPFR15_EINT24S0 *((volatile unsigned int*)(0x4266C7C0UL)) -#define bFM3_GPIO_EPFR15_EINT24S1 *((volatile unsigned int*)(0x4266C7C4UL)) -#define bFM3_GPIO_EPFR15_EINT25S0 *((volatile unsigned int*)(0x4266C7C8UL)) -#define bFM3_GPIO_EPFR15_EINT25S1 *((volatile unsigned int*)(0x4266C7CCUL)) -#define bFM3_GPIO_EPFR15_EINT26S0 *((volatile unsigned int*)(0x4266C7D0UL)) -#define bFM3_GPIO_EPFR15_EINT26S1 *((volatile unsigned int*)(0x4266C7D4UL)) -#define bFM3_GPIO_EPFR15_EINT27S0 *((volatile unsigned int*)(0x4266C7D8UL)) -#define bFM3_GPIO_EPFR15_EINT27S1 *((volatile unsigned int*)(0x4266C7DCUL)) -#define bFM3_GPIO_EPFR15_EINT28S0 *((volatile unsigned int*)(0x4266C7E0UL)) -#define bFM3_GPIO_EPFR15_EINT28S1 *((volatile unsigned int*)(0x4266C7E4UL)) -#define bFM3_GPIO_EPFR15_EINT29S0 *((volatile unsigned int*)(0x4266C7E8UL)) -#define bFM3_GPIO_EPFR15_EINT29S1 *((volatile unsigned int*)(0x4266C7ECUL)) -#define bFM3_GPIO_EPFR15_EINT30S0 *((volatile unsigned int*)(0x4266C7F0UL)) -#define bFM3_GPIO_EPFR15_EINT30S1 *((volatile unsigned int*)(0x4266C7F4UL)) -#define bFM3_GPIO_EPFR15_EINT31S0 *((volatile unsigned int*)(0x4266C7F8UL)) -#define bFM3_GPIO_EPFR15_EINT31S1 *((volatile unsigned int*)(0x4266C7FCUL)) -#define bFM3_GPIO_PZR0_P0 *((volatile unsigned int*)(0x4266E000UL)) -#define bFM3_GPIO_PZR0_P1 *((volatile unsigned int*)(0x4266E004UL)) -#define bFM3_GPIO_PZR0_P2 *((volatile unsigned int*)(0x4266E008UL)) -#define bFM3_GPIO_PZR0_P3 *((volatile unsigned int*)(0x4266E00CUL)) -#define bFM3_GPIO_PZR0_P4 *((volatile unsigned int*)(0x4266E010UL)) -#define bFM3_GPIO_PZR0_P5 *((volatile unsigned int*)(0x4266E014UL)) -#define bFM3_GPIO_PZR0_P6 *((volatile unsigned int*)(0x4266E018UL)) -#define bFM3_GPIO_PZR0_P7 *((volatile unsigned int*)(0x4266E01CUL)) -#define bFM3_GPIO_PZR0_P8 *((volatile unsigned int*)(0x4266E020UL)) -#define bFM3_GPIO_PZR0_P9 *((volatile unsigned int*)(0x4266E024UL)) -#define bFM3_GPIO_PZR1_P0 *((volatile unsigned int*)(0x4266E080UL)) -#define bFM3_GPIO_PZR1_P1 *((volatile unsigned int*)(0x4266E084UL)) -#define bFM3_GPIO_PZR1_P2 *((volatile unsigned int*)(0x4266E088UL)) -#define bFM3_GPIO_PZR1_P3 *((volatile unsigned int*)(0x4266E08CUL)) -#define bFM3_GPIO_PZR1_P4 *((volatile unsigned int*)(0x4266E090UL)) -#define bFM3_GPIO_PZR1_P5 *((volatile unsigned int*)(0x4266E094UL)) -#define bFM3_GPIO_PZR1_P6 *((volatile unsigned int*)(0x4266E098UL)) -#define bFM3_GPIO_PZR1_P7 *((volatile unsigned int*)(0x4266E09CUL)) -#define bFM3_GPIO_PZR1_P8 *((volatile unsigned int*)(0x4266E0A0UL)) -#define bFM3_GPIO_PZR1_P9 *((volatile unsigned int*)(0x4266E0A4UL)) -#define bFM3_GPIO_PZR1_PA *((volatile unsigned int*)(0x4266E0A8UL)) -#define bFM3_GPIO_PZR1_PB *((volatile unsigned int*)(0x4266E0ACUL)) -#define bFM3_GPIO_PZR1_PC *((volatile unsigned int*)(0x4266E0B0UL)) -#define bFM3_GPIO_PZR1_PD *((volatile unsigned int*)(0x4266E0B4UL)) -#define bFM3_GPIO_PZR1_PE *((volatile unsigned int*)(0x4266E0B8UL)) -#define bFM3_GPIO_PZR1_PF *((volatile unsigned int*)(0x4266E0BCUL)) -#define bFM3_GPIO_PZR2_P0 *((volatile unsigned int*)(0x4266E100UL)) -#define bFM3_GPIO_PZR2_P1 *((volatile unsigned int*)(0x4266E104UL)) -#define bFM3_GPIO_PZR2_P2 *((volatile unsigned int*)(0x4266E108UL)) -#define bFM3_GPIO_PZR2_P3 *((volatile unsigned int*)(0x4266E10CUL)) -#define bFM3_GPIO_PZR2_P4 *((volatile unsigned int*)(0x4266E110UL)) -#define bFM3_GPIO_PZR2_P5 *((volatile unsigned int*)(0x4266E114UL)) -#define bFM3_GPIO_PZR2_P6 *((volatile unsigned int*)(0x4266E118UL)) -#define bFM3_GPIO_PZR2_P7 *((volatile unsigned int*)(0x4266E11CUL)) -#define bFM3_GPIO_PZR2_P8 *((volatile unsigned int*)(0x4266E120UL)) -#define bFM3_GPIO_PZR2_P9 *((volatile unsigned int*)(0x4266E124UL)) -#define bFM3_GPIO_PZR3_P0 *((volatile unsigned int*)(0x4266E180UL)) -#define bFM3_GPIO_PZR3_P1 *((volatile unsigned int*)(0x4266E184UL)) -#define bFM3_GPIO_PZR3_P2 *((volatile unsigned int*)(0x4266E188UL)) -#define bFM3_GPIO_PZR3_P3 *((volatile unsigned int*)(0x4266E18CUL)) -#define bFM3_GPIO_PZR3_P4 *((volatile unsigned int*)(0x4266E190UL)) -#define bFM3_GPIO_PZR3_P5 *((volatile unsigned int*)(0x4266E194UL)) -#define bFM3_GPIO_PZR3_P6 *((volatile unsigned int*)(0x4266E198UL)) -#define bFM3_GPIO_PZR3_P7 *((volatile unsigned int*)(0x4266E19CUL)) -#define bFM3_GPIO_PZR3_P8 *((volatile unsigned int*)(0x4266E1A0UL)) -#define bFM3_GPIO_PZR3_P9 *((volatile unsigned int*)(0x4266E1A4UL)) -#define bFM3_GPIO_PZR3_PA *((volatile unsigned int*)(0x4266E1A8UL)) -#define bFM3_GPIO_PZR3_PB *((volatile unsigned int*)(0x4266E1ACUL)) -#define bFM3_GPIO_PZR3_PC *((volatile unsigned int*)(0x4266E1B0UL)) -#define bFM3_GPIO_PZR3_PD *((volatile unsigned int*)(0x4266E1B4UL)) -#define bFM3_GPIO_PZR3_PE *((volatile unsigned int*)(0x4266E1B8UL)) -#define bFM3_GPIO_PZR3_PF *((volatile unsigned int*)(0x4266E1BCUL)) -#define bFM3_GPIO_PZR4_P0 *((volatile unsigned int*)(0x4266E200UL)) -#define bFM3_GPIO_PZR4_P1 *((volatile unsigned int*)(0x4266E204UL)) -#define bFM3_GPIO_PZR4_P2 *((volatile unsigned int*)(0x4266E208UL)) -#define bFM3_GPIO_PZR4_P3 *((volatile unsigned int*)(0x4266E20CUL)) -#define bFM3_GPIO_PZR4_P4 *((volatile unsigned int*)(0x4266E210UL)) -#define bFM3_GPIO_PZR4_P5 *((volatile unsigned int*)(0x4266E214UL)) -#define bFM3_GPIO_PZR4_P6 *((volatile unsigned int*)(0x4266E218UL)) -#define bFM3_GPIO_PZR4_P7 *((volatile unsigned int*)(0x4266E21CUL)) -#define bFM3_GPIO_PZR4_P8 *((volatile unsigned int*)(0x4266E220UL)) -#define bFM3_GPIO_PZR4_P9 *((volatile unsigned int*)(0x4266E224UL)) -#define bFM3_GPIO_PZR4_PA *((volatile unsigned int*)(0x4266E228UL)) -#define bFM3_GPIO_PZR4_PB *((volatile unsigned int*)(0x4266E22CUL)) -#define bFM3_GPIO_PZR4_PC *((volatile unsigned int*)(0x4266E230UL)) -#define bFM3_GPIO_PZR4_PD *((volatile unsigned int*)(0x4266E234UL)) -#define bFM3_GPIO_PZR4_PE *((volatile unsigned int*)(0x4266E238UL)) -#define bFM3_GPIO_PZR5_P0 *((volatile unsigned int*)(0x4266E280UL)) -#define bFM3_GPIO_PZR5_P1 *((volatile unsigned int*)(0x4266E284UL)) -#define bFM3_GPIO_PZR5_P2 *((volatile unsigned int*)(0x4266E288UL)) -#define bFM3_GPIO_PZR5_P3 *((volatile unsigned int*)(0x4266E28CUL)) -#define bFM3_GPIO_PZR5_P4 *((volatile unsigned int*)(0x4266E290UL)) -#define bFM3_GPIO_PZR5_P5 *((volatile unsigned int*)(0x4266E294UL)) -#define bFM3_GPIO_PZR5_P6 *((volatile unsigned int*)(0x4266E298UL)) -#define bFM3_GPIO_PZR5_P7 *((volatile unsigned int*)(0x4266E29CUL)) -#define bFM3_GPIO_PZR5_P8 *((volatile unsigned int*)(0x4266E2A0UL)) -#define bFM3_GPIO_PZR5_P9 *((volatile unsigned int*)(0x4266E2A4UL)) -#define bFM3_GPIO_PZR5_PA *((volatile unsigned int*)(0x4266E2A8UL)) -#define bFM3_GPIO_PZR5_PB *((volatile unsigned int*)(0x4266E2ACUL)) -#define bFM3_GPIO_PZR5_PC *((volatile unsigned int*)(0x4266E2B0UL)) -#define bFM3_GPIO_PZR5_PD *((volatile unsigned int*)(0x4266E2B4UL)) -#define bFM3_GPIO_PZR6_P0 *((volatile unsigned int*)(0x4266E300UL)) -#define bFM3_GPIO_PZR6_P1 *((volatile unsigned int*)(0x4266E304UL)) -#define bFM3_GPIO_PZR6_P2 *((volatile unsigned int*)(0x4266E308UL)) -#define bFM3_GPIO_PZR7_P0 *((volatile unsigned int*)(0x4266E380UL)) -#define bFM3_GPIO_PZR7_P1 *((volatile unsigned int*)(0x4266E384UL)) -#define bFM3_GPIO_PZR7_P2 *((volatile unsigned int*)(0x4266E388UL)) -#define bFM3_GPIO_PZR7_P3 *((volatile unsigned int*)(0x4266E38CUL)) -#define bFM3_GPIO_PZR7_P4 *((volatile unsigned int*)(0x4266E390UL)) -#define bFM3_GPIO_PZR7_P5 *((volatile unsigned int*)(0x4266E394UL)) -#define bFM3_GPIO_PZR7_P6 *((volatile unsigned int*)(0x4266E398UL)) -#define bFM3_GPIO_PZR7_P7 *((volatile unsigned int*)(0x4266E39CUL)) -#define bFM3_GPIO_PZR7_P8 *((volatile unsigned int*)(0x4266E3A0UL)) -#define bFM3_GPIO_PZR7_P9 *((volatile unsigned int*)(0x4266E3A4UL)) -#define bFM3_GPIO_PZR7_PA *((volatile unsigned int*)(0x4266E3A8UL)) -#define bFM3_GPIO_PZR7_PB *((volatile unsigned int*)(0x4266E3ACUL)) -#define bFM3_GPIO_PZR7_PC *((volatile unsigned int*)(0x4266E3B0UL)) -#define bFM3_GPIO_PZR7_PD *((volatile unsigned int*)(0x4266E3B4UL)) -#define bFM3_GPIO_PZR7_PE *((volatile unsigned int*)(0x4266E3B8UL)) -#define bFM3_GPIO_PZR7_PF *((volatile unsigned int*)(0x4266E3BCUL)) -#define bFM3_GPIO_PZR8_P0 *((volatile unsigned int*)(0x4266E400UL)) -#define bFM3_GPIO_PZR8_P1 *((volatile unsigned int*)(0x4266E404UL)) -#define bFM3_GPIO_PZR8_P2 *((volatile unsigned int*)(0x4266E408UL)) -#define bFM3_GPIO_PZR8_P3 *((volatile unsigned int*)(0x4266E40CUL)) -#define bFM3_GPIO_PZR9_P0 *((volatile unsigned int*)(0x4266E480UL)) -#define bFM3_GPIO_PZR9_P1 *((volatile unsigned int*)(0x4266E484UL)) -#define bFM3_GPIO_PZR9_P2 *((volatile unsigned int*)(0x4266E488UL)) -#define bFM3_GPIO_PZR9_P3 *((volatile unsigned int*)(0x4266E48CUL)) -#define bFM3_GPIO_PZR9_P4 *((volatile unsigned int*)(0x4266E490UL)) -#define bFM3_GPIO_PZR9_P5 *((volatile unsigned int*)(0x4266E494UL)) -#define bFM3_GPIO_PZRA_P0 *((volatile unsigned int*)(0x4266E500UL)) -#define bFM3_GPIO_PZRA_P1 *((volatile unsigned int*)(0x4266E504UL)) -#define bFM3_GPIO_PZRA_P2 *((volatile unsigned int*)(0x4266E508UL)) -#define bFM3_GPIO_PZRA_P3 *((volatile unsigned int*)(0x4266E50CUL)) -#define bFM3_GPIO_PZRA_P4 *((volatile unsigned int*)(0x4266E510UL)) -#define bFM3_GPIO_PZRA_P5 *((volatile unsigned int*)(0x4266E514UL)) -#define bFM3_GPIO_PZRB_P0 *((volatile unsigned int*)(0x4266E580UL)) -#define bFM3_GPIO_PZRB_P1 *((volatile unsigned int*)(0x4266E584UL)) -#define bFM3_GPIO_PZRB_P2 *((volatile unsigned int*)(0x4266E588UL)) -#define bFM3_GPIO_PZRB_P3 *((volatile unsigned int*)(0x4266E58CUL)) -#define bFM3_GPIO_PZRB_P4 *((volatile unsigned int*)(0x4266E590UL)) -#define bFM3_GPIO_PZRB_P5 *((volatile unsigned int*)(0x4266E594UL)) -#define bFM3_GPIO_PZRB_P6 *((volatile unsigned int*)(0x4266E598UL)) -#define bFM3_GPIO_PZRB_P7 *((volatile unsigned int*)(0x4266E59CUL)) -#define bFM3_GPIO_PZRC_P0 *((volatile unsigned int*)(0x4266E600UL)) -#define bFM3_GPIO_PZRC_P1 *((volatile unsigned int*)(0x4266E604UL)) -#define bFM3_GPIO_PZRC_P2 *((volatile unsigned int*)(0x4266E608UL)) -#define bFM3_GPIO_PZRC_P3 *((volatile unsigned int*)(0x4266E60CUL)) -#define bFM3_GPIO_PZRC_P4 *((volatile unsigned int*)(0x4266E610UL)) -#define bFM3_GPIO_PZRC_P5 *((volatile unsigned int*)(0x4266E614UL)) -#define bFM3_GPIO_PZRC_P6 *((volatile unsigned int*)(0x4266E618UL)) -#define bFM3_GPIO_PZRC_P7 *((volatile unsigned int*)(0x4266E61CUL)) -#define bFM3_GPIO_PZRC_P8 *((volatile unsigned int*)(0x4266E620UL)) -#define bFM3_GPIO_PZRC_P9 *((volatile unsigned int*)(0x4266E624UL)) -#define bFM3_GPIO_PZRC_PA *((volatile unsigned int*)(0x4266E628UL)) -#define bFM3_GPIO_PZRC_PB *((volatile unsigned int*)(0x4266E62CUL)) -#define bFM3_GPIO_PZRC_PC *((volatile unsigned int*)(0x4266E630UL)) -#define bFM3_GPIO_PZRC_PD *((volatile unsigned int*)(0x4266E634UL)) -#define bFM3_GPIO_PZRC_PE *((volatile unsigned int*)(0x4266E638UL)) -#define bFM3_GPIO_PZRC_PF *((volatile unsigned int*)(0x4266E63CUL)) -#define bFM3_GPIO_PZRD_P0 *((volatile unsigned int*)(0x4266E680UL)) -#define bFM3_GPIO_PZRD_P1 *((volatile unsigned int*)(0x4266E684UL)) -#define bFM3_GPIO_PZRD_P2 *((volatile unsigned int*)(0x4266E688UL)) -#define bFM3_GPIO_PZRD_P3 *((volatile unsigned int*)(0x4266E68CUL)) -#define bFM3_GPIO_PZRE_P0 *((volatile unsigned int*)(0x4266E700UL)) -#define bFM3_GPIO_PZRE_P2 *((volatile unsigned int*)(0x4266E708UL)) -#define bFM3_GPIO_PZRE_P3 *((volatile unsigned int*)(0x4266E70CUL)) -#define bFM3_GPIO_PZRF_P0 *((volatile unsigned int*)(0x4266E780UL)) -#define bFM3_GPIO_PZRF_P1 *((volatile unsigned int*)(0x4266E784UL)) -#define bFM3_GPIO_PZRF_P2 *((volatile unsigned int*)(0x4266E788UL)) -#define bFM3_GPIO_PZRF_P3 *((volatile unsigned int*)(0x4266E78CUL)) -#define bFM3_GPIO_PZRF_P4 *((volatile unsigned int*)(0x4266E790UL)) -#define bFM3_GPIO_PZRF_P5 *((volatile unsigned int*)(0x4266E794UL)) -#define bFM3_GPIO_PZRF_P6 *((volatile unsigned int*)(0x4266E798UL)) - -/* Low voltage detection registers */ -#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* USB clock registers */ -#define bFM3_USBETHERNETCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) -#define bFM3_USBETHERNETCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) -#define bFM3_USBETHERNETCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) -#define bFM3_USBETHERNETCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) -#define bFM3_USBETHERNETCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) -#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM3_USBETHERNETCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) -#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) -#define bFM3_USBETHERNETCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) -#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) -#define bFM3_USBETHERNETCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) -#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) -#define bFM3_USBETHERNETCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) -#define bFM3_USBETHERNETCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) - -/* UART asynchronous channel 0 registers */ -#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* UART synchronous channel 0 registers */ -#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) - -/* UART LIN channel 0 registers */ -#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* I2C channel 0 registers */ -#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) - -/* UART asynchronous channel 1 registers */ -#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* UART synchronous channel 1 registers */ -#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) - -/* UART LIN channel 1 registers */ -#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* I2C channel 1 registers */ -#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) - -/* UART asynchronous channel 2 registers */ -#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* UART synchronous channel 2 registers */ -#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) - -/* UART LIN channel 2 registers */ -#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* I2C channel 2 registers */ -#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) - -/* UART asynchronous channel 3 registers */ -#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* UART synchronous channel 3 registers */ -#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) - -/* UART LIN channel 3 registers */ -#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* I2C channel 3 registers */ -#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) - -/* UART asynchronous channel 4 registers */ -#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART synchronous channel 4 registers */ -#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART LIN channel 4 registers */ -#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* I2C channel 4 registers */ -#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART asynchronous channel 5 registers */ -#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART synchronous channel 5 registers */ -#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART LIN channel 5 registers */ -#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* I2C channel 5 registers */ -#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART asynchronous channel 6 registers */ -#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART synchronous channel 6 registers */ -#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART LIN channel 6 registers */ -#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* I2C channel 6 registers */ -#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART asynchronous channel 7 registers */ -#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART synchronous channel 7 registers */ -#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART LIN channel 7 registers */ -#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* I2C channel 7 registers */ -#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* MFS Noise Filter Control registers */ -#define bFM3_MFS_NFC_I2CDNF_I2CDNF00 *((volatile unsigned int*)(0x42710000UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF01 *((volatile unsigned int*)(0x42710004UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF10 *((volatile unsigned int*)(0x42710008UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF11 *((volatile unsigned int*)(0x4271000CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF20 *((volatile unsigned int*)(0x42710010UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF21 *((volatile unsigned int*)(0x42710014UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF30 *((volatile unsigned int*)(0x42710018UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF31 *((volatile unsigned int*)(0x4271001CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF40 *((volatile unsigned int*)(0x42710020UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF41 *((volatile unsigned int*)(0x42710024UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF50 *((volatile unsigned int*)(0x42710028UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF51 *((volatile unsigned int*)(0x4271002CUL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF60 *((volatile unsigned int*)(0x42710030UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF61 *((volatile unsigned int*)(0x42710034UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF70 *((volatile unsigned int*)(0x42710038UL)) -#define bFM3_MFS_NFC_I2CDNF_I2CDNF71 *((volatile unsigned int*)(0x4271003CUL)) - -/* CRC registers */ -#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* External bus interface registers */ -#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM3_EXBUS_MODE0_RDY *((volatile unsigned int*)(0x427E0018UL)) -#define bFM3_EXBUS_MODE0_SHRTDOUT *((volatile unsigned int*)(0x427E001CUL)) -#define bFM3_EXBUS_MODE0_MPXMODE *((volatile unsigned int*)(0x427E0020UL)) -#define bFM3_EXBUS_MODE0_ALEINV *((volatile unsigned int*)(0x427E0024UL)) -#define bFM3_EXBUS_MODE0_MPXDOFF *((volatile unsigned int*)(0x427E002CUL)) -#define bFM3_EXBUS_MODE0_MPXCSOF *((volatile unsigned int*)(0x427E0030UL)) -#define bFM3_EXBUS_MODE0_MOEXEUP *((volatile unsigned int*)(0x427E0034UL)) -#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) -#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM3_EXBUS_MODE1_RDY *((volatile unsigned int*)(0x427E0098UL)) -#define bFM3_EXBUS_MODE1_SHRTDOUT *((volatile unsigned int*)(0x427E009CUL)) -#define bFM3_EXBUS_MODE1_MPXMODE *((volatile unsigned int*)(0x427E00A0UL)) -#define bFM3_EXBUS_MODE1_ALEINV *((volatile unsigned int*)(0x427E00A4UL)) -#define bFM3_EXBUS_MODE1_MPXDOFF *((volatile unsigned int*)(0x427E00ACUL)) -#define bFM3_EXBUS_MODE1_MPXCSOF *((volatile unsigned int*)(0x427E00B0UL)) -#define bFM3_EXBUS_MODE1_MOEXEUP *((volatile unsigned int*)(0x427E00B4UL)) -#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) -#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM3_EXBUS_MODE2_RDY *((volatile unsigned int*)(0x427E0118UL)) -#define bFM3_EXBUS_MODE2_SHRTDOUT *((volatile unsigned int*)(0x427E011CUL)) -#define bFM3_EXBUS_MODE2_MPXMODE *((volatile unsigned int*)(0x427E0120UL)) -#define bFM3_EXBUS_MODE2_ALEINV *((volatile unsigned int*)(0x427E0124UL)) -#define bFM3_EXBUS_MODE2_MPXDOFF *((volatile unsigned int*)(0x427E012CUL)) -#define bFM3_EXBUS_MODE2_MPXCSOF *((volatile unsigned int*)(0x427E0130UL)) -#define bFM3_EXBUS_MODE2_MOEXEUP *((volatile unsigned int*)(0x427E0134UL)) -#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) -#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM3_EXBUS_MODE3_RDY *((volatile unsigned int*)(0x427E0198UL)) -#define bFM3_EXBUS_MODE3_SHRTDOUT *((volatile unsigned int*)(0x427E019CUL)) -#define bFM3_EXBUS_MODE3_MPXMODE *((volatile unsigned int*)(0x427E01A0UL)) -#define bFM3_EXBUS_MODE3_ALEINV *((volatile unsigned int*)(0x427E01A4UL)) -#define bFM3_EXBUS_MODE3_MPXDOFF *((volatile unsigned int*)(0x427E01ACUL)) -#define bFM3_EXBUS_MODE3_MPXCSOF *((volatile unsigned int*)(0x427E01B0UL)) -#define bFM3_EXBUS_MODE3_MOEXEUP *((volatile unsigned int*)(0x427E01B4UL)) -#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) -#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) -#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) -#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) -#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) -#define bFM3_EXBUS_MODE4_RDY *((volatile unsigned int*)(0x427E0218UL)) -#define bFM3_EXBUS_MODE4_SHRTDOUT *((volatile unsigned int*)(0x427E021CUL)) -#define bFM3_EXBUS_MODE4_MPXMODE *((volatile unsigned int*)(0x427E0220UL)) -#define bFM3_EXBUS_MODE4_ALEINV *((volatile unsigned int*)(0x427E0224UL)) -#define bFM3_EXBUS_MODE4_MPXDOFF *((volatile unsigned int*)(0x427E022CUL)) -#define bFM3_EXBUS_MODE4_MPXCSOF *((volatile unsigned int*)(0x427E0230UL)) -#define bFM3_EXBUS_MODE4_MOEXEUP *((volatile unsigned int*)(0x427E0234UL)) -#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) -#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) -#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) -#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) -#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) -#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) -#define bFM3_EXBUS_MODE5_RDY *((volatile unsigned int*)(0x427E0298UL)) -#define bFM3_EXBUS_MODE5_SHRTDOUT *((volatile unsigned int*)(0x427E029CUL)) -#define bFM3_EXBUS_MODE5_MPXMODE *((volatile unsigned int*)(0x427E02A0UL)) -#define bFM3_EXBUS_MODE5_ALEINV *((volatile unsigned int*)(0x427E02A4UL)) -#define bFM3_EXBUS_MODE5_MPXDOFF *((volatile unsigned int*)(0x427E02ACUL)) -#define bFM3_EXBUS_MODE5_MPXCSOF *((volatile unsigned int*)(0x427E02B0UL)) -#define bFM3_EXBUS_MODE5_MOEXEUP *((volatile unsigned int*)(0x427E02B4UL)) -#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) -#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) -#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) -#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) -#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) -#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) -#define bFM3_EXBUS_MODE6_RDY *((volatile unsigned int*)(0x427E0318UL)) -#define bFM3_EXBUS_MODE6_SHRTDOUT *((volatile unsigned int*)(0x427E031CUL)) -#define bFM3_EXBUS_MODE6_MPXMODE *((volatile unsigned int*)(0x427E0320UL)) -#define bFM3_EXBUS_MODE6_ALEINV *((volatile unsigned int*)(0x427E0324UL)) -#define bFM3_EXBUS_MODE6_MPXDOFF *((volatile unsigned int*)(0x427E032CUL)) -#define bFM3_EXBUS_MODE6_MPXCSOF *((volatile unsigned int*)(0x427E0330UL)) -#define bFM3_EXBUS_MODE6_MOEXEUP *((volatile unsigned int*)(0x427E0334UL)) -#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) -#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM3_EXBUS_MODE7_RDY *((volatile unsigned int*)(0x427E0398UL)) -#define bFM3_EXBUS_MODE7_SHRTDOUT *((volatile unsigned int*)(0x427E039CUL)) -#define bFM3_EXBUS_MODE7_MPXMODE *((volatile unsigned int*)(0x427E03A0UL)) -#define bFM3_EXBUS_MODE7_ALEINV *((volatile unsigned int*)(0x427E03A4UL)) -#define bFM3_EXBUS_MODE7_MPXDOFF *((volatile unsigned int*)(0x427E03ACUL)) -#define bFM3_EXBUS_MODE7_MPXCSOF *((volatile unsigned int*)(0x427E03B0UL)) -#define bFM3_EXBUS_MODE7_MOEXEUP *((volatile unsigned int*)(0x427E03B4UL)) -#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) -#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) -#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) -#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) -#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) -#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) -#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) -#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) -#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) -#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) -#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) -#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) -#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) -#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) -#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) -#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) -#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) -#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) -#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) -#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) -#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) -#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) -#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) -#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) -#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) -#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) -#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) -#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) -#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) -#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) -#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) -#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) -#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) -#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) -#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) -#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) -#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) -#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) -#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) -#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) -#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) -#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) -#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) -#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) -#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) -#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) -#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) -#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) -#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) -#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) -#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) -#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) -#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) -#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) -#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) -#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) -#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) -#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) -#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) -#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) -#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) -#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) -#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) -#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) -#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) -#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) -#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) -#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) -#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) -#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) -#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) -#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) -#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) -#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) -#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) -#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) -#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) -#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) -#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) -#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) -#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) -#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) -#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) -#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) -#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) -#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) -#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) -#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) -#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) -#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) -#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) -#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) -#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) -#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) -#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) -#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) -#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) -#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) -#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) -#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) -#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) -#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) -#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) -#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) -#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) -#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) -#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) -#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) -#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) -#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) -#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) -#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) -#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) -#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) -#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) -#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) -#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) -#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) -#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) -#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) -#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) -#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) -#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) -#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) -#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) -#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) -#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) -#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) -#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) -#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) -#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) -#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) -#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) -#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) -#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) -#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) -#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) -#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) -#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) -#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) -#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) -#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) -#define bFM3_EXBUS_ATIM0_ALC0 *((volatile unsigned int*)(0x427E0C00UL)) -#define bFM3_EXBUS_ATIM0_ALC1 *((volatile unsigned int*)(0x427E0C04UL)) -#define bFM3_EXBUS_ATIM0_ALC2 *((volatile unsigned int*)(0x427E0C08UL)) -#define bFM3_EXBUS_ATIM0_ALC3 *((volatile unsigned int*)(0x427E0C0CUL)) -#define bFM3_EXBUS_ATIM0_ALES0 *((volatile unsigned int*)(0x427E0C10UL)) -#define bFM3_EXBUS_ATIM0_ALES1 *((volatile unsigned int*)(0x427E0C14UL)) -#define bFM3_EXBUS_ATIM0_ALES2 *((volatile unsigned int*)(0x427E0C18UL)) -#define bFM3_EXBUS_ATIM0_ALES3 *((volatile unsigned int*)(0x427E0C1CUL)) -#define bFM3_EXBUS_ATIM0_ALEW0 *((volatile unsigned int*)(0x427E0C20UL)) -#define bFM3_EXBUS_ATIM0_ALEW1 *((volatile unsigned int*)(0x427E0C24UL)) -#define bFM3_EXBUS_ATIM0_ALEW2 *((volatile unsigned int*)(0x427E0C28UL)) -#define bFM3_EXBUS_ATIM0_ALEW3 *((volatile unsigned int*)(0x427E0C2CUL)) -#define bFM3_EXBUS_ATIM1_ALC0 *((volatile unsigned int*)(0x427E0C80UL)) -#define bFM3_EXBUS_ATIM1_ALC1 *((volatile unsigned int*)(0x427E0C84UL)) -#define bFM3_EXBUS_ATIM1_ALC2 *((volatile unsigned int*)(0x427E0C88UL)) -#define bFM3_EXBUS_ATIM1_ALC3 *((volatile unsigned int*)(0x427E0C8CUL)) -#define bFM3_EXBUS_ATIM1_ALES0 *((volatile unsigned int*)(0x427E0C90UL)) -#define bFM3_EXBUS_ATIM1_ALES1 *((volatile unsigned int*)(0x427E0C94UL)) -#define bFM3_EXBUS_ATIM1_ALES2 *((volatile unsigned int*)(0x427E0C98UL)) -#define bFM3_EXBUS_ATIM1_ALES3 *((volatile unsigned int*)(0x427E0C9CUL)) -#define bFM3_EXBUS_ATIM1_ALEW0 *((volatile unsigned int*)(0x427E0CA0UL)) -#define bFM3_EXBUS_ATIM1_ALEW1 *((volatile unsigned int*)(0x427E0CA4UL)) -#define bFM3_EXBUS_ATIM1_ALEW2 *((volatile unsigned int*)(0x427E0CA8UL)) -#define bFM3_EXBUS_ATIM1_ALEW3 *((volatile unsigned int*)(0x427E0CACUL)) -#define bFM3_EXBUS_ATIM2_ALC0 *((volatile unsigned int*)(0x427E0D00UL)) -#define bFM3_EXBUS_ATIM2_ALC1 *((volatile unsigned int*)(0x427E0D04UL)) -#define bFM3_EXBUS_ATIM2_ALC2 *((volatile unsigned int*)(0x427E0D08UL)) -#define bFM3_EXBUS_ATIM2_ALC3 *((volatile unsigned int*)(0x427E0D0CUL)) -#define bFM3_EXBUS_ATIM2_ALES0 *((volatile unsigned int*)(0x427E0D10UL)) -#define bFM3_EXBUS_ATIM2_ALES1 *((volatile unsigned int*)(0x427E0D14UL)) -#define bFM3_EXBUS_ATIM2_ALES2 *((volatile unsigned int*)(0x427E0D18UL)) -#define bFM3_EXBUS_ATIM2_ALES3 *((volatile unsigned int*)(0x427E0D1CUL)) -#define bFM3_EXBUS_ATIM2_ALEW0 *((volatile unsigned int*)(0x427E0D20UL)) -#define bFM3_EXBUS_ATIM2_ALEW1 *((volatile unsigned int*)(0x427E0D24UL)) -#define bFM3_EXBUS_ATIM2_ALEW2 *((volatile unsigned int*)(0x427E0D28UL)) -#define bFM3_EXBUS_ATIM2_ALEW3 *((volatile unsigned int*)(0x427E0D2CUL)) -#define bFM3_EXBUS_ATIM3_ALC0 *((volatile unsigned int*)(0x427E0D80UL)) -#define bFM3_EXBUS_ATIM3_ALC1 *((volatile unsigned int*)(0x427E0D84UL)) -#define bFM3_EXBUS_ATIM3_ALC2 *((volatile unsigned int*)(0x427E0D88UL)) -#define bFM3_EXBUS_ATIM3_ALC3 *((volatile unsigned int*)(0x427E0D8CUL)) -#define bFM3_EXBUS_ATIM3_ALES0 *((volatile unsigned int*)(0x427E0D90UL)) -#define bFM3_EXBUS_ATIM3_ALES1 *((volatile unsigned int*)(0x427E0D94UL)) -#define bFM3_EXBUS_ATIM3_ALES2 *((volatile unsigned int*)(0x427E0D98UL)) -#define bFM3_EXBUS_ATIM3_ALES3 *((volatile unsigned int*)(0x427E0D9CUL)) -#define bFM3_EXBUS_ATIM3_ALEW0 *((volatile unsigned int*)(0x427E0DA0UL)) -#define bFM3_EXBUS_ATIM3_ALEW1 *((volatile unsigned int*)(0x427E0DA4UL)) -#define bFM3_EXBUS_ATIM3_ALEW2 *((volatile unsigned int*)(0x427E0DA8UL)) -#define bFM3_EXBUS_ATIM3_ALEW3 *((volatile unsigned int*)(0x427E0DACUL)) -#define bFM3_EXBUS_ATIM4_ALC0 *((volatile unsigned int*)(0x427E0E00UL)) -#define bFM3_EXBUS_ATIM4_ALC1 *((volatile unsigned int*)(0x427E0E04UL)) -#define bFM3_EXBUS_ATIM4_ALC2 *((volatile unsigned int*)(0x427E0E08UL)) -#define bFM3_EXBUS_ATIM4_ALC3 *((volatile unsigned int*)(0x427E0E0CUL)) -#define bFM3_EXBUS_ATIM4_ALES0 *((volatile unsigned int*)(0x427E0E10UL)) -#define bFM3_EXBUS_ATIM4_ALES1 *((volatile unsigned int*)(0x427E0E14UL)) -#define bFM3_EXBUS_ATIM4_ALES2 *((volatile unsigned int*)(0x427E0E18UL)) -#define bFM3_EXBUS_ATIM4_ALES3 *((volatile unsigned int*)(0x427E0E1CUL)) -#define bFM3_EXBUS_ATIM4_ALEW0 *((volatile unsigned int*)(0x427E0E20UL)) -#define bFM3_EXBUS_ATIM4_ALEW1 *((volatile unsigned int*)(0x427E0E24UL)) -#define bFM3_EXBUS_ATIM4_ALEW2 *((volatile unsigned int*)(0x427E0E28UL)) -#define bFM3_EXBUS_ATIM4_ALEW3 *((volatile unsigned int*)(0x427E0E2CUL)) -#define bFM3_EXBUS_ATIM5_ALC0 *((volatile unsigned int*)(0x427E0E80UL)) -#define bFM3_EXBUS_ATIM5_ALC1 *((volatile unsigned int*)(0x427E0E84UL)) -#define bFM3_EXBUS_ATIM5_ALC2 *((volatile unsigned int*)(0x427E0E88UL)) -#define bFM3_EXBUS_ATIM5_ALC3 *((volatile unsigned int*)(0x427E0E8CUL)) -#define bFM3_EXBUS_ATIM5_ALES0 *((volatile unsigned int*)(0x427E0E90UL)) -#define bFM3_EXBUS_ATIM5_ALES1 *((volatile unsigned int*)(0x427E0E94UL)) -#define bFM3_EXBUS_ATIM5_ALES2 *((volatile unsigned int*)(0x427E0E98UL)) -#define bFM3_EXBUS_ATIM5_ALES3 *((volatile unsigned int*)(0x427E0E9CUL)) -#define bFM3_EXBUS_ATIM5_ALEW0 *((volatile unsigned int*)(0x427E0EA0UL)) -#define bFM3_EXBUS_ATIM5_ALEW1 *((volatile unsigned int*)(0x427E0EA4UL)) -#define bFM3_EXBUS_ATIM5_ALEW2 *((volatile unsigned int*)(0x427E0EA8UL)) -#define bFM3_EXBUS_ATIM5_ALEW3 *((volatile unsigned int*)(0x427E0EACUL)) -#define bFM3_EXBUS_ATIM6_ALC0 *((volatile unsigned int*)(0x427E0F00UL)) -#define bFM3_EXBUS_ATIM6_ALC1 *((volatile unsigned int*)(0x427E0F04UL)) -#define bFM3_EXBUS_ATIM6_ALC2 *((volatile unsigned int*)(0x427E0F08UL)) -#define bFM3_EXBUS_ATIM6_ALC3 *((volatile unsigned int*)(0x427E0F0CUL)) -#define bFM3_EXBUS_ATIM6_ALES0 *((volatile unsigned int*)(0x427E0F10UL)) -#define bFM3_EXBUS_ATIM6_ALES1 *((volatile unsigned int*)(0x427E0F14UL)) -#define bFM3_EXBUS_ATIM6_ALES2 *((volatile unsigned int*)(0x427E0F18UL)) -#define bFM3_EXBUS_ATIM6_ALES3 *((volatile unsigned int*)(0x427E0F1CUL)) -#define bFM3_EXBUS_ATIM6_ALEW0 *((volatile unsigned int*)(0x427E0F20UL)) -#define bFM3_EXBUS_ATIM6_ALEW1 *((volatile unsigned int*)(0x427E0F24UL)) -#define bFM3_EXBUS_ATIM6_ALEW2 *((volatile unsigned int*)(0x427E0F28UL)) -#define bFM3_EXBUS_ATIM6_ALEW3 *((volatile unsigned int*)(0x427E0F2CUL)) -#define bFM3_EXBUS_ATIM7_ALC0 *((volatile unsigned int*)(0x427E0F80UL)) -#define bFM3_EXBUS_ATIM7_ALC1 *((volatile unsigned int*)(0x427E0F84UL)) -#define bFM3_EXBUS_ATIM7_ALC2 *((volatile unsigned int*)(0x427E0F88UL)) -#define bFM3_EXBUS_ATIM7_ALC3 *((volatile unsigned int*)(0x427E0F8CUL)) -#define bFM3_EXBUS_ATIM7_ALES0 *((volatile unsigned int*)(0x427E0F90UL)) -#define bFM3_EXBUS_ATIM7_ALES1 *((volatile unsigned int*)(0x427E0F94UL)) -#define bFM3_EXBUS_ATIM7_ALES2 *((volatile unsigned int*)(0x427E0F98UL)) -#define bFM3_EXBUS_ATIM7_ALES3 *((volatile unsigned int*)(0x427E0F9CUL)) -#define bFM3_EXBUS_ATIM7_ALEW0 *((volatile unsigned int*)(0x427E0FA0UL)) -#define bFM3_EXBUS_ATIM7_ALEW1 *((volatile unsigned int*)(0x427E0FA4UL)) -#define bFM3_EXBUS_ATIM7_ALEW2 *((volatile unsigned int*)(0x427E0FA8UL)) -#define bFM3_EXBUS_ATIM7_ALEW3 *((volatile unsigned int*)(0x427E0FACUL)) -#define bFM3_EXBUS_DCLKR_MDIV0 *((volatile unsigned int*)(0x427E6000UL)) -#define bFM3_EXBUS_DCLKR_MDIV1 *((volatile unsigned int*)(0x427E6004UL)) -#define bFM3_EXBUS_DCLKR_MDIV2 *((volatile unsigned int*)(0x427E6008UL)) -#define bFM3_EXBUS_DCLKR_MDIV3 *((volatile unsigned int*)(0x427E600CUL)) -#define bFM3_EXBUS_DCLKR_MCLKON *((volatile unsigned int*)(0x427E6010UL)) - -/* USB channel 0 registers */ -#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL)) -#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* USB channel 1 registers */ -#define bFM3_USB1_HCNT_HOST *((volatile unsigned int*)(0x42A42000UL)) -#define bFM3_USB1_HCNT_URST *((volatile unsigned int*)(0x42A42004UL)) -#define bFM3_USB1_HCNT_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) -#define bFM3_USB1_HCNT_DIRE *((volatile unsigned int*)(0x42A4200CUL)) -#define bFM3_USB1_HCNT_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) -#define bFM3_USB1_HCNT_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) -#define bFM3_USB1_HCNT_URIRE *((volatile unsigned int*)(0x42A42018UL)) -#define bFM3_USB1_HCNT_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) -#define bFM3_USB1_HCNT_RETRY *((volatile unsigned int*)(0x42A42020UL)) -#define bFM3_USB1_HCNT_CANCEL *((volatile unsigned int*)(0x42A42024UL)) -#define bFM3_USB1_HCNT_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) -#define bFM3_USB1_HCNT0_HOST *((volatile unsigned int*)(0x42A42000UL)) -#define bFM3_USB1_HCNT0_URST *((volatile unsigned int*)(0x42A42004UL)) -#define bFM3_USB1_HCNT0_SOFIRE *((volatile unsigned int*)(0x42A42008UL)) -#define bFM3_USB1_HCNT0_DIRE *((volatile unsigned int*)(0x42A4200CUL)) -#define bFM3_USB1_HCNT0_CNNIRE *((volatile unsigned int*)(0x42A42010UL)) -#define bFM3_USB1_HCNT0_CMPIRE *((volatile unsigned int*)(0x42A42014UL)) -#define bFM3_USB1_HCNT0_URIRE *((volatile unsigned int*)(0x42A42018UL)) -#define bFM3_USB1_HCNT0_RWKIRE *((volatile unsigned int*)(0x42A4201CUL)) -#define bFM3_USB1_HCNT1_RETRY *((volatile unsigned int*)(0x42A42020UL)) -#define bFM3_USB1_HCNT1_CANCEL *((volatile unsigned int*)(0x42A42024UL)) -#define bFM3_USB1_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42A42028UL)) -#define bFM3_USB1_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42A42080UL)) -#define bFM3_USB1_HIRQ_DIRQ *((volatile unsigned int*)(0x42A42084UL)) -#define bFM3_USB1_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42A42088UL)) -#define bFM3_USB1_HIRQ_CMPIRQ *((volatile unsigned int*)(0x42A4208CUL)) -#define bFM3_USB1_HIRQ_URIRQ *((volatile unsigned int*)(0x42A42090UL)) -#define bFM3_USB1_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42A42094UL)) -#define bFM3_USB1_HIRQ_TCAN *((volatile unsigned int*)(0x42A4209CUL)) -#define bFM3_USB1_HERR_HS0 *((volatile unsigned int*)(0x42A420A0UL)) -#define bFM3_USB1_HERR_HS1 *((volatile unsigned int*)(0x42A420A4UL)) -#define bFM3_USB1_HERR_STUFF *((volatile unsigned int*)(0x42A420A8UL)) -#define bFM3_USB1_HERR_TGERR *((volatile unsigned int*)(0x42A420ACUL)) -#define bFM3_USB1_HERR_CRC *((volatile unsigned int*)(0x42A420B0UL)) -#define bFM3_USB1_HERR_TOUT *((volatile unsigned int*)(0x42A420B4UL)) -#define bFM3_USB1_HERR_RERR *((volatile unsigned int*)(0x42A420B8UL)) -#define bFM3_USB1_HERR_LSTOF *((volatile unsigned int*)(0x42A420BCUL)) -#define bFM3_USB1_HSTATE_CSTAT *((volatile unsigned int*)(0x42A42100UL)) -#define bFM3_USB1_HSTATE_TMODE *((volatile unsigned int*)(0x42A42104UL)) -#define bFM3_USB1_HSTATE_SUSP *((volatile unsigned int*)(0x42A42108UL)) -#define bFM3_USB1_HSTATE_SOFBUSY *((volatile unsigned int*)(0x42A4210CUL)) -#define bFM3_USB1_HSTATE_CLKSEL *((volatile unsigned int*)(0x42A42110UL)) -#define bFM3_USB1_HSTATE_ALIVE *((volatile unsigned int*)(0x42A42114UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42A42120UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42A42124UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42A42128UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x42A4212CUL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42A42130UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42A42134UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42A42138UL)) -#define bFM3_USB1_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x42A4213CUL)) -#define bFM3_USB1_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42A42180UL)) -#define bFM3_USB1_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42A42184UL)) -#define bFM3_USB1_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42A42188UL)) -#define bFM3_USB1_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x42A4218CUL)) -#define bFM3_USB1_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42A42190UL)) -#define bFM3_USB1_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42A42194UL)) -#define bFM3_USB1_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42A42198UL)) -#define bFM3_USB1_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x42A4219CUL)) -#define bFM3_USB1_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x42A421A0UL)) -#define bFM3_USB1_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x42A421A4UL)) -#define bFM3_USB1_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x42A421A8UL)) -#define bFM3_USB1_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x42A421ACUL)) -#define bFM3_USB1_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x42A421B0UL)) -#define bFM3_USB1_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x42A421B4UL)) -#define bFM3_USB1_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x42A421B8UL)) -#define bFM3_USB1_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x42A421BCUL)) -#define bFM3_USB1_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42A42180UL)) -#define bFM3_USB1_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42A42184UL)) -#define bFM3_USB1_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42A42188UL)) -#define bFM3_USB1_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x42A4218CUL)) -#define bFM3_USB1_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42A42190UL)) -#define bFM3_USB1_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42A42194UL)) -#define bFM3_USB1_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42A42198UL)) -#define bFM3_USB1_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x42A4219CUL)) -#define bFM3_USB1_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x42A421A0UL)) -#define bFM3_USB1_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x42A421A4UL)) -#define bFM3_USB1_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x42A421A8UL)) -#define bFM3_USB1_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x42A421ACUL)) -#define bFM3_USB1_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x42A421B0UL)) -#define bFM3_USB1_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x42A421B4UL)) -#define bFM3_USB1_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x42A421B8UL)) -#define bFM3_USB1_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x42A421BCUL)) -#define bFM3_USB1_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42A42200UL)) -#define bFM3_USB1_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42A42204UL)) -#define bFM3_USB1_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42A42208UL)) -#define bFM3_USB1_HADR_ADDRESS0 *((volatile unsigned int*)(0x42A42220UL)) -#define bFM3_USB1_HADR_ADDRESS1 *((volatile unsigned int*)(0x42A42224UL)) -#define bFM3_USB1_HADR_ADDRESS2 *((volatile unsigned int*)(0x42A42228UL)) -#define bFM3_USB1_HADR_ADDRESS3 *((volatile unsigned int*)(0x42A4222CUL)) -#define bFM3_USB1_HADR_ADDRESS4 *((volatile unsigned int*)(0x42A42230UL)) -#define bFM3_USB1_HADR_ADDRESS5 *((volatile unsigned int*)(0x42A42234UL)) -#define bFM3_USB1_HADR_ADDRESS6 *((volatile unsigned int*)(0x42A42238UL)) -#define bFM3_USB1_HEOF_EOF0 *((volatile unsigned int*)(0x42A42280UL)) -#define bFM3_USB1_HEOF_EOF1 *((volatile unsigned int*)(0x42A42284UL)) -#define bFM3_USB1_HEOF_EOF2 *((volatile unsigned int*)(0x42A42288UL)) -#define bFM3_USB1_HEOF_EOF3 *((volatile unsigned int*)(0x42A4228CUL)) -#define bFM3_USB1_HEOF_EOF4 *((volatile unsigned int*)(0x42A42290UL)) -#define bFM3_USB1_HEOF_EOF5 *((volatile unsigned int*)(0x42A42294UL)) -#define bFM3_USB1_HEOF_EOF6 *((volatile unsigned int*)(0x42A42298UL)) -#define bFM3_USB1_HEOF_EOF7 *((volatile unsigned int*)(0x42A4229CUL)) -#define bFM3_USB1_HEOF_EOF8 *((volatile unsigned int*)(0x42A422A0UL)) -#define bFM3_USB1_HEOF_EOF9 *((volatile unsigned int*)(0x42A422A4UL)) -#define bFM3_USB1_HEOF_EOF10 *((volatile unsigned int*)(0x42A422A8UL)) -#define bFM3_USB1_HEOF_EOF11 *((volatile unsigned int*)(0x42A422ACUL)) -#define bFM3_USB1_HEOF_EOF12 *((volatile unsigned int*)(0x42A422B0UL)) -#define bFM3_USB1_HEOF_EOF13 *((volatile unsigned int*)(0x42A422B4UL)) -#define bFM3_USB1_HEOF_EOF14 *((volatile unsigned int*)(0x42A422B8UL)) -#define bFM3_USB1_HEOF_EOF15 *((volatile unsigned int*)(0x42A422BCUL)) -#define bFM3_USB1_HEOF0_EOF00 *((volatile unsigned int*)(0x42A42280UL)) -#define bFM3_USB1_HEOF0_EOF01 *((volatile unsigned int*)(0x42A42284UL)) -#define bFM3_USB1_HEOF0_EOF02 *((volatile unsigned int*)(0x42A42288UL)) -#define bFM3_USB1_HEOF0_EOF03 *((volatile unsigned int*)(0x42A4228CUL)) -#define bFM3_USB1_HEOF0_EOF04 *((volatile unsigned int*)(0x42A42290UL)) -#define bFM3_USB1_HEOF0_EOF05 *((volatile unsigned int*)(0x42A42294UL)) -#define bFM3_USB1_HEOF0_EOF06 *((volatile unsigned int*)(0x42A42298UL)) -#define bFM3_USB1_HEOF0_EOF07 *((volatile unsigned int*)(0x42A4229CUL)) -#define bFM3_USB1_HEOF1_EOF10 *((volatile unsigned int*)(0x42A422A0UL)) -#define bFM3_USB1_HEOF1_EOF11 *((volatile unsigned int*)(0x42A422A4UL)) -#define bFM3_USB1_HEOF1_EOF12 *((volatile unsigned int*)(0x42A422A8UL)) -#define bFM3_USB1_HEOF1_EOF13 *((volatile unsigned int*)(0x42A422ACUL)) -#define bFM3_USB1_HEOF1_EOF14 *((volatile unsigned int*)(0x42A422B0UL)) -#define bFM3_USB1_HEOF1_EOF15 *((volatile unsigned int*)(0x42A422B4UL)) -#define bFM3_USB1_HFRAME_FRAME0 *((volatile unsigned int*)(0x42A42300UL)) -#define bFM3_USB1_HFRAME_FRAME1 *((volatile unsigned int*)(0x42A42304UL)) -#define bFM3_USB1_HFRAME_FRAME2 *((volatile unsigned int*)(0x42A42308UL)) -#define bFM3_USB1_HFRAME_FRAME3 *((volatile unsigned int*)(0x42A4230CUL)) -#define bFM3_USB1_HFRAME_FRAME4 *((volatile unsigned int*)(0x42A42310UL)) -#define bFM3_USB1_HFRAME_FRAME5 *((volatile unsigned int*)(0x42A42314UL)) -#define bFM3_USB1_HFRAME_FRAME6 *((volatile unsigned int*)(0x42A42318UL)) -#define bFM3_USB1_HFRAME_FRAME7 *((volatile unsigned int*)(0x42A4231CUL)) -#define bFM3_USB1_HFRAME_FRAME8 *((volatile unsigned int*)(0x42A42320UL)) -#define bFM3_USB1_HFRAME_FRAME9 *((volatile unsigned int*)(0x42A42324UL)) -#define bFM3_USB1_HFRAME_FRAME10 *((volatile unsigned int*)(0x42A42328UL)) -#define bFM3_USB1_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42A42300UL)) -#define bFM3_USB1_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42A42304UL)) -#define bFM3_USB1_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42A42308UL)) -#define bFM3_USB1_HFRAME0_FRAME03 *((volatile unsigned int*)(0x42A4230CUL)) -#define bFM3_USB1_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42A42310UL)) -#define bFM3_USB1_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42A42314UL)) -#define bFM3_USB1_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42A42318UL)) -#define bFM3_USB1_HFRAME0_FRAME07 *((volatile unsigned int*)(0x42A4231CUL)) -#define bFM3_USB1_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42A42320UL)) -#define bFM3_USB1_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42A42324UL)) -#define bFM3_USB1_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42A42328UL)) -#define bFM3_USB1_HFRAME1_FRAME13 *((volatile unsigned int*)(0x42A4232CUL)) -#define bFM3_USB1_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42A42380UL)) -#define bFM3_USB1_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42A42384UL)) -#define bFM3_USB1_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42A42388UL)) -#define bFM3_USB1_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x42A4238CUL)) -#define bFM3_USB1_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42A42390UL)) -#define bFM3_USB1_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42A42394UL)) -#define bFM3_USB1_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42A42398UL)) -#define bFM3_USB1_HTOKEN_TGGL *((volatile unsigned int*)(0x42A4239CUL)) -#define bFM3_USB1_UDCC_PWC *((volatile unsigned int*)(0x42A42400UL)) -#define bFM3_USB1_UDCC_RFBK *((volatile unsigned int*)(0x42A42404UL)) -#define bFM3_USB1_UDCC_STALCLREN *((volatile unsigned int*)(0x42A4240CUL)) -#define bFM3_USB1_UDCC_USTP *((volatile unsigned int*)(0x42A42410UL)) -#define bFM3_USB1_UDCC_HCONX *((volatile unsigned int*)(0x42A42414UL)) -#define bFM3_USB1_UDCC_RESUM *((volatile unsigned int*)(0x42A42418UL)) -#define bFM3_USB1_UDCC_RST *((volatile unsigned int*)(0x42A4241CUL)) -#define bFM3_USB1_EP0C_PKS00 *((volatile unsigned int*)(0x42A42480UL)) -#define bFM3_USB1_EP0C_PKS01 *((volatile unsigned int*)(0x42A42484UL)) -#define bFM3_USB1_EP0C_PKS02 *((volatile unsigned int*)(0x42A42488UL)) -#define bFM3_USB1_EP0C_PKS03 *((volatile unsigned int*)(0x42A4248CUL)) -#define bFM3_USB1_EP0C_PKS04 *((volatile unsigned int*)(0x42A42490UL)) -#define bFM3_USB1_EP0C_PKS05 *((volatile unsigned int*)(0x42A42494UL)) -#define bFM3_USB1_EP0C_PKS06 *((volatile unsigned int*)(0x42A42498UL)) -#define bFM3_USB1_EP0C_STAL *((volatile unsigned int*)(0x42A424A4UL)) -#define bFM3_USB1_EP1C_PKS10 *((volatile unsigned int*)(0x42A42500UL)) -#define bFM3_USB1_EP1C_PKS11 *((volatile unsigned int*)(0x42A42504UL)) -#define bFM3_USB1_EP1C_PKS12 *((volatile unsigned int*)(0x42A42508UL)) -#define bFM3_USB1_EP1C_PKS13 *((volatile unsigned int*)(0x42A4250CUL)) -#define bFM3_USB1_EP1C_PKS14 *((volatile unsigned int*)(0x42A42510UL)) -#define bFM3_USB1_EP1C_PKS15 *((volatile unsigned int*)(0x42A42514UL)) -#define bFM3_USB1_EP1C_PKS16 *((volatile unsigned int*)(0x42A42518UL)) -#define bFM3_USB1_EP1C_PKS17 *((volatile unsigned int*)(0x42A4251CUL)) -#define bFM3_USB1_EP1C_PKS18 *((volatile unsigned int*)(0x42A42520UL)) -#define bFM3_USB1_EP1C_STAL *((volatile unsigned int*)(0x42A42524UL)) -#define bFM3_USB1_EP1C_NULE *((volatile unsigned int*)(0x42A42528UL)) -#define bFM3_USB1_EP1C_DMAE *((volatile unsigned int*)(0x42A4252CUL)) -#define bFM3_USB1_EP1C_DIR *((volatile unsigned int*)(0x42A42530UL)) -#define bFM3_USB1_EP1C_TYPE0 *((volatile unsigned int*)(0x42A42534UL)) -#define bFM3_USB1_EP1C_TYPE1 *((volatile unsigned int*)(0x42A42538UL)) -#define bFM3_USB1_EP1C_EPEN *((volatile unsigned int*)(0x42A4253CUL)) -#define bFM3_USB1_EP2C_PKS20 *((volatile unsigned int*)(0x42A42580UL)) -#define bFM3_USB1_EP2C_PKS21 *((volatile unsigned int*)(0x42A42584UL)) -#define bFM3_USB1_EP2C_PKS22 *((volatile unsigned int*)(0x42A42588UL)) -#define bFM3_USB1_EP2C_PKS23 *((volatile unsigned int*)(0x42A4258CUL)) -#define bFM3_USB1_EP2C_PKS24 *((volatile unsigned int*)(0x42A42590UL)) -#define bFM3_USB1_EP2C_PKS25 *((volatile unsigned int*)(0x42A42594UL)) -#define bFM3_USB1_EP2C_PKS26 *((volatile unsigned int*)(0x42A42598UL)) -#define bFM3_USB1_EP2C_STAL *((volatile unsigned int*)(0x42A425A4UL)) -#define bFM3_USB1_EP2C_NULE *((volatile unsigned int*)(0x42A425A8UL)) -#define bFM3_USB1_EP2C_DMAE *((volatile unsigned int*)(0x42A425ACUL)) -#define bFM3_USB1_EP2C_DIR *((volatile unsigned int*)(0x42A425B0UL)) -#define bFM3_USB1_EP2C_TYPE0 *((volatile unsigned int*)(0x42A425B4UL)) -#define bFM3_USB1_EP2C_TYPE1 *((volatile unsigned int*)(0x42A425B8UL)) -#define bFM3_USB1_EP2C_EPEN *((volatile unsigned int*)(0x42A425BCUL)) -#define bFM3_USB1_EP3C_PKS30 *((volatile unsigned int*)(0x42A42600UL)) -#define bFM3_USB1_EP3C_PKS31 *((volatile unsigned int*)(0x42A42604UL)) -#define bFM3_USB1_EP3C_PKS32 *((volatile unsigned int*)(0x42A42608UL)) -#define bFM3_USB1_EP3C_PKS33 *((volatile unsigned int*)(0x42A4260CUL)) -#define bFM3_USB1_EP3C_PKS34 *((volatile unsigned int*)(0x42A42610UL)) -#define bFM3_USB1_EP3C_PKS35 *((volatile unsigned int*)(0x42A42614UL)) -#define bFM3_USB1_EP3C_PKS36 *((volatile unsigned int*)(0x42A42618UL)) -#define bFM3_USB1_EP3C_STAL *((volatile unsigned int*)(0x42A42624UL)) -#define bFM3_USB1_EP3C_NULE *((volatile unsigned int*)(0x42A42628UL)) -#define bFM3_USB1_EP3C_DMAE *((volatile unsigned int*)(0x42A4262CUL)) -#define bFM3_USB1_EP3C_DIR *((volatile unsigned int*)(0x42A42630UL)) -#define bFM3_USB1_EP3C_TYPE0 *((volatile unsigned int*)(0x42A42634UL)) -#define bFM3_USB1_EP3C_TYPE1 *((volatile unsigned int*)(0x42A42638UL)) -#define bFM3_USB1_EP3C_EPEN *((volatile unsigned int*)(0x42A4263CUL)) -#define bFM3_USB1_EP4C_PKS40 *((volatile unsigned int*)(0x42A42680UL)) -#define bFM3_USB1_EP4C_PKS41 *((volatile unsigned int*)(0x42A42684UL)) -#define bFM3_USB1_EP4C_PKS42 *((volatile unsigned int*)(0x42A42688UL)) -#define bFM3_USB1_EP4C_PKS43 *((volatile unsigned int*)(0x42A4268CUL)) -#define bFM3_USB1_EP4C_PKS44 *((volatile unsigned int*)(0x42A42690UL)) -#define bFM3_USB1_EP4C_PKS45 *((volatile unsigned int*)(0x42A42694UL)) -#define bFM3_USB1_EP4C_PKS46 *((volatile unsigned int*)(0x42A42698UL)) -#define bFM3_USB1_EP4C_STAL *((volatile unsigned int*)(0x42A426A4UL)) -#define bFM3_USB1_EP4C_NULE *((volatile unsigned int*)(0x42A426A8UL)) -#define bFM3_USB1_EP4C_DMAE *((volatile unsigned int*)(0x42A426ACUL)) -#define bFM3_USB1_EP4C_DIR *((volatile unsigned int*)(0x42A426B0UL)) -#define bFM3_USB1_EP4C_TYPE0 *((volatile unsigned int*)(0x42A426B4UL)) -#define bFM3_USB1_EP4C_TYPE1 *((volatile unsigned int*)(0x42A426B8UL)) -#define bFM3_USB1_EP4C_EPEN *((volatile unsigned int*)(0x42A426BCUL)) -#define bFM3_USB1_EP5C_PKS50 *((volatile unsigned int*)(0x42A42700UL)) -#define bFM3_USB1_EP5C_PKS51 *((volatile unsigned int*)(0x42A42704UL)) -#define bFM3_USB1_EP5C_PKS52 *((volatile unsigned int*)(0x42A42708UL)) -#define bFM3_USB1_EP5C_PKS53 *((volatile unsigned int*)(0x42A4270CUL)) -#define bFM3_USB1_EP5C_PKS54 *((volatile unsigned int*)(0x42A42710UL)) -#define bFM3_USB1_EP5C_PKS55 *((volatile unsigned int*)(0x42A42714UL)) -#define bFM3_USB1_EP5C_PKS56 *((volatile unsigned int*)(0x42A42718UL)) -#define bFM3_USB1_EP5C_STAL *((volatile unsigned int*)(0x42A42724UL)) -#define bFM3_USB1_EP5C_NULE *((volatile unsigned int*)(0x42A42728UL)) -#define bFM3_USB1_EP5C_DMAE *((volatile unsigned int*)(0x42A4272CUL)) -#define bFM3_USB1_EP5C_DIR *((volatile unsigned int*)(0x42A42730UL)) -#define bFM3_USB1_EP5C_TYPE0 *((volatile unsigned int*)(0x42A42734UL)) -#define bFM3_USB1_EP5C_TYPE1 *((volatile unsigned int*)(0x42A42738UL)) -#define bFM3_USB1_EP5C_EPEN *((volatile unsigned int*)(0x42A4273CUL)) -#define bFM3_USB1_TMSP_TMSP0 *((volatile unsigned int*)(0x42A42780UL)) -#define bFM3_USB1_TMSP_TMSP1 *((volatile unsigned int*)(0x42A42784UL)) -#define bFM3_USB1_TMSP_TMSP2 *((volatile unsigned int*)(0x42A42788UL)) -#define bFM3_USB1_TMSP_TMSP3 *((volatile unsigned int*)(0x42A4278CUL)) -#define bFM3_USB1_TMSP_TMSP4 *((volatile unsigned int*)(0x42A42790UL)) -#define bFM3_USB1_TMSP_TMSP5 *((volatile unsigned int*)(0x42A42794UL)) -#define bFM3_USB1_TMSP_TMSP6 *((volatile unsigned int*)(0x42A42798UL)) -#define bFM3_USB1_TMSP_TMSP7 *((volatile unsigned int*)(0x42A4279CUL)) -#define bFM3_USB1_TMSP_TMSP8 *((volatile unsigned int*)(0x42A427A0UL)) -#define bFM3_USB1_TMSP_TMSP9 *((volatile unsigned int*)(0x42A427A4UL)) -#define bFM3_USB1_TMSP_TMSP10 *((volatile unsigned int*)(0x42A427A8UL)) -#define bFM3_USB1_UDCS_CONF *((volatile unsigned int*)(0x42A42800UL)) -#define bFM3_USB1_UDCS_SETP *((volatile unsigned int*)(0x42A42804UL)) -#define bFM3_USB1_UDCS_WKUP *((volatile unsigned int*)(0x42A42808UL)) -#define bFM3_USB1_UDCS_BRST *((volatile unsigned int*)(0x42A4280CUL)) -#define bFM3_USB1_UDCS_SOF *((volatile unsigned int*)(0x42A42810UL)) -#define bFM3_USB1_UDCS_SUSP *((volatile unsigned int*)(0x42A42814UL)) -#define bFM3_USB1_UDCIE_CONFIE *((volatile unsigned int*)(0x42A42820UL)) -#define bFM3_USB1_UDCIE_CONFN *((volatile unsigned int*)(0x42A42824UL)) -#define bFM3_USB1_UDCIE_WKUPIE *((volatile unsigned int*)(0x42A42828UL)) -#define bFM3_USB1_UDCIE_BRSTIE *((volatile unsigned int*)(0x42A4282CUL)) -#define bFM3_USB1_UDCIE_SOFIE *((volatile unsigned int*)(0x42A42830UL)) -#define bFM3_USB1_UDCIE_SUSPIE *((volatile unsigned int*)(0x42A42834UL)) -#define bFM3_USB1_EP0IS_DRQI *((volatile unsigned int*)(0x42A428A8UL)) -#define bFM3_USB1_EP0IS_DRQIIE *((volatile unsigned int*)(0x42A428B8UL)) -#define bFM3_USB1_EP0IS_BFINI *((volatile unsigned int*)(0x42A428BCUL)) -#define bFM3_USB1_EP0OS_SIZE0 *((volatile unsigned int*)(0x42A42900UL)) -#define bFM3_USB1_EP0OS_SIZE1 *((volatile unsigned int*)(0x42A42904UL)) -#define bFM3_USB1_EP0OS_SIZE2 *((volatile unsigned int*)(0x42A42908UL)) -#define bFM3_USB1_EP0OS_SIZE3 *((volatile unsigned int*)(0x42A4290CUL)) -#define bFM3_USB1_EP0OS_SIZE4 *((volatile unsigned int*)(0x42A42910UL)) -#define bFM3_USB1_EP0OS_SIZE5 *((volatile unsigned int*)(0x42A42914UL)) -#define bFM3_USB1_EP0OS_SIZE6 *((volatile unsigned int*)(0x42A42918UL)) -#define bFM3_USB1_EP0OS_SPK *((volatile unsigned int*)(0x42A42924UL)) -#define bFM3_USB1_EP0OS_DRQO *((volatile unsigned int*)(0x42A42928UL)) -#define bFM3_USB1_EP0OS_SPKIE *((volatile unsigned int*)(0x42A42934UL)) -#define bFM3_USB1_EP0OS_DRQOIE *((volatile unsigned int*)(0x42A42938UL)) -#define bFM3_USB1_EP0OS_BFINI *((volatile unsigned int*)(0x42A4293CUL)) -#define bFM3_USB1_EP1S_SIZE10 *((volatile unsigned int*)(0x42A42980UL)) -#define bFM3_USB1_EP1S_SIZE11 *((volatile unsigned int*)(0x42A42984UL)) -#define bFM3_USB1_EP1S_SIZE12 *((volatile unsigned int*)(0x42A42988UL)) -#define bFM3_USB1_EP1S_SIZE13 *((volatile unsigned int*)(0x42A4298CUL)) -#define bFM3_USB1_EP1S_SIZE14 *((volatile unsigned int*)(0x42A42990UL)) -#define bFM3_USB1_EP1S_SIZE15 *((volatile unsigned int*)(0x42A42994UL)) -#define bFM3_USB1_EP1S_SIZE16 *((volatile unsigned int*)(0x42A42998UL)) -#define bFM3_USB1_EP1S_SIZE17 *((volatile unsigned int*)(0x42A4299CUL)) -#define bFM3_USB1_EP1S_SIZE18 *((volatile unsigned int*)(0x42A429A0UL)) -#define bFM3_USB1_EP1S_SPK *((volatile unsigned int*)(0x42A429A4UL)) -#define bFM3_USB1_EP1S_DRQ *((volatile unsigned int*)(0x42A429A8UL)) -#define bFM3_USB1_EP1S_BUSY *((volatile unsigned int*)(0x42A429ACUL)) -#define bFM3_USB1_EP1S_SPKIE *((volatile unsigned int*)(0x42A429B4UL)) -#define bFM3_USB1_EP1S_DRQIE *((volatile unsigned int*)(0x42A429B8UL)) -#define bFM3_USB1_EP1S_BFINI *((volatile unsigned int*)(0x42A429BCUL)) -#define bFM3_USB1_EP2S_SIZE20 *((volatile unsigned int*)(0x42A42A00UL)) -#define bFM3_USB1_EP2S_SIZE21 *((volatile unsigned int*)(0x42A42A04UL)) -#define bFM3_USB1_EP2S_SIZE22 *((volatile unsigned int*)(0x42A42A08UL)) -#define bFM3_USB1_EP2S_SIZE23 *((volatile unsigned int*)(0x42A42A0CUL)) -#define bFM3_USB1_EP2S_SIZE24 *((volatile unsigned int*)(0x42A42A10UL)) -#define bFM3_USB1_EP2S_SIZE25 *((volatile unsigned int*)(0x42A42A14UL)) -#define bFM3_USB1_EP2S_SIZE26 *((volatile unsigned int*)(0x42A42A18UL)) -#define bFM3_USB1_EP2S_SPK *((volatile unsigned int*)(0x42A42A24UL)) -#define bFM3_USB1_EP2S_DRQ *((volatile unsigned int*)(0x42A42A28UL)) -#define bFM3_USB1_EP2S_BUSY *((volatile unsigned int*)(0x42A42A2CUL)) -#define bFM3_USB1_EP2S_SPKIE *((volatile unsigned int*)(0x42A42A34UL)) -#define bFM3_USB1_EP2S_DRQIE *((volatile unsigned int*)(0x42A42A38UL)) -#define bFM3_USB1_EP2S_BFINI *((volatile unsigned int*)(0x42A42A3CUL)) -#define bFM3_USB1_EP3S_SIZE30 *((volatile unsigned int*)(0x42A42A80UL)) -#define bFM3_USB1_EP3S_SIZE31 *((volatile unsigned int*)(0x42A42A84UL)) -#define bFM3_USB1_EP3S_SIZE32 *((volatile unsigned int*)(0x42A42A88UL)) -#define bFM3_USB1_EP3S_SIZE33 *((volatile unsigned int*)(0x42A42A8CUL)) -#define bFM3_USB1_EP3S_SIZE34 *((volatile unsigned int*)(0x42A42A90UL)) -#define bFM3_USB1_EP3S_SIZE35 *((volatile unsigned int*)(0x42A42A94UL)) -#define bFM3_USB1_EP3S_SIZE36 *((volatile unsigned int*)(0x42A42A98UL)) -#define bFM3_USB1_EP3S_SPK *((volatile unsigned int*)(0x42A42AA4UL)) -#define bFM3_USB1_EP3S_DRQ *((volatile unsigned int*)(0x42A42AA8UL)) -#define bFM3_USB1_EP3S_BUSY *((volatile unsigned int*)(0x42A42AACUL)) -#define bFM3_USB1_EP3S_SPKIE *((volatile unsigned int*)(0x42A42AB4UL)) -#define bFM3_USB1_EP3S_DRQIE *((volatile unsigned int*)(0x42A42AB8UL)) -#define bFM3_USB1_EP3S_BFINI *((volatile unsigned int*)(0x42A42ABCUL)) -#define bFM3_USB1_EP4S_SIZE40 *((volatile unsigned int*)(0x42A42B00UL)) -#define bFM3_USB1_EP4S_SIZE41 *((volatile unsigned int*)(0x42A42B04UL)) -#define bFM3_USB1_EP4S_SIZE42 *((volatile unsigned int*)(0x42A42B08UL)) -#define bFM3_USB1_EP4S_SIZE43 *((volatile unsigned int*)(0x42A42B0CUL)) -#define bFM3_USB1_EP4S_SIZE44 *((volatile unsigned int*)(0x42A42B10UL)) -#define bFM3_USB1_EP4S_SIZE45 *((volatile unsigned int*)(0x42A42B14UL)) -#define bFM3_USB1_EP4S_SIZE46 *((volatile unsigned int*)(0x42A42B18UL)) -#define bFM3_USB1_EP4S_SPK *((volatile unsigned int*)(0x42A42B24UL)) -#define bFM3_USB1_EP4S_DRQ *((volatile unsigned int*)(0x42A42B28UL)) -#define bFM3_USB1_EP4S_BUSY *((volatile unsigned int*)(0x42A42B2CUL)) -#define bFM3_USB1_EP4S_SPKIE *((volatile unsigned int*)(0x42A42B34UL)) -#define bFM3_USB1_EP4S_DRQIE *((volatile unsigned int*)(0x42A42B38UL)) -#define bFM3_USB1_EP4S_BFINI *((volatile unsigned int*)(0x42A42B3CUL)) -#define bFM3_USB1_EP5S_SIZE50 *((volatile unsigned int*)(0x42A42B80UL)) -#define bFM3_USB1_EP5S_SIZE51 *((volatile unsigned int*)(0x42A42B84UL)) -#define bFM3_USB1_EP5S_SIZE52 *((volatile unsigned int*)(0x42A42B88UL)) -#define bFM3_USB1_EP5S_SIZE53 *((volatile unsigned int*)(0x42A42B8CUL)) -#define bFM3_USB1_EP5S_SIZE54 *((volatile unsigned int*)(0x42A42B90UL)) -#define bFM3_USB1_EP5S_SIZE55 *((volatile unsigned int*)(0x42A42B94UL)) -#define bFM3_USB1_EP5S_SIZE56 *((volatile unsigned int*)(0x42A42B98UL)) -#define bFM3_USB1_EP5S_SPK *((volatile unsigned int*)(0x42A42BA4UL)) -#define bFM3_USB1_EP5S_DRQ *((volatile unsigned int*)(0x42A42BA8UL)) -#define bFM3_USB1_EP5S_BUSY *((volatile unsigned int*)(0x42A42BACUL)) -#define bFM3_USB1_EP5S_SPKIE *((volatile unsigned int*)(0x42A42BB4UL)) -#define bFM3_USB1_EP5S_DRQIE *((volatile unsigned int*)(0x42A42BB8UL)) -#define bFM3_USB1_EP5S_BFINI *((volatile unsigned int*)(0x42A42BBCUL)) - -/* DMA controller */ -#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* ETHERNET-MAC0 registers*/ -#define bFM3_ETHERNET_MAC0_MCR_RE *((volatile unsigned int*)(0x42C80008UL)) -#define bFM3_ETHERNET_MAC0_MCR_TE *((volatile unsigned int*)(0x42C8000CUL)) -#define bFM3_ETHERNET_MAC0_MCR_DC *((volatile unsigned int*)(0x42C80010UL)) -#define bFM3_ETHERNET_MAC0_MCR_BL0 *((volatile unsigned int*)(0x42C80014UL)) -#define bFM3_ETHERNET_MAC0_MCR_BL1 *((volatile unsigned int*)(0x42C80018UL)) -#define bFM3_ETHERNET_MAC0_MCR_ACS *((volatile unsigned int*)(0x42C8001CUL)) -#define bFM3_ETHERNET_MAC0_MCR_LUD *((volatile unsigned int*)(0x42C80020UL)) -#define bFM3_ETHERNET_MAC0_MCR_DR *((volatile unsigned int*)(0x42C80024UL)) -#define bFM3_ETHERNET_MAC0_MCR_IPC *((volatile unsigned int*)(0x42C80028UL)) -#define bFM3_ETHERNET_MAC0_MCR_DM *((volatile unsigned int*)(0x42C8002CUL)) -#define bFM3_ETHERNET_MAC0_MCR_LM *((volatile unsigned int*)(0x42C80030UL)) -#define bFM3_ETHERNET_MAC0_MCR_DO *((volatile unsigned int*)(0x42C80034UL)) -#define bFM3_ETHERNET_MAC0_MCR_FES *((volatile unsigned int*)(0x42C80038UL)) -#define bFM3_ETHERNET_MAC0_MCR_PS *((volatile unsigned int*)(0x42C8003CUL)) -#define bFM3_ETHERNET_MAC0_MCR_DCRS *((volatile unsigned int*)(0x42C80040UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG0 *((volatile unsigned int*)(0x42C80044UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG1 *((volatile unsigned int*)(0x42C80048UL)) -#define bFM3_ETHERNET_MAC0_MCR_IFG2 *((volatile unsigned int*)(0x42C8004CUL)) -#define bFM3_ETHERNET_MAC0_MCR_JE *((volatile unsigned int*)(0x42C80050UL)) -#define bFM3_ETHERNET_MAC0_MCR_BE *((volatile unsigned int*)(0x42C80054UL)) -#define bFM3_ETHERNET_MAC0_MCR_JD *((volatile unsigned int*)(0x42C80058UL)) -#define bFM3_ETHERNET_MAC0_MCR_WD *((volatile unsigned int*)(0x42C8005CUL)) -#define bFM3_ETHERNET_MAC0_MCR_TC *((volatile unsigned int*)(0x42C80060UL)) -#define bFM3_ETHERNET_MAC0_MCR_CST *((volatile unsigned int*)(0x42C80064UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PR *((volatile unsigned int*)(0x42C80080UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HUC *((volatile unsigned int*)(0x42C80084UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HMC *((volatile unsigned int*)(0x42C80088UL)) -#define bFM3_ETHERNET_MAC0_MFFR_DAIF *((volatile unsigned int*)(0x42C8008CUL)) -#define bFM3_ETHERNET_MAC0_MFFR_PM *((volatile unsigned int*)(0x42C80090UL)) -#define bFM3_ETHERNET_MAC0_MFFR_DB *((volatile unsigned int*)(0x42C80094UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PCF0 *((volatile unsigned int*)(0x42C80098UL)) -#define bFM3_ETHERNET_MAC0_MFFR_PCF1 *((volatile unsigned int*)(0x42C8009CUL)) -#define bFM3_ETHERNET_MAC0_MFFR_SAIF *((volatile unsigned int*)(0x42C800A0UL)) -#define bFM3_ETHERNET_MAC0_MFFR_SAF *((volatile unsigned int*)(0x42C800A4UL)) -#define bFM3_ETHERNET_MAC0_MFFR_HPF *((volatile unsigned int*)(0x42C800A8UL)) -#define bFM3_ETHERNET_MAC0_MFFR_RA *((volatile unsigned int*)(0x42C800FCUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH0 *((volatile unsigned int*)(0x42C80100UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH1 *((volatile unsigned int*)(0x42C80104UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH2 *((volatile unsigned int*)(0x42C80108UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH3 *((volatile unsigned int*)(0x42C8010CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH4 *((volatile unsigned int*)(0x42C80110UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH5 *((volatile unsigned int*)(0x42C80114UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH6 *((volatile unsigned int*)(0x42C80118UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH7 *((volatile unsigned int*)(0x42C8011CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH8 *((volatile unsigned int*)(0x42C80120UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH9 *((volatile unsigned int*)(0x42C80124UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH10 *((volatile unsigned int*)(0x42C80128UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH11 *((volatile unsigned int*)(0x42C8012CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH12 *((volatile unsigned int*)(0x42C80130UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH13 *((volatile unsigned int*)(0x42C80134UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH14 *((volatile unsigned int*)(0x42C80138UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH15 *((volatile unsigned int*)(0x42C8013CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH16 *((volatile unsigned int*)(0x42C80140UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH17 *((volatile unsigned int*)(0x42C80144UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH18 *((volatile unsigned int*)(0x42C80148UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH19 *((volatile unsigned int*)(0x42C8014CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH20 *((volatile unsigned int*)(0x42C80150UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH21 *((volatile unsigned int*)(0x42C80154UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH22 *((volatile unsigned int*)(0x42C80158UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH23 *((volatile unsigned int*)(0x42C8015CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH24 *((volatile unsigned int*)(0x42C80160UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH25 *((volatile unsigned int*)(0x42C80164UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH26 *((volatile unsigned int*)(0x42C80168UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH27 *((volatile unsigned int*)(0x42C8016CUL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH28 *((volatile unsigned int*)(0x42C80170UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH29 *((volatile unsigned int*)(0x42C80174UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH30 *((volatile unsigned int*)(0x42C80178UL)) -#define bFM3_ETHERNET_MAC0_MHTRH_HTH31 *((volatile unsigned int*)(0x42C8017CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL0 *((volatile unsigned int*)(0x42C80180UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL1 *((volatile unsigned int*)(0x42C80184UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL2 *((volatile unsigned int*)(0x42C80188UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL3 *((volatile unsigned int*)(0x42C8018CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL4 *((volatile unsigned int*)(0x42C80190UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL5 *((volatile unsigned int*)(0x42C80194UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL6 *((volatile unsigned int*)(0x42C80198UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL7 *((volatile unsigned int*)(0x42C8019CUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL8 *((volatile unsigned int*)(0x42C801A0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL9 *((volatile unsigned int*)(0x42C801A4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL10 *((volatile unsigned int*)(0x42C801A8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL11 *((volatile unsigned int*)(0x42C801ACUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL12 *((volatile unsigned int*)(0x42C801B0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL13 *((volatile unsigned int*)(0x42C801B4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL14 *((volatile unsigned int*)(0x42C801B8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL15 *((volatile unsigned int*)(0x42C801BCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL16 *((volatile unsigned int*)(0x42C801C0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL17 *((volatile unsigned int*)(0x42C801C4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL18 *((volatile unsigned int*)(0x42C801C8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL19 *((volatile unsigned int*)(0x42C801CCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL20 *((volatile unsigned int*)(0x42C801D0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL21 *((volatile unsigned int*)(0x42C801D4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL22 *((volatile unsigned int*)(0x42C801D8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL23 *((volatile unsigned int*)(0x42C801DCUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL24 *((volatile unsigned int*)(0x42C801E0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL25 *((volatile unsigned int*)(0x42C801E4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL26 *((volatile unsigned int*)(0x42C801E8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL27 *((volatile unsigned int*)(0x42C801ECUL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL28 *((volatile unsigned int*)(0x42C801F0UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL29 *((volatile unsigned int*)(0x42C801F4UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL30 *((volatile unsigned int*)(0x42C801F8UL)) -#define bFM3_ETHERNET_MAC0_MHTRL_HTL31 *((volatile unsigned int*)(0x42C801FCUL)) -#define bFM3_ETHERNET_MAC0_GAR_GB *((volatile unsigned int*)(0x42C80200UL)) -#define bFM3_ETHERNET_MAC0_GAR_GW *((volatile unsigned int*)(0x42C80204UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR0 *((volatile unsigned int*)(0x42C80208UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR1 *((volatile unsigned int*)(0x42C8020CUL)) -#define bFM3_ETHERNET_MAC0_GAR_CR2 *((volatile unsigned int*)(0x42C80210UL)) -#define bFM3_ETHERNET_MAC0_GAR_CR3 *((volatile unsigned int*)(0x42C80214UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR0 *((volatile unsigned int*)(0x42C80218UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR1 *((volatile unsigned int*)(0x42C8021CUL)) -#define bFM3_ETHERNET_MAC0_GAR_GR2 *((volatile unsigned int*)(0x42C80220UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR3 *((volatile unsigned int*)(0x42C80224UL)) -#define bFM3_ETHERNET_MAC0_GAR_GR4 *((volatile unsigned int*)(0x42C80228UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA0 *((volatile unsigned int*)(0x42C8022CUL)) -#define bFM3_ETHERNET_MAC0_GAR_PA1 *((volatile unsigned int*)(0x42C80230UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA2 *((volatile unsigned int*)(0x42C80234UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA3 *((volatile unsigned int*)(0x42C80238UL)) -#define bFM3_ETHERNET_MAC0_GAR_PA4 *((volatile unsigned int*)(0x42C8023CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD0 *((volatile unsigned int*)(0x42C80280UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD1 *((volatile unsigned int*)(0x42C80284UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD2 *((volatile unsigned int*)(0x42C80288UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD3 *((volatile unsigned int*)(0x42C8028CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD4 *((volatile unsigned int*)(0x42C80290UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD5 *((volatile unsigned int*)(0x42C80294UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD6 *((volatile unsigned int*)(0x42C80298UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD7 *((volatile unsigned int*)(0x42C8029CUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD8 *((volatile unsigned int*)(0x42C802A0UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD9 *((volatile unsigned int*)(0x42C802A4UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD10 *((volatile unsigned int*)(0x42C802A8UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD11 *((volatile unsigned int*)(0x42C802ACUL)) -#define bFM3_ETHERNET_MAC0_GDR_GD12 *((volatile unsigned int*)(0x42C802B0UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD13 *((volatile unsigned int*)(0x42C802B4UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD14 *((volatile unsigned int*)(0x42C802B8UL)) -#define bFM3_ETHERNET_MAC0_GDR_GD15 *((volatile unsigned int*)(0x42C802BCUL)) -#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA *((volatile unsigned int*)(0x42C80300UL)) -#define bFM3_ETHERNET_MAC0_FCR_TFE *((volatile unsigned int*)(0x42C80304UL)) -#define bFM3_ETHERNET_MAC0_FCR_RFE *((volatile unsigned int*)(0x42C80308UL)) -#define bFM3_ETHERNET_MAC0_FCR_UP *((volatile unsigned int*)(0x42C8030CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PLT0 *((volatile unsigned int*)(0x42C80310UL)) -#define bFM3_ETHERNET_MAC0_FCR_PLT1 *((volatile unsigned int*)(0x42C80314UL)) -#define bFM3_ETHERNET_MAC0_FCR_DZPQ *((volatile unsigned int*)(0x42C8031CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT0 *((volatile unsigned int*)(0x42C80340UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT1 *((volatile unsigned int*)(0x42C80344UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT2 *((volatile unsigned int*)(0x42C80348UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT3 *((volatile unsigned int*)(0x42C8034CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT4 *((volatile unsigned int*)(0x42C80350UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT5 *((volatile unsigned int*)(0x42C80354UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT6 *((volatile unsigned int*)(0x42C80358UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT7 *((volatile unsigned int*)(0x42C8035CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT8 *((volatile unsigned int*)(0x42C80360UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT9 *((volatile unsigned int*)(0x42C80364UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT10 *((volatile unsigned int*)(0x42C80368UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT11 *((volatile unsigned int*)(0x42C8036CUL)) -#define bFM3_ETHERNET_MAC0_FCR_PT12 *((volatile unsigned int*)(0x42C80370UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT13 *((volatile unsigned int*)(0x42C80374UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT14 *((volatile unsigned int*)(0x42C80378UL)) -#define bFM3_ETHERNET_MAC0_FCR_PT15 *((volatile unsigned int*)(0x42C8037CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL0 *((volatile unsigned int*)(0x42C80380UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL1 *((volatile unsigned int*)(0x42C80384UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL2 *((volatile unsigned int*)(0x42C80388UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL3 *((volatile unsigned int*)(0x42C8038CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL4 *((volatile unsigned int*)(0x42C80390UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL5 *((volatile unsigned int*)(0x42C80394UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL6 *((volatile unsigned int*)(0x42C80398UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL7 *((volatile unsigned int*)(0x42C8039CUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL8 *((volatile unsigned int*)(0x42C803A0UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL9 *((volatile unsigned int*)(0x42C803A4UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL10 *((volatile unsigned int*)(0x42C803A8UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL11 *((volatile unsigned int*)(0x42C803ACUL)) -#define bFM3_ETHERNET_MAC0_VTR_VL12 *((volatile unsigned int*)(0x42C803B0UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL13 *((volatile unsigned int*)(0x42C803B4UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL14 *((volatile unsigned int*)(0x42C803B8UL)) -#define bFM3_ETHERNET_MAC0_VTR_VL15 *((volatile unsigned int*)(0x42C803BCUL)) -#define bFM3_ETHERNET_MAC0_VTR_ETV *((volatile unsigned int*)(0x42C803C0UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42C80500UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42C80504UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42C80508UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42C8050CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42C80510UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42C80514UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42C80518UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42C8051CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42C80520UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42C80524UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42C80528UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42C8052CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42C80530UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42C80534UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42C80538UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42C8053CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42C80540UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42C80544UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42C80548UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42C8054CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42C80550UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42C80554UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42C80558UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42C8055CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42C80560UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42C80564UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42C80568UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42C8056CUL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42C80570UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42C80574UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42C80578UL)) -#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42C8057CUL)) -#define bFM3_ETHERNET_MAC0_PMTR_PD *((volatile unsigned int*)(0x42C80580UL)) -#define bFM3_ETHERNET_MAC0_PMTR_MPE *((volatile unsigned int*)(0x42C80584UL)) -#define bFM3_ETHERNET_MAC0_PMTR_WFE *((volatile unsigned int*)(0x42C80588UL)) -#define bFM3_ETHERNET_MAC0_PMTR_MPR *((volatile unsigned int*)(0x42C80594UL)) -#define bFM3_ETHERNET_MAC0_PMTR_WPR *((volatile unsigned int*)(0x42C80598UL)) -#define bFM3_ETHERNET_MAC0_PMTR_GU *((volatile unsigned int*)(0x42C805A4UL)) -#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR *((volatile unsigned int*)(0x42C805FCUL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN *((volatile unsigned int*)(0x42C80600UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX *((volatile unsigned int*)(0x42C80604UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN *((volatile unsigned int*)(0x42C80608UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX *((volatile unsigned int*)(0x42C8060CUL)) -#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST *((volatile unsigned int*)(0x42C80620UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST *((volatile unsigned int*)(0x42C80624UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN *((volatile unsigned int*)(0x42C80640UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_PLS *((volatile unsigned int*)(0x42C80644UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN *((volatile unsigned int*)(0x42C80648UL)) -#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA *((volatile unsigned int*)(0x42C8064CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT0 *((volatile unsigned int*)(0x42C80680UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT1 *((volatile unsigned int*)(0x42C80684UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT2 *((volatile unsigned int*)(0x42C80688UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT3 *((volatile unsigned int*)(0x42C8068CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT4 *((volatile unsigned int*)(0x42C80690UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT5 *((volatile unsigned int*)(0x42C80694UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT6 *((volatile unsigned int*)(0x42C80698UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT7 *((volatile unsigned int*)(0x42C8069CUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT8 *((volatile unsigned int*)(0x42C806A0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT9 *((volatile unsigned int*)(0x42C806A4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT10 *((volatile unsigned int*)(0x42C806A8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT11 *((volatile unsigned int*)(0x42C806ACUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT12 *((volatile unsigned int*)(0x42C806B0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT13 *((volatile unsigned int*)(0x42C806B4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT14 *((volatile unsigned int*)(0x42C806B8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_TWT15 *((volatile unsigned int*)(0x42C806BCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT0 *((volatile unsigned int*)(0x42C806C0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT1 *((volatile unsigned int*)(0x42C806C4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT2 *((volatile unsigned int*)(0x42C806C8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT3 *((volatile unsigned int*)(0x42C806CCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT4 *((volatile unsigned int*)(0x42C806D0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT5 *((volatile unsigned int*)(0x42C806D4UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT6 *((volatile unsigned int*)(0x42C806D8UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT7 *((volatile unsigned int*)(0x42C806DCUL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT8 *((volatile unsigned int*)(0x42C806E0UL)) -#define bFM3_ETHERNET_MAC0_LPITCR_LIT9 *((volatile unsigned int*)(0x42C806E4UL)) -#define bFM3_ETHERNET_MAC0_ISR_RGIS *((volatile unsigned int*)(0x42C80700UL)) -#define bFM3_ETHERNET_MAC0_ISR_PIS *((volatile unsigned int*)(0x42C8070CUL)) -#define bFM3_ETHERNET_MAC0_ISR_MIS *((volatile unsigned int*)(0x42C80710UL)) -#define bFM3_ETHERNET_MAC0_ISR_RIS *((volatile unsigned int*)(0x42C80714UL)) -#define bFM3_ETHERNET_MAC0_ISR_TIS *((volatile unsigned int*)(0x42C80718UL)) -#define bFM3_ETHERNET_MAC0_ISR_COIS *((volatile unsigned int*)(0x42C8071CUL)) -#define bFM3_ETHERNET_MAC0_ISR_TSIS *((volatile unsigned int*)(0x42C80724UL)) -#define bFM3_ETHERNET_MAC0_ISR_LPIIS *((volatile unsigned int*)(0x42C80728UL)) -#define bFM3_ETHERNET_MAC0_IMR_RGIM *((volatile unsigned int*)(0x42C80780UL)) -#define bFM3_ETHERNET_MAC0_IMR_PIM *((volatile unsigned int*)(0x42C8078CUL)) -#define bFM3_ETHERNET_MAC0_IMR_TSIM *((volatile unsigned int*)(0x42C80794UL)) -#define bFM3_ETHERNET_MAC0_IMR_LPIIM *((volatile unsigned int*)(0x42C80798UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A32 *((volatile unsigned int*)(0x42C80800UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A33 *((volatile unsigned int*)(0x42C80804UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A34 *((volatile unsigned int*)(0x42C80808UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A35 *((volatile unsigned int*)(0x42C8080CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A36 *((volatile unsigned int*)(0x42C80810UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A37 *((volatile unsigned int*)(0x42C80814UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A38 *((volatile unsigned int*)(0x42C80818UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A39 *((volatile unsigned int*)(0x42C8081CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A40 *((volatile unsigned int*)(0x42C80820UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A41 *((volatile unsigned int*)(0x42C80824UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A42 *((volatile unsigned int*)(0x42C80828UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A43 *((volatile unsigned int*)(0x42C8082CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A44 *((volatile unsigned int*)(0x42C80830UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A45 *((volatile unsigned int*)(0x42C80834UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A46 *((volatile unsigned int*)(0x42C80838UL)) -#define bFM3_ETHERNET_MAC0_MAR0H_A47 *((volatile unsigned int*)(0x42C8083CUL)) -#define bFM3_ETHERNET_MAC0_MAR0H_MO *((volatile unsigned int*)(0x42C8087CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A0 *((volatile unsigned int*)(0x42C80880UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A1 *((volatile unsigned int*)(0x42C80884UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A2 *((volatile unsigned int*)(0x42C80888UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A3 *((volatile unsigned int*)(0x42C8088CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A4 *((volatile unsigned int*)(0x42C80890UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A5 *((volatile unsigned int*)(0x42C80894UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A6 *((volatile unsigned int*)(0x42C80898UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A7 *((volatile unsigned int*)(0x42C8089CUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A8 *((volatile unsigned int*)(0x42C808A0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A9 *((volatile unsigned int*)(0x42C808A4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A10 *((volatile unsigned int*)(0x42C808A8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A11 *((volatile unsigned int*)(0x42C808ACUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A12 *((volatile unsigned int*)(0x42C808B0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A13 *((volatile unsigned int*)(0x42C808B4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A14 *((volatile unsigned int*)(0x42C808B8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A15 *((volatile unsigned int*)(0x42C808BCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A16 *((volatile unsigned int*)(0x42C808C0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A17 *((volatile unsigned int*)(0x42C808C4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A18 *((volatile unsigned int*)(0x42C808C8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A19 *((volatile unsigned int*)(0x42C808CCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A20 *((volatile unsigned int*)(0x42C808D0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A21 *((volatile unsigned int*)(0x42C808D4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A22 *((volatile unsigned int*)(0x42C808D8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A23 *((volatile unsigned int*)(0x42C808DCUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A24 *((volatile unsigned int*)(0x42C808E0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A25 *((volatile unsigned int*)(0x42C808E4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A26 *((volatile unsigned int*)(0x42C808E8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A27 *((volatile unsigned int*)(0x42C808ECUL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A28 *((volatile unsigned int*)(0x42C808F0UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A29 *((volatile unsigned int*)(0x42C808F4UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A30 *((volatile unsigned int*)(0x42C808F8UL)) -#define bFM3_ETHERNET_MAC0_MAR0L_A31 *((volatile unsigned int*)(0x42C808FCUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A32 *((volatile unsigned int*)(0x42C80900UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A33 *((volatile unsigned int*)(0x42C80904UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A34 *((volatile unsigned int*)(0x42C80908UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A35 *((volatile unsigned int*)(0x42C8090CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A36 *((volatile unsigned int*)(0x42C80910UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A37 *((volatile unsigned int*)(0x42C80914UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A38 *((volatile unsigned int*)(0x42C80918UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A39 *((volatile unsigned int*)(0x42C8091CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A40 *((volatile unsigned int*)(0x42C80920UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A41 *((volatile unsigned int*)(0x42C80924UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A42 *((volatile unsigned int*)(0x42C80928UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A43 *((volatile unsigned int*)(0x42C8092CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A44 *((volatile unsigned int*)(0x42C80930UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A45 *((volatile unsigned int*)(0x42C80934UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A46 *((volatile unsigned int*)(0x42C80938UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_A47 *((volatile unsigned int*)(0x42C8093CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC0 *((volatile unsigned int*)(0x42C80960UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC1 *((volatile unsigned int*)(0x42C80964UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC2 *((volatile unsigned int*)(0x42C80968UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC3 *((volatile unsigned int*)(0x42C8096CUL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC4 *((volatile unsigned int*)(0x42C80970UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_MBC5 *((volatile unsigned int*)(0x42C80974UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_SA *((volatile unsigned int*)(0x42C80978UL)) -#define bFM3_ETHERNET_MAC0_MAR1H_AE *((volatile unsigned int*)(0x42C8097CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A0 *((volatile unsigned int*)(0x42C80980UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A1 *((volatile unsigned int*)(0x42C80984UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A2 *((volatile unsigned int*)(0x42C80988UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A3 *((volatile unsigned int*)(0x42C8098CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A4 *((volatile unsigned int*)(0x42C80990UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A5 *((volatile unsigned int*)(0x42C80994UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A6 *((volatile unsigned int*)(0x42C80998UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A7 *((volatile unsigned int*)(0x42C8099CUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A8 *((volatile unsigned int*)(0x42C809A0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A9 *((volatile unsigned int*)(0x42C809A4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A10 *((volatile unsigned int*)(0x42C809A8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A11 *((volatile unsigned int*)(0x42C809ACUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A12 *((volatile unsigned int*)(0x42C809B0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A13 *((volatile unsigned int*)(0x42C809B4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A14 *((volatile unsigned int*)(0x42C809B8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A15 *((volatile unsigned int*)(0x42C809BCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A16 *((volatile unsigned int*)(0x42C809C0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A17 *((volatile unsigned int*)(0x42C809C4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A18 *((volatile unsigned int*)(0x42C809C8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A19 *((volatile unsigned int*)(0x42C809CCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A20 *((volatile unsigned int*)(0x42C809D0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A21 *((volatile unsigned int*)(0x42C809D4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A22 *((volatile unsigned int*)(0x42C809D8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A23 *((volatile unsigned int*)(0x42C809DCUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A24 *((volatile unsigned int*)(0x42C809E0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A25 *((volatile unsigned int*)(0x42C809E4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A26 *((volatile unsigned int*)(0x42C809E8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A27 *((volatile unsigned int*)(0x42C809ECUL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A28 *((volatile unsigned int*)(0x42C809F0UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A29 *((volatile unsigned int*)(0x42C809F4UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A30 *((volatile unsigned int*)(0x42C809F8UL)) -#define bFM3_ETHERNET_MAC0_MAR1L_A31 *((volatile unsigned int*)(0x42C809FCUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A32 *((volatile unsigned int*)(0x42C80A00UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A33 *((volatile unsigned int*)(0x42C80A04UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A34 *((volatile unsigned int*)(0x42C80A08UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A35 *((volatile unsigned int*)(0x42C80A0CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A36 *((volatile unsigned int*)(0x42C80A10UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A37 *((volatile unsigned int*)(0x42C80A14UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A38 *((volatile unsigned int*)(0x42C80A18UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A39 *((volatile unsigned int*)(0x42C80A1CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A40 *((volatile unsigned int*)(0x42C80A20UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A41 *((volatile unsigned int*)(0x42C80A24UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A42 *((volatile unsigned int*)(0x42C80A28UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A43 *((volatile unsigned int*)(0x42C80A2CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A44 *((volatile unsigned int*)(0x42C80A30UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A45 *((volatile unsigned int*)(0x42C80A34UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A46 *((volatile unsigned int*)(0x42C80A38UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_A47 *((volatile unsigned int*)(0x42C80A3CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC0 *((volatile unsigned int*)(0x42C80A60UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC1 *((volatile unsigned int*)(0x42C80A64UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC2 *((volatile unsigned int*)(0x42C80A68UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC3 *((volatile unsigned int*)(0x42C80A6CUL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC4 *((volatile unsigned int*)(0x42C80A70UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_MBC5 *((volatile unsigned int*)(0x42C80A74UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_SA *((volatile unsigned int*)(0x42C80A78UL)) -#define bFM3_ETHERNET_MAC0_MAR2H_AE *((volatile unsigned int*)(0x42C80A7CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A0 *((volatile unsigned int*)(0x42C80A80UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A1 *((volatile unsigned int*)(0x42C80A84UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A2 *((volatile unsigned int*)(0x42C80A88UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A3 *((volatile unsigned int*)(0x42C80A8CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A4 *((volatile unsigned int*)(0x42C80A90UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A5 *((volatile unsigned int*)(0x42C80A94UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A6 *((volatile unsigned int*)(0x42C80A98UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A7 *((volatile unsigned int*)(0x42C80A9CUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A8 *((volatile unsigned int*)(0x42C80AA0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A9 *((volatile unsigned int*)(0x42C80AA4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A10 *((volatile unsigned int*)(0x42C80AA8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A11 *((volatile unsigned int*)(0x42C80AACUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A12 *((volatile unsigned int*)(0x42C80AB0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A13 *((volatile unsigned int*)(0x42C80AB4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A14 *((volatile unsigned int*)(0x42C80AB8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A15 *((volatile unsigned int*)(0x42C80ABCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A16 *((volatile unsigned int*)(0x42C80AC0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A17 *((volatile unsigned int*)(0x42C80AC4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A18 *((volatile unsigned int*)(0x42C80AC8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A19 *((volatile unsigned int*)(0x42C80ACCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A20 *((volatile unsigned int*)(0x42C80AD0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A21 *((volatile unsigned int*)(0x42C80AD4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A22 *((volatile unsigned int*)(0x42C80AD8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A23 *((volatile unsigned int*)(0x42C80ADCUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A24 *((volatile unsigned int*)(0x42C80AE0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A25 *((volatile unsigned int*)(0x42C80AE4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A26 *((volatile unsigned int*)(0x42C80AE8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A27 *((volatile unsigned int*)(0x42C80AECUL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A28 *((volatile unsigned int*)(0x42C80AF0UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A29 *((volatile unsigned int*)(0x42C80AF4UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A30 *((volatile unsigned int*)(0x42C80AF8UL)) -#define bFM3_ETHERNET_MAC0_MAR2L_A31 *((volatile unsigned int*)(0x42C80AFCUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A32 *((volatile unsigned int*)(0x42C80B00UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A33 *((volatile unsigned int*)(0x42C80B04UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A34 *((volatile unsigned int*)(0x42C80B08UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A35 *((volatile unsigned int*)(0x42C80B0CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A36 *((volatile unsigned int*)(0x42C80B10UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A37 *((volatile unsigned int*)(0x42C80B14UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A38 *((volatile unsigned int*)(0x42C80B18UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A39 *((volatile unsigned int*)(0x42C80B1CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A40 *((volatile unsigned int*)(0x42C80B20UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A41 *((volatile unsigned int*)(0x42C80B24UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A42 *((volatile unsigned int*)(0x42C80B28UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A43 *((volatile unsigned int*)(0x42C80B2CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A44 *((volatile unsigned int*)(0x42C80B30UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A45 *((volatile unsigned int*)(0x42C80B34UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A46 *((volatile unsigned int*)(0x42C80B38UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_A47 *((volatile unsigned int*)(0x42C80B3CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC0 *((volatile unsigned int*)(0x42C80B60UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC1 *((volatile unsigned int*)(0x42C80B64UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC2 *((volatile unsigned int*)(0x42C80B68UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC3 *((volatile unsigned int*)(0x42C80B6CUL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC4 *((volatile unsigned int*)(0x42C80B70UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_MBC5 *((volatile unsigned int*)(0x42C80B74UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_SA *((volatile unsigned int*)(0x42C80B78UL)) -#define bFM3_ETHERNET_MAC0_MAR3H_AE *((volatile unsigned int*)(0x42C80B7CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A0 *((volatile unsigned int*)(0x42C80B80UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A1 *((volatile unsigned int*)(0x42C80B84UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A2 *((volatile unsigned int*)(0x42C80B88UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A3 *((volatile unsigned int*)(0x42C80B8CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A4 *((volatile unsigned int*)(0x42C80B90UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A5 *((volatile unsigned int*)(0x42C80B94UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A6 *((volatile unsigned int*)(0x42C80B98UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A7 *((volatile unsigned int*)(0x42C80B9CUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A8 *((volatile unsigned int*)(0x42C80BA0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A9 *((volatile unsigned int*)(0x42C80BA4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A10 *((volatile unsigned int*)(0x42C80BA8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A11 *((volatile unsigned int*)(0x42C80BACUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A12 *((volatile unsigned int*)(0x42C80BB0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A13 *((volatile unsigned int*)(0x42C80BB4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A14 *((volatile unsigned int*)(0x42C80BB8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A15 *((volatile unsigned int*)(0x42C80BBCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A16 *((volatile unsigned int*)(0x42C80BC0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A17 *((volatile unsigned int*)(0x42C80BC4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A18 *((volatile unsigned int*)(0x42C80BC8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A19 *((volatile unsigned int*)(0x42C80BCCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A20 *((volatile unsigned int*)(0x42C80BD0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A21 *((volatile unsigned int*)(0x42C80BD4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A22 *((volatile unsigned int*)(0x42C80BD8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A23 *((volatile unsigned int*)(0x42C80BDCUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A24 *((volatile unsigned int*)(0x42C80BE0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A25 *((volatile unsigned int*)(0x42C80BE4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A26 *((volatile unsigned int*)(0x42C80BE8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A27 *((volatile unsigned int*)(0x42C80BECUL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A28 *((volatile unsigned int*)(0x42C80BF0UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A29 *((volatile unsigned int*)(0x42C80BF4UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A30 *((volatile unsigned int*)(0x42C80BF8UL)) -#define bFM3_ETHERNET_MAC0_MAR3L_A31 *((volatile unsigned int*)(0x42C80BFCUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A32 *((volatile unsigned int*)(0x42C80C00UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A33 *((volatile unsigned int*)(0x42C80C04UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A34 *((volatile unsigned int*)(0x42C80C08UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A35 *((volatile unsigned int*)(0x42C80C0CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A36 *((volatile unsigned int*)(0x42C80C10UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A37 *((volatile unsigned int*)(0x42C80C14UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A38 *((volatile unsigned int*)(0x42C80C18UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A39 *((volatile unsigned int*)(0x42C80C1CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A40 *((volatile unsigned int*)(0x42C80C20UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A41 *((volatile unsigned int*)(0x42C80C24UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A42 *((volatile unsigned int*)(0x42C80C28UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A43 *((volatile unsigned int*)(0x42C80C2CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A44 *((volatile unsigned int*)(0x42C80C30UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A45 *((volatile unsigned int*)(0x42C80C34UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A46 *((volatile unsigned int*)(0x42C80C38UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_A47 *((volatile unsigned int*)(0x42C80C3CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC0 *((volatile unsigned int*)(0x42C80C60UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC1 *((volatile unsigned int*)(0x42C80C64UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC2 *((volatile unsigned int*)(0x42C80C68UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC3 *((volatile unsigned int*)(0x42C80C6CUL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC4 *((volatile unsigned int*)(0x42C80C70UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_MBC5 *((volatile unsigned int*)(0x42C80C74UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_SA *((volatile unsigned int*)(0x42C80C78UL)) -#define bFM3_ETHERNET_MAC0_MAR4H_AE *((volatile unsigned int*)(0x42C80C7CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A0 *((volatile unsigned int*)(0x42C80C80UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A1 *((volatile unsigned int*)(0x42C80C84UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A2 *((volatile unsigned int*)(0x42C80C88UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A3 *((volatile unsigned int*)(0x42C80C8CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A4 *((volatile unsigned int*)(0x42C80C90UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A5 *((volatile unsigned int*)(0x42C80C94UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A6 *((volatile unsigned int*)(0x42C80C98UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A7 *((volatile unsigned int*)(0x42C80C9CUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A8 *((volatile unsigned int*)(0x42C80CA0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A9 *((volatile unsigned int*)(0x42C80CA4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A10 *((volatile unsigned int*)(0x42C80CA8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A11 *((volatile unsigned int*)(0x42C80CACUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A12 *((volatile unsigned int*)(0x42C80CB0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A13 *((volatile unsigned int*)(0x42C80CB4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A14 *((volatile unsigned int*)(0x42C80CB8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A15 *((volatile unsigned int*)(0x42C80CBCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A16 *((volatile unsigned int*)(0x42C80CC0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A17 *((volatile unsigned int*)(0x42C80CC4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A18 *((volatile unsigned int*)(0x42C80CC8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A19 *((volatile unsigned int*)(0x42C80CCCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A20 *((volatile unsigned int*)(0x42C80CD0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A21 *((volatile unsigned int*)(0x42C80CD4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A22 *((volatile unsigned int*)(0x42C80CD8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A23 *((volatile unsigned int*)(0x42C80CDCUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A24 *((volatile unsigned int*)(0x42C80CE0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A25 *((volatile unsigned int*)(0x42C80CE4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A26 *((volatile unsigned int*)(0x42C80CE8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A27 *((volatile unsigned int*)(0x42C80CECUL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A28 *((volatile unsigned int*)(0x42C80CF0UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A29 *((volatile unsigned int*)(0x42C80CF4UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A30 *((volatile unsigned int*)(0x42C80CF8UL)) -#define bFM3_ETHERNET_MAC0_MAR4L_A31 *((volatile unsigned int*)(0x42C80CFCUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A32 *((volatile unsigned int*)(0x42C80D00UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A33 *((volatile unsigned int*)(0x42C80D04UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A34 *((volatile unsigned int*)(0x42C80D08UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A35 *((volatile unsigned int*)(0x42C80D0CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A36 *((volatile unsigned int*)(0x42C80D10UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A37 *((volatile unsigned int*)(0x42C80D14UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A38 *((volatile unsigned int*)(0x42C80D18UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A39 *((volatile unsigned int*)(0x42C80D1CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A40 *((volatile unsigned int*)(0x42C80D20UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A41 *((volatile unsigned int*)(0x42C80D24UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A42 *((volatile unsigned int*)(0x42C80D28UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A43 *((volatile unsigned int*)(0x42C80D2CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A44 *((volatile unsigned int*)(0x42C80D30UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A45 *((volatile unsigned int*)(0x42C80D34UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A46 *((volatile unsigned int*)(0x42C80D38UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_A47 *((volatile unsigned int*)(0x42C80D3CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC0 *((volatile unsigned int*)(0x42C80D60UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC1 *((volatile unsigned int*)(0x42C80D64UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC2 *((volatile unsigned int*)(0x42C80D68UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC3 *((volatile unsigned int*)(0x42C80D6CUL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC4 *((volatile unsigned int*)(0x42C80D70UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_MBC5 *((volatile unsigned int*)(0x42C80D74UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_SA *((volatile unsigned int*)(0x42C80D78UL)) -#define bFM3_ETHERNET_MAC0_MAR5H_AE *((volatile unsigned int*)(0x42C80D7CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A0 *((volatile unsigned int*)(0x42C80D80UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A1 *((volatile unsigned int*)(0x42C80D84UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A2 *((volatile unsigned int*)(0x42C80D88UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A3 *((volatile unsigned int*)(0x42C80D8CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A4 *((volatile unsigned int*)(0x42C80D90UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A5 *((volatile unsigned int*)(0x42C80D94UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A6 *((volatile unsigned int*)(0x42C80D98UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A7 *((volatile unsigned int*)(0x42C80D9CUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A8 *((volatile unsigned int*)(0x42C80DA0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A9 *((volatile unsigned int*)(0x42C80DA4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A10 *((volatile unsigned int*)(0x42C80DA8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A11 *((volatile unsigned int*)(0x42C80DACUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A12 *((volatile unsigned int*)(0x42C80DB0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A13 *((volatile unsigned int*)(0x42C80DB4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A14 *((volatile unsigned int*)(0x42C80DB8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A15 *((volatile unsigned int*)(0x42C80DBCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A16 *((volatile unsigned int*)(0x42C80DC0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A17 *((volatile unsigned int*)(0x42C80DC4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A18 *((volatile unsigned int*)(0x42C80DC8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A19 *((volatile unsigned int*)(0x42C80DCCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A20 *((volatile unsigned int*)(0x42C80DD0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A21 *((volatile unsigned int*)(0x42C80DD4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A22 *((volatile unsigned int*)(0x42C80DD8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A23 *((volatile unsigned int*)(0x42C80DDCUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A24 *((volatile unsigned int*)(0x42C80DE0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A25 *((volatile unsigned int*)(0x42C80DE4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A26 *((volatile unsigned int*)(0x42C80DE8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A27 *((volatile unsigned int*)(0x42C80DECUL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A28 *((volatile unsigned int*)(0x42C80DF0UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A29 *((volatile unsigned int*)(0x42C80DF4UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A30 *((volatile unsigned int*)(0x42C80DF8UL)) -#define bFM3_ETHERNET_MAC0_MAR5L_A31 *((volatile unsigned int*)(0x42C80DFCUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A32 *((volatile unsigned int*)(0x42C80E00UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A33 *((volatile unsigned int*)(0x42C80E04UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A34 *((volatile unsigned int*)(0x42C80E08UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A35 *((volatile unsigned int*)(0x42C80E0CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A36 *((volatile unsigned int*)(0x42C80E10UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A37 *((volatile unsigned int*)(0x42C80E14UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A38 *((volatile unsigned int*)(0x42C80E18UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A39 *((volatile unsigned int*)(0x42C80E1CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A40 *((volatile unsigned int*)(0x42C80E20UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A41 *((volatile unsigned int*)(0x42C80E24UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A42 *((volatile unsigned int*)(0x42C80E28UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A43 *((volatile unsigned int*)(0x42C80E2CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A44 *((volatile unsigned int*)(0x42C80E30UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A45 *((volatile unsigned int*)(0x42C80E34UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A46 *((volatile unsigned int*)(0x42C80E38UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_A47 *((volatile unsigned int*)(0x42C80E3CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC0 *((volatile unsigned int*)(0x42C80E60UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC1 *((volatile unsigned int*)(0x42C80E64UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC2 *((volatile unsigned int*)(0x42C80E68UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC3 *((volatile unsigned int*)(0x42C80E6CUL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC4 *((volatile unsigned int*)(0x42C80E70UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_MBC5 *((volatile unsigned int*)(0x42C80E74UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_SA *((volatile unsigned int*)(0x42C80E78UL)) -#define bFM3_ETHERNET_MAC0_MAR6H_AE *((volatile unsigned int*)(0x42C80E7CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A0 *((volatile unsigned int*)(0x42C80E80UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A1 *((volatile unsigned int*)(0x42C80E84UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A2 *((volatile unsigned int*)(0x42C80E88UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A3 *((volatile unsigned int*)(0x42C80E8CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A4 *((volatile unsigned int*)(0x42C80E90UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A5 *((volatile unsigned int*)(0x42C80E94UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A6 *((volatile unsigned int*)(0x42C80E98UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A7 *((volatile unsigned int*)(0x42C80E9CUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A8 *((volatile unsigned int*)(0x42C80EA0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A9 *((volatile unsigned int*)(0x42C80EA4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A10 *((volatile unsigned int*)(0x42C80EA8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A11 *((volatile unsigned int*)(0x42C80EACUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A12 *((volatile unsigned int*)(0x42C80EB0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A13 *((volatile unsigned int*)(0x42C80EB4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A14 *((volatile unsigned int*)(0x42C80EB8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A15 *((volatile unsigned int*)(0x42C80EBCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A16 *((volatile unsigned int*)(0x42C80EC0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A17 *((volatile unsigned int*)(0x42C80EC4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A18 *((volatile unsigned int*)(0x42C80EC8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A19 *((volatile unsigned int*)(0x42C80ECCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A20 *((volatile unsigned int*)(0x42C80ED0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A21 *((volatile unsigned int*)(0x42C80ED4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A22 *((volatile unsigned int*)(0x42C80ED8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A23 *((volatile unsigned int*)(0x42C80EDCUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A24 *((volatile unsigned int*)(0x42C80EE0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A25 *((volatile unsigned int*)(0x42C80EE4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A26 *((volatile unsigned int*)(0x42C80EE8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A27 *((volatile unsigned int*)(0x42C80EECUL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A28 *((volatile unsigned int*)(0x42C80EF0UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A29 *((volatile unsigned int*)(0x42C80EF4UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A30 *((volatile unsigned int*)(0x42C80EF8UL)) -#define bFM3_ETHERNET_MAC0_MAR6L_A31 *((volatile unsigned int*)(0x42C80EFCUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A32 *((volatile unsigned int*)(0x42C80F00UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A33 *((volatile unsigned int*)(0x42C80F04UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A34 *((volatile unsigned int*)(0x42C80F08UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A35 *((volatile unsigned int*)(0x42C80F0CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A36 *((volatile unsigned int*)(0x42C80F10UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A37 *((volatile unsigned int*)(0x42C80F14UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A38 *((volatile unsigned int*)(0x42C80F18UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A39 *((volatile unsigned int*)(0x42C80F1CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A40 *((volatile unsigned int*)(0x42C80F20UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A41 *((volatile unsigned int*)(0x42C80F24UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A42 *((volatile unsigned int*)(0x42C80F28UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A43 *((volatile unsigned int*)(0x42C80F2CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A44 *((volatile unsigned int*)(0x42C80F30UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A45 *((volatile unsigned int*)(0x42C80F34UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A46 *((volatile unsigned int*)(0x42C80F38UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_A47 *((volatile unsigned int*)(0x42C80F3CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC0 *((volatile unsigned int*)(0x42C80F60UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC1 *((volatile unsigned int*)(0x42C80F64UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC2 *((volatile unsigned int*)(0x42C80F68UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC3 *((volatile unsigned int*)(0x42C80F6CUL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC4 *((volatile unsigned int*)(0x42C80F70UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_MBC5 *((volatile unsigned int*)(0x42C80F74UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_SA *((volatile unsigned int*)(0x42C80F78UL)) -#define bFM3_ETHERNET_MAC0_MAR7H_AE *((volatile unsigned int*)(0x42C80F7CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A0 *((volatile unsigned int*)(0x42C80F80UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A1 *((volatile unsigned int*)(0x42C80F84UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A2 *((volatile unsigned int*)(0x42C80F88UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A3 *((volatile unsigned int*)(0x42C80F8CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A4 *((volatile unsigned int*)(0x42C80F90UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A5 *((volatile unsigned int*)(0x42C80F94UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A6 *((volatile unsigned int*)(0x42C80F98UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A7 *((volatile unsigned int*)(0x42C80F9CUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A8 *((volatile unsigned int*)(0x42C80FA0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A9 *((volatile unsigned int*)(0x42C80FA4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A10 *((volatile unsigned int*)(0x42C80FA8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A11 *((volatile unsigned int*)(0x42C80FACUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A12 *((volatile unsigned int*)(0x42C80FB0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A13 *((volatile unsigned int*)(0x42C80FB4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A14 *((volatile unsigned int*)(0x42C80FB8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A15 *((volatile unsigned int*)(0x42C80FBCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A16 *((volatile unsigned int*)(0x42C80FC0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A17 *((volatile unsigned int*)(0x42C80FC4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A18 *((volatile unsigned int*)(0x42C80FC8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A19 *((volatile unsigned int*)(0x42C80FCCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A20 *((volatile unsigned int*)(0x42C80FD0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A21 *((volatile unsigned int*)(0x42C80FD4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A22 *((volatile unsigned int*)(0x42C80FD8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A23 *((volatile unsigned int*)(0x42C80FDCUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A24 *((volatile unsigned int*)(0x42C80FE0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A25 *((volatile unsigned int*)(0x42C80FE4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A26 *((volatile unsigned int*)(0x42C80FE8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A27 *((volatile unsigned int*)(0x42C80FECUL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A28 *((volatile unsigned int*)(0x42C80FF0UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A29 *((volatile unsigned int*)(0x42C80FF4UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A30 *((volatile unsigned int*)(0x42C80FF8UL)) -#define bFM3_ETHERNET_MAC0_MAR7L_A31 *((volatile unsigned int*)(0x42C80FFCUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A32 *((volatile unsigned int*)(0x42C81000UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A33 *((volatile unsigned int*)(0x42C81004UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A34 *((volatile unsigned int*)(0x42C81008UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A35 *((volatile unsigned int*)(0x42C8100CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A36 *((volatile unsigned int*)(0x42C81010UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A37 *((volatile unsigned int*)(0x42C81014UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A38 *((volatile unsigned int*)(0x42C81018UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A39 *((volatile unsigned int*)(0x42C8101CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A40 *((volatile unsigned int*)(0x42C81020UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A41 *((volatile unsigned int*)(0x42C81024UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A42 *((volatile unsigned int*)(0x42C81028UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A43 *((volatile unsigned int*)(0x42C8102CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A44 *((volatile unsigned int*)(0x42C81030UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A45 *((volatile unsigned int*)(0x42C81034UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A46 *((volatile unsigned int*)(0x42C81038UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_A47 *((volatile unsigned int*)(0x42C8103CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC0 *((volatile unsigned int*)(0x42C81060UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC1 *((volatile unsigned int*)(0x42C81064UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC2 *((volatile unsigned int*)(0x42C81068UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC3 *((volatile unsigned int*)(0x42C8106CUL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC4 *((volatile unsigned int*)(0x42C81070UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_MBC5 *((volatile unsigned int*)(0x42C81074UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_SA *((volatile unsigned int*)(0x42C81078UL)) -#define bFM3_ETHERNET_MAC0_MAR8H_AE *((volatile unsigned int*)(0x42C8107CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A0 *((volatile unsigned int*)(0x42C81080UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A1 *((volatile unsigned int*)(0x42C81084UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A2 *((volatile unsigned int*)(0x42C81088UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A3 *((volatile unsigned int*)(0x42C8108CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A4 *((volatile unsigned int*)(0x42C81090UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A5 *((volatile unsigned int*)(0x42C81094UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A6 *((volatile unsigned int*)(0x42C81098UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A7 *((volatile unsigned int*)(0x42C8109CUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A8 *((volatile unsigned int*)(0x42C810A0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A9 *((volatile unsigned int*)(0x42C810A4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A10 *((volatile unsigned int*)(0x42C810A8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A11 *((volatile unsigned int*)(0x42C810ACUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A12 *((volatile unsigned int*)(0x42C810B0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A13 *((volatile unsigned int*)(0x42C810B4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A14 *((volatile unsigned int*)(0x42C810B8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A15 *((volatile unsigned int*)(0x42C810BCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A16 *((volatile unsigned int*)(0x42C810C0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A17 *((volatile unsigned int*)(0x42C810C4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A18 *((volatile unsigned int*)(0x42C810C8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A19 *((volatile unsigned int*)(0x42C810CCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A20 *((volatile unsigned int*)(0x42C810D0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A21 *((volatile unsigned int*)(0x42C810D4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A22 *((volatile unsigned int*)(0x42C810D8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A23 *((volatile unsigned int*)(0x42C810DCUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A24 *((volatile unsigned int*)(0x42C810E0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A25 *((volatile unsigned int*)(0x42C810E4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A26 *((volatile unsigned int*)(0x42C810E8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A27 *((volatile unsigned int*)(0x42C810ECUL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A28 *((volatile unsigned int*)(0x42C810F0UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A29 *((volatile unsigned int*)(0x42C810F4UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A30 *((volatile unsigned int*)(0x42C810F8UL)) -#define bFM3_ETHERNET_MAC0_MAR8L_A31 *((volatile unsigned int*)(0x42C810FCUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A32 *((volatile unsigned int*)(0x42C81100UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A33 *((volatile unsigned int*)(0x42C81104UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A34 *((volatile unsigned int*)(0x42C81108UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A35 *((volatile unsigned int*)(0x42C8110CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A36 *((volatile unsigned int*)(0x42C81110UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A37 *((volatile unsigned int*)(0x42C81114UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A38 *((volatile unsigned int*)(0x42C81118UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A39 *((volatile unsigned int*)(0x42C8111CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A40 *((volatile unsigned int*)(0x42C81120UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A41 *((volatile unsigned int*)(0x42C81124UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A42 *((volatile unsigned int*)(0x42C81128UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A43 *((volatile unsigned int*)(0x42C8112CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A44 *((volatile unsigned int*)(0x42C81130UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A45 *((volatile unsigned int*)(0x42C81134UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A46 *((volatile unsigned int*)(0x42C81138UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_A47 *((volatile unsigned int*)(0x42C8113CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC0 *((volatile unsigned int*)(0x42C81160UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC1 *((volatile unsigned int*)(0x42C81164UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC2 *((volatile unsigned int*)(0x42C81168UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC3 *((volatile unsigned int*)(0x42C8116CUL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC4 *((volatile unsigned int*)(0x42C81170UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_MBC5 *((volatile unsigned int*)(0x42C81174UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_SA *((volatile unsigned int*)(0x42C81178UL)) -#define bFM3_ETHERNET_MAC0_MAR9H_AE *((volatile unsigned int*)(0x42C8117CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A0 *((volatile unsigned int*)(0x42C81180UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A1 *((volatile unsigned int*)(0x42C81184UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A2 *((volatile unsigned int*)(0x42C81188UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A3 *((volatile unsigned int*)(0x42C8118CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A4 *((volatile unsigned int*)(0x42C81190UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A5 *((volatile unsigned int*)(0x42C81194UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A6 *((volatile unsigned int*)(0x42C81198UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A7 *((volatile unsigned int*)(0x42C8119CUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A8 *((volatile unsigned int*)(0x42C811A0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A9 *((volatile unsigned int*)(0x42C811A4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A10 *((volatile unsigned int*)(0x42C811A8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A11 *((volatile unsigned int*)(0x42C811ACUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A12 *((volatile unsigned int*)(0x42C811B0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A13 *((volatile unsigned int*)(0x42C811B4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A14 *((volatile unsigned int*)(0x42C811B8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A15 *((volatile unsigned int*)(0x42C811BCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A16 *((volatile unsigned int*)(0x42C811C0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A17 *((volatile unsigned int*)(0x42C811C4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A18 *((volatile unsigned int*)(0x42C811C8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A19 *((volatile unsigned int*)(0x42C811CCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A20 *((volatile unsigned int*)(0x42C811D0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A21 *((volatile unsigned int*)(0x42C811D4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A22 *((volatile unsigned int*)(0x42C811D8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A23 *((volatile unsigned int*)(0x42C811DCUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A24 *((volatile unsigned int*)(0x42C811E0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A25 *((volatile unsigned int*)(0x42C811E4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A26 *((volatile unsigned int*)(0x42C811E8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A27 *((volatile unsigned int*)(0x42C811ECUL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A28 *((volatile unsigned int*)(0x42C811F0UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A29 *((volatile unsigned int*)(0x42C811F4UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A30 *((volatile unsigned int*)(0x42C811F8UL)) -#define bFM3_ETHERNET_MAC0_MAR9L_A31 *((volatile unsigned int*)(0x42C811FCUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A32 *((volatile unsigned int*)(0x42C81200UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A33 *((volatile unsigned int*)(0x42C81204UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A34 *((volatile unsigned int*)(0x42C81208UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A35 *((volatile unsigned int*)(0x42C8120CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A36 *((volatile unsigned int*)(0x42C81210UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A37 *((volatile unsigned int*)(0x42C81214UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A38 *((volatile unsigned int*)(0x42C81218UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A39 *((volatile unsigned int*)(0x42C8121CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A40 *((volatile unsigned int*)(0x42C81220UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A41 *((volatile unsigned int*)(0x42C81224UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A42 *((volatile unsigned int*)(0x42C81228UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A43 *((volatile unsigned int*)(0x42C8122CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A44 *((volatile unsigned int*)(0x42C81230UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A45 *((volatile unsigned int*)(0x42C81234UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A46 *((volatile unsigned int*)(0x42C81238UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_A47 *((volatile unsigned int*)(0x42C8123CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC0 *((volatile unsigned int*)(0x42C81260UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC1 *((volatile unsigned int*)(0x42C81264UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC2 *((volatile unsigned int*)(0x42C81268UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC3 *((volatile unsigned int*)(0x42C8126CUL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC4 *((volatile unsigned int*)(0x42C81270UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_MBC5 *((volatile unsigned int*)(0x42C81274UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_SA *((volatile unsigned int*)(0x42C81278UL)) -#define bFM3_ETHERNET_MAC0_MAR10H_AE *((volatile unsigned int*)(0x42C8127CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A0 *((volatile unsigned int*)(0x42C81280UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A1 *((volatile unsigned int*)(0x42C81284UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A2 *((volatile unsigned int*)(0x42C81288UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A3 *((volatile unsigned int*)(0x42C8128CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A4 *((volatile unsigned int*)(0x42C81290UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A5 *((volatile unsigned int*)(0x42C81294UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A6 *((volatile unsigned int*)(0x42C81298UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A7 *((volatile unsigned int*)(0x42C8129CUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A8 *((volatile unsigned int*)(0x42C812A0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A9 *((volatile unsigned int*)(0x42C812A4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A10 *((volatile unsigned int*)(0x42C812A8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A11 *((volatile unsigned int*)(0x42C812ACUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A12 *((volatile unsigned int*)(0x42C812B0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A13 *((volatile unsigned int*)(0x42C812B4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A14 *((volatile unsigned int*)(0x42C812B8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A15 *((volatile unsigned int*)(0x42C812BCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A16 *((volatile unsigned int*)(0x42C812C0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A17 *((volatile unsigned int*)(0x42C812C4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A18 *((volatile unsigned int*)(0x42C812C8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A19 *((volatile unsigned int*)(0x42C812CCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A20 *((volatile unsigned int*)(0x42C812D0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A21 *((volatile unsigned int*)(0x42C812D4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A22 *((volatile unsigned int*)(0x42C812D8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A23 *((volatile unsigned int*)(0x42C812DCUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A24 *((volatile unsigned int*)(0x42C812E0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A25 *((volatile unsigned int*)(0x42C812E4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A26 *((volatile unsigned int*)(0x42C812E8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A27 *((volatile unsigned int*)(0x42C812ECUL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A28 *((volatile unsigned int*)(0x42C812F0UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A29 *((volatile unsigned int*)(0x42C812F4UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A30 *((volatile unsigned int*)(0x42C812F8UL)) -#define bFM3_ETHERNET_MAC0_MAR10L_A31 *((volatile unsigned int*)(0x42C812FCUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A32 *((volatile unsigned int*)(0x42C81300UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A33 *((volatile unsigned int*)(0x42C81304UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A34 *((volatile unsigned int*)(0x42C81308UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A35 *((volatile unsigned int*)(0x42C8130CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A36 *((volatile unsigned int*)(0x42C81310UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A37 *((volatile unsigned int*)(0x42C81314UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A38 *((volatile unsigned int*)(0x42C81318UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A39 *((volatile unsigned int*)(0x42C8131CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A40 *((volatile unsigned int*)(0x42C81320UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A41 *((volatile unsigned int*)(0x42C81324UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A42 *((volatile unsigned int*)(0x42C81328UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A43 *((volatile unsigned int*)(0x42C8132CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A44 *((volatile unsigned int*)(0x42C81330UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A45 *((volatile unsigned int*)(0x42C81334UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A46 *((volatile unsigned int*)(0x42C81338UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_A47 *((volatile unsigned int*)(0x42C8133CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC0 *((volatile unsigned int*)(0x42C81360UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC1 *((volatile unsigned int*)(0x42C81364UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC2 *((volatile unsigned int*)(0x42C81368UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC3 *((volatile unsigned int*)(0x42C8136CUL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC4 *((volatile unsigned int*)(0x42C81370UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_MBC5 *((volatile unsigned int*)(0x42C81374UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_SA *((volatile unsigned int*)(0x42C81378UL)) -#define bFM3_ETHERNET_MAC0_MAR11H_AE *((volatile unsigned int*)(0x42C8137CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A0 *((volatile unsigned int*)(0x42C81380UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A1 *((volatile unsigned int*)(0x42C81384UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A2 *((volatile unsigned int*)(0x42C81388UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A3 *((volatile unsigned int*)(0x42C8138CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A4 *((volatile unsigned int*)(0x42C81390UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A5 *((volatile unsigned int*)(0x42C81394UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A6 *((volatile unsigned int*)(0x42C81398UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A7 *((volatile unsigned int*)(0x42C8139CUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A8 *((volatile unsigned int*)(0x42C813A0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A9 *((volatile unsigned int*)(0x42C813A4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A10 *((volatile unsigned int*)(0x42C813A8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A11 *((volatile unsigned int*)(0x42C813ACUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A12 *((volatile unsigned int*)(0x42C813B0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A13 *((volatile unsigned int*)(0x42C813B4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A14 *((volatile unsigned int*)(0x42C813B8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A15 *((volatile unsigned int*)(0x42C813BCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A16 *((volatile unsigned int*)(0x42C813C0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A17 *((volatile unsigned int*)(0x42C813C4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A18 *((volatile unsigned int*)(0x42C813C8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A19 *((volatile unsigned int*)(0x42C813CCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A20 *((volatile unsigned int*)(0x42C813D0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A21 *((volatile unsigned int*)(0x42C813D4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A22 *((volatile unsigned int*)(0x42C813D8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A23 *((volatile unsigned int*)(0x42C813DCUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A24 *((volatile unsigned int*)(0x42C813E0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A25 *((volatile unsigned int*)(0x42C813E4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A26 *((volatile unsigned int*)(0x42C813E8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A27 *((volatile unsigned int*)(0x42C813ECUL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A28 *((volatile unsigned int*)(0x42C813F0UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A29 *((volatile unsigned int*)(0x42C813F4UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A30 *((volatile unsigned int*)(0x42C813F8UL)) -#define bFM3_ETHERNET_MAC0_MAR11L_A31 *((volatile unsigned int*)(0x42C813FCUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A32 *((volatile unsigned int*)(0x42C81400UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A33 *((volatile unsigned int*)(0x42C81404UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A34 *((volatile unsigned int*)(0x42C81408UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A35 *((volatile unsigned int*)(0x42C8140CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A36 *((volatile unsigned int*)(0x42C81410UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A37 *((volatile unsigned int*)(0x42C81414UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A38 *((volatile unsigned int*)(0x42C81418UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A39 *((volatile unsigned int*)(0x42C8141CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A40 *((volatile unsigned int*)(0x42C81420UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A41 *((volatile unsigned int*)(0x42C81424UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A42 *((volatile unsigned int*)(0x42C81428UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A43 *((volatile unsigned int*)(0x42C8142CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A44 *((volatile unsigned int*)(0x42C81430UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A45 *((volatile unsigned int*)(0x42C81434UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A46 *((volatile unsigned int*)(0x42C81438UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_A47 *((volatile unsigned int*)(0x42C8143CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC0 *((volatile unsigned int*)(0x42C81460UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC1 *((volatile unsigned int*)(0x42C81464UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC2 *((volatile unsigned int*)(0x42C81468UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC3 *((volatile unsigned int*)(0x42C8146CUL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC4 *((volatile unsigned int*)(0x42C81470UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_MBC5 *((volatile unsigned int*)(0x42C81474UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_SA *((volatile unsigned int*)(0x42C81478UL)) -#define bFM3_ETHERNET_MAC0_MAR12H_AE *((volatile unsigned int*)(0x42C8147CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A0 *((volatile unsigned int*)(0x42C81480UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A1 *((volatile unsigned int*)(0x42C81484UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A2 *((volatile unsigned int*)(0x42C81488UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A3 *((volatile unsigned int*)(0x42C8148CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A4 *((volatile unsigned int*)(0x42C81490UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A5 *((volatile unsigned int*)(0x42C81494UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A6 *((volatile unsigned int*)(0x42C81498UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A7 *((volatile unsigned int*)(0x42C8149CUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A8 *((volatile unsigned int*)(0x42C814A0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A9 *((volatile unsigned int*)(0x42C814A4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A10 *((volatile unsigned int*)(0x42C814A8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A11 *((volatile unsigned int*)(0x42C814ACUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A12 *((volatile unsigned int*)(0x42C814B0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A13 *((volatile unsigned int*)(0x42C814B4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A14 *((volatile unsigned int*)(0x42C814B8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A15 *((volatile unsigned int*)(0x42C814BCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A16 *((volatile unsigned int*)(0x42C814C0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A17 *((volatile unsigned int*)(0x42C814C4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A18 *((volatile unsigned int*)(0x42C814C8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A19 *((volatile unsigned int*)(0x42C814CCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A20 *((volatile unsigned int*)(0x42C814D0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A21 *((volatile unsigned int*)(0x42C814D4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A22 *((volatile unsigned int*)(0x42C814D8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A23 *((volatile unsigned int*)(0x42C814DCUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A24 *((volatile unsigned int*)(0x42C814E0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A25 *((volatile unsigned int*)(0x42C814E4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A26 *((volatile unsigned int*)(0x42C814E8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A27 *((volatile unsigned int*)(0x42C814ECUL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A28 *((volatile unsigned int*)(0x42C814F0UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A29 *((volatile unsigned int*)(0x42C814F4UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A30 *((volatile unsigned int*)(0x42C814F8UL)) -#define bFM3_ETHERNET_MAC0_MAR12L_A31 *((volatile unsigned int*)(0x42C814FCUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A32 *((volatile unsigned int*)(0x42C81500UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A33 *((volatile unsigned int*)(0x42C81504UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A34 *((volatile unsigned int*)(0x42C81508UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A35 *((volatile unsigned int*)(0x42C8150CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A36 *((volatile unsigned int*)(0x42C81510UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A37 *((volatile unsigned int*)(0x42C81514UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A38 *((volatile unsigned int*)(0x42C81518UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A39 *((volatile unsigned int*)(0x42C8151CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A40 *((volatile unsigned int*)(0x42C81520UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A41 *((volatile unsigned int*)(0x42C81524UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A42 *((volatile unsigned int*)(0x42C81528UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A43 *((volatile unsigned int*)(0x42C8152CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A44 *((volatile unsigned int*)(0x42C81530UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A45 *((volatile unsigned int*)(0x42C81534UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A46 *((volatile unsigned int*)(0x42C81538UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_A47 *((volatile unsigned int*)(0x42C8153CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC0 *((volatile unsigned int*)(0x42C81560UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC1 *((volatile unsigned int*)(0x42C81564UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC2 *((volatile unsigned int*)(0x42C81568UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC3 *((volatile unsigned int*)(0x42C8156CUL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC4 *((volatile unsigned int*)(0x42C81570UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_MBC5 *((volatile unsigned int*)(0x42C81574UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_SA *((volatile unsigned int*)(0x42C81578UL)) -#define bFM3_ETHERNET_MAC0_MAR13H_AE *((volatile unsigned int*)(0x42C8157CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A0 *((volatile unsigned int*)(0x42C81580UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A1 *((volatile unsigned int*)(0x42C81584UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A2 *((volatile unsigned int*)(0x42C81588UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A3 *((volatile unsigned int*)(0x42C8158CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A4 *((volatile unsigned int*)(0x42C81590UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A5 *((volatile unsigned int*)(0x42C81594UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A6 *((volatile unsigned int*)(0x42C81598UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A7 *((volatile unsigned int*)(0x42C8159CUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A8 *((volatile unsigned int*)(0x42C815A0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A9 *((volatile unsigned int*)(0x42C815A4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A10 *((volatile unsigned int*)(0x42C815A8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A11 *((volatile unsigned int*)(0x42C815ACUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A12 *((volatile unsigned int*)(0x42C815B0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A13 *((volatile unsigned int*)(0x42C815B4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A14 *((volatile unsigned int*)(0x42C815B8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A15 *((volatile unsigned int*)(0x42C815BCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A16 *((volatile unsigned int*)(0x42C815C0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A17 *((volatile unsigned int*)(0x42C815C4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A18 *((volatile unsigned int*)(0x42C815C8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A19 *((volatile unsigned int*)(0x42C815CCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A20 *((volatile unsigned int*)(0x42C815D0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A21 *((volatile unsigned int*)(0x42C815D4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A22 *((volatile unsigned int*)(0x42C815D8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A23 *((volatile unsigned int*)(0x42C815DCUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A24 *((volatile unsigned int*)(0x42C815E0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A25 *((volatile unsigned int*)(0x42C815E4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A26 *((volatile unsigned int*)(0x42C815E8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A27 *((volatile unsigned int*)(0x42C815ECUL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A28 *((volatile unsigned int*)(0x42C815F0UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A29 *((volatile unsigned int*)(0x42C815F4UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A30 *((volatile unsigned int*)(0x42C815F8UL)) -#define bFM3_ETHERNET_MAC0_MAR13L_A31 *((volatile unsigned int*)(0x42C815FCUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A32 *((volatile unsigned int*)(0x42C81600UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A33 *((volatile unsigned int*)(0x42C81604UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A34 *((volatile unsigned int*)(0x42C81608UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A35 *((volatile unsigned int*)(0x42C8160CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A36 *((volatile unsigned int*)(0x42C81610UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A37 *((volatile unsigned int*)(0x42C81614UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A38 *((volatile unsigned int*)(0x42C81618UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A39 *((volatile unsigned int*)(0x42C8161CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A40 *((volatile unsigned int*)(0x42C81620UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A41 *((volatile unsigned int*)(0x42C81624UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A42 *((volatile unsigned int*)(0x42C81628UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A43 *((volatile unsigned int*)(0x42C8162CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A44 *((volatile unsigned int*)(0x42C81630UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A45 *((volatile unsigned int*)(0x42C81634UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A46 *((volatile unsigned int*)(0x42C81638UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_A47 *((volatile unsigned int*)(0x42C8163CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC0 *((volatile unsigned int*)(0x42C81660UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC1 *((volatile unsigned int*)(0x42C81664UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC2 *((volatile unsigned int*)(0x42C81668UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC3 *((volatile unsigned int*)(0x42C8166CUL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC4 *((volatile unsigned int*)(0x42C81670UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_MBC5 *((volatile unsigned int*)(0x42C81674UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_SA *((volatile unsigned int*)(0x42C81678UL)) -#define bFM3_ETHERNET_MAC0_MAR14H_AE *((volatile unsigned int*)(0x42C8167CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A0 *((volatile unsigned int*)(0x42C81680UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A1 *((volatile unsigned int*)(0x42C81684UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A2 *((volatile unsigned int*)(0x42C81688UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A3 *((volatile unsigned int*)(0x42C8168CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A4 *((volatile unsigned int*)(0x42C81690UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A5 *((volatile unsigned int*)(0x42C81694UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A6 *((volatile unsigned int*)(0x42C81698UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A7 *((volatile unsigned int*)(0x42C8169CUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A8 *((volatile unsigned int*)(0x42C816A0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A9 *((volatile unsigned int*)(0x42C816A4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A10 *((volatile unsigned int*)(0x42C816A8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A11 *((volatile unsigned int*)(0x42C816ACUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A12 *((volatile unsigned int*)(0x42C816B0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A13 *((volatile unsigned int*)(0x42C816B4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A14 *((volatile unsigned int*)(0x42C816B8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A15 *((volatile unsigned int*)(0x42C816BCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A16 *((volatile unsigned int*)(0x42C816C0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A17 *((volatile unsigned int*)(0x42C816C4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A18 *((volatile unsigned int*)(0x42C816C8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A19 *((volatile unsigned int*)(0x42C816CCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A20 *((volatile unsigned int*)(0x42C816D0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A21 *((volatile unsigned int*)(0x42C816D4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A22 *((volatile unsigned int*)(0x42C816D8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A23 *((volatile unsigned int*)(0x42C816DCUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A24 *((volatile unsigned int*)(0x42C816E0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A25 *((volatile unsigned int*)(0x42C816E4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A26 *((volatile unsigned int*)(0x42C816E8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A27 *((volatile unsigned int*)(0x42C816ECUL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A28 *((volatile unsigned int*)(0x42C816F0UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A29 *((volatile unsigned int*)(0x42C816F4UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A30 *((volatile unsigned int*)(0x42C816F8UL)) -#define bFM3_ETHERNET_MAC0_MAR14L_A31 *((volatile unsigned int*)(0x42C816FCUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A32 *((volatile unsigned int*)(0x42C81700UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A33 *((volatile unsigned int*)(0x42C81704UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A34 *((volatile unsigned int*)(0x42C81708UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A35 *((volatile unsigned int*)(0x42C8170CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A36 *((volatile unsigned int*)(0x42C81710UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A37 *((volatile unsigned int*)(0x42C81714UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A38 *((volatile unsigned int*)(0x42C81718UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A39 *((volatile unsigned int*)(0x42C8171CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A40 *((volatile unsigned int*)(0x42C81720UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A41 *((volatile unsigned int*)(0x42C81724UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A42 *((volatile unsigned int*)(0x42C81728UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A43 *((volatile unsigned int*)(0x42C8172CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A44 *((volatile unsigned int*)(0x42C81730UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A45 *((volatile unsigned int*)(0x42C81734UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A46 *((volatile unsigned int*)(0x42C81738UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_A47 *((volatile unsigned int*)(0x42C8173CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC0 *((volatile unsigned int*)(0x42C81760UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC1 *((volatile unsigned int*)(0x42C81764UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC2 *((volatile unsigned int*)(0x42C81768UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC3 *((volatile unsigned int*)(0x42C8176CUL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC4 *((volatile unsigned int*)(0x42C81770UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_MBC5 *((volatile unsigned int*)(0x42C81774UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_SA *((volatile unsigned int*)(0x42C81778UL)) -#define bFM3_ETHERNET_MAC0_MAR15H_AE *((volatile unsigned int*)(0x42C8177CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A0 *((volatile unsigned int*)(0x42C81780UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A1 *((volatile unsigned int*)(0x42C81784UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A2 *((volatile unsigned int*)(0x42C81788UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A3 *((volatile unsigned int*)(0x42C8178CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A4 *((volatile unsigned int*)(0x42C81790UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A5 *((volatile unsigned int*)(0x42C81794UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A6 *((volatile unsigned int*)(0x42C81798UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A7 *((volatile unsigned int*)(0x42C8179CUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A8 *((volatile unsigned int*)(0x42C817A0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A9 *((volatile unsigned int*)(0x42C817A4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A10 *((volatile unsigned int*)(0x42C817A8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A11 *((volatile unsigned int*)(0x42C817ACUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A12 *((volatile unsigned int*)(0x42C817B0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A13 *((volatile unsigned int*)(0x42C817B4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A14 *((volatile unsigned int*)(0x42C817B8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A15 *((volatile unsigned int*)(0x42C817BCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A16 *((volatile unsigned int*)(0x42C817C0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A17 *((volatile unsigned int*)(0x42C817C4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A18 *((volatile unsigned int*)(0x42C817C8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A19 *((volatile unsigned int*)(0x42C817CCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A20 *((volatile unsigned int*)(0x42C817D0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A21 *((volatile unsigned int*)(0x42C817D4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A22 *((volatile unsigned int*)(0x42C817D8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A23 *((volatile unsigned int*)(0x42C817DCUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A24 *((volatile unsigned int*)(0x42C817E0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A25 *((volatile unsigned int*)(0x42C817E4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A26 *((volatile unsigned int*)(0x42C817E8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A27 *((volatile unsigned int*)(0x42C817ECUL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A28 *((volatile unsigned int*)(0x42C817F0UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A29 *((volatile unsigned int*)(0x42C817F4UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A30 *((volatile unsigned int*)(0x42C817F8UL)) -#define bFM3_ETHERNET_MAC0_MAR15L_A31 *((volatile unsigned int*)(0x42C817FCUL)) -#define bFM3_ETHERNET_MAC0_RGSR_LM *((volatile unsigned int*)(0x42C81B00UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LSP0 *((volatile unsigned int*)(0x42C81B04UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LSP1 *((volatile unsigned int*)(0x42C81B08UL)) -#define bFM3_ETHERNET_MAC0_RGSR_LS *((volatile unsigned int*)(0x42C81B0CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSE *((volatile unsigned int*)(0x42C8E000UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TFCU *((volatile unsigned int*)(0x42C8E004UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSI *((volatile unsigned int*)(0x42C8E008UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSU *((volatile unsigned int*)(0x42C8E00CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TITE *((volatile unsigned int*)(0x42C8E010UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TARU *((volatile unsigned int*)(0x42C8E014UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSEA *((volatile unsigned int*)(0x42C8E020UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSDB *((volatile unsigned int*)(0x42C8E024UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSV2E *((volatile unsigned int*)(0x42C8E028UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TETSP *((volatile unsigned int*)(0x42C8E02CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E *((volatile unsigned int*)(0x42C8E030UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E *((volatile unsigned int*)(0x42C8E034UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TETSEM *((volatile unsigned int*)(0x42C8E038UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSMRM *((volatile unsigned int*)(0x42C8E03CUL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSPS0 *((volatile unsigned int*)(0x42C8E040UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSPS1 *((volatile unsigned int*)(0x42C8E044UL)) -#define bFM3_ETHERNET_MAC0_TSCR_TSENMF *((volatile unsigned int*)(0x42C8E048UL)) -#define bFM3_ETHERNET_MAC0_TSCR_ATSFC *((volatile unsigned int*)(0x42C8E060UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC0 *((volatile unsigned int*)(0x42C8E080UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC1 *((volatile unsigned int*)(0x42C8E084UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC2 *((volatile unsigned int*)(0x42C8E088UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC3 *((volatile unsigned int*)(0x42C8E08CUL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC4 *((volatile unsigned int*)(0x42C8E090UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC5 *((volatile unsigned int*)(0x42C8E094UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC6 *((volatile unsigned int*)(0x42C8E098UL)) -#define bFM3_ETHERNET_MAC0_SSIR_SSINC7 *((volatile unsigned int*)(0x42C8E09CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS0 *((volatile unsigned int*)(0x42C8E100UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS1 *((volatile unsigned int*)(0x42C8E104UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS2 *((volatile unsigned int*)(0x42C8E108UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS3 *((volatile unsigned int*)(0x42C8E10CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS4 *((volatile unsigned int*)(0x42C8E110UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS5 *((volatile unsigned int*)(0x42C8E114UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS6 *((volatile unsigned int*)(0x42C8E118UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS7 *((volatile unsigned int*)(0x42C8E11CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS8 *((volatile unsigned int*)(0x42C8E120UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS9 *((volatile unsigned int*)(0x42C8E124UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS10 *((volatile unsigned int*)(0x42C8E128UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS11 *((volatile unsigned int*)(0x42C8E12CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS12 *((volatile unsigned int*)(0x42C8E130UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS13 *((volatile unsigned int*)(0x42C8E134UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS14 *((volatile unsigned int*)(0x42C8E138UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS15 *((volatile unsigned int*)(0x42C8E13CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS16 *((volatile unsigned int*)(0x42C8E140UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS17 *((volatile unsigned int*)(0x42C8E144UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS18 *((volatile unsigned int*)(0x42C8E148UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS19 *((volatile unsigned int*)(0x42C8E14CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS20 *((volatile unsigned int*)(0x42C8E150UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS21 *((volatile unsigned int*)(0x42C8E154UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS22 *((volatile unsigned int*)(0x42C8E158UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS23 *((volatile unsigned int*)(0x42C8E15CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS24 *((volatile unsigned int*)(0x42C8E160UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS25 *((volatile unsigned int*)(0x42C8E164UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS26 *((volatile unsigned int*)(0x42C8E168UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS27 *((volatile unsigned int*)(0x42C8E16CUL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS28 *((volatile unsigned int*)(0x42C8E170UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS29 *((volatile unsigned int*)(0x42C8E174UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS30 *((volatile unsigned int*)(0x42C8E178UL)) -#define bFM3_ETHERNET_MAC0_STSR_TSS31 *((volatile unsigned int*)(0x42C8E17CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS0 *((volatile unsigned int*)(0x42C8E080UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS1 *((volatile unsigned int*)(0x42C8E084UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS2 *((volatile unsigned int*)(0x42C8E088UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS3 *((volatile unsigned int*)(0x42C8E08CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS4 *((volatile unsigned int*)(0x42C8E090UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS5 *((volatile unsigned int*)(0x42C8E094UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS6 *((volatile unsigned int*)(0x42C8E098UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS7 *((volatile unsigned int*)(0x42C8E09CUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS8 *((volatile unsigned int*)(0x42C8E0A0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS9 *((volatile unsigned int*)(0x42C8E0A4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS10 *((volatile unsigned int*)(0x42C8E0A8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS11 *((volatile unsigned int*)(0x42C8E0ACUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS12 *((volatile unsigned int*)(0x42C8E0B0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS13 *((volatile unsigned int*)(0x42C8E0B4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS14 *((volatile unsigned int*)(0x42C8E0B8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS15 *((volatile unsigned int*)(0x42C8E0BCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS16 *((volatile unsigned int*)(0x42C8E0C0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS17 *((volatile unsigned int*)(0x42C8E0C4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS18 *((volatile unsigned int*)(0x42C8E0C8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS19 *((volatile unsigned int*)(0x42C8E0CCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS20 *((volatile unsigned int*)(0x42C8E0D0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS21 *((volatile unsigned int*)(0x42C8E0D4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS22 *((volatile unsigned int*)(0x42C8E0D8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS23 *((volatile unsigned int*)(0x42C8E0DCUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS24 *((volatile unsigned int*)(0x42C8E0E0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS25 *((volatile unsigned int*)(0x42C8E0E4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS26 *((volatile unsigned int*)(0x42C8E0E8UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS27 *((volatile unsigned int*)(0x42C8E0ECUL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS28 *((volatile unsigned int*)(0x42C8E0F0UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS29 *((volatile unsigned int*)(0x42C8E0F4UL)) -#define bFM3_ETHERNET_MAC0_STNR_TSSS30 *((volatile unsigned int*)(0x42C8E0F8UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS0 *((volatile unsigned int*)(0x42C8E200UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS1 *((volatile unsigned int*)(0x42C8E204UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS2 *((volatile unsigned int*)(0x42C8E208UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS3 *((volatile unsigned int*)(0x42C8E20CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS4 *((volatile unsigned int*)(0x42C8E210UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS5 *((volatile unsigned int*)(0x42C8E214UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS6 *((volatile unsigned int*)(0x42C8E218UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS7 *((volatile unsigned int*)(0x42C8E21CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS8 *((volatile unsigned int*)(0x42C8E220UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS9 *((volatile unsigned int*)(0x42C8E224UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS10 *((volatile unsigned int*)(0x42C8E228UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS11 *((volatile unsigned int*)(0x42C8E22CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS12 *((volatile unsigned int*)(0x42C8E230UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS13 *((volatile unsigned int*)(0x42C8E234UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS14 *((volatile unsigned int*)(0x42C8E238UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS15 *((volatile unsigned int*)(0x42C8E23CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS16 *((volatile unsigned int*)(0x42C8E240UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS17 *((volatile unsigned int*)(0x42C8E244UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS18 *((volatile unsigned int*)(0x42C8E248UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS19 *((volatile unsigned int*)(0x42C8E24CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS20 *((volatile unsigned int*)(0x42C8E250UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS21 *((volatile unsigned int*)(0x42C8E254UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS22 *((volatile unsigned int*)(0x42C8E258UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS23 *((volatile unsigned int*)(0x42C8E25CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS24 *((volatile unsigned int*)(0x42C8E260UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS25 *((volatile unsigned int*)(0x42C8E264UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS26 *((volatile unsigned int*)(0x42C8E268UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS27 *((volatile unsigned int*)(0x42C8E26CUL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS28 *((volatile unsigned int*)(0x42C8E270UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS29 *((volatile unsigned int*)(0x42C8E274UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS30 *((volatile unsigned int*)(0x42C8E278UL)) -#define bFM3_ETHERNET_MAC0_STSUR_TSS31 *((volatile unsigned int*)(0x42C8E27CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS0 *((volatile unsigned int*)(0x42C8E280UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS1 *((volatile unsigned int*)(0x42C8E284UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS2 *((volatile unsigned int*)(0x42C8E288UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS3 *((volatile unsigned int*)(0x42C8E28CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS4 *((volatile unsigned int*)(0x42C8E290UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS5 *((volatile unsigned int*)(0x42C8E294UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS6 *((volatile unsigned int*)(0x42C8E298UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS7 *((volatile unsigned int*)(0x42C8E29CUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS8 *((volatile unsigned int*)(0x42C8E2A0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS9 *((volatile unsigned int*)(0x42C8E2A4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS10 *((volatile unsigned int*)(0x42C8E2A8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS11 *((volatile unsigned int*)(0x42C8E2ACUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS12 *((volatile unsigned int*)(0x42C8E2B0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS13 *((volatile unsigned int*)(0x42C8E2B4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS14 *((volatile unsigned int*)(0x42C8E2B8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS15 *((volatile unsigned int*)(0x42C8E2BCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS16 *((volatile unsigned int*)(0x42C8E2C0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS17 *((volatile unsigned int*)(0x42C8E2C4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS18 *((volatile unsigned int*)(0x42C8E2C8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS19 *((volatile unsigned int*)(0x42C8E2CCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS20 *((volatile unsigned int*)(0x42C8E2D0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS21 *((volatile unsigned int*)(0x42C8E2D4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS22 *((volatile unsigned int*)(0x42C8E2D8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS23 *((volatile unsigned int*)(0x42C8E2DCUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS24 *((volatile unsigned int*)(0x42C8E2E0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS25 *((volatile unsigned int*)(0x42C8E2E4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS26 *((volatile unsigned int*)(0x42C8E2E8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS27 *((volatile unsigned int*)(0x42C8E2ECUL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS28 *((volatile unsigned int*)(0x42C8E2F0UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS29 *((volatile unsigned int*)(0x42C8E2F4UL)) -#define bFM3_ETHERNET_MAC0_STNUR_TSSS30 *((volatile unsigned int*)(0x42C8E2F8UL)) -#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB *((volatile unsigned int*)(0x42C8E2FCUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR0 *((volatile unsigned int*)(0x42C8E300UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR1 *((volatile unsigned int*)(0x42C8E304UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR2 *((volatile unsigned int*)(0x42C8E308UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR3 *((volatile unsigned int*)(0x42C8E30CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR4 *((volatile unsigned int*)(0x42C8E310UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR5 *((volatile unsigned int*)(0x42C8E314UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR6 *((volatile unsigned int*)(0x42C8E318UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR7 *((volatile unsigned int*)(0x42C8E31CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR8 *((volatile unsigned int*)(0x42C8E320UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR9 *((volatile unsigned int*)(0x42C8E324UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR10 *((volatile unsigned int*)(0x42C8E328UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR11 *((volatile unsigned int*)(0x42C8E32CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR12 *((volatile unsigned int*)(0x42C8E330UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR13 *((volatile unsigned int*)(0x42C8E334UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR14 *((volatile unsigned int*)(0x42C8E338UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR15 *((volatile unsigned int*)(0x42C8E33CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR16 *((volatile unsigned int*)(0x42C8E340UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR17 *((volatile unsigned int*)(0x42C8E344UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR18 *((volatile unsigned int*)(0x42C8E348UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR19 *((volatile unsigned int*)(0x42C8E34CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR20 *((volatile unsigned int*)(0x42C8E350UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR21 *((volatile unsigned int*)(0x42C8E354UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR22 *((volatile unsigned int*)(0x42C8E358UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR23 *((volatile unsigned int*)(0x42C8E35CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR24 *((volatile unsigned int*)(0x42C8E360UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR25 *((volatile unsigned int*)(0x42C8E364UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR26 *((volatile unsigned int*)(0x42C8E368UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR27 *((volatile unsigned int*)(0x42C8E36CUL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR28 *((volatile unsigned int*)(0x42C8E370UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR29 *((volatile unsigned int*)(0x42C8E374UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR30 *((volatile unsigned int*)(0x42C8E378UL)) -#define bFM3_ETHERNET_MAC0_TSAR_TSAR31 *((volatile unsigned int*)(0x42C8E37CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR0 *((volatile unsigned int*)(0x42C8E380UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR1 *((volatile unsigned int*)(0x42C8E384UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR2 *((volatile unsigned int*)(0x42C8E388UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR3 *((volatile unsigned int*)(0x42C8E38CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR4 *((volatile unsigned int*)(0x42C8E390UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR5 *((volatile unsigned int*)(0x42C8E394UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR6 *((volatile unsigned int*)(0x42C8E398UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR7 *((volatile unsigned int*)(0x42C8E39CUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR8 *((volatile unsigned int*)(0x42C8E3A0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR9 *((volatile unsigned int*)(0x42C8E3A4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR10 *((volatile unsigned int*)(0x42C8E3A8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR11 *((volatile unsigned int*)(0x42C8E3ACUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR12 *((volatile unsigned int*)(0x42C8E3B0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR13 *((volatile unsigned int*)(0x42C8E3B4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR14 *((volatile unsigned int*)(0x42C8E3B8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR15 *((volatile unsigned int*)(0x42C8E3BCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR16 *((volatile unsigned int*)(0x42C8E3C0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR17 *((volatile unsigned int*)(0x42C8E3C4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR18 *((volatile unsigned int*)(0x42C8E3C8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR19 *((volatile unsigned int*)(0x42C8E3CCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR20 *((volatile unsigned int*)(0x42C8E3D0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR21 *((volatile unsigned int*)(0x42C8E3D4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR22 *((volatile unsigned int*)(0x42C8E3D8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR23 *((volatile unsigned int*)(0x42C8E3DCUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR24 *((volatile unsigned int*)(0x42C8E3E0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR25 *((volatile unsigned int*)(0x42C8E3E4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR26 *((volatile unsigned int*)(0x42C8E3E8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR27 *((volatile unsigned int*)(0x42C8E3ECUL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR28 *((volatile unsigned int*)(0x42C8E3F0UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR29 *((volatile unsigned int*)(0x42C8E3F4UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR30 *((volatile unsigned int*)(0x42C8E3F8UL)) -#define bFM3_ETHERNET_MAC0_TTSR_TSTR31 *((volatile unsigned int*)(0x42C8E3FCUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR0 *((volatile unsigned int*)(0x42C8E400UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR1 *((volatile unsigned int*)(0x42C8E404UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR2 *((volatile unsigned int*)(0x42C8E408UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR3 *((volatile unsigned int*)(0x42C8E40CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR4 *((volatile unsigned int*)(0x42C8E410UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR5 *((volatile unsigned int*)(0x42C8E414UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR6 *((volatile unsigned int*)(0x42C8E418UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR7 *((volatile unsigned int*)(0x42C8E41CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR8 *((volatile unsigned int*)(0x42C8E420UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR9 *((volatile unsigned int*)(0x42C8E424UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR10 *((volatile unsigned int*)(0x42C8E428UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR11 *((volatile unsigned int*)(0x42C8E42CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR12 *((volatile unsigned int*)(0x42C8E430UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR13 *((volatile unsigned int*)(0x42C8E434UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR14 *((volatile unsigned int*)(0x42C8E438UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR15 *((volatile unsigned int*)(0x42C8E43CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR16 *((volatile unsigned int*)(0x42C8E440UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR17 *((volatile unsigned int*)(0x42C8E444UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR18 *((volatile unsigned int*)(0x42C8E448UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR19 *((volatile unsigned int*)(0x42C8E44CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR20 *((volatile unsigned int*)(0x42C8E450UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR21 *((volatile unsigned int*)(0x42C8E454UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR22 *((volatile unsigned int*)(0x42C8E458UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR23 *((volatile unsigned int*)(0x42C8E45CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR24 *((volatile unsigned int*)(0x42C8E460UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR25 *((volatile unsigned int*)(0x42C8E464UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR26 *((volatile unsigned int*)(0x42C8E468UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR27 *((volatile unsigned int*)(0x42C8E46CUL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR28 *((volatile unsigned int*)(0x42C8E470UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR29 *((volatile unsigned int*)(0x42C8E474UL)) -#define bFM3_ETHERNET_MAC0_TTNR_TSTR30 *((volatile unsigned int*)(0x42C8E478UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42C8E480UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42C8E484UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42C8E488UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42C8E48CUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42C8E490UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42C8E494UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42C8E498UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42C8E49CUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42C8E4A0UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42C8E4A4UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42C8E4A8UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42C8E4ACUL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42C8E4B0UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42C8E4B4UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42C8E4B8UL)) -#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42C8E4BCUL)) -#define bFM3_ETHERNET_MAC0_TSR_TSSOVF *((volatile unsigned int*)(0x42C8E500UL)) -#define bFM3_ETHERNET_MAC0_TSR_TSTART *((volatile unsigned int*)(0x42C8E504UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSTS *((volatile unsigned int*)(0x42C8E508UL)) -#define bFM3_ETHERNET_MAC0_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSSTM *((volatile unsigned int*)(0x42C8E560UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS0 *((volatile unsigned int*)(0x42C8E564UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS1 *((volatile unsigned int*)(0x42C8E568UL)) -#define bFM3_ETHERNET_MAC0_TSR_ATSNS2 *((volatile unsigned int*)(0x42C8E56CUL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42C8E580UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42C8E584UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42C8E588UL)) -#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42C8E58CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN0 *((volatile unsigned int*)(0x42C8E600UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN1 *((volatile unsigned int*)(0x42C8E604UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN2 *((volatile unsigned int*)(0x42C8E608UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN3 *((volatile unsigned int*)(0x42C8E60CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN4 *((volatile unsigned int*)(0x42C8E610UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN5 *((volatile unsigned int*)(0x42C8E614UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN6 *((volatile unsigned int*)(0x42C8E618UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN7 *((volatile unsigned int*)(0x42C8E61CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN8 *((volatile unsigned int*)(0x42C8E620UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN9 *((volatile unsigned int*)(0x42C8E624UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN10 *((volatile unsigned int*)(0x42C8E628UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN11 *((volatile unsigned int*)(0x42C8E62CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN12 *((volatile unsigned int*)(0x42C8E630UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN13 *((volatile unsigned int*)(0x42C8E634UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN14 *((volatile unsigned int*)(0x42C8E638UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN15 *((volatile unsigned int*)(0x42C8E63CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN16 *((volatile unsigned int*)(0x42C8E640UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN17 *((volatile unsigned int*)(0x42C8E644UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN18 *((volatile unsigned int*)(0x42C8E648UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN19 *((volatile unsigned int*)(0x42C8E64CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN20 *((volatile unsigned int*)(0x42C8E650UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN21 *((volatile unsigned int*)(0x42C8E654UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN22 *((volatile unsigned int*)(0x42C8E658UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN23 *((volatile unsigned int*)(0x42C8E65CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN24 *((volatile unsigned int*)(0x42C8E660UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN25 *((volatile unsigned int*)(0x42C8E664UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN26 *((volatile unsigned int*)(0x42C8E668UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN27 *((volatile unsigned int*)(0x42C8E66CUL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN28 *((volatile unsigned int*)(0x42C8E670UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN29 *((volatile unsigned int*)(0x42C8E674UL)) -#define bFM3_ETHERNET_MAC0_ATNR_ATN30 *((volatile unsigned int*)(0x42C8E678UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS0 *((volatile unsigned int*)(0x42C8E680UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS1 *((volatile unsigned int*)(0x42C8E684UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS2 *((volatile unsigned int*)(0x42C8E688UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS3 *((volatile unsigned int*)(0x42C8E68CUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS4 *((volatile unsigned int*)(0x42C8E690UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS5 *((volatile unsigned int*)(0x42C8E694UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS6 *((volatile unsigned int*)(0x42C8E698UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS7 *((volatile unsigned int*)(0x42C8E69CUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS8 *((volatile unsigned int*)(0x42C8E6A0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS9 *((volatile unsigned int*)(0x42C8E6A4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS10 *((volatile unsigned int*)(0x42C8E6A8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS11 *((volatile unsigned int*)(0x42C8E6ACUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS12 *((volatile unsigned int*)(0x42C8E6B0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS13 *((volatile unsigned int*)(0x42C8E6B4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS14 *((volatile unsigned int*)(0x42C8E6B8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS15 *((volatile unsigned int*)(0x42C8E6BCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS16 *((volatile unsigned int*)(0x42C8E6C0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS17 *((volatile unsigned int*)(0x42C8E6C4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS18 *((volatile unsigned int*)(0x42C8E6C8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS19 *((volatile unsigned int*)(0x42C8E6CCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS20 *((volatile unsigned int*)(0x42C8E6D0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS21 *((volatile unsigned int*)(0x42C8E6D4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS22 *((volatile unsigned int*)(0x42C8E6D8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS23 *((volatile unsigned int*)(0x42C8E6DCUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS24 *((volatile unsigned int*)(0x42C8E6E0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS25 *((volatile unsigned int*)(0x42C8E6E4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS26 *((volatile unsigned int*)(0x42C8E6E8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS27 *((volatile unsigned int*)(0x42C8E6ECUL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS28 *((volatile unsigned int*)(0x42C8E6F0UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS29 *((volatile unsigned int*)(0x42C8E6F4UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS30 *((volatile unsigned int*)(0x42C8E6F8UL)) -#define bFM3_ETHERNET_MAC0_ATSR_ATS31 *((volatile unsigned int*)(0x42C8E6FCUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A32 *((volatile unsigned int*)(0x42C90000UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A33 *((volatile unsigned int*)(0x42C90004UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A34 *((volatile unsigned int*)(0x42C90008UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A35 *((volatile unsigned int*)(0x42C9000CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A36 *((volatile unsigned int*)(0x42C90010UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A37 *((volatile unsigned int*)(0x42C90014UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A38 *((volatile unsigned int*)(0x42C90018UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A39 *((volatile unsigned int*)(0x42C9001CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A40 *((volatile unsigned int*)(0x42C90020UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A41 *((volatile unsigned int*)(0x42C90024UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A42 *((volatile unsigned int*)(0x42C90028UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A43 *((volatile unsigned int*)(0x42C9002CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A44 *((volatile unsigned int*)(0x42C90030UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A45 *((volatile unsigned int*)(0x42C90034UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A46 *((volatile unsigned int*)(0x42C90038UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_A47 *((volatile unsigned int*)(0x42C9003CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC0 *((volatile unsigned int*)(0x42C90060UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC1 *((volatile unsigned int*)(0x42C90064UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC2 *((volatile unsigned int*)(0x42C90068UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC3 *((volatile unsigned int*)(0x42C9006CUL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC4 *((volatile unsigned int*)(0x42C90070UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_MBC5 *((volatile unsigned int*)(0x42C90074UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_SA *((volatile unsigned int*)(0x42C90078UL)) -#define bFM3_ETHERNET_MAC0_MAR16H_AE *((volatile unsigned int*)(0x42C9007CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A0 *((volatile unsigned int*)(0x42C90080UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A1 *((volatile unsigned int*)(0x42C90084UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A2 *((volatile unsigned int*)(0x42C90088UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A3 *((volatile unsigned int*)(0x42C9008CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A4 *((volatile unsigned int*)(0x42C90090UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A5 *((volatile unsigned int*)(0x42C90094UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A6 *((volatile unsigned int*)(0x42C90098UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A7 *((volatile unsigned int*)(0x42C9009CUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A8 *((volatile unsigned int*)(0x42C900A0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A9 *((volatile unsigned int*)(0x42C900A4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A10 *((volatile unsigned int*)(0x42C900A8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A11 *((volatile unsigned int*)(0x42C900ACUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A12 *((volatile unsigned int*)(0x42C900B0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A13 *((volatile unsigned int*)(0x42C900B4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A14 *((volatile unsigned int*)(0x42C900B8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A15 *((volatile unsigned int*)(0x42C900BCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A16 *((volatile unsigned int*)(0x42C900C0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A17 *((volatile unsigned int*)(0x42C900C4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A18 *((volatile unsigned int*)(0x42C900C8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A19 *((volatile unsigned int*)(0x42C900CCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A20 *((volatile unsigned int*)(0x42C900D0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A21 *((volatile unsigned int*)(0x42C900D4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A22 *((volatile unsigned int*)(0x42C900D8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A23 *((volatile unsigned int*)(0x42C900DCUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A24 *((volatile unsigned int*)(0x42C900E0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A25 *((volatile unsigned int*)(0x42C900E4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A26 *((volatile unsigned int*)(0x42C900E8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A27 *((volatile unsigned int*)(0x42C900ECUL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A28 *((volatile unsigned int*)(0x42C900F0UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A29 *((volatile unsigned int*)(0x42C900F4UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A30 *((volatile unsigned int*)(0x42C900F8UL)) -#define bFM3_ETHERNET_MAC0_MAR16L_A31 *((volatile unsigned int*)(0x42C900FCUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A32 *((volatile unsigned int*)(0x42C90100UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A33 *((volatile unsigned int*)(0x42C90104UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A34 *((volatile unsigned int*)(0x42C90108UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A35 *((volatile unsigned int*)(0x42C9010CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A36 *((volatile unsigned int*)(0x42C90110UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A37 *((volatile unsigned int*)(0x42C90114UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A38 *((volatile unsigned int*)(0x42C90118UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A39 *((volatile unsigned int*)(0x42C9011CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A40 *((volatile unsigned int*)(0x42C90120UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A41 *((volatile unsigned int*)(0x42C90124UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A42 *((volatile unsigned int*)(0x42C90128UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A43 *((volatile unsigned int*)(0x42C9012CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A44 *((volatile unsigned int*)(0x42C90130UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A45 *((volatile unsigned int*)(0x42C90134UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A46 *((volatile unsigned int*)(0x42C90138UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_A47 *((volatile unsigned int*)(0x42C9013CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC0 *((volatile unsigned int*)(0x42C90160UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC1 *((volatile unsigned int*)(0x42C90164UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC2 *((volatile unsigned int*)(0x42C90168UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC3 *((volatile unsigned int*)(0x42C9016CUL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC4 *((volatile unsigned int*)(0x42C90170UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_MBC5 *((volatile unsigned int*)(0x42C90174UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_SA *((volatile unsigned int*)(0x42C90178UL)) -#define bFM3_ETHERNET_MAC0_MAR17H_AE *((volatile unsigned int*)(0x42C9017CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A0 *((volatile unsigned int*)(0x42C90180UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A1 *((volatile unsigned int*)(0x42C90184UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A2 *((volatile unsigned int*)(0x42C90188UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A3 *((volatile unsigned int*)(0x42C9018CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A4 *((volatile unsigned int*)(0x42C90190UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A5 *((volatile unsigned int*)(0x42C90194UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A6 *((volatile unsigned int*)(0x42C90198UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A7 *((volatile unsigned int*)(0x42C9019CUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A8 *((volatile unsigned int*)(0x42C901A0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A9 *((volatile unsigned int*)(0x42C901A4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A10 *((volatile unsigned int*)(0x42C901A8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A11 *((volatile unsigned int*)(0x42C901ACUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A12 *((volatile unsigned int*)(0x42C901B0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A13 *((volatile unsigned int*)(0x42C901B4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A14 *((volatile unsigned int*)(0x42C901B8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A15 *((volatile unsigned int*)(0x42C901BCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A16 *((volatile unsigned int*)(0x42C901C0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A17 *((volatile unsigned int*)(0x42C901C4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A18 *((volatile unsigned int*)(0x42C901C8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A19 *((volatile unsigned int*)(0x42C901CCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A20 *((volatile unsigned int*)(0x42C901D0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A21 *((volatile unsigned int*)(0x42C901D4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A22 *((volatile unsigned int*)(0x42C901D8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A23 *((volatile unsigned int*)(0x42C901DCUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A24 *((volatile unsigned int*)(0x42C901E0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A25 *((volatile unsigned int*)(0x42C901E4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A26 *((volatile unsigned int*)(0x42C901E8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A27 *((volatile unsigned int*)(0x42C901ECUL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A28 *((volatile unsigned int*)(0x42C901F0UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A29 *((volatile unsigned int*)(0x42C901F4UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A30 *((volatile unsigned int*)(0x42C901F8UL)) -#define bFM3_ETHERNET_MAC0_MAR17L_A31 *((volatile unsigned int*)(0x42C901FCUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A32 *((volatile unsigned int*)(0x42C90200UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A33 *((volatile unsigned int*)(0x42C90204UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A34 *((volatile unsigned int*)(0x42C90208UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A35 *((volatile unsigned int*)(0x42C9020CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A36 *((volatile unsigned int*)(0x42C90210UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A37 *((volatile unsigned int*)(0x42C90214UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A38 *((volatile unsigned int*)(0x42C90218UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A39 *((volatile unsigned int*)(0x42C9021CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A40 *((volatile unsigned int*)(0x42C90220UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A41 *((volatile unsigned int*)(0x42C90224UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A42 *((volatile unsigned int*)(0x42C90228UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A43 *((volatile unsigned int*)(0x42C9022CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A44 *((volatile unsigned int*)(0x42C90230UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A45 *((volatile unsigned int*)(0x42C90234UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A46 *((volatile unsigned int*)(0x42C90238UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_A47 *((volatile unsigned int*)(0x42C9023CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC0 *((volatile unsigned int*)(0x42C90260UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC1 *((volatile unsigned int*)(0x42C90264UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC2 *((volatile unsigned int*)(0x42C90268UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC3 *((volatile unsigned int*)(0x42C9026CUL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC4 *((volatile unsigned int*)(0x42C90270UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_MBC5 *((volatile unsigned int*)(0x42C90274UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_SA *((volatile unsigned int*)(0x42C90278UL)) -#define bFM3_ETHERNET_MAC0_MAR18H_AE *((volatile unsigned int*)(0x42C9027CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A0 *((volatile unsigned int*)(0x42C90280UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A1 *((volatile unsigned int*)(0x42C90284UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A2 *((volatile unsigned int*)(0x42C90288UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A3 *((volatile unsigned int*)(0x42C9028CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A4 *((volatile unsigned int*)(0x42C90290UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A5 *((volatile unsigned int*)(0x42C90294UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A6 *((volatile unsigned int*)(0x42C90298UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A7 *((volatile unsigned int*)(0x42C9029CUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A8 *((volatile unsigned int*)(0x42C902A0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A9 *((volatile unsigned int*)(0x42C902A4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A10 *((volatile unsigned int*)(0x42C902A8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A11 *((volatile unsigned int*)(0x42C902ACUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A12 *((volatile unsigned int*)(0x42C902B0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A13 *((volatile unsigned int*)(0x42C902B4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A14 *((volatile unsigned int*)(0x42C902B8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A15 *((volatile unsigned int*)(0x42C902BCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A16 *((volatile unsigned int*)(0x42C902C0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A17 *((volatile unsigned int*)(0x42C902C4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A18 *((volatile unsigned int*)(0x42C902C8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A19 *((volatile unsigned int*)(0x42C902CCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A20 *((volatile unsigned int*)(0x42C902D0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A21 *((volatile unsigned int*)(0x42C902D4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A22 *((volatile unsigned int*)(0x42C902D8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A23 *((volatile unsigned int*)(0x42C902DCUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A24 *((volatile unsigned int*)(0x42C902E0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A25 *((volatile unsigned int*)(0x42C902E4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A26 *((volatile unsigned int*)(0x42C902E8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A27 *((volatile unsigned int*)(0x42C902ECUL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A28 *((volatile unsigned int*)(0x42C902F0UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A29 *((volatile unsigned int*)(0x42C902F4UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A30 *((volatile unsigned int*)(0x42C902F8UL)) -#define bFM3_ETHERNET_MAC0_MAR18L_A31 *((volatile unsigned int*)(0x42C902FCUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A32 *((volatile unsigned int*)(0x42C90300UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A33 *((volatile unsigned int*)(0x42C90304UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A34 *((volatile unsigned int*)(0x42C90308UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A35 *((volatile unsigned int*)(0x42C9030CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A36 *((volatile unsigned int*)(0x42C90310UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A37 *((volatile unsigned int*)(0x42C90314UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A38 *((volatile unsigned int*)(0x42C90318UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A39 *((volatile unsigned int*)(0x42C9031CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A40 *((volatile unsigned int*)(0x42C90320UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A41 *((volatile unsigned int*)(0x42C90324UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A42 *((volatile unsigned int*)(0x42C90328UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A43 *((volatile unsigned int*)(0x42C9032CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A44 *((volatile unsigned int*)(0x42C90330UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A45 *((volatile unsigned int*)(0x42C90334UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A46 *((volatile unsigned int*)(0x42C90338UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_A47 *((volatile unsigned int*)(0x42C9033CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC0 *((volatile unsigned int*)(0x42C90360UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC1 *((volatile unsigned int*)(0x42C90364UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC2 *((volatile unsigned int*)(0x42C90368UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC3 *((volatile unsigned int*)(0x42C9036CUL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC4 *((volatile unsigned int*)(0x42C90370UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_MBC5 *((volatile unsigned int*)(0x42C90374UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_SA *((volatile unsigned int*)(0x42C90378UL)) -#define bFM3_ETHERNET_MAC0_MAR19H_AE *((volatile unsigned int*)(0x42C9037CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A0 *((volatile unsigned int*)(0x42C90380UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A1 *((volatile unsigned int*)(0x42C90384UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A2 *((volatile unsigned int*)(0x42C90388UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A3 *((volatile unsigned int*)(0x42C9038CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A4 *((volatile unsigned int*)(0x42C90390UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A5 *((volatile unsigned int*)(0x42C90394UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A6 *((volatile unsigned int*)(0x42C90398UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A7 *((volatile unsigned int*)(0x42C9039CUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A8 *((volatile unsigned int*)(0x42C903A0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A9 *((volatile unsigned int*)(0x42C903A4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A10 *((volatile unsigned int*)(0x42C903A8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A11 *((volatile unsigned int*)(0x42C903ACUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A12 *((volatile unsigned int*)(0x42C903B0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A13 *((volatile unsigned int*)(0x42C903B4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A14 *((volatile unsigned int*)(0x42C903B8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A15 *((volatile unsigned int*)(0x42C903BCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A16 *((volatile unsigned int*)(0x42C903C0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A17 *((volatile unsigned int*)(0x42C903C4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A18 *((volatile unsigned int*)(0x42C903C8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A19 *((volatile unsigned int*)(0x42C903CCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A20 *((volatile unsigned int*)(0x42C903D0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A21 *((volatile unsigned int*)(0x42C903D4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A22 *((volatile unsigned int*)(0x42C903D8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A23 *((volatile unsigned int*)(0x42C903DCUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A24 *((volatile unsigned int*)(0x42C903E0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A25 *((volatile unsigned int*)(0x42C903E4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A26 *((volatile unsigned int*)(0x42C903E8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A27 *((volatile unsigned int*)(0x42C903ECUL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A28 *((volatile unsigned int*)(0x42C903F0UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A29 *((volatile unsigned int*)(0x42C903F4UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A30 *((volatile unsigned int*)(0x42C903F8UL)) -#define bFM3_ETHERNET_MAC0_MAR19L_A31 *((volatile unsigned int*)(0x42C903FCUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A32 *((volatile unsigned int*)(0x42C90400UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A33 *((volatile unsigned int*)(0x42C90404UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A34 *((volatile unsigned int*)(0x42C90408UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A35 *((volatile unsigned int*)(0x42C9040CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A36 *((volatile unsigned int*)(0x42C90410UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A37 *((volatile unsigned int*)(0x42C90414UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A38 *((volatile unsigned int*)(0x42C90418UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A39 *((volatile unsigned int*)(0x42C9041CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A40 *((volatile unsigned int*)(0x42C90420UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A41 *((volatile unsigned int*)(0x42C90424UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A42 *((volatile unsigned int*)(0x42C90428UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A43 *((volatile unsigned int*)(0x42C9042CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A44 *((volatile unsigned int*)(0x42C90430UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A45 *((volatile unsigned int*)(0x42C90434UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A46 *((volatile unsigned int*)(0x42C90438UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_A47 *((volatile unsigned int*)(0x42C9043CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC0 *((volatile unsigned int*)(0x42C90460UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC1 *((volatile unsigned int*)(0x42C90464UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC2 *((volatile unsigned int*)(0x42C90468UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC3 *((volatile unsigned int*)(0x42C9046CUL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC4 *((volatile unsigned int*)(0x42C90470UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_MBC5 *((volatile unsigned int*)(0x42C90474UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_SA *((volatile unsigned int*)(0x42C90478UL)) -#define bFM3_ETHERNET_MAC0_MAR20H_AE *((volatile unsigned int*)(0x42C9047CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A0 *((volatile unsigned int*)(0x42C90480UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A1 *((volatile unsigned int*)(0x42C90484UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A2 *((volatile unsigned int*)(0x42C90488UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A3 *((volatile unsigned int*)(0x42C9048CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A4 *((volatile unsigned int*)(0x42C90490UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A5 *((volatile unsigned int*)(0x42C90494UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A6 *((volatile unsigned int*)(0x42C90498UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A7 *((volatile unsigned int*)(0x42C9049CUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A8 *((volatile unsigned int*)(0x42C904A0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A9 *((volatile unsigned int*)(0x42C904A4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A10 *((volatile unsigned int*)(0x42C904A8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A11 *((volatile unsigned int*)(0x42C904ACUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A12 *((volatile unsigned int*)(0x42C904B0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A13 *((volatile unsigned int*)(0x42C904B4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A14 *((volatile unsigned int*)(0x42C904B8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A15 *((volatile unsigned int*)(0x42C904BCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A16 *((volatile unsigned int*)(0x42C904C0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A17 *((volatile unsigned int*)(0x42C904C4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A18 *((volatile unsigned int*)(0x42C904C8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A19 *((volatile unsigned int*)(0x42C904CCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A20 *((volatile unsigned int*)(0x42C904D0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A21 *((volatile unsigned int*)(0x42C904D4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A22 *((volatile unsigned int*)(0x42C904D8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A23 *((volatile unsigned int*)(0x42C904DCUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A24 *((volatile unsigned int*)(0x42C904E0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A25 *((volatile unsigned int*)(0x42C904E4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A26 *((volatile unsigned int*)(0x42C904E8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A27 *((volatile unsigned int*)(0x42C904ECUL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A28 *((volatile unsigned int*)(0x42C904F0UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A29 *((volatile unsigned int*)(0x42C904F4UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A30 *((volatile unsigned int*)(0x42C904F8UL)) -#define bFM3_ETHERNET_MAC0_MAR20L_A31 *((volatile unsigned int*)(0x42C904FCUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A32 *((volatile unsigned int*)(0x42C90500UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A33 *((volatile unsigned int*)(0x42C90504UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A34 *((volatile unsigned int*)(0x42C90508UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A35 *((volatile unsigned int*)(0x42C9050CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A36 *((volatile unsigned int*)(0x42C90510UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A37 *((volatile unsigned int*)(0x42C90514UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A38 *((volatile unsigned int*)(0x42C90518UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A39 *((volatile unsigned int*)(0x42C9051CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A40 *((volatile unsigned int*)(0x42C90520UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A41 *((volatile unsigned int*)(0x42C90524UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A42 *((volatile unsigned int*)(0x42C90528UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A43 *((volatile unsigned int*)(0x42C9052CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A44 *((volatile unsigned int*)(0x42C90530UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A45 *((volatile unsigned int*)(0x42C90534UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A46 *((volatile unsigned int*)(0x42C90538UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_A47 *((volatile unsigned int*)(0x42C9053CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC0 *((volatile unsigned int*)(0x42C90560UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC1 *((volatile unsigned int*)(0x42C90564UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC2 *((volatile unsigned int*)(0x42C90568UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC3 *((volatile unsigned int*)(0x42C9056CUL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC4 *((volatile unsigned int*)(0x42C90570UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_MBC5 *((volatile unsigned int*)(0x42C90574UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_SA *((volatile unsigned int*)(0x42C90578UL)) -#define bFM3_ETHERNET_MAC0_MAR21H_AE *((volatile unsigned int*)(0x42C9057CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A0 *((volatile unsigned int*)(0x42C90580UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A1 *((volatile unsigned int*)(0x42C90584UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A2 *((volatile unsigned int*)(0x42C90588UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A3 *((volatile unsigned int*)(0x42C9058CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A4 *((volatile unsigned int*)(0x42C90590UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A5 *((volatile unsigned int*)(0x42C90594UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A6 *((volatile unsigned int*)(0x42C90598UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A7 *((volatile unsigned int*)(0x42C9059CUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A8 *((volatile unsigned int*)(0x42C905A0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A9 *((volatile unsigned int*)(0x42C905A4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A10 *((volatile unsigned int*)(0x42C905A8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A11 *((volatile unsigned int*)(0x42C905ACUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A12 *((volatile unsigned int*)(0x42C905B0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A13 *((volatile unsigned int*)(0x42C905B4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A14 *((volatile unsigned int*)(0x42C905B8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A15 *((volatile unsigned int*)(0x42C905BCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A16 *((volatile unsigned int*)(0x42C905C0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A17 *((volatile unsigned int*)(0x42C905C4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A18 *((volatile unsigned int*)(0x42C905C8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A19 *((volatile unsigned int*)(0x42C905CCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A20 *((volatile unsigned int*)(0x42C905D0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A21 *((volatile unsigned int*)(0x42C905D4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A22 *((volatile unsigned int*)(0x42C905D8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A23 *((volatile unsigned int*)(0x42C905DCUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A24 *((volatile unsigned int*)(0x42C905E0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A25 *((volatile unsigned int*)(0x42C905E4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A26 *((volatile unsigned int*)(0x42C905E8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A27 *((volatile unsigned int*)(0x42C905ECUL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A28 *((volatile unsigned int*)(0x42C905F0UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A29 *((volatile unsigned int*)(0x42C905F4UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A30 *((volatile unsigned int*)(0x42C905F8UL)) -#define bFM3_ETHERNET_MAC0_MAR21L_A31 *((volatile unsigned int*)(0x42C905FCUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A32 *((volatile unsigned int*)(0x42C90600UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A33 *((volatile unsigned int*)(0x42C90604UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A34 *((volatile unsigned int*)(0x42C90608UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A35 *((volatile unsigned int*)(0x42C9060CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A36 *((volatile unsigned int*)(0x42C90610UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A37 *((volatile unsigned int*)(0x42C90614UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A38 *((volatile unsigned int*)(0x42C90618UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A39 *((volatile unsigned int*)(0x42C9061CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A40 *((volatile unsigned int*)(0x42C90620UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A41 *((volatile unsigned int*)(0x42C90624UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A42 *((volatile unsigned int*)(0x42C90628UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A43 *((volatile unsigned int*)(0x42C9062CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A44 *((volatile unsigned int*)(0x42C90630UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A45 *((volatile unsigned int*)(0x42C90634UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A46 *((volatile unsigned int*)(0x42C90638UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_A47 *((volatile unsigned int*)(0x42C9063CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC0 *((volatile unsigned int*)(0x42C90660UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC1 *((volatile unsigned int*)(0x42C90664UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC2 *((volatile unsigned int*)(0x42C90668UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC3 *((volatile unsigned int*)(0x42C9066CUL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC4 *((volatile unsigned int*)(0x42C90670UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_MBC5 *((volatile unsigned int*)(0x42C90674UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_SA *((volatile unsigned int*)(0x42C90678UL)) -#define bFM3_ETHERNET_MAC0_MAR22H_AE *((volatile unsigned int*)(0x42C9067CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A0 *((volatile unsigned int*)(0x42C90680UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A1 *((volatile unsigned int*)(0x42C90684UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A2 *((volatile unsigned int*)(0x42C90688UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A3 *((volatile unsigned int*)(0x42C9068CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A4 *((volatile unsigned int*)(0x42C90690UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A5 *((volatile unsigned int*)(0x42C90694UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A6 *((volatile unsigned int*)(0x42C90698UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A7 *((volatile unsigned int*)(0x42C9069CUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A8 *((volatile unsigned int*)(0x42C906A0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A9 *((volatile unsigned int*)(0x42C906A4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A10 *((volatile unsigned int*)(0x42C906A8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A11 *((volatile unsigned int*)(0x42C906ACUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A12 *((volatile unsigned int*)(0x42C906B0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A13 *((volatile unsigned int*)(0x42C906B4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A14 *((volatile unsigned int*)(0x42C906B8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A15 *((volatile unsigned int*)(0x42C906BCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A16 *((volatile unsigned int*)(0x42C906C0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A17 *((volatile unsigned int*)(0x42C906C4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A18 *((volatile unsigned int*)(0x42C906C8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A19 *((volatile unsigned int*)(0x42C906CCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A20 *((volatile unsigned int*)(0x42C906D0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A21 *((volatile unsigned int*)(0x42C906D4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A22 *((volatile unsigned int*)(0x42C906D8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A23 *((volatile unsigned int*)(0x42C906DCUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A24 *((volatile unsigned int*)(0x42C906E0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A25 *((volatile unsigned int*)(0x42C906E4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A26 *((volatile unsigned int*)(0x42C906E8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A27 *((volatile unsigned int*)(0x42C906ECUL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A28 *((volatile unsigned int*)(0x42C906F0UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A29 *((volatile unsigned int*)(0x42C906F4UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A30 *((volatile unsigned int*)(0x42C906F8UL)) -#define bFM3_ETHERNET_MAC0_MAR22L_A31 *((volatile unsigned int*)(0x42C906FCUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A32 *((volatile unsigned int*)(0x42C90700UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A33 *((volatile unsigned int*)(0x42C90704UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A34 *((volatile unsigned int*)(0x42C90708UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A35 *((volatile unsigned int*)(0x42C9070CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A36 *((volatile unsigned int*)(0x42C90710UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A37 *((volatile unsigned int*)(0x42C90714UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A38 *((volatile unsigned int*)(0x42C90718UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A39 *((volatile unsigned int*)(0x42C9071CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A40 *((volatile unsigned int*)(0x42C90720UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A41 *((volatile unsigned int*)(0x42C90724UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A42 *((volatile unsigned int*)(0x42C90728UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A43 *((volatile unsigned int*)(0x42C9072CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A44 *((volatile unsigned int*)(0x42C90730UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A45 *((volatile unsigned int*)(0x42C90734UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A46 *((volatile unsigned int*)(0x42C90738UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_A47 *((volatile unsigned int*)(0x42C9073CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC0 *((volatile unsigned int*)(0x42C90760UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC1 *((volatile unsigned int*)(0x42C90764UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC2 *((volatile unsigned int*)(0x42C90768UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC3 *((volatile unsigned int*)(0x42C9076CUL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC4 *((volatile unsigned int*)(0x42C90770UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_MBC5 *((volatile unsigned int*)(0x42C90774UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_SA *((volatile unsigned int*)(0x42C90778UL)) -#define bFM3_ETHERNET_MAC0_MAR23H_AE *((volatile unsigned int*)(0x42C9077CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A0 *((volatile unsigned int*)(0x42C90780UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A1 *((volatile unsigned int*)(0x42C90784UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A2 *((volatile unsigned int*)(0x42C90788UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A3 *((volatile unsigned int*)(0x42C9078CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A4 *((volatile unsigned int*)(0x42C90790UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A5 *((volatile unsigned int*)(0x42C90794UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A6 *((volatile unsigned int*)(0x42C90798UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A7 *((volatile unsigned int*)(0x42C9079CUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A8 *((volatile unsigned int*)(0x42C907A0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A9 *((volatile unsigned int*)(0x42C907A4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A10 *((volatile unsigned int*)(0x42C907A8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A11 *((volatile unsigned int*)(0x42C907ACUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A12 *((volatile unsigned int*)(0x42C907B0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A13 *((volatile unsigned int*)(0x42C907B4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A14 *((volatile unsigned int*)(0x42C907B8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A15 *((volatile unsigned int*)(0x42C907BCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A16 *((volatile unsigned int*)(0x42C907C0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A17 *((volatile unsigned int*)(0x42C907C4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A18 *((volatile unsigned int*)(0x42C907C8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A19 *((volatile unsigned int*)(0x42C907CCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A20 *((volatile unsigned int*)(0x42C907D0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A21 *((volatile unsigned int*)(0x42C907D4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A22 *((volatile unsigned int*)(0x42C907D8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A23 *((volatile unsigned int*)(0x42C907DCUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A24 *((volatile unsigned int*)(0x42C907E0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A25 *((volatile unsigned int*)(0x42C907E4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A26 *((volatile unsigned int*)(0x42C907E8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A27 *((volatile unsigned int*)(0x42C907ECUL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A28 *((volatile unsigned int*)(0x42C907F0UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A29 *((volatile unsigned int*)(0x42C907F4UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A30 *((volatile unsigned int*)(0x42C907F8UL)) -#define bFM3_ETHERNET_MAC0_MAR23L_A31 *((volatile unsigned int*)(0x42C907FCUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A32 *((volatile unsigned int*)(0x42C90800UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A33 *((volatile unsigned int*)(0x42C90804UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A34 *((volatile unsigned int*)(0x42C90808UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A35 *((volatile unsigned int*)(0x42C9080CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A36 *((volatile unsigned int*)(0x42C90810UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A37 *((volatile unsigned int*)(0x42C90814UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A38 *((volatile unsigned int*)(0x42C90818UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A39 *((volatile unsigned int*)(0x42C9081CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A40 *((volatile unsigned int*)(0x42C90820UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A41 *((volatile unsigned int*)(0x42C90824UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A42 *((volatile unsigned int*)(0x42C90828UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A43 *((volatile unsigned int*)(0x42C9082CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A44 *((volatile unsigned int*)(0x42C90830UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A45 *((volatile unsigned int*)(0x42C90834UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A46 *((volatile unsigned int*)(0x42C90838UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_A47 *((volatile unsigned int*)(0x42C9083CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC0 *((volatile unsigned int*)(0x42C90860UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC1 *((volatile unsigned int*)(0x42C90864UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC2 *((volatile unsigned int*)(0x42C90868UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC3 *((volatile unsigned int*)(0x42C9086CUL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC4 *((volatile unsigned int*)(0x42C90870UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_MBC5 *((volatile unsigned int*)(0x42C90874UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_SA *((volatile unsigned int*)(0x42C90878UL)) -#define bFM3_ETHERNET_MAC0_MAR24H_AE *((volatile unsigned int*)(0x42C9087CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A0 *((volatile unsigned int*)(0x42C90880UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A1 *((volatile unsigned int*)(0x42C90884UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A2 *((volatile unsigned int*)(0x42C90888UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A3 *((volatile unsigned int*)(0x42C9088CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A4 *((volatile unsigned int*)(0x42C90890UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A5 *((volatile unsigned int*)(0x42C90894UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A6 *((volatile unsigned int*)(0x42C90898UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A7 *((volatile unsigned int*)(0x42C9089CUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A8 *((volatile unsigned int*)(0x42C908A0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A9 *((volatile unsigned int*)(0x42C908A4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A10 *((volatile unsigned int*)(0x42C908A8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A11 *((volatile unsigned int*)(0x42C908ACUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A12 *((volatile unsigned int*)(0x42C908B0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A13 *((volatile unsigned int*)(0x42C908B4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A14 *((volatile unsigned int*)(0x42C908B8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A15 *((volatile unsigned int*)(0x42C908BCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A16 *((volatile unsigned int*)(0x42C908C0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A17 *((volatile unsigned int*)(0x42C908C4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A18 *((volatile unsigned int*)(0x42C908C8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A19 *((volatile unsigned int*)(0x42C908CCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A20 *((volatile unsigned int*)(0x42C908D0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A21 *((volatile unsigned int*)(0x42C908D4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A22 *((volatile unsigned int*)(0x42C908D8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A23 *((volatile unsigned int*)(0x42C908DCUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A24 *((volatile unsigned int*)(0x42C908E0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A25 *((volatile unsigned int*)(0x42C908E4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A26 *((volatile unsigned int*)(0x42C908E8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A27 *((volatile unsigned int*)(0x42C908ECUL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A28 *((volatile unsigned int*)(0x42C908F0UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A29 *((volatile unsigned int*)(0x42C908F4UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A30 *((volatile unsigned int*)(0x42C908F8UL)) -#define bFM3_ETHERNET_MAC0_MAR24L_A31 *((volatile unsigned int*)(0x42C908FCUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A32 *((volatile unsigned int*)(0x42C90900UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A33 *((volatile unsigned int*)(0x42C90904UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A34 *((volatile unsigned int*)(0x42C90908UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A35 *((volatile unsigned int*)(0x42C9090CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A36 *((volatile unsigned int*)(0x42C90910UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A37 *((volatile unsigned int*)(0x42C90914UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A38 *((volatile unsigned int*)(0x42C90918UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A39 *((volatile unsigned int*)(0x42C9091CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A40 *((volatile unsigned int*)(0x42C90920UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A41 *((volatile unsigned int*)(0x42C90924UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A42 *((volatile unsigned int*)(0x42C90928UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A43 *((volatile unsigned int*)(0x42C9092CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A44 *((volatile unsigned int*)(0x42C90930UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A45 *((volatile unsigned int*)(0x42C90934UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A46 *((volatile unsigned int*)(0x42C90938UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_A47 *((volatile unsigned int*)(0x42C9093CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC0 *((volatile unsigned int*)(0x42C90960UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC1 *((volatile unsigned int*)(0x42C90964UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC2 *((volatile unsigned int*)(0x42C90968UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC3 *((volatile unsigned int*)(0x42C9096CUL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC4 *((volatile unsigned int*)(0x42C90970UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_MBC5 *((volatile unsigned int*)(0x42C90974UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_SA *((volatile unsigned int*)(0x42C90978UL)) -#define bFM3_ETHERNET_MAC0_MAR25H_AE *((volatile unsigned int*)(0x42C9097CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A0 *((volatile unsigned int*)(0x42C90980UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A1 *((volatile unsigned int*)(0x42C90984UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A2 *((volatile unsigned int*)(0x42C90988UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A3 *((volatile unsigned int*)(0x42C9098CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A4 *((volatile unsigned int*)(0x42C90990UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A5 *((volatile unsigned int*)(0x42C90994UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A6 *((volatile unsigned int*)(0x42C90998UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A7 *((volatile unsigned int*)(0x42C9099CUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A8 *((volatile unsigned int*)(0x42C909A0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A9 *((volatile unsigned int*)(0x42C909A4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A10 *((volatile unsigned int*)(0x42C909A8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A11 *((volatile unsigned int*)(0x42C909ACUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A12 *((volatile unsigned int*)(0x42C909B0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A13 *((volatile unsigned int*)(0x42C909B4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A14 *((volatile unsigned int*)(0x42C909B8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A15 *((volatile unsigned int*)(0x42C909BCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A16 *((volatile unsigned int*)(0x42C909C0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A17 *((volatile unsigned int*)(0x42C909C4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A18 *((volatile unsigned int*)(0x42C909C8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A19 *((volatile unsigned int*)(0x42C909CCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A20 *((volatile unsigned int*)(0x42C909D0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A21 *((volatile unsigned int*)(0x42C909D4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A22 *((volatile unsigned int*)(0x42C909D8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A23 *((volatile unsigned int*)(0x42C909DCUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A24 *((volatile unsigned int*)(0x42C909E0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A25 *((volatile unsigned int*)(0x42C909E4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A26 *((volatile unsigned int*)(0x42C909E8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A27 *((volatile unsigned int*)(0x42C909ECUL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A28 *((volatile unsigned int*)(0x42C909F0UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A29 *((volatile unsigned int*)(0x42C909F4UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A30 *((volatile unsigned int*)(0x42C909F8UL)) -#define bFM3_ETHERNET_MAC0_MAR25L_A31 *((volatile unsigned int*)(0x42C909FCUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A32 *((volatile unsigned int*)(0x42C90A00UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A33 *((volatile unsigned int*)(0x42C90A04UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A34 *((volatile unsigned int*)(0x42C90A08UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A35 *((volatile unsigned int*)(0x42C90A0CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A36 *((volatile unsigned int*)(0x42C90A10UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A37 *((volatile unsigned int*)(0x42C90A14UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A38 *((volatile unsigned int*)(0x42C90A18UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A39 *((volatile unsigned int*)(0x42C90A1CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A40 *((volatile unsigned int*)(0x42C90A20UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A41 *((volatile unsigned int*)(0x42C90A24UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A42 *((volatile unsigned int*)(0x42C90A28UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A43 *((volatile unsigned int*)(0x42C90A2CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A44 *((volatile unsigned int*)(0x42C90A30UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A45 *((volatile unsigned int*)(0x42C90A34UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A46 *((volatile unsigned int*)(0x42C90A38UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_A47 *((volatile unsigned int*)(0x42C90A3CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC0 *((volatile unsigned int*)(0x42C90A60UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC1 *((volatile unsigned int*)(0x42C90A64UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC2 *((volatile unsigned int*)(0x42C90A68UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC3 *((volatile unsigned int*)(0x42C90A6CUL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC4 *((volatile unsigned int*)(0x42C90A70UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_MBC5 *((volatile unsigned int*)(0x42C90A74UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_SA *((volatile unsigned int*)(0x42C90A78UL)) -#define bFM3_ETHERNET_MAC0_MAR26H_AE *((volatile unsigned int*)(0x42C90A7CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A0 *((volatile unsigned int*)(0x42C90A80UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A1 *((volatile unsigned int*)(0x42C90A84UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A2 *((volatile unsigned int*)(0x42C90A88UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A3 *((volatile unsigned int*)(0x42C90A8CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A4 *((volatile unsigned int*)(0x42C90A90UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A5 *((volatile unsigned int*)(0x42C90A94UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A6 *((volatile unsigned int*)(0x42C90A98UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A7 *((volatile unsigned int*)(0x42C90A9CUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A8 *((volatile unsigned int*)(0x42C90AA0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A9 *((volatile unsigned int*)(0x42C90AA4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A10 *((volatile unsigned int*)(0x42C90AA8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A11 *((volatile unsigned int*)(0x42C90AACUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A12 *((volatile unsigned int*)(0x42C90AB0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A13 *((volatile unsigned int*)(0x42C90AB4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A14 *((volatile unsigned int*)(0x42C90AB8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A15 *((volatile unsigned int*)(0x42C90ABCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A16 *((volatile unsigned int*)(0x42C90AC0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A17 *((volatile unsigned int*)(0x42C90AC4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A18 *((volatile unsigned int*)(0x42C90AC8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A19 *((volatile unsigned int*)(0x42C90ACCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A20 *((volatile unsigned int*)(0x42C90AD0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A21 *((volatile unsigned int*)(0x42C90AD4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A22 *((volatile unsigned int*)(0x42C90AD8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A23 *((volatile unsigned int*)(0x42C90ADCUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A24 *((volatile unsigned int*)(0x42C90AE0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A25 *((volatile unsigned int*)(0x42C90AE4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A26 *((volatile unsigned int*)(0x42C90AE8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A27 *((volatile unsigned int*)(0x42C90AECUL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A28 *((volatile unsigned int*)(0x42C90AF0UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A29 *((volatile unsigned int*)(0x42C90AF4UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A30 *((volatile unsigned int*)(0x42C90AF8UL)) -#define bFM3_ETHERNET_MAC0_MAR26L_A31 *((volatile unsigned int*)(0x42C90AFCUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A32 *((volatile unsigned int*)(0x42C90B00UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A33 *((volatile unsigned int*)(0x42C90B04UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A34 *((volatile unsigned int*)(0x42C90B08UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A35 *((volatile unsigned int*)(0x42C90B0CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A36 *((volatile unsigned int*)(0x42C90B10UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A37 *((volatile unsigned int*)(0x42C90B14UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A38 *((volatile unsigned int*)(0x42C90B18UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A39 *((volatile unsigned int*)(0x42C90B1CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A40 *((volatile unsigned int*)(0x42C90B20UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A41 *((volatile unsigned int*)(0x42C90B24UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A42 *((volatile unsigned int*)(0x42C90B28UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A43 *((volatile unsigned int*)(0x42C90B2CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A44 *((volatile unsigned int*)(0x42C90B30UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A45 *((volatile unsigned int*)(0x42C90B34UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A46 *((volatile unsigned int*)(0x42C90B38UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_A47 *((volatile unsigned int*)(0x42C90B3CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC0 *((volatile unsigned int*)(0x42C90B60UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC1 *((volatile unsigned int*)(0x42C90B64UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC2 *((volatile unsigned int*)(0x42C90B68UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC3 *((volatile unsigned int*)(0x42C90B6CUL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC4 *((volatile unsigned int*)(0x42C90B70UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_MBC5 *((volatile unsigned int*)(0x42C90B74UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_SA *((volatile unsigned int*)(0x42C90B78UL)) -#define bFM3_ETHERNET_MAC0_MAR27H_AE *((volatile unsigned int*)(0x42C90B7CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A0 *((volatile unsigned int*)(0x42C90B80UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A1 *((volatile unsigned int*)(0x42C90B84UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A2 *((volatile unsigned int*)(0x42C90B88UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A3 *((volatile unsigned int*)(0x42C90B8CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A4 *((volatile unsigned int*)(0x42C90B90UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A5 *((volatile unsigned int*)(0x42C90B94UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A6 *((volatile unsigned int*)(0x42C90B98UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A7 *((volatile unsigned int*)(0x42C90B9CUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A8 *((volatile unsigned int*)(0x42C90BA0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A9 *((volatile unsigned int*)(0x42C90BA4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A10 *((volatile unsigned int*)(0x42C90BA8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A11 *((volatile unsigned int*)(0x42C90BACUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A12 *((volatile unsigned int*)(0x42C90BB0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A13 *((volatile unsigned int*)(0x42C90BB4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A14 *((volatile unsigned int*)(0x42C90BB8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A15 *((volatile unsigned int*)(0x42C90BBCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A16 *((volatile unsigned int*)(0x42C90BC0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A17 *((volatile unsigned int*)(0x42C90BC4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A18 *((volatile unsigned int*)(0x42C90BC8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A19 *((volatile unsigned int*)(0x42C90BCCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A20 *((volatile unsigned int*)(0x42C90BD0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A21 *((volatile unsigned int*)(0x42C90BD4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A22 *((volatile unsigned int*)(0x42C90BD8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A23 *((volatile unsigned int*)(0x42C90BDCUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A24 *((volatile unsigned int*)(0x42C90BE0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A25 *((volatile unsigned int*)(0x42C90BE4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A26 *((volatile unsigned int*)(0x42C90BE8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A27 *((volatile unsigned int*)(0x42C90BECUL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A28 *((volatile unsigned int*)(0x42C90BF0UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A29 *((volatile unsigned int*)(0x42C90BF4UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A30 *((volatile unsigned int*)(0x42C90BF8UL)) -#define bFM3_ETHERNET_MAC0_MAR27L_A31 *((volatile unsigned int*)(0x42C90BFCUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A32 *((volatile unsigned int*)(0x42C90C00UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A33 *((volatile unsigned int*)(0x42C90C04UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A34 *((volatile unsigned int*)(0x42C90C08UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A35 *((volatile unsigned int*)(0x42C90C0CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A36 *((volatile unsigned int*)(0x42C90C10UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A37 *((volatile unsigned int*)(0x42C90C14UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A38 *((volatile unsigned int*)(0x42C90C18UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A39 *((volatile unsigned int*)(0x42C90C1CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A40 *((volatile unsigned int*)(0x42C90C20UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A41 *((volatile unsigned int*)(0x42C90C24UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A42 *((volatile unsigned int*)(0x42C90C28UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A43 *((volatile unsigned int*)(0x42C90C2CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A44 *((volatile unsigned int*)(0x42C90C30UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A45 *((volatile unsigned int*)(0x42C90C34UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A46 *((volatile unsigned int*)(0x42C90C38UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_A47 *((volatile unsigned int*)(0x42C90C3CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC0 *((volatile unsigned int*)(0x42C90C60UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC1 *((volatile unsigned int*)(0x42C90C64UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC2 *((volatile unsigned int*)(0x42C90C68UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC3 *((volatile unsigned int*)(0x42C90C6CUL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC4 *((volatile unsigned int*)(0x42C90C70UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_MBC5 *((volatile unsigned int*)(0x42C90C74UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_SA *((volatile unsigned int*)(0x42C90C78UL)) -#define bFM3_ETHERNET_MAC0_MAR28H_AE *((volatile unsigned int*)(0x42C90C7CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A0 *((volatile unsigned int*)(0x42C90C80UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A1 *((volatile unsigned int*)(0x42C90C84UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A2 *((volatile unsigned int*)(0x42C90C88UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A3 *((volatile unsigned int*)(0x42C90C8CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A4 *((volatile unsigned int*)(0x42C90C90UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A5 *((volatile unsigned int*)(0x42C90C94UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A6 *((volatile unsigned int*)(0x42C90C98UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A7 *((volatile unsigned int*)(0x42C90C9CUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A8 *((volatile unsigned int*)(0x42C90CA0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A9 *((volatile unsigned int*)(0x42C90CA4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A10 *((volatile unsigned int*)(0x42C90CA8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A11 *((volatile unsigned int*)(0x42C90CACUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A12 *((volatile unsigned int*)(0x42C90CB0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A13 *((volatile unsigned int*)(0x42C90CB4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A14 *((volatile unsigned int*)(0x42C90CB8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A15 *((volatile unsigned int*)(0x42C90CBCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A16 *((volatile unsigned int*)(0x42C90CC0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A17 *((volatile unsigned int*)(0x42C90CC4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A18 *((volatile unsigned int*)(0x42C90CC8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A19 *((volatile unsigned int*)(0x42C90CCCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A20 *((volatile unsigned int*)(0x42C90CD0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A21 *((volatile unsigned int*)(0x42C90CD4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A22 *((volatile unsigned int*)(0x42C90CD8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A23 *((volatile unsigned int*)(0x42C90CDCUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A24 *((volatile unsigned int*)(0x42C90CE0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A25 *((volatile unsigned int*)(0x42C90CE4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A26 *((volatile unsigned int*)(0x42C90CE8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A27 *((volatile unsigned int*)(0x42C90CECUL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A28 *((volatile unsigned int*)(0x42C90CF0UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A29 *((volatile unsigned int*)(0x42C90CF4UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A30 *((volatile unsigned int*)(0x42C90CF8UL)) -#define bFM3_ETHERNET_MAC0_MAR28L_A31 *((volatile unsigned int*)(0x42C90CFCUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A32 *((volatile unsigned int*)(0x42C90D00UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A33 *((volatile unsigned int*)(0x42C90D04UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A34 *((volatile unsigned int*)(0x42C90D08UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A35 *((volatile unsigned int*)(0x42C90D0CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A36 *((volatile unsigned int*)(0x42C90D10UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A37 *((volatile unsigned int*)(0x42C90D14UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A38 *((volatile unsigned int*)(0x42C90D18UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A39 *((volatile unsigned int*)(0x42C90D1CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A40 *((volatile unsigned int*)(0x42C90D20UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A41 *((volatile unsigned int*)(0x42C90D24UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A42 *((volatile unsigned int*)(0x42C90D28UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A43 *((volatile unsigned int*)(0x42C90D2CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A44 *((volatile unsigned int*)(0x42C90D30UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A45 *((volatile unsigned int*)(0x42C90D34UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A46 *((volatile unsigned int*)(0x42C90D38UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_A47 *((volatile unsigned int*)(0x42C90D3CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC0 *((volatile unsigned int*)(0x42C90D60UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC1 *((volatile unsigned int*)(0x42C90D64UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC2 *((volatile unsigned int*)(0x42C90D68UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC3 *((volatile unsigned int*)(0x42C90D6CUL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC4 *((volatile unsigned int*)(0x42C90D70UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_MBC5 *((volatile unsigned int*)(0x42C90D74UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_SA *((volatile unsigned int*)(0x42C90D78UL)) -#define bFM3_ETHERNET_MAC0_MAR29H_AE *((volatile unsigned int*)(0x42C90D7CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A0 *((volatile unsigned int*)(0x42C90D80UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A1 *((volatile unsigned int*)(0x42C90D84UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A2 *((volatile unsigned int*)(0x42C90D88UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A3 *((volatile unsigned int*)(0x42C90D8CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A4 *((volatile unsigned int*)(0x42C90D90UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A5 *((volatile unsigned int*)(0x42C90D94UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A6 *((volatile unsigned int*)(0x42C90D98UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A7 *((volatile unsigned int*)(0x42C90D9CUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A8 *((volatile unsigned int*)(0x42C90DA0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A9 *((volatile unsigned int*)(0x42C90DA4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A10 *((volatile unsigned int*)(0x42C90DA8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A11 *((volatile unsigned int*)(0x42C90DACUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A12 *((volatile unsigned int*)(0x42C90DB0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A13 *((volatile unsigned int*)(0x42C90DB4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A14 *((volatile unsigned int*)(0x42C90DB8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A15 *((volatile unsigned int*)(0x42C90DBCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A16 *((volatile unsigned int*)(0x42C90DC0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A17 *((volatile unsigned int*)(0x42C90DC4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A18 *((volatile unsigned int*)(0x42C90DC8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A19 *((volatile unsigned int*)(0x42C90DCCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A20 *((volatile unsigned int*)(0x42C90DD0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A21 *((volatile unsigned int*)(0x42C90DD4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A22 *((volatile unsigned int*)(0x42C90DD8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A23 *((volatile unsigned int*)(0x42C90DDCUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A24 *((volatile unsigned int*)(0x42C90DE0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A25 *((volatile unsigned int*)(0x42C90DE4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A26 *((volatile unsigned int*)(0x42C90DE8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A27 *((volatile unsigned int*)(0x42C90DECUL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A28 *((volatile unsigned int*)(0x42C90DF0UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A29 *((volatile unsigned int*)(0x42C90DF4UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A30 *((volatile unsigned int*)(0x42C90DF8UL)) -#define bFM3_ETHERNET_MAC0_MAR29L_A31 *((volatile unsigned int*)(0x42C90DFCUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A32 *((volatile unsigned int*)(0x42C90E00UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A33 *((volatile unsigned int*)(0x42C90E04UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A34 *((volatile unsigned int*)(0x42C90E08UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A35 *((volatile unsigned int*)(0x42C90E0CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A36 *((volatile unsigned int*)(0x42C90E10UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A37 *((volatile unsigned int*)(0x42C90E14UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A38 *((volatile unsigned int*)(0x42C90E18UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A39 *((volatile unsigned int*)(0x42C90E1CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A40 *((volatile unsigned int*)(0x42C90E20UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A41 *((volatile unsigned int*)(0x42C90E24UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A42 *((volatile unsigned int*)(0x42C90E28UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A43 *((volatile unsigned int*)(0x42C90E2CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A44 *((volatile unsigned int*)(0x42C90E30UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A45 *((volatile unsigned int*)(0x42C90E34UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A46 *((volatile unsigned int*)(0x42C90E38UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_A47 *((volatile unsigned int*)(0x42C90E3CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC0 *((volatile unsigned int*)(0x42C90E60UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC1 *((volatile unsigned int*)(0x42C90E64UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC2 *((volatile unsigned int*)(0x42C90E68UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC3 *((volatile unsigned int*)(0x42C90E6CUL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC4 *((volatile unsigned int*)(0x42C90E70UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_MBC5 *((volatile unsigned int*)(0x42C90E74UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_SA *((volatile unsigned int*)(0x42C90E78UL)) -#define bFM3_ETHERNET_MAC0_MAR30H_AE *((volatile unsigned int*)(0x42C90E7CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A0 *((volatile unsigned int*)(0x42C90E80UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A1 *((volatile unsigned int*)(0x42C90E84UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A2 *((volatile unsigned int*)(0x42C90E88UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A3 *((volatile unsigned int*)(0x42C90E8CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A4 *((volatile unsigned int*)(0x42C90E90UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A5 *((volatile unsigned int*)(0x42C90E94UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A6 *((volatile unsigned int*)(0x42C90E98UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A7 *((volatile unsigned int*)(0x42C90E9CUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A8 *((volatile unsigned int*)(0x42C90EA0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A9 *((volatile unsigned int*)(0x42C90EA4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A10 *((volatile unsigned int*)(0x42C90EA8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A11 *((volatile unsigned int*)(0x42C90EACUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A12 *((volatile unsigned int*)(0x42C90EB0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A13 *((volatile unsigned int*)(0x42C90EB4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A14 *((volatile unsigned int*)(0x42C90EB8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A15 *((volatile unsigned int*)(0x42C90EBCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A16 *((volatile unsigned int*)(0x42C90EC0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A17 *((volatile unsigned int*)(0x42C90EC4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A18 *((volatile unsigned int*)(0x42C90EC8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A19 *((volatile unsigned int*)(0x42C90ECCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A20 *((volatile unsigned int*)(0x42C90ED0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A21 *((volatile unsigned int*)(0x42C90ED4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A22 *((volatile unsigned int*)(0x42C90ED8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A23 *((volatile unsigned int*)(0x42C90EDCUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A24 *((volatile unsigned int*)(0x42C90EE0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A25 *((volatile unsigned int*)(0x42C90EE4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A26 *((volatile unsigned int*)(0x42C90EE8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A27 *((volatile unsigned int*)(0x42C90EECUL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A28 *((volatile unsigned int*)(0x42C90EF0UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A29 *((volatile unsigned int*)(0x42C90EF4UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A30 *((volatile unsigned int*)(0x42C90EF8UL)) -#define bFM3_ETHERNET_MAC0_MAR30L_A31 *((volatile unsigned int*)(0x42C90EFCUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A32 *((volatile unsigned int*)(0x42C90F00UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A33 *((volatile unsigned int*)(0x42C90F04UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A34 *((volatile unsigned int*)(0x42C90F08UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A35 *((volatile unsigned int*)(0x42C90F0CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A36 *((volatile unsigned int*)(0x42C90F10UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A37 *((volatile unsigned int*)(0x42C90F14UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A38 *((volatile unsigned int*)(0x42C90F18UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A39 *((volatile unsigned int*)(0x42C90F1CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A40 *((volatile unsigned int*)(0x42C90F20UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A41 *((volatile unsigned int*)(0x42C90F24UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A42 *((volatile unsigned int*)(0x42C90F28UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A43 *((volatile unsigned int*)(0x42C90F2CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A44 *((volatile unsigned int*)(0x42C90F30UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A45 *((volatile unsigned int*)(0x42C90F34UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A46 *((volatile unsigned int*)(0x42C90F38UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_A47 *((volatile unsigned int*)(0x42C90F3CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC0 *((volatile unsigned int*)(0x42C90F60UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC1 *((volatile unsigned int*)(0x42C90F64UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC2 *((volatile unsigned int*)(0x42C90F68UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC3 *((volatile unsigned int*)(0x42C90F6CUL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC4 *((volatile unsigned int*)(0x42C90F70UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_MBC5 *((volatile unsigned int*)(0x42C90F74UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_SA *((volatile unsigned int*)(0x42C90F78UL)) -#define bFM3_ETHERNET_MAC0_MAR31H_AE *((volatile unsigned int*)(0x42C90F7CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A0 *((volatile unsigned int*)(0x42C90F80UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A1 *((volatile unsigned int*)(0x42C90F84UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A2 *((volatile unsigned int*)(0x42C90F88UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A3 *((volatile unsigned int*)(0x42C90F8CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A4 *((volatile unsigned int*)(0x42C90F90UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A5 *((volatile unsigned int*)(0x42C90F94UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A6 *((volatile unsigned int*)(0x42C90F98UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A7 *((volatile unsigned int*)(0x42C90F9CUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A8 *((volatile unsigned int*)(0x42C90FA0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A9 *((volatile unsigned int*)(0x42C90FA4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A10 *((volatile unsigned int*)(0x42C90FA8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A11 *((volatile unsigned int*)(0x42C90FACUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A12 *((volatile unsigned int*)(0x42C90FB0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A13 *((volatile unsigned int*)(0x42C90FB4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A14 *((volatile unsigned int*)(0x42C90FB8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A15 *((volatile unsigned int*)(0x42C90FBCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A16 *((volatile unsigned int*)(0x42C90FC0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A17 *((volatile unsigned int*)(0x42C90FC4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A18 *((volatile unsigned int*)(0x42C90FC8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A19 *((volatile unsigned int*)(0x42C90FCCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A20 *((volatile unsigned int*)(0x42C90FD0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A21 *((volatile unsigned int*)(0x42C90FD4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A22 *((volatile unsigned int*)(0x42C90FD8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A23 *((volatile unsigned int*)(0x42C90FDCUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A24 *((volatile unsigned int*)(0x42C90FE0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A25 *((volatile unsigned int*)(0x42C90FE4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A26 *((volatile unsigned int*)(0x42C90FE8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A27 *((volatile unsigned int*)(0x42C90FECUL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A28 *((volatile unsigned int*)(0x42C90FF0UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A29 *((volatile unsigned int*)(0x42C90FF4UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A30 *((volatile unsigned int*)(0x42C90FF8UL)) -#define bFM3_ETHERNET_MAC0_MAR31L_A31 *((volatile unsigned int*)(0x42C90FFCUL)) -#define bFM3_ETHERNET_MAC0_BMR_SWR *((volatile unsigned int*)(0x42CA0000UL)) -#define bFM3_ETHERNET_MAC0_BMR_DA *((volatile unsigned int*)(0x42CA0004UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL0 *((volatile unsigned int*)(0x42CA0008UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL1 *((volatile unsigned int*)(0x42CA000CUL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL2 *((volatile unsigned int*)(0x42CA0010UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL3 *((volatile unsigned int*)(0x42CA0014UL)) -#define bFM3_ETHERNET_MAC0_BMR_DSL4 *((volatile unsigned int*)(0x42CA0018UL)) -#define bFM3_ETHERNET_MAC0_BMR_ATDS *((volatile unsigned int*)(0x42CA001CUL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL0 *((volatile unsigned int*)(0x42CA0020UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL1 *((volatile unsigned int*)(0x42CA0024UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL2 *((volatile unsigned int*)(0x42CA0028UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL3 *((volatile unsigned int*)(0x42CA002CUL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL4 *((volatile unsigned int*)(0x42CA0030UL)) -#define bFM3_ETHERNET_MAC0_BMR_PBL5 *((volatile unsigned int*)(0x42CA0034UL)) -#define bFM3_ETHERNET_MAC0_BMR_PR0 *((volatile unsigned int*)(0x42CA0038UL)) -#define bFM3_ETHERNET_MAC0_BMR_PR1 *((volatile unsigned int*)(0x42CA003CUL)) -#define bFM3_ETHERNET_MAC0_BMR_FB *((volatile unsigned int*)(0x42CA0040UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL0 *((volatile unsigned int*)(0x42CA0044UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL1 *((volatile unsigned int*)(0x42CA0048UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL2 *((volatile unsigned int*)(0x42CA004CUL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL3 *((volatile unsigned int*)(0x42CA0050UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL4 *((volatile unsigned int*)(0x42CA0054UL)) -#define bFM3_ETHERNET_MAC0_BMR_RPBL5 *((volatile unsigned int*)(0x42CA0058UL)) -#define bFM3_ETHERNET_MAC0_BMR_USP *((volatile unsigned int*)(0x42CA005CUL)) -#define bFM3_ETHERNET_MAC0_BMR_8XPBL *((volatile unsigned int*)(0x42CA0060UL)) -#define bFM3_ETHERNET_MAC0_BMR_AAL *((volatile unsigned int*)(0x42CA0064UL)) -#define bFM3_ETHERNET_MAC0_BMR_MB *((volatile unsigned int*)(0x42CA0068UL)) -#define bFM3_ETHERNET_MAC0_BMR_TXPR *((volatile unsigned int*)(0x42CA006CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD0 *((volatile unsigned int*)(0x42CA0080UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD1 *((volatile unsigned int*)(0x42CA0084UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD2 *((volatile unsigned int*)(0x42CA0088UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD3 *((volatile unsigned int*)(0x42CA008CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD4 *((volatile unsigned int*)(0x42CA0090UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD5 *((volatile unsigned int*)(0x42CA0094UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD6 *((volatile unsigned int*)(0x42CA0098UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD7 *((volatile unsigned int*)(0x42CA009CUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD8 *((volatile unsigned int*)(0x42CA00A0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD9 *((volatile unsigned int*)(0x42CA00A4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD10 *((volatile unsigned int*)(0x42CA00A8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD11 *((volatile unsigned int*)(0x42CA00ACUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD12 *((volatile unsigned int*)(0x42CA00B0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD13 *((volatile unsigned int*)(0x42CA00B4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD14 *((volatile unsigned int*)(0x42CA00B8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD15 *((volatile unsigned int*)(0x42CA00BCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD16 *((volatile unsigned int*)(0x42CA00C0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD17 *((volatile unsigned int*)(0x42CA00C4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD18 *((volatile unsigned int*)(0x42CA00C8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD19 *((volatile unsigned int*)(0x42CA00CCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD20 *((volatile unsigned int*)(0x42CA00D0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD21 *((volatile unsigned int*)(0x42CA00D4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD22 *((volatile unsigned int*)(0x42CA00D8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD23 *((volatile unsigned int*)(0x42CA00DCUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD24 *((volatile unsigned int*)(0x42CA00E0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD25 *((volatile unsigned int*)(0x42CA00E4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD26 *((volatile unsigned int*)(0x42CA00E8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD27 *((volatile unsigned int*)(0x42CA00ECUL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD28 *((volatile unsigned int*)(0x42CA00F0UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD29 *((volatile unsigned int*)(0x42CA00F4UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD30 *((volatile unsigned int*)(0x42CA00F8UL)) -#define bFM3_ETHERNET_MAC0_TPDR_TPD31 *((volatile unsigned int*)(0x42CA00FCUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD0 *((volatile unsigned int*)(0x42CA0100UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD1 *((volatile unsigned int*)(0x42CA0104UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD2 *((volatile unsigned int*)(0x42CA0108UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD3 *((volatile unsigned int*)(0x42CA010CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD4 *((volatile unsigned int*)(0x42CA0110UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD5 *((volatile unsigned int*)(0x42CA0114UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD6 *((volatile unsigned int*)(0x42CA0118UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD7 *((volatile unsigned int*)(0x42CA011CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD8 *((volatile unsigned int*)(0x42CA0120UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD9 *((volatile unsigned int*)(0x42CA0124UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD10 *((volatile unsigned int*)(0x42CA0128UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD11 *((volatile unsigned int*)(0x42CA012CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD12 *((volatile unsigned int*)(0x42CA0130UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD13 *((volatile unsigned int*)(0x42CA0134UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD14 *((volatile unsigned int*)(0x42CA0138UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD15 *((volatile unsigned int*)(0x42CA013CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD16 *((volatile unsigned int*)(0x42CA0140UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD17 *((volatile unsigned int*)(0x42CA0144UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD18 *((volatile unsigned int*)(0x42CA0148UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD19 *((volatile unsigned int*)(0x42CA014CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD20 *((volatile unsigned int*)(0x42CA0150UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD21 *((volatile unsigned int*)(0x42CA0154UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD22 *((volatile unsigned int*)(0x42CA0158UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD23 *((volatile unsigned int*)(0x42CA015CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD24 *((volatile unsigned int*)(0x42CA0160UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD25 *((volatile unsigned int*)(0x42CA0164UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD26 *((volatile unsigned int*)(0x42CA0168UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD27 *((volatile unsigned int*)(0x42CA016CUL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD28 *((volatile unsigned int*)(0x42CA0170UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD29 *((volatile unsigned int*)(0x42CA0174UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD30 *((volatile unsigned int*)(0x42CA0178UL)) -#define bFM3_ETHERNET_MAC0_RPDR_RPD31 *((volatile unsigned int*)(0x42CA017CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL2 *((volatile unsigned int*)(0x42CA0188UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL3 *((volatile unsigned int*)(0x42CA018CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL4 *((volatile unsigned int*)(0x42CA0190UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL5 *((volatile unsigned int*)(0x42CA0194UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL6 *((volatile unsigned int*)(0x42CA0198UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL7 *((volatile unsigned int*)(0x42CA019CUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL8 *((volatile unsigned int*)(0x42CA01A0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL9 *((volatile unsigned int*)(0x42CA01A4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL10 *((volatile unsigned int*)(0x42CA01A8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL11 *((volatile unsigned int*)(0x42CA01ACUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL12 *((volatile unsigned int*)(0x42CA01B0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL13 *((volatile unsigned int*)(0x42CA01B4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL14 *((volatile unsigned int*)(0x42CA01B8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL15 *((volatile unsigned int*)(0x42CA01BCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL16 *((volatile unsigned int*)(0x42CA01C0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL17 *((volatile unsigned int*)(0x42CA01C4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL18 *((volatile unsigned int*)(0x42CA01C8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL19 *((volatile unsigned int*)(0x42CA01CCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL20 *((volatile unsigned int*)(0x42CA01D0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL21 *((volatile unsigned int*)(0x42CA01D4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL22 *((volatile unsigned int*)(0x42CA01D8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL23 *((volatile unsigned int*)(0x42CA01DCUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL24 *((volatile unsigned int*)(0x42CA01E0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL25 *((volatile unsigned int*)(0x42CA01E4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL26 *((volatile unsigned int*)(0x42CA01E8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL27 *((volatile unsigned int*)(0x42CA01ECUL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL28 *((volatile unsigned int*)(0x42CA01F0UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL29 *((volatile unsigned int*)(0x42CA01F4UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL30 *((volatile unsigned int*)(0x42CA01F8UL)) -#define bFM3_ETHERNET_MAC0_RDLAR_SRL31 *((volatile unsigned int*)(0x42CA01FCUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL2 *((volatile unsigned int*)(0x42CA0208UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL3 *((volatile unsigned int*)(0x42CA020CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL4 *((volatile unsigned int*)(0x42CA0210UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL5 *((volatile unsigned int*)(0x42CA0214UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL6 *((volatile unsigned int*)(0x42CA0218UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL7 *((volatile unsigned int*)(0x42CA021CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL8 *((volatile unsigned int*)(0x42CA0220UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL9 *((volatile unsigned int*)(0x42CA0224UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL10 *((volatile unsigned int*)(0x42CA0228UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL11 *((volatile unsigned int*)(0x42CA022CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL12 *((volatile unsigned int*)(0x42CA0230UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL13 *((volatile unsigned int*)(0x42CA0234UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL14 *((volatile unsigned int*)(0x42CA0238UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL15 *((volatile unsigned int*)(0x42CA023CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL16 *((volatile unsigned int*)(0x42CA0240UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL17 *((volatile unsigned int*)(0x42CA0244UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL18 *((volatile unsigned int*)(0x42CA0248UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL19 *((volatile unsigned int*)(0x42CA024CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL20 *((volatile unsigned int*)(0x42CA0250UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL21 *((volatile unsigned int*)(0x42CA0254UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL22 *((volatile unsigned int*)(0x42CA0258UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL23 *((volatile unsigned int*)(0x42CA025CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL24 *((volatile unsigned int*)(0x42CA0260UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL25 *((volatile unsigned int*)(0x42CA0264UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL26 *((volatile unsigned int*)(0x42CA0268UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL27 *((volatile unsigned int*)(0x42CA026CUL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL28 *((volatile unsigned int*)(0x42CA0270UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL29 *((volatile unsigned int*)(0x42CA0274UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL30 *((volatile unsigned int*)(0x42CA0278UL)) -#define bFM3_ETHERNET_MAC0_TDLAR_STL31 *((volatile unsigned int*)(0x42CA027CUL)) -#define bFM3_ETHERNET_MAC0_SR_TI *((volatile unsigned int*)(0x42CA0280UL)) -#define bFM3_ETHERNET_MAC0_SR_TPS *((volatile unsigned int*)(0x42CA0284UL)) -#define bFM3_ETHERNET_MAC0_SR_TU *((volatile unsigned int*)(0x42CA0288UL)) -#define bFM3_ETHERNET_MAC0_SR_TJT *((volatile unsigned int*)(0x42CA028CUL)) -#define bFM3_ETHERNET_MAC0_SR_OVF *((volatile unsigned int*)(0x42CA0290UL)) -#define bFM3_ETHERNET_MAC0_SR_UNF *((volatile unsigned int*)(0x42CA0294UL)) -#define bFM3_ETHERNET_MAC0_SR_RI *((volatile unsigned int*)(0x42CA0298UL)) -#define bFM3_ETHERNET_MAC0_SR_RU *((volatile unsigned int*)(0x42CA029CUL)) -#define bFM3_ETHERNET_MAC0_SR_RPS *((volatile unsigned int*)(0x42CA02A0UL)) -#define bFM3_ETHERNET_MAC0_SR_RWT *((volatile unsigned int*)(0x42CA02A4UL)) -#define bFM3_ETHERNET_MAC0_SR_ETI *((volatile unsigned int*)(0x42CA02A8UL)) -#define bFM3_ETHERNET_MAC0_SR_FBI *((volatile unsigned int*)(0x42CA02B4UL)) -#define bFM3_ETHERNET_MAC0_SR_ERI *((volatile unsigned int*)(0x42CA02B8UL)) -#define bFM3_ETHERNET_MAC0_SR_AIS *((volatile unsigned int*)(0x42CA02BCUL)) -#define bFM3_ETHERNET_MAC0_SR_NIS *((volatile unsigned int*)(0x42CA02C0UL)) -#define bFM3_ETHERNET_MAC0_SR_RS0 *((volatile unsigned int*)(0x42CA02C4UL)) -#define bFM3_ETHERNET_MAC0_SR_RS1 *((volatile unsigned int*)(0x42CA02C8UL)) -#define bFM3_ETHERNET_MAC0_SR_RS2 *((volatile unsigned int*)(0x42CA02CCUL)) -#define bFM3_ETHERNET_MAC0_SR_TS0 *((volatile unsigned int*)(0x42CA02D0UL)) -#define bFM3_ETHERNET_MAC0_SR_TS1 *((volatile unsigned int*)(0x42CA02D4UL)) -#define bFM3_ETHERNET_MAC0_SR_TS2 *((volatile unsigned int*)(0x42CA02D8UL)) -#define bFM3_ETHERNET_MAC0_SR_EB0 *((volatile unsigned int*)(0x42CA02DCUL)) -#define bFM3_ETHERNET_MAC0_SR_EB1 *((volatile unsigned int*)(0x42CA02E0UL)) -#define bFM3_ETHERNET_MAC0_SR_EB2 *((volatile unsigned int*)(0x42CA02E4UL)) -#define bFM3_ETHERNET_MAC0_SR_GLI *((volatile unsigned int*)(0x42CA02E8UL)) -#define bFM3_ETHERNET_MAC0_SR_GMI *((volatile unsigned int*)(0x42CA02ECUL)) -#define bFM3_ETHERNET_MAC0_SR_GPI *((volatile unsigned int*)(0x42CA02F0UL)) -#define bFM3_ETHERNET_MAC0_SR_TTI *((volatile unsigned int*)(0x42CA02F4UL)) -#define bFM3_ETHERNET_MAC0_SR_GLPII *((volatile unsigned int*)(0x42CA02F8UL)) -#define bFM3_ETHERNET_MAC0_OMR_SR *((volatile unsigned int*)(0x42CA0304UL)) -#define bFM3_ETHERNET_MAC0_OMR_OSF *((volatile unsigned int*)(0x42CA0308UL)) -#define bFM3_ETHERNET_MAC0_OMR_RTC0 *((volatile unsigned int*)(0x42CA030CUL)) -#define bFM3_ETHERNET_MAC0_OMR_RTC1 *((volatile unsigned int*)(0x42CA0310UL)) -#define bFM3_ETHERNET_MAC0_OMR_FUF *((volatile unsigned int*)(0x42CA0318UL)) -#define bFM3_ETHERNET_MAC0_OMR_FEF *((volatile unsigned int*)(0x42CA031CUL)) -#define bFM3_ETHERNET_MAC0_OMR_ST *((volatile unsigned int*)(0x42CA0334UL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC0 *((volatile unsigned int*)(0x42CA0338UL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC1 *((volatile unsigned int*)(0x42CA033CUL)) -#define bFM3_ETHERNET_MAC0_OMR_TTC2 *((volatile unsigned int*)(0x42CA0340UL)) -#define bFM3_ETHERNET_MAC0_OMR_FTF *((volatile unsigned int*)(0x42CA0350UL)) -#define bFM3_ETHERNET_MAC0_OMR_TSF *((volatile unsigned int*)(0x42CA0354UL)) -#define bFM3_ETHERNET_MAC0_OMR_DFF *((volatile unsigned int*)(0x42CA0360UL)) -#define bFM3_ETHERNET_MAC0_OMR_RSF *((volatile unsigned int*)(0x42CA0364UL)) -#define bFM3_ETHERNET_MAC0_OMR_DT *((volatile unsigned int*)(0x42CA0368UL)) -#define bFM3_ETHERNET_MAC0_IER_TIE *((volatile unsigned int*)(0x42CA0380UL)) -#define bFM3_ETHERNET_MAC0_IER_TSE *((volatile unsigned int*)(0x42CA0384UL)) -#define bFM3_ETHERNET_MAC0_IER_TUE *((volatile unsigned int*)(0x42CA0388UL)) -#define bFM3_ETHERNET_MAC0_IER_TJE *((volatile unsigned int*)(0x42CA038CUL)) -#define bFM3_ETHERNET_MAC0_IER_OVE *((volatile unsigned int*)(0x42CA0390UL)) -#define bFM3_ETHERNET_MAC0_IER_UNE *((volatile unsigned int*)(0x42CA0394UL)) -#define bFM3_ETHERNET_MAC0_IER_RIE *((volatile unsigned int*)(0x42CA0398UL)) -#define bFM3_ETHERNET_MAC0_IER_RUE *((volatile unsigned int*)(0x42CA039CUL)) -#define bFM3_ETHERNET_MAC0_IER_RSE *((volatile unsigned int*)(0x42CA03A0UL)) -#define bFM3_ETHERNET_MAC0_IER_RWE *((volatile unsigned int*)(0x42CA03A4UL)) -#define bFM3_ETHERNET_MAC0_IER_ETE *((volatile unsigned int*)(0x42CA03A8UL)) -#define bFM3_ETHERNET_MAC0_IER_FBE *((volatile unsigned int*)(0x42CA03B4UL)) -#define bFM3_ETHERNET_MAC0_IER_ERE *((volatile unsigned int*)(0x42CA03B8UL)) -#define bFM3_ETHERNET_MAC0_IER_AIE *((volatile unsigned int*)(0x42CA03BCUL)) -#define bFM3_ETHERNET_MAC0_IER_NIE *((volatile unsigned int*)(0x42CA03C0UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42CA0400UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42CA0404UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42CA0408UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42CA040CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42CA0410UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42CA0414UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42CA0418UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42CA041CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42CA0420UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42CA0424UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42CA0428UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42CA042CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42CA0430UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42CA0434UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42CA0438UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42CA043CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH *((volatile unsigned int*)(0x42CA0440UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42CA0444UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42CA0448UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42CA044CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42CA0450UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42CA0454UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42CA0458UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42CA045CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42CA0460UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42CA0464UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42CA0468UL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42CA046CUL)) -#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF *((volatile unsigned int*)(0x42CA0470UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0 *((volatile unsigned int*)(0x42CA0480UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1 *((volatile unsigned int*)(0x42CA0484UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2 *((volatile unsigned int*)(0x42CA0488UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3 *((volatile unsigned int*)(0x42CA048CUL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4 *((volatile unsigned int*)(0x42CA0490UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5 *((volatile unsigned int*)(0x42CA0494UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6 *((volatile unsigned int*)(0x42CA0498UL)) -#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7 *((volatile unsigned int*)(0x42CA049CUL)) -#define bFM3_ETHERNET_MAC0_AHBSR_AHBS *((volatile unsigned int*)(0x42CA0580UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42CA0900UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42CA0904UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42CA0908UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42CA090CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42CA0910UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42CA0914UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42CA0918UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42CA091CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42CA0920UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42CA0924UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42CA0928UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42CA092CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42CA0930UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42CA0934UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42CA0938UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42CA093CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42CA0940UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42CA0944UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42CA0948UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42CA094CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42CA0950UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42CA0954UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42CA0958UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42CA095CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42CA0960UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42CA0964UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42CA0968UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42CA096CUL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42CA0970UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42CA0974UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42CA0978UL)) -#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42CA097CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42CA0980UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42CA0984UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42CA0988UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42CA098CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42CA0990UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42CA0994UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42CA0998UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42CA099CUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42CA09A0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42CA09A4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42CA09A8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42CA09ACUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42CA09B0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42CA09B4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42CA09B8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42CA09BCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42CA09C0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42CA09C4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42CA09C8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42CA09CCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42CA09D0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42CA09D4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42CA09D8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42CA09DCUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42CA09E0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42CA09E4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42CA09E8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42CA09ECUL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42CA09F0UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42CA09F4UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42CA09F8UL)) -#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42CA09FCUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42CA0A00UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42CA0A04UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42CA0A08UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42CA0A0CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42CA0A10UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42CA0A14UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42CA0A18UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42CA0A1CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42CA0A20UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42CA0A24UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42CA0A28UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42CA0A2CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42CA0A30UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42CA0A34UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42CA0A38UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42CA0A3CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42CA0A40UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42CA0A44UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42CA0A48UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42CA0A4CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42CA0A50UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42CA0A54UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42CA0A58UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42CA0A5CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42CA0A60UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42CA0A64UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42CA0A68UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42CA0A6CUL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42CA0A70UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42CA0A74UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42CA0A78UL)) -#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42CA0A7CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42CA0A80UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42CA0A84UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42CA0A88UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42CA0A8CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42CA0A90UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42CA0A94UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42CA0A98UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42CA0A9CUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42CA0AA0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42CA0AA4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42CA0AA8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42CA0AACUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42CA0AB0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42CA0AB4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42CA0AB8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42CA0ABCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42CA0AC0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42CA0AC4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42CA0AC8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42CA0ACCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42CA0AD0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42CA0AD4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42CA0AD8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42CA0ADCUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42CA0AE0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42CA0AE4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42CA0AE8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42CA0AECUL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42CA0AF0UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42CA0AF4UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42CA0AF8UL)) -#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42CA0AFCUL)) - -/* ETHERNET-MAC-CONTROL registers */ -#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE *((volatile unsigned int*)(0x42CC0000UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0 *((volatile unsigned int*)(0x42CC0020UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1 *((volatile unsigned int*)(0x42CC0024UL)) -#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL *((volatile unsigned int*)(0x42CC0070UL)) -#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0 *((volatile unsigned int*)(0x42CC0100UL)) -#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1 *((volatile unsigned int*)(0x42CC0104UL)) - -/* ETHERNET-MAC1 registers*/ -#define bFM3_ETHERNET_MAC1_MCR_RE *((volatile unsigned int*)(0x42CE0008UL)) -#define bFM3_ETHERNET_MAC1_MCR_TE *((volatile unsigned int*)(0x42CE000CUL)) -#define bFM3_ETHERNET_MAC1_MCR_DC *((volatile unsigned int*)(0x42CE0010UL)) -#define bFM3_ETHERNET_MAC1_MCR_BL0 *((volatile unsigned int*)(0x42CE0014UL)) -#define bFM3_ETHERNET_MAC1_MCR_BL1 *((volatile unsigned int*)(0x42CE0018UL)) -#define bFM3_ETHERNET_MAC1_MCR_ACS *((volatile unsigned int*)(0x42CE001CUL)) -#define bFM3_ETHERNET_MAC1_MCR_LUD *((volatile unsigned int*)(0x42CE0020UL)) -#define bFM3_ETHERNET_MAC1_MCR_DR *((volatile unsigned int*)(0x42CE0024UL)) -#define bFM3_ETHERNET_MAC1_MCR_IPC *((volatile unsigned int*)(0x42CE0028UL)) -#define bFM3_ETHERNET_MAC1_MCR_DM *((volatile unsigned int*)(0x42CE002CUL)) -#define bFM3_ETHERNET_MAC1_MCR_LM *((volatile unsigned int*)(0x42CE0030UL)) -#define bFM3_ETHERNET_MAC1_MCR_DO *((volatile unsigned int*)(0x42CE0034UL)) -#define bFM3_ETHERNET_MAC1_MCR_FES *((volatile unsigned int*)(0x42CE0038UL)) -#define bFM3_ETHERNET_MAC1_MCR_PS *((volatile unsigned int*)(0x42CE003CUL)) -#define bFM3_ETHERNET_MAC1_MCR_DCRS *((volatile unsigned int*)(0x42CE0040UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG0 *((volatile unsigned int*)(0x42CE0044UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG1 *((volatile unsigned int*)(0x42CE0048UL)) -#define bFM3_ETHERNET_MAC1_MCR_IFG2 *((volatile unsigned int*)(0x42CE004CUL)) -#define bFM3_ETHERNET_MAC1_MCR_JE *((volatile unsigned int*)(0x42CE0050UL)) -#define bFM3_ETHERNET_MAC1_MCR_BE *((volatile unsigned int*)(0x42CE0054UL)) -#define bFM3_ETHERNET_MAC1_MCR_JD *((volatile unsigned int*)(0x42CE0058UL)) -#define bFM3_ETHERNET_MAC1_MCR_WD *((volatile unsigned int*)(0x42CE005CUL)) -#define bFM3_ETHERNET_MAC1_MCR_TC *((volatile unsigned int*)(0x42CE0060UL)) -#define bFM3_ETHERNET_MAC1_MCR_CST *((volatile unsigned int*)(0x42CE0064UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PR *((volatile unsigned int*)(0x42CE0080UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HUC *((volatile unsigned int*)(0x42CE0084UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HMC *((volatile unsigned int*)(0x42CE0088UL)) -#define bFM3_ETHERNET_MAC1_MFFR_DAIF *((volatile unsigned int*)(0x42CE008CUL)) -#define bFM3_ETHERNET_MAC1_MFFR_PM *((volatile unsigned int*)(0x42CE0090UL)) -#define bFM3_ETHERNET_MAC1_MFFR_DB *((volatile unsigned int*)(0x42CE0094UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PCF0 *((volatile unsigned int*)(0x42CE0098UL)) -#define bFM3_ETHERNET_MAC1_MFFR_PCF1 *((volatile unsigned int*)(0x42CE009CUL)) -#define bFM3_ETHERNET_MAC1_MFFR_SAIF *((volatile unsigned int*)(0x42CE00A0UL)) -#define bFM3_ETHERNET_MAC1_MFFR_SAF *((volatile unsigned int*)(0x42CE00A4UL)) -#define bFM3_ETHERNET_MAC1_MFFR_HPF *((volatile unsigned int*)(0x42CE00A8UL)) -#define bFM3_ETHERNET_MAC1_MFFR_RA *((volatile unsigned int*)(0x42CE00FCUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH0 *((volatile unsigned int*)(0x42CE0100UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH1 *((volatile unsigned int*)(0x42CE0104UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH2 *((volatile unsigned int*)(0x42CE0108UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH3 *((volatile unsigned int*)(0x42CE010CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH4 *((volatile unsigned int*)(0x42CE0110UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH5 *((volatile unsigned int*)(0x42CE0114UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH6 *((volatile unsigned int*)(0x42CE0118UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH7 *((volatile unsigned int*)(0x42CE011CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH8 *((volatile unsigned int*)(0x42CE0120UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH9 *((volatile unsigned int*)(0x42CE0124UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH10 *((volatile unsigned int*)(0x42CE0128UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH11 *((volatile unsigned int*)(0x42CE012CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH12 *((volatile unsigned int*)(0x42CE0130UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH13 *((volatile unsigned int*)(0x42CE0134UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH14 *((volatile unsigned int*)(0x42CE0138UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH15 *((volatile unsigned int*)(0x42CE013CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH16 *((volatile unsigned int*)(0x42CE0140UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH17 *((volatile unsigned int*)(0x42CE0144UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH18 *((volatile unsigned int*)(0x42CE0148UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH19 *((volatile unsigned int*)(0x42CE014CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH20 *((volatile unsigned int*)(0x42CE0150UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH21 *((volatile unsigned int*)(0x42CE0154UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH22 *((volatile unsigned int*)(0x42CE0158UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH23 *((volatile unsigned int*)(0x42CE015CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH24 *((volatile unsigned int*)(0x42CE0160UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH25 *((volatile unsigned int*)(0x42CE0164UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH26 *((volatile unsigned int*)(0x42CE0168UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH27 *((volatile unsigned int*)(0x42CE016CUL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH28 *((volatile unsigned int*)(0x42CE0170UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH29 *((volatile unsigned int*)(0x42CE0174UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH30 *((volatile unsigned int*)(0x42CE0178UL)) -#define bFM3_ETHERNET_MAC1_MHTRH_HTH31 *((volatile unsigned int*)(0x42CE017CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL0 *((volatile unsigned int*)(0x42CE0180UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL1 *((volatile unsigned int*)(0x42CE0184UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL2 *((volatile unsigned int*)(0x42CE0188UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL3 *((volatile unsigned int*)(0x42CE018CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL4 *((volatile unsigned int*)(0x42CE0190UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL5 *((volatile unsigned int*)(0x42CE0194UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL6 *((volatile unsigned int*)(0x42CE0198UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL7 *((volatile unsigned int*)(0x42CE019CUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL8 *((volatile unsigned int*)(0x42CE01A0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL9 *((volatile unsigned int*)(0x42CE01A4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL10 *((volatile unsigned int*)(0x42CE01A8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL11 *((volatile unsigned int*)(0x42CE01ACUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL12 *((volatile unsigned int*)(0x42CE01B0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL13 *((volatile unsigned int*)(0x42CE01B4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL14 *((volatile unsigned int*)(0x42CE01B8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL15 *((volatile unsigned int*)(0x42CE01BCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL16 *((volatile unsigned int*)(0x42CE01C0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL17 *((volatile unsigned int*)(0x42CE01C4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL18 *((volatile unsigned int*)(0x42CE01C8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL19 *((volatile unsigned int*)(0x42CE01CCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL20 *((volatile unsigned int*)(0x42CE01D0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL21 *((volatile unsigned int*)(0x42CE01D4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL22 *((volatile unsigned int*)(0x42CE01D8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL23 *((volatile unsigned int*)(0x42CE01DCUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL24 *((volatile unsigned int*)(0x42CE01E0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL25 *((volatile unsigned int*)(0x42CE01E4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL26 *((volatile unsigned int*)(0x42CE01E8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL27 *((volatile unsigned int*)(0x42CE01ECUL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL28 *((volatile unsigned int*)(0x42CE01F0UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL29 *((volatile unsigned int*)(0x42CE01F4UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL30 *((volatile unsigned int*)(0x42CE01F8UL)) -#define bFM3_ETHERNET_MAC1_MHTRL_HTL31 *((volatile unsigned int*)(0x42CE01FCUL)) -#define bFM3_ETHERNET_MAC1_GAR_GB *((volatile unsigned int*)(0x42CE0200UL)) -#define bFM3_ETHERNET_MAC1_GAR_GW *((volatile unsigned int*)(0x42CE0204UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR0 *((volatile unsigned int*)(0x42CE0208UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR1 *((volatile unsigned int*)(0x42CE020CUL)) -#define bFM3_ETHERNET_MAC1_GAR_CR2 *((volatile unsigned int*)(0x42CE0210UL)) -#define bFM3_ETHERNET_MAC1_GAR_CR3 *((volatile unsigned int*)(0x42CE0214UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR0 *((volatile unsigned int*)(0x42CE0218UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR1 *((volatile unsigned int*)(0x42CE021CUL)) -#define bFM3_ETHERNET_MAC1_GAR_GR2 *((volatile unsigned int*)(0x42CE0220UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR3 *((volatile unsigned int*)(0x42CE0224UL)) -#define bFM3_ETHERNET_MAC1_GAR_GR4 *((volatile unsigned int*)(0x42CE0228UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA0 *((volatile unsigned int*)(0x42CE022CUL)) -#define bFM3_ETHERNET_MAC1_GAR_PA1 *((volatile unsigned int*)(0x42CE0230UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA2 *((volatile unsigned int*)(0x42CE0234UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA3 *((volatile unsigned int*)(0x42CE0238UL)) -#define bFM3_ETHERNET_MAC1_GAR_PA4 *((volatile unsigned int*)(0x42CE023CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD0 *((volatile unsigned int*)(0x42CE0280UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD1 *((volatile unsigned int*)(0x42CE0284UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD2 *((volatile unsigned int*)(0x42CE0288UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD3 *((volatile unsigned int*)(0x42CE028CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD4 *((volatile unsigned int*)(0x42CE0290UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD5 *((volatile unsigned int*)(0x42CE0294UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD6 *((volatile unsigned int*)(0x42CE0298UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD7 *((volatile unsigned int*)(0x42CE029CUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD8 *((volatile unsigned int*)(0x42CE02A0UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD9 *((volatile unsigned int*)(0x42CE02A4UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD10 *((volatile unsigned int*)(0x42CE02A8UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD11 *((volatile unsigned int*)(0x42CE02ACUL)) -#define bFM3_ETHERNET_MAC1_GDR_GD12 *((volatile unsigned int*)(0x42CE02B0UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD13 *((volatile unsigned int*)(0x42CE02B4UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD14 *((volatile unsigned int*)(0x42CE02B8UL)) -#define bFM3_ETHERNET_MAC1_GDR_GD15 *((volatile unsigned int*)(0x42CE02BCUL)) -#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA *((volatile unsigned int*)(0x42CE0300UL)) -#define bFM3_ETHERNET_MAC1_FCR_TFE *((volatile unsigned int*)(0x42CE0304UL)) -#define bFM3_ETHERNET_MAC1_FCR_RFE *((volatile unsigned int*)(0x42CE0308UL)) -#define bFM3_ETHERNET_MAC1_FCR_UP *((volatile unsigned int*)(0x42CE030CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PLT0 *((volatile unsigned int*)(0x42CE0310UL)) -#define bFM3_ETHERNET_MAC1_FCR_PLT1 *((volatile unsigned int*)(0x42CE0314UL)) -#define bFM3_ETHERNET_MAC1_FCR_DZPQ *((volatile unsigned int*)(0x42CE031CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT0 *((volatile unsigned int*)(0x42CE0340UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT1 *((volatile unsigned int*)(0x42CE0344UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT2 *((volatile unsigned int*)(0x42CE0348UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT3 *((volatile unsigned int*)(0x42CE034CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT4 *((volatile unsigned int*)(0x42CE0350UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT5 *((volatile unsigned int*)(0x42CE0354UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT6 *((volatile unsigned int*)(0x42CE0358UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT7 *((volatile unsigned int*)(0x42CE035CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT8 *((volatile unsigned int*)(0x42CE0360UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT9 *((volatile unsigned int*)(0x42CE0364UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT10 *((volatile unsigned int*)(0x42CE0368UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT11 *((volatile unsigned int*)(0x42CE036CUL)) -#define bFM3_ETHERNET_MAC1_FCR_PT12 *((volatile unsigned int*)(0x42CE0370UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT13 *((volatile unsigned int*)(0x42CE0374UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT14 *((volatile unsigned int*)(0x42CE0378UL)) -#define bFM3_ETHERNET_MAC1_FCR_PT15 *((volatile unsigned int*)(0x42CE037CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL0 *((volatile unsigned int*)(0x42CE0380UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL1 *((volatile unsigned int*)(0x42CE0384UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL2 *((volatile unsigned int*)(0x42CE0388UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL3 *((volatile unsigned int*)(0x42CE038CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL4 *((volatile unsigned int*)(0x42CE0390UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL5 *((volatile unsigned int*)(0x42CE0394UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL6 *((volatile unsigned int*)(0x42CE0398UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL7 *((volatile unsigned int*)(0x42CE039CUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL8 *((volatile unsigned int*)(0x42CE03A0UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL9 *((volatile unsigned int*)(0x42CE03A4UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL10 *((volatile unsigned int*)(0x42CE03A8UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL11 *((volatile unsigned int*)(0x42CE03ACUL)) -#define bFM3_ETHERNET_MAC1_VTR_VL12 *((volatile unsigned int*)(0x42CE03B0UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL13 *((volatile unsigned int*)(0x42CE03B4UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL14 *((volatile unsigned int*)(0x42CE03B8UL)) -#define bFM3_ETHERNET_MAC1_VTR_VL15 *((volatile unsigned int*)(0x42CE03BCUL)) -#define bFM3_ETHERNET_MAC1_VTR_ETV *((volatile unsigned int*)(0x42CE03C0UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0 *((volatile unsigned int*)(0x42CE0500UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1 *((volatile unsigned int*)(0x42CE0504UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2 *((volatile unsigned int*)(0x42CE0508UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3 *((volatile unsigned int*)(0x42CE050CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4 *((volatile unsigned int*)(0x42CE0510UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5 *((volatile unsigned int*)(0x42CE0514UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6 *((volatile unsigned int*)(0x42CE0518UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7 *((volatile unsigned int*)(0x42CE051CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8 *((volatile unsigned int*)(0x42CE0520UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9 *((volatile unsigned int*)(0x42CE0524UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10 *((volatile unsigned int*)(0x42CE0528UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11 *((volatile unsigned int*)(0x42CE052CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12 *((volatile unsigned int*)(0x42CE0530UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13 *((volatile unsigned int*)(0x42CE0534UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14 *((volatile unsigned int*)(0x42CE0538UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15 *((volatile unsigned int*)(0x42CE053CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16 *((volatile unsigned int*)(0x42CE0540UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17 *((volatile unsigned int*)(0x42CE0544UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18 *((volatile unsigned int*)(0x42CE0548UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19 *((volatile unsigned int*)(0x42CE054CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20 *((volatile unsigned int*)(0x42CE0550UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21 *((volatile unsigned int*)(0x42CE0554UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22 *((volatile unsigned int*)(0x42CE0558UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23 *((volatile unsigned int*)(0x42CE055CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24 *((volatile unsigned int*)(0x42CE0560UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25 *((volatile unsigned int*)(0x42CE0564UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26 *((volatile unsigned int*)(0x42CE0568UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27 *((volatile unsigned int*)(0x42CE056CUL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28 *((volatile unsigned int*)(0x42CE0570UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29 *((volatile unsigned int*)(0x42CE0574UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30 *((volatile unsigned int*)(0x42CE0578UL)) -#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31 *((volatile unsigned int*)(0x42CE057CUL)) -#define bFM3_ETHERNET_MAC1_PMTR_PD *((volatile unsigned int*)(0x42CE0580UL)) -#define bFM3_ETHERNET_MAC1_PMTR_MPE *((volatile unsigned int*)(0x42CE0584UL)) -#define bFM3_ETHERNET_MAC1_PMTR_WFE *((volatile unsigned int*)(0x42CE0588UL)) -#define bFM3_ETHERNET_MAC1_PMTR_MPR *((volatile unsigned int*)(0x42CE0594UL)) -#define bFM3_ETHERNET_MAC1_PMTR_WPR *((volatile unsigned int*)(0x42CE0598UL)) -#define bFM3_ETHERNET_MAC1_PMTR_GU *((volatile unsigned int*)(0x42CE05A4UL)) -#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR *((volatile unsigned int*)(0x42CE05FCUL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN *((volatile unsigned int*)(0x42CE0600UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX *((volatile unsigned int*)(0x42CE0604UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN *((volatile unsigned int*)(0x42CE0608UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX *((volatile unsigned int*)(0x42CE060CUL)) -#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST *((volatile unsigned int*)(0x42CE0620UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST *((volatile unsigned int*)(0x42CE0624UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN *((volatile unsigned int*)(0x42CE0640UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_PLS *((volatile unsigned int*)(0x42CE0644UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN *((volatile unsigned int*)(0x42CE0648UL)) -#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA *((volatile unsigned int*)(0x42CE064CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT0 *((volatile unsigned int*)(0x42CE0680UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT1 *((volatile unsigned int*)(0x42CE0684UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT2 *((volatile unsigned int*)(0x42CE0688UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT3 *((volatile unsigned int*)(0x42CE068CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT4 *((volatile unsigned int*)(0x42CE0690UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT5 *((volatile unsigned int*)(0x42CE0694UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT6 *((volatile unsigned int*)(0x42CE0698UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT7 *((volatile unsigned int*)(0x42CE069CUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT8 *((volatile unsigned int*)(0x42CE06A0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT9 *((volatile unsigned int*)(0x42CE06A4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT10 *((volatile unsigned int*)(0x42CE06A8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT11 *((volatile unsigned int*)(0x42CE06ACUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT12 *((volatile unsigned int*)(0x42CE06B0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT13 *((volatile unsigned int*)(0x42CE06B4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT14 *((volatile unsigned int*)(0x42CE06B8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_TWT15 *((volatile unsigned int*)(0x42CE06BCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT0 *((volatile unsigned int*)(0x42CE06C0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT1 *((volatile unsigned int*)(0x42CE06C4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT2 *((volatile unsigned int*)(0x42CE06C8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT3 *((volatile unsigned int*)(0x42CE06CCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT4 *((volatile unsigned int*)(0x42CE06D0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT5 *((volatile unsigned int*)(0x42CE06D4UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT6 *((volatile unsigned int*)(0x42CE06D8UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT7 *((volatile unsigned int*)(0x42CE06DCUL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT8 *((volatile unsigned int*)(0x42CE06E0UL)) -#define bFM3_ETHERNET_MAC1_LPITCR_LIT9 *((volatile unsigned int*)(0x42CE06E4UL)) -#define bFM3_ETHERNET_MAC1_ISR_RGIS *((volatile unsigned int*)(0x42CE0700UL)) -#define bFM3_ETHERNET_MAC1_ISR_PIS *((volatile unsigned int*)(0x42CE070CUL)) -#define bFM3_ETHERNET_MAC1_ISR_MIS *((volatile unsigned int*)(0x42CE0710UL)) -#define bFM3_ETHERNET_MAC1_ISR_RIS *((volatile unsigned int*)(0x42CE0714UL)) -#define bFM3_ETHERNET_MAC1_ISR_TIS *((volatile unsigned int*)(0x42CE0718UL)) -#define bFM3_ETHERNET_MAC1_ISR_COIS *((volatile unsigned int*)(0x42CE071CUL)) -#define bFM3_ETHERNET_MAC1_ISR_TSIS *((volatile unsigned int*)(0x42CE0724UL)) -#define bFM3_ETHERNET_MAC1_ISR_LPIIS *((volatile unsigned int*)(0x42CE0728UL)) -#define bFM3_ETHERNET_MAC1_IMR_RGIM *((volatile unsigned int*)(0x42CE0780UL)) -#define bFM3_ETHERNET_MAC1_IMR_PIM *((volatile unsigned int*)(0x42CE078CUL)) -#define bFM3_ETHERNET_MAC1_IMR_TSIM *((volatile unsigned int*)(0x42CE0794UL)) -#define bFM3_ETHERNET_MAC1_IMR_LPIIM *((volatile unsigned int*)(0x42CE0798UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A32 *((volatile unsigned int*)(0x42CE0800UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A33 *((volatile unsigned int*)(0x42CE0804UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A34 *((volatile unsigned int*)(0x42CE0808UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A35 *((volatile unsigned int*)(0x42CE080CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A36 *((volatile unsigned int*)(0x42CE0810UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A37 *((volatile unsigned int*)(0x42CE0814UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A38 *((volatile unsigned int*)(0x42CE0818UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A39 *((volatile unsigned int*)(0x42CE081CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A40 *((volatile unsigned int*)(0x42CE0820UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A41 *((volatile unsigned int*)(0x42CE0824UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A42 *((volatile unsigned int*)(0x42CE0828UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A43 *((volatile unsigned int*)(0x42CE082CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A44 *((volatile unsigned int*)(0x42CE0830UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A45 *((volatile unsigned int*)(0x42CE0834UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A46 *((volatile unsigned int*)(0x42CE0838UL)) -#define bFM3_ETHERNET_MAC1_MAR0H_A47 *((volatile unsigned int*)(0x42CE083CUL)) -#define bFM3_ETHERNET_MAC1_MAR0H_MO *((volatile unsigned int*)(0x42CE087CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A0 *((volatile unsigned int*)(0x42CE0880UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A1 *((volatile unsigned int*)(0x42CE0884UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A2 *((volatile unsigned int*)(0x42CE0888UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A3 *((volatile unsigned int*)(0x42CE088CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A4 *((volatile unsigned int*)(0x42CE0890UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A5 *((volatile unsigned int*)(0x42CE0894UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A6 *((volatile unsigned int*)(0x42CE0898UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A7 *((volatile unsigned int*)(0x42CE089CUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A8 *((volatile unsigned int*)(0x42CE08A0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A9 *((volatile unsigned int*)(0x42CE08A4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A10 *((volatile unsigned int*)(0x42CE08A8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A11 *((volatile unsigned int*)(0x42CE08ACUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A12 *((volatile unsigned int*)(0x42CE08B0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A13 *((volatile unsigned int*)(0x42CE08B4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A14 *((volatile unsigned int*)(0x42CE08B8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A15 *((volatile unsigned int*)(0x42CE08BCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A16 *((volatile unsigned int*)(0x42CE08C0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A17 *((volatile unsigned int*)(0x42CE08C4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A18 *((volatile unsigned int*)(0x42CE08C8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A19 *((volatile unsigned int*)(0x42CE08CCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A20 *((volatile unsigned int*)(0x42CE08D0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A21 *((volatile unsigned int*)(0x42CE08D4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A22 *((volatile unsigned int*)(0x42CE08D8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A23 *((volatile unsigned int*)(0x42CE08DCUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A24 *((volatile unsigned int*)(0x42CE08E0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A25 *((volatile unsigned int*)(0x42CE08E4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A26 *((volatile unsigned int*)(0x42CE08E8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A27 *((volatile unsigned int*)(0x42CE08ECUL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A28 *((volatile unsigned int*)(0x42CE08F0UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A29 *((volatile unsigned int*)(0x42CE08F4UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A30 *((volatile unsigned int*)(0x42CE08F8UL)) -#define bFM3_ETHERNET_MAC1_MAR0L_A31 *((volatile unsigned int*)(0x42CE08FCUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A32 *((volatile unsigned int*)(0x42CE0900UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A33 *((volatile unsigned int*)(0x42CE0904UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A34 *((volatile unsigned int*)(0x42CE0908UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A35 *((volatile unsigned int*)(0x42CE090CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A36 *((volatile unsigned int*)(0x42CE0910UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A37 *((volatile unsigned int*)(0x42CE0914UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A38 *((volatile unsigned int*)(0x42CE0918UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A39 *((volatile unsigned int*)(0x42CE091CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A40 *((volatile unsigned int*)(0x42CE0920UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A41 *((volatile unsigned int*)(0x42CE0924UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A42 *((volatile unsigned int*)(0x42CE0928UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A43 *((volatile unsigned int*)(0x42CE092CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A44 *((volatile unsigned int*)(0x42CE0930UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A45 *((volatile unsigned int*)(0x42CE0934UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A46 *((volatile unsigned int*)(0x42CE0938UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_A47 *((volatile unsigned int*)(0x42CE093CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC0 *((volatile unsigned int*)(0x42CE0960UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC1 *((volatile unsigned int*)(0x42CE0964UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC2 *((volatile unsigned int*)(0x42CE0968UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC3 *((volatile unsigned int*)(0x42CE096CUL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC4 *((volatile unsigned int*)(0x42CE0970UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_MBC5 *((volatile unsigned int*)(0x42CE0974UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_SA *((volatile unsigned int*)(0x42CE0978UL)) -#define bFM3_ETHERNET_MAC1_MAR1H_AE *((volatile unsigned int*)(0x42CE097CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A0 *((volatile unsigned int*)(0x42CE0980UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A1 *((volatile unsigned int*)(0x42CE0984UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A2 *((volatile unsigned int*)(0x42CE0988UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A3 *((volatile unsigned int*)(0x42CE098CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A4 *((volatile unsigned int*)(0x42CE0990UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A5 *((volatile unsigned int*)(0x42CE0994UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A6 *((volatile unsigned int*)(0x42CE0998UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A7 *((volatile unsigned int*)(0x42CE099CUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A8 *((volatile unsigned int*)(0x42CE09A0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A9 *((volatile unsigned int*)(0x42CE09A4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A10 *((volatile unsigned int*)(0x42CE09A8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A11 *((volatile unsigned int*)(0x42CE09ACUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A12 *((volatile unsigned int*)(0x42CE09B0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A13 *((volatile unsigned int*)(0x42CE09B4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A14 *((volatile unsigned int*)(0x42CE09B8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A15 *((volatile unsigned int*)(0x42CE09BCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A16 *((volatile unsigned int*)(0x42CE09C0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A17 *((volatile unsigned int*)(0x42CE09C4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A18 *((volatile unsigned int*)(0x42CE09C8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A19 *((volatile unsigned int*)(0x42CE09CCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A20 *((volatile unsigned int*)(0x42CE09D0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A21 *((volatile unsigned int*)(0x42CE09D4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A22 *((volatile unsigned int*)(0x42CE09D8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A23 *((volatile unsigned int*)(0x42CE09DCUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A24 *((volatile unsigned int*)(0x42CE09E0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A25 *((volatile unsigned int*)(0x42CE09E4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A26 *((volatile unsigned int*)(0x42CE09E8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A27 *((volatile unsigned int*)(0x42CE09ECUL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A28 *((volatile unsigned int*)(0x42CE09F0UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A29 *((volatile unsigned int*)(0x42CE09F4UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A30 *((volatile unsigned int*)(0x42CE09F8UL)) -#define bFM3_ETHERNET_MAC1_MAR1L_A31 *((volatile unsigned int*)(0x42CE09FCUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A32 *((volatile unsigned int*)(0x42CE0A00UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A33 *((volatile unsigned int*)(0x42CE0A04UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A34 *((volatile unsigned int*)(0x42CE0A08UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A35 *((volatile unsigned int*)(0x42CE0A0CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A36 *((volatile unsigned int*)(0x42CE0A10UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A37 *((volatile unsigned int*)(0x42CE0A14UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A38 *((volatile unsigned int*)(0x42CE0A18UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A39 *((volatile unsigned int*)(0x42CE0A1CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A40 *((volatile unsigned int*)(0x42CE0A20UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A41 *((volatile unsigned int*)(0x42CE0A24UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A42 *((volatile unsigned int*)(0x42CE0A28UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A43 *((volatile unsigned int*)(0x42CE0A2CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A44 *((volatile unsigned int*)(0x42CE0A30UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A45 *((volatile unsigned int*)(0x42CE0A34UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A46 *((volatile unsigned int*)(0x42CE0A38UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_A47 *((volatile unsigned int*)(0x42CE0A3CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC0 *((volatile unsigned int*)(0x42CE0A60UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC1 *((volatile unsigned int*)(0x42CE0A64UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC2 *((volatile unsigned int*)(0x42CE0A68UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC3 *((volatile unsigned int*)(0x42CE0A6CUL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC4 *((volatile unsigned int*)(0x42CE0A70UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_MBC5 *((volatile unsigned int*)(0x42CE0A74UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_SA *((volatile unsigned int*)(0x42CE0A78UL)) -#define bFM3_ETHERNET_MAC1_MAR2H_AE *((volatile unsigned int*)(0x42CE0A7CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A0 *((volatile unsigned int*)(0x42CE0A80UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A1 *((volatile unsigned int*)(0x42CE0A84UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A2 *((volatile unsigned int*)(0x42CE0A88UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A3 *((volatile unsigned int*)(0x42CE0A8CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A4 *((volatile unsigned int*)(0x42CE0A90UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A5 *((volatile unsigned int*)(0x42CE0A94UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A6 *((volatile unsigned int*)(0x42CE0A98UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A7 *((volatile unsigned int*)(0x42CE0A9CUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A8 *((volatile unsigned int*)(0x42CE0AA0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A9 *((volatile unsigned int*)(0x42CE0AA4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A10 *((volatile unsigned int*)(0x42CE0AA8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A11 *((volatile unsigned int*)(0x42CE0AACUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A12 *((volatile unsigned int*)(0x42CE0AB0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A13 *((volatile unsigned int*)(0x42CE0AB4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A14 *((volatile unsigned int*)(0x42CE0AB8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A15 *((volatile unsigned int*)(0x42CE0ABCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A16 *((volatile unsigned int*)(0x42CE0AC0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A17 *((volatile unsigned int*)(0x42CE0AC4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A18 *((volatile unsigned int*)(0x42CE0AC8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A19 *((volatile unsigned int*)(0x42CE0ACCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A20 *((volatile unsigned int*)(0x42CE0AD0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A21 *((volatile unsigned int*)(0x42CE0AD4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A22 *((volatile unsigned int*)(0x42CE0AD8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A23 *((volatile unsigned int*)(0x42CE0ADCUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A24 *((volatile unsigned int*)(0x42CE0AE0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A25 *((volatile unsigned int*)(0x42CE0AE4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A26 *((volatile unsigned int*)(0x42CE0AE8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A27 *((volatile unsigned int*)(0x42CE0AECUL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A28 *((volatile unsigned int*)(0x42CE0AF0UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A29 *((volatile unsigned int*)(0x42CE0AF4UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A30 *((volatile unsigned int*)(0x42CE0AF8UL)) -#define bFM3_ETHERNET_MAC1_MAR2L_A31 *((volatile unsigned int*)(0x42CE0AFCUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A32 *((volatile unsigned int*)(0x42CE0B00UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A33 *((volatile unsigned int*)(0x42CE0B04UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A34 *((volatile unsigned int*)(0x42CE0B08UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A35 *((volatile unsigned int*)(0x42CE0B0CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A36 *((volatile unsigned int*)(0x42CE0B10UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A37 *((volatile unsigned int*)(0x42CE0B14UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A38 *((volatile unsigned int*)(0x42CE0B18UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A39 *((volatile unsigned int*)(0x42CE0B1CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A40 *((volatile unsigned int*)(0x42CE0B20UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A41 *((volatile unsigned int*)(0x42CE0B24UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A42 *((volatile unsigned int*)(0x42CE0B28UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A43 *((volatile unsigned int*)(0x42CE0B2CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A44 *((volatile unsigned int*)(0x42CE0B30UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A45 *((volatile unsigned int*)(0x42CE0B34UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A46 *((volatile unsigned int*)(0x42CE0B38UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_A47 *((volatile unsigned int*)(0x42CE0B3CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC0 *((volatile unsigned int*)(0x42CE0B60UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC1 *((volatile unsigned int*)(0x42CE0B64UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC2 *((volatile unsigned int*)(0x42CE0B68UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC3 *((volatile unsigned int*)(0x42CE0B6CUL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC4 *((volatile unsigned int*)(0x42CE0B70UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_MBC5 *((volatile unsigned int*)(0x42CE0B74UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_SA *((volatile unsigned int*)(0x42CE0B78UL)) -#define bFM3_ETHERNET_MAC1_MAR3H_AE *((volatile unsigned int*)(0x42CE0B7CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A0 *((volatile unsigned int*)(0x42CE0B80UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A1 *((volatile unsigned int*)(0x42CE0B84UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A2 *((volatile unsigned int*)(0x42CE0B88UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A3 *((volatile unsigned int*)(0x42CE0B8CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A4 *((volatile unsigned int*)(0x42CE0B90UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A5 *((volatile unsigned int*)(0x42CE0B94UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A6 *((volatile unsigned int*)(0x42CE0B98UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A7 *((volatile unsigned int*)(0x42CE0B9CUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A8 *((volatile unsigned int*)(0x42CE0BA0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A9 *((volatile unsigned int*)(0x42CE0BA4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A10 *((volatile unsigned int*)(0x42CE0BA8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A11 *((volatile unsigned int*)(0x42CE0BACUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A12 *((volatile unsigned int*)(0x42CE0BB0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A13 *((volatile unsigned int*)(0x42CE0BB4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A14 *((volatile unsigned int*)(0x42CE0BB8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A15 *((volatile unsigned int*)(0x42CE0BBCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A16 *((volatile unsigned int*)(0x42CE0BC0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A17 *((volatile unsigned int*)(0x42CE0BC4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A18 *((volatile unsigned int*)(0x42CE0BC8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A19 *((volatile unsigned int*)(0x42CE0BCCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A20 *((volatile unsigned int*)(0x42CE0BD0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A21 *((volatile unsigned int*)(0x42CE0BD4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A22 *((volatile unsigned int*)(0x42CE0BD8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A23 *((volatile unsigned int*)(0x42CE0BDCUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A24 *((volatile unsigned int*)(0x42CE0BE0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A25 *((volatile unsigned int*)(0x42CE0BE4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A26 *((volatile unsigned int*)(0x42CE0BE8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A27 *((volatile unsigned int*)(0x42CE0BECUL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A28 *((volatile unsigned int*)(0x42CE0BF0UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A29 *((volatile unsigned int*)(0x42CE0BF4UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A30 *((volatile unsigned int*)(0x42CE0BF8UL)) -#define bFM3_ETHERNET_MAC1_MAR3L_A31 *((volatile unsigned int*)(0x42CE0BFCUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A32 *((volatile unsigned int*)(0x42CE0C00UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A33 *((volatile unsigned int*)(0x42CE0C04UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A34 *((volatile unsigned int*)(0x42CE0C08UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A35 *((volatile unsigned int*)(0x42CE0C0CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A36 *((volatile unsigned int*)(0x42CE0C10UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A37 *((volatile unsigned int*)(0x42CE0C14UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A38 *((volatile unsigned int*)(0x42CE0C18UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A39 *((volatile unsigned int*)(0x42CE0C1CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A40 *((volatile unsigned int*)(0x42CE0C20UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A41 *((volatile unsigned int*)(0x42CE0C24UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A42 *((volatile unsigned int*)(0x42CE0C28UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A43 *((volatile unsigned int*)(0x42CE0C2CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A44 *((volatile unsigned int*)(0x42CE0C30UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A45 *((volatile unsigned int*)(0x42CE0C34UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A46 *((volatile unsigned int*)(0x42CE0C38UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_A47 *((volatile unsigned int*)(0x42CE0C3CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC0 *((volatile unsigned int*)(0x42CE0C60UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC1 *((volatile unsigned int*)(0x42CE0C64UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC2 *((volatile unsigned int*)(0x42CE0C68UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC3 *((volatile unsigned int*)(0x42CE0C6CUL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC4 *((volatile unsigned int*)(0x42CE0C70UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_MBC5 *((volatile unsigned int*)(0x42CE0C74UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_SA *((volatile unsigned int*)(0x42CE0C78UL)) -#define bFM3_ETHERNET_MAC1_MAR4H_AE *((volatile unsigned int*)(0x42CE0C7CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A0 *((volatile unsigned int*)(0x42CE0C80UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A1 *((volatile unsigned int*)(0x42CE0C84UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A2 *((volatile unsigned int*)(0x42CE0C88UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A3 *((volatile unsigned int*)(0x42CE0C8CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A4 *((volatile unsigned int*)(0x42CE0C90UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A5 *((volatile unsigned int*)(0x42CE0C94UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A6 *((volatile unsigned int*)(0x42CE0C98UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A7 *((volatile unsigned int*)(0x42CE0C9CUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A8 *((volatile unsigned int*)(0x42CE0CA0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A9 *((volatile unsigned int*)(0x42CE0CA4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A10 *((volatile unsigned int*)(0x42CE0CA8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A11 *((volatile unsigned int*)(0x42CE0CACUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A12 *((volatile unsigned int*)(0x42CE0CB0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A13 *((volatile unsigned int*)(0x42CE0CB4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A14 *((volatile unsigned int*)(0x42CE0CB8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A15 *((volatile unsigned int*)(0x42CE0CBCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A16 *((volatile unsigned int*)(0x42CE0CC0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A17 *((volatile unsigned int*)(0x42CE0CC4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A18 *((volatile unsigned int*)(0x42CE0CC8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A19 *((volatile unsigned int*)(0x42CE0CCCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A20 *((volatile unsigned int*)(0x42CE0CD0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A21 *((volatile unsigned int*)(0x42CE0CD4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A22 *((volatile unsigned int*)(0x42CE0CD8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A23 *((volatile unsigned int*)(0x42CE0CDCUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A24 *((volatile unsigned int*)(0x42CE0CE0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A25 *((volatile unsigned int*)(0x42CE0CE4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A26 *((volatile unsigned int*)(0x42CE0CE8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A27 *((volatile unsigned int*)(0x42CE0CECUL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A28 *((volatile unsigned int*)(0x42CE0CF0UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A29 *((volatile unsigned int*)(0x42CE0CF4UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A30 *((volatile unsigned int*)(0x42CE0CF8UL)) -#define bFM3_ETHERNET_MAC1_MAR4L_A31 *((volatile unsigned int*)(0x42CE0CFCUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A32 *((volatile unsigned int*)(0x42CE0D00UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A33 *((volatile unsigned int*)(0x42CE0D04UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A34 *((volatile unsigned int*)(0x42CE0D08UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A35 *((volatile unsigned int*)(0x42CE0D0CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A36 *((volatile unsigned int*)(0x42CE0D10UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A37 *((volatile unsigned int*)(0x42CE0D14UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A38 *((volatile unsigned int*)(0x42CE0D18UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A39 *((volatile unsigned int*)(0x42CE0D1CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A40 *((volatile unsigned int*)(0x42CE0D20UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A41 *((volatile unsigned int*)(0x42CE0D24UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A42 *((volatile unsigned int*)(0x42CE0D28UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A43 *((volatile unsigned int*)(0x42CE0D2CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A44 *((volatile unsigned int*)(0x42CE0D30UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A45 *((volatile unsigned int*)(0x42CE0D34UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A46 *((volatile unsigned int*)(0x42CE0D38UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_A47 *((volatile unsigned int*)(0x42CE0D3CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC0 *((volatile unsigned int*)(0x42CE0D60UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC1 *((volatile unsigned int*)(0x42CE0D64UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC2 *((volatile unsigned int*)(0x42CE0D68UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC3 *((volatile unsigned int*)(0x42CE0D6CUL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC4 *((volatile unsigned int*)(0x42CE0D70UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_MBC5 *((volatile unsigned int*)(0x42CE0D74UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_SA *((volatile unsigned int*)(0x42CE0D78UL)) -#define bFM3_ETHERNET_MAC1_MAR5H_AE *((volatile unsigned int*)(0x42CE0D7CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A0 *((volatile unsigned int*)(0x42CE0D80UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A1 *((volatile unsigned int*)(0x42CE0D84UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A2 *((volatile unsigned int*)(0x42CE0D88UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A3 *((volatile unsigned int*)(0x42CE0D8CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A4 *((volatile unsigned int*)(0x42CE0D90UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A5 *((volatile unsigned int*)(0x42CE0D94UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A6 *((volatile unsigned int*)(0x42CE0D98UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A7 *((volatile unsigned int*)(0x42CE0D9CUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A8 *((volatile unsigned int*)(0x42CE0DA0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A9 *((volatile unsigned int*)(0x42CE0DA4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A10 *((volatile unsigned int*)(0x42CE0DA8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A11 *((volatile unsigned int*)(0x42CE0DACUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A12 *((volatile unsigned int*)(0x42CE0DB0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A13 *((volatile unsigned int*)(0x42CE0DB4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A14 *((volatile unsigned int*)(0x42CE0DB8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A15 *((volatile unsigned int*)(0x42CE0DBCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A16 *((volatile unsigned int*)(0x42CE0DC0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A17 *((volatile unsigned int*)(0x42CE0DC4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A18 *((volatile unsigned int*)(0x42CE0DC8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A19 *((volatile unsigned int*)(0x42CE0DCCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A20 *((volatile unsigned int*)(0x42CE0DD0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A21 *((volatile unsigned int*)(0x42CE0DD4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A22 *((volatile unsigned int*)(0x42CE0DD8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A23 *((volatile unsigned int*)(0x42CE0DDCUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A24 *((volatile unsigned int*)(0x42CE0DE0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A25 *((volatile unsigned int*)(0x42CE0DE4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A26 *((volatile unsigned int*)(0x42CE0DE8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A27 *((volatile unsigned int*)(0x42CE0DECUL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A28 *((volatile unsigned int*)(0x42CE0DF0UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A29 *((volatile unsigned int*)(0x42CE0DF4UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A30 *((volatile unsigned int*)(0x42CE0DF8UL)) -#define bFM3_ETHERNET_MAC1_MAR5L_A31 *((volatile unsigned int*)(0x42CE0DFCUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A32 *((volatile unsigned int*)(0x42CE0E00UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A33 *((volatile unsigned int*)(0x42CE0E04UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A34 *((volatile unsigned int*)(0x42CE0E08UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A35 *((volatile unsigned int*)(0x42CE0E0CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A36 *((volatile unsigned int*)(0x42CE0E10UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A37 *((volatile unsigned int*)(0x42CE0E14UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A38 *((volatile unsigned int*)(0x42CE0E18UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A39 *((volatile unsigned int*)(0x42CE0E1CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A40 *((volatile unsigned int*)(0x42CE0E20UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A41 *((volatile unsigned int*)(0x42CE0E24UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A42 *((volatile unsigned int*)(0x42CE0E28UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A43 *((volatile unsigned int*)(0x42CE0E2CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A44 *((volatile unsigned int*)(0x42CE0E30UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A45 *((volatile unsigned int*)(0x42CE0E34UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A46 *((volatile unsigned int*)(0x42CE0E38UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_A47 *((volatile unsigned int*)(0x42CE0E3CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC0 *((volatile unsigned int*)(0x42CE0E60UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC1 *((volatile unsigned int*)(0x42CE0E64UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC2 *((volatile unsigned int*)(0x42CE0E68UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC3 *((volatile unsigned int*)(0x42CE0E6CUL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC4 *((volatile unsigned int*)(0x42CE0E70UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_MBC5 *((volatile unsigned int*)(0x42CE0E74UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_SA *((volatile unsigned int*)(0x42CE0E78UL)) -#define bFM3_ETHERNET_MAC1_MAR6H_AE *((volatile unsigned int*)(0x42CE0E7CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A0 *((volatile unsigned int*)(0x42CE0E80UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A1 *((volatile unsigned int*)(0x42CE0E84UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A2 *((volatile unsigned int*)(0x42CE0E88UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A3 *((volatile unsigned int*)(0x42CE0E8CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A4 *((volatile unsigned int*)(0x42CE0E90UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A5 *((volatile unsigned int*)(0x42CE0E94UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A6 *((volatile unsigned int*)(0x42CE0E98UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A7 *((volatile unsigned int*)(0x42CE0E9CUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A8 *((volatile unsigned int*)(0x42CE0EA0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A9 *((volatile unsigned int*)(0x42CE0EA4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A10 *((volatile unsigned int*)(0x42CE0EA8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A11 *((volatile unsigned int*)(0x42CE0EACUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A12 *((volatile unsigned int*)(0x42CE0EB0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A13 *((volatile unsigned int*)(0x42CE0EB4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A14 *((volatile unsigned int*)(0x42CE0EB8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A15 *((volatile unsigned int*)(0x42CE0EBCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A16 *((volatile unsigned int*)(0x42CE0EC0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A17 *((volatile unsigned int*)(0x42CE0EC4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A18 *((volatile unsigned int*)(0x42CE0EC8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A19 *((volatile unsigned int*)(0x42CE0ECCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A20 *((volatile unsigned int*)(0x42CE0ED0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A21 *((volatile unsigned int*)(0x42CE0ED4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A22 *((volatile unsigned int*)(0x42CE0ED8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A23 *((volatile unsigned int*)(0x42CE0EDCUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A24 *((volatile unsigned int*)(0x42CE0EE0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A25 *((volatile unsigned int*)(0x42CE0EE4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A26 *((volatile unsigned int*)(0x42CE0EE8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A27 *((volatile unsigned int*)(0x42CE0EECUL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A28 *((volatile unsigned int*)(0x42CE0EF0UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A29 *((volatile unsigned int*)(0x42CE0EF4UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A30 *((volatile unsigned int*)(0x42CE0EF8UL)) -#define bFM3_ETHERNET_MAC1_MAR6L_A31 *((volatile unsigned int*)(0x42CE0EFCUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A32 *((volatile unsigned int*)(0x42CE0F00UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A33 *((volatile unsigned int*)(0x42CE0F04UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A34 *((volatile unsigned int*)(0x42CE0F08UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A35 *((volatile unsigned int*)(0x42CE0F0CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A36 *((volatile unsigned int*)(0x42CE0F10UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A37 *((volatile unsigned int*)(0x42CE0F14UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A38 *((volatile unsigned int*)(0x42CE0F18UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A39 *((volatile unsigned int*)(0x42CE0F1CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A40 *((volatile unsigned int*)(0x42CE0F20UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A41 *((volatile unsigned int*)(0x42CE0F24UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A42 *((volatile unsigned int*)(0x42CE0F28UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A43 *((volatile unsigned int*)(0x42CE0F2CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A44 *((volatile unsigned int*)(0x42CE0F30UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A45 *((volatile unsigned int*)(0x42CE0F34UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A46 *((volatile unsigned int*)(0x42CE0F38UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_A47 *((volatile unsigned int*)(0x42CE0F3CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC0 *((volatile unsigned int*)(0x42CE0F60UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC1 *((volatile unsigned int*)(0x42CE0F64UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC2 *((volatile unsigned int*)(0x42CE0F68UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC3 *((volatile unsigned int*)(0x42CE0F6CUL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC4 *((volatile unsigned int*)(0x42CE0F70UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_MBC5 *((volatile unsigned int*)(0x42CE0F74UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_SA *((volatile unsigned int*)(0x42CE0F78UL)) -#define bFM3_ETHERNET_MAC1_MAR7H_AE *((volatile unsigned int*)(0x42CE0F7CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A0 *((volatile unsigned int*)(0x42CE0F80UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A1 *((volatile unsigned int*)(0x42CE0F84UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A2 *((volatile unsigned int*)(0x42CE0F88UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A3 *((volatile unsigned int*)(0x42CE0F8CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A4 *((volatile unsigned int*)(0x42CE0F90UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A5 *((volatile unsigned int*)(0x42CE0F94UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A6 *((volatile unsigned int*)(0x42CE0F98UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A7 *((volatile unsigned int*)(0x42CE0F9CUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A8 *((volatile unsigned int*)(0x42CE0FA0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A9 *((volatile unsigned int*)(0x42CE0FA4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A10 *((volatile unsigned int*)(0x42CE0FA8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A11 *((volatile unsigned int*)(0x42CE0FACUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A12 *((volatile unsigned int*)(0x42CE0FB0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A13 *((volatile unsigned int*)(0x42CE0FB4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A14 *((volatile unsigned int*)(0x42CE0FB8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A15 *((volatile unsigned int*)(0x42CE0FBCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A16 *((volatile unsigned int*)(0x42CE0FC0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A17 *((volatile unsigned int*)(0x42CE0FC4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A18 *((volatile unsigned int*)(0x42CE0FC8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A19 *((volatile unsigned int*)(0x42CE0FCCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A20 *((volatile unsigned int*)(0x42CE0FD0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A21 *((volatile unsigned int*)(0x42CE0FD4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A22 *((volatile unsigned int*)(0x42CE0FD8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A23 *((volatile unsigned int*)(0x42CE0FDCUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A24 *((volatile unsigned int*)(0x42CE0FE0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A25 *((volatile unsigned int*)(0x42CE0FE4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A26 *((volatile unsigned int*)(0x42CE0FE8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A27 *((volatile unsigned int*)(0x42CE0FECUL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A28 *((volatile unsigned int*)(0x42CE0FF0UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A29 *((volatile unsigned int*)(0x42CE0FF4UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A30 *((volatile unsigned int*)(0x42CE0FF8UL)) -#define bFM3_ETHERNET_MAC1_MAR7L_A31 *((volatile unsigned int*)(0x42CE0FFCUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A32 *((volatile unsigned int*)(0x42CE1000UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A33 *((volatile unsigned int*)(0x42CE1004UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A34 *((volatile unsigned int*)(0x42CE1008UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A35 *((volatile unsigned int*)(0x42CE100CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A36 *((volatile unsigned int*)(0x42CE1010UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A37 *((volatile unsigned int*)(0x42CE1014UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A38 *((volatile unsigned int*)(0x42CE1018UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A39 *((volatile unsigned int*)(0x42CE101CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A40 *((volatile unsigned int*)(0x42CE1020UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A41 *((volatile unsigned int*)(0x42CE1024UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A42 *((volatile unsigned int*)(0x42CE1028UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A43 *((volatile unsigned int*)(0x42CE102CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A44 *((volatile unsigned int*)(0x42CE1030UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A45 *((volatile unsigned int*)(0x42CE1034UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A46 *((volatile unsigned int*)(0x42CE1038UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_A47 *((volatile unsigned int*)(0x42CE103CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC0 *((volatile unsigned int*)(0x42CE1060UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC1 *((volatile unsigned int*)(0x42CE1064UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC2 *((volatile unsigned int*)(0x42CE1068UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC3 *((volatile unsigned int*)(0x42CE106CUL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC4 *((volatile unsigned int*)(0x42CE1070UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_MBC5 *((volatile unsigned int*)(0x42CE1074UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_SA *((volatile unsigned int*)(0x42CE1078UL)) -#define bFM3_ETHERNET_MAC1_MAR8H_AE *((volatile unsigned int*)(0x42CE107CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A0 *((volatile unsigned int*)(0x42CE1080UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A1 *((volatile unsigned int*)(0x42CE1084UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A2 *((volatile unsigned int*)(0x42CE1088UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A3 *((volatile unsigned int*)(0x42CE108CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A4 *((volatile unsigned int*)(0x42CE1090UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A5 *((volatile unsigned int*)(0x42CE1094UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A6 *((volatile unsigned int*)(0x42CE1098UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A7 *((volatile unsigned int*)(0x42CE109CUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A8 *((volatile unsigned int*)(0x42CE10A0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A9 *((volatile unsigned int*)(0x42CE10A4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A10 *((volatile unsigned int*)(0x42CE10A8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A11 *((volatile unsigned int*)(0x42CE10ACUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A12 *((volatile unsigned int*)(0x42CE10B0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A13 *((volatile unsigned int*)(0x42CE10B4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A14 *((volatile unsigned int*)(0x42CE10B8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A15 *((volatile unsigned int*)(0x42CE10BCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A16 *((volatile unsigned int*)(0x42CE10C0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A17 *((volatile unsigned int*)(0x42CE10C4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A18 *((volatile unsigned int*)(0x42CE10C8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A19 *((volatile unsigned int*)(0x42CE10CCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A20 *((volatile unsigned int*)(0x42CE10D0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A21 *((volatile unsigned int*)(0x42CE10D4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A22 *((volatile unsigned int*)(0x42CE10D8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A23 *((volatile unsigned int*)(0x42CE10DCUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A24 *((volatile unsigned int*)(0x42CE10E0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A25 *((volatile unsigned int*)(0x42CE10E4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A26 *((volatile unsigned int*)(0x42CE10E8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A27 *((volatile unsigned int*)(0x42CE10ECUL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A28 *((volatile unsigned int*)(0x42CE10F0UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A29 *((volatile unsigned int*)(0x42CE10F4UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A30 *((volatile unsigned int*)(0x42CE10F8UL)) -#define bFM3_ETHERNET_MAC1_MAR8L_A31 *((volatile unsigned int*)(0x42CE10FCUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A32 *((volatile unsigned int*)(0x42CE1100UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A33 *((volatile unsigned int*)(0x42CE1104UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A34 *((volatile unsigned int*)(0x42CE1108UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A35 *((volatile unsigned int*)(0x42CE110CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A36 *((volatile unsigned int*)(0x42CE1110UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A37 *((volatile unsigned int*)(0x42CE1114UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A38 *((volatile unsigned int*)(0x42CE1118UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A39 *((volatile unsigned int*)(0x42CE111CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A40 *((volatile unsigned int*)(0x42CE1120UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A41 *((volatile unsigned int*)(0x42CE1124UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A42 *((volatile unsigned int*)(0x42CE1128UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A43 *((volatile unsigned int*)(0x42CE112CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A44 *((volatile unsigned int*)(0x42CE1130UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A45 *((volatile unsigned int*)(0x42CE1134UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A46 *((volatile unsigned int*)(0x42CE1138UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_A47 *((volatile unsigned int*)(0x42CE113CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC0 *((volatile unsigned int*)(0x42CE1160UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC1 *((volatile unsigned int*)(0x42CE1164UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC2 *((volatile unsigned int*)(0x42CE1168UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC3 *((volatile unsigned int*)(0x42CE116CUL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC4 *((volatile unsigned int*)(0x42CE1170UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_MBC5 *((volatile unsigned int*)(0x42CE1174UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_SA *((volatile unsigned int*)(0x42CE1178UL)) -#define bFM3_ETHERNET_MAC1_MAR9H_AE *((volatile unsigned int*)(0x42CE117CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A0 *((volatile unsigned int*)(0x42CE1180UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A1 *((volatile unsigned int*)(0x42CE1184UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A2 *((volatile unsigned int*)(0x42CE1188UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A3 *((volatile unsigned int*)(0x42CE118CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A4 *((volatile unsigned int*)(0x42CE1190UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A5 *((volatile unsigned int*)(0x42CE1194UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A6 *((volatile unsigned int*)(0x42CE1198UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A7 *((volatile unsigned int*)(0x42CE119CUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A8 *((volatile unsigned int*)(0x42CE11A0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A9 *((volatile unsigned int*)(0x42CE11A4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A10 *((volatile unsigned int*)(0x42CE11A8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A11 *((volatile unsigned int*)(0x42CE11ACUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A12 *((volatile unsigned int*)(0x42CE11B0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A13 *((volatile unsigned int*)(0x42CE11B4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A14 *((volatile unsigned int*)(0x42CE11B8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A15 *((volatile unsigned int*)(0x42CE11BCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A16 *((volatile unsigned int*)(0x42CE11C0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A17 *((volatile unsigned int*)(0x42CE11C4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A18 *((volatile unsigned int*)(0x42CE11C8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A19 *((volatile unsigned int*)(0x42CE11CCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A20 *((volatile unsigned int*)(0x42CE11D0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A21 *((volatile unsigned int*)(0x42CE11D4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A22 *((volatile unsigned int*)(0x42CE11D8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A23 *((volatile unsigned int*)(0x42CE11DCUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A24 *((volatile unsigned int*)(0x42CE11E0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A25 *((volatile unsigned int*)(0x42CE11E4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A26 *((volatile unsigned int*)(0x42CE11E8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A27 *((volatile unsigned int*)(0x42CE11ECUL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A28 *((volatile unsigned int*)(0x42CE11F0UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A29 *((volatile unsigned int*)(0x42CE11F4UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A30 *((volatile unsigned int*)(0x42CE11F8UL)) -#define bFM3_ETHERNET_MAC1_MAR9L_A31 *((volatile unsigned int*)(0x42CE11FCUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A32 *((volatile unsigned int*)(0x42CE1200UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A33 *((volatile unsigned int*)(0x42CE1204UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A34 *((volatile unsigned int*)(0x42CE1208UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A35 *((volatile unsigned int*)(0x42CE120CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A36 *((volatile unsigned int*)(0x42CE1210UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A37 *((volatile unsigned int*)(0x42CE1214UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A38 *((volatile unsigned int*)(0x42CE1218UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A39 *((volatile unsigned int*)(0x42CE121CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A40 *((volatile unsigned int*)(0x42CE1220UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A41 *((volatile unsigned int*)(0x42CE1224UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A42 *((volatile unsigned int*)(0x42CE1228UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A43 *((volatile unsigned int*)(0x42CE122CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A44 *((volatile unsigned int*)(0x42CE1230UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A45 *((volatile unsigned int*)(0x42CE1234UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A46 *((volatile unsigned int*)(0x42CE1238UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_A47 *((volatile unsigned int*)(0x42CE123CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC0 *((volatile unsigned int*)(0x42CE1260UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC1 *((volatile unsigned int*)(0x42CE1264UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC2 *((volatile unsigned int*)(0x42CE1268UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC3 *((volatile unsigned int*)(0x42CE126CUL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC4 *((volatile unsigned int*)(0x42CE1270UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_MBC5 *((volatile unsigned int*)(0x42CE1274UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_SA *((volatile unsigned int*)(0x42CE1278UL)) -#define bFM3_ETHERNET_MAC1_MAR10H_AE *((volatile unsigned int*)(0x42CE127CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A0 *((volatile unsigned int*)(0x42CE1280UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A1 *((volatile unsigned int*)(0x42CE1284UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A2 *((volatile unsigned int*)(0x42CE1288UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A3 *((volatile unsigned int*)(0x42CE128CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A4 *((volatile unsigned int*)(0x42CE1290UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A5 *((volatile unsigned int*)(0x42CE1294UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A6 *((volatile unsigned int*)(0x42CE1298UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A7 *((volatile unsigned int*)(0x42CE129CUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A8 *((volatile unsigned int*)(0x42CE12A0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A9 *((volatile unsigned int*)(0x42CE12A4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A10 *((volatile unsigned int*)(0x42CE12A8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A11 *((volatile unsigned int*)(0x42CE12ACUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A12 *((volatile unsigned int*)(0x42CE12B0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A13 *((volatile unsigned int*)(0x42CE12B4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A14 *((volatile unsigned int*)(0x42CE12B8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A15 *((volatile unsigned int*)(0x42CE12BCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A16 *((volatile unsigned int*)(0x42CE12C0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A17 *((volatile unsigned int*)(0x42CE12C4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A18 *((volatile unsigned int*)(0x42CE12C8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A19 *((volatile unsigned int*)(0x42CE12CCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A20 *((volatile unsigned int*)(0x42CE12D0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A21 *((volatile unsigned int*)(0x42CE12D4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A22 *((volatile unsigned int*)(0x42CE12D8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A23 *((volatile unsigned int*)(0x42CE12DCUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A24 *((volatile unsigned int*)(0x42CE12E0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A25 *((volatile unsigned int*)(0x42CE12E4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A26 *((volatile unsigned int*)(0x42CE12E8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A27 *((volatile unsigned int*)(0x42CE12ECUL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A28 *((volatile unsigned int*)(0x42CE12F0UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A29 *((volatile unsigned int*)(0x42CE12F4UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A30 *((volatile unsigned int*)(0x42CE12F8UL)) -#define bFM3_ETHERNET_MAC1_MAR10L_A31 *((volatile unsigned int*)(0x42CE12FCUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A32 *((volatile unsigned int*)(0x42CE1300UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A33 *((volatile unsigned int*)(0x42CE1304UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A34 *((volatile unsigned int*)(0x42CE1308UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A35 *((volatile unsigned int*)(0x42CE130CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A36 *((volatile unsigned int*)(0x42CE1310UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A37 *((volatile unsigned int*)(0x42CE1314UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A38 *((volatile unsigned int*)(0x42CE1318UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A39 *((volatile unsigned int*)(0x42CE131CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A40 *((volatile unsigned int*)(0x42CE1320UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A41 *((volatile unsigned int*)(0x42CE1324UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A42 *((volatile unsigned int*)(0x42CE1328UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A43 *((volatile unsigned int*)(0x42CE132CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A44 *((volatile unsigned int*)(0x42CE1330UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A45 *((volatile unsigned int*)(0x42CE1334UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A46 *((volatile unsigned int*)(0x42CE1338UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_A47 *((volatile unsigned int*)(0x42CE133CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC0 *((volatile unsigned int*)(0x42CE1360UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC1 *((volatile unsigned int*)(0x42CE1364UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC2 *((volatile unsigned int*)(0x42CE1368UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC3 *((volatile unsigned int*)(0x42CE136CUL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC4 *((volatile unsigned int*)(0x42CE1370UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_MBC5 *((volatile unsigned int*)(0x42CE1374UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_SA *((volatile unsigned int*)(0x42CE1378UL)) -#define bFM3_ETHERNET_MAC1_MAR11H_AE *((volatile unsigned int*)(0x42CE137CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A0 *((volatile unsigned int*)(0x42CE1380UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A1 *((volatile unsigned int*)(0x42CE1384UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A2 *((volatile unsigned int*)(0x42CE1388UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A3 *((volatile unsigned int*)(0x42CE138CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A4 *((volatile unsigned int*)(0x42CE1390UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A5 *((volatile unsigned int*)(0x42CE1394UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A6 *((volatile unsigned int*)(0x42CE1398UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A7 *((volatile unsigned int*)(0x42CE139CUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A8 *((volatile unsigned int*)(0x42CE13A0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A9 *((volatile unsigned int*)(0x42CE13A4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A10 *((volatile unsigned int*)(0x42CE13A8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A11 *((volatile unsigned int*)(0x42CE13ACUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A12 *((volatile unsigned int*)(0x42CE13B0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A13 *((volatile unsigned int*)(0x42CE13B4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A14 *((volatile unsigned int*)(0x42CE13B8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A15 *((volatile unsigned int*)(0x42CE13BCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A16 *((volatile unsigned int*)(0x42CE13C0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A17 *((volatile unsigned int*)(0x42CE13C4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A18 *((volatile unsigned int*)(0x42CE13C8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A19 *((volatile unsigned int*)(0x42CE13CCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A20 *((volatile unsigned int*)(0x42CE13D0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A21 *((volatile unsigned int*)(0x42CE13D4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A22 *((volatile unsigned int*)(0x42CE13D8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A23 *((volatile unsigned int*)(0x42CE13DCUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A24 *((volatile unsigned int*)(0x42CE13E0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A25 *((volatile unsigned int*)(0x42CE13E4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A26 *((volatile unsigned int*)(0x42CE13E8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A27 *((volatile unsigned int*)(0x42CE13ECUL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A28 *((volatile unsigned int*)(0x42CE13F0UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A29 *((volatile unsigned int*)(0x42CE13F4UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A30 *((volatile unsigned int*)(0x42CE13F8UL)) -#define bFM3_ETHERNET_MAC1_MAR11L_A31 *((volatile unsigned int*)(0x42CE13FCUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A32 *((volatile unsigned int*)(0x42CE1400UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A33 *((volatile unsigned int*)(0x42CE1404UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A34 *((volatile unsigned int*)(0x42CE1408UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A35 *((volatile unsigned int*)(0x42CE140CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A36 *((volatile unsigned int*)(0x42CE1410UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A37 *((volatile unsigned int*)(0x42CE1414UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A38 *((volatile unsigned int*)(0x42CE1418UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A39 *((volatile unsigned int*)(0x42CE141CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A40 *((volatile unsigned int*)(0x42CE1420UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A41 *((volatile unsigned int*)(0x42CE1424UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A42 *((volatile unsigned int*)(0x42CE1428UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A43 *((volatile unsigned int*)(0x42CE142CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A44 *((volatile unsigned int*)(0x42CE1430UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A45 *((volatile unsigned int*)(0x42CE1434UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A46 *((volatile unsigned int*)(0x42CE1438UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_A47 *((volatile unsigned int*)(0x42CE143CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC0 *((volatile unsigned int*)(0x42CE1460UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC1 *((volatile unsigned int*)(0x42CE1464UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC2 *((volatile unsigned int*)(0x42CE1468UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC3 *((volatile unsigned int*)(0x42CE146CUL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC4 *((volatile unsigned int*)(0x42CE1470UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_MBC5 *((volatile unsigned int*)(0x42CE1474UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_SA *((volatile unsigned int*)(0x42CE1478UL)) -#define bFM3_ETHERNET_MAC1_MAR12H_AE *((volatile unsigned int*)(0x42CE147CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A0 *((volatile unsigned int*)(0x42CE1480UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A1 *((volatile unsigned int*)(0x42CE1484UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A2 *((volatile unsigned int*)(0x42CE1488UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A3 *((volatile unsigned int*)(0x42CE148CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A4 *((volatile unsigned int*)(0x42CE1490UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A5 *((volatile unsigned int*)(0x42CE1494UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A6 *((volatile unsigned int*)(0x42CE1498UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A7 *((volatile unsigned int*)(0x42CE149CUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A8 *((volatile unsigned int*)(0x42CE14A0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A9 *((volatile unsigned int*)(0x42CE14A4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A10 *((volatile unsigned int*)(0x42CE14A8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A11 *((volatile unsigned int*)(0x42CE14ACUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A12 *((volatile unsigned int*)(0x42CE14B0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A13 *((volatile unsigned int*)(0x42CE14B4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A14 *((volatile unsigned int*)(0x42CE14B8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A15 *((volatile unsigned int*)(0x42CE14BCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A16 *((volatile unsigned int*)(0x42CE14C0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A17 *((volatile unsigned int*)(0x42CE14C4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A18 *((volatile unsigned int*)(0x42CE14C8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A19 *((volatile unsigned int*)(0x42CE14CCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A20 *((volatile unsigned int*)(0x42CE14D0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A21 *((volatile unsigned int*)(0x42CE14D4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A22 *((volatile unsigned int*)(0x42CE14D8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A23 *((volatile unsigned int*)(0x42CE14DCUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A24 *((volatile unsigned int*)(0x42CE14E0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A25 *((volatile unsigned int*)(0x42CE14E4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A26 *((volatile unsigned int*)(0x42CE14E8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A27 *((volatile unsigned int*)(0x42CE14ECUL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A28 *((volatile unsigned int*)(0x42CE14F0UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A29 *((volatile unsigned int*)(0x42CE14F4UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A30 *((volatile unsigned int*)(0x42CE14F8UL)) -#define bFM3_ETHERNET_MAC1_MAR12L_A31 *((volatile unsigned int*)(0x42CE14FCUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A32 *((volatile unsigned int*)(0x42CE1500UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A33 *((volatile unsigned int*)(0x42CE1504UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A34 *((volatile unsigned int*)(0x42CE1508UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A35 *((volatile unsigned int*)(0x42CE150CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A36 *((volatile unsigned int*)(0x42CE1510UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A37 *((volatile unsigned int*)(0x42CE1514UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A38 *((volatile unsigned int*)(0x42CE1518UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A39 *((volatile unsigned int*)(0x42CE151CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A40 *((volatile unsigned int*)(0x42CE1520UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A41 *((volatile unsigned int*)(0x42CE1524UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A42 *((volatile unsigned int*)(0x42CE1528UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A43 *((volatile unsigned int*)(0x42CE152CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A44 *((volatile unsigned int*)(0x42CE1530UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A45 *((volatile unsigned int*)(0x42CE1534UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A46 *((volatile unsigned int*)(0x42CE1538UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_A47 *((volatile unsigned int*)(0x42CE153CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC0 *((volatile unsigned int*)(0x42CE1560UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC1 *((volatile unsigned int*)(0x42CE1564UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC2 *((volatile unsigned int*)(0x42CE1568UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC3 *((volatile unsigned int*)(0x42CE156CUL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC4 *((volatile unsigned int*)(0x42CE1570UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_MBC5 *((volatile unsigned int*)(0x42CE1574UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_SA *((volatile unsigned int*)(0x42CE1578UL)) -#define bFM3_ETHERNET_MAC1_MAR13H_AE *((volatile unsigned int*)(0x42CE157CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A0 *((volatile unsigned int*)(0x42CE1580UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A1 *((volatile unsigned int*)(0x42CE1584UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A2 *((volatile unsigned int*)(0x42CE1588UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A3 *((volatile unsigned int*)(0x42CE158CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A4 *((volatile unsigned int*)(0x42CE1590UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A5 *((volatile unsigned int*)(0x42CE1594UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A6 *((volatile unsigned int*)(0x42CE1598UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A7 *((volatile unsigned int*)(0x42CE159CUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A8 *((volatile unsigned int*)(0x42CE15A0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A9 *((volatile unsigned int*)(0x42CE15A4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A10 *((volatile unsigned int*)(0x42CE15A8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A11 *((volatile unsigned int*)(0x42CE15ACUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A12 *((volatile unsigned int*)(0x42CE15B0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A13 *((volatile unsigned int*)(0x42CE15B4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A14 *((volatile unsigned int*)(0x42CE15B8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A15 *((volatile unsigned int*)(0x42CE15BCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A16 *((volatile unsigned int*)(0x42CE15C0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A17 *((volatile unsigned int*)(0x42CE15C4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A18 *((volatile unsigned int*)(0x42CE15C8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A19 *((volatile unsigned int*)(0x42CE15CCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A20 *((volatile unsigned int*)(0x42CE15D0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A21 *((volatile unsigned int*)(0x42CE15D4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A22 *((volatile unsigned int*)(0x42CE15D8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A23 *((volatile unsigned int*)(0x42CE15DCUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A24 *((volatile unsigned int*)(0x42CE15E0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A25 *((volatile unsigned int*)(0x42CE15E4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A26 *((volatile unsigned int*)(0x42CE15E8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A27 *((volatile unsigned int*)(0x42CE15ECUL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A28 *((volatile unsigned int*)(0x42CE15F0UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A29 *((volatile unsigned int*)(0x42CE15F4UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A30 *((volatile unsigned int*)(0x42CE15F8UL)) -#define bFM3_ETHERNET_MAC1_MAR13L_A31 *((volatile unsigned int*)(0x42CE15FCUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A32 *((volatile unsigned int*)(0x42CE1600UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A33 *((volatile unsigned int*)(0x42CE1604UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A34 *((volatile unsigned int*)(0x42CE1608UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A35 *((volatile unsigned int*)(0x42CE160CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A36 *((volatile unsigned int*)(0x42CE1610UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A37 *((volatile unsigned int*)(0x42CE1614UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A38 *((volatile unsigned int*)(0x42CE1618UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A39 *((volatile unsigned int*)(0x42CE161CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A40 *((volatile unsigned int*)(0x42CE1620UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A41 *((volatile unsigned int*)(0x42CE1624UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A42 *((volatile unsigned int*)(0x42CE1628UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A43 *((volatile unsigned int*)(0x42CE162CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A44 *((volatile unsigned int*)(0x42CE1630UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A45 *((volatile unsigned int*)(0x42CE1634UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A46 *((volatile unsigned int*)(0x42CE1638UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_A47 *((volatile unsigned int*)(0x42CE163CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC0 *((volatile unsigned int*)(0x42CE1660UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC1 *((volatile unsigned int*)(0x42CE1664UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC2 *((volatile unsigned int*)(0x42CE1668UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC3 *((volatile unsigned int*)(0x42CE166CUL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC4 *((volatile unsigned int*)(0x42CE1670UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_MBC5 *((volatile unsigned int*)(0x42CE1674UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_SA *((volatile unsigned int*)(0x42CE1678UL)) -#define bFM3_ETHERNET_MAC1_MAR14H_AE *((volatile unsigned int*)(0x42CE167CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A0 *((volatile unsigned int*)(0x42CE1680UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A1 *((volatile unsigned int*)(0x42CE1684UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A2 *((volatile unsigned int*)(0x42CE1688UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A3 *((volatile unsigned int*)(0x42CE168CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A4 *((volatile unsigned int*)(0x42CE1690UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A5 *((volatile unsigned int*)(0x42CE1694UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A6 *((volatile unsigned int*)(0x42CE1698UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A7 *((volatile unsigned int*)(0x42CE169CUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A8 *((volatile unsigned int*)(0x42CE16A0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A9 *((volatile unsigned int*)(0x42CE16A4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A10 *((volatile unsigned int*)(0x42CE16A8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A11 *((volatile unsigned int*)(0x42CE16ACUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A12 *((volatile unsigned int*)(0x42CE16B0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A13 *((volatile unsigned int*)(0x42CE16B4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A14 *((volatile unsigned int*)(0x42CE16B8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A15 *((volatile unsigned int*)(0x42CE16BCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A16 *((volatile unsigned int*)(0x42CE16C0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A17 *((volatile unsigned int*)(0x42CE16C4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A18 *((volatile unsigned int*)(0x42CE16C8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A19 *((volatile unsigned int*)(0x42CE16CCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A20 *((volatile unsigned int*)(0x42CE16D0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A21 *((volatile unsigned int*)(0x42CE16D4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A22 *((volatile unsigned int*)(0x42CE16D8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A23 *((volatile unsigned int*)(0x42CE16DCUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A24 *((volatile unsigned int*)(0x42CE16E0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A25 *((volatile unsigned int*)(0x42CE16E4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A26 *((volatile unsigned int*)(0x42CE16E8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A27 *((volatile unsigned int*)(0x42CE16ECUL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A28 *((volatile unsigned int*)(0x42CE16F0UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A29 *((volatile unsigned int*)(0x42CE16F4UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A30 *((volatile unsigned int*)(0x42CE16F8UL)) -#define bFM3_ETHERNET_MAC1_MAR14L_A31 *((volatile unsigned int*)(0x42CE16FCUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A32 *((volatile unsigned int*)(0x42CE1700UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A33 *((volatile unsigned int*)(0x42CE1704UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A34 *((volatile unsigned int*)(0x42CE1708UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A35 *((volatile unsigned int*)(0x42CE170CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A36 *((volatile unsigned int*)(0x42CE1710UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A37 *((volatile unsigned int*)(0x42CE1714UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A38 *((volatile unsigned int*)(0x42CE1718UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A39 *((volatile unsigned int*)(0x42CE171CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A40 *((volatile unsigned int*)(0x42CE1720UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A41 *((volatile unsigned int*)(0x42CE1724UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A42 *((volatile unsigned int*)(0x42CE1728UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A43 *((volatile unsigned int*)(0x42CE172CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A44 *((volatile unsigned int*)(0x42CE1730UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A45 *((volatile unsigned int*)(0x42CE1734UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A46 *((volatile unsigned int*)(0x42CE1738UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_A47 *((volatile unsigned int*)(0x42CE173CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC0 *((volatile unsigned int*)(0x42CE1760UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC1 *((volatile unsigned int*)(0x42CE1764UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC2 *((volatile unsigned int*)(0x42CE1768UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC3 *((volatile unsigned int*)(0x42CE176CUL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC4 *((volatile unsigned int*)(0x42CE1770UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_MBC5 *((volatile unsigned int*)(0x42CE1774UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_SA *((volatile unsigned int*)(0x42CE1778UL)) -#define bFM3_ETHERNET_MAC1_MAR15H_AE *((volatile unsigned int*)(0x42CE177CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A0 *((volatile unsigned int*)(0x42CE1780UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A1 *((volatile unsigned int*)(0x42CE1784UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A2 *((volatile unsigned int*)(0x42CE1788UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A3 *((volatile unsigned int*)(0x42CE178CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A4 *((volatile unsigned int*)(0x42CE1790UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A5 *((volatile unsigned int*)(0x42CE1794UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A6 *((volatile unsigned int*)(0x42CE1798UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A7 *((volatile unsigned int*)(0x42CE179CUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A8 *((volatile unsigned int*)(0x42CE17A0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A9 *((volatile unsigned int*)(0x42CE17A4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A10 *((volatile unsigned int*)(0x42CE17A8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A11 *((volatile unsigned int*)(0x42CE17ACUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A12 *((volatile unsigned int*)(0x42CE17B0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A13 *((volatile unsigned int*)(0x42CE17B4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A14 *((volatile unsigned int*)(0x42CE17B8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A15 *((volatile unsigned int*)(0x42CE17BCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A16 *((volatile unsigned int*)(0x42CE17C0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A17 *((volatile unsigned int*)(0x42CE17C4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A18 *((volatile unsigned int*)(0x42CE17C8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A19 *((volatile unsigned int*)(0x42CE17CCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A20 *((volatile unsigned int*)(0x42CE17D0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A21 *((volatile unsigned int*)(0x42CE17D4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A22 *((volatile unsigned int*)(0x42CE17D8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A23 *((volatile unsigned int*)(0x42CE17DCUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A24 *((volatile unsigned int*)(0x42CE17E0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A25 *((volatile unsigned int*)(0x42CE17E4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A26 *((volatile unsigned int*)(0x42CE17E8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A27 *((volatile unsigned int*)(0x42CE17ECUL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A28 *((volatile unsigned int*)(0x42CE17F0UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A29 *((volatile unsigned int*)(0x42CE17F4UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A30 *((volatile unsigned int*)(0x42CE17F8UL)) -#define bFM3_ETHERNET_MAC1_MAR15L_A31 *((volatile unsigned int*)(0x42CE17FCUL)) -#define bFM3_ETHERNET_MAC1_RGSR_LM *((volatile unsigned int*)(0x42CE1B00UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LSP0 *((volatile unsigned int*)(0x42CE1B04UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LSP1 *((volatile unsigned int*)(0x42CE1B08UL)) -#define bFM3_ETHERNET_MAC1_RGSR_LS *((volatile unsigned int*)(0x42CE1B0CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSE *((volatile unsigned int*)(0x42CEE000UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TFCU *((volatile unsigned int*)(0x42CEE004UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSI *((volatile unsigned int*)(0x42CEE008UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSU *((volatile unsigned int*)(0x42CEE00CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TITE *((volatile unsigned int*)(0x42CEE010UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TARU *((volatile unsigned int*)(0x42CEE014UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSEA *((volatile unsigned int*)(0x42CEE020UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSDB *((volatile unsigned int*)(0x42CEE024UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSV2E *((volatile unsigned int*)(0x42CEE028UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TETSP *((volatile unsigned int*)(0x42CEE02CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E *((volatile unsigned int*)(0x42CEE030UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E *((volatile unsigned int*)(0x42CEE034UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TETSEM *((volatile unsigned int*)(0x42CEE038UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSMRM *((volatile unsigned int*)(0x42CEE03CUL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSPS0 *((volatile unsigned int*)(0x42CEE040UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSPS1 *((volatile unsigned int*)(0x42CEE044UL)) -#define bFM3_ETHERNET_MAC1_TSCR_TSENMF *((volatile unsigned int*)(0x42CEE048UL)) -#define bFM3_ETHERNET_MAC1_TSCR_ATSFC *((volatile unsigned int*)(0x42CEE060UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC0 *((volatile unsigned int*)(0x42CEE080UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC1 *((volatile unsigned int*)(0x42CEE084UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC2 *((volatile unsigned int*)(0x42CEE088UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC3 *((volatile unsigned int*)(0x42CEE08CUL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC4 *((volatile unsigned int*)(0x42CEE090UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC5 *((volatile unsigned int*)(0x42CEE094UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC6 *((volatile unsigned int*)(0x42CEE098UL)) -#define bFM3_ETHERNET_MAC1_SSIR_SSINC7 *((volatile unsigned int*)(0x42CEE09CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS0 *((volatile unsigned int*)(0x42CEE100UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS1 *((volatile unsigned int*)(0x42CEE104UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS2 *((volatile unsigned int*)(0x42CEE108UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS3 *((volatile unsigned int*)(0x42CEE10CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS4 *((volatile unsigned int*)(0x42CEE110UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS5 *((volatile unsigned int*)(0x42CEE114UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS6 *((volatile unsigned int*)(0x42CEE118UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS7 *((volatile unsigned int*)(0x42CEE11CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS8 *((volatile unsigned int*)(0x42CEE120UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS9 *((volatile unsigned int*)(0x42CEE124UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS10 *((volatile unsigned int*)(0x42CEE128UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS11 *((volatile unsigned int*)(0x42CEE12CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS12 *((volatile unsigned int*)(0x42CEE130UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS13 *((volatile unsigned int*)(0x42CEE134UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS14 *((volatile unsigned int*)(0x42CEE138UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS15 *((volatile unsigned int*)(0x42CEE13CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS16 *((volatile unsigned int*)(0x42CEE140UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS17 *((volatile unsigned int*)(0x42CEE144UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS18 *((volatile unsigned int*)(0x42CEE148UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS19 *((volatile unsigned int*)(0x42CEE14CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS20 *((volatile unsigned int*)(0x42CEE150UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS21 *((volatile unsigned int*)(0x42CEE154UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS22 *((volatile unsigned int*)(0x42CEE158UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS23 *((volatile unsigned int*)(0x42CEE15CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS24 *((volatile unsigned int*)(0x42CEE160UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS25 *((volatile unsigned int*)(0x42CEE164UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS26 *((volatile unsigned int*)(0x42CEE168UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS27 *((volatile unsigned int*)(0x42CEE16CUL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS28 *((volatile unsigned int*)(0x42CEE170UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS29 *((volatile unsigned int*)(0x42CEE174UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS30 *((volatile unsigned int*)(0x42CEE178UL)) -#define bFM3_ETHERNET_MAC1_STSR_TSS31 *((volatile unsigned int*)(0x42CEE17CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS0 *((volatile unsigned int*)(0x42CEE080UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS1 *((volatile unsigned int*)(0x42CEE084UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS2 *((volatile unsigned int*)(0x42CEE088UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS3 *((volatile unsigned int*)(0x42CEE08CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS4 *((volatile unsigned int*)(0x42CEE090UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS5 *((volatile unsigned int*)(0x42CEE094UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS6 *((volatile unsigned int*)(0x42CEE098UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS7 *((volatile unsigned int*)(0x42CEE09CUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS8 *((volatile unsigned int*)(0x42CEE0A0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS9 *((volatile unsigned int*)(0x42CEE0A4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS10 *((volatile unsigned int*)(0x42CEE0A8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS11 *((volatile unsigned int*)(0x42CEE0ACUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS12 *((volatile unsigned int*)(0x42CEE0B0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS13 *((volatile unsigned int*)(0x42CEE0B4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS14 *((volatile unsigned int*)(0x42CEE0B8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS15 *((volatile unsigned int*)(0x42CEE0BCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS16 *((volatile unsigned int*)(0x42CEE0C0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS17 *((volatile unsigned int*)(0x42CEE0C4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS18 *((volatile unsigned int*)(0x42CEE0C8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS19 *((volatile unsigned int*)(0x42CEE0CCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS20 *((volatile unsigned int*)(0x42CEE0D0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS21 *((volatile unsigned int*)(0x42CEE0D4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS22 *((volatile unsigned int*)(0x42CEE0D8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS23 *((volatile unsigned int*)(0x42CEE0DCUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS24 *((volatile unsigned int*)(0x42CEE0E0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS25 *((volatile unsigned int*)(0x42CEE0E4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS26 *((volatile unsigned int*)(0x42CEE0E8UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS27 *((volatile unsigned int*)(0x42CEE0ECUL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS28 *((volatile unsigned int*)(0x42CEE0F0UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS29 *((volatile unsigned int*)(0x42CEE0F4UL)) -#define bFM3_ETHERNET_MAC1_STNR_TSSS30 *((volatile unsigned int*)(0x42CEE0F8UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS0 *((volatile unsigned int*)(0x42CEE200UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS1 *((volatile unsigned int*)(0x42CEE204UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS2 *((volatile unsigned int*)(0x42CEE208UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS3 *((volatile unsigned int*)(0x42CEE20CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS4 *((volatile unsigned int*)(0x42CEE210UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS5 *((volatile unsigned int*)(0x42CEE214UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS6 *((volatile unsigned int*)(0x42CEE218UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS7 *((volatile unsigned int*)(0x42CEE21CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS8 *((volatile unsigned int*)(0x42CEE220UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS9 *((volatile unsigned int*)(0x42CEE224UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS10 *((volatile unsigned int*)(0x42CEE228UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS11 *((volatile unsigned int*)(0x42CEE22CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS12 *((volatile unsigned int*)(0x42CEE230UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS13 *((volatile unsigned int*)(0x42CEE234UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS14 *((volatile unsigned int*)(0x42CEE238UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS15 *((volatile unsigned int*)(0x42CEE23CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS16 *((volatile unsigned int*)(0x42CEE240UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS17 *((volatile unsigned int*)(0x42CEE244UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS18 *((volatile unsigned int*)(0x42CEE248UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS19 *((volatile unsigned int*)(0x42CEE24CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS20 *((volatile unsigned int*)(0x42CEE250UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS21 *((volatile unsigned int*)(0x42CEE254UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS22 *((volatile unsigned int*)(0x42CEE258UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS23 *((volatile unsigned int*)(0x42CEE25CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS24 *((volatile unsigned int*)(0x42CEE260UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS25 *((volatile unsigned int*)(0x42CEE264UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS26 *((volatile unsigned int*)(0x42CEE268UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS27 *((volatile unsigned int*)(0x42CEE26CUL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS28 *((volatile unsigned int*)(0x42CEE270UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS29 *((volatile unsigned int*)(0x42CEE274UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS30 *((volatile unsigned int*)(0x42CEE278UL)) -#define bFM3_ETHERNET_MAC1_STSUR_TSS31 *((volatile unsigned int*)(0x42CEE27CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS0 *((volatile unsigned int*)(0x42CEE280UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS1 *((volatile unsigned int*)(0x42CEE284UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS2 *((volatile unsigned int*)(0x42CEE288UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS3 *((volatile unsigned int*)(0x42CEE28CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS4 *((volatile unsigned int*)(0x42CEE290UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS5 *((volatile unsigned int*)(0x42CEE294UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS6 *((volatile unsigned int*)(0x42CEE298UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS7 *((volatile unsigned int*)(0x42CEE29CUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS8 *((volatile unsigned int*)(0x42CEE2A0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS9 *((volatile unsigned int*)(0x42CEE2A4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS10 *((volatile unsigned int*)(0x42CEE2A8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS11 *((volatile unsigned int*)(0x42CEE2ACUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS12 *((volatile unsigned int*)(0x42CEE2B0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS13 *((volatile unsigned int*)(0x42CEE2B4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS14 *((volatile unsigned int*)(0x42CEE2B8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS15 *((volatile unsigned int*)(0x42CEE2BCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS16 *((volatile unsigned int*)(0x42CEE2C0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS17 *((volatile unsigned int*)(0x42CEE2C4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS18 *((volatile unsigned int*)(0x42CEE2C8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS19 *((volatile unsigned int*)(0x42CEE2CCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS20 *((volatile unsigned int*)(0x42CEE2D0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS21 *((volatile unsigned int*)(0x42CEE2D4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS22 *((volatile unsigned int*)(0x42CEE2D8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS23 *((volatile unsigned int*)(0x42CEE2DCUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS24 *((volatile unsigned int*)(0x42CEE2E0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS25 *((volatile unsigned int*)(0x42CEE2E4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS26 *((volatile unsigned int*)(0x42CEE2E8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS27 *((volatile unsigned int*)(0x42CEE2ECUL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS28 *((volatile unsigned int*)(0x42CEE2F0UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS29 *((volatile unsigned int*)(0x42CEE2F4UL)) -#define bFM3_ETHERNET_MAC1_STNUR_TSSS30 *((volatile unsigned int*)(0x42CEE2F8UL)) -#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB *((volatile unsigned int*)(0x42CEE2FCUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR0 *((volatile unsigned int*)(0x42CEE300UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR1 *((volatile unsigned int*)(0x42CEE304UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR2 *((volatile unsigned int*)(0x42CEE308UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR3 *((volatile unsigned int*)(0x42CEE30CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR4 *((volatile unsigned int*)(0x42CEE310UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR5 *((volatile unsigned int*)(0x42CEE314UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR6 *((volatile unsigned int*)(0x42CEE318UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR7 *((volatile unsigned int*)(0x42CEE31CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR8 *((volatile unsigned int*)(0x42CEE320UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR9 *((volatile unsigned int*)(0x42CEE324UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR10 *((volatile unsigned int*)(0x42CEE328UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR11 *((volatile unsigned int*)(0x42CEE32CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR12 *((volatile unsigned int*)(0x42CEE330UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR13 *((volatile unsigned int*)(0x42CEE334UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR14 *((volatile unsigned int*)(0x42CEE338UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR15 *((volatile unsigned int*)(0x42CEE33CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR16 *((volatile unsigned int*)(0x42CEE340UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR17 *((volatile unsigned int*)(0x42CEE344UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR18 *((volatile unsigned int*)(0x42CEE348UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR19 *((volatile unsigned int*)(0x42CEE34CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR20 *((volatile unsigned int*)(0x42CEE350UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR21 *((volatile unsigned int*)(0x42CEE354UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR22 *((volatile unsigned int*)(0x42CEE358UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR23 *((volatile unsigned int*)(0x42CEE35CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR24 *((volatile unsigned int*)(0x42CEE360UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR25 *((volatile unsigned int*)(0x42CEE364UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR26 *((volatile unsigned int*)(0x42CEE368UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR27 *((volatile unsigned int*)(0x42CEE36CUL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR28 *((volatile unsigned int*)(0x42CEE370UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR29 *((volatile unsigned int*)(0x42CEE374UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR30 *((volatile unsigned int*)(0x42CEE378UL)) -#define bFM3_ETHERNET_MAC1_TSAR_TSAR31 *((volatile unsigned int*)(0x42CEE37CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR0 *((volatile unsigned int*)(0x42CEE380UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR1 *((volatile unsigned int*)(0x42CEE384UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR2 *((volatile unsigned int*)(0x42CEE388UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR3 *((volatile unsigned int*)(0x42CEE38CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR4 *((volatile unsigned int*)(0x42CEE390UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR5 *((volatile unsigned int*)(0x42CEE394UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR6 *((volatile unsigned int*)(0x42CEE398UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR7 *((volatile unsigned int*)(0x42CEE39CUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR8 *((volatile unsigned int*)(0x42CEE3A0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR9 *((volatile unsigned int*)(0x42CEE3A4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR10 *((volatile unsigned int*)(0x42CEE3A8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR11 *((volatile unsigned int*)(0x42CEE3ACUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR12 *((volatile unsigned int*)(0x42CEE3B0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR13 *((volatile unsigned int*)(0x42CEE3B4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR14 *((volatile unsigned int*)(0x42CEE3B8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR15 *((volatile unsigned int*)(0x42CEE3BCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR16 *((volatile unsigned int*)(0x42CEE3C0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR17 *((volatile unsigned int*)(0x42CEE3C4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR18 *((volatile unsigned int*)(0x42CEE3C8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR19 *((volatile unsigned int*)(0x42CEE3CCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR20 *((volatile unsigned int*)(0x42CEE3D0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR21 *((volatile unsigned int*)(0x42CEE3D4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR22 *((volatile unsigned int*)(0x42CEE3D8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR23 *((volatile unsigned int*)(0x42CEE3DCUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR24 *((volatile unsigned int*)(0x42CEE3E0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR25 *((volatile unsigned int*)(0x42CEE3E4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR26 *((volatile unsigned int*)(0x42CEE3E8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR27 *((volatile unsigned int*)(0x42CEE3ECUL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR28 *((volatile unsigned int*)(0x42CEE3F0UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR29 *((volatile unsigned int*)(0x42CEE3F4UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR30 *((volatile unsigned int*)(0x42CEE3F8UL)) -#define bFM3_ETHERNET_MAC1_TTSR_TSTR31 *((volatile unsigned int*)(0x42CEE3FCUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR0 *((volatile unsigned int*)(0x42CEE400UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR1 *((volatile unsigned int*)(0x42CEE404UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR2 *((volatile unsigned int*)(0x42CEE408UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR3 *((volatile unsigned int*)(0x42CEE40CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR4 *((volatile unsigned int*)(0x42CEE410UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR5 *((volatile unsigned int*)(0x42CEE414UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR6 *((volatile unsigned int*)(0x42CEE418UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR7 *((volatile unsigned int*)(0x42CEE41CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR8 *((volatile unsigned int*)(0x42CEE420UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR9 *((volatile unsigned int*)(0x42CEE424UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR10 *((volatile unsigned int*)(0x42CEE428UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR11 *((volatile unsigned int*)(0x42CEE42CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR12 *((volatile unsigned int*)(0x42CEE430UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR13 *((volatile unsigned int*)(0x42CEE434UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR14 *((volatile unsigned int*)(0x42CEE438UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR15 *((volatile unsigned int*)(0x42CEE43CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR16 *((volatile unsigned int*)(0x42CEE440UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR17 *((volatile unsigned int*)(0x42CEE444UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR18 *((volatile unsigned int*)(0x42CEE448UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR19 *((volatile unsigned int*)(0x42CEE44CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR20 *((volatile unsigned int*)(0x42CEE450UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR21 *((volatile unsigned int*)(0x42CEE454UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR22 *((volatile unsigned int*)(0x42CEE458UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR23 *((volatile unsigned int*)(0x42CEE45CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR24 *((volatile unsigned int*)(0x42CEE460UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR25 *((volatile unsigned int*)(0x42CEE464UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR26 *((volatile unsigned int*)(0x42CEE468UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR27 *((volatile unsigned int*)(0x42CEE46CUL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR28 *((volatile unsigned int*)(0x42CEE470UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR29 *((volatile unsigned int*)(0x42CEE474UL)) -#define bFM3_ETHERNET_MAC1_TTNR_TSTR30 *((volatile unsigned int*)(0x42CEE478UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0 *((volatile unsigned int*)(0x42CEE480UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1 *((volatile unsigned int*)(0x42CEE484UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2 *((volatile unsigned int*)(0x42CEE488UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3 *((volatile unsigned int*)(0x42CEE48CUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4 *((volatile unsigned int*)(0x42CEE490UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5 *((volatile unsigned int*)(0x42CEE494UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6 *((volatile unsigned int*)(0x42CEE498UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7 *((volatile unsigned int*)(0x42CEE49CUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8 *((volatile unsigned int*)(0x42CEE4A0UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9 *((volatile unsigned int*)(0x42CEE4A4UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10 *((volatile unsigned int*)(0x42CEE4A8UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11 *((volatile unsigned int*)(0x42CEE4ACUL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12 *((volatile unsigned int*)(0x42CEE4B0UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13 *((volatile unsigned int*)(0x42CEE4B4UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14 *((volatile unsigned int*)(0x42CEE4B8UL)) -#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15 *((volatile unsigned int*)(0x42CEE4BCUL)) -#define bFM3_ETHERNET_MAC1_TSR_TSSOVF *((volatile unsigned int*)(0x42CEE500UL)) -#define bFM3_ETHERNET_MAC1_TSR_TSTART *((volatile unsigned int*)(0x42CEE504UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSTS *((volatile unsigned int*)(0x42CEE508UL)) -#define bFM3_ETHERNET_MAC1_TSR_TRGTER *((volatile unsigned int*)(0x42C8E50CUL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSSTM *((volatile unsigned int*)(0x42CEE560UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS0 *((volatile unsigned int*)(0x42CEE564UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS1 *((volatile unsigned int*)(0x42CEE568UL)) -#define bFM3_ETHERNET_MAC1_TSR_ATSNS2 *((volatile unsigned int*)(0x42CEE56CUL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0 *((volatile unsigned int*)(0x42CEE580UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1 *((volatile unsigned int*)(0x42CEE584UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2 *((volatile unsigned int*)(0x42CEE588UL)) -#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3 *((volatile unsigned int*)(0x42CEE58CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN0 *((volatile unsigned int*)(0x42CEE600UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN1 *((volatile unsigned int*)(0x42CEE604UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN2 *((volatile unsigned int*)(0x42CEE608UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN3 *((volatile unsigned int*)(0x42CEE60CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN4 *((volatile unsigned int*)(0x42CEE610UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN5 *((volatile unsigned int*)(0x42CEE614UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN6 *((volatile unsigned int*)(0x42CEE618UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN7 *((volatile unsigned int*)(0x42CEE61CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN8 *((volatile unsigned int*)(0x42CEE620UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN9 *((volatile unsigned int*)(0x42CEE624UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN10 *((volatile unsigned int*)(0x42CEE628UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN11 *((volatile unsigned int*)(0x42CEE62CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN12 *((volatile unsigned int*)(0x42CEE630UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN13 *((volatile unsigned int*)(0x42CEE634UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN14 *((volatile unsigned int*)(0x42CEE638UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN15 *((volatile unsigned int*)(0x42CEE63CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN16 *((volatile unsigned int*)(0x42CEE640UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN17 *((volatile unsigned int*)(0x42CEE644UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN18 *((volatile unsigned int*)(0x42CEE648UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN19 *((volatile unsigned int*)(0x42CEE64CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN20 *((volatile unsigned int*)(0x42CEE650UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN21 *((volatile unsigned int*)(0x42CEE654UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN22 *((volatile unsigned int*)(0x42CEE658UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN23 *((volatile unsigned int*)(0x42CEE65CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN24 *((volatile unsigned int*)(0x42CEE660UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN25 *((volatile unsigned int*)(0x42CEE664UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN26 *((volatile unsigned int*)(0x42CEE668UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN27 *((volatile unsigned int*)(0x42CEE66CUL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN28 *((volatile unsigned int*)(0x42CEE670UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN29 *((volatile unsigned int*)(0x42CEE674UL)) -#define bFM3_ETHERNET_MAC1_ATNR_ATN30 *((volatile unsigned int*)(0x42CEE678UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS0 *((volatile unsigned int*)(0x42CEE680UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS1 *((volatile unsigned int*)(0x42CEE684UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS2 *((volatile unsigned int*)(0x42CEE688UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS3 *((volatile unsigned int*)(0x42CEE68CUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS4 *((volatile unsigned int*)(0x42CEE690UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS5 *((volatile unsigned int*)(0x42CEE694UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS6 *((volatile unsigned int*)(0x42CEE698UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS7 *((volatile unsigned int*)(0x42CEE69CUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS8 *((volatile unsigned int*)(0x42CEE6A0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS9 *((volatile unsigned int*)(0x42CEE6A4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS10 *((volatile unsigned int*)(0x42CEE6A8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS11 *((volatile unsigned int*)(0x42CEE6ACUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS12 *((volatile unsigned int*)(0x42CEE6B0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS13 *((volatile unsigned int*)(0x42CEE6B4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS14 *((volatile unsigned int*)(0x42CEE6B8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS15 *((volatile unsigned int*)(0x42CEE6BCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS16 *((volatile unsigned int*)(0x42CEE6C0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS17 *((volatile unsigned int*)(0x42CEE6C4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS18 *((volatile unsigned int*)(0x42CEE6C8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS19 *((volatile unsigned int*)(0x42CEE6CCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS20 *((volatile unsigned int*)(0x42CEE6D0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS21 *((volatile unsigned int*)(0x42CEE6D4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS22 *((volatile unsigned int*)(0x42CEE6D8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS23 *((volatile unsigned int*)(0x42CEE6DCUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS24 *((volatile unsigned int*)(0x42CEE6E0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS25 *((volatile unsigned int*)(0x42CEE6E4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS26 *((volatile unsigned int*)(0x42CEE6E8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS27 *((volatile unsigned int*)(0x42CEE6ECUL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS28 *((volatile unsigned int*)(0x42CEE6F0UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS29 *((volatile unsigned int*)(0x42CEE6F4UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS30 *((volatile unsigned int*)(0x42CEE6F8UL)) -#define bFM3_ETHERNET_MAC1_ATSR_ATS31 *((volatile unsigned int*)(0x42CEE6FCUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A32 *((volatile unsigned int*)(0x42CF0000UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A33 *((volatile unsigned int*)(0x42CF0004UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A34 *((volatile unsigned int*)(0x42CF0008UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A35 *((volatile unsigned int*)(0x42CF000CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A36 *((volatile unsigned int*)(0x42CF0010UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A37 *((volatile unsigned int*)(0x42CF0014UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A38 *((volatile unsigned int*)(0x42CF0018UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A39 *((volatile unsigned int*)(0x42CF001CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A40 *((volatile unsigned int*)(0x42CF0020UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A41 *((volatile unsigned int*)(0x42CF0024UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A42 *((volatile unsigned int*)(0x42CF0028UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A43 *((volatile unsigned int*)(0x42CF002CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A44 *((volatile unsigned int*)(0x42CF0030UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A45 *((volatile unsigned int*)(0x42CF0034UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A46 *((volatile unsigned int*)(0x42CF0038UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_A47 *((volatile unsigned int*)(0x42CF003CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC0 *((volatile unsigned int*)(0x42CF0060UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC1 *((volatile unsigned int*)(0x42CF0064UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC2 *((volatile unsigned int*)(0x42CF0068UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC3 *((volatile unsigned int*)(0x42CF006CUL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC4 *((volatile unsigned int*)(0x42CF0070UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_MBC5 *((volatile unsigned int*)(0x42CF0074UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_SA *((volatile unsigned int*)(0x42CF0078UL)) -#define bFM3_ETHERNET_MAC1_MAR16H_AE *((volatile unsigned int*)(0x42CF007CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A0 *((volatile unsigned int*)(0x42CF0080UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A1 *((volatile unsigned int*)(0x42CF0084UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A2 *((volatile unsigned int*)(0x42CF0088UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A3 *((volatile unsigned int*)(0x42CF008CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A4 *((volatile unsigned int*)(0x42CF0090UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A5 *((volatile unsigned int*)(0x42CF0094UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A6 *((volatile unsigned int*)(0x42CF0098UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A7 *((volatile unsigned int*)(0x42CF009CUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A8 *((volatile unsigned int*)(0x42CF00A0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A9 *((volatile unsigned int*)(0x42CF00A4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A10 *((volatile unsigned int*)(0x42CF00A8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A11 *((volatile unsigned int*)(0x42CF00ACUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A12 *((volatile unsigned int*)(0x42CF00B0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A13 *((volatile unsigned int*)(0x42CF00B4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A14 *((volatile unsigned int*)(0x42CF00B8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A15 *((volatile unsigned int*)(0x42CF00BCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A16 *((volatile unsigned int*)(0x42CF00C0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A17 *((volatile unsigned int*)(0x42CF00C4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A18 *((volatile unsigned int*)(0x42CF00C8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A19 *((volatile unsigned int*)(0x42CF00CCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A20 *((volatile unsigned int*)(0x42CF00D0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A21 *((volatile unsigned int*)(0x42CF00D4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A22 *((volatile unsigned int*)(0x42CF00D8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A23 *((volatile unsigned int*)(0x42CF00DCUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A24 *((volatile unsigned int*)(0x42CF00E0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A25 *((volatile unsigned int*)(0x42CF00E4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A26 *((volatile unsigned int*)(0x42CF00E8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A27 *((volatile unsigned int*)(0x42CF00ECUL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A28 *((volatile unsigned int*)(0x42CF00F0UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A29 *((volatile unsigned int*)(0x42CF00F4UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A30 *((volatile unsigned int*)(0x42CF00F8UL)) -#define bFM3_ETHERNET_MAC1_MAR16L_A31 *((volatile unsigned int*)(0x42CF00FCUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A32 *((volatile unsigned int*)(0x42CF0100UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A33 *((volatile unsigned int*)(0x42CF0104UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A34 *((volatile unsigned int*)(0x42CF0108UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A35 *((volatile unsigned int*)(0x42CF010CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A36 *((volatile unsigned int*)(0x42CF0110UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A37 *((volatile unsigned int*)(0x42CF0114UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A38 *((volatile unsigned int*)(0x42CF0118UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A39 *((volatile unsigned int*)(0x42CF011CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A40 *((volatile unsigned int*)(0x42CF0120UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A41 *((volatile unsigned int*)(0x42CF0124UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A42 *((volatile unsigned int*)(0x42CF0128UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A43 *((volatile unsigned int*)(0x42CF012CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A44 *((volatile unsigned int*)(0x42CF0130UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A45 *((volatile unsigned int*)(0x42CF0134UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A46 *((volatile unsigned int*)(0x42CF0138UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_A47 *((volatile unsigned int*)(0x42CF013CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC0 *((volatile unsigned int*)(0x42CF0160UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC1 *((volatile unsigned int*)(0x42CF0164UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC2 *((volatile unsigned int*)(0x42CF0168UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC3 *((volatile unsigned int*)(0x42CF016CUL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC4 *((volatile unsigned int*)(0x42CF0170UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_MBC5 *((volatile unsigned int*)(0x42CF0174UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_SA *((volatile unsigned int*)(0x42CF0178UL)) -#define bFM3_ETHERNET_MAC1_MAR17H_AE *((volatile unsigned int*)(0x42CF017CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A0 *((volatile unsigned int*)(0x42CF0180UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A1 *((volatile unsigned int*)(0x42CF0184UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A2 *((volatile unsigned int*)(0x42CF0188UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A3 *((volatile unsigned int*)(0x42CF018CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A4 *((volatile unsigned int*)(0x42CF0190UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A5 *((volatile unsigned int*)(0x42CF0194UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A6 *((volatile unsigned int*)(0x42CF0198UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A7 *((volatile unsigned int*)(0x42CF019CUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A8 *((volatile unsigned int*)(0x42CF01A0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A9 *((volatile unsigned int*)(0x42CF01A4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A10 *((volatile unsigned int*)(0x42CF01A8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A11 *((volatile unsigned int*)(0x42CF01ACUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A12 *((volatile unsigned int*)(0x42CF01B0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A13 *((volatile unsigned int*)(0x42CF01B4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A14 *((volatile unsigned int*)(0x42CF01B8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A15 *((volatile unsigned int*)(0x42CF01BCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A16 *((volatile unsigned int*)(0x42CF01C0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A17 *((volatile unsigned int*)(0x42CF01C4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A18 *((volatile unsigned int*)(0x42CF01C8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A19 *((volatile unsigned int*)(0x42CF01CCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A20 *((volatile unsigned int*)(0x42CF01D0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A21 *((volatile unsigned int*)(0x42CF01D4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A22 *((volatile unsigned int*)(0x42CF01D8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A23 *((volatile unsigned int*)(0x42CF01DCUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A24 *((volatile unsigned int*)(0x42CF01E0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A25 *((volatile unsigned int*)(0x42CF01E4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A26 *((volatile unsigned int*)(0x42CF01E8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A27 *((volatile unsigned int*)(0x42CF01ECUL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A28 *((volatile unsigned int*)(0x42CF01F0UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A29 *((volatile unsigned int*)(0x42CF01F4UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A30 *((volatile unsigned int*)(0x42CF01F8UL)) -#define bFM3_ETHERNET_MAC1_MAR17L_A31 *((volatile unsigned int*)(0x42CF01FCUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A32 *((volatile unsigned int*)(0x42CF0200UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A33 *((volatile unsigned int*)(0x42CF0204UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A34 *((volatile unsigned int*)(0x42CF0208UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A35 *((volatile unsigned int*)(0x42CF020CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A36 *((volatile unsigned int*)(0x42CF0210UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A37 *((volatile unsigned int*)(0x42CF0214UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A38 *((volatile unsigned int*)(0x42CF0218UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A39 *((volatile unsigned int*)(0x42CF021CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A40 *((volatile unsigned int*)(0x42CF0220UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A41 *((volatile unsigned int*)(0x42CF0224UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A42 *((volatile unsigned int*)(0x42CF0228UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A43 *((volatile unsigned int*)(0x42CF022CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A44 *((volatile unsigned int*)(0x42CF0230UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A45 *((volatile unsigned int*)(0x42CF0234UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A46 *((volatile unsigned int*)(0x42CF0238UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_A47 *((volatile unsigned int*)(0x42CF023CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC0 *((volatile unsigned int*)(0x42CF0260UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC1 *((volatile unsigned int*)(0x42CF0264UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC2 *((volatile unsigned int*)(0x42CF0268UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC3 *((volatile unsigned int*)(0x42CF026CUL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC4 *((volatile unsigned int*)(0x42CF0270UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_MBC5 *((volatile unsigned int*)(0x42CF0274UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_SA *((volatile unsigned int*)(0x42CF0278UL)) -#define bFM3_ETHERNET_MAC1_MAR18H_AE *((volatile unsigned int*)(0x42CF027CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A0 *((volatile unsigned int*)(0x42CF0280UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A1 *((volatile unsigned int*)(0x42CF0284UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A2 *((volatile unsigned int*)(0x42CF0288UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A3 *((volatile unsigned int*)(0x42CF028CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A4 *((volatile unsigned int*)(0x42CF0290UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A5 *((volatile unsigned int*)(0x42CF0294UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A6 *((volatile unsigned int*)(0x42CF0298UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A7 *((volatile unsigned int*)(0x42CF029CUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A8 *((volatile unsigned int*)(0x42CF02A0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A9 *((volatile unsigned int*)(0x42CF02A4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A10 *((volatile unsigned int*)(0x42CF02A8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A11 *((volatile unsigned int*)(0x42CF02ACUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A12 *((volatile unsigned int*)(0x42CF02B0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A13 *((volatile unsigned int*)(0x42CF02B4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A14 *((volatile unsigned int*)(0x42CF02B8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A15 *((volatile unsigned int*)(0x42CF02BCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A16 *((volatile unsigned int*)(0x42CF02C0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A17 *((volatile unsigned int*)(0x42CF02C4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A18 *((volatile unsigned int*)(0x42CF02C8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A19 *((volatile unsigned int*)(0x42CF02CCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A20 *((volatile unsigned int*)(0x42CF02D0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A21 *((volatile unsigned int*)(0x42CF02D4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A22 *((volatile unsigned int*)(0x42CF02D8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A23 *((volatile unsigned int*)(0x42CF02DCUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A24 *((volatile unsigned int*)(0x42CF02E0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A25 *((volatile unsigned int*)(0x42CF02E4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A26 *((volatile unsigned int*)(0x42CF02E8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A27 *((volatile unsigned int*)(0x42CF02ECUL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A28 *((volatile unsigned int*)(0x42CF02F0UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A29 *((volatile unsigned int*)(0x42CF02F4UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A30 *((volatile unsigned int*)(0x42CF02F8UL)) -#define bFM3_ETHERNET_MAC1_MAR18L_A31 *((volatile unsigned int*)(0x42CF02FCUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A32 *((volatile unsigned int*)(0x42CF0300UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A33 *((volatile unsigned int*)(0x42CF0304UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A34 *((volatile unsigned int*)(0x42CF0308UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A35 *((volatile unsigned int*)(0x42CF030CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A36 *((volatile unsigned int*)(0x42CF0310UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A37 *((volatile unsigned int*)(0x42CF0314UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A38 *((volatile unsigned int*)(0x42CF0318UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A39 *((volatile unsigned int*)(0x42CF031CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A40 *((volatile unsigned int*)(0x42CF0320UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A41 *((volatile unsigned int*)(0x42CF0324UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A42 *((volatile unsigned int*)(0x42CF0328UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A43 *((volatile unsigned int*)(0x42CF032CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A44 *((volatile unsigned int*)(0x42CF0330UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A45 *((volatile unsigned int*)(0x42CF0334UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A46 *((volatile unsigned int*)(0x42CF0338UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_A47 *((volatile unsigned int*)(0x42CF033CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC0 *((volatile unsigned int*)(0x42CF0360UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC1 *((volatile unsigned int*)(0x42CF0364UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC2 *((volatile unsigned int*)(0x42CF0368UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC3 *((volatile unsigned int*)(0x42CF036CUL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC4 *((volatile unsigned int*)(0x42CF0370UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_MBC5 *((volatile unsigned int*)(0x42CF0374UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_SA *((volatile unsigned int*)(0x42CF0378UL)) -#define bFM3_ETHERNET_MAC1_MAR19H_AE *((volatile unsigned int*)(0x42CF037CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A0 *((volatile unsigned int*)(0x42CF0380UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A1 *((volatile unsigned int*)(0x42CF0384UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A2 *((volatile unsigned int*)(0x42CF0388UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A3 *((volatile unsigned int*)(0x42CF038CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A4 *((volatile unsigned int*)(0x42CF0390UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A5 *((volatile unsigned int*)(0x42CF0394UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A6 *((volatile unsigned int*)(0x42CF0398UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A7 *((volatile unsigned int*)(0x42CF039CUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A8 *((volatile unsigned int*)(0x42CF03A0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A9 *((volatile unsigned int*)(0x42CF03A4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A10 *((volatile unsigned int*)(0x42CF03A8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A11 *((volatile unsigned int*)(0x42CF03ACUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A12 *((volatile unsigned int*)(0x42CF03B0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A13 *((volatile unsigned int*)(0x42CF03B4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A14 *((volatile unsigned int*)(0x42CF03B8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A15 *((volatile unsigned int*)(0x42CF03BCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A16 *((volatile unsigned int*)(0x42CF03C0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A17 *((volatile unsigned int*)(0x42CF03C4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A18 *((volatile unsigned int*)(0x42CF03C8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A19 *((volatile unsigned int*)(0x42CF03CCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A20 *((volatile unsigned int*)(0x42CF03D0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A21 *((volatile unsigned int*)(0x42CF03D4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A22 *((volatile unsigned int*)(0x42CF03D8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A23 *((volatile unsigned int*)(0x42CF03DCUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A24 *((volatile unsigned int*)(0x42CF03E0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A25 *((volatile unsigned int*)(0x42CF03E4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A26 *((volatile unsigned int*)(0x42CF03E8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A27 *((volatile unsigned int*)(0x42CF03ECUL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A28 *((volatile unsigned int*)(0x42CF03F0UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A29 *((volatile unsigned int*)(0x42CF03F4UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A30 *((volatile unsigned int*)(0x42CF03F8UL)) -#define bFM3_ETHERNET_MAC1_MAR19L_A31 *((volatile unsigned int*)(0x42CF03FCUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A32 *((volatile unsigned int*)(0x42CF0400UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A33 *((volatile unsigned int*)(0x42CF0404UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A34 *((volatile unsigned int*)(0x42CF0408UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A35 *((volatile unsigned int*)(0x42CF040CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A36 *((volatile unsigned int*)(0x42CF0410UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A37 *((volatile unsigned int*)(0x42CF0414UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A38 *((volatile unsigned int*)(0x42CF0418UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A39 *((volatile unsigned int*)(0x42CF041CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A40 *((volatile unsigned int*)(0x42CF0420UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A41 *((volatile unsigned int*)(0x42CF0424UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A42 *((volatile unsigned int*)(0x42CF0428UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A43 *((volatile unsigned int*)(0x42CF042CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A44 *((volatile unsigned int*)(0x42CF0430UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A45 *((volatile unsigned int*)(0x42CF0434UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A46 *((volatile unsigned int*)(0x42CF0438UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_A47 *((volatile unsigned int*)(0x42CF043CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC0 *((volatile unsigned int*)(0x42CF0460UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC1 *((volatile unsigned int*)(0x42CF0464UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC2 *((volatile unsigned int*)(0x42CF0468UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC3 *((volatile unsigned int*)(0x42CF046CUL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC4 *((volatile unsigned int*)(0x42CF0470UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_MBC5 *((volatile unsigned int*)(0x42CF0474UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_SA *((volatile unsigned int*)(0x42CF0478UL)) -#define bFM3_ETHERNET_MAC1_MAR20H_AE *((volatile unsigned int*)(0x42CF047CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A0 *((volatile unsigned int*)(0x42CF0480UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A1 *((volatile unsigned int*)(0x42CF0484UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A2 *((volatile unsigned int*)(0x42CF0488UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A3 *((volatile unsigned int*)(0x42CF048CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A4 *((volatile unsigned int*)(0x42CF0490UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A5 *((volatile unsigned int*)(0x42CF0494UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A6 *((volatile unsigned int*)(0x42CF0498UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A7 *((volatile unsigned int*)(0x42CF049CUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A8 *((volatile unsigned int*)(0x42CF04A0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A9 *((volatile unsigned int*)(0x42CF04A4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A10 *((volatile unsigned int*)(0x42CF04A8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A11 *((volatile unsigned int*)(0x42CF04ACUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A12 *((volatile unsigned int*)(0x42CF04B0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A13 *((volatile unsigned int*)(0x42CF04B4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A14 *((volatile unsigned int*)(0x42CF04B8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A15 *((volatile unsigned int*)(0x42CF04BCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A16 *((volatile unsigned int*)(0x42CF04C0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A17 *((volatile unsigned int*)(0x42CF04C4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A18 *((volatile unsigned int*)(0x42CF04C8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A19 *((volatile unsigned int*)(0x42CF04CCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A20 *((volatile unsigned int*)(0x42CF04D0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A21 *((volatile unsigned int*)(0x42CF04D4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A22 *((volatile unsigned int*)(0x42CF04D8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A23 *((volatile unsigned int*)(0x42CF04DCUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A24 *((volatile unsigned int*)(0x42CF04E0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A25 *((volatile unsigned int*)(0x42CF04E4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A26 *((volatile unsigned int*)(0x42CF04E8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A27 *((volatile unsigned int*)(0x42CF04ECUL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A28 *((volatile unsigned int*)(0x42CF04F0UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A29 *((volatile unsigned int*)(0x42CF04F4UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A30 *((volatile unsigned int*)(0x42CF04F8UL)) -#define bFM3_ETHERNET_MAC1_MAR20L_A31 *((volatile unsigned int*)(0x42CF04FCUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A32 *((volatile unsigned int*)(0x42CF0500UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A33 *((volatile unsigned int*)(0x42CF0504UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A34 *((volatile unsigned int*)(0x42CF0508UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A35 *((volatile unsigned int*)(0x42CF050CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A36 *((volatile unsigned int*)(0x42CF0510UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A37 *((volatile unsigned int*)(0x42CF0514UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A38 *((volatile unsigned int*)(0x42CF0518UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A39 *((volatile unsigned int*)(0x42CF051CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A40 *((volatile unsigned int*)(0x42CF0520UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A41 *((volatile unsigned int*)(0x42CF0524UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A42 *((volatile unsigned int*)(0x42CF0528UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A43 *((volatile unsigned int*)(0x42CF052CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A44 *((volatile unsigned int*)(0x42CF0530UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A45 *((volatile unsigned int*)(0x42CF0534UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A46 *((volatile unsigned int*)(0x42CF0538UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_A47 *((volatile unsigned int*)(0x42CF053CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC0 *((volatile unsigned int*)(0x42CF0560UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC1 *((volatile unsigned int*)(0x42CF0564UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC2 *((volatile unsigned int*)(0x42CF0568UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC3 *((volatile unsigned int*)(0x42CF056CUL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC4 *((volatile unsigned int*)(0x42CF0570UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_MBC5 *((volatile unsigned int*)(0x42CF0574UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_SA *((volatile unsigned int*)(0x42CF0578UL)) -#define bFM3_ETHERNET_MAC1_MAR21H_AE *((volatile unsigned int*)(0x42CF057CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A0 *((volatile unsigned int*)(0x42CF0580UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A1 *((volatile unsigned int*)(0x42CF0584UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A2 *((volatile unsigned int*)(0x42CF0588UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A3 *((volatile unsigned int*)(0x42CF058CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A4 *((volatile unsigned int*)(0x42CF0590UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A5 *((volatile unsigned int*)(0x42CF0594UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A6 *((volatile unsigned int*)(0x42CF0598UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A7 *((volatile unsigned int*)(0x42CF059CUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A8 *((volatile unsigned int*)(0x42CF05A0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A9 *((volatile unsigned int*)(0x42CF05A4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A10 *((volatile unsigned int*)(0x42CF05A8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A11 *((volatile unsigned int*)(0x42CF05ACUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A12 *((volatile unsigned int*)(0x42CF05B0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A13 *((volatile unsigned int*)(0x42CF05B4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A14 *((volatile unsigned int*)(0x42CF05B8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A15 *((volatile unsigned int*)(0x42CF05BCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A16 *((volatile unsigned int*)(0x42CF05C0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A17 *((volatile unsigned int*)(0x42CF05C4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A18 *((volatile unsigned int*)(0x42CF05C8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A19 *((volatile unsigned int*)(0x42CF05CCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A20 *((volatile unsigned int*)(0x42CF05D0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A21 *((volatile unsigned int*)(0x42CF05D4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A22 *((volatile unsigned int*)(0x42CF05D8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A23 *((volatile unsigned int*)(0x42CF05DCUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A24 *((volatile unsigned int*)(0x42CF05E0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A25 *((volatile unsigned int*)(0x42CF05E4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A26 *((volatile unsigned int*)(0x42CF05E8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A27 *((volatile unsigned int*)(0x42CF05ECUL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A28 *((volatile unsigned int*)(0x42CF05F0UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A29 *((volatile unsigned int*)(0x42CF05F4UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A30 *((volatile unsigned int*)(0x42CF05F8UL)) -#define bFM3_ETHERNET_MAC1_MAR21L_A31 *((volatile unsigned int*)(0x42CF05FCUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A32 *((volatile unsigned int*)(0x42CF0600UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A33 *((volatile unsigned int*)(0x42CF0604UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A34 *((volatile unsigned int*)(0x42CF0608UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A35 *((volatile unsigned int*)(0x42CF060CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A36 *((volatile unsigned int*)(0x42CF0610UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A37 *((volatile unsigned int*)(0x42CF0614UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A38 *((volatile unsigned int*)(0x42CF0618UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A39 *((volatile unsigned int*)(0x42CF061CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A40 *((volatile unsigned int*)(0x42CF0620UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A41 *((volatile unsigned int*)(0x42CF0624UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A42 *((volatile unsigned int*)(0x42CF0628UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A43 *((volatile unsigned int*)(0x42CF062CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A44 *((volatile unsigned int*)(0x42CF0630UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A45 *((volatile unsigned int*)(0x42CF0634UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A46 *((volatile unsigned int*)(0x42CF0638UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_A47 *((volatile unsigned int*)(0x42CF063CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC0 *((volatile unsigned int*)(0x42CF0660UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC1 *((volatile unsigned int*)(0x42CF0664UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC2 *((volatile unsigned int*)(0x42CF0668UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC3 *((volatile unsigned int*)(0x42CF066CUL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC4 *((volatile unsigned int*)(0x42CF0670UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_MBC5 *((volatile unsigned int*)(0x42CF0674UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_SA *((volatile unsigned int*)(0x42CF0678UL)) -#define bFM3_ETHERNET_MAC1_MAR22H_AE *((volatile unsigned int*)(0x42CF067CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A0 *((volatile unsigned int*)(0x42CF0680UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A1 *((volatile unsigned int*)(0x42CF0684UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A2 *((volatile unsigned int*)(0x42CF0688UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A3 *((volatile unsigned int*)(0x42CF068CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A4 *((volatile unsigned int*)(0x42CF0690UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A5 *((volatile unsigned int*)(0x42CF0694UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A6 *((volatile unsigned int*)(0x42CF0698UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A7 *((volatile unsigned int*)(0x42CF069CUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A8 *((volatile unsigned int*)(0x42CF06A0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A9 *((volatile unsigned int*)(0x42CF06A4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A10 *((volatile unsigned int*)(0x42CF06A8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A11 *((volatile unsigned int*)(0x42CF06ACUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A12 *((volatile unsigned int*)(0x42CF06B0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A13 *((volatile unsigned int*)(0x42CF06B4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A14 *((volatile unsigned int*)(0x42CF06B8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A15 *((volatile unsigned int*)(0x42CF06BCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A16 *((volatile unsigned int*)(0x42CF06C0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A17 *((volatile unsigned int*)(0x42CF06C4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A18 *((volatile unsigned int*)(0x42CF06C8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A19 *((volatile unsigned int*)(0x42CF06CCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A20 *((volatile unsigned int*)(0x42CF06D0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A21 *((volatile unsigned int*)(0x42CF06D4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A22 *((volatile unsigned int*)(0x42CF06D8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A23 *((volatile unsigned int*)(0x42CF06DCUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A24 *((volatile unsigned int*)(0x42CF06E0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A25 *((volatile unsigned int*)(0x42CF06E4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A26 *((volatile unsigned int*)(0x42CF06E8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A27 *((volatile unsigned int*)(0x42CF06ECUL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A28 *((volatile unsigned int*)(0x42CF06F0UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A29 *((volatile unsigned int*)(0x42CF06F4UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A30 *((volatile unsigned int*)(0x42CF06F8UL)) -#define bFM3_ETHERNET_MAC1_MAR22L_A31 *((volatile unsigned int*)(0x42CF06FCUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A32 *((volatile unsigned int*)(0x42CF0700UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A33 *((volatile unsigned int*)(0x42CF0704UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A34 *((volatile unsigned int*)(0x42CF0708UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A35 *((volatile unsigned int*)(0x42CF070CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A36 *((volatile unsigned int*)(0x42CF0710UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A37 *((volatile unsigned int*)(0x42CF0714UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A38 *((volatile unsigned int*)(0x42CF0718UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A39 *((volatile unsigned int*)(0x42CF071CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A40 *((volatile unsigned int*)(0x42CF0720UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A41 *((volatile unsigned int*)(0x42CF0724UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A42 *((volatile unsigned int*)(0x42CF0728UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A43 *((volatile unsigned int*)(0x42CF072CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A44 *((volatile unsigned int*)(0x42CF0730UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A45 *((volatile unsigned int*)(0x42CF0734UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A46 *((volatile unsigned int*)(0x42CF0738UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_A47 *((volatile unsigned int*)(0x42CF073CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC0 *((volatile unsigned int*)(0x42CF0760UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC1 *((volatile unsigned int*)(0x42CF0764UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC2 *((volatile unsigned int*)(0x42CF0768UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC3 *((volatile unsigned int*)(0x42CF076CUL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC4 *((volatile unsigned int*)(0x42CF0770UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_MBC5 *((volatile unsigned int*)(0x42CF0774UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_SA *((volatile unsigned int*)(0x42CF0778UL)) -#define bFM3_ETHERNET_MAC1_MAR23H_AE *((volatile unsigned int*)(0x42CF077CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A0 *((volatile unsigned int*)(0x42CF0780UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A1 *((volatile unsigned int*)(0x42CF0784UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A2 *((volatile unsigned int*)(0x42CF0788UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A3 *((volatile unsigned int*)(0x42CF078CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A4 *((volatile unsigned int*)(0x42CF0790UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A5 *((volatile unsigned int*)(0x42CF0794UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A6 *((volatile unsigned int*)(0x42CF0798UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A7 *((volatile unsigned int*)(0x42CF079CUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A8 *((volatile unsigned int*)(0x42CF07A0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A9 *((volatile unsigned int*)(0x42CF07A4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A10 *((volatile unsigned int*)(0x42CF07A8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A11 *((volatile unsigned int*)(0x42CF07ACUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A12 *((volatile unsigned int*)(0x42CF07B0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A13 *((volatile unsigned int*)(0x42CF07B4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A14 *((volatile unsigned int*)(0x42CF07B8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A15 *((volatile unsigned int*)(0x42CF07BCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A16 *((volatile unsigned int*)(0x42CF07C0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A17 *((volatile unsigned int*)(0x42CF07C4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A18 *((volatile unsigned int*)(0x42CF07C8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A19 *((volatile unsigned int*)(0x42CF07CCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A20 *((volatile unsigned int*)(0x42CF07D0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A21 *((volatile unsigned int*)(0x42CF07D4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A22 *((volatile unsigned int*)(0x42CF07D8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A23 *((volatile unsigned int*)(0x42CF07DCUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A24 *((volatile unsigned int*)(0x42CF07E0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A25 *((volatile unsigned int*)(0x42CF07E4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A26 *((volatile unsigned int*)(0x42CF07E8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A27 *((volatile unsigned int*)(0x42CF07ECUL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A28 *((volatile unsigned int*)(0x42CF07F0UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A29 *((volatile unsigned int*)(0x42CF07F4UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A30 *((volatile unsigned int*)(0x42CF07F8UL)) -#define bFM3_ETHERNET_MAC1_MAR23L_A31 *((volatile unsigned int*)(0x42CF07FCUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A32 *((volatile unsigned int*)(0x42CF0800UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A33 *((volatile unsigned int*)(0x42CF0804UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A34 *((volatile unsigned int*)(0x42CF0808UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A35 *((volatile unsigned int*)(0x42CF080CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A36 *((volatile unsigned int*)(0x42CF0810UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A37 *((volatile unsigned int*)(0x42CF0814UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A38 *((volatile unsigned int*)(0x42CF0818UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A39 *((volatile unsigned int*)(0x42CF081CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A40 *((volatile unsigned int*)(0x42CF0820UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A41 *((volatile unsigned int*)(0x42CF0824UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A42 *((volatile unsigned int*)(0x42CF0828UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A43 *((volatile unsigned int*)(0x42CF082CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A44 *((volatile unsigned int*)(0x42CF0830UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A45 *((volatile unsigned int*)(0x42CF0834UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A46 *((volatile unsigned int*)(0x42CF0838UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_A47 *((volatile unsigned int*)(0x42CF083CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC0 *((volatile unsigned int*)(0x42CF0860UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC1 *((volatile unsigned int*)(0x42CF0864UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC2 *((volatile unsigned int*)(0x42CF0868UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC3 *((volatile unsigned int*)(0x42CF086CUL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC4 *((volatile unsigned int*)(0x42CF0870UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_MBC5 *((volatile unsigned int*)(0x42CF0874UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_SA *((volatile unsigned int*)(0x42CF0878UL)) -#define bFM3_ETHERNET_MAC1_MAR24H_AE *((volatile unsigned int*)(0x42CF087CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A0 *((volatile unsigned int*)(0x42CF0880UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A1 *((volatile unsigned int*)(0x42CF0884UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A2 *((volatile unsigned int*)(0x42CF0888UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A3 *((volatile unsigned int*)(0x42CF088CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A4 *((volatile unsigned int*)(0x42CF0890UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A5 *((volatile unsigned int*)(0x42CF0894UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A6 *((volatile unsigned int*)(0x42CF0898UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A7 *((volatile unsigned int*)(0x42CF089CUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A8 *((volatile unsigned int*)(0x42CF08A0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A9 *((volatile unsigned int*)(0x42CF08A4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A10 *((volatile unsigned int*)(0x42CF08A8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A11 *((volatile unsigned int*)(0x42CF08ACUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A12 *((volatile unsigned int*)(0x42CF08B0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A13 *((volatile unsigned int*)(0x42CF08B4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A14 *((volatile unsigned int*)(0x42CF08B8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A15 *((volatile unsigned int*)(0x42CF08BCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A16 *((volatile unsigned int*)(0x42CF08C0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A17 *((volatile unsigned int*)(0x42CF08C4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A18 *((volatile unsigned int*)(0x42CF08C8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A19 *((volatile unsigned int*)(0x42CF08CCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A20 *((volatile unsigned int*)(0x42CF08D0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A21 *((volatile unsigned int*)(0x42CF08D4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A22 *((volatile unsigned int*)(0x42CF08D8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A23 *((volatile unsigned int*)(0x42CF08DCUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A24 *((volatile unsigned int*)(0x42CF08E0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A25 *((volatile unsigned int*)(0x42CF08E4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A26 *((volatile unsigned int*)(0x42CF08E8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A27 *((volatile unsigned int*)(0x42CF08ECUL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A28 *((volatile unsigned int*)(0x42CF08F0UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A29 *((volatile unsigned int*)(0x42CF08F4UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A30 *((volatile unsigned int*)(0x42CF08F8UL)) -#define bFM3_ETHERNET_MAC1_MAR24L_A31 *((volatile unsigned int*)(0x42CF08FCUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A32 *((volatile unsigned int*)(0x42CF0900UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A33 *((volatile unsigned int*)(0x42CF0904UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A34 *((volatile unsigned int*)(0x42CF0908UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A35 *((volatile unsigned int*)(0x42CF090CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A36 *((volatile unsigned int*)(0x42CF0910UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A37 *((volatile unsigned int*)(0x42CF0914UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A38 *((volatile unsigned int*)(0x42CF0918UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A39 *((volatile unsigned int*)(0x42CF091CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A40 *((volatile unsigned int*)(0x42CF0920UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A41 *((volatile unsigned int*)(0x42CF0924UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A42 *((volatile unsigned int*)(0x42CF0928UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A43 *((volatile unsigned int*)(0x42CF092CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A44 *((volatile unsigned int*)(0x42CF0930UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A45 *((volatile unsigned int*)(0x42CF0934UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A46 *((volatile unsigned int*)(0x42CF0938UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_A47 *((volatile unsigned int*)(0x42CF093CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC0 *((volatile unsigned int*)(0x42CF0960UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC1 *((volatile unsigned int*)(0x42CF0964UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC2 *((volatile unsigned int*)(0x42CF0968UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC3 *((volatile unsigned int*)(0x42CF096CUL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC4 *((volatile unsigned int*)(0x42CF0970UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_MBC5 *((volatile unsigned int*)(0x42CF0974UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_SA *((volatile unsigned int*)(0x42CF0978UL)) -#define bFM3_ETHERNET_MAC1_MAR25H_AE *((volatile unsigned int*)(0x42CF097CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A0 *((volatile unsigned int*)(0x42CF0980UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A1 *((volatile unsigned int*)(0x42CF0984UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A2 *((volatile unsigned int*)(0x42CF0988UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A3 *((volatile unsigned int*)(0x42CF098CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A4 *((volatile unsigned int*)(0x42CF0990UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A5 *((volatile unsigned int*)(0x42CF0994UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A6 *((volatile unsigned int*)(0x42CF0998UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A7 *((volatile unsigned int*)(0x42CF099CUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A8 *((volatile unsigned int*)(0x42CF09A0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A9 *((volatile unsigned int*)(0x42CF09A4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A10 *((volatile unsigned int*)(0x42CF09A8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A11 *((volatile unsigned int*)(0x42CF09ACUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A12 *((volatile unsigned int*)(0x42CF09B0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A13 *((volatile unsigned int*)(0x42CF09B4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A14 *((volatile unsigned int*)(0x42CF09B8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A15 *((volatile unsigned int*)(0x42CF09BCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A16 *((volatile unsigned int*)(0x42CF09C0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A17 *((volatile unsigned int*)(0x42CF09C4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A18 *((volatile unsigned int*)(0x42CF09C8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A19 *((volatile unsigned int*)(0x42CF09CCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A20 *((volatile unsigned int*)(0x42CF09D0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A21 *((volatile unsigned int*)(0x42CF09D4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A22 *((volatile unsigned int*)(0x42CF09D8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A23 *((volatile unsigned int*)(0x42CF09DCUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A24 *((volatile unsigned int*)(0x42CF09E0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A25 *((volatile unsigned int*)(0x42CF09E4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A26 *((volatile unsigned int*)(0x42CF09E8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A27 *((volatile unsigned int*)(0x42CF09ECUL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A28 *((volatile unsigned int*)(0x42CF09F0UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A29 *((volatile unsigned int*)(0x42CF09F4UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A30 *((volatile unsigned int*)(0x42CF09F8UL)) -#define bFM3_ETHERNET_MAC1_MAR25L_A31 *((volatile unsigned int*)(0x42CF09FCUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A32 *((volatile unsigned int*)(0x42CF0A00UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A33 *((volatile unsigned int*)(0x42CF0A04UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A34 *((volatile unsigned int*)(0x42CF0A08UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A35 *((volatile unsigned int*)(0x42CF0A0CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A36 *((volatile unsigned int*)(0x42CF0A10UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A37 *((volatile unsigned int*)(0x42CF0A14UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A38 *((volatile unsigned int*)(0x42CF0A18UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A39 *((volatile unsigned int*)(0x42CF0A1CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A40 *((volatile unsigned int*)(0x42CF0A20UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A41 *((volatile unsigned int*)(0x42CF0A24UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A42 *((volatile unsigned int*)(0x42CF0A28UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A43 *((volatile unsigned int*)(0x42CF0A2CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A44 *((volatile unsigned int*)(0x42CF0A30UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A45 *((volatile unsigned int*)(0x42CF0A34UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A46 *((volatile unsigned int*)(0x42CF0A38UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_A47 *((volatile unsigned int*)(0x42CF0A3CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC0 *((volatile unsigned int*)(0x42CF0A60UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC1 *((volatile unsigned int*)(0x42CF0A64UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC2 *((volatile unsigned int*)(0x42CF0A68UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC3 *((volatile unsigned int*)(0x42CF0A6CUL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC4 *((volatile unsigned int*)(0x42CF0A70UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_MBC5 *((volatile unsigned int*)(0x42CF0A74UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_SA *((volatile unsigned int*)(0x42CF0A78UL)) -#define bFM3_ETHERNET_MAC1_MAR26H_AE *((volatile unsigned int*)(0x42CF0A7CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A0 *((volatile unsigned int*)(0x42CF0A80UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A1 *((volatile unsigned int*)(0x42CF0A84UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A2 *((volatile unsigned int*)(0x42CF0A88UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A3 *((volatile unsigned int*)(0x42CF0A8CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A4 *((volatile unsigned int*)(0x42CF0A90UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A5 *((volatile unsigned int*)(0x42CF0A94UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A6 *((volatile unsigned int*)(0x42CF0A98UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A7 *((volatile unsigned int*)(0x42CF0A9CUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A8 *((volatile unsigned int*)(0x42CF0AA0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A9 *((volatile unsigned int*)(0x42CF0AA4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A10 *((volatile unsigned int*)(0x42CF0AA8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A11 *((volatile unsigned int*)(0x42CF0AACUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A12 *((volatile unsigned int*)(0x42CF0AB0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A13 *((volatile unsigned int*)(0x42CF0AB4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A14 *((volatile unsigned int*)(0x42CF0AB8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A15 *((volatile unsigned int*)(0x42CF0ABCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A16 *((volatile unsigned int*)(0x42CF0AC0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A17 *((volatile unsigned int*)(0x42CF0AC4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A18 *((volatile unsigned int*)(0x42CF0AC8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A19 *((volatile unsigned int*)(0x42CF0ACCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A20 *((volatile unsigned int*)(0x42CF0AD0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A21 *((volatile unsigned int*)(0x42CF0AD4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A22 *((volatile unsigned int*)(0x42CF0AD8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A23 *((volatile unsigned int*)(0x42CF0ADCUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A24 *((volatile unsigned int*)(0x42CF0AE0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A25 *((volatile unsigned int*)(0x42CF0AE4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A26 *((volatile unsigned int*)(0x42CF0AE8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A27 *((volatile unsigned int*)(0x42CF0AECUL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A28 *((volatile unsigned int*)(0x42CF0AF0UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A29 *((volatile unsigned int*)(0x42CF0AF4UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A30 *((volatile unsigned int*)(0x42CF0AF8UL)) -#define bFM3_ETHERNET_MAC1_MAR26L_A31 *((volatile unsigned int*)(0x42CF0AFCUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A32 *((volatile unsigned int*)(0x42CF0B00UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A33 *((volatile unsigned int*)(0x42CF0B04UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A34 *((volatile unsigned int*)(0x42CF0B08UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A35 *((volatile unsigned int*)(0x42CF0B0CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A36 *((volatile unsigned int*)(0x42CF0B10UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A37 *((volatile unsigned int*)(0x42CF0B14UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A38 *((volatile unsigned int*)(0x42CF0B18UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A39 *((volatile unsigned int*)(0x42CF0B1CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A40 *((volatile unsigned int*)(0x42CF0B20UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A41 *((volatile unsigned int*)(0x42CF0B24UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A42 *((volatile unsigned int*)(0x42CF0B28UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A43 *((volatile unsigned int*)(0x42CF0B2CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A44 *((volatile unsigned int*)(0x42CF0B30UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A45 *((volatile unsigned int*)(0x42CF0B34UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A46 *((volatile unsigned int*)(0x42CF0B38UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_A47 *((volatile unsigned int*)(0x42CF0B3CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC0 *((volatile unsigned int*)(0x42CF0B60UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC1 *((volatile unsigned int*)(0x42CF0B64UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC2 *((volatile unsigned int*)(0x42CF0B68UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC3 *((volatile unsigned int*)(0x42CF0B6CUL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC4 *((volatile unsigned int*)(0x42CF0B70UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_MBC5 *((volatile unsigned int*)(0x42CF0B74UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_SA *((volatile unsigned int*)(0x42CF0B78UL)) -#define bFM3_ETHERNET_MAC1_MAR27H_AE *((volatile unsigned int*)(0x42CF0B7CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A0 *((volatile unsigned int*)(0x42CF0B80UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A1 *((volatile unsigned int*)(0x42CF0B84UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A2 *((volatile unsigned int*)(0x42CF0B88UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A3 *((volatile unsigned int*)(0x42CF0B8CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A4 *((volatile unsigned int*)(0x42CF0B90UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A5 *((volatile unsigned int*)(0x42CF0B94UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A6 *((volatile unsigned int*)(0x42CF0B98UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A7 *((volatile unsigned int*)(0x42CF0B9CUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A8 *((volatile unsigned int*)(0x42CF0BA0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A9 *((volatile unsigned int*)(0x42CF0BA4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A10 *((volatile unsigned int*)(0x42CF0BA8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A11 *((volatile unsigned int*)(0x42CF0BACUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A12 *((volatile unsigned int*)(0x42CF0BB0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A13 *((volatile unsigned int*)(0x42CF0BB4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A14 *((volatile unsigned int*)(0x42CF0BB8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A15 *((volatile unsigned int*)(0x42CF0BBCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A16 *((volatile unsigned int*)(0x42CF0BC0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A17 *((volatile unsigned int*)(0x42CF0BC4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A18 *((volatile unsigned int*)(0x42CF0BC8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A19 *((volatile unsigned int*)(0x42CF0BCCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A20 *((volatile unsigned int*)(0x42CF0BD0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A21 *((volatile unsigned int*)(0x42CF0BD4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A22 *((volatile unsigned int*)(0x42CF0BD8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A23 *((volatile unsigned int*)(0x42CF0BDCUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A24 *((volatile unsigned int*)(0x42CF0BE0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A25 *((volatile unsigned int*)(0x42CF0BE4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A26 *((volatile unsigned int*)(0x42CF0BE8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A27 *((volatile unsigned int*)(0x42CF0BECUL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A28 *((volatile unsigned int*)(0x42CF0BF0UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A29 *((volatile unsigned int*)(0x42CF0BF4UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A30 *((volatile unsigned int*)(0x42CF0BF8UL)) -#define bFM3_ETHERNET_MAC1_MAR27L_A31 *((volatile unsigned int*)(0x42CF0BFCUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A32 *((volatile unsigned int*)(0x42CF0C00UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A33 *((volatile unsigned int*)(0x42CF0C04UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A34 *((volatile unsigned int*)(0x42CF0C08UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A35 *((volatile unsigned int*)(0x42CF0C0CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A36 *((volatile unsigned int*)(0x42CF0C10UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A37 *((volatile unsigned int*)(0x42CF0C14UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A38 *((volatile unsigned int*)(0x42CF0C18UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A39 *((volatile unsigned int*)(0x42CF0C1CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A40 *((volatile unsigned int*)(0x42CF0C20UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A41 *((volatile unsigned int*)(0x42CF0C24UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A42 *((volatile unsigned int*)(0x42CF0C28UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A43 *((volatile unsigned int*)(0x42CF0C2CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A44 *((volatile unsigned int*)(0x42CF0C30UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A45 *((volatile unsigned int*)(0x42CF0C34UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A46 *((volatile unsigned int*)(0x42CF0C38UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_A47 *((volatile unsigned int*)(0x42CF0C3CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC0 *((volatile unsigned int*)(0x42CF0C60UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC1 *((volatile unsigned int*)(0x42CF0C64UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC2 *((volatile unsigned int*)(0x42CF0C68UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC3 *((volatile unsigned int*)(0x42CF0C6CUL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC4 *((volatile unsigned int*)(0x42CF0C70UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_MBC5 *((volatile unsigned int*)(0x42CF0C74UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_SA *((volatile unsigned int*)(0x42CF0C78UL)) -#define bFM3_ETHERNET_MAC1_MAR28H_AE *((volatile unsigned int*)(0x42CF0C7CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A0 *((volatile unsigned int*)(0x42CF0C80UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A1 *((volatile unsigned int*)(0x42CF0C84UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A2 *((volatile unsigned int*)(0x42CF0C88UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A3 *((volatile unsigned int*)(0x42CF0C8CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A4 *((volatile unsigned int*)(0x42CF0C90UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A5 *((volatile unsigned int*)(0x42CF0C94UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A6 *((volatile unsigned int*)(0x42CF0C98UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A7 *((volatile unsigned int*)(0x42CF0C9CUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A8 *((volatile unsigned int*)(0x42CF0CA0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A9 *((volatile unsigned int*)(0x42CF0CA4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A10 *((volatile unsigned int*)(0x42CF0CA8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A11 *((volatile unsigned int*)(0x42CF0CACUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A12 *((volatile unsigned int*)(0x42CF0CB0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A13 *((volatile unsigned int*)(0x42CF0CB4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A14 *((volatile unsigned int*)(0x42CF0CB8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A15 *((volatile unsigned int*)(0x42CF0CBCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A16 *((volatile unsigned int*)(0x42CF0CC0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A17 *((volatile unsigned int*)(0x42CF0CC4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A18 *((volatile unsigned int*)(0x42CF0CC8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A19 *((volatile unsigned int*)(0x42CF0CCCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A20 *((volatile unsigned int*)(0x42CF0CD0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A21 *((volatile unsigned int*)(0x42CF0CD4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A22 *((volatile unsigned int*)(0x42CF0CD8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A23 *((volatile unsigned int*)(0x42CF0CDCUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A24 *((volatile unsigned int*)(0x42CF0CE0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A25 *((volatile unsigned int*)(0x42CF0CE4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A26 *((volatile unsigned int*)(0x42CF0CE8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A27 *((volatile unsigned int*)(0x42CF0CECUL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A28 *((volatile unsigned int*)(0x42CF0CF0UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A29 *((volatile unsigned int*)(0x42CF0CF4UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A30 *((volatile unsigned int*)(0x42CF0CF8UL)) -#define bFM3_ETHERNET_MAC1_MAR28L_A31 *((volatile unsigned int*)(0x42CF0CFCUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A32 *((volatile unsigned int*)(0x42CF0D00UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A33 *((volatile unsigned int*)(0x42CF0D04UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A34 *((volatile unsigned int*)(0x42CF0D08UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A35 *((volatile unsigned int*)(0x42CF0D0CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A36 *((volatile unsigned int*)(0x42CF0D10UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A37 *((volatile unsigned int*)(0x42CF0D14UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A38 *((volatile unsigned int*)(0x42CF0D18UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A39 *((volatile unsigned int*)(0x42CF0D1CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A40 *((volatile unsigned int*)(0x42CF0D20UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A41 *((volatile unsigned int*)(0x42CF0D24UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A42 *((volatile unsigned int*)(0x42CF0D28UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A43 *((volatile unsigned int*)(0x42CF0D2CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A44 *((volatile unsigned int*)(0x42CF0D30UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A45 *((volatile unsigned int*)(0x42CF0D34UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A46 *((volatile unsigned int*)(0x42CF0D38UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_A47 *((volatile unsigned int*)(0x42CF0D3CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC0 *((volatile unsigned int*)(0x42CF0D60UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC1 *((volatile unsigned int*)(0x42CF0D64UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC2 *((volatile unsigned int*)(0x42CF0D68UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC3 *((volatile unsigned int*)(0x42CF0D6CUL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC4 *((volatile unsigned int*)(0x42CF0D70UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_MBC5 *((volatile unsigned int*)(0x42CF0D74UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_SA *((volatile unsigned int*)(0x42CF0D78UL)) -#define bFM3_ETHERNET_MAC1_MAR29H_AE *((volatile unsigned int*)(0x42CF0D7CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A0 *((volatile unsigned int*)(0x42CF0D80UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A1 *((volatile unsigned int*)(0x42CF0D84UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A2 *((volatile unsigned int*)(0x42CF0D88UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A3 *((volatile unsigned int*)(0x42CF0D8CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A4 *((volatile unsigned int*)(0x42CF0D90UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A5 *((volatile unsigned int*)(0x42CF0D94UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A6 *((volatile unsigned int*)(0x42CF0D98UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A7 *((volatile unsigned int*)(0x42CF0D9CUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A8 *((volatile unsigned int*)(0x42CF0DA0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A9 *((volatile unsigned int*)(0x42CF0DA4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A10 *((volatile unsigned int*)(0x42CF0DA8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A11 *((volatile unsigned int*)(0x42CF0DACUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A12 *((volatile unsigned int*)(0x42CF0DB0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A13 *((volatile unsigned int*)(0x42CF0DB4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A14 *((volatile unsigned int*)(0x42CF0DB8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A15 *((volatile unsigned int*)(0x42CF0DBCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A16 *((volatile unsigned int*)(0x42CF0DC0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A17 *((volatile unsigned int*)(0x42CF0DC4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A18 *((volatile unsigned int*)(0x42CF0DC8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A19 *((volatile unsigned int*)(0x42CF0DCCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A20 *((volatile unsigned int*)(0x42CF0DD0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A21 *((volatile unsigned int*)(0x42CF0DD4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A22 *((volatile unsigned int*)(0x42CF0DD8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A23 *((volatile unsigned int*)(0x42CF0DDCUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A24 *((volatile unsigned int*)(0x42CF0DE0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A25 *((volatile unsigned int*)(0x42CF0DE4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A26 *((volatile unsigned int*)(0x42CF0DE8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A27 *((volatile unsigned int*)(0x42CF0DECUL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A28 *((volatile unsigned int*)(0x42CF0DF0UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A29 *((volatile unsigned int*)(0x42CF0DF4UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A30 *((volatile unsigned int*)(0x42CF0DF8UL)) -#define bFM3_ETHERNET_MAC1_MAR29L_A31 *((volatile unsigned int*)(0x42CF0DFCUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A32 *((volatile unsigned int*)(0x42CF0E00UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A33 *((volatile unsigned int*)(0x42CF0E04UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A34 *((volatile unsigned int*)(0x42CF0E08UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A35 *((volatile unsigned int*)(0x42CF0E0CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A36 *((volatile unsigned int*)(0x42CF0E10UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A37 *((volatile unsigned int*)(0x42CF0E14UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A38 *((volatile unsigned int*)(0x42CF0E18UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A39 *((volatile unsigned int*)(0x42CF0E1CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A40 *((volatile unsigned int*)(0x42CF0E20UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A41 *((volatile unsigned int*)(0x42CF0E24UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A42 *((volatile unsigned int*)(0x42CF0E28UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A43 *((volatile unsigned int*)(0x42CF0E2CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A44 *((volatile unsigned int*)(0x42CF0E30UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A45 *((volatile unsigned int*)(0x42CF0E34UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A46 *((volatile unsigned int*)(0x42CF0E38UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_A47 *((volatile unsigned int*)(0x42CF0E3CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC0 *((volatile unsigned int*)(0x42CF0E60UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC1 *((volatile unsigned int*)(0x42CF0E64UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC2 *((volatile unsigned int*)(0x42CF0E68UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC3 *((volatile unsigned int*)(0x42CF0E6CUL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC4 *((volatile unsigned int*)(0x42CF0E70UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_MBC5 *((volatile unsigned int*)(0x42CF0E74UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_SA *((volatile unsigned int*)(0x42CF0E78UL)) -#define bFM3_ETHERNET_MAC1_MAR30H_AE *((volatile unsigned int*)(0x42CF0E7CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A0 *((volatile unsigned int*)(0x42CF0E80UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A1 *((volatile unsigned int*)(0x42CF0E84UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A2 *((volatile unsigned int*)(0x42CF0E88UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A3 *((volatile unsigned int*)(0x42CF0E8CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A4 *((volatile unsigned int*)(0x42CF0E90UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A5 *((volatile unsigned int*)(0x42CF0E94UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A6 *((volatile unsigned int*)(0x42CF0E98UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A7 *((volatile unsigned int*)(0x42CF0E9CUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A8 *((volatile unsigned int*)(0x42CF0EA0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A9 *((volatile unsigned int*)(0x42CF0EA4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A10 *((volatile unsigned int*)(0x42CF0EA8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A11 *((volatile unsigned int*)(0x42CF0EACUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A12 *((volatile unsigned int*)(0x42CF0EB0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A13 *((volatile unsigned int*)(0x42CF0EB4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A14 *((volatile unsigned int*)(0x42CF0EB8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A15 *((volatile unsigned int*)(0x42CF0EBCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A16 *((volatile unsigned int*)(0x42CF0EC0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A17 *((volatile unsigned int*)(0x42CF0EC4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A18 *((volatile unsigned int*)(0x42CF0EC8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A19 *((volatile unsigned int*)(0x42CF0ECCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A20 *((volatile unsigned int*)(0x42CF0ED0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A21 *((volatile unsigned int*)(0x42CF0ED4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A22 *((volatile unsigned int*)(0x42CF0ED8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A23 *((volatile unsigned int*)(0x42CF0EDCUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A24 *((volatile unsigned int*)(0x42CF0EE0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A25 *((volatile unsigned int*)(0x42CF0EE4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A26 *((volatile unsigned int*)(0x42CF0EE8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A27 *((volatile unsigned int*)(0x42CF0EECUL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A28 *((volatile unsigned int*)(0x42CF0EF0UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A29 *((volatile unsigned int*)(0x42CF0EF4UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A30 *((volatile unsigned int*)(0x42CF0EF8UL)) -#define bFM3_ETHERNET_MAC1_MAR30L_A31 *((volatile unsigned int*)(0x42CF0EFCUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A32 *((volatile unsigned int*)(0x42CF0F00UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A33 *((volatile unsigned int*)(0x42CF0F04UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A34 *((volatile unsigned int*)(0x42CF0F08UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A35 *((volatile unsigned int*)(0x42CF0F0CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A36 *((volatile unsigned int*)(0x42CF0F10UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A37 *((volatile unsigned int*)(0x42CF0F14UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A38 *((volatile unsigned int*)(0x42CF0F18UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A39 *((volatile unsigned int*)(0x42CF0F1CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A40 *((volatile unsigned int*)(0x42CF0F20UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A41 *((volatile unsigned int*)(0x42CF0F24UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A42 *((volatile unsigned int*)(0x42CF0F28UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A43 *((volatile unsigned int*)(0x42CF0F2CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A44 *((volatile unsigned int*)(0x42CF0F30UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A45 *((volatile unsigned int*)(0x42CF0F34UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A46 *((volatile unsigned int*)(0x42CF0F38UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_A47 *((volatile unsigned int*)(0x42CF0F3CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC0 *((volatile unsigned int*)(0x42CF0F60UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC1 *((volatile unsigned int*)(0x42CF0F64UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC2 *((volatile unsigned int*)(0x42CF0F68UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC3 *((volatile unsigned int*)(0x42CF0F6CUL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC4 *((volatile unsigned int*)(0x42CF0F70UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_MBC5 *((volatile unsigned int*)(0x42CF0F74UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_SA *((volatile unsigned int*)(0x42CF0F78UL)) -#define bFM3_ETHERNET_MAC1_MAR31H_AE *((volatile unsigned int*)(0x42CF0F7CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A0 *((volatile unsigned int*)(0x42CF0F80UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A1 *((volatile unsigned int*)(0x42CF0F84UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A2 *((volatile unsigned int*)(0x42CF0F88UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A3 *((volatile unsigned int*)(0x42CF0F8CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A4 *((volatile unsigned int*)(0x42CF0F90UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A5 *((volatile unsigned int*)(0x42CF0F94UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A6 *((volatile unsigned int*)(0x42CF0F98UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A7 *((volatile unsigned int*)(0x42CF0F9CUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A8 *((volatile unsigned int*)(0x42CF0FA0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A9 *((volatile unsigned int*)(0x42CF0FA4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A10 *((volatile unsigned int*)(0x42CF0FA8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A11 *((volatile unsigned int*)(0x42CF0FACUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A12 *((volatile unsigned int*)(0x42CF0FB0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A13 *((volatile unsigned int*)(0x42CF0FB4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A14 *((volatile unsigned int*)(0x42CF0FB8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A15 *((volatile unsigned int*)(0x42CF0FBCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A16 *((volatile unsigned int*)(0x42CF0FC0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A17 *((volatile unsigned int*)(0x42CF0FC4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A18 *((volatile unsigned int*)(0x42CF0FC8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A19 *((volatile unsigned int*)(0x42CF0FCCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A20 *((volatile unsigned int*)(0x42CF0FD0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A21 *((volatile unsigned int*)(0x42CF0FD4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A22 *((volatile unsigned int*)(0x42CF0FD8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A23 *((volatile unsigned int*)(0x42CF0FDCUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A24 *((volatile unsigned int*)(0x42CF0FE0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A25 *((volatile unsigned int*)(0x42CF0FE4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A26 *((volatile unsigned int*)(0x42CF0FE8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A27 *((volatile unsigned int*)(0x42CF0FECUL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A28 *((volatile unsigned int*)(0x42CF0FF0UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A29 *((volatile unsigned int*)(0x42CF0FF4UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A30 *((volatile unsigned int*)(0x42CF0FF8UL)) -#define bFM3_ETHERNET_MAC1_MAR31L_A31 *((volatile unsigned int*)(0x42CF0FFCUL)) -#define bFM3_ETHERNET_MAC1_BMR_SWR *((volatile unsigned int*)(0x42D00000UL)) -#define bFM3_ETHERNET_MAC1_BMR_DA *((volatile unsigned int*)(0x42D00004UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL0 *((volatile unsigned int*)(0x42D00008UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL1 *((volatile unsigned int*)(0x42D0000CUL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL2 *((volatile unsigned int*)(0x42D00010UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL3 *((volatile unsigned int*)(0x42D00014UL)) -#define bFM3_ETHERNET_MAC1_BMR_DSL4 *((volatile unsigned int*)(0x42D00018UL)) -#define bFM3_ETHERNET_MAC1_BMR_ATDS *((volatile unsigned int*)(0x42D0001CUL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL0 *((volatile unsigned int*)(0x42D00020UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL1 *((volatile unsigned int*)(0x42D00024UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL2 *((volatile unsigned int*)(0x42D00028UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL3 *((volatile unsigned int*)(0x42D0002CUL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL4 *((volatile unsigned int*)(0x42D00030UL)) -#define bFM3_ETHERNET_MAC1_BMR_PBL5 *((volatile unsigned int*)(0x42D00034UL)) -#define bFM3_ETHERNET_MAC1_BMR_PR0 *((volatile unsigned int*)(0x42D00038UL)) -#define bFM3_ETHERNET_MAC1_BMR_PR1 *((volatile unsigned int*)(0x42D0003CUL)) -#define bFM3_ETHERNET_MAC1_BMR_FB *((volatile unsigned int*)(0x42D00040UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL0 *((volatile unsigned int*)(0x42D00044UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL1 *((volatile unsigned int*)(0x42D00048UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL2 *((volatile unsigned int*)(0x42D0004CUL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL3 *((volatile unsigned int*)(0x42D00050UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL4 *((volatile unsigned int*)(0x42D00054UL)) -#define bFM3_ETHERNET_MAC1_BMR_RPBL5 *((volatile unsigned int*)(0x42D00058UL)) -#define bFM3_ETHERNET_MAC1_BMR_USP *((volatile unsigned int*)(0x42D0005CUL)) -#define bFM3_ETHERNET_MAC1_BMR_8XPBL *((volatile unsigned int*)(0x42D00060UL)) -#define bFM3_ETHERNET_MAC1_BMR_AAL *((volatile unsigned int*)(0x42D00064UL)) -#define bFM3_ETHERNET_MAC1_BMR_MB *((volatile unsigned int*)(0x42D00068UL)) -#define bFM3_ETHERNET_MAC1_BMR_TXPR *((volatile unsigned int*)(0x42D0006CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD0 *((volatile unsigned int*)(0x42D00080UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD1 *((volatile unsigned int*)(0x42D00084UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD2 *((volatile unsigned int*)(0x42D00088UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD3 *((volatile unsigned int*)(0x42D0008CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD4 *((volatile unsigned int*)(0x42D00090UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD5 *((volatile unsigned int*)(0x42D00094UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD6 *((volatile unsigned int*)(0x42D00098UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD7 *((volatile unsigned int*)(0x42D0009CUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD8 *((volatile unsigned int*)(0x42D000A0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD9 *((volatile unsigned int*)(0x42D000A4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD10 *((volatile unsigned int*)(0x42D000A8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD11 *((volatile unsigned int*)(0x42D000ACUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD12 *((volatile unsigned int*)(0x42D000B0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD13 *((volatile unsigned int*)(0x42D000B4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD14 *((volatile unsigned int*)(0x42D000B8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD15 *((volatile unsigned int*)(0x42D000BCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD16 *((volatile unsigned int*)(0x42D000C0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD17 *((volatile unsigned int*)(0x42D000C4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD18 *((volatile unsigned int*)(0x42D000C8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD19 *((volatile unsigned int*)(0x42D000CCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD20 *((volatile unsigned int*)(0x42D000D0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD21 *((volatile unsigned int*)(0x42D000D4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD22 *((volatile unsigned int*)(0x42D000D8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD23 *((volatile unsigned int*)(0x42D000DCUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD24 *((volatile unsigned int*)(0x42D000E0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD25 *((volatile unsigned int*)(0x42D000E4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD26 *((volatile unsigned int*)(0x42D000E8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD27 *((volatile unsigned int*)(0x42D000ECUL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD28 *((volatile unsigned int*)(0x42D000F0UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD29 *((volatile unsigned int*)(0x42D000F4UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD30 *((volatile unsigned int*)(0x42D000F8UL)) -#define bFM3_ETHERNET_MAC1_TPDR_TPD31 *((volatile unsigned int*)(0x42D000FCUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD0 *((volatile unsigned int*)(0x42D00100UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD1 *((volatile unsigned int*)(0x42D00104UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD2 *((volatile unsigned int*)(0x42D00108UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD3 *((volatile unsigned int*)(0x42D0010CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD4 *((volatile unsigned int*)(0x42D00110UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD5 *((volatile unsigned int*)(0x42D00114UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD6 *((volatile unsigned int*)(0x42D00118UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD7 *((volatile unsigned int*)(0x42D0011CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD8 *((volatile unsigned int*)(0x42D00120UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD9 *((volatile unsigned int*)(0x42D00124UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD10 *((volatile unsigned int*)(0x42D00128UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD11 *((volatile unsigned int*)(0x42D0012CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD12 *((volatile unsigned int*)(0x42D00130UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD13 *((volatile unsigned int*)(0x42D00134UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD14 *((volatile unsigned int*)(0x42D00138UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD15 *((volatile unsigned int*)(0x42D0013CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD16 *((volatile unsigned int*)(0x42D00140UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD17 *((volatile unsigned int*)(0x42D00144UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD18 *((volatile unsigned int*)(0x42D00148UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD19 *((volatile unsigned int*)(0x42D0014CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD20 *((volatile unsigned int*)(0x42D00150UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD21 *((volatile unsigned int*)(0x42D00154UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD22 *((volatile unsigned int*)(0x42D00158UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD23 *((volatile unsigned int*)(0x42D0015CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD24 *((volatile unsigned int*)(0x42D00160UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD25 *((volatile unsigned int*)(0x42D00164UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD26 *((volatile unsigned int*)(0x42D00168UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD27 *((volatile unsigned int*)(0x42D0016CUL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD28 *((volatile unsigned int*)(0x42D00170UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD29 *((volatile unsigned int*)(0x42D00174UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD30 *((volatile unsigned int*)(0x42D00178UL)) -#define bFM3_ETHERNET_MAC1_RPDR_RPD31 *((volatile unsigned int*)(0x42D0017CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL2 *((volatile unsigned int*)(0x42D00188UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL3 *((volatile unsigned int*)(0x42D0018CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL4 *((volatile unsigned int*)(0x42D00190UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL5 *((volatile unsigned int*)(0x42D00194UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL6 *((volatile unsigned int*)(0x42D00198UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL7 *((volatile unsigned int*)(0x42D0019CUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL8 *((volatile unsigned int*)(0x42D001A0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL9 *((volatile unsigned int*)(0x42D001A4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL10 *((volatile unsigned int*)(0x42D001A8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL11 *((volatile unsigned int*)(0x42D001ACUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL12 *((volatile unsigned int*)(0x42D001B0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL13 *((volatile unsigned int*)(0x42D001B4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL14 *((volatile unsigned int*)(0x42D001B8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL15 *((volatile unsigned int*)(0x42D001BCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL16 *((volatile unsigned int*)(0x42D001C0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL17 *((volatile unsigned int*)(0x42D001C4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL18 *((volatile unsigned int*)(0x42D001C8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL19 *((volatile unsigned int*)(0x42D001CCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL20 *((volatile unsigned int*)(0x42D001D0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL21 *((volatile unsigned int*)(0x42D001D4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL22 *((volatile unsigned int*)(0x42D001D8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL23 *((volatile unsigned int*)(0x42D001DCUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL24 *((volatile unsigned int*)(0x42D001E0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL25 *((volatile unsigned int*)(0x42D001E4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL26 *((volatile unsigned int*)(0x42D001E8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL27 *((volatile unsigned int*)(0x42D001ECUL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL28 *((volatile unsigned int*)(0x42D001F0UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL29 *((volatile unsigned int*)(0x42D001F4UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL30 *((volatile unsigned int*)(0x42D001F8UL)) -#define bFM3_ETHERNET_MAC1_RDLAR_SRL31 *((volatile unsigned int*)(0x42D001FCUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL2 *((volatile unsigned int*)(0x42D00208UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL3 *((volatile unsigned int*)(0x42D0020CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL4 *((volatile unsigned int*)(0x42D00210UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL5 *((volatile unsigned int*)(0x42D00214UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL6 *((volatile unsigned int*)(0x42D00218UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL7 *((volatile unsigned int*)(0x42D0021CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL8 *((volatile unsigned int*)(0x42D00220UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL9 *((volatile unsigned int*)(0x42D00224UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL10 *((volatile unsigned int*)(0x42D00228UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL11 *((volatile unsigned int*)(0x42D0022CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL12 *((volatile unsigned int*)(0x42D00230UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL13 *((volatile unsigned int*)(0x42D00234UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL14 *((volatile unsigned int*)(0x42D00238UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL15 *((volatile unsigned int*)(0x42D0023CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL16 *((volatile unsigned int*)(0x42D00240UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL17 *((volatile unsigned int*)(0x42D00244UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL18 *((volatile unsigned int*)(0x42D00248UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL19 *((volatile unsigned int*)(0x42D0024CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL20 *((volatile unsigned int*)(0x42D00250UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL21 *((volatile unsigned int*)(0x42D00254UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL22 *((volatile unsigned int*)(0x42D00258UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL23 *((volatile unsigned int*)(0x42D0025CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL24 *((volatile unsigned int*)(0x42D00260UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL25 *((volatile unsigned int*)(0x42D00264UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL26 *((volatile unsigned int*)(0x42D00268UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL27 *((volatile unsigned int*)(0x42D0026CUL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL28 *((volatile unsigned int*)(0x42D00270UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL29 *((volatile unsigned int*)(0x42D00274UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL30 *((volatile unsigned int*)(0x42D00278UL)) -#define bFM3_ETHERNET_MAC1_TDLAR_STL31 *((volatile unsigned int*)(0x42D0027CUL)) -#define bFM3_ETHERNET_MAC1_SR_TI *((volatile unsigned int*)(0x42D00280UL)) -#define bFM3_ETHERNET_MAC1_SR_TPS *((volatile unsigned int*)(0x42D00284UL)) -#define bFM3_ETHERNET_MAC1_SR_TU *((volatile unsigned int*)(0x42D00288UL)) -#define bFM3_ETHERNET_MAC1_SR_TJT *((volatile unsigned int*)(0x42D0028CUL)) -#define bFM3_ETHERNET_MAC1_SR_OVF *((volatile unsigned int*)(0x42D00290UL)) -#define bFM3_ETHERNET_MAC1_SR_UNF *((volatile unsigned int*)(0x42D00294UL)) -#define bFM3_ETHERNET_MAC1_SR_RI *((volatile unsigned int*)(0x42D00298UL)) -#define bFM3_ETHERNET_MAC1_SR_RU *((volatile unsigned int*)(0x42D0029CUL)) -#define bFM3_ETHERNET_MAC1_SR_RPS *((volatile unsigned int*)(0x42D002A0UL)) -#define bFM3_ETHERNET_MAC1_SR_RWT *((volatile unsigned int*)(0x42D002A4UL)) -#define bFM3_ETHERNET_MAC1_SR_ETI *((volatile unsigned int*)(0x42D002A8UL)) -#define bFM3_ETHERNET_MAC1_SR_FBI *((volatile unsigned int*)(0x42D002B4UL)) -#define bFM3_ETHERNET_MAC1_SR_ERI *((volatile unsigned int*)(0x42D002B8UL)) -#define bFM3_ETHERNET_MAC1_SR_AIS *((volatile unsigned int*)(0x42D002BCUL)) -#define bFM3_ETHERNET_MAC1_SR_NIS *((volatile unsigned int*)(0x42D002C0UL)) -#define bFM3_ETHERNET_MAC1_SR_RS0 *((volatile unsigned int*)(0x42D002C4UL)) -#define bFM3_ETHERNET_MAC1_SR_RS1 *((volatile unsigned int*)(0x42D002C8UL)) -#define bFM3_ETHERNET_MAC1_SR_RS2 *((volatile unsigned int*)(0x42D002CCUL)) -#define bFM3_ETHERNET_MAC1_SR_TS0 *((volatile unsigned int*)(0x42D002D0UL)) -#define bFM3_ETHERNET_MAC1_SR_TS1 *((volatile unsigned int*)(0x42D002D4UL)) -#define bFM3_ETHERNET_MAC1_SR_TS2 *((volatile unsigned int*)(0x42D002D8UL)) -#define bFM3_ETHERNET_MAC1_SR_EB0 *((volatile unsigned int*)(0x42D002DCUL)) -#define bFM3_ETHERNET_MAC1_SR_EB1 *((volatile unsigned int*)(0x42D002E0UL)) -#define bFM3_ETHERNET_MAC1_SR_EB2 *((volatile unsigned int*)(0x42D002E4UL)) -#define bFM3_ETHERNET_MAC1_SR_GLI *((volatile unsigned int*)(0x42D002E8UL)) -#define bFM3_ETHERNET_MAC1_SR_GMI *((volatile unsigned int*)(0x42D002ECUL)) -#define bFM3_ETHERNET_MAC1_SR_GPI *((volatile unsigned int*)(0x42D002F0UL)) -#define bFM3_ETHERNET_MAC1_SR_TTI *((volatile unsigned int*)(0x42D002F4UL)) -#define bFM3_ETHERNET_MAC1_SR_GLPII *((volatile unsigned int*)(0x42D002F8UL)) -#define bFM3_ETHERNET_MAC1_OMR_SR *((volatile unsigned int*)(0x42D00304UL)) -#define bFM3_ETHERNET_MAC1_OMR_OSF *((volatile unsigned int*)(0x42D00308UL)) -#define bFM3_ETHERNET_MAC1_OMR_RTC0 *((volatile unsigned int*)(0x42D0030CUL)) -#define bFM3_ETHERNET_MAC1_OMR_RTC1 *((volatile unsigned int*)(0x42D00310UL)) -#define bFM3_ETHERNET_MAC1_OMR_FUF *((volatile unsigned int*)(0x42D00318UL)) -#define bFM3_ETHERNET_MAC1_OMR_FEF *((volatile unsigned int*)(0x42D0031CUL)) -#define bFM3_ETHERNET_MAC1_OMR_ST *((volatile unsigned int*)(0x42D00334UL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC0 *((volatile unsigned int*)(0x42D00338UL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC1 *((volatile unsigned int*)(0x42D0033CUL)) -#define bFM3_ETHERNET_MAC1_OMR_TTC2 *((volatile unsigned int*)(0x42D00340UL)) -#define bFM3_ETHERNET_MAC1_OMR_FTF *((volatile unsigned int*)(0x42D00350UL)) -#define bFM3_ETHERNET_MAC1_OMR_TSF *((volatile unsigned int*)(0x42D00354UL)) -#define bFM3_ETHERNET_MAC1_OMR_DFF *((volatile unsigned int*)(0x42D00360UL)) -#define bFM3_ETHERNET_MAC1_OMR_RSF *((volatile unsigned int*)(0x42D00364UL)) -#define bFM3_ETHERNET_MAC1_OMR_DT *((volatile unsigned int*)(0x42D00368UL)) -#define bFM3_ETHERNET_MAC1_IER_TIE *((volatile unsigned int*)(0x42D00380UL)) -#define bFM3_ETHERNET_MAC1_IER_TSE *((volatile unsigned int*)(0x42D00384UL)) -#define bFM3_ETHERNET_MAC1_IER_TUE *((volatile unsigned int*)(0x42D00388UL)) -#define bFM3_ETHERNET_MAC1_IER_TJE *((volatile unsigned int*)(0x42D0038CUL)) -#define bFM3_ETHERNET_MAC1_IER_OVE *((volatile unsigned int*)(0x42D00390UL)) -#define bFM3_ETHERNET_MAC1_IER_UNE *((volatile unsigned int*)(0x42D00394UL)) -#define bFM3_ETHERNET_MAC1_IER_RIE *((volatile unsigned int*)(0x42D00398UL)) -#define bFM3_ETHERNET_MAC1_IER_RUE *((volatile unsigned int*)(0x42D0039CUL)) -#define bFM3_ETHERNET_MAC1_IER_RSE *((volatile unsigned int*)(0x42D003A0UL)) -#define bFM3_ETHERNET_MAC1_IER_RWE *((volatile unsigned int*)(0x42D003A4UL)) -#define bFM3_ETHERNET_MAC1_IER_ETE *((volatile unsigned int*)(0x42D003A8UL)) -#define bFM3_ETHERNET_MAC1_IER_FBE *((volatile unsigned int*)(0x42D003B4UL)) -#define bFM3_ETHERNET_MAC1_IER_ERE *((volatile unsigned int*)(0x42D003B8UL)) -#define bFM3_ETHERNET_MAC1_IER_AIE *((volatile unsigned int*)(0x42D003BCUL)) -#define bFM3_ETHERNET_MAC1_IER_NIE *((volatile unsigned int*)(0x42D003C0UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0 *((volatile unsigned int*)(0x42D00400UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1 *((volatile unsigned int*)(0x42D00404UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2 *((volatile unsigned int*)(0x42D00408UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3 *((volatile unsigned int*)(0x42D0040CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4 *((volatile unsigned int*)(0x42D00410UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5 *((volatile unsigned int*)(0x42D00414UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6 *((volatile unsigned int*)(0x42D00418UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7 *((volatile unsigned int*)(0x42D0041CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8 *((volatile unsigned int*)(0x42D00420UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9 *((volatile unsigned int*)(0x42D00424UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10 *((volatile unsigned int*)(0x42D00428UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11 *((volatile unsigned int*)(0x42D0042CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12 *((volatile unsigned int*)(0x42D00430UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13 *((volatile unsigned int*)(0x42D00434UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14 *((volatile unsigned int*)(0x42D00438UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15 *((volatile unsigned int*)(0x42D0043CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH *((volatile unsigned int*)(0x42D00440UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0 *((volatile unsigned int*)(0x42D00444UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1 *((volatile unsigned int*)(0x42D00448UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2 *((volatile unsigned int*)(0x42D0044CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3 *((volatile unsigned int*)(0x42D00450UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4 *((volatile unsigned int*)(0x42D00454UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5 *((volatile unsigned int*)(0x42D00458UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6 *((volatile unsigned int*)(0x42D0045CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7 *((volatile unsigned int*)(0x42D00460UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8 *((volatile unsigned int*)(0x42D00464UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9 *((volatile unsigned int*)(0x42D00468UL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10 *((volatile unsigned int*)(0x42D0046CUL)) -#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF *((volatile unsigned int*)(0x42D00470UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0 *((volatile unsigned int*)(0x42D00480UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1 *((volatile unsigned int*)(0x42D00484UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2 *((volatile unsigned int*)(0x42D00488UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3 *((volatile unsigned int*)(0x42D0048CUL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4 *((volatile unsigned int*)(0x42D00490UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5 *((volatile unsigned int*)(0x42D00494UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6 *((volatile unsigned int*)(0x42D00498UL)) -#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7 *((volatile unsigned int*)(0x42D0049CUL)) -#define bFM3_ETHERNET_MAC1_AHBSR_AHBS *((volatile unsigned int*)(0x42D00580UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0 *((volatile unsigned int*)(0x42D00900UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1 *((volatile unsigned int*)(0x42D00904UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2 *((volatile unsigned int*)(0x42D00908UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3 *((volatile unsigned int*)(0x42D0090CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4 *((volatile unsigned int*)(0x42D00910UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5 *((volatile unsigned int*)(0x42D00914UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6 *((volatile unsigned int*)(0x42D00918UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7 *((volatile unsigned int*)(0x42D0091CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8 *((volatile unsigned int*)(0x42D00920UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9 *((volatile unsigned int*)(0x42D00924UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10 *((volatile unsigned int*)(0x42D00928UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11 *((volatile unsigned int*)(0x42D0092CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12 *((volatile unsigned int*)(0x42D00930UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13 *((volatile unsigned int*)(0x42D00934UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14 *((volatile unsigned int*)(0x42D00938UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15 *((volatile unsigned int*)(0x42D0093CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16 *((volatile unsigned int*)(0x42D00940UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17 *((volatile unsigned int*)(0x42D00944UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18 *((volatile unsigned int*)(0x42D00948UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19 *((volatile unsigned int*)(0x42D0094CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20 *((volatile unsigned int*)(0x42D00950UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21 *((volatile unsigned int*)(0x42D00954UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22 *((volatile unsigned int*)(0x42D00958UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23 *((volatile unsigned int*)(0x42D0095CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24 *((volatile unsigned int*)(0x42D00960UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25 *((volatile unsigned int*)(0x42D00964UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26 *((volatile unsigned int*)(0x42D00968UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27 *((volatile unsigned int*)(0x42D0096CUL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28 *((volatile unsigned int*)(0x42D00970UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29 *((volatile unsigned int*)(0x42D00974UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30 *((volatile unsigned int*)(0x42D00978UL)) -#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31 *((volatile unsigned int*)(0x42D0097CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0 *((volatile unsigned int*)(0x42D00980UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1 *((volatile unsigned int*)(0x42D00984UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2 *((volatile unsigned int*)(0x42D00988UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3 *((volatile unsigned int*)(0x42D0098CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4 *((volatile unsigned int*)(0x42D00990UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5 *((volatile unsigned int*)(0x42D00994UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6 *((volatile unsigned int*)(0x42D00998UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7 *((volatile unsigned int*)(0x42D0099CUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8 *((volatile unsigned int*)(0x42D009A0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9 *((volatile unsigned int*)(0x42D009A4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10 *((volatile unsigned int*)(0x42D009A8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11 *((volatile unsigned int*)(0x42D009ACUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12 *((volatile unsigned int*)(0x42D009B0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13 *((volatile unsigned int*)(0x42D009B4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14 *((volatile unsigned int*)(0x42D009B8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15 *((volatile unsigned int*)(0x42D009BCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16 *((volatile unsigned int*)(0x42D009C0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17 *((volatile unsigned int*)(0x42D009C4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18 *((volatile unsigned int*)(0x42D009C8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19 *((volatile unsigned int*)(0x42D009CCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20 *((volatile unsigned int*)(0x42D009D0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21 *((volatile unsigned int*)(0x42D009D4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22 *((volatile unsigned int*)(0x42D009D8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23 *((volatile unsigned int*)(0x42D009DCUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24 *((volatile unsigned int*)(0x42D009E0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25 *((volatile unsigned int*)(0x42D009E4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26 *((volatile unsigned int*)(0x42D009E8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27 *((volatile unsigned int*)(0x42D009ECUL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28 *((volatile unsigned int*)(0x42D009F0UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29 *((volatile unsigned int*)(0x42D009F4UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30 *((volatile unsigned int*)(0x42D009F8UL)) -#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31 *((volatile unsigned int*)(0x42D009FCUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0 *((volatile unsigned int*)(0x42D00A00UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1 *((volatile unsigned int*)(0x42D00A04UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2 *((volatile unsigned int*)(0x42D00A08UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3 *((volatile unsigned int*)(0x42D00A0CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4 *((volatile unsigned int*)(0x42D00A10UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5 *((volatile unsigned int*)(0x42D00A14UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6 *((volatile unsigned int*)(0x42D00A18UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7 *((volatile unsigned int*)(0x42D00A1CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8 *((volatile unsigned int*)(0x42D00A20UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9 *((volatile unsigned int*)(0x42D00A24UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10 *((volatile unsigned int*)(0x42D00A28UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11 *((volatile unsigned int*)(0x42D00A2CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12 *((volatile unsigned int*)(0x42D00A30UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13 *((volatile unsigned int*)(0x42D00A34UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14 *((volatile unsigned int*)(0x42D00A38UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15 *((volatile unsigned int*)(0x42D00A3CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16 *((volatile unsigned int*)(0x42D00A40UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17 *((volatile unsigned int*)(0x42D00A44UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18 *((volatile unsigned int*)(0x42D00A48UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19 *((volatile unsigned int*)(0x42D00A4CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20 *((volatile unsigned int*)(0x42D00A50UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21 *((volatile unsigned int*)(0x42D00A54UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22 *((volatile unsigned int*)(0x42D00A58UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23 *((volatile unsigned int*)(0x42D00A5CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24 *((volatile unsigned int*)(0x42D00A60UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25 *((volatile unsigned int*)(0x42D00A64UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26 *((volatile unsigned int*)(0x42D00A68UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27 *((volatile unsigned int*)(0x42D00A6CUL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28 *((volatile unsigned int*)(0x42D00A70UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29 *((volatile unsigned int*)(0x42D00A74UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30 *((volatile unsigned int*)(0x42D00A78UL)) -#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31 *((volatile unsigned int*)(0x42D00A7CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0 *((volatile unsigned int*)(0x42D00A80UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1 *((volatile unsigned int*)(0x42D00A84UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2 *((volatile unsigned int*)(0x42D00A88UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3 *((volatile unsigned int*)(0x42D00A8CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4 *((volatile unsigned int*)(0x42D00A90UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5 *((volatile unsigned int*)(0x42D00A94UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6 *((volatile unsigned int*)(0x42D00A98UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7 *((volatile unsigned int*)(0x42D00A9CUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8 *((volatile unsigned int*)(0x42D00AA0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9 *((volatile unsigned int*)(0x42D00AA4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10 *((volatile unsigned int*)(0x42D00AA8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11 *((volatile unsigned int*)(0x42D00AACUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12 *((volatile unsigned int*)(0x42D00AB0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13 *((volatile unsigned int*)(0x42D00AB4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14 *((volatile unsigned int*)(0x42D00AB8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15 *((volatile unsigned int*)(0x42D00ABCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16 *((volatile unsigned int*)(0x42D00AC0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17 *((volatile unsigned int*)(0x42D00AC4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18 *((volatile unsigned int*)(0x42D00AC8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19 *((volatile unsigned int*)(0x42D00ACCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20 *((volatile unsigned int*)(0x42D00AD0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21 *((volatile unsigned int*)(0x42D00AD4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22 *((volatile unsigned int*)(0x42D00AD8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23 *((volatile unsigned int*)(0x42D00ADCUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24 *((volatile unsigned int*)(0x42D00AE0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25 *((volatile unsigned int*)(0x42D00AE4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26 *((volatile unsigned int*)(0x42D00AE8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27 *((volatile unsigned int*)(0x42D00AECUL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28 *((volatile unsigned int*)(0x42D00AF0UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29 *((volatile unsigned int*)(0x42D00AF4UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30 *((volatile unsigned int*)(0x42D00AF8UL)) -#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31 *((volatile unsigned int*)(0x42D00AFCUL)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9B610T_H_ */ - diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S deleted file mode 100644 index 85d59276e2..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S +++ /dev/null @@ -1,333 +0,0 @@ -;/************************************************************************/ -;/* (C) Fujitsu Semiconductor Europe GmbH */ -;/* */ -;/* The following software deliverable is intended for and must only be */ -;/* used for reference and in an evaluation laboratory environment. */ -;/* It is provided on an as-is basis without charge and is subject to */ -;/* alterations. */ -;/* It is the user’s obligation to fully test the software in its */ -;/* environment and to ensure proper functionality, qualification and */ -;/* compliance with component specifications. */ -;/* */ -;/* In the event the software deliverable includes the use of open */ -;/* source components, the provisions of the governing open source */ -;/* license agreement shall apply with respect to such software */ -;/* deliverable. */ -;/* FSEU does not warrant that the deliverables do not infringe any */ -;/* third party intellectual property right (IPR). In the event that */ -;/* the deliverables infringe a third party IPR it is the sole */ -;/* responsibility of the customer to obtain necessary licenses to */ -;/* continue the usage of the deliverable. */ -;/* */ -;/* To the maximum extent permitted by applicable law FSEU disclaims all */ -;/* warranties, whether express or implied, in particular, but not */ -;/* limited to, warranties of merchantability and fitness for a */ -;/* particular purpose for which the deliverable is not designated. */ -;/* */ -;/* To the maximum extent permitted by applicable law, FSEU's liability */ -;/* is restricted to intention and gross negligence. */ -;/* FSEU is not liable for consequential damages. */ -;/* */ -;/* (V1.4) */ -;/************************************************************************/ -;/* Startup for ARM */ -;/* Version V1.02 */ -;/* Date 2011-07-25 */ -;/* Target-mcu MB9B61x */ -;/************************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0 - DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1 - DCD USB0F_Handler ; 34: USB0 Function - DCD USB0_Handler ; 35: USB0 Function / USB0 HOST - DCD USB1F_Handler ; 36: USB1 Function - DCD USB1_Handler ; 37: USB1 Function / USB1 HOST - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15 - DCD DummyHandler ; 47: Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT CSV_Handler [WEAK] - EXPORT SWDT_Handler [WEAK] - EXPORT LVD_Handler [WEAK] - EXPORT MFT_WG_IRQHandler [WEAK] - EXPORT INT0_7_Handler [WEAK] - EXPORT INT8_31_Handler [WEAK] - EXPORT DT_Handler [WEAK] - EXPORT MFS0RX_IRQHandler [WEAK] - EXPORT MFS0TX_IRQHandler [WEAK] - EXPORT MFS1RX_IRQHandler [WEAK] - EXPORT MFS1TX_IRQHandler [WEAK] - EXPORT MFS2RX_IRQHandler [WEAK] - EXPORT MFS2TX_IRQHandler [WEAK] - EXPORT MFS3RX_IRQHandler [WEAK] - EXPORT MFS3TX_IRQHandler [WEAK] - EXPORT MFS4RX_IRQHandler [WEAK] - EXPORT MFS4TX_IRQHandler [WEAK] - EXPORT MFS5RX_IRQHandler [WEAK] - EXPORT MFS5TX_IRQHandler [WEAK] - EXPORT MFS6RX_IRQHandler [WEAK] - EXPORT MFS6TX_IRQHandler [WEAK] - EXPORT MFS7RX_IRQHandler [WEAK] - EXPORT MFS7TX_IRQHandler [WEAK] - EXPORT PPG_Handler [WEAK] - EXPORT TIM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT MFT_FRT_IRQHandler [WEAK] - EXPORT MFT_IPC_IRQHandler [WEAK] - EXPORT MFT_OPC_IRQHandler [WEAK] - EXPORT BT0_7_IRQHandler [WEAK] - EXPORT ETHER_MAC0_IRQHandler [WEAK] - EXPORT ETHER_MAC1_IRQHandler [WEAK] - EXPORT USB0F_Handler [WEAK] - EXPORT USB0_Handler [WEAK] - EXPORT USB1F_Handler [WEAK] - EXPORT USB1_Handler [WEAK] - EXPORT DMAC0_Handler [WEAK] - EXPORT DMAC1_Handler [WEAK] - EXPORT DMAC2_Handler [WEAK] - EXPORT DMAC3_Handler [WEAK] - EXPORT DMAC4_Handler [WEAK] - EXPORT DMAC5_Handler [WEAK] - EXPORT DMAC6_Handler [WEAK] - EXPORT DMAC7_Handler [WEAK] - EXPORT BT8_15_IRQHandler [WEAK] - EXPORT DummyHandler [WEAK] - -CSV_Handler -SWDT_Handler -LVD_Handler -MFT_WG_IRQHandler -INT0_7_Handler -INT8_31_Handler -DT_Handler -MFS0RX_IRQHandler -MFS0TX_IRQHandler -MFS1RX_IRQHandler -MFS1TX_IRQHandler -MFS2RX_IRQHandler -MFS2TX_IRQHandler -MFS3RX_IRQHandler -MFS3TX_IRQHandler -MFS4RX_IRQHandler -MFS4TX_IRQHandler -MFS5RX_IRQHandler -MFS5TX_IRQHandler -MFS6RX_IRQHandler -MFS6TX_IRQHandler -MFS7RX_IRQHandler -MFS7TX_IRQHandler -PPG_Handler -TIM_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -MFT_FRT_IRQHandler -MFT_IPC_IRQHandler -MFT_OPC_IRQHandler -BT0_7_IRQHandler -DMAC0_Handler -DMAC1_Handler -DMAC2_Handler -DMAC3_Handler -DMAC4_Handler -DMAC5_Handler -DMAC6_Handler -DMAC7_Handler -ETHER_MAC0_IRQHandler -ETHER_MAC1_IRQHandler -USB0F_Handler -USB0_Handler -USB1F_Handler -USB1_Handler -BT8_15_IRQHandler -DummyHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c deleted file mode 100644 index ef641de1ef..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - **************************************************************************** -** -** File : startup_mb9bf61x.c -** -** Abstract : This file contains interrupt vector and startup code. -** -** Functions : Reset_Handler -** -** Target : Fujitsu FM3 microcontrollers -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the Atollic TrueSTUDIO(R) toolchain. -** - **************************************************************************** -*/ - -/** -**=========================================================================== -** Revisions -**=========================================================================== -** Date Modification -** 2011-08-18 First issue. -**=========================================================================== -*/ - -/** -**=========================================================================== -** External declarations -**=========================================================================== -*/ -extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector; -extern unsigned long _estack; -extern void __libc_init_array(); -extern void SystemInit(); -extern void main(); - -/** -**=========================================================================== -** Default interrupt handler -**=========================================================================== -*/ -void Default_Handler() -{ - /* Hang here */ - while(1) - { - } -} - -/** -**=========================================================================== -** Reset handler -**=========================================================================== -*/ -__attribute__((naked)) void Reset_Handler() -{ - /* Data and BSS variables */ - unsigned long *srcdata, *dstdata, *sbss; - - /* Set up the stack pointer */ - asm("ldr sp,=_estack\n\t"); - - /* Set up vector table offset register */ - dstdata = (unsigned long *)0xe000ed08; - *dstdata = (unsigned long)&_isr_vector; - - srcdata = &_sidata; - dstdata = &_sdata; - sbss = &_sbss; - - /* Copy data */ - while(dstdata != &_edata) - { - *(dstdata++) = *(srcdata++); - } - - /* Clear BSS */ - while(sbss != &_ebss) - { - *(sbss++) = '\0'; - } - - /* Run static constructors */ - //__libc_init_array(); - - /* Call the clock system initialization function.*/ - SystemInit(); - - /* Jump to main */ - main(); - - /* In case main returns, use default handler */ - Default_Handler(); -} - -/** -**=========================================================================== -** Weak definitions of handlers point to Default_Handler if not implemented -**=========================================================================== -*/ -void NMI_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler"))); - -void CSV_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void LVD_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DT_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void PPG_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); -void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void USB0_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void USB1_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler"))); -void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler"))); - - -/** -**=========================================================================== -** Interrupt Vector Table -**=========================================================================== -*/ -void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = { - /* Processor exceptions */ - (void (*)(void))&_estack, /* 0 - Stack pointer */ - Reset_Handler, /* 1 - Reset */ - NMI_Handler, /* 2 - NMI */ - HardFault_Handler, /* 3 - Hard fault */ - MemManage_Handler, /* 4 - Memory management fault */ - BusFault_Handler, /* 5 - Bus fault */ - UsageFault_Handler, /* 6 - Usage fault */ - 0, /* 7 - Reserved */ - 0, /* 8 - Reserved */ - 0, /* 9 - Reserved */ - 0, /* 10 - Reserved */ - SVC_Handler, /* 11 - SVCall */ - DebugMonitor_Handler, /* 12 - Reserved for Debug */ - 0, /* 13 - Reserved */ - PendSV_Handler, /* 14 - PendSV */ - SysTick_Handler, /* 15 - Systick */ - - /* External Interrupts */ - CSV_Handler, /* 0: Clock Super Visor */ - SWDT_Handler, /* 1: Software Watchdog Timer */ - LVD_Handler, /* 2: Low Voltage Detector */ - MFT_WG_IRQHandler, /* 3: Wave Form Generator / DTIF */ - INT0_7_Handler, /* 4: External Interrupt Request ch.0 to ch.7 */ - INT8_31_Handler, /* 5: External Interrupt Request ch.8 to ch.31 */ - DT_Handler, /* 6: Dual Timer / Quad Decoder */ - MFS0RX_IRQHandler, /* 7: MultiFunction Serial ch.0 */ - MFS0TX_IRQHandler, /* 8: MultiFunction Serial ch.0 */ - MFS1RX_IRQHandler, /* 9: MultiFunction Serial ch.1 */ - MFS1TX_IRQHandler, /* 10: MultiFunction Serial ch.1 */ - MFS2RX_IRQHandler, /* 11: MultiFunction Serial ch.2 */ - MFS2TX_IRQHandler, /* 12: MultiFunction Serial ch.2 */ - MFS3RX_IRQHandler, /* 13: MultiFunction Serial ch.3 */ - MFS3TX_IRQHandler, /* 14: MultiFunction Serial ch.3 */ - MFS4RX_IRQHandler, /* 15: MultiFunction Serial ch.4 */ - MFS4TX_IRQHandler, /* 16: MultiFunction Serial ch.4 */ - MFS5RX_IRQHandler, /* 17: MultiFunction Serial ch.5 */ - MFS5TX_IRQHandler, /* 18: MultiFunction Serial ch.5 */ - MFS6RX_IRQHandler, /* 19: MultiFunction Serial ch.6 */ - MFS6TX_IRQHandler, /* 20: MultiFunction Serial ch.6 */ - MFS7RX_IRQHandler, /* 21: MultiFunction Serial ch.7 */ - MFS7TX_IRQHandler, /* 22: MultiFunction Serial ch.7 */ - PPG_Handler, /* 23: PPG */ - TIM_IRQHandler, /* 24: OSC / PLL / Watch Counter */ - ADC0_IRQHandler, /* 25: ADC0 */ - ADC1_IRQHandler, /* 26: ADC1 */ - ADC2_IRQHandler, /* 27: ADC2 */ - MFT_FRT_IRQHandler, /* 28: Free-run Timer */ - MFT_IPC_IRQHandler, /* 29: Input Capture */ - MFT_OPC_IRQHandler, /* 30: Output Compare */ - BT0_7_IRQHandler, /* 31: Base Timer ch.0 to ch.7 */ - ETHER_MAC0_IRQHandler, /* 32: Ethernet MAC ch.0 */ - ETHER_MAC1_IRQHandler, /* 33: Ethernet MAC ch.1 */ - USB0F_Handler, /* 34: USB0 Function */ - USB0_Handler, /* 35: USB0 Function / USB0 HOST */ - USB1F_Handler, /* 36: USB1 Function */ - USB1_Handler, /* 37: USB1 Function / USB1 HOST */ - DMAC0_Handler, /* 38: DMAC ch.0 */ - DMAC1_Handler, /* 39: DMAC ch.1 */ - DMAC2_Handler, /* 40: DMAC ch.2 */ - DMAC3_Handler, /* 41: DMAC ch.3 */ - DMAC4_Handler, /* 42: DMAC ch.4 */ - DMAC5_Handler, /* 43: DMAC ch.5 */ - DMAC6_Handler, /* 44: DMAC ch.6 */ - DMAC7_Handler, /* 45: DMAC ch.7 */ - BT8_15_IRQHandler, /* 46: Base Timer ch.8 to ch.15 */ - Default_Handler /* 47: Reserved */ -}; diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S deleted file mode 100644 index 7bc1acf0cd..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S +++ /dev/null @@ -1,417 +0,0 @@ -;/************************************************************************/ -;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -;/* */ -;/* The following software deliverable is intended for and must only be */ -;/* used for reference and in an evaluation laboratory environment. */ -;/* It is provided on an as-is basis without charge and is subject to */ -;/* alterations. */ -;/* It is the user's obligation to fully test the software in its */ -;/* environment and to ensure proper functionality, qualification and */ -;/* compliance with component specifications. */ -;/* */ -;/* In the event the software deliverable includes the use of open */ -;/* source components, the provisions of the governing open source */ -;/* license agreement shall apply with respect to such software */ -;/* deliverable. */ -;/* FSEU does not warrant that the deliverables do not infringe any */ -;/* third party intellectual property right (IPR). In the event that */ -;/* the deliverables infringe a third party IPR it is the sole */ -;/* responsibility of the customer to obtain necessary licenses to */ -;/* continue the usage of the deliverable. */ -;/* */ -;/* To the maximum extent permitted by applicable law FSEU disclaims all */ -;/* warranties, whether express or implied, in particular, but not */ -;/* limited to, warranties of merchantability and fitness for a */ -;/* particular purpose for which the deliverable is not designated. */ -;/* */ -;/* To the maximum extent permitted by applicable law, FSEU's liability */ -;/* is restricted to intentional misconduct and gross negligence. */ -;/* FSEU is not liable for consequential damages. */ -;/* */ -;/* (V1.5) */ -;/************************************************************************/ -;/* Startup for IAR */ -;/* Version V1.00 */ -;/* Date 2011-07-25 */ -;/* Target-mcu MB9B610 */ -;/************************************************************************/ - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset - DCD NMI_Handler ; NMI - DCD HardFault_Handler ; Hard Fault - DCD MemManage_Handler ; MPU Fault - DCD BusFault_Handler ; Bus Fault - DCD UsageFault_Handler ; Usage Fault - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall - DCD DebugMon_Handler ; Debug Monitor - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV - DCD SysTick_Handler ; SysTick - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_31_Handler ; 5: External Interrupt Request ch.8 to ch.31 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT0_7_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD ETHER_MAC0_IRQHandler ; 32: Ethernet MAC ch.0 - DCD ETHER_MAC1_IRQHandler ; 33: Ethernet MAC ch.1 - DCD USB0F_Handler ; 34: USB0 Function - DCD USB0_Handler ; 35: USB0 Function / USB0 HOST - DCD USB1F_Handler ; 36: USB1 Function - DCD USB1_Handler ; 37: USB1 Function / USB1 HOST - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD BT8_15_IRQHandler ; 46: Base Timer ch.8 to ch.15 - DCD DummyHandler ; 47: Reserved - - THUMB -; Dummy Exception Handlers (infinite loops which can be modified) - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - - - PUBWEAK CSV_Handler - SECTION .text:CODE:REORDER(1) -CSV_Handler - B CSV_Handler - - PUBWEAK SWDT_Handler - SECTION .text:CODE:REORDER(1) -SWDT_Handler - B SWDT_Handler - - PUBWEAK LVD_Handler - SECTION .text:CODE:REORDER(1) -LVD_Handler - B LVD_Handler - - PUBWEAK MFT_WG_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_WG_IRQHandler - B MFT_WG_IRQHandler - - PUBWEAK INT0_7_Handler - SECTION .text:CODE:REORDER(1) -INT0_7_Handler - B INT0_7_Handler - - PUBWEAK INT8_31_Handler - SECTION .text:CODE:REORDER(1) -INT8_31_Handler - B INT8_31_Handler - - PUBWEAK DT_Handler - SECTION .text:CODE:REORDER(1) -DT_Handler - B DT_Handler - - PUBWEAK MFS0RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0RX_IRQHandler - B MFS0RX_IRQHandler - - PUBWEAK MFS0TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0TX_IRQHandler - B MFS0TX_IRQHandler - - PUBWEAK MFS1RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1RX_IRQHandler - B MFS1RX_IRQHandler - - PUBWEAK MFS1TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1TX_IRQHandler - B MFS1TX_IRQHandler - - PUBWEAK MFS2RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2RX_IRQHandler - B MFS2RX_IRQHandler - - PUBWEAK MFS2TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2TX_IRQHandler - B MFS2TX_IRQHandler - - PUBWEAK MFS3RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3RX_IRQHandler - B MFS3RX_IRQHandler - - PUBWEAK MFS3TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3TX_IRQHandler - B MFS3TX_IRQHandler - - PUBWEAK MFS4RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4RX_IRQHandler - B MFS4RX_IRQHandler - - PUBWEAK MFS4TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4TX_IRQHandler - B MFS4TX_IRQHandler - - PUBWEAK MFS5RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5RX_IRQHandler - B MFS5RX_IRQHandler - - PUBWEAK MFS5TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5TX_IRQHandler - B MFS5TX_IRQHandler - - PUBWEAK MFS6RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6RX_IRQHandler - B MFS6RX_IRQHandler - - PUBWEAK MFS6TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6TX_IRQHandler - B MFS6TX_IRQHandler - - PUBWEAK MFS7RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7RX_IRQHandler - B MFS7RX_IRQHandler - - PUBWEAK MFS7TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7TX_IRQHandler - B MFS7TX_IRQHandler - - PUBWEAK PPG_Handler - SECTION .text:CODE:REORDER(1) -PPG_Handler - B PPG_Handler - - PUBWEAK TIM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM_IRQHandler - B TIM_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK MFT_FRT_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_FRT_IRQHandler - B MFT_FRT_IRQHandler - - PUBWEAK MFT_IPC_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_IPC_IRQHandler - B MFT_IPC_IRQHandler - - PUBWEAK MFT_OPC_IRQHandler - SECTION .text:CODE:REORDER(1) -MFT_OPC_IRQHandler - B MFT_OPC_IRQHandler - - PUBWEAK BT0_7_IRQHandler - SECTION .text:CODE:REORDER(1) -BT0_7_IRQHandler - B BT0_7_IRQHandler - - PUBWEAK ETHER_MAC0_IRQHandler - SECTION .text:CODE:REORDER(1) -ETHER_MAC0_IRQHandler - B ETHER_MAC0_IRQHandler - - PUBWEAK ETHER_MAC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ETHER_MAC1_IRQHandler - B ETHER_MAC1_IRQHandler - - PUBWEAK USB0F_Handler - SECTION .text:CODE:REORDER(1) -USB0F_Handler - B USB0F_Handler - - PUBWEAK USB0_Handler - SECTION .text:CODE:REORDER(1) -USB0_Handler - B USB0_Handler - - PUBWEAK USB1F_Handler - SECTION .text:CODE:REORDER(1) -USB1F_Handler - B USB1F_Handler - - PUBWEAK USB1_Handler - SECTION .text:CODE:REORDER(1) -USB1_Handler - B USB1_Handler - - PUBWEAK DMAC0_Handler - SECTION .text:CODE:REORDER(1) -DMAC0_Handler - B DMAC0_Handler - - - PUBWEAK DMAC1_Handler - SECTION .text:CODE:REORDER(1) -DMAC1_Handler - B DMAC1_Handler - - PUBWEAK DMAC2_Handler - SECTION .text:CODE:REORDER(1) -DMAC2_Handler - B DMAC2_Handler - - PUBWEAK DMAC3_Handler - SECTION .text:CODE:REORDER(1) -DMAC3_Handler - B DMAC3_Handler - - PUBWEAK DMAC4_Handler - SECTION .text:CODE:REORDER(1) -DMAC4_Handler - B DMAC4_Handler - - PUBWEAK DMAC5_Handler - SECTION .text:CODE:REORDER(1) -DMAC5_Handler - B DMAC5_Handler - - PUBWEAK DMAC6_Handler - SECTION .text:CODE:REORDER(1) -DMAC6_Handler - B DMAC6_Handler - - PUBWEAK DMAC7_Handler - SECTION .text:CODE:REORDER(1) -DMAC7_Handler - B DMAC7_Handler - - PUBWEAK BT8_15_IRQHandler - SECTION .text:CODE:REORDER(1) -BT8_15_IRQHandler - B BT8_15_IRQHandler - - PUBWEAK DummyHandler - SECTION .text:CODE:REORDER(1) -DummyHandler - B DummyHandler - - END diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c deleted file mode 100644 index a039f02431..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c +++ /dev/null @@ -1,206 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ - -#include "board.h" - -/** \file system_mb9bf61x.c - ** - ** FM3 system initialization functions - ** All adjustments can be done in belonging header file. - ** - ** History: - ** 2011-07-07 V1.0 MWi original version - ******************************************************************************/ - -/** - ****************************************************************************** - ** System Clock Frequency (Core Clock) Variable according CMSIS - ******************************************************************************/ -uint32_t SystemCoreClock = __HCLK; - -/** - ****************************************************************************** - ** \brief Update the System Core Clock with current core Clock retrieved from - ** cpu registers. - ** \param none - ** \return none - ******************************************************************************/ -void SystemCoreClockUpdate (void) { - uint32_t masterClk; - uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance - - switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) { - case 0: /* internal High-speed Cr osc. */ - masterClk = __CLKHC; - break; - - case 1: /* external main osc. */ - masterClk = __CLKMO; - break; - - case 2: /* PLL clock */ - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violation: - // "Unordered accesses to a volatile location" - u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1)); - masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1)); - break; - - case 4: /* internal Low-speed CR osc. */ - masterClk = __CLKLC; - break; - - case 5: /* external Sub osc. */ - masterClk = __CLKSO; - break; - - default: - masterClk = 0Ul; - break; - } - - switch (FM3_CRG->BSC_PSR & 0x07) { - case 0: - SystemCoreClock = masterClk; - break; - - case 1: - SystemCoreClock = masterClk / 2; - break; - - case 2: - SystemCoreClock = masterClk / 3; - break; - - case 3: - SystemCoreClock = masterClk / 4; - break; - - case 4: - SystemCoreClock = masterClk / 6; - break; - - case 5: - SystemCoreClock = masterClk /8; - break; - - case 6: - SystemCoreClock = masterClk /16; - break; - - default: - SystemCoreClock = 0Ul; - break; - } - -} - -/** - ****************************************************************************** - ** \brief Setup the microcontroller system. Initialize the System and update - ** the SystemCoreClock variable. - ** - ** \param none - ** \return none - ******************************************************************************/ -void SystemInit (void) { - - static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance - -#if (HWWD_DISABLE) /* HW Watchdog Disable */ - FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */ - FM3_HWWDT->WDG_LCK = 0xE5331AAE; - FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */ -#endif - -#if (CLOCK_SETUP) /* Clock Setup */ - FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */ - FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */ - FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */ - FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */ - FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */ - FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */ - - FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */ - - if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */ - while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */ - } - - if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ - while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ - } - - FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */ - FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */ - FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */ - - if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */ - FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */ - while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */ - } - - FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */ - - { - volatile unsigned int i; - for(i=0;i<200000;i++); - } - // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) - // violations: - // "Unordered reads and writes to or from same location" and - // "Unordered accesses to a volatile location" - do - { - u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0); - }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead); -#endif // (CLOCK_SETUP) - -#if (CR_TRIM_SETUP) - /* CR Trimming Data */ - if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) ) - { - /* UnLock (MCR_FTRM) */ - FM3_CRTRIM->MCR_RLR = 0x1ACCE554; - /* Set MCR_FTRM */ - FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM; - /* Lock (MCR_FTRM) */ - FM3_CRTRIM->MCR_RLR = 0x00000000; - } -#endif // (CR_TRIM_SETUP) -} - - - diff --git a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h b/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h deleted file mode 100644 index 819f3646e9..0000000000 --- a/bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h +++ /dev/null @@ -1,678 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/** \file system_mb9bf61x.h - ** - ** Headerfile for FM3 system parameters - ** - ** User clock definitions can be done for the following clock settings: - ** - CLOCK_SETUP : Execute the clock settings form the settings below in - ** SystemInit() - ** - __CLKMO : External clock frequency for main oscillion - ** - __CLKSO : External clock frequency for sub oscillion - ** - SCM_CTL : System Clock Mode Control Register - ** - BSC_PSR : Base Clock Prescaler Register - ** - APBC0_PSR : APB0 Prescaler Register - ** - APBC1_PSR : APB1 Prescaler Register - ** - APBC2_PSR : APB2 Prescaler Register - ** - SWC_PSR : Software Watchdog Clock Prescaler Register - ** - TTC_PSR : Trace Clock Prescaler Register - ** - CSW_TMR : Clock Stabilization Wait Time Register - ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register - ** - PLL_CTL1 : PLL Control Register 1 - ** - PLL_CTL2 : PLL Control Register 2 - ** - ** The register settings are check for correct values of reserved bits. - ** Otherwise a preprocessor error is output and stops the build process. - ** Furthermore the 'master clock' is retrieved from the register settings - ** and the system clock (HCLK) is calculated from the Base Clock Prescaler - ** Register (BSC_PSR). This value is used for the global CMSIS variable - ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is - ** is checked. Note that not all possible wrong setting are checked! The - ** user has to take care to fulfill the settings stated in the according - ** device's data sheet! - ** - ** User definition for Hardware Watchdog: - ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit() - ** - ** User definition for CR Trimming: - ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit() - ** - ** History: - ** 2011-05-16 V1.0 MWi original version - *****************************************************************************/ - -#ifndef _SYSTEM_MB9BF61X_H_ -#define _SYSTEM_MB9BF61X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************/ -/* Include files */ -/******************************************************************************/ - -#include - -/******************************************************************************/ -/* Global pre-processor symbols/macros ('define') */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* START OF USER SETTINGS HERE */ -/* =========================== */ -/* */ -/* All lines with '<<<' can be set by user. */ -/* */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Clock Setup Enable - ** (USER SETTING) - ** - ** - 0 = No clock setup done by system_mb9xfxxx.c - ** - 1 = Clock setup done by system_mb9xfxxx.c - ******************************************************************************/ -#define CLOCK_SETUP 1 // <<< Define clock setup here - -/** - ****************************************************************************** - ** \brief External Main Clock Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal - -/** - ****************************************************************************** - ** \brief External Sub Clock Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal - -/** - ****************************************************************************** - ** \brief System Clock Mode Control Register value definition - ** (USER SETTING) - ** - ** SCM_CTL - ** - ** Bit#7-5 : RCS[2:0] - ** - 0 = Internal high-speed CR oscillation (default) - ** - 1 = Main oscillation clock - ** - 2 = PLL oscillation clock - ** - 3 = (not allowed) - ** - 4 = Internal low-speed CR oscillation - ** - 5 = Sub clock oscillation - ** - 6 = (not allowed) - ** - 7 = (not allowed) - ** - ** Bit#4 : PLLE - ** - 0 = Disable PLL (default) - ** - 1 = Enable PLL - ** - ** Bit#3 : SOSCE - ** - 0 = Disable sub oscillation (default) - ** - 1 = Enable sub oscillation - ** - ** Bit#2 : (reserved) - ** - ** Bit#1 : MOSCE - ** - 0 = Disable main oscillation (default) - ** - 1 = Enable main oscillation - ** - ** Bit#0 : (reserved) - ******************************************************************************/ -#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here - -/** - ****************************************************************************** - ** \brief Base Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** BSC_PSR - ** - ** Bit#7-3 : (reserved) - ** - ** Bit#2-0 : BSR[2:0] - ** - 0 = HCLK = Master Clock - ** - 1 = HCLK = Master Clock / 2 - ** - 2 = HCLK = Master Clock / 3 - ** - 3 = HCLK = Master Clock / 4 - ** - 4 = HCLK = Master Clock / 6 - ** - 5 = HCLK = Master Clock / 8 - ** - 6 = HCLK = Master Clock / 16 - ** - 7 = (reserved) - ******************************************************************************/ -#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here - -/** - ****************************************************************************** - ** \brief APB0 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC0_PSR - ** - ** Bit#7-2 : (reserved) - ** - ** Bit#1-0 : BSR[2:0] - ** - 0 = PCLK0 = HCLK - ** - 1 = PCLK0 = HCLK / 2 - ** - 2 = PCLK0 = HCLK / 4 - ** - 3 = PCLK0 = HCLK / 8 - ******************************************************************************/ -#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here - -/** - ****************************************************************************** - ** \brief APB1 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC1_PSR - ** - ** Bit#7 : APBC1EN - ** - 0 = Disable PCLK1 output - ** - 1 = Enables PCLK1 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC1RST - ** - 0 = APB1 bus reset, inactive (default) - ** - 1 = APB1 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC1[2:0] - ** - 0 = PCLK1 = HCLK - ** - 1 = PCLK1 = HCLK / 2 - ** - 2 = PCLK1 = HCLK / 4 - ** - 3 = PCLK1 = HCLK / 8 - ******************************************************************************/ -#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here - -/** - ****************************************************************************** - ** \brief APB2 Prescaler Register value definition - ** (USER SETTING) - ** - ** APBC2_PSR - ** - ** Bit#7 : APBC2EN - ** - 0 = Disable PCLK2 output - ** - 1 = Enables PCLK2 (default) - ** - ** Bit#6-5 : (reserved) - ** - ** Bit#4 : APBC2RST - ** - 0 = APB2 bus reset, inactive (default) - ** - 1 = APB2 bus reset, active - ** - ** Bit#3-2 : (reserved) - ** - ** Bit#1-0 : APBC2[1:0] - ** - 0 = PCLK2 = HCLK - ** - 1 = PCLK2 = HCLK / 2 - ** - 2 = PCLK2 = HCLK / 4 - ** - 3 = PCLK2 = HCLK / 8 - ******************************************************************************/ -#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here - -/** - ****************************************************************************** - ** \brief Software Watchdog Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** SWC_PSR - ** - ** Bit#7 : TESTB - ** - 0 = (not allowed) - ** - 1 = (always write "1" to this bit) - ** - ** Bit#6-2 : (reserved) - ** - ** Bit#1-0 : SWDS[2:0] - ** - 0 = SWDGOGCLK = PCLK0 - ** - 1 = SWDGOGCLK = PCLK0 / 2 - ** - 2 = SWDGOGCLK = PCLK0 / 4 - ** - 3 = SWDGOGCLK = PCLK0 / 8 - ******************************************************************************/ -#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here - -/** - ****************************************************************************** - ** \brief Trace Clock Prescaler Register value definition - ** (USER SETTING) - ** - ** TTC_PSR - ** - ** Bit#7-1 : (reserved) - ** - ** Bit#0 : TTC - ** - 0 = TPIUCLK = HCLK - ** - 1 = TPIUCLK = HCLK / 2 - ******************************************************************************/ -#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here - -/** - ****************************************************************************** - ** \brief Clock Stabilization Wait Time Register value definition - ** (USER SETTING) - ** - ** CSW_TMR - ** - ** Bit#7 : (reserved) - ** - ** Bit#6-4 : SOWT[2:0] - ** - 0 = ~10.3 ms (default) - ** - 1 = ~20.5 ms - ** - 2 = ~41 ms - ** - 3 = ~82 ms - ** - 4 = ~164 ms - ** - 5 = ~327 ms - ** - 6 = ~655 ms - ** - 7 = ~1.31 s - ** - ** Bit#3-0 : MOWT[3:0] - ** - 0 = ~500 ns (default) - ** - 1 = ~8 us - ** - 2 = ~16 us - ** - 3 = ~32 us - ** - 4 = ~64 us - ** - 5 = ~128 us - ** - 6 = ~256 us - ** - 7 = ~512 us - ** - 8 = ~1.0 ms - ** - 9 = ~2.0 ms - ** - 10 = ~4.0 ms - ** - 11 = ~8.0 ms - ** - 12 = ~33.0 ms - ** - 13 = ~131 ms - ** - 14 = ~524 ms - ** - 15 = ~2.0 s - ******************************************************************************/ -#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Clock Stabilization Wait Time Setup Register value definition - ** (USER SETTING) - ** - ** PSW_TMR - ** - ** Bit#7-5 : (reserved) - ** - ** Bit#4 : PINC - ** - 0 = Selects CLKMO (main oscillation) (default) - ** - 1 = (setting diabled) - ** - ** Bit#3 : (reserved) - ** - ** Bit#2-0 : POWT[2:0] - ** - 0 = ~128 us (default) - ** - 1 = ~256 us - ** - 2 = ~512 us - ** - 3 = ~1.02 ms - ** - 4 = ~2.05 ms - ** - 5 = ~4.10 ms - ** - 6 = ~8.20 ms - ** - 7 = ~16.40 ms - ******************************************************************************/ -#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here - -/** - ****************************************************************************** - ** \brief PLL Control Register 1 value definition - ** (USER SETTING) - ** - ** PLL_CTL1 - ** - ** Bit#7-4 : PLLK[3:0] - ** - 0 = Division(PLLK) = 1/1 (default) - ** - 1 = Division(PLLK) = 1/2 - ** - 2 = Division(PLLK) = 1/3 - ** - . . . - ** - 15 = Division(PLLK) = 1/16 - ** - ** Bit#3-0 : PLLM[3:0] - ** - 0 = Division(PLLM) = 1/1 (default) - ** - 1 = Division(PLLM) = 1/2 - ** - 2 = Division(PLLM) = 1/3 - ** - . . . - ** - 15 = Division(PLLM) = 1/16 - ******************************************************************************/ -#define PLL_CTL1_Val 0x00000001 // <<< Define PLL_CTL1 here - -/** - ****************************************************************************** - ** \brief PLL Control Register 2 value definition - ** (USER SETTING) - ** - ** PLL_CTL2 - ** - ** Bit#7-6 : (reserved) - ** - ** Bit#5-0 : PLLN[5:0] - ** - 0 = Division(PLLN) = 1/1 (default) - ** - 1 = Division(PLLN) = 1/2 - ** - 2 = Division(PLLN) = 1/3 - ** - . . . - ** - 63 = Division(PLLN) = 1/64 - ******************************************************************************/ -#define PLL_CTL2_Val 0x00000023 // <<< Define PLL_CTL2 here - -/** - ****************************************************************************** - ** \brief Hardware Watchdog disable definition - ** (USER SETTING) - ** - ** - 0 = Hardware Watchdog enable - ** - 1 = Hardware Watchdog disable - ******************************************************************************/ -#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here - -/** - ****************************************************************************** - ** \brief Trimming CR - ** (USER SETTING) - ** - ** - 0 = CR is not trimmed at startup - ** - 1 = CR is trimmed at startup - ******************************************************************************/ -#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here - - -/******************************************************************************/ -/* */ -/* END OF USER SETTINGS HERE */ -/* ========================= */ -/* */ -/******************************************************************************/ - -/******************************************************************************/ -/* Device dependent System Clock absolute maximum ranges */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL) - ** (USER SETTING) - ******************************************************************************/ -#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */ - -/** - ****************************************************************************** - ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMIN ( 4000000UL) - -/** - ****************************************************************************** - ** \brief Maximum Main Clock frequency using external clock - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKMOMAX ( 50000000UL) - -/** - ****************************************************************************** - ** \brief Any case minimum Sub Clock frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMIN ( 32000UL) - -/** - ****************************************************************************** - ** \brief Maximum Sub Clock frequency using external clock - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __CLKSOMAX ( 100000UL) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL input frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMIN ( 4000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL input frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKINMAX ( 16000000UL) - -/** - ****************************************************************************** - ** \brief Absolute minimum PLL oscillation frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMIN (200000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum PLL oscillation frequency - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __PLLCLKMAX (300000000UL) - -/** - ****************************************************************************** - ** \brief Absolute maximum System Clock frequency (HCLK) - ** (DEVICE DEPENDENT SETTING) - ******************************************************************************/ -#define __HCLKMAX (144000000UL) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking range (clock settings) - ******************************************************************************/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) - -/** - ****************************************************************************** - ** \brief Preprocessor macro for checking bits with mask (clock settings) - ******************************************************************************/ -#define CHECK_RSVD(val, mask) (val & mask) - - -/******************************************************************************/ -/* Check register settings */ -/******************************************************************************/ -#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA)) - #error "SCM_CTL: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10) - #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" -#endif - -#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F)) - #error "CSW_TMR: Invalid values of reserved bits!" -#endif - -#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */ - #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007)) - #error "PSW_TMR: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF)) - #error "PLL_CTL1: Invalid values of reserved bits!" - #endif - - #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F)) - #error "PLL_CTL2: Invalid values of reserved bits!" - #endif -#endif - -#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007)) - #error "BSC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003)) - #error "APBC0_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083)) - #error "APBC1_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083)) - #error "APBC2_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003)) - #error "SWC_PSR: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001)) - #error "TTC_PSR: Invalid values of reserved bits!" -#endif - -/******************************************************************************/ -/* Define clocks with checking settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Calculate PLL K factor from settings - ******************************************************************************/ -#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL N factor from settings - ******************************************************************************/ -#define __PLLN (((PLL_CTL2_Val ) & 0x3F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL M factor from settings - ******************************************************************************/ -#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1) - -/** - ****************************************************************************** - ** \brief Calculate PLL output frequency from settings - ******************************************************************************/ -#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) - -/******************************************************************************/ -/* Determine core clock frequency according to settings */ -/******************************************************************************/ - -/** - ****************************************************************************** - ** \brief Define Master Clock from settings - ******************************************************************************/ -#if (((SCM_CTL_Val >> 5) & 0x07) == 0) - #define __MASTERCLK (__CLKHC) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 1) - #define __MASTERCLK (__CLKMO) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 2) - #define __MASTERCLK (__PLLCLK) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 4) - #define __MASTERCLK (__CLKLC) -#elif (((SCM_CTL_Val >> 5) & 0x07) == 5) - #define __MASTERCLK (__CLKSO) -#else - #define __MASTERCLK (0UL) -#endif - -/** - ****************************************************************************** - ** \brief Define System Clock Frequency (Core Clock) from settings - ******************************************************************************/ -#if ((BSC_PSR_Val & 0x07) == 0) - #define __HCLK (__MASTERCLK / 1) -#elif ((BSC_PSR_Val & 0x07) == 1) - #define __HCLK (__MASTERCLK / 2) -#elif ((BSC_PSR_Val & 0x07) == 2) - #define __HCLK (__MASTERCLK / 3) -#elif ((BSC_PSR_Val & 0x07) == 3) - #define __HCLK (__MASTERCLK / 4) -#elif ((BSC_PSR_Val & 0x07) == 4) - #define __HCLK (__MASTERCLK / 6) -#elif ((BSC_PSR_Val & 0x07) == 5) - #define __HCLK (__MASTERCLK / 8) -#elif ((BSC_PSR_Val & 0x07) == 6) - #define __HCLK (__MASTERCLK /16) -#else - #define __HCLK (0UL) -#endif - -/******************************************************************************/ -/* HCLK range check */ -/******************************************************************************/ -#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0) - #error "Main Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0) - #error "Sub Oscillator Clock (CLKMO) out of range!" -#endif - -#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0) - #error "PLL input frequency out of range!" -#endif - -#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0) - #error "PLL oscillation frequency out of range!" -#endif - -#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0) - #error "System Clock (HCLK) out of range!" -#endif - -/******************************************************************************/ -/* Global function prototypes ('extern', definition in C source) */ -/******************************************************************************/ - -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) - -extern void SystemInit (void); // Initialize the system - -extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_MB9BF61X_H */ diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h b/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7a59b5923e..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,93 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoefQ31[6144]; -extern const q15_t twiddleCoefQ15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h b/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 8d7fac0f04..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,85 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { - 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { - 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { - 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { - 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { - 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { - 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { - 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { - 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH - }; - - const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { - 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH - }; - -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/arm_math.h b/bsp/mb9bf618s/CMSIS/Include/arm_math.h deleted file mode 100644 index 65304c127d..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7306 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2013 ARM Limited. All rights reserved. -* -* $Date: 17. January 2013 -* $Revision: V1.4.1 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * Copyright Notice - * - * Copyright (C) 2010-2013 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -#if defined ( __CC_ARM ) //Keil -//SMMLAR - #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR - #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm0.h b/bsp/mb9bf618s/CMSIS/Include/core_cm0.h deleted file mode 100644 index ab31de0ee8..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,682 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h b/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 5cea74e9af..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,793 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm3.h b/bsp/mb9bf618s/CMSIS/Include/core_cm3.h deleted file mode 100644 index 122c9aa4a8..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1627 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm4.h b/bsp/mb9bf618s/CMSIS/Include/core_cm4.h deleted file mode 100644 index d65016c714..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1772 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h b/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index 83db95b5f1..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h b/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 0a18fafc30..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h b/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index d213f0eed7..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/mb9bf618s/CMSIS/Include/core_sc000.h b/bsp/mb9bf618s/CMSIS/Include/core_sc000.h deleted file mode 100644 index 1a2a0f2e30..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,813 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (0) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/Include/core_sc300.h b/bsp/mb9bf618s/CMSIS/Include/core_sc300.h deleted file mode 100644 index cc34d6fc0e..0000000000 --- a/bsp/mb9bf618s/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1598 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/mb9bf618s/CMSIS/README.txt b/bsp/mb9bf618s/CMSIS/README.txt deleted file mode 100644 index 23717194f4..0000000000 --- a/bsp/mb9bf618s/CMSIS/README.txt +++ /dev/null @@ -1,37 +0,0 @@ -* ------------------------------------------------------------------- -* Copyright (C) 2011-2013 ARM Limited. All rights reserved. -* -* Date: 18 March 2013 -* Revision: V3.20 -* -* Project: Cortex Microcontroller Software Interface Standard (CMSIS) -* Title: Release Note for CMSIS -* -* ------------------------------------------------------------------- - - -NOTE - Open the index.html file to access CMSIS documentation - - -The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all -Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects -and reduces time-to-market for new embedded applications. - -CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). -Any user of the software package is bound to the terms and conditions of the end user license agreement. - - -You will find the following sub-directories: - -Documentation - Contains CMSIS documentation. - -DSP_Lib - MDK project files, Examples and source files etc.. to build the - CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. - -Include - CMSIS Core Support and CMSIS DSP Include Files. - -Lib - CMSIS DSP Libraries. - -RTOS - CMSIS RTOS API template header file. - -SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/bsp/mb9bf618s/CMSIS/SConscript b/bsp/mb9bf618s/CMSIS/SConscript deleted file mode 100644 index 64f6f21408..0000000000 --- a/bsp/mb9bf618s/CMSIS/SConscript +++ /dev/null @@ -1,21 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c') - -CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/'] - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c'] -elif rtconfig.CROSS_TOOL == 'keil': - src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S'] - -CPPDEFINES = [rtconfig.FM3_TYPE] -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/mb9bf618s/SConscript b/bsp/mb9bf618s/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/mb9bf618s/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/mb9bf618s/SConstruct b/bsp/mb9bf618s/SConstruct deleted file mode 100644 index 97f374e663..0000000000 --- a/bsp/mb9bf618s/SConstruct +++ /dev/null @@ -1,35 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/mb9bf618s/applications/SConscript b/bsp/mb9bf618s/applications/SConscript deleted file mode 100644 index 01eb940dfb..0000000000 --- a/bsp/mb9bf618s/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf618s/applications/application.c b/bsp/mb9bf618s/applications/application.c deleted file mode 100644 index 737034fff6..0000000000 --- a/bsp/mb9bf618s/applications/application.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-05-24 Bernard the first version - */ - -/** - * @addtogroup FM3 - */ -/*@{*/ - -#include -#include "board.h" - -void rt_init_thread_entry(void *parameter) -{ -#ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); -#endif - -#ifdef RT_USING_FINSH - (RT_CONSOLE_DEVICE_NAME); -#endif /* RT_USING_FINSH */ - - /**< init led device */ - { - extern void rt_led_hw_init(void); - rt_led_hw_init(); - } - -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, 8, 20); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf618s/applications/startup.c b/bsp/mb9bf618s/applications/startup.c deleted file mode 100644 index 22d38bcf95..0000000000 --- a/bsp/mb9bf618s/applications/startup.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP -#ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); -#elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); -#else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); -#endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init application */ - rt_application_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf618s/drivers/SConscript b/bsp/mb9bf618s/drivers/SConscript deleted file mode 100644 index 5bbef48785..0000000000 --- a/bsp/mb9bf618s/drivers/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/mb9bf618s/drivers/board.c b/bsp/mb9bf618s/drivers/board.c deleted file mode 100644 index 8490e7a060..0000000000 --- a/bsp/mb9bf618s/drivers/board.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" - -#include "serial.h" - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This fucntion returns milliseconds since system passed - */ -rt_uint32_t rt_hw_tick_get_millisecond(void) -{ - rt_tick_t tick; - rt_uint32_t value; - -#define TICK_MS (1000/RT_TICK_PER_SECOND) - - tick = rt_tick_get(); - value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD; - - return value; -} - -/** - * This fucntion returns microseconds since system passed - */ -rt_uint32_t rt_hw_tick_get_microsecond(void) -{ - rt_tick_t tick; - rt_uint32_t value; - -#define TICK_US (1000000/RT_TICK_PER_SECOND) - - tick = rt_tick_get(); - value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; - - return value; -} - -/** -* This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init(void) -{ - /* disable all analog input. */ - FM3_GPIO->ADE = 0; - - /* init systick */ - SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -} - -/*@}*/ diff --git a/bsp/mb9bf618s/drivers/board.h b/bsp/mb9bf618s/drivers/board.h deleted file mode 100644 index c082b0b54c..0000000000 --- a/bsp/mb9bf618s/drivers/board.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#if defined MB9B610S -# include -#elif defined MB9B610T -# include -#else -# warning "you must define CPU type. e.g: MB9B610S or MB9B610T" -# warning "define MB9B610S default" -# define MB9B610S /* default: MB9B610S */ -# include -#endif - -#include "serial.h" - -//Internal SRAM memory size[Kbytes] <8-64> -//product MB9BFx16S/T MB9BFx17S/T MB9BFx18S/T -//FLASH : 512 768 1024 -//SRAM0 : 32 48 64 -//SRAM1 : 32 48 64 -#define FM3_SRAM_SIZE 128 -#define FM3_SRAM_END (0x1FFF0000 + FM3_SRAM_SIZE * 1024) - -/* RT_USING_UART */ -#define RT_USING_UART0 -//#define RT_USING_UART2 -//#define RT_USING_UART4 -#define RT_UART_RX_BUFFER_SIZE 64 - -void rt_hw_board_init(void); -rt_uint32_t rt_hw_tick_get_millisecond(void); -rt_uint32_t rt_hw_tick_get_microsecond(void); - -#endif diff --git a/bsp/mb9bf618s/drivers/led.c b/bsp/mb9bf618s/drivers/led.c deleted file mode 100644 index bfad9947e7..0000000000 --- a/bsp/mb9bf618s/drivers/led.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ - -#include -#include "board.h" - -#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */ - -#define LED_NUM 4 -struct fm3_gpio_ctrl -{ - uint32_t led_num; - volatile uint32_t * PDOR; - volatile uint32_t * PDIR; -}; - -struct fm3_led -{ - /* inherit from rt_device */ - struct rt_device parent; - - struct fm3_gpio_ctrl fm3_gpio_ctrl[LED_NUM]; -}; - -static struct fm3_led fm3_led; - -static rt_err_t rt_led_init (rt_device_t dev) -{ - uint32_t i; - - /* led0 : P54 */ - FM3_GPIO->PFR5 &= ~((1<<7) | (1<<6) | (1<<5) |(1<<4)); /* set P54 fuction is GPIO. */ - FM3_GPIO->DDR5 |= (1<<7) | (1<<6) | (1<<5) |(1<<4); /* set P54 output. */ - - /* LED0 */ - i = 0; - fm3_led.fm3_gpio_ctrl[i].led_num = 4; - fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; - fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; - - /* LED1 */ - i++; - fm3_led.fm3_gpio_ctrl[i].led_num = 5; - fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; - fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; - - /* LED2 */ - i++; - fm3_led.fm3_gpio_ctrl[i].led_num = 6; - fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; - fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; - - /* LED3 */ - i++; - fm3_led.fm3_gpio_ctrl[i].led_num = 7; - fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5; - fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5; - - return RT_EOK; -} - -static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_led_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_ubase_t index = 0; - rt_ubase_t nr = size; - rt_uint8_t * value = buffer; - - RT_ASSERT(dev == &fm3_led.parent); - RT_ASSERT((pos+size) <= LED_NUM ); - - for(index=0; index -void led(rt_uint32_t led, rt_uint32_t value) -{ - rt_uint8_t led_value = value; - rt_led_write(&fm3_led.parent, led, &led_value, 1); -} -FINSH_FUNCTION_EXPORT(led, e.g:led(0,100).) -#endif diff --git a/bsp/mb9bf618s/drivers/serial.c b/bsp/mb9bf618s/drivers/serial.c deleted file mode 100644 index 79279e79e5..0000000000 --- a/bsp/mb9bf618s/drivers/serial.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#include - -#include "serial.h" - -/** - * @addtogroup FM3 MB9B610 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable interrupt */ - UART_ENABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - UART_DISABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->SSR & SSR_RDRF) - { - *ptr = uart->uart_device->RDR & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, - const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = '\r'; - } - - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = (*ptr & 0x1FF); - - ++ptr; - --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, - rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->SSR & SSR_RDRF) - { - rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -#ifdef RT_USING_UART0 -/* UART0 device driver structure */ -#define UART0 FM3_MFS0_UART -struct serial_int_rx uart0_int_rx; -struct serial_device uart0 = -{ - UART0, - MFS0RX_IRQn, - MFS0TX_IRQn, - &uart0_int_rx, - RT_NULL -}; -struct rt_device uart0_device; - -void MFS0RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&uart0_device); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /**< #ifdef RT_USING_UART0 */ - -#ifdef RT_USING_UART2 -/* UART2 device driver structure */ -#define UART2 FM3_MFS2_UART -struct serial_int_rx uart2_int_rx; -struct serial_device uart2 = -{ - UART2, - MFS2RX_IRQn, - MFS2TX_IRQn, - &uart2_int_rx, - RT_NULL -}; -struct rt_device uart2_device; - -void MFS2RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&uart2_device); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /**< #ifdef RT_USING_UART2 */ - -#ifdef RT_USING_UART4 -/* UART4 device driver structure */ -#define UART4 FM3_MFS4_UART -struct serial_int_rx uart4_int_rx; -struct serial_device uart4 = -{ - (FM3_MFS03_UART_TypeDef*)UART4, - MFS4RX_IRQn, - MFS4TX_IRQn, - &uart4_int_rx, - RT_NULL -}; -struct rt_device uart4_device; - -void MFS4RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&uart4_device); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /**< #ifdef RT_USING_UART4 */ - -void rt_hw_serial_init(void) -{ - uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); - -#ifdef RT_USING_UART0 - /* initialize UART0 */ - /* Set Uart Ch0 Port, SIN0_0:P21, SOT0_0:P22 */ - FM3_GPIO->ADE &= ~(1UL<<31); /* disable P22 AN31 function */ - FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | (1<<1) | (1<<2); - FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 & ~(3<<4 | 3<<6) | (1<<4) | (1<<6); - - uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; - uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ - uart0.uart_device->ESCR = ESCR_DATABITS_8; - uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - /* register UART0 device */ - rt_hw_serial_register(&uart0_device, - "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); -#endif /**< #ifdef RT_USING_UART0 */ - -#ifdef RT_USING_UART2 - /* initialize UART2 */ - /* Set Uart Ch2 Port, SIN2_2:P17, SOT2_2:P18 */ - FM3_GPIO->ADE &= ~(1<<7 | 1<<8); /* disable P17 AN07 and P18 AN08 function */ - FM3_GPIO->PFR1 = FM3_GPIO->PFR1 | (1<<7) | (1<<8) ; - FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | (3<<16) | (3<<18) ; - - uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;; - uart2.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ - uart2.uart_device->ESCR = ESCR_DATABITS_8; - uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - /* register UART2 device */ - rt_hw_serial_register(&uart2_device, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); -#endif /**< #ifdef RT_USING_UART2 */ - -#ifdef RT_USING_UART4 - /* initialize UART4 */ - /* Set Uart Ch4 Port, SIN4_2:P05, SOT4_2:P06 */ - FM3_GPIO->PFR0 = FM3_GPIO->PFR0 | (1<<5) | (1<<6); - FM3_GPIO->EPFR08 = FM3_GPIO->EPFR08 | (3<<4) | (3<<6); - - uart4.uart_device->SMR = SMR_MD_UART | SMR_SOE;; - uart4.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ - uart4.uart_device->ESCR = ESCR_DATABITS_8; - uart4.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - /* register UART4 device */ - rt_hw_serial_register(&uart4_device, - "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart4); -#endif /**< #ifdef RT_USING_UART4 */ -} - -/*@}*/ diff --git a/bsp/mb9bf618s/drivers/serial.h b/bsp/mb9bf618s/drivers/serial.h deleted file mode 100644 index 388f9eef86..0000000000 --- a/bsp/mb9bf618s/drivers/serial.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#include "board.h" - -#define SMR_SOE 0x01U -#define SMR_BDS 0x04U -#define SMR_SBL 0x08U -#define SMR_WUCR 0x10U -#define SMR_MD_UART 0x00U -#define SMR_MD_UART_MP 0x20U -#define SMR_MD_SIO 0x40U -#define SMR_MD_LIN 0x60U -#define SMR_MD_I2C 0x80U - -#define SCR_TXE 0x01U -#define SCR_RXE 0x02U -#define SCR_TBIE 0x04U -#define SCR_TIE 0x08U -#define SCR_RIE 0x10U -#define SCR_UPGL 0x80U - -#define SSR_TBI 0x01U -#define SSR_TDRE 0x02U -#define SSR_RDRF 0x04U -#define SSR_ORE 0x08U -#define SSR_FRE 0x10U -#define SSR_PE 0x20U -#define SSR_REC 0x80U - -#define ESCR_P 0x08U -#define ESCR_PEN 0x10U -#define ESCR_INV 0x20U -#define ESCR_ESBL 0x40U -#define ESCR_FLWEN 0x80U -#define ESCR_DATABITS_8 0x00U -#define ESCR_DATABITS_5 0x01U -#define ESCR_DATABITS_6 0x02U -#define ESCR_DATABITS_7 0x03U -#define ESCR_DATABITS_9 0x04U - -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -/* - * Enable/DISABLE Interrupt Controller - */ -/* deviation from MISRA-C:2004 Rule 19.7 */ -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -struct serial_device -{ - FM3_MFS03_UART_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq, tx_irq; - - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -void rt_hw_serial_isr(rt_device_t device); -void rt_hw_serial_init(void); - -#endif diff --git a/bsp/mb9bf618s/project.ewp b/bsp/mb9bf618s/project.ewp deleted file mode 100644 index 25f7f69663..0000000000 --- a/bsp/mb9bf618s/project.ewp +++ /dev/null @@ -1,2012 +0,0 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 15 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 15 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Applications - - $PROJ_DIR$\applications\application.c - - - $PROJ_DIR$\applications\startup.c - - - - CMSIS - - $PROJ_DIR$\CMSIS\DeviceSupport\fujitsu\mb9bf61x\system_mb9bf61x.c - - - $PROJ_DIR$\CMSIS\DeviceSupport\fujitsu\mb9bf61x\startup\iar\startup_mb9bf61x.S - - - - Compiler - - $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\time.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c - - - - CPU - - $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c - - - $PROJ_DIR$\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S - - - - Drivers - - $PROJ_DIR$\drivers\led.c - - - $PROJ_DIR$\drivers\serial.c - - - $PROJ_DIR$\drivers\board.c - - - - Finsh - - $PROJ_DIR$\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\components\finsh\msh.c - - - - Kernel - - $PROJ_DIR$\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\src\thread.c - - - $PROJ_DIR$\..\..\src\clock.c - - - $PROJ_DIR$\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\src\timer.c - - - $PROJ_DIR$\..\..\src\mem.c - - - $PROJ_DIR$\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\src\device.c - - - $PROJ_DIR$\..\..\src\object.c - - - $PROJ_DIR$\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\src\idle.c - - - $PROJ_DIR$\..\..\src\components.c - - - $PROJ_DIR$\..\..\src\irq.c - - - - POSIX - - - utestcases - - diff --git a/bsp/mb9bf618s/project.eww b/bsp/mb9bf618s/project.eww deleted file mode 100644 index c2cb02eb1e..0000000000 --- a/bsp/mb9bf618s/project.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/mb9bf618s/project.uvproj b/bsp/mb9bf618s/project.uvproj deleted file mode 100644 index c249d3fac1..0000000000 --- a/bsp/mb9bf618s/project.uvproj +++ /dev/null @@ -1,630 +0,0 @@ - - - 1.1 -
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- - - - 1 - 0 - 0 - 1 - 1 - 4099 - - 0 - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x1fff0000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - MB9B610S, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND - - applications;.;CMSIS\Include;CMSIS\DeviceSupport\fujitsu\mb9bf61x;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc;..\..\examples\utest\testcases\kernel - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - rtthread-fm3.sct - - - - - - - - - - - Applications - - - startup.c - 1 - applications\startup.c - - - - - application.c - 1 - applications\application.c - - - - - CMSIS - - - system_mb9bf61x.c - 1 - CMSIS\DeviceSupport\fujitsu\mb9bf61x\system_mb9bf61x.c - - - - - startup_mb9bf61x.S - 2 - CMSIS\DeviceSupport\fujitsu\mb9bf61x\startup\arm\startup_mb9bf61x.S - - - - - Compiler - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - stdlib.c - 1 - ..\..\components\libc\compilers\common\stdlib.c - - - - - time.c - 1 - ..\..\components\libc\compilers\common\time.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - Drivers - - - serial.c - 1 - drivers\serial.c - - - - - board.c - 1 - drivers\board.c - - - - - led.c - 1 - drivers\led.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - Kernel - - - device.c - 1 - ..\..\src\device.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - clock.c - 1 - ..\..\src\clock.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - - - diff --git a/bsp/mb9bf618s/rtconfig.h b/bsp/mb9bf618s/rtconfig.h deleted file mode 100644 index d887692233..0000000000 --- a/bsp/mb9bf618s/rtconfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 - -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_DEBUG_COLOR -#define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ -#define RT_USING_HOOK - -/* SECTION: IPC */ -/* Using Semaphore */ -#define RT_USING_SEMAPHORE - -/* Using Mutex */ -#define RT_USING_MUTEX - -/* Using Event */ -#define RT_USING_EVENT - -/* Using MailBox */ -#define RT_USING_MAILBOX - -/* Using Message Queue */ -#define RT_USING_MESSAGEQUEUE - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ -#define RT_USING_HEAP - -/* Using Small MM */ -#define RT_USING_SMALL_MEM - -// -#define RT_USING_COMPONENTS_INIT - -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE - -/* SECTION: Console options */ -/* #define RT_TINY_SIZE */ -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart0" - -/* SECTION: finsh, a C-Express shell */ -/* Using FinSH as Shell*/ -#define RT_USING_FINSH -/* Using symbol table */ -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_STACK_SIZE 1024 - -#endif diff --git a/bsp/mb9bf618s/rtconfig.py b/bsp/mb9bf618s/rtconfig.py deleted file mode 100644 index 474ff3dd57..0000000000 --- a/bsp/mb9bf618s/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -#device options -# FM3_TYPE = -# 'MB9B610S','MB9B610T', -FM3_TYPE = 'MB9B610S' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'F:\Program Files\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI_2013.05.23\bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'E:/Keil' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-fm3.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread-fm3.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - CFLAGS = '' - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"' - - LFLAGS = ' --config rtthread-fm3.icf' - LFLAGS += ' --semihosting' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf618s/rtthread-fm3.icf b/bsp/mb9bf618s/rtthread-fm3.icf deleted file mode 100644 index 7876fa0c81..0000000000 --- a/bsp/mb9bf618s/rtthread-fm3.icf +++ /dev/null @@ -1,34 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x0; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0; -define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly, block RTT_INIT_FUNC }; -place in RAM_region { readwrite, block CSTACK, last block HEAP }; diff --git a/bsp/mb9bf618s/rtthread-fm3.ld b/bsp/mb9bf618s/rtthread-fm3.ld deleted file mode 100644 index 6696a0b1c2..0000000000 --- a/bsp/mb9bf618s/rtthread-fm3.ld +++ /dev/null @@ -1,143 +0,0 @@ -/* - * linker script for Fujitsu with GNU ld - * aozima 2013-07-13 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 1M /* 1MB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram, 64KB SRAM0 + 64KB SRAM1 */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x400; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _isr_vector = .; /* define isr_vector start address */ - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/mb9bf618s/rtthread-fm3.sct b/bsp/mb9bf618s/rtthread-fm3.sct deleted file mode 100644 index 405f2ebb65..0000000000 --- a/bsp/mb9bf618s/rtthread-fm3.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00100000 { ; load region size_region - ER_IROM1 0x00000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x1FFF0000 0x00020000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/mb9bf618s/template.ewp b/bsp/mb9bf618s/template.ewp deleted file mode 100644 index 4883fc16e7..0000000000 --- a/bsp/mb9bf618s/template.ewp +++ /dev/null @@ -1,1839 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 15 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 15 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/mb9bf618s/template.uvproj b/bsp/mb9bf618s/template.uvproj deleted file mode 100644 index ec72dd0f7f..0000000000 --- a/bsp/mb9bf618s/template.uvproj +++ /dev/null @@ -1,394 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rtthread - 0x4 - ARM-ADS - - - MB9BF618S - Fujitsu Semiconductors - IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - - "Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000) - 6149 - mb9bf618s.h - - - - - - - - - - SFD\Fujitsu\MB9BF610\MB9BF618S.SFR - 0 - - - - Fujitsu\MB9BF610\ - Fujitsu\MB9BF610\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-fm3 - 1 - 0 - 0 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 0 - - 0 - 7 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - 0 - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 1 - 0x0 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x1fff0000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - rtthread-fm3.sct - - - - - - - - - - - - -- cgit v1.3.1